[llvm] [ISel] Introduce `llvm.pext` and `llvm.pdep` intrinsics (PR #200570)

[Jan Schultke via llvm-commits]

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@@ -1763,6 +1771,30 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CLMUL(SDNode *N) {
                      DAG.getShiftAmountConstant(ShAmt, VT, DL));
 }
 
+SDValue DAGTypeLegalizer::PromoteIntRes_PEXT(SDNode *N) {
+  SDLoc DL(N);
+  EVT VT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+  if (!TLI.isOperationLegalOrCustomOrPromote(ISD::PEXT, VT)) {
+    if (SDValue Res = TLI.expandPEXT(N, DAG))
+      return DAG.getNode(ISD::ANY_EXTEND, DL, VT, Res);
+  }
+  SDValue X = ZExtPromotedInteger(N->getOperand(0));
+  SDValue Y = ZExtPromotedInteger(N->getOperand(1));
+  return DAG.getNode(ISD::PEXT, DL, VT, X, Y);
+}
+
+SDValue DAGTypeLegalizer::PromoteIntRes_PDEP(SDNode *N) {
+  SDLoc DL(N);
+  EVT VT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+  if (!TLI.isOperationLegalOrCustomOrPromote(ISD::PDEP, VT)) {
+    if (SDValue Res = TLI.expandPDEP(N, DAG))
+      return DAG.getNode(ISD::ANY_EXTEND, DL, VT, Res);
+  }
+  SDValue X = ZExtPromotedInteger(N->getOperand(0));
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eisenwave wrote:

I've changed it so only the mask is getting zero-extended. There is an implicit AND operation induced by the mask anyway, so the other operand doesn't need to be zero-extended.

I don't see how you can avoid zero-extending the mask though. If you add random garbage bits to both the mask and the left operand, then what stops `PDEP` from depositing random garbage upper bits?

https://github.com/llvm/llvm-project/pull/200570