[llvm] [AMDGPU] using divergent/uniform information in ISel of zext (PR #174539)

[Zeng Wu via llvm-commits]

zwu-2025 wrote:

> There are still many test failures.

there are 16 failures, some of them looks normal but others seems needs investigation. Except the pattern pointed by @arsenm 's comment, the other one is
```
bb.1:
  ; Use the alloca outside of the defining block.
  store i32 0, ptr addrspace(5) %alloca
  store i32 1, ptr addrspace(5) %gep1
  %gep2 = getelementptr [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 %in
  %load = load i32, ptr addrspace(5) %gep2
  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %add = add i32 %load, %tid
  store i32 %add, ptr addrspace(1) %out
  br label %bb.2
```
in test `func_non_entry_block_static_alloca_align4 at non-entry-alloca.ll`.
The difference is out-of-expectation.

https://github.com/llvm/llvm-project/pull/174539