[llvm] [AMDGPU] Use shorter form for i16 operands (PR #198005)

[Stanislav Mekhanoshin via llvm-commits]

rampitec wrote:

Then it is not just asm bug. If you imagine this instruction has 0x3f800000 immediate encoder will now use 1.0 inline. Which will of course screw low 16 bits. That is unlikely one can write a source like this because the literal is out of range, but it is not difficult to produce llvm IR like this.

https://github.com/llvm/llvm-project/pull/198005