[llvm] [AMDGPU] using divergent/uniform information in ISel of zext (PR #174539)
Zeng Wu via llvm-commits
llvm-commits at lists.llvm.org
Fri May 29 08:52:41 PDT 2026
https://github.com/zwu-2025 updated https://github.com/llvm/llvm-project/pull/174539
>From b20ed163ed103c6d02036bd64af37ab5c610d7c2 Mon Sep 17 00:00:00 2001
From: zwu-2025 <Zeng.Wu2 at amd.com>
Date: Mon, 23 Mar 2026 17:49:18 +0000
Subject: [PATCH 01/29] changes decision order of UseRC and use
common-sub-regclass
---
.../lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 21 +++++++++++++------
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 322766dee5aa9..20c02317019c6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -24,9 +24,11 @@
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/PseudoProbe.h"
+#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetMachine.h"
using namespace llvm;
@@ -103,12 +105,7 @@ void InstrEmitter::EmitCopyFromReg(SDValue Op, bool IsClone, Register SrcReg,
bool MatchReg = true;
MVT VT = Op.getSimpleValueType();
-
- // FIXME: The Untyped check is a workaround for SystemZ i128 inline assembly
- // using i128, when it should probably be using v2i64.
- const TargetRegisterClass *UseRC =
- VT == MVT::Untyped ? nullptr : TLI->getRegClassFor(VT, Op->isDivergent());
-
+ const TargetRegisterClass *UseRC = nullptr;
for (SDNode *User : Op->users()) {
bool Match = true;
if (User->getOpcode() == ISD::CopyToReg && User->getOperand(2) == Op) {
@@ -132,6 +129,7 @@ void InstrEmitter::EmitCopyFromReg(SDValue Op, bool IsClone, Register SrcReg,
RC = TRI->getAllocatableClass(
TII->getRegClass(II, i + II.getNumDefs()));
}
+
if (!UseRC)
UseRC = RC;
else if (RC) {
@@ -150,6 +148,17 @@ void InstrEmitter::EmitCopyFromReg(SDValue Op, bool IsClone, Register SrcReg,
break;
}
+ // FIXME: The Untyped check is a workaround for SystemZ i128 inline assembly
+ // using i128, when it should probably be using v2i64.
+ const TargetRegisterClass *RegClassForVT =
+ VT == MVT::Untyped ? nullptr : TLI->getRegClassFor(VT, Op->isDivergent());
+
+ if (UseRC == nullptr || !UseRC->isAllocatable()) {
+ UseRC = RegClassForVT;
+ } else if (auto CommonSubClass = TRI->getCommonSubClass(UseRC, RegClassForVT)) {
+ UseRC = CommonSubClass;
+ }
+
const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
>From ce4a770ba8f8b677a497bae30bb97d4b48abf087 Mon Sep 17 00:00:00 2001
From: zwu-2025 <Zeng.Wu2 at amd.com>
Date: Mon, 23 Mar 2026 21:58:21 +0000
Subject: [PATCH 02/29] Select S_AND for ZEXT Only if directly from ICMP and
UNIFORM
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 61 +++++++++++++++++--
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h | 1 +
.../llvm.amdgcn.uniform_ext_i1_to_i32.ll | 47 ++++++++++++++
3 files changed, 105 insertions(+), 4 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.uniform_ext_i1_to_i32.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index cc2058a5a1d4a..d630cf46b7dbe 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -325,10 +325,57 @@ bool AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(SDNode *N) const {
return false;
}
-void AMDGPUDAGToDAGISel::PreprocessISelDAG() {
- if (!Subtarget->d16PreservesUnusedBits())
- return;
+bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
+ // For the DAG:
+ // t134: i1 = setcc t52, Constant:i32<0>, setne:ch
+ // t133: i32 = zero_extend t134
+ // After DAG selections, it is:
+ // t134: i1 = S_CMP_LG_U32 t52, t19
+ // t133: i32,i1 = S_AND_B32 t134, TargetConstant:i32<1>
+ //
+ // And the listed MIR are:
+ // S_CMP_LG_U32 killed %25:sreg_32, %26:sreg_32, implicit-def $scc
+ // %27:sreg_32 = COPY $scc
+ // %28:sreg_32 = S_AND_B32 killed %27:sreg_32, 1, implicit-def dead $scc
+ //
+ // After SI-Fix-SGPR-Copies, if wave size is 64, the fixSCCCopy will change it to
+ // S_CMP_LG_U32 killed %25:sreg_32, %26:sreg_32, implicit-def $scc
+ // %79:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit $scc
+ // %27:sreg_32 = COPY %79:sreg_64_xexec; illegal vgpr to sgpr copy
+ //
+ // This preprocess changes DAG
+ // t133: i32 = zero_extend t134 into --> S_CSELEECT_B32 -1 0
+ // if it is valid.
+ if (N->isDivergent()) return false;
+
+ // If to i64, it is probably used for lane mask, then we don't do the changes here.
+ if (N->getValueType(0) != MVT::i32) return false;
+
+ auto CondNode = N->getOperand(0);
+ if (CondNode->getOpcode() == ISD::FREEZE) {
+ CondNode = CondNode->getOperand(0);
+ }
+
+ if (CondNode->getOpcode() != ISD::SETCC)
+ return false;
+
+ if (CondNode->getOperand(0).getValueType() != MVT::i32 || CondNode->getOperand(1).getValueType() != MVT::i32)
+ return false;
+
+ SDLoc DL(N);
+ SDValue TrueValue = CurDAG->getAllOnesConstant(DL, MVT::i32, true);
+ SDValue FalseValue = CurDAG->getTargetConstant(0, DL, MVT::i32);
+ SDValue Chain = CurDAG->getEntryNode(); // Basic chain to anchor the copy
+ SDValue CopyToSCC = CurDAG->getCopyToReg(Chain, DL, AMDGPU::SCC, CondNode, SDValue());
+ SmallVector<SDValue, 3> Ops = {TrueValue, FalseValue, CopyToSCC.getValue(1)};
+ MachineSDNode *CSelectNode = CurDAG->getMachineNode(AMDGPU::S_CSELECT_B32, DL, CurDAG->getVTList(MVT::i32), Ops);
+ CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), SDValue(CSelectNode, 0));
+
+ return true;
+}
+
+void AMDGPUDAGToDAGISel::PreprocessISelDAG() {
SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
bool MadeChange = false;
@@ -340,8 +387,14 @@ void AMDGPUDAGToDAGISel::PreprocessISelDAG() {
switch (N->getOpcode()) {
case ISD::BUILD_VECTOR:
// TODO: Match load d16 from shl (extload:i16), 16
- MadeChange |= matchLoadD16FromBuildVector(N);
+ if (Subtarget->d16PreservesUnusedBits())
+ MadeChange |= matchLoadD16FromBuildVector(N);
+
break;
+ case ISD::ZERO_EXTEND:
+ MadeChange |= preprocessZeroExtend(N);
+ break;
+
default:
break;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
index ffeb6dfdb3f90..9cc34cc769cf0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
@@ -67,6 +67,7 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel {
bool runOnMachineFunction(MachineFunction &MF) override;
bool matchLoadD16FromBuildVector(SDNode *N) const;
+ bool preprocessZeroExtend(SDNode *N) const;
void PreprocessISelDAG() override;
void Select(SDNode *N) override;
void PostprocessISelDAG() override;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.uniform_ext_i1_to_i32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.uniform_ext_i1_to_i32.ll
new file mode 100644
index 0000000000000..f5cc63694be9a
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.uniform_ext_i1_to_i32.ll
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck --check-prefix=GFX950 %s
+
+declare i32 @llvm.amdgcn.workitem.id.x() #0
+
+define amdgpu_kernel void @zext_i1_to_i64_uniform(ptr addrspace(1) %out, i1 %pred, i32 %a, i32 %b) #0 {
+entry:
+ ; GFX950-LABEL: zext_i1_to_i64_uniform
+ ; GFX950: s_load_dwordx2 s[0:1], s[4:5], 0x30
+ ; GFX950-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+ ; GFX950-NEXT: s_mov_b32 s4, 0
+ ; GFX950-NEXT: v_mov_b32_e32 v2, 0
+ ; GFX950-NEXT: v_mov_b32_e32 v1, s4
+ ; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+ ; GFX950-NEXT: s_cmp_eq_u32 s0, s1
+ ; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
+ ; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
+ ; GFX950-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
+ ; GFX950-NEXT: s_endpgm
+
+ %cmp = icmp eq i32 %a, %b
+ %tmp2 = zext i1 %cmp to i64
+ store i64 %tmp2, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @zext_i1_to_i32_uniform(ptr addrspace(1) %out, i1 %pred, i32 %a, i32 %b) #0 {
+entry:
+ ; GFX950-LABEL: zext_i1_to_i32_uniform
+ ; GFX950: s_load_dwordx2 s[0:1], s[4:5], 0x30
+ ; GFX950-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+ ; GFX950-NEXT: v_mov_b32_e32 v0, 0
+ ; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+ ; GFX950-NEXT: s_cmp_eq_u32 s0, s1
+ ; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
+ ; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
+ ; GFX950-NEXT: s_cselect_b32 s0, -1, 0
+ ; GFX950-NEXT: v_mov_b32_e32 v1, s0
+ ; GFX950-NEXT: global_store_dword v0, v1, s[2:3]
+ ; GFX950-NEXT: s_endpgm
+ %cmp = icmp eq i32 %a, %b
+ %tmp2 = zext i1 %cmp to i32
+ store i32 %tmp2, ptr addrspace(1) %out
+ ret void
+}
+
+attributes #0 = { nounwind }
>From 5cf7ac1a475840ed11253ef222af48b3eadf7702 Mon Sep 17 00:00:00 2001
From: zwu-2025 <Zeng.Wu2 at amd.com>
Date: Sun, 19 Apr 2026 05:25:02 +0000
Subject: [PATCH 03/29] validate scc is not cross bb before and after
si-fix-sgpr-copies
---
llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 80 ++++++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
index 5994eeb54095b..066f11c932fe5 100644
--- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
@@ -159,6 +159,8 @@ class SIFixSGPRCopies {
MachineBasicBlock *BlockToInsertTo,
MachineBasicBlock::iterator PointToInsertTo,
const DebugLoc &DL);
+
+ void validateNoCrossBlockSCC(MachineFunction &MF);
};
class SIFixSGPRCopiesLegacy : public MachineFunctionPass {
@@ -623,6 +625,8 @@ bool SIFixSGPRCopies::run(MachineFunction &MF) {
if (MF.getProperties().hasSelected())
return false;
+ validateNoCrossBlockSCC(MF);
+
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
MRI = &MF.getRegInfo();
TRI = ST.getRegisterInfo();
@@ -781,8 +785,12 @@ bool SIFixSGPRCopies::run(MachineFunction &MF) {
}
lowerVGPR2SGPRCopies(MF);
+
+ validateNoCrossBlockSCC(MF);
// Postprocessing
fixSCCCopies(MF);
+ validateNoCrossBlockSCC(MF);
+
for (auto *MI : S2VCopies) {
// Check if it is still valid
if (MI->isCopy()) {
@@ -806,6 +814,8 @@ bool SIFixSGPRCopies::run(MachineFunction &MF) {
if (MF.getTarget().getOptLevel() > CodeGenOptLevel::None && EnableM0Merge)
hoistAndMergeSGPRInits(AMDGPU::M0, *MRI, TRI, *MDT, TII);
+ validateNoCrossBlockSCC(MF);
+
SiblingPenalty.clear();
V2SCopies.clear();
SCCCopies.clear();
@@ -1012,6 +1022,10 @@ void SIFixSGPRCopies::analyzeVGPRToSGPRCopy(MachineInstr* MI) {
AnalysisWorklist.push_back(U);
}
}
+
+ for (auto I : Info.SChain) {
+ LLVM_DEBUG(dbgs() << "Chain 12345:"; I->dump(););
+ }
V2SCopies[Info.ID] = std::move(Info);
}
@@ -1055,6 +1069,72 @@ bool SIFixSGPRCopies::needToBeConvertedToVALU(V2SCopyInfo *Info) {
return Info->NeedToBeConvertedToVALU;
}
+void SIFixSGPRCopies::validateNoCrossBlockSCC(MachineFunction &MF) {
+
+ for (const MachineBasicBlock &MBB : MF) {
+ // assert(!MBB.isLiveIn(AMDGPU::SCC) && "AMDGPU::SCC is live-in to a basic
+ // block! Cross-BB SCC liveness detected.");
+
+ bool SCCDefinedInCurrentBlock = false;
+
+ for (const MachineInstr &MI : MBB) {
+ bool ReadsSCC = false;
+ bool ModifiesSCC = false;
+
+ for (const MachineOperand &MO : MI.operands()) {
+ if (MO.isRegMask() && MO.clobbersPhysReg(AMDGPU::SCC)) {
+ ModifiesSCC = true;
+ continue;
+ }
+
+ if (!MO.isReg())
+ continue;
+
+ Register Reg = MO.getReg();
+ if (!Reg || !Reg.isPhysical())
+ continue;
+
+ unsigned BitSize = 0;
+ if (Reg.isPhysical()) {
+ const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
+ BitSize = TRI->getRegSizeInBits(*RC);
+ } else {
+ if (MRI->getType(Reg).isValid()) {
+ BitSize = MRI->getType(Reg).getSizeInBits();
+ } else {
+ const TargetRegisterClass *RC = MRI->getRegClass(Reg);
+ if (RC)
+ BitSize = TRI->getRegSizeInBits(*RC);
+ }
+ }
+
+ if (BitSize != 32)
+ continue;
+
+ if (TRI->regsOverlap(Reg, AMDGPU::SCC)) {
+ if (MO.readsReg())
+ ReadsSCC = true;
+ if (MO.isDef())
+ ModifiesSCC = true;
+ }
+ }
+
+ if (ReadsSCC) {
+ if (!SCCDefinedInCurrentBlock) {
+ errs() << "Violation in MBB: " << MBB.getName() << "\n";
+ errs() << "Instruction: " << MI << "\n";
+ llvm_unreachable(
+ "SCC is read before being defined in the same basic block!");
+ }
+ }
+
+ if (ModifiesSCC) {
+ SCCDefinedInCurrentBlock = true;
+ }
+ }
+ }
+}
+
void SIFixSGPRCopies::lowerVGPR2SGPRCopies(MachineFunction &MF) {
SmallVector<unsigned, 8> LoweringWorklist;
>From 1b0fc97a167201c1ecc9610c7c1667e2f97e0f0b Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Fri, 15 May 2026 18:18:46 +0000
Subject: [PATCH 04/29] comments
---
.../lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 9 +--
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 72 ++++++++-----------
2 files changed, 35 insertions(+), 46 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 20c02317019c6..17c1b048bd4d2 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -153,10 +153,11 @@ void InstrEmitter::EmitCopyFromReg(SDValue Op, bool IsClone, Register SrcReg,
const TargetRegisterClass *RegClassForVT =
VT == MVT::Untyped ? nullptr : TLI->getRegClassFor(VT, Op->isDivergent());
- if (UseRC == nullptr || !UseRC->isAllocatable()) {
- UseRC = RegClassForVT;
- } else if (auto CommonSubClass = TRI->getCommonSubClass(UseRC, RegClassForVT)) {
- UseRC = CommonSubClass;
+ if (!UseRC || !UseRC->isAllocatable()) {
+ UseRC = RegClassForVT;
+ } else if (const TargetRegisterClass *CommonSubClass =
+ TRI->getCommonSubClass(UseRC, RegClassForVT)) {
+ UseRC = CommonSubClass;
}
const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index d630cf46b7dbe..472dfae9405e3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -326,53 +326,41 @@ bool AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(SDNode *N) const {
}
bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
- // For the DAG:
- // t134: i1 = setcc t52, Constant:i32<0>, setne:ch
- // t133: i32 = zero_extend t134
- // After DAG selections, it is:
- // t134: i1 = S_CMP_LG_U32 t52, t19
- // t133: i32,i1 = S_AND_B32 t134, TargetConstant:i32<1>
- //
- // And the listed MIR are:
- // S_CMP_LG_U32 killed %25:sreg_32, %26:sreg_32, implicit-def $scc
- // %27:sreg_32 = COPY $scc
- // %28:sreg_32 = S_AND_B32 killed %27:sreg_32, 1, implicit-def dead $scc
- //
- // After SI-Fix-SGPR-Copies, if wave size is 64, the fixSCCCopy will change it to
- // S_CMP_LG_U32 killed %25:sreg_32, %26:sreg_32, implicit-def $scc
- // %79:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit $scc
- // %27:sreg_32 = COPY %79:sreg_64_xexec; illegal vgpr to sgpr copy
- //
- // This preprocess changes DAG
- // t133: i32 = zero_extend t134 into --> S_CSELEECT_B32 -1 0
- // if it is valid.
- if (N->isDivergent()) return false;
-
- // If to i64, it is probably used for lane mask, then we don't do the changes here.
- if (N->getValueType(0) != MVT::i32) return false;
-
- auto CondNode = N->getOperand(0);
- if (CondNode->getOpcode() == ISD::FREEZE) {
- CondNode = CondNode->getOperand(0);
- }
+ // If the extension of uniform i1 to i32 is not used as lanemask, we want to
+ // the result type is int32. This method mutates node `zero_extend i1 to i32`
+ // directly to S_CSELECT_B32. Instead of change the following
+ // SI-Fix-SGPR-Copies to support it, we make changes earlier bofore inst
+ // selection.
+ if (N->isDivergent())
+ return false;
- if (CondNode->getOpcode() != ISD::SETCC)
- return false;
+ // If to i64, it is probably used for lane mask, then we don't do the changes
+ // here.
+ if (N->getValueType(0) != MVT::i32)
+ return false;
- if (CondNode->getOperand(0).getValueType() != MVT::i32 || CondNode->getOperand(1).getValueType() != MVT::i32)
- return false;
+ SDValue CondNode = N->getOperand(0);
+ if (CondNode->getOpcode() != ISD::SETCC)
+ return false;
- SDLoc DL(N);
- SDValue TrueValue = CurDAG->getAllOnesConstant(DL, MVT::i32, true);
- SDValue FalseValue = CurDAG->getTargetConstant(0, DL, MVT::i32);
+ if (CondNode->getOperand(0).getValueType() != MVT::i32 ||
+ CondNode->getOperand(1).getValueType() != MVT::i32)
+ return false;
- SDValue Chain = CurDAG->getEntryNode(); // Basic chain to anchor the copy
- SDValue CopyToSCC = CurDAG->getCopyToReg(Chain, DL, AMDGPU::SCC, CondNode, SDValue());
- SmallVector<SDValue, 3> Ops = {TrueValue, FalseValue, CopyToSCC.getValue(1)};
- MachineSDNode *CSelectNode = CurDAG->getMachineNode(AMDGPU::S_CSELECT_B32, DL, CurDAG->getVTList(MVT::i32), Ops);
- CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), SDValue(CSelectNode, 0));
+ SDLoc DL(N);
+ SDValue TrueValue = CurDAG->getTargetConstant(1, DL, MVT::i32);
+ SDValue FalseValue = CurDAG->getTargetConstant(0, DL, MVT::i32);
+
+ SDValue Chain = CurDAG->getEntryNode(); // Basic chain to anchor the copy
+ SDValue CopyToSCC =
+ CurDAG->getCopyToReg(Chain, DL, AMDGPU::SCC, CondNode, SDValue());
+ SDValue Ops[4] = {TrueValue, FalseValue, CopyToSCC.getValue(1),
+ CopyToSCC.getValue(1)};
+ MachineSDNode *CSelectNode = CurDAG->getMachineNode(
+ AMDGPU::S_CSELECT_B32, DL, CurDAG->getVTList(MVT::i32), Ops);
+ CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), SDValue(CSelectNode, 0));
- return true;
+ return true;
}
void AMDGPUDAGToDAGISel::PreprocessISelDAG() {
>From def6ea135cf851d40586cf4d58c4847b95ea3f41 Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Fri, 15 May 2026 19:08:37 +0000
Subject: [PATCH 05/29] new basic lit-test
---
...amdgcn.uniform_ext_i1_to_i32.ll => uniform_ext_i1_to_i32.ll} | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
rename llvm/test/CodeGen/AMDGPU/{llvm.amdgcn.uniform_ext_i1_to_i32.ll => uniform_ext_i1_to_i32.ll} (94%)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.uniform_ext_i1_to_i32.ll b/llvm/test/CodeGen/AMDGPU/uniform_ext_i1_to_i32.ll
similarity index 94%
rename from llvm/test/CodeGen/AMDGPU/llvm.amdgcn.uniform_ext_i1_to_i32.ll
rename to llvm/test/CodeGen/AMDGPU/uniform_ext_i1_to_i32.ll
index f5cc63694be9a..97aaf9eb4b681 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.uniform_ext_i1_to_i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/uniform_ext_i1_to_i32.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck --check-prefix=GFX950 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck --check-prefix=GFX950 %s
declare i32 @llvm.amdgcn.workitem.id.x() #0
>From 646aebb184adb3c638b425951e6411dd3b2f9802 Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Fri, 15 May 2026 19:42:53 +0000
Subject: [PATCH 06/29] cleanup
---
llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 74 -------------------
.../CodeGen/AMDGPU/uniform_ext_i1_to_i32.ll | 37 ++++++++--
2 files changed, 32 insertions(+), 79 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
index 066f11c932fe5..603665611e2bf 100644
--- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
@@ -159,8 +159,6 @@ class SIFixSGPRCopies {
MachineBasicBlock *BlockToInsertTo,
MachineBasicBlock::iterator PointToInsertTo,
const DebugLoc &DL);
-
- void validateNoCrossBlockSCC(MachineFunction &MF);
};
class SIFixSGPRCopiesLegacy : public MachineFunctionPass {
@@ -625,8 +623,6 @@ bool SIFixSGPRCopies::run(MachineFunction &MF) {
if (MF.getProperties().hasSelected())
return false;
- validateNoCrossBlockSCC(MF);
-
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
MRI = &MF.getRegInfo();
TRI = ST.getRegisterInfo();
@@ -786,10 +782,8 @@ bool SIFixSGPRCopies::run(MachineFunction &MF) {
lowerVGPR2SGPRCopies(MF);
- validateNoCrossBlockSCC(MF);
// Postprocessing
fixSCCCopies(MF);
- validateNoCrossBlockSCC(MF);
for (auto *MI : S2VCopies) {
// Check if it is still valid
@@ -814,8 +808,6 @@ bool SIFixSGPRCopies::run(MachineFunction &MF) {
if (MF.getTarget().getOptLevel() > CodeGenOptLevel::None && EnableM0Merge)
hoistAndMergeSGPRInits(AMDGPU::M0, *MRI, TRI, *MDT, TII);
- validateNoCrossBlockSCC(MF);
-
SiblingPenalty.clear();
V2SCopies.clear();
SCCCopies.clear();
@@ -1069,72 +1061,6 @@ bool SIFixSGPRCopies::needToBeConvertedToVALU(V2SCopyInfo *Info) {
return Info->NeedToBeConvertedToVALU;
}
-void SIFixSGPRCopies::validateNoCrossBlockSCC(MachineFunction &MF) {
-
- for (const MachineBasicBlock &MBB : MF) {
- // assert(!MBB.isLiveIn(AMDGPU::SCC) && "AMDGPU::SCC is live-in to a basic
- // block! Cross-BB SCC liveness detected.");
-
- bool SCCDefinedInCurrentBlock = false;
-
- for (const MachineInstr &MI : MBB) {
- bool ReadsSCC = false;
- bool ModifiesSCC = false;
-
- for (const MachineOperand &MO : MI.operands()) {
- if (MO.isRegMask() && MO.clobbersPhysReg(AMDGPU::SCC)) {
- ModifiesSCC = true;
- continue;
- }
-
- if (!MO.isReg())
- continue;
-
- Register Reg = MO.getReg();
- if (!Reg || !Reg.isPhysical())
- continue;
-
- unsigned BitSize = 0;
- if (Reg.isPhysical()) {
- const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
- BitSize = TRI->getRegSizeInBits(*RC);
- } else {
- if (MRI->getType(Reg).isValid()) {
- BitSize = MRI->getType(Reg).getSizeInBits();
- } else {
- const TargetRegisterClass *RC = MRI->getRegClass(Reg);
- if (RC)
- BitSize = TRI->getRegSizeInBits(*RC);
- }
- }
-
- if (BitSize != 32)
- continue;
-
- if (TRI->regsOverlap(Reg, AMDGPU::SCC)) {
- if (MO.readsReg())
- ReadsSCC = true;
- if (MO.isDef())
- ModifiesSCC = true;
- }
- }
-
- if (ReadsSCC) {
- if (!SCCDefinedInCurrentBlock) {
- errs() << "Violation in MBB: " << MBB.getName() << "\n";
- errs() << "Instruction: " << MI << "\n";
- llvm_unreachable(
- "SCC is read before being defined in the same basic block!");
- }
- }
-
- if (ModifiesSCC) {
- SCCDefinedInCurrentBlock = true;
- }
- }
- }
-}
-
void SIFixSGPRCopies::lowerVGPR2SGPRCopies(MachineFunction &MF) {
SmallVector<unsigned, 8> LoweringWorklist;
diff --git a/llvm/test/CodeGen/AMDGPU/uniform_ext_i1_to_i32.ll b/llvm/test/CodeGen/AMDGPU/uniform_ext_i1_to_i32.ll
index 97aaf9eb4b681..183c8487a9698 100644
--- a/llvm/test/CodeGen/AMDGPU/uniform_ext_i1_to_i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/uniform_ext_i1_to_i32.ll
@@ -3,9 +3,36 @@
declare i32 @llvm.amdgcn.workitem.id.x() #0
-define amdgpu_kernel void @zext_i1_to_i64_uniform(ptr addrspace(1) %out, i1 %pred, i32 %a, i32 %b) #0 {
+; divergent i64
+define i64 @zext_i1_to_i64(i32 %a, i32 %b) #0 {
entry:
- ; GFX950-LABEL: zext_i1_to_i64_uniform
+ ; GFX950-LABEL: zext_i1_to_i64
+ ; GFX950: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+ ; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
+ ; GFX950-NEXT: v_mov_b32_e32 v1, 0
+ ; GFX950-NEXT: s_nop 0
+ ; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+ ; GFX950-NEXT: s_setpc_b64 s[30:31]
+
+ %cmp = icmp eq i32 %a, %b
+ %tmp2 = zext i1 %cmp to i64
+ ret i64 %tmp2
+}
+
+; divergent i32
+define i32 @zext_i1_to_i32(i1 %pred) #0 {
+entry:
+ ; GFX950-LABEL: zext_i1_to_i32
+ ; GFX950: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+ ; GFX950-NEXT: v_and_b32_e32 v0, 1, v0
+ ; GFX950-NEXT: s_setpc_b64 s[30:31]
+ %tmp2 = zext i1 %pred to i32
+ ret i32 %tmp2
+}
+
+define amdgpu_kernel void @kernel_zext_i1_to_i64_uniform(ptr addrspace(1) %out, i1 %pred, i32 %a, i32 %b) #0 {
+entry:
+ ; GFX950-LABEL: kernel_zext_i1_to_i64_uniform
; GFX950: s_load_dwordx2 s[0:1], s[4:5], 0x30
; GFX950-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX950-NEXT: s_mov_b32 s4, 0
@@ -24,9 +51,9 @@ entry:
ret void
}
-define amdgpu_kernel void @zext_i1_to_i32_uniform(ptr addrspace(1) %out, i1 %pred, i32 %a, i32 %b) #0 {
+define amdgpu_kernel void @kernel_zext_i1_to_i32_uniform(ptr addrspace(1) %out, i1 %pred, i32 %a, i32 %b) #0 {
entry:
- ; GFX950-LABEL: zext_i1_to_i32_uniform
+ ; GFX950-LABEL: kernel_zext_i1_to_i32_uniform
; GFX950: s_load_dwordx2 s[0:1], s[4:5], 0x30
; GFX950-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX950-NEXT: v_mov_b32_e32 v0, 0
@@ -34,7 +61,7 @@ entry:
; GFX950-NEXT: s_cmp_eq_u32 s0, s1
; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
- ; GFX950-NEXT: s_cselect_b32 s0, -1, 0
+ ; GFX950-NEXT: s_cselect_b32 s0, 1, 0
; GFX950-NEXT: v_mov_b32_e32 v1, s0
; GFX950-NEXT: global_store_dword v0, v1, s[2:3]
; GFX950-NEXT: s_endpgm
>From 21211ec274ee2d045b01d52b7de9b2d9ff31d17e Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Fri, 15 May 2026 19:45:14 +0000
Subject: [PATCH 07/29] cleanup
---
llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 5 -----
1 file changed, 5 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
index 603665611e2bf..ef0224ec723a0 100644
--- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
@@ -781,10 +781,8 @@ bool SIFixSGPRCopies::run(MachineFunction &MF) {
}
lowerVGPR2SGPRCopies(MF);
-
// Postprocessing
fixSCCCopies(MF);
-
for (auto *MI : S2VCopies) {
// Check if it is still valid
if (MI->isCopy()) {
@@ -1015,9 +1013,6 @@ void SIFixSGPRCopies::analyzeVGPRToSGPRCopy(MachineInstr* MI) {
}
}
- for (auto I : Info.SChain) {
- LLVM_DEBUG(dbgs() << "Chain 12345:"; I->dump(););
- }
V2SCopies[Info.ID] = std::move(Info);
}
>From 4770cf73336db313e7254d8ecbb1be924f2075cf Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Fri, 15 May 2026 19:45:49 +0000
Subject: [PATCH 08/29] cleanup
---
llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
index ef0224ec723a0..5994eeb54095b 100644
--- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
@@ -1012,7 +1012,6 @@ void SIFixSGPRCopies::analyzeVGPRToSGPRCopy(MachineInstr* MI) {
AnalysisWorklist.push_back(U);
}
}
-
V2SCopies[Info.ID] = std::move(Info);
}
>From 60d960b8654c74da71e29fcad25d386fda57cf83 Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Fri, 15 May 2026 20:05:21 +0000
Subject: [PATCH 09/29] comments
---
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 1 -
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 13 ++++++-------
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 17c1b048bd4d2..2ec959f392738 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -129,7 +129,6 @@ void InstrEmitter::EmitCopyFromReg(SDValue Op, bool IsClone, Register SrcReg,
RC = TRI->getAllocatableClass(
TII->getRegClass(II, i + II.getNumDefs()));
}
-
if (!UseRC)
UseRC = RC;
else if (RC) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 472dfae9405e3..19f68260c2a1b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -325,17 +325,14 @@ bool AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(SDNode *N) const {
return false;
}
+// TODO: To support sext and any_ext.
bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
- // If the extension of uniform i1 to i32 is not used as lanemask, we want to
- // the result type is int32. This method mutates node `zero_extend i1 to i32`
- // directly to S_CSELECT_B32. Instead of change the following
- // SI-Fix-SGPR-Copies to support it, we make changes earlier bofore inst
- // selection.
+ // This is special case for pattern of common compare + select if it can be
+ // selected to SALU. The pattern will be directly selected to `s_cselect`, to
+ // avoid an intermediate i1 virtual register to be interpreted as a lane mask.
if (N->isDivergent())
return false;
- // If to i64, it is probably used for lane mask, then we don't do the changes
- // here.
if (N->getValueType(0) != MVT::i32)
return false;
@@ -343,6 +340,8 @@ bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
if (CondNode->getOpcode() != ISD::SETCC)
return false;
+ // TODO: To support the operand type is int64 if s_cmp_i64 is supported on
+ // some targets
if (CondNode->getOperand(0).getValueType() != MVT::i32 ||
CondNode->getOperand(1).getValueType() != MVT::i32)
return false;
>From 59a38790c0da80c3a8ac817a5d7ca191252c0ca4 Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Fri, 15 May 2026 20:10:48 +0000
Subject: [PATCH 10/29] change TODO
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 19f68260c2a1b..780d334096c6e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -325,7 +325,6 @@ bool AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(SDNode *N) const {
return false;
}
-// TODO: To support sext and any_ext.
bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
// This is special case for pattern of common compare + select if it can be
// selected to SALU. The pattern will be directly selected to `s_cselect`, to
@@ -379,8 +378,9 @@ void AMDGPUDAGToDAGISel::PreprocessISelDAG() {
break;
case ISD::ZERO_EXTEND:
- MadeChange |= preprocessZeroExtend(N);
- break;
+ // TODO: To support sext and any_ext.
+ MadeChange |= preprocessZeroExtend(N);
+ break;
default:
break;
>From 57178ea2ea2f74faccf77045f88434283f3ce7fe Mon Sep 17 00:00:00 2001
From: Zeng Wu <zengwu13 at amd.com>
Date: Fri, 15 May 2026 16:53:58 -0700
Subject: [PATCH 11/29] Apply suggestion from @arsenm
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 780d334096c6e..89d0b8493a90c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -328,7 +328,9 @@ bool AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(SDNode *N) const {
bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
// This is special case for pattern of common compare + select if it can be
// selected to SALU. The pattern will be directly selected to `s_cselect`, to
- // avoid an intermediate i1 virtual register to be interpreted as a lane mask.
+ // This is special case for the common pattern of compare + select if it can be
+ // selected to SALU. The pattern will be directly selected to `s_cselect`, to
+ // avoid an intermediate i1 virtual register which will be interpreted as a lane mask.
if (N->isDivergent())
return false;
>From 32f09ca3ed971c2cb7bf21672618064a380ef0ea Mon Sep 17 00:00:00 2001
From: Zeng Wu <zengwu13 at amd.com>
Date: Fri, 15 May 2026 16:56:00 -0700
Subject: [PATCH 12/29] Apply suggestion from @arsenm
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 89d0b8493a90c..62a2cf58a8de5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -344,7 +344,7 @@ bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
// TODO: To support the operand type is int64 if s_cmp_i64 is supported on
// some targets
if (CondNode->getOperand(0).getValueType() != MVT::i32 ||
- CondNode->getOperand(1).getValueType() != MVT::i32)
+ if (CondNode->getOperand(0).getValueType() != MVT::i32)
return false;
SDLoc DL(N);
>From cda7d165698df2f8ae98625bc7b7b879fc44baf3 Mon Sep 17 00:00:00 2001
From: Zeng Wu <zengwu13 at amd.com>
Date: Fri, 15 May 2026 16:56:24 -0700
Subject: [PATCH 13/29] Apply suggestion from @arsenm
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 62a2cf58a8de5..6774944c592ba 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -344,6 +344,7 @@ bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
// TODO: To support the operand type is int64 if s_cmp_i64 is supported on
// some targets
if (CondNode->getOperand(0).getValueType() != MVT::i32 ||
+ if (CondNode->getOperand(0).getValueType() != MVT::i32)
if (CondNode->getOperand(0).getValueType() != MVT::i32)
return false;
>From 262117fcc5a313ad3eed2192ac50fbe4faeeae9f Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Sat, 16 May 2026 01:04:22 +0000
Subject: [PATCH 14/29] support i64
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 10 ++--
.../CodeGen/AMDGPU/uniform_ext_i1_to_i32.ll | 48 +++++++++++++++++--
2 files changed, 49 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 6774944c592ba..6635c4ee4b532 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -326,7 +326,7 @@ bool AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(SDNode *N) const {
}
bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
- // This is special case for pattern of common compare + select if it can be
+ // This is special case for common pattern of compare + select if it can be
// selected to SALU. The pattern will be directly selected to `s_cselect`, to
// This is special case for the common pattern of compare + select if it can be
// selected to SALU. The pattern will be directly selected to `s_cselect`, to
@@ -334,7 +334,8 @@ bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
if (N->isDivergent())
return false;
- if (N->getValueType(0) != MVT::i32)
+ EVT ResType = N->getOperand(0).getValueType();
+ if (ResType != MVT::i32 && ResType != MVT::i64)
return false;
SDValue CondNode = N->getOperand(0);
@@ -343,8 +344,6 @@ bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
// TODO: To support the operand type is int64 if s_cmp_i64 is supported on
// some targets
- if (CondNode->getOperand(0).getValueType() != MVT::i32 ||
- if (CondNode->getOperand(0).getValueType() != MVT::i32)
if (CondNode->getOperand(0).getValueType() != MVT::i32)
return false;
@@ -357,8 +356,9 @@ bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
CurDAG->getCopyToReg(Chain, DL, AMDGPU::SCC, CondNode, SDValue());
SDValue Ops[4] = {TrueValue, FalseValue, CopyToSCC.getValue(1),
CopyToSCC.getValue(1)};
+ auto SelectCode = ResType == MVT::i32 ? AMDGPU::S_CSELECT_B32 : AMDGPU::S_CSELECT_B64;
MachineSDNode *CSelectNode = CurDAG->getMachineNode(
- AMDGPU::S_CSELECT_B32, DL, CurDAG->getVTList(MVT::i32), Ops);
+ SelectCode, DL, CurDAG->getVTList(MVT::i32), Ops);
CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), SDValue(CSelectNode, 0));
return true;
diff --git a/llvm/test/CodeGen/AMDGPU/uniform_ext_i1_to_i32.ll b/llvm/test/CodeGen/AMDGPU/uniform_ext_i1_to_i32.ll
index 183c8487a9698..06e6fe7b09751 100644
--- a/llvm/test/CodeGen/AMDGPU/uniform_ext_i1_to_i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/uniform_ext_i1_to_i32.ll
@@ -4,9 +4,9 @@
declare i32 @llvm.amdgcn.workitem.id.x() #0
; divergent i64
-define i64 @zext_i1_to_i64(i32 %a, i32 %b) #0 {
+define i64 @test_zext_i1_to_i64(i32 %a, i32 %b) #0 {
entry:
- ; GFX950-LABEL: zext_i1_to_i64
+ ; GFX950-LABEL: test_zext_i1_to_i64
; GFX950: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
; GFX950-NEXT: v_mov_b32_e32 v1, 0
@@ -20,9 +20,9 @@ entry:
}
; divergent i32
-define i32 @zext_i1_to_i32(i1 %pred) #0 {
+define i32 @test_zext_i1_to_i32(i1 %pred) #0 {
entry:
- ; GFX950-LABEL: zext_i1_to_i32
+ ; GFX950-LABEL: test_zext_i1_to_i32
; GFX950: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_and_b32_e32 v0, 1, v0
; GFX950-NEXT: s_setpc_b64 s[30:31]
@@ -30,6 +30,46 @@ entry:
ret i32 %tmp2
}
+; uniform i32
+define i32 @test_uniform_zext(i32 inreg %val) {
+
+; GFX950-LABEL: test_uniform_zext:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: s_cmp_lg_u32 s0, 0
+; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX950-NEXT: s_cselect_b32 s0, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v0, s0
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+
+entry:
+ %cmp = icmp ne i32 %val, 0
+ %zext = zext i1 %cmp to i32
+
+ ret i32 %zext
+}
+
+; uniform i64
+define i64 @test_uniform_zext_i64(i32 inreg %val) {
+; GFX950-LABEL: test_uniform_zext_i64:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: s_cmp_lg_u32 s0, 0
+; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX950-NEXT: s_cselect_b32 s0, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v0, s0
+; GFX950-NEXT: v_mov_b32_e32 v1, 0
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+
+entry:
+ %cmp = icmp ne i32 %val, 0
+ %zext = zext i1 %cmp to i64
+
+ ret i64 %zext
+}
+
define amdgpu_kernel void @kernel_zext_i1_to_i64_uniform(ptr addrspace(1) %out, i1 %pred, i32 %a, i32 %b) #0 {
entry:
; GFX950-LABEL: kernel_zext_i1_to_i64_uniform
>From fcabf71751c26d2405be90b2227cf03b1008b9ee Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Sat, 16 May 2026 23:52:13 +0000
Subject: [PATCH 15/29] lit test
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 6635c4ee4b532..211bf6e9fdc81 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -356,7 +356,8 @@ bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
CurDAG->getCopyToReg(Chain, DL, AMDGPU::SCC, CondNode, SDValue());
SDValue Ops[4] = {TrueValue, FalseValue, CopyToSCC.getValue(1),
CopyToSCC.getValue(1)};
- auto SelectCode = ResType == MVT::i32 ? AMDGPU::S_CSELECT_B32 : AMDGPU::S_CSELECT_B64;
+ unsigned SelectCode =
+ ResType == MVT::i32 ? AMDGPU::S_CSELECT_B32 : AMDGPU::S_CSELECT_B64;
MachineSDNode *CSelectNode = CurDAG->getMachineNode(
SelectCode, DL, CurDAG->getVTList(MVT::i32), Ops);
CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), SDValue(CSelectNode, 0));
>From 43cf80e83fccd3f9a092c0e05e10476739ad85e2 Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Sat, 16 May 2026 23:52:13 +0000
Subject: [PATCH 16/29] extend lit tests to cover all ops in setcc and operand
types i16, i32 and i64
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 8 +-
.../CodeGen/AMDGPU/uniform_ext_i1_to_i32.ll | 114 -
.../AMDGPU/zero_extend_i1_to_i32_i64.ll | 2028 +++++++++++++++++
3 files changed, 2032 insertions(+), 118 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/uniform_ext_i1_to_i32.ll
create mode 100644 llvm/test/CodeGen/AMDGPU/zero_extend_i1_to_i32_i64.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 211bf6e9fdc81..5d27b02250d8b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -334,7 +334,7 @@ bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
if (N->isDivergent())
return false;
- EVT ResType = N->getOperand(0).getValueType();
+ EVT ResType = N->getValueType(0);
if (ResType != MVT::i32 && ResType != MVT::i64)
return false;
@@ -356,10 +356,10 @@ bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
CurDAG->getCopyToReg(Chain, DL, AMDGPU::SCC, CondNode, SDValue());
SDValue Ops[4] = {TrueValue, FalseValue, CopyToSCC.getValue(1),
CopyToSCC.getValue(1)};
- unsigned SelectCode =
- ResType == MVT::i32 ? AMDGPU::S_CSELECT_B32 : AMDGPU::S_CSELECT_B64;
+ bool IsInt32 = ResType == MVT::i32;
+ unsigned SelectCode = IsInt32 ? AMDGPU::S_CSELECT_B32 : AMDGPU::S_CSELECT_B64;
MachineSDNode *CSelectNode = CurDAG->getMachineNode(
- SelectCode, DL, CurDAG->getVTList(MVT::i32), Ops);
+ SelectCode, DL, CurDAG->getVTList(IsInt32 ? MVT::i32 : MVT::i64), Ops);
CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), SDValue(CSelectNode, 0));
return true;
diff --git a/llvm/test/CodeGen/AMDGPU/uniform_ext_i1_to_i32.ll b/llvm/test/CodeGen/AMDGPU/uniform_ext_i1_to_i32.ll
deleted file mode 100644
index 06e6fe7b09751..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/uniform_ext_i1_to_i32.ll
+++ /dev/null
@@ -1,114 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck --check-prefix=GFX950 %s
-
-declare i32 @llvm.amdgcn.workitem.id.x() #0
-
-; divergent i64
-define i64 @test_zext_i1_to_i64(i32 %a, i32 %b) #0 {
-entry:
- ; GFX950-LABEL: test_zext_i1_to_i64
- ; GFX950: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
- ; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
- ; GFX950-NEXT: v_mov_b32_e32 v1, 0
- ; GFX950-NEXT: s_nop 0
- ; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
- ; GFX950-NEXT: s_setpc_b64 s[30:31]
-
- %cmp = icmp eq i32 %a, %b
- %tmp2 = zext i1 %cmp to i64
- ret i64 %tmp2
-}
-
-; divergent i32
-define i32 @test_zext_i1_to_i32(i1 %pred) #0 {
-entry:
- ; GFX950-LABEL: test_zext_i1_to_i32
- ; GFX950: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
- ; GFX950-NEXT: v_and_b32_e32 v0, 1, v0
- ; GFX950-NEXT: s_setpc_b64 s[30:31]
- %tmp2 = zext i1 %pred to i32
- ret i32 %tmp2
-}
-
-; uniform i32
-define i32 @test_uniform_zext(i32 inreg %val) {
-
-; GFX950-LABEL: test_uniform_zext:
-; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: s_cmp_lg_u32 s0, 0
-; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
-; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; GFX950-NEXT: s_cselect_b32 s0, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v0, s0
-; GFX950-NEXT: s_setpc_b64 s[30:31]
-
-entry:
- %cmp = icmp ne i32 %val, 0
- %zext = zext i1 %cmp to i32
-
- ret i32 %zext
-}
-
-; uniform i64
-define i64 @test_uniform_zext_i64(i32 inreg %val) {
-; GFX950-LABEL: test_uniform_zext_i64:
-; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: s_cmp_lg_u32 s0, 0
-; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
-; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; GFX950-NEXT: s_cselect_b32 s0, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v0, s0
-; GFX950-NEXT: v_mov_b32_e32 v1, 0
-; GFX950-NEXT: s_setpc_b64 s[30:31]
-
-entry:
- %cmp = icmp ne i32 %val, 0
- %zext = zext i1 %cmp to i64
-
- ret i64 %zext
-}
-
-define amdgpu_kernel void @kernel_zext_i1_to_i64_uniform(ptr addrspace(1) %out, i1 %pred, i32 %a, i32 %b) #0 {
-entry:
- ; GFX950-LABEL: kernel_zext_i1_to_i64_uniform
- ; GFX950: s_load_dwordx2 s[0:1], s[4:5], 0x30
- ; GFX950-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
- ; GFX950-NEXT: s_mov_b32 s4, 0
- ; GFX950-NEXT: v_mov_b32_e32 v2, 0
- ; GFX950-NEXT: v_mov_b32_e32 v1, s4
- ; GFX950-NEXT: s_waitcnt lgkmcnt(0)
- ; GFX950-NEXT: s_cmp_eq_u32 s0, s1
- ; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
- ; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
- ; GFX950-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
- ; GFX950-NEXT: s_endpgm
-
- %cmp = icmp eq i32 %a, %b
- %tmp2 = zext i1 %cmp to i64
- store i64 %tmp2, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @kernel_zext_i1_to_i32_uniform(ptr addrspace(1) %out, i1 %pred, i32 %a, i32 %b) #0 {
-entry:
- ; GFX950-LABEL: kernel_zext_i1_to_i32_uniform
- ; GFX950: s_load_dwordx2 s[0:1], s[4:5], 0x30
- ; GFX950-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
- ; GFX950-NEXT: v_mov_b32_e32 v0, 0
- ; GFX950-NEXT: s_waitcnt lgkmcnt(0)
- ; GFX950-NEXT: s_cmp_eq_u32 s0, s1
- ; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
- ; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
- ; GFX950-NEXT: s_cselect_b32 s0, 1, 0
- ; GFX950-NEXT: v_mov_b32_e32 v1, s0
- ; GFX950-NEXT: global_store_dword v0, v1, s[2:3]
- ; GFX950-NEXT: s_endpgm
- %cmp = icmp eq i32 %a, %b
- %tmp2 = zext i1 %cmp to i32
- store i32 %tmp2, ptr addrspace(1) %out
- ret void
-}
-
-attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/AMDGPU/zero_extend_i1_to_i32_i64.ll b/llvm/test/CodeGen/AMDGPU/zero_extend_i1_to_i32_i64.ll
new file mode 100644
index 0000000000000..5566df56b098c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/zero_extend_i1_to_i32_i64.ll
@@ -0,0 +1,2028 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck --check-prefix=GFX950 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=GFX1250 %s
+
+declare i32 @llvm.amdgcn.workitem.id.x() #0
+
+; ============================================================================
+; Divergent i32 compares
+; ============================================================================
+
+define i32 @divergent_i32_eq_i32(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_eq_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: divergent_i32_eq_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp eq i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i64 @divergent_i32_eq_i64(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_eq_i64:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
+; GFX950-NEXT: v_mov_b32_e32 v1, 0
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: divergent_i32_eq_i64:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp eq i32 %a, %b
+ %zext = zext i1 %cmp to i64
+ ret i64 %zext
+}
+
+define i32 @divergent_i32_ne_i32(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_ne_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: divergent_i32_ne_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp ne i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @divergent_i32_ugt_i32(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_ugt_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_gt_u32_e32 vcc, v0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: divergent_i32_ugt_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp ugt i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @divergent_i32_uge_i32(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_uge_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: divergent_i32_uge_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp uge i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @divergent_i32_ult_i32(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_ult_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: divergent_i32_ult_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp ult i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @divergent_i32_ule_i32(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_ule_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_le_u32_e32 vcc, v0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: divergent_i32_ule_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_le_u32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp ule i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @divergent_i32_sgt_i32(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_sgt_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, v0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: divergent_i32_sgt_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp sgt i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @divergent_i32_sge_i32(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_sge_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: divergent_i32_sge_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_ge_i32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp sge i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @divergent_i32_slt_i32(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_slt_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: divergent_i32_slt_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp slt i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @divergent_i32_sle_i32(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_sle_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_le_i32_e32 vcc, v0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: divergent_i32_sle_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_le_i32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp sle i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+; ============================================================================
+; Uniform i32 compares
+; ============================================================================
+
+define i32 @uniform_i32_eq_i32(i32 inreg %a, i32 inreg %b) #0 {
+; GFX950-LABEL: uniform_i32_eq_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: s_cmp_eq_u32 s0, s1
+; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX950-NEXT: s_cselect_b32 s0, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v0, s0
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: uniform_i32_eq_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_eq_u32 s0, s1
+; GFX1250-NEXT: s_cselect_b32 s0, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1250-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp eq i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i64 @uniform_i32_eq_i64(i32 inreg %a, i32 inreg %b) #0 {
+; GFX950-LABEL: uniform_i32_eq_i64:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: s_cmp_eq_u32 s0, s1
+; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX950-NEXT: s_cselect_b32 s0, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v0, s0
+; GFX950-NEXT: v_mov_b32_e32 v1, 0
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: uniform_i32_eq_i64:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_eq_u32 s0, s1
+; GFX1250-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-NEXT: s_cselect_b32 s0, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1250-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp eq i32 %a, %b
+ %zext = zext i1 %cmp to i64
+ ret i64 %zext
+}
+
+define i32 @uniform_i32_ne_i32(i32 inreg %a, i32 inreg %b) #0 {
+; GFX950-LABEL: uniform_i32_ne_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: s_cmp_lg_u32 s0, s1
+; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX950-NEXT: s_cselect_b32 s0, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v0, s0
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: uniform_i32_ne_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_lg_u32 s0, s1
+; GFX1250-NEXT: s_cselect_b32 s0, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1250-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp ne i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @uniform_i32_ugt_i32(i32 inreg %a, i32 inreg %b) #0 {
+; GFX950-LABEL: uniform_i32_ugt_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: s_cmp_gt_u32 s0, s1
+; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX950-NEXT: s_cselect_b32 s0, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v0, s0
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: uniform_i32_ugt_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_gt_u32 s0, s1
+; GFX1250-NEXT: s_cselect_b32 s0, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1250-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp ugt i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @uniform_i32_uge_i32(i32 inreg %a, i32 inreg %b) #0 {
+; GFX950-LABEL: uniform_i32_uge_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: s_cmp_ge_u32 s0, s1
+; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX950-NEXT: s_cselect_b32 s0, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v0, s0
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: uniform_i32_uge_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_ge_u32 s0, s1
+; GFX1250-NEXT: s_cselect_b32 s0, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1250-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp uge i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @uniform_i32_ult_i32(i32 inreg %a, i32 inreg %b) #0 {
+; GFX950-LABEL: uniform_i32_ult_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: s_cmp_lt_u32 s0, s1
+; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX950-NEXT: s_cselect_b32 s0, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v0, s0
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: uniform_i32_ult_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_lt_u32 s0, s1
+; GFX1250-NEXT: s_cselect_b32 s0, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1250-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp ult i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @uniform_i32_ule_i32(i32 inreg %a, i32 inreg %b) #0 {
+; GFX950-LABEL: uniform_i32_ule_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: s_cmp_le_u32 s0, s1
+; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX950-NEXT: s_cselect_b32 s0, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v0, s0
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: uniform_i32_ule_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_le_u32 s0, s1
+; GFX1250-NEXT: s_cselect_b32 s0, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1250-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp ule i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @uniform_i32_sgt_i32(i32 inreg %a, i32 inreg %b) #0 {
+; GFX950-LABEL: uniform_i32_sgt_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: s_cmp_gt_i32 s0, s1
+; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX950-NEXT: s_cselect_b32 s0, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v0, s0
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: uniform_i32_sgt_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_gt_i32 s0, s1
+; GFX1250-NEXT: s_cselect_b32 s0, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1250-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp sgt i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @uniform_i32_sge_i32(i32 inreg %a, i32 inreg %b) #0 {
+; GFX950-LABEL: uniform_i32_sge_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: s_cmp_ge_i32 s0, s1
+; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX950-NEXT: s_cselect_b32 s0, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v0, s0
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: uniform_i32_sge_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_ge_i32 s0, s1
+; GFX1250-NEXT: s_cselect_b32 s0, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1250-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp sge i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @uniform_i32_slt_i32(i32 inreg %a, i32 inreg %b) #0 {
+; GFX950-LABEL: uniform_i32_slt_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: s_cmp_lt_i32 s0, s1
+; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX950-NEXT: s_cselect_b32 s0, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v0, s0
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: uniform_i32_slt_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_lt_i32 s0, s1
+; GFX1250-NEXT: s_cselect_b32 s0, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1250-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp slt i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @uniform_i32_sle_i32(i32 inreg %a, i32 inreg %b) #0 {
+; GFX950-LABEL: uniform_i32_sle_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: s_cmp_le_i32 s0, s1
+; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX950-NEXT: s_cselect_b32 s0, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v0, s0
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: uniform_i32_sle_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_le_i32 s0, s1
+; GFX1250-NEXT: s_cselect_b32 s0, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1250-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp sle i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+
+; ============================================================================
+; AMDGPU_KERNEL ABI tests
+; ============================================================================
+
+; ----------------------------------------------------------------------------
+; Uniform i32 compares
+; ----------------------------------------------------------------------------
+
+define amdgpu_kernel void @kernel_uniform_i32_eq_i32(
+; GFX950-LABEL: kernel_uniform_i32_eq_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_cmp_eq_u32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i32_eq_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_eq_u32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i32 %a,
+ i32 %b) #0 {
+entry:
+ %cmp = icmp eq i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i32_eq_i64(
+; GFX950-LABEL: kernel_uniform_i32_eq_i64:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_cmp_eq_u32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b64 s[2:3], 1, 0
+; GFX950-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
+; GFX950-NEXT: global_store_dwordx2 v0, v[2:3], s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i32_eq_i64:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_eq_u32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b64 s[2:3], 1, 0
+; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[2:3]
+; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i32 %a,
+ i32 %b) #0 {
+entry:
+ %cmp = icmp eq i32 %a, %b
+ %zext = zext i1 %cmp to i64
+ store i64 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i32_ne_i32(
+; GFX950-LABEL: kernel_uniform_i32_ne_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_cmp_lg_u32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i32_ne_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_lg_u32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i32 %a,
+ i32 %b) #0 {
+entry:
+ %cmp = icmp ne i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i32_ugt_i32(
+; GFX950-LABEL: kernel_uniform_i32_ugt_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_cmp_gt_u32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i32_ugt_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_gt_u32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i32 %a,
+ i32 %b) #0 {
+entry:
+ %cmp = icmp ugt i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i32_uge_i32(
+; GFX950-LABEL: kernel_uniform_i32_uge_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_cmp_ge_u32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i32_uge_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_ge_u32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i32 %a,
+ i32 %b) #0 {
+entry:
+ %cmp = icmp uge i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i32_ult_i32(
+; GFX950-LABEL: kernel_uniform_i32_ult_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_cmp_lt_u32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i32_ult_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_lt_u32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i32 %a,
+ i32 %b) #0 {
+entry:
+ %cmp = icmp ult i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i32_ule_i32(
+; GFX950-LABEL: kernel_uniform_i32_ule_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_cmp_le_u32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i32_ule_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_le_u32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i32 %a,
+ i32 %b) #0 {
+entry:
+ %cmp = icmp ule i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i32_sgt_i32(
+; GFX950-LABEL: kernel_uniform_i32_sgt_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_cmp_gt_i32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i32_sgt_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_gt_i32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i32 %a,
+ i32 %b) #0 {
+entry:
+ %cmp = icmp sgt i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i32_sge_i32(
+; GFX950-LABEL: kernel_uniform_i32_sge_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_cmp_ge_i32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i32_sge_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_ge_i32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i32 %a,
+ i32 %b) #0 {
+entry:
+ %cmp = icmp sge i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i32_slt_i32(
+; GFX950-LABEL: kernel_uniform_i32_slt_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_cmp_lt_i32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i32_slt_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_lt_i32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i32 %a,
+ i32 %b) #0 {
+entry:
+ %cmp = icmp slt i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i32_sle_i32(
+; GFX950-LABEL: kernel_uniform_i32_sle_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_cmp_le_i32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i32_sle_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_le_i32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i32 %a,
+ i32 %b) #0 {
+entry:
+ %cmp = icmp sle i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+; ----------------------------------------------------------------------------
+; Uniform i16 compares
+; ----------------------------------------------------------------------------
+
+define amdgpu_kernel void @kernel_uniform_i16_eq_i32(
+; GFX950-LABEL: kernel_uniform_i16_eq_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_lshr_b32 s3, s2, 16
+; GFX950-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX950-NEXT: s_cmp_eq_u32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i16_eq_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_lshr_b32 s3, s2, 16
+; GFX1250-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_cmp_eq_u32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i16 %a,
+ i16 %b) #0 {
+entry:
+ %cmp = icmp eq i16 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i16_eq_i64(
+; GFX950-LABEL: kernel_uniform_i16_eq_i64:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_lshr_b32 s3, s2, 16
+; GFX950-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX950-NEXT: s_cmp_eq_u32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b64 s[2:3], 1, 0
+; GFX950-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
+; GFX950-NEXT: global_store_dwordx2 v0, v[2:3], s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i16_eq_i64:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
+; GFX1250-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_lshr_b32 s3, s2, 16
+; GFX1250-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_cmp_eq_u32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b64 s[2:3], 1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[2:3]
+; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i16 %a,
+ i16 %b) #0 {
+entry:
+ %cmp = icmp eq i16 %a, %b
+ %zext = zext i1 %cmp to i64
+ store i64 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i16_ne_i32(
+; GFX950-LABEL: kernel_uniform_i16_ne_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_lshr_b32 s3, s2, 16
+; GFX950-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX950-NEXT: s_cmp_lg_u32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i16_ne_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_lshr_b32 s3, s2, 16
+; GFX1250-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_cmp_lg_u32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i16 %a,
+ i16 %b) #0 {
+entry:
+ %cmp = icmp ne i16 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i16_ugt_i32(
+; GFX950-LABEL: kernel_uniform_i16_ugt_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_lshr_b32 s3, s2, 16
+; GFX950-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX950-NEXT: s_cmp_gt_u32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i16_ugt_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_lshr_b32 s3, s2, 16
+; GFX1250-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_cmp_gt_u32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i16 %a,
+ i16 %b) #0 {
+entry:
+ %cmp = icmp ugt i16 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i16_uge_i32(
+; GFX950-LABEL: kernel_uniform_i16_uge_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_lshr_b32 s3, s2, 16
+; GFX950-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX950-NEXT: s_cmp_ge_u32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i16_uge_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_lshr_b32 s3, s2, 16
+; GFX1250-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_cmp_ge_u32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i16 %a,
+ i16 %b) #0 {
+entry:
+ %cmp = icmp uge i16 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i16_ult_i32(
+; GFX950-LABEL: kernel_uniform_i16_ult_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_lshr_b32 s3, s2, 16
+; GFX950-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX950-NEXT: s_cmp_lt_u32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i16_ult_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_lshr_b32 s3, s2, 16
+; GFX1250-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_cmp_lt_u32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i16 %a,
+ i16 %b) #0 {
+entry:
+ %cmp = icmp ult i16 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i16_ule_i32(
+; GFX950-LABEL: kernel_uniform_i16_ule_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_lshr_b32 s3, s2, 16
+; GFX950-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX950-NEXT: s_cmp_le_u32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i16_ule_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_lshr_b32 s3, s2, 16
+; GFX1250-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_cmp_le_u32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i16 %a,
+ i16 %b) #0 {
+entry:
+ %cmp = icmp ule i16 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i16_sgt_i32(
+; GFX950-LABEL: kernel_uniform_i16_sgt_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_ashr_i32 s3, s2, 16
+; GFX950-NEXT: s_sext_i32_i16 s2, s2
+; GFX950-NEXT: s_cmp_gt_i32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i16_sgt_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_ashr_i32 s3, s2, 16
+; GFX1250-NEXT: s_sext_i32_i16 s2, s2
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_cmp_gt_i32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i16 %a,
+ i16 %b) #0 {
+entry:
+ %cmp = icmp sgt i16 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i16_sge_i32(
+; GFX950-LABEL: kernel_uniform_i16_sge_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_ashr_i32 s3, s2, 16
+; GFX950-NEXT: s_sext_i32_i16 s2, s2
+; GFX950-NEXT: s_cmp_ge_i32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i16_sge_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_ashr_i32 s3, s2, 16
+; GFX1250-NEXT: s_sext_i32_i16 s2, s2
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_cmp_ge_i32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i16 %a,
+ i16 %b) #0 {
+entry:
+ %cmp = icmp sge i16 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i16_slt_i32(
+; GFX950-LABEL: kernel_uniform_i16_slt_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_ashr_i32 s3, s2, 16
+; GFX950-NEXT: s_sext_i32_i16 s2, s2
+; GFX950-NEXT: s_cmp_lt_i32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i16_slt_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_ashr_i32 s3, s2, 16
+; GFX1250-NEXT: s_sext_i32_i16 s2, s2
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_cmp_lt_i32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i16 %a,
+ i16 %b) #0 {
+entry:
+ %cmp = icmp slt i16 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i16_sle_i32(
+; GFX950-LABEL: kernel_uniform_i16_sle_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_ashr_i32 s3, s2, 16
+; GFX950-NEXT: s_sext_i32_i16 s2, s2
+; GFX950-NEXT: s_cmp_le_i32 s2, s3
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i16_sle_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_ashr_i32 s3, s2, 16
+; GFX1250-NEXT: s_sext_i32_i16 s2, s2
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_cmp_le_i32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i16 %a,
+ i16 %b) #0 {
+entry:
+ %cmp = icmp sle i16 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+; ----------------------------------------------------------------------------
+; Divergent i64 compares
+; ----------------------------------------------------------------------------
+
+define amdgpu_kernel void @kernel_i64_eq_i32(
+; GFX950-LABEL: kernel_i64_eq_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[2:3]
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_i64_eq_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
+; GFX1250-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i64 %a,
+ i64 %b) #0 {
+entry:
+ %cmp = icmp eq i64 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_i64_eq_i64(
+; GFX950-LABEL: kernel_i64_eq_i64:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX950-NEXT: s_mov_b32 s4, 0
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s4
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[2:3]
+; GFX950-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_i64_eq_i64:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
+; GFX1250-NEXT: s_mov_b32 s2, 0
+; GFX1250-NEXT: s_cselect_b32 s3, -1, 0
+; GFX1250-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, s3
+; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i64 %a,
+ i64 %b) #0 {
+entry:
+ %cmp = icmp eq i64 %a, %b
+ %zext = zext i1 %cmp to i64
+ store i64 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_i64_ne_i32(
+; GFX950-LABEL: kernel_i64_ne_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_cmp_lg_u64 s[2:3], s[6:7]
+; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX950-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[2:3]
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_i64_ne_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
+; GFX1250-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_lg_u64 s[2:3], s[6:7]
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i64 %a,
+ i64 %b) #0 {
+entry:
+ %cmp = icmp ne i64 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_i64_ugt_i32(
+; GFX950-LABEL: kernel_i64_ugt_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
+; GFX950-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1]
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_i64_ugt_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
+; GFX1250-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_gt_u64_e64 s2, s[2:3], s[6:7]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i64 %a,
+ i64 %b) #0 {
+entry:
+ %cmp = icmp ugt i64 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_i64_uge_i32(
+; GFX950-LABEL: kernel_i64_uge_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
+; GFX950-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[0:1]
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_i64_uge_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
+; GFX1250-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_ge_u64_e64 s2, s[2:3], s[6:7]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i64 %a,
+ i64 %b) #0 {
+entry:
+ %cmp = icmp uge i64 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_i64_ult_i32(
+; GFX950-LABEL: kernel_i64_ult_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
+; GFX950-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1]
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_i64_ult_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
+; GFX1250-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_lt_u64_e64 s2, s[2:3], s[6:7]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i64 %a,
+ i64 %b) #0 {
+entry:
+ %cmp = icmp ult i64 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i64_ule_i32(
+; GFX950-LABEL: kernel_uniform_i64_ule_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
+; GFX950-NEXT: v_cmp_le_u64_e32 vcc, s[2:3], v[0:1]
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i64_ule_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
+; GFX1250-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_le_u64_e64 s2, s[2:3], s[6:7]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i64 %a,
+ i64 %b) #0 {
+entry:
+ %cmp = icmp ule i64 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i64_sgt_i32(
+; GFX950-LABEL: kernel_uniform_i64_sgt_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
+; GFX950-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i64_sgt_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
+; GFX1250-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_gt_i64_e64 s2, s[2:3], s[6:7]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i64 %a,
+ i64 %b) #0 {
+entry:
+ %cmp = icmp sgt i64 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i64_sge_i32(
+; GFX950-LABEL: kernel_uniform_i64_sge_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
+; GFX950-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[0:1]
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i64_sge_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
+; GFX1250-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_ge_i64_e64 s2, s[2:3], s[6:7]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i64 %a,
+ i64 %b) #0 {
+entry:
+ %cmp = icmp sge i64 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i64_slt_i32(
+; GFX950-LABEL: kernel_uniform_i64_slt_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
+; GFX950-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i64_slt_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
+; GFX1250-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_lt_i64_e64 s2, s[2:3], s[6:7]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i64 %a,
+ i64 %b) #0 {
+entry:
+ %cmp = icmp slt i64 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @kernel_uniform_i64_sle_i32(
+; GFX950-LABEL: kernel_uniform_i64_sle_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
+; GFX950-NEXT: v_cmp_le_i64_e32 vcc, s[2:3], v[0:1]
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_uniform_i64_sle_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
+; GFX1250-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_le_i64_e64 s2, s[2:3], s[6:7]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i64 %a,
+ i64 %b) #0 {
+entry:
+ %cmp = icmp sle i64 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+
+; To test divergent with amdgpu kernel ABI.
+define amdgpu_kernel void @kernel_divergent_i32_cmp_i32(ptr addrspace(1) %out, i1 %pred, i32 %a) #0 {
+; GFX950-LABEL: kernel_divergent_i32_cmp_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x30
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX950-NEXT: v_mov_b32_e32 v1, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, s2, v0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_divergent_i32_cmp_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x30 nv
+; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1250-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, s2, v0
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX1250-NEXT: s_endpgm
+entry:
+ %workitem.id = call i32 @llvm.amdgcn.workitem.id.x()
+ %cmp = icmp eq i32 %a, %workitem.id
+ %tmp2 = zext i1 %cmp to i32
+ store i32 %tmp2, ptr addrspace(1) %out
+ ret void
+}
+
+; To test divergent zero i1 to i64 with amdgpu kernel ABI
+define amdgpu_kernel void @kernel_divergent_i64_cmp_i32(ptr addrspace(1) %out, i1 %pred, i32 %a) #0 {
+; GFX950-LABEL: kernel_divergent_i64_cmp_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x30
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, s2, v0
+; GFX950-NEXT: s_mov_b32 s2, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: kernel_divergent_i64_cmp_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x30 nv
+; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1250-NEXT: s_mov_b32 s3, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, s2, v0
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX1250-NEXT: s_endpgm
+entry:
+ %workitem.id = call i32 @llvm.amdgcn.workitem.id.x()
+ %cmp = icmp eq i32 %a, %workitem.id
+ %tmp2 = zext i1 %cmp to i64
+ store i64 %tmp2, ptr addrspace(1) %out
+ ret void
+}
+
+; To test divergent with amdgpu kernel ABI.
+define amdgpu_kernel void @zext_i1_to_i32_uniform(ptr addrspace(1) %out, i1 %pred, i32 %a) #0 {
+; GFX950-LABEL: zext_i1_to_i32_uniform:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x30
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX950-NEXT: v_mov_b32_e32 v1, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, s2, v0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: zext_i1_to_i32_uniform:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x30 nv
+; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1250-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, s2, v0
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX1250-NEXT: s_endpgm
+entry:
+ %workitem.id = call i32 @llvm.amdgcn.workitem.id.x()
+ %cmp = icmp eq i32 %a, %workitem.id
+ %tmp2 = zext i1 %cmp to i32
+ store i32 %tmp2, ptr addrspace(1) %out
+ ret void
+}
+
+; TO test zero_extend from i1 to 64 uniform
+define amdgpu_kernel void @zext_i1_to_i64_uniform(ptr addrspace(1) %out, i1 %pred, i32 %a, i32 %b) #0 {
+; GFX950-LABEL: zext_i1_to_i64_uniform:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x30
+; GFX950-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_cmp_eq_u32 s0, s1
+; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX950-NEXT: s_cselect_b64 s[0:1], 1, 0
+; GFX950-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-NEXT: global_store_dwordx2 v0, v[2:3], s[2:3]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: zext_i1_to_i64_uniform:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x30 nv
+; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_eq_u32 s0, s1
+; GFX1250-NEXT: s_cselect_b32 s0, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1250-NEXT: s_cselect_b64 s[0:1], 1, 0
+; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
+; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[2:3]
+; GFX1250-NEXT: s_endpgm
+entry:
+ %cmp = icmp eq i32 %a, %b
+ %tmp2 = zext i1 %cmp to i64
+ store i64 %tmp2, ptr addrspace(1) %out
+ ret void
+}
>From 3d0256116891c124c9518e14a1fb1654987d8cbc Mon Sep 17 00:00:00 2001
From: Zeng Wu <zengwu13 at amd.com>
Date: Sat, 16 May 2026 22:57:54 -0700
Subject: [PATCH 17/29] Update llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
Co-authored-by: Shilei Tian <i at tianshilei.me>
---
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 2ec959f392738..d7d9cb4132c5d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -157,7 +157,11 @@ void InstrEmitter::EmitCopyFromReg(SDValue Op, bool IsClone, Register SrcReg,
} else if (const TargetRegisterClass *CommonSubClass =
TRI->getCommonSubClass(UseRC, RegClassForVT)) {
UseRC = CommonSubClass;
- }
+ if (!UseRC || !UseRC->isAllocatable())
+ UseRC = RegClassForVT;
+ else if (const TargetRegisterClass *CommonSubClass =
+ TRI->getCommonSubClass(UseRC, RegClassForVT))
+ UseRC = CommonSubClass;
const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
>From c3531d6fcfea039443a515bec2c133ee4822d4dc Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Sun, 17 May 2026 06:56:22 +0000
Subject: [PATCH 18/29] update lit test
---
.../AMDGPU/zero_extend_i1_to_i32_i64.ll | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/llvm/test/CodeGen/AMDGPU/zero_extend_i1_to_i32_i64.ll b/llvm/test/CodeGen/AMDGPU/zero_extend_i1_to_i32_i64.ll
index 5566df56b098c..7fa407866dac9 100644
--- a/llvm/test/CodeGen/AMDGPU/zero_extend_i1_to_i32_i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/zero_extend_i1_to_i32_i64.ll
@@ -2026,3 +2026,27 @@ entry:
store i64 %tmp2, ptr addrspace(1) %out
ret void
}
+
+define amdgpu_ps i32 @zext_i1_to_i32_uniform_amdgpu_ps_abi(i32 inreg %a, i32 inreg %b) #0 {
+; GFX950-LABEL: zext_i1_to_i32_uniform_amdgpu_ps_abi:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_cmp_eq_u32 s0, s1
+; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX950-NEXT: s_cselect_b32 s0, 1, 0
+; GFX950-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: zext_i1_to_i32_uniform_amdgpu_ps_abi:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_cmp_eq_u32 s0, s1
+; GFX1250-NEXT: s_cselect_b32 s0, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1250-NEXT: ; return to shader part epilog
+entry:
+ %cmp = icmp eq i32 %a, %b
+ %tmp2 = zext i1 %cmp to i32
+ ret i32 %tmp2
+}
>From 523573a37dae4f88fb7fe6202e95ad9bbf9c4f77 Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Mon, 18 May 2026 04:35:13 +0000
Subject: [PATCH 19/29] format
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 5d27b02250d8b..3cf6086d1dac0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -378,7 +378,7 @@ void AMDGPUDAGToDAGISel::PreprocessISelDAG() {
case ISD::BUILD_VECTOR:
// TODO: Match load d16 from shl (extload:i16), 16
if (Subtarget->d16PreservesUnusedBits())
- MadeChange |= matchLoadD16FromBuildVector(N);
+ MadeChange |= matchLoadD16FromBuildVector(N);
break;
case ISD::ZERO_EXTEND:
>From 29589b4433535ca01bda62515060e1ad20bc57c9 Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Mon, 18 May 2026 04:45:11 +0000
Subject: [PATCH 20/29] apply clang-format for all relevant changes
---
.../lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 59 ++++++++++---------
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 7 ++-
2 files changed, 34 insertions(+), 32 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index d7d9cb4132c5d..e83037f264e7f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -157,36 +157,37 @@ void InstrEmitter::EmitCopyFromReg(SDValue Op, bool IsClone, Register SrcReg,
} else if (const TargetRegisterClass *CommonSubClass =
TRI->getCommonSubClass(UseRC, RegClassForVT)) {
UseRC = CommonSubClass;
- if (!UseRC || !UseRC->isAllocatable())
- UseRC = RegClassForVT;
- else if (const TargetRegisterClass *CommonSubClass =
+ if (!UseRC || !UseRC->isAllocatable())
+ UseRC = RegClassForVT;
+ else if (const TargetRegisterClass *CommonSubClass =
TRI->getCommonSubClass(UseRC, RegClassForVT))
- UseRC = CommonSubClass;
-
- const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
- SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
-
- // Figure out the register class to create for the destreg.
- if (VRBase) {
- DstRC = MRI->getRegClass(VRBase);
- } else if (UseRC) {
- assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
- "Incompatible phys register def and uses!");
- DstRC = UseRC;
- } else
- DstRC = SrcRC;
-
- // If all uses are reading from the src physical register and copying the
- // register is either impossible or very expensive, then don't create a copy.
- if (MatchReg && SrcRC->expensiveOrImpossibleToCopy()) {
- VRBase = SrcReg;
- } else {
- // Create the reg, emit the copy.
- VRBase = MRI->createVirtualRegister(DstRC);
- BuildMI(*MBB, InsertPos, Op.getDebugLoc(), TII->get(TargetOpcode::COPY),
- VRBase)
- .addReg(SrcReg);
- }
+ UseRC = CommonSubClass;
+
+ const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
+ SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
+
+ // Figure out the register class to create for the destreg.
+ if (VRBase) {
+ DstRC = MRI->getRegClass(VRBase);
+ } else if (UseRC) {
+ assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
+ "Incompatible phys register def and uses!");
+ DstRC = UseRC;
+ } else
+ DstRC = SrcRC;
+
+ // If all uses are reading from the src physical register and copying the
+ // register is either impossible or very expensive, then don't create a
+ // copy.
+ if (MatchReg && SrcRC->expensiveOrImpossibleToCopy()) {
+ VRBase = SrcReg;
+ } else {
+ // Create the reg, emit the copy.
+ VRBase = MRI->createVirtualRegister(DstRC);
+ BuildMI(*MBB, InsertPos, Op.getDebugLoc(), TII->get(TargetOpcode::COPY),
+ VRBase)
+ .addReg(SrcReg);
+ }
if (IsClone)
VRBaseMap.erase(Op);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 3cf6086d1dac0..838a46878d609 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -328,9 +328,10 @@ bool AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(SDNode *N) const {
bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
// This is special case for common pattern of compare + select if it can be
// selected to SALU. The pattern will be directly selected to `s_cselect`, to
- // This is special case for the common pattern of compare + select if it can be
- // selected to SALU. The pattern will be directly selected to `s_cselect`, to
- // avoid an intermediate i1 virtual register which will be interpreted as a lane mask.
+ // This is special case for the common pattern of compare + select if it can
+ // be selected to SALU. The pattern will be directly selected to `s_cselect`,
+ // to avoid an intermediate i1 virtual register which will be interpreted as a
+ // lane mask.
if (N->isDivergent())
return false;
>From 89c333fb68ea04ff0fc4674851101d30d5ecd8e8 Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Mon, 18 May 2026 04:51:34 +0000
Subject: [PATCH 21/29] format
---
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index e83037f264e7f..5b60315d3f214 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -188,6 +188,7 @@ void InstrEmitter::EmitCopyFromReg(SDValue Op, bool IsClone, Register SrcReg,
VRBase)
.addReg(SrcReg);
}
+ }
if (IsClone)
VRBaseMap.erase(Op);
>From ae1e0dc3e6987444883d5020c334da82d4cd90bb Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Mon, 18 May 2026 18:12:03 +0000
Subject: [PATCH 22/29] fix rebase error
---
.../lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 63 ++++++++++---------
1 file changed, 32 insertions(+), 31 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 5b60315d3f214..ce0e7b73cdfb9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -157,37 +157,38 @@ void InstrEmitter::EmitCopyFromReg(SDValue Op, bool IsClone, Register SrcReg,
} else if (const TargetRegisterClass *CommonSubClass =
TRI->getCommonSubClass(UseRC, RegClassForVT)) {
UseRC = CommonSubClass;
- if (!UseRC || !UseRC->isAllocatable())
- UseRC = RegClassForVT;
- else if (const TargetRegisterClass *CommonSubClass =
- TRI->getCommonSubClass(UseRC, RegClassForVT))
- UseRC = CommonSubClass;
-
- const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
- SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
-
- // Figure out the register class to create for the destreg.
- if (VRBase) {
- DstRC = MRI->getRegClass(VRBase);
- } else if (UseRC) {
- assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
- "Incompatible phys register def and uses!");
- DstRC = UseRC;
- } else
- DstRC = SrcRC;
-
- // If all uses are reading from the src physical register and copying the
- // register is either impossible or very expensive, then don't create a
- // copy.
- if (MatchReg && SrcRC->expensiveOrImpossibleToCopy()) {
- VRBase = SrcReg;
- } else {
- // Create the reg, emit the copy.
- VRBase = MRI->createVirtualRegister(DstRC);
- BuildMI(*MBB, InsertPos, Op.getDebugLoc(), TII->get(TargetOpcode::COPY),
- VRBase)
- .addReg(SrcReg);
- }
+ }
+
+ if (!UseRC || !UseRC->isAllocatable())
+ UseRC = RegClassForVT;
+ else if (const TargetRegisterClass *CommonSubClass =
+ TRI->getCommonSubClass(UseRC, RegClassForVT))
+ UseRC = CommonSubClass;
+
+ const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
+ SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
+
+ // Figure out the register class to create for the destreg.
+ if (VRBase) {
+ DstRC = MRI->getRegClass(VRBase);
+ } else if (UseRC) {
+ assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
+ "Incompatible phys register def and uses!");
+ DstRC = UseRC;
+ } else
+ DstRC = SrcRC;
+
+ // If all uses are reading from the src physical register and copying the
+ // register is either impossible or very expensive, then don't create a
+ // copy.
+ if (MatchReg && SrcRC->expensiveOrImpossibleToCopy()) {
+ VRBase = SrcReg;
+ } else {
+ // Create the reg, emit the copy.
+ VRBase = MRI->createVirtualRegister(DstRC);
+ BuildMI(*MBB, InsertPos, Op.getDebugLoc(), TII->get(TargetOpcode::COPY),
+ VRBase)
+ .addReg(SrcReg);
}
if (IsClone)
>From 7c5513d9d0fb39b6e8dbe1d80d2bef7c4a4e46fa Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Tue, 19 May 2026 06:50:17 +0000
Subject: [PATCH 23/29] refactor lit-test
---
llvm/test/CodeGen/AMDGPU/zero_extend.ll | 686 +++++++
.../AMDGPU/zero_extend_i1_to_i32_i64.ll | 1703 +++++------------
2 files changed, 1203 insertions(+), 1186 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/zero_extend.ll b/llvm/test/CodeGen/AMDGPU/zero_extend.ll
index f0f8eaa7ab0de..0199aa6c00427 100644
--- a/llvm/test/CodeGen/AMDGPU/zero_extend.ll
+++ b/llvm/test/CodeGen/AMDGPU/zero_extend.ll
@@ -1,6 +1,8 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -enable-var-scope --check-prefixes=GCN,SI %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope --check-prefixes=GCN,VI %s
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=GFX1250 %s
; R600: {{^}}s_mad_zext_i32_to_i64:
; R600: MEM_RAT_CACHELESS STORE_RAW
@@ -10,6 +12,60 @@
; GCN: v_mov_b32_e32 v[[V_ZERO:[0-9]]], 0{{$}}
; GCN: buffer_store_dwordx2 v[0:[[V_ZERO]]]
define amdgpu_kernel void @s_mad_zext_i32_to_i64(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) #0 {
+; SI-LABEL: s_mad_zext_i32_to_i64:
+; SI: ; %bb.0: ; %entry
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: v_mov_b32_e32 v1, 0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mul_i32 s0, s0, s1
+; SI-NEXT: s_add_i32 s0, s0, s2
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: s_mad_zext_i32_to_i64:
+; VI: ; %bb.0: ; %entry
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: v_mov_b32_e32 v1, 0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mul_i32 s0, s0, s1
+; VI-NEXT: s_add_i32 s0, s0, s2
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; VI-NEXT: s_endpgm
+;
+; R600-LABEL: s_mad_zext_i32_to_i64:
+; R600: ; %bb.0: ; %entry
+; R600-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+; R600-NEXT: ALU clause starting at 4:
+; R600-NEXT: MULLO_INT * T0.X, KC0[2].Z, KC0[2].W,
+; R600-NEXT: ADD_INT T0.X, PS, KC0[3].X,
+; R600-NEXT: MOV T0.Y, 0.0,
+; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX1250-LABEL: s_mad_zext_i32_to_i64:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
+; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_mul_i32 s0, s0, s1
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_add_co_i32 s0, s0, s2
+; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
+; GFX1250-NEXT: global_store_b64 v1, v[0:1], s[6:7]
+; GFX1250-NEXT: s_endpgm
entry:
%tmp0 = mul i32 %a, %b
%tmp1 = add i32 %tmp0, %c
@@ -21,6 +77,61 @@ entry:
; GCN-LABEL: {{^}}s_cmp_zext_i1_to_i32
; GCN: v_cndmask_b32
define amdgpu_kernel void @s_cmp_zext_i1_to_i32(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
+; SI-LABEL: s_cmp_zext_i1_to_i32:
+; SI: ; %bb.0: ; %entry
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
+; SI-NEXT: s_cmp_eq_u32 s4, s5
+; SI-NEXT: s_cselect_b64 s[4:5], -1, 0
+; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; SI-NEXT: s_cselect_b32 s4, 1, 0
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: s_cmp_zext_i1_to_i32:
+; VI: ; %bb.0: ; %entry
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b64 s[4:5], s[2:3]
+; VI-NEXT: s_cmp_eq_u32 s4, s5
+; VI-NEXT: s_cselect_b64 s[4:5], -1, 0
+; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; VI-NEXT: s_cselect_b32 s4, 1, 0
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
+;
+; R600-LABEL: s_cmp_zext_i1_to_i32:
+; R600: ; %bb.0: ; %entry
+; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+; R600-NEXT: ALU clause starting at 4:
+; R600-NEXT: SETE_INT * T0.W, KC0[2].Z, KC0[2].W,
+; R600-NEXT: AND_INT T0.X, PV.W, 1,
+; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX1250-LABEL: s_cmp_zext_i1_to_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_eq_u32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
entry:
%tmp0 = icmp eq i32 %a, %b
%tmp1 = zext i1 %tmp0 to i32
@@ -30,6 +141,60 @@ entry:
; GCN-LABEL: {{^}}s_arg_zext_i1_to_i64:
define amdgpu_kernel void @s_arg_zext_i1_to_i64(ptr addrspace(1) %out, i1 zeroext %arg) #0 {
+; SI-LABEL: s_arg_zext_i1_to_i64:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dword s6, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: v_mov_b32_e32 v1, 0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_and_b32 s4, s6, 1
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: s_arg_zext_i1_to_i64:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dword s6, s[4:5], 0x2c
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: v_mov_b32_e32 v1, 0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_and_b32 s4, s6, 1
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; VI-NEXT: s_endpgm
+;
+; R600-LABEL: s_arg_zext_i1_to_i64:
+; R600: ; %bb.0:
+; R600-NEXT: ALU 0, @8, KC0[], KC1[]
+; R600-NEXT: TEX 0 @6
+; R600-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]
+; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+; R600-NEXT: Fetch clause starting at 6:
+; R600-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3
+; R600-NEXT: ALU clause starting at 8:
+; R600-NEXT: MOV * T0.X, 0.0,
+; R600-NEXT: ALU clause starting at 9:
+; R600-NEXT: BFE_INT T0.X, T0.X, 0.0, 1,
+; R600-NEXT: MOV T0.Y, 0.0,
+; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX1250-LABEL: s_arg_zext_i1_to_i64:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_and_b32 s2, s2, 1
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
+; GFX1250-NEXT: global_store_b64 v1, v[0:1], s[0:1]
+; GFX1250-NEXT: s_endpgm
%ext = zext i1 %arg to i64
store i64 %ext, ptr addrspace(1) %out, align 8
ret void
@@ -40,6 +205,65 @@ define amdgpu_kernel void @s_arg_zext_i1_to_i64(ptr addrspace(1) %out, i1 zeroex
; GCN-DAG: s_cmp_eq_u32
; GCN: v_cndmask_b32
define amdgpu_kernel void @s_cmp_zext_i1_to_i64(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
+; SI-LABEL: s_cmp_zext_i1_to_i64:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
+; SI-NEXT: s_cmp_eq_u32 s4, s5
+; SI-NEXT: s_cselect_b64 s[4:5], -1, 0
+; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; SI-NEXT: s_cselect_b64 s[4:5], 1, 0
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: v_mov_b32_e32 v1, s5
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: s_cmp_zext_i1_to_i64:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b64 s[4:5], s[2:3]
+; VI-NEXT: s_cmp_eq_u32 s4, s5
+; VI-NEXT: s_cselect_b64 s[4:5], -1, 0
+; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; VI-NEXT: s_cselect_b64 s[4:5], 1, 0
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: v_mov_b32_e32 v1, s5
+; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; VI-NEXT: s_endpgm
+;
+; R600-LABEL: s_cmp_zext_i1_to_i64:
+; R600: ; %bb.0:
+; R600-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+; R600-NEXT: ALU clause starting at 4:
+; R600-NEXT: SETE_INT * T0.W, KC0[2].Z, KC0[2].W,
+; R600-NEXT: AND_INT T0.X, PV.W, 1,
+; R600-NEXT: MOV T0.Y, 0.0,
+; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX1250-LABEL: s_cmp_zext_i1_to_i64:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_cmp_eq_u32 s2, s3
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1250-NEXT: s_cselect_b64 s[2:3], 1, 0
+; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[2:3]
+; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX1250-NEXT: s_endpgm
%cmp = icmp eq i32 %a, %b
%ext = zext i1 %cmp to i64
store i64 %ext, ptr addrspace(1) %out, align 8
@@ -59,10 +283,472 @@ define amdgpu_kernel void @s_cmp_zext_i1_to_i64(ptr addrspace(1) %out, i32 %a, i
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CC]]
; GCN: buffer_store_short [[RESULT]]
define amdgpu_kernel void @s_cmp_zext_i1_to_i16(ptr addrspace(1) %out, [8 x i32], i16 zeroext %a, [8 x i32], i16 zeroext %b) #0 {
+; SI-LABEL: s_cmp_zext_i1_to_i16:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dword s6, s[4:5], 0x13
+; SI-NEXT: s_load_dword s7, s[4:5], 0x1c
+; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_and_b32 s4, s6, 0xffff
+; SI-NEXT: s_and_b32 s5, s7, 0xffff
+; SI-NEXT: s_cmp_eq_u32 s4, s5
+; SI-NEXT: s_cselect_b64 s[4:5], -1, 0
+; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; SI-NEXT: s_cselect_b32 s4, 1, 0
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: s_cmp_zext_i1_to_i16:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dword s6, s[4:5], 0x70
+; VI-NEXT: s_load_dword s7, s[4:5], 0x4c
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_and_b32 s4, s6, 0xffff
+; VI-NEXT: s_and_b32 s5, s7, 0xffff
+; VI-NEXT: s_cmp_eq_u32 s5, s4
+; VI-NEXT: s_cselect_b64 s[4:5], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
+; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
+;
+; R600-LABEL: s_cmp_zext_i1_to_i16:
+; R600: ; %bb.0:
+; R600-NEXT: ALU 0, @10, KC0[], KC1[]
+; R600-NEXT: TEX 1 @6
+; R600-NEXT: ALU 14, @11, KC0[CB0:0-32], KC1[]
+; R600-NEXT: MEM_RAT MSKOR T0.XW, T1.X
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+; R600-NEXT: Fetch clause starting at 6:
+; R600-NEXT: VTX_READ_16 T1.X, T0.X, 72, #3
+; R600-NEXT: VTX_READ_16 T0.X, T0.X, 108, #3
+; R600-NEXT: ALU clause starting at 10:
+; R600-NEXT: MOV * T0.X, 0.0,
+; R600-NEXT: ALU clause starting at 11:
+; R600-NEXT: BFE_INT T0.Z, T1.X, 0.0, literal.x,
+; R600-NEXT: BFE_INT T0.W, T0.X, 0.0, literal.x, BS:VEC_120/SCL_212
+; R600-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,
+; R600-NEXT: 16(2.242078e-44), 3(4.203895e-45)
+; R600-NEXT: SETE_INT * T0.W, PV.Z, PV.W,
+; R600-NEXT: AND_INT T0.W, PV.W, 1,
+; R600-NEXT: LSHL * T1.W, T1.W, literal.x,
+; R600-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; R600-NEXT: LSHL T0.X, PV.W, PS,
+; R600-NEXT: LSHL * T0.W, literal.x, PS,
+; R600-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; R600-NEXT: MOV T0.Y, 0.0,
+; R600-NEXT: MOV * T0.Z, 0.0,
+; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX1250-LABEL: s_cmp_zext_i1_to_i16:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_clause 0x2
+; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x70 nv
+; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x4c nv
+; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1250-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX1250-NEXT: s_and_b32 s3, s3, 0xffff
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_cmp_eq_u32 s3, s2
+; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
+; GFX1250-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
%tmp0 = icmp eq i16 %a, %b
%tmp1 = zext i1 %tmp0 to i16
store i16 %tmp1, ptr addrspace(1) %out
ret void
}
+; ============================================================================
+; Divergent i32 compares
+; ============================================================================
+
+define i32 @divergent_i32_eq_i32(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_eq_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GCN-LABEL: divergent_i32_eq_i32:
+; GCN: ; %bb.0: ; %entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; R600-LABEL: divergent_i32_eq_i32:
+; R600: ; %bb.0: ; %entry
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+;
+; GFX1250-LABEL: divergent_i32_eq_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp eq i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i64 @divergent_i32_eq_i64(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_eq_i64:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
+; GFX950-NEXT: v_mov_b32_e32 v1, 0
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GCN-LABEL: divergent_i32_eq_i64:
+; GCN: ; %bb.0: ; %entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; R600-LABEL: divergent_i32_eq_i64:
+; R600: ; %bb.0: ; %entry
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+;
+; GFX1250-LABEL: divergent_i32_eq_i64:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp eq i32 %a, %b
+ %zext = zext i1 %cmp to i64
+ ret i64 %zext
+}
+
+define i32 @divergent_i32_ne_i32(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_ne_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GCN-LABEL: divergent_i32_ne_i32:
+; GCN: ; %bb.0: ; %entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; R600-LABEL: divergent_i32_ne_i32:
+; R600: ; %bb.0: ; %entry
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+;
+; GFX1250-LABEL: divergent_i32_ne_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp ne i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @divergent_i32_ugt_i32(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_ugt_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_gt_u32_e32 vcc, v0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GCN-LABEL: divergent_i32_ugt_i32:
+; GCN: ; %bb.0: ; %entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cmp_gt_u32_e32 vcc, v0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; R600-LABEL: divergent_i32_ugt_i32:
+; R600: ; %bb.0: ; %entry
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+;
+; GFX1250-LABEL: divergent_i32_ugt_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp ugt i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @divergent_i32_uge_i32(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_uge_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GCN-LABEL: divergent_i32_uge_i32:
+; GCN: ; %bb.0: ; %entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; R600-LABEL: divergent_i32_uge_i32:
+; R600: ; %bb.0: ; %entry
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+;
+; GFX1250-LABEL: divergent_i32_uge_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp uge i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @divergent_i32_ult_i32(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_ult_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GCN-LABEL: divergent_i32_ult_i32:
+; GCN: ; %bb.0: ; %entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; R600-LABEL: divergent_i32_ult_i32:
+; R600: ; %bb.0: ; %entry
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+;
+; GFX1250-LABEL: divergent_i32_ult_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp ult i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @divergent_i32_ule_i32(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_ule_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_le_u32_e32 vcc, v0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GCN-LABEL: divergent_i32_ule_i32:
+; GCN: ; %bb.0: ; %entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, v0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; R600-LABEL: divergent_i32_ule_i32:
+; R600: ; %bb.0: ; %entry
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+;
+; GFX1250-LABEL: divergent_i32_ule_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_le_u32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp ule i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @divergent_i32_sgt_i32(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_sgt_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, v0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GCN-LABEL: divergent_i32_sgt_i32:
+; GCN: ; %bb.0: ; %entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cmp_gt_i32_e32 vcc, v0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; R600-LABEL: divergent_i32_sgt_i32:
+; R600: ; %bb.0: ; %entry
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+;
+; GFX1250-LABEL: divergent_i32_sgt_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp sgt i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @divergent_i32_sge_i32(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_sge_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GCN-LABEL: divergent_i32_sge_i32:
+; GCN: ; %bb.0: ; %entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; R600-LABEL: divergent_i32_sge_i32:
+; R600: ; %bb.0: ; %entry
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+;
+; GFX1250-LABEL: divergent_i32_sge_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_ge_i32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp sge i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @divergent_i32_slt_i32(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_slt_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GCN-LABEL: divergent_i32_slt_i32:
+; GCN: ; %bb.0: ; %entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; R600-LABEL: divergent_i32_slt_i32:
+; R600: ; %bb.0: ; %entry
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+;
+; GFX1250-LABEL: divergent_i32_slt_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp slt i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
+define i32 @divergent_i32_sle_i32(i32 %a, i32 %b) #0 {
+; GFX950-LABEL: divergent_i32_sle_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cmp_le_i32_e32 vcc, v0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GCN-LABEL: divergent_i32_sle_i32:
+; GCN: ; %bb.0: ; %entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cmp_le_i32_e32 vcc, v0, v1
+; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; R600-LABEL: divergent_i32_sle_i32:
+; R600: ; %bb.0: ; %entry
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+;
+; GFX1250-LABEL: divergent_i32_sle_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_cmp_le_i32_e32 vcc_lo, v0, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+entry:
+ %cmp = icmp sle i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ ret i32 %zext
+}
+
attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/AMDGPU/zero_extend_i1_to_i32_i64.ll b/llvm/test/CodeGen/AMDGPU/zero_extend_i1_to_i32_i64.ll
index 7fa407866dac9..7aef9c35cd745 100644
--- a/llvm/test/CodeGen/AMDGPU/zero_extend_i1_to_i32_i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/zero_extend_i1_to_i32_i64.ll
@@ -4,254 +4,6 @@
declare i32 @llvm.amdgcn.workitem.id.x() #0
-; ============================================================================
-; Divergent i32 compares
-; ============================================================================
-
-define i32 @divergent_i32_eq_i32(i32 %a, i32 %b) #0 {
-; GFX950-LABEL: divergent_i32_eq_i32:
-; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: divergent_i32_eq_i32:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1
-; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
-entry:
- %cmp = icmp eq i32 %a, %b
- %zext = zext i1 %cmp to i32
- ret i32 %zext
-}
-
-define i64 @divergent_i32_eq_i64(i32 %a, i32 %b) #0 {
-; GFX950-LABEL: divergent_i32_eq_i64:
-; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
-; GFX950-NEXT: v_mov_b32_e32 v1, 0
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: divergent_i32_eq_i64:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1
-; GFX1250-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
-entry:
- %cmp = icmp eq i32 %a, %b
- %zext = zext i1 %cmp to i64
- ret i64 %zext
-}
-
-define i32 @divergent_i32_ne_i32(i32 %a, i32 %b) #0 {
-; GFX950-LABEL: divergent_i32_ne_i32:
-; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: divergent_i32_ne_i32:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, v0, v1
-; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
-entry:
- %cmp = icmp ne i32 %a, %b
- %zext = zext i1 %cmp to i32
- ret i32 %zext
-}
-
-define i32 @divergent_i32_ugt_i32(i32 %a, i32 %b) #0 {
-; GFX950-LABEL: divergent_i32_ugt_i32:
-; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_cmp_gt_u32_e32 vcc, v0, v1
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: divergent_i32_ugt_i32:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v1
-; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
-entry:
- %cmp = icmp ugt i32 %a, %b
- %zext = zext i1 %cmp to i32
- ret i32 %zext
-}
-
-define i32 @divergent_i32_uge_i32(i32 %a, i32 %b) #0 {
-; GFX950-LABEL: divergent_i32_uge_i32:
-; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: divergent_i32_uge_i32:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v1
-; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
-entry:
- %cmp = icmp uge i32 %a, %b
- %zext = zext i1 %cmp to i32
- ret i32 %zext
-}
-
-define i32 @divergent_i32_ult_i32(i32 %a, i32 %b) #0 {
-; GFX950-LABEL: divergent_i32_ult_i32:
-; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: divergent_i32_ult_i32:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v1
-; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
-entry:
- %cmp = icmp ult i32 %a, %b
- %zext = zext i1 %cmp to i32
- ret i32 %zext
-}
-
-define i32 @divergent_i32_ule_i32(i32 %a, i32 %b) #0 {
-; GFX950-LABEL: divergent_i32_ule_i32:
-; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_cmp_le_u32_e32 vcc, v0, v1
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: divergent_i32_ule_i32:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_cmp_le_u32_e32 vcc_lo, v0, v1
-; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
-entry:
- %cmp = icmp ule i32 %a, %b
- %zext = zext i1 %cmp to i32
- ret i32 %zext
-}
-
-define i32 @divergent_i32_sgt_i32(i32 %a, i32 %b) #0 {
-; GFX950-LABEL: divergent_i32_sgt_i32:
-; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, v0, v1
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: divergent_i32_sgt_i32:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v1
-; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
-entry:
- %cmp = icmp sgt i32 %a, %b
- %zext = zext i1 %cmp to i32
- ret i32 %zext
-}
-
-define i32 @divergent_i32_sge_i32(i32 %a, i32 %b) #0 {
-; GFX950-LABEL: divergent_i32_sge_i32:
-; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: divergent_i32_sge_i32:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_cmp_ge_i32_e32 vcc_lo, v0, v1
-; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
-entry:
- %cmp = icmp sge i32 %a, %b
- %zext = zext i1 %cmp to i32
- ret i32 %zext
-}
-
-define i32 @divergent_i32_slt_i32(i32 %a, i32 %b) #0 {
-; GFX950-LABEL: divergent_i32_slt_i32:
-; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: divergent_i32_slt_i32:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v1
-; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
-entry:
- %cmp = icmp slt i32 %a, %b
- %zext = zext i1 %cmp to i32
- ret i32 %zext
-}
-
-define i32 @divergent_i32_sle_i32(i32 %a, i32 %b) #0 {
-; GFX950-LABEL: divergent_i32_sle_i32:
-; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_cmp_le_i32_e32 vcc, v0, v1
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: divergent_i32_sle_i32:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_cmp_le_i32_e32 vcc_lo, v0, v1
-; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
-entry:
- %cmp = icmp sle i32 %a, %b
- %zext = zext i1 %cmp to i32
- ret i32 %zext
-}
-
; ============================================================================
; Uniform i32 compares
; ============================================================================
@@ -568,114 +320,261 @@ entry:
; ============================================================================
-; AMDGPU_KERNEL ABI tests
+; AMDGPU_PS ABI tests
; ============================================================================
-; ----------------------------------------------------------------------------
-; Uniform i32 compares
-; ----------------------------------------------------------------------------
-define amdgpu_kernel void @kernel_uniform_i32_eq_i32(
-; GFX950-LABEL: kernel_uniform_i32_eq_i32:
+; To test divergent with amdgpu kernel ABI.
+define amdgpu_kernel void @kernel_divergent_i32_cmp_i32(ptr addrspace(1) %out, i1 %pred, i32 %a) #0 {
+; GFX950-LABEL: kernel_divergent_i32_cmp_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x30
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX950-NEXT: v_mov_b32_e32 v1, 0
; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_cmp_eq_u32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, s2, v0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v1, v0, s[0:1]
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i32_eq_i32:
+; GFX1250-LABEL: kernel_divergent_i32_cmp_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x30 nv
+; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1250-NEXT: v_mov_b32_e32 v1, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_cmp_eq_u32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, s2, v0
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX1250-NEXT: s_endpgm
- ptr addrspace(1) %out,
- i32 %a,
- i32 %b) #0 {
entry:
- %cmp = icmp eq i32 %a, %b
- %zext = zext i1 %cmp to i32
- store i32 %zext, ptr addrspace(1) %out
+ %workitem.id = call i32 @llvm.amdgcn.workitem.id.x()
+ %cmp = icmp eq i32 %a, %workitem.id
+ %tmp2 = zext i1 %cmp to i32
+ store i32 %tmp2, ptr addrspace(1) %out
ret void
}
-define amdgpu_kernel void @kernel_uniform_i32_eq_i64(
-; GFX950-LABEL: kernel_uniform_i32_eq_i64:
+; To test divergent zero i1 to i64 with amdgpu kernel ABI
+define amdgpu_kernel void @kernel_divergent_i64_cmp_i32(ptr addrspace(1) %out, i1 %pred, i32 %a) #0 {
+; GFX950-LABEL: kernel_divergent_i64_cmp_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x30
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_cmp_eq_u32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b64 s[2:3], 1, 0
-; GFX950-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
-; GFX950-NEXT: global_store_dwordx2 v0, v[2:3], s[0:1]
+; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, s2, v0
+; GFX950-NEXT: s_mov_b32 s2, 0
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i32_eq_i64:
+; GFX1250-LABEL: kernel_divergent_i64_cmp_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x30 nv
+; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1250-NEXT: s_mov_b32 s3, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_cmp_eq_u32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b64 s[2:3], 1, 0
-; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[2:3]
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, s2, v0
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1250-NEXT: s_endpgm
- ptr addrspace(1) %out,
- i32 %a,
- i32 %b) #0 {
entry:
- %cmp = icmp eq i32 %a, %b
- %zext = zext i1 %cmp to i64
- store i64 %zext, ptr addrspace(1) %out
+ %workitem.id = call i32 @llvm.amdgcn.workitem.id.x()
+ %cmp = icmp eq i32 %a, %workitem.id
+ %tmp2 = zext i1 %cmp to i64
+ store i64 %tmp2, ptr addrspace(1) %out
+ ret void
+}
+
+; To test divergent with amdgpu kernel ABI.
+define amdgpu_kernel void @zext_i1_to_i32_uniform(ptr addrspace(1) %out, i1 %pred, i32 %a) #0 {
+; GFX950-LABEL: zext_i1_to_i32_uniform:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x30
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX950-NEXT: v_mov_b32_e32 v1, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, s2, v0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: zext_i1_to_i32_uniform:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x30 nv
+; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1250-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, s2, v0
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX1250-NEXT: s_endpgm
+entry:
+ %workitem.id = call i32 @llvm.amdgcn.workitem.id.x()
+ %cmp = icmp eq i32 %a, %workitem.id
+ %tmp2 = zext i1 %cmp to i32
+ store i32 %tmp2, ptr addrspace(1) %out
ret void
}
-define amdgpu_kernel void @kernel_uniform_i32_ne_i32(
-; GFX950-LABEL: kernel_uniform_i32_ne_i32:
+; TO test zero_extend from i1 to 64 uniform
+define amdgpu_kernel void @zext_i1_to_i64_uniform(ptr addrspace(1) %out, i1 %pred, i32 %a, i32 %b) #0 {
+; GFX950-LABEL: zext_i1_to_i64_uniform:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x30
+; GFX950-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX950-NEXT: v_mov_b32_e32 v0, 0
; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_cmp_lg_u32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_cmp_eq_u32 s0, s1
+; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX950-NEXT: s_cselect_b64 s[0:1], 1, 0
+; GFX950-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-NEXT: global_store_dwordx2 v0, v[2:3], s[2:3]
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i32_ne_i32:
+; GFX1250-LABEL: zext_i1_to_i64_uniform:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x30 nv
+; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_cmp_lg_u32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1250-NEXT: s_cmp_eq_u32 s0, s1
+; GFX1250-NEXT: s_cselect_b32 s0, -1, 0
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1250-NEXT: s_cselect_b64 s[0:1], 1, 0
+; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
+; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[2:3]
+; GFX1250-NEXT: s_endpgm
+entry:
+ %cmp = icmp eq i32 %a, %b
+ %tmp2 = zext i1 %cmp to i64
+ store i64 %tmp2, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps i32 @zext_i1_to_i32_uniform_amdgpu_ps_abi(i32 inreg %a, i32 inreg %b) #0 {
+; GFX950-LABEL: zext_i1_to_i32_uniform_amdgpu_ps_abi:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: s_cmp_eq_u32 s0, s1
+; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX950-NEXT: s_cselect_b32 s0, 1, 0
+; GFX950-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: zext_i1_to_i32_uniform_amdgpu_ps_abi:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_cmp_eq_u32 s0, s1
+; GFX1250-NEXT: s_cselect_b32 s0, -1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1250-NEXT: ; return to shader part epilog
+entry:
+ %cmp = icmp eq i32 %a, %b
+ %tmp2 = zext i1 %cmp to i32
+ ret i32 %tmp2
+}
+
+; ----------------------------------------------------------------------------
+; Uniform i32 compares
+; ----------------------------------------------------------------------------
+
+define amdgpu_ps void @ps_uniform_i32_eq_i32(
+; GFX950-LABEL: ps_uniform_i32_eq_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: ps_uniform_i32_eq_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i32 %a,
+ i32 %b) #0 {
+entry:
+ %cmp = icmp eq i32 %a, %b
+ %zext = zext i1 %cmp to i32
+ store i32 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @ps_uniform_i32_eq_i64(
+; GFX950-LABEL: ps_uniform_i32_eq_i64:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
+; GFX950-NEXT: s_mov_b32 s0, 0
+; GFX950-NEXT: v_mov_b32_e32 v3, s0
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: ps_uniform_i32_eq_i64:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: s_mov_b32 s0, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_mov_b32_e32 v3, s0
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1250-NEXT: s_endpgm
+ ptr addrspace(1) %out,
+ i32 %a,
+ i32 %b) #0 {
+entry:
+ %cmp = icmp eq i32 %a, %b
+ %zext = zext i1 %cmp to i64
+ store i64 %zext, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @ps_uniform_i32_ne_i32(
+; GFX950-LABEL: ps_uniform_i32_ne_i32:
+; GFX950: ; %bb.0: ; %entry
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, v2, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
+; GFX950-NEXT: s_endpgm
+;
+; GFX1250-LABEL: ps_uniform_i32_ne_i32:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i32 %a,
@@ -687,32 +586,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i32_ugt_i32(
-; GFX950-LABEL: kernel_uniform_i32_ugt_i32:
+define amdgpu_ps void @ps_uniform_i32_ugt_i32(
+; GFX950-LABEL: ps_uniform_i32_ugt_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_cmp_gt_u32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_gt_u32_e32 vcc, v2, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i32_ugt_i32:
+; GFX1250-LABEL: ps_uniform_i32_ugt_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_cmp_gt_u32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_gt_u32_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i32 %a,
@@ -724,32 +612,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i32_uge_i32(
-; GFX950-LABEL: kernel_uniform_i32_uge_i32:
+define amdgpu_ps void @ps_uniform_i32_uge_i32(
+; GFX950-LABEL: ps_uniform_i32_uge_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_cmp_ge_u32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_ge_u32_e32 vcc, v2, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i32_uge_i32:
+; GFX1250-LABEL: ps_uniform_i32_uge_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_cmp_ge_u32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_ge_u32_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i32 %a,
@@ -761,32 +638,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i32_ult_i32(
-; GFX950-LABEL: kernel_uniform_i32_ult_i32:
+define amdgpu_ps void @ps_uniform_i32_ult_i32(
+; GFX950-LABEL: ps_uniform_i32_ult_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_cmp_lt_u32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_lt_u32_e32 vcc, v2, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i32_ult_i32:
+; GFX1250-LABEL: ps_uniform_i32_ult_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_cmp_lt_u32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i32 %a,
@@ -798,32 +664,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i32_ule_i32(
-; GFX950-LABEL: kernel_uniform_i32_ule_i32:
+define amdgpu_ps void @ps_uniform_i32_ule_i32(
+; GFX950-LABEL: ps_uniform_i32_ule_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_cmp_le_u32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_le_u32_e32 vcc, v2, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i32_ule_i32:
+; GFX1250-LABEL: ps_uniform_i32_ule_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_cmp_le_u32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_le_u32_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i32 %a,
@@ -835,32 +690,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i32_sgt_i32(
-; GFX950-LABEL: kernel_uniform_i32_sgt_i32:
+define amdgpu_ps void @ps_uniform_i32_sgt_i32(
+; GFX950-LABEL: ps_uniform_i32_sgt_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_cmp_gt_i32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, v2, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i32_sgt_i32:
+; GFX1250-LABEL: ps_uniform_i32_sgt_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_cmp_gt_i32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_gt_i32_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i32 %a,
@@ -872,32 +716,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i32_sge_i32(
-; GFX950-LABEL: kernel_uniform_i32_sge_i32:
+define amdgpu_ps void @ps_uniform_i32_sge_i32(
+; GFX950-LABEL: ps_uniform_i32_sge_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_cmp_ge_i32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_ge_i32_e32 vcc, v2, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i32_sge_i32:
+; GFX1250-LABEL: ps_uniform_i32_sge_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_cmp_ge_i32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_ge_i32_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i32 %a,
@@ -909,32 +742,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i32_slt_i32(
-; GFX950-LABEL: kernel_uniform_i32_slt_i32:
+define amdgpu_ps void @ps_uniform_i32_slt_i32(
+; GFX950-LABEL: ps_uniform_i32_slt_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_cmp_lt_i32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, v2, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i32_slt_i32:
+; GFX1250-LABEL: ps_uniform_i32_slt_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_cmp_lt_i32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i32 %a,
@@ -946,32 +768,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i32_sle_i32(
-; GFX950-LABEL: kernel_uniform_i32_sle_i32:
+define amdgpu_ps void @ps_uniform_i32_sle_i32(
+; GFX950-LABEL: ps_uniform_i32_sle_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_cmp_le_i32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_le_i32_e32 vcc, v2, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i32_sle_i32:
+; GFX1250-LABEL: ps_uniform_i32_sle_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_cmp_le_i32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_le_i32_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i32 %a,
@@ -987,38 +798,21 @@ entry:
; Uniform i16 compares
; ----------------------------------------------------------------------------
-define amdgpu_kernel void @kernel_uniform_i16_eq_i32(
-; GFX950-LABEL: kernel_uniform_i16_eq_i32:
+define amdgpu_ps void @ps_uniform_i16_eq_i32(
+; GFX950-LABEL: ps_uniform_i16_eq_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_lshr_b32 s3, s2, 16
-; GFX950-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX950-NEXT: s_cmp_eq_u32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, v2, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i16_eq_i32:
+; GFX1250-LABEL: ps_uniform_i16_eq_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_lshr_b32 s3, s2, 16
-; GFX1250-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_cmp_eq_u32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_eq_u16_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i16 %a,
@@ -1030,39 +824,25 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i16_eq_i64(
-; GFX950-LABEL: kernel_uniform_i16_eq_i64:
+define amdgpu_ps void @ps_uniform_i16_eq_i64(
+; GFX950-LABEL: ps_uniform_i16_eq_i64:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_lshr_b32 s3, s2, 16
-; GFX950-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX950-NEXT: s_cmp_eq_u32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b64 s[2:3], 1, 0
-; GFX950-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
-; GFX950-NEXT: global_store_dwordx2 v0, v[2:3], s[0:1]
+; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, v2, v3
+; GFX950-NEXT: s_mov_b32 s0, 0
+; GFX950-NEXT: v_mov_b32_e32 v3, s0
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i16_eq_i64:
+; GFX1250-LABEL: ps_uniform_i16_eq_i64:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_mov_b32_e32 v2, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_lshr_b32 s3, s2, 16
-; GFX1250-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_cmp_eq_u32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b64 s[2:3], 1, 0
+; GFX1250-NEXT: v_cmp_eq_u16_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: s_mov_b32 s0, 0
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[2:3]
-; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX1250-NEXT: v_mov_b32_e32 v3, s0
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i16 %a,
@@ -1074,38 +854,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i16_ne_i32(
-; GFX950-LABEL: kernel_uniform_i16_ne_i32:
+define amdgpu_ps void @ps_uniform_i16_ne_i32(
+; GFX950-LABEL: ps_uniform_i16_ne_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_lshr_b32 s3, s2, 16
-; GFX950-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX950-NEXT: s_cmp_lg_u32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, v2, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i16_ne_i32:
+; GFX1250-LABEL: ps_uniform_i16_ne_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_lshr_b32 s3, s2, 16
-; GFX1250-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_cmp_lg_u32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_ne_u16_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i16 %a,
@@ -1117,38 +880,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i16_ugt_i32(
-; GFX950-LABEL: kernel_uniform_i16_ugt_i32:
+define amdgpu_ps void @ps_uniform_i16_ugt_i32(
+; GFX950-LABEL: ps_uniform_i16_ugt_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_lshr_b32 s3, s2, 16
-; GFX950-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX950-NEXT: s_cmp_gt_u32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_gt_u16_e32 vcc, v2, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i16_ugt_i32:
+; GFX1250-LABEL: ps_uniform_i16_ugt_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_lshr_b32 s3, s2, 16
-; GFX1250-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_cmp_gt_u32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_gt_u16_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i16 %a,
@@ -1160,38 +906,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i16_uge_i32(
-; GFX950-LABEL: kernel_uniform_i16_uge_i32:
+define amdgpu_ps void @ps_uniform_i16_uge_i32(
+; GFX950-LABEL: ps_uniform_i16_uge_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_lshr_b32 s3, s2, 16
-; GFX950-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX950-NEXT: s_cmp_ge_u32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_ge_u16_e32 vcc, v2, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i16_uge_i32:
+; GFX1250-LABEL: ps_uniform_i16_uge_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_lshr_b32 s3, s2, 16
-; GFX1250-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_cmp_ge_u32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_ge_u16_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i16 %a,
@@ -1203,38 +932,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i16_ult_i32(
-; GFX950-LABEL: kernel_uniform_i16_ult_i32:
+define amdgpu_ps void @ps_uniform_i16_ult_i32(
+; GFX950-LABEL: ps_uniform_i16_ult_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_lshr_b32 s3, s2, 16
-; GFX950-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX950-NEXT: s_cmp_lt_u32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_lt_u16_e32 vcc, v2, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i16_ult_i32:
+; GFX1250-LABEL: ps_uniform_i16_ult_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_lshr_b32 s3, s2, 16
-; GFX1250-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_cmp_lt_u32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_lt_u16_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i16 %a,
@@ -1246,38 +958,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i16_ule_i32(
-; GFX950-LABEL: kernel_uniform_i16_ule_i32:
+define amdgpu_ps void @ps_uniform_i16_ule_i32(
+; GFX950-LABEL: ps_uniform_i16_ule_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_lshr_b32 s3, s2, 16
-; GFX950-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX950-NEXT: s_cmp_le_u32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_le_u16_e32 vcc, v2, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i16_ule_i32:
+; GFX1250-LABEL: ps_uniform_i16_ule_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_lshr_b32 s3, s2, 16
-; GFX1250-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_cmp_le_u32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_le_u16_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i16 %a,
@@ -1289,38 +984,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i16_sgt_i32(
-; GFX950-LABEL: kernel_uniform_i16_sgt_i32:
+define amdgpu_ps void @ps_uniform_i16_sgt_i32(
+; GFX950-LABEL: ps_uniform_i16_sgt_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_ashr_i32 s3, s2, 16
-; GFX950-NEXT: s_sext_i32_i16 s2, s2
-; GFX950-NEXT: s_cmp_gt_i32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, v2, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i16_sgt_i32:
+; GFX1250-LABEL: ps_uniform_i16_sgt_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_ashr_i32 s3, s2, 16
-; GFX1250-NEXT: s_sext_i32_i16 s2, s2
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_cmp_gt_i32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_gt_i16_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i16 %a,
@@ -1332,38 +1010,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i16_sge_i32(
-; GFX950-LABEL: kernel_uniform_i16_sge_i32:
+define amdgpu_ps void @ps_uniform_i16_sge_i32(
+; GFX950-LABEL: ps_uniform_i16_sge_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_ashr_i32 s3, s2, 16
-; GFX950-NEXT: s_sext_i32_i16 s2, s2
-; GFX950-NEXT: s_cmp_ge_i32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_ge_i16_e32 vcc, v2, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i16_sge_i32:
+; GFX1250-LABEL: ps_uniform_i16_sge_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_ashr_i32 s3, s2, 16
-; GFX1250-NEXT: s_sext_i32_i16 s2, s2
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_cmp_ge_i32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_ge_i16_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i16 %a,
@@ -1375,38 +1036,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i16_slt_i32(
-; GFX950-LABEL: kernel_uniform_i16_slt_i32:
+define amdgpu_ps void @ps_uniform_i16_slt_i32(
+; GFX950-LABEL: ps_uniform_i16_slt_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_ashr_i32 s3, s2, 16
-; GFX950-NEXT: s_sext_i32_i16 s2, s2
-; GFX950-NEXT: s_cmp_lt_i32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, v2, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i16_slt_i32:
+; GFX1250-LABEL: ps_uniform_i16_slt_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_ashr_i32 s3, s2, 16
-; GFX1250-NEXT: s_sext_i32_i16 s2, s2
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_cmp_lt_i32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_lt_i16_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i16 %a,
@@ -1418,38 +1062,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i16_sle_i32(
-; GFX950-LABEL: kernel_uniform_i16_sle_i32:
+define amdgpu_ps void @ps_uniform_i16_sle_i32(
+; GFX950-LABEL: ps_uniform_i16_sle_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_ashr_i32 s3, s2, 16
-; GFX950-NEXT: s_sext_i32_i16 s2, s2
-; GFX950-NEXT: s_cmp_le_i32 s2, s3
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_le_i16_e32 vcc, v2, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i16_sle_i32:
+; GFX1250-LABEL: ps_uniform_i16_sle_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_ashr_i32 s3, s2, 16
-; GFX1250-NEXT: s_sext_i32_i16 s2, s2
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_cmp_le_i32 s2, s3
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_le_i16_e32 vcc_lo, v2, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i16 %a,
@@ -1465,32 +1092,21 @@ entry:
; Divergent i64 compares
; ----------------------------------------------------------------------------
-define amdgpu_kernel void @kernel_i64_eq_i32(
-; GFX950-LABEL: kernel_i64_eq_i32:
+define amdgpu_ps void @ps_i64_eq_i32(
+; GFX950-LABEL: ps_i64_eq_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[2:3]
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[4:5]
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_i64_eq_i32:
+; GFX1250-LABEL: ps_i64_eq_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
-; GFX1250-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i64 %a,
@@ -1502,34 +1118,25 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_i64_eq_i64(
-; GFX950-LABEL: kernel_i64_eq_i64:
+define amdgpu_ps void @ps_i64_eq_i64(
+; GFX950-LABEL: ps_i64_eq_i64:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX950-NEXT: s_mov_b32 s4, 0
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s4
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[2:3]
-; GFX950-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX950-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[4:5]
+; GFX950-NEXT: s_mov_b32 s0, 0
+; GFX950-NEXT: v_mov_b32_e32 v3, s0
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_i64_eq_i64:
+; GFX1250-LABEL: ps_i64_eq_i64:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
-; GFX1250-NEXT: s_mov_b32 s2, 0
-; GFX1250-NEXT: s_cselect_b32 s3, -1, 0
-; GFX1250-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, s3
-; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX1250-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX1250-NEXT: s_mov_b32 s0, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_mov_b32_e32 v3, s0
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i64 %a,
@@ -1541,32 +1148,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_i64_ne_i32(
-; GFX950-LABEL: kernel_i64_ne_i32:
+define amdgpu_ps void @ps_i64_ne_i32(
+; GFX950-LABEL: ps_i64_ne_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_cmp_lg_u64 s[2:3], s[6:7]
-; GFX950-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX950-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[2:3]
-; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: v_cmp_ne_u64_e32 vcc, v[2:3], v[4:5]
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_i64_ne_i32:
+; GFX1250-LABEL: ps_i64_ne_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
-; GFX1250-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_cmp_lg_u64 s[2:3], s[6:7]
-; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i64 %a,
@@ -1578,32 +1174,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_i64_ugt_i32(
-; GFX950-LABEL: kernel_i64_ugt_i32:
+define amdgpu_ps void @ps_i64_ugt_i32(
+; GFX950-LABEL: ps_i64_ugt_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
-; GFX950-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1]
+; GFX950-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[4:5]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_i64_ugt_i32:
+; GFX1250-LABEL: ps_i64_ugt_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
-; GFX1250-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_cmp_gt_u64_e64 s2, s[2:3], s[6:7]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i64 %a,
@@ -1615,32 +1200,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_i64_uge_i32(
-; GFX950-LABEL: kernel_i64_uge_i32:
+define amdgpu_ps void @ps_i64_uge_i32(
+; GFX950-LABEL: ps_i64_uge_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
-; GFX950-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[0:1]
+; GFX950-NEXT: v_cmp_ge_u64_e32 vcc, v[2:3], v[4:5]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_i64_uge_i32:
+; GFX1250-LABEL: ps_i64_uge_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
-; GFX1250-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_cmp_ge_u64_e64 s2, s[2:3], s[6:7]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_ge_u64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i64 %a,
@@ -1652,32 +1226,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_i64_ult_i32(
-; GFX950-LABEL: kernel_i64_ult_i32:
+define amdgpu_ps void @ps_i64_ult_i32(
+; GFX950-LABEL: ps_i64_ult_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
-; GFX950-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1]
+; GFX950-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[4:5]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_i64_ult_i32:
+; GFX1250-LABEL: ps_i64_ult_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
-; GFX1250-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_cmp_lt_u64_e64 s2, s[2:3], s[6:7]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i64 %a,
@@ -1689,32 +1252,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i64_ule_i32(
-; GFX950-LABEL: kernel_uniform_i64_ule_i32:
+define amdgpu_ps void @ps_uniform_i64_ule_i32(
+; GFX950-LABEL: ps_uniform_i64_ule_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
-; GFX950-NEXT: v_cmp_le_u64_e32 vcc, s[2:3], v[0:1]
+; GFX950-NEXT: v_cmp_le_u64_e32 vcc, v[2:3], v[4:5]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i64_ule_i32:
+; GFX1250-LABEL: ps_uniform_i64_ule_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
-; GFX1250-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_cmp_le_u64_e64 s2, s[2:3], s[6:7]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_le_u64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i64 %a,
@@ -1726,32 +1278,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i64_sgt_i32(
-; GFX950-LABEL: kernel_uniform_i64_sgt_i32:
+define amdgpu_ps void @ps_uniform_i64_sgt_i32(
+; GFX950-LABEL: ps_uniform_i64_sgt_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
-; GFX950-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
+; GFX950-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[4:5]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i64_sgt_i32:
+; GFX1250-LABEL: ps_uniform_i64_sgt_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
-; GFX1250-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_cmp_gt_i64_e64 s2, s[2:3], s[6:7]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i64 %a,
@@ -1763,32 +1304,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i64_sge_i32(
-; GFX950-LABEL: kernel_uniform_i64_sge_i32:
+define amdgpu_ps void @ps_uniform_i64_sge_i32(
+; GFX950-LABEL: ps_uniform_i64_sge_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
-; GFX950-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[0:1]
+; GFX950-NEXT: v_cmp_ge_i64_e32 vcc, v[2:3], v[4:5]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i64_sge_i32:
+; GFX1250-LABEL: ps_uniform_i64_sge_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
-; GFX1250-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_cmp_ge_i64_e64 s2, s[2:3], s[6:7]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_ge_i64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i64 %a,
@@ -1800,32 +1330,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i64_slt_i32(
-; GFX950-LABEL: kernel_uniform_i64_slt_i32:
+define amdgpu_ps void @ps_uniform_i64_slt_i32(
+; GFX950-LABEL: ps_uniform_i64_slt_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
-; GFX950-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
+; GFX950-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[4:5]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i64_slt_i32:
+; GFX1250-LABEL: ps_uniform_i64_slt_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
-; GFX1250-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_cmp_lt_i64_e64 s2, s[2:3], s[6:7]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i64 %a,
@@ -1837,32 +1356,21 @@ entry:
ret void
}
-define amdgpu_kernel void @kernel_uniform_i64_sle_i32(
-; GFX950-LABEL: kernel_uniform_i64_sle_i32:
+define amdgpu_ps void @ps_uniform_i64_sle_i32(
+; GFX950-LABEL: ps_uniform_i64_sle_i32:
; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
-; GFX950-NEXT: v_cmp_le_i64_e32 vcc, s[2:3], v[0:1]
+; GFX950-NEXT: v_cmp_le_i64_e32 vcc, v[2:3], v[4:5]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: global_store_dword v[0:1], v2, off
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: kernel_uniform_i64_sle_i32:
+; GFX1250-LABEL: ps_uniform_i64_sle_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34 nv
-; GFX1250-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_cmp_le_i64_e64 s2, s[2:3], s[6:7]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-NEXT: v_cmp_le_i64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
ptr addrspace(1) %out,
i64 %a,
@@ -1873,180 +1381,3 @@ entry:
store i32 %zext, ptr addrspace(1) %out
ret void
}
-
-
-; To test divergent with amdgpu kernel ABI.
-define amdgpu_kernel void @kernel_divergent_i32_cmp_i32(ptr addrspace(1) %out, i1 %pred, i32 %a) #0 {
-; GFX950-LABEL: kernel_divergent_i32_cmp_i32:
-; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dword s2, s[4:5], 0x30
-; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX950-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX950-NEXT: v_mov_b32_e32 v1, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, s2, v0
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: global_store_dword v1, v0, s[0:1]
-; GFX950-NEXT: s_endpgm
-;
-; GFX1250-LABEL: kernel_divergent_i32_cmp_i32:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x30 nv
-; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX1250-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, s2, v0
-; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX1250-NEXT: s_endpgm
-entry:
- %workitem.id = call i32 @llvm.amdgcn.workitem.id.x()
- %cmp = icmp eq i32 %a, %workitem.id
- %tmp2 = zext i1 %cmp to i32
- store i32 %tmp2, ptr addrspace(1) %out
- ret void
-}
-
-; To test divergent zero i1 to i64 with amdgpu kernel ABI
-define amdgpu_kernel void @kernel_divergent_i64_cmp_i32(ptr addrspace(1) %out, i1 %pred, i32 %a) #0 {
-; GFX950-LABEL: kernel_divergent_i64_cmp_i32:
-; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dword s2, s[4:5], 0x30
-; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX950-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, s2, v0
-; GFX950-NEXT: s_mov_b32 s2, 0
-; GFX950-NEXT: v_mov_b32_e32 v1, s2
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX950-NEXT: s_endpgm
-;
-; GFX1250-LABEL: kernel_divergent_i64_cmp_i32:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x30 nv
-; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX1250-NEXT: s_mov_b32 s3, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1250-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, s2, v0
-; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX1250-NEXT: s_endpgm
-entry:
- %workitem.id = call i32 @llvm.amdgcn.workitem.id.x()
- %cmp = icmp eq i32 %a, %workitem.id
- %tmp2 = zext i1 %cmp to i64
- store i64 %tmp2, ptr addrspace(1) %out
- ret void
-}
-
-; To test divergent with amdgpu kernel ABI.
-define amdgpu_kernel void @zext_i1_to_i32_uniform(ptr addrspace(1) %out, i1 %pred, i32 %a) #0 {
-; GFX950-LABEL: zext_i1_to_i32_uniform:
-; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dword s2, s[4:5], 0x30
-; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX950-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX950-NEXT: v_mov_b32_e32 v1, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, s2, v0
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT: global_store_dword v1, v0, s[0:1]
-; GFX950-NEXT: s_endpgm
-;
-; GFX1250-LABEL: zext_i1_to_i32_uniform:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x30 nv
-; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX1250-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, s2, v0
-; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX1250-NEXT: s_endpgm
-entry:
- %workitem.id = call i32 @llvm.amdgcn.workitem.id.x()
- %cmp = icmp eq i32 %a, %workitem.id
- %tmp2 = zext i1 %cmp to i32
- store i32 %tmp2, ptr addrspace(1) %out
- ret void
-}
-
-; TO test zero_extend from i1 to 64 uniform
-define amdgpu_kernel void @zext_i1_to_i64_uniform(ptr addrspace(1) %out, i1 %pred, i32 %a, i32 %b) #0 {
-; GFX950-LABEL: zext_i1_to_i64_uniform:
-; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x30
-; GFX950-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_cmp_eq_u32 s0, s1
-; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
-; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; GFX950-NEXT: s_cselect_b64 s[0:1], 1, 0
-; GFX950-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-NEXT: global_store_dwordx2 v0, v[2:3], s[2:3]
-; GFX950-NEXT: s_endpgm
-;
-; GFX1250-LABEL: zext_i1_to_i64_uniform:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x30 nv
-; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_mov_b32_e32 v2, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_cmp_eq_u32 s0, s1
-; GFX1250-NEXT: s_cselect_b32 s0, -1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_and_b32 s0, s0, exec_lo
-; GFX1250-NEXT: s_cselect_b64 s[0:1], 1, 0
-; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
-; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[2:3]
-; GFX1250-NEXT: s_endpgm
-entry:
- %cmp = icmp eq i32 %a, %b
- %tmp2 = zext i1 %cmp to i64
- store i64 %tmp2, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_ps i32 @zext_i1_to_i32_uniform_amdgpu_ps_abi(i32 inreg %a, i32 inreg %b) #0 {
-; GFX950-LABEL: zext_i1_to_i32_uniform_amdgpu_ps_abi:
-; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_cmp_eq_u32 s0, s1
-; GFX950-NEXT: s_cselect_b64 s[0:1], -1, 0
-; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; GFX950-NEXT: s_cselect_b32 s0, 1, 0
-; GFX950-NEXT: ; return to shader part epilog
-;
-; GFX1250-LABEL: zext_i1_to_i32_uniform_amdgpu_ps_abi:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_cmp_eq_u32 s0, s1
-; GFX1250-NEXT: s_cselect_b32 s0, -1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: s_and_b32 s0, s0, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
-; GFX1250-NEXT: ; return to shader part epilog
-entry:
- %cmp = icmp eq i32 %a, %b
- %tmp2 = zext i1 %cmp to i32
- ret i32 %tmp2
-}
>From 040375168a312b51606d09a6cd3af7ebf047f3ae Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Thu, 21 May 2026 06:16:05 +0000
Subject: [PATCH 24/29] comments
---
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 3 +--
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 7 +++++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index ce0e7b73cdfb9..a867ddfc600a2 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -179,8 +179,7 @@ void InstrEmitter::EmitCopyFromReg(SDValue Op, bool IsClone, Register SrcReg,
DstRC = SrcRC;
// If all uses are reading from the src physical register and copying the
- // register is either impossible or very expensive, then don't create a
- // copy.
+ // register is either impossible or very expensive, then don't create a copy.
if (MatchReg && SrcRC->expensiveOrImpossibleToCopy()) {
VRBase = SrcReg;
} else {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 838a46878d609..a74656888a5e8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -355,8 +355,11 @@ bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
SDValue Chain = CurDAG->getEntryNode(); // Basic chain to anchor the copy
SDValue CopyToSCC =
CurDAG->getCopyToReg(Chain, DL, AMDGPU::SCC, CondNode, SDValue());
- SDValue Ops[4] = {TrueValue, FalseValue, CopyToSCC.getValue(1),
- CopyToSCC.getValue(1)};
+ SDValue Ops[4] = {
+ TrueValue, FalseValue,
+ CopyToSCC.getValue(1), // Explicitly state SCC is read
+ CopyToSCC.getValue(2) // Glue
+ };
bool IsInt32 = ResType == MVT::i32;
unsigned SelectCode = IsInt32 ? AMDGPU::S_CSELECT_B32 : AMDGPU::S_CSELECT_B64;
MachineSDNode *CSelectNode = CurDAG->getMachineNode(
>From 8039fc571f2850e99f885825f48e63983f16e7b5 Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Thu, 21 May 2026 06:29:33 +0000
Subject: [PATCH 25/29] comments
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index a74656888a5e8..efe9eb0dd940f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -357,8 +357,8 @@ bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
CurDAG->getCopyToReg(Chain, DL, AMDGPU::SCC, CondNode, SDValue());
SDValue Ops[4] = {
TrueValue, FalseValue,
- CopyToSCC.getValue(1), // Explicitly state SCC is read
- CopyToSCC.getValue(2) // Glue
+ CurDAG->getRegister(AMDGPU::SCC, MVT::i1), // Explicitly state SCC is read
+ CopyToSCC.getValue(1) // Glue
};
bool IsInt32 = ResType == MVT::i32;
unsigned SelectCode = IsInt32 ? AMDGPU::S_CSELECT_B32 : AMDGPU::S_CSELECT_B64;
>From f9ac002a7cf27222faad60a2a29a73530efad996 Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Thu, 21 May 2026 18:16:29 +0000
Subject: [PATCH 26/29] redundant cleanup
---
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 6 ------
1 file changed, 6 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index a867ddfc600a2..2ec959f392738 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -159,12 +159,6 @@ void InstrEmitter::EmitCopyFromReg(SDValue Op, bool IsClone, Register SrcReg,
UseRC = CommonSubClass;
}
- if (!UseRC || !UseRC->isAllocatable())
- UseRC = RegClassForVT;
- else if (const TargetRegisterClass *CommonSubClass =
- TRI->getCommonSubClass(UseRC, RegClassForVT))
- UseRC = CommonSubClass;
-
const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
>From d0a2697520a29c7357288db7f96ab965923d619e Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Thu, 28 May 2026 04:36:13 +0000
Subject: [PATCH 27/29] comments
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index efe9eb0dd940f..1720d994d49a2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -326,10 +326,8 @@ bool AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(SDNode *N) const {
}
bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
- // This is special case for common pattern of compare + select if it can be
+ // This is special case for zext from setcc if it can be
// selected to SALU. The pattern will be directly selected to `s_cselect`, to
- // This is special case for the common pattern of compare + select if it can
- // be selected to SALU. The pattern will be directly selected to `s_cselect`,
// to avoid an intermediate i1 virtual register which will be interpreted as a
// lane mask.
if (N->isDivergent())
@@ -360,10 +358,11 @@ bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
CurDAG->getRegister(AMDGPU::SCC, MVT::i1), // Explicitly state SCC is read
CopyToSCC.getValue(1) // Glue
};
- bool IsInt32 = ResType == MVT::i32;
- unsigned SelectCode = IsInt32 ? AMDGPU::S_CSELECT_B32 : AMDGPU::S_CSELECT_B64;
- MachineSDNode *CSelectNode = CurDAG->getMachineNode(
- SelectCode, DL, CurDAG->getVTList(IsInt32 ? MVT::i32 : MVT::i64), Ops);
+
+ unsigned SelectCode =
+ ResType == MVT::i32 ? AMDGPU::S_CSELECT_B32 : AMDGPU::S_CSELECT_B64;
+ MachineSDNode *CSelectNode =
+ CurDAG->getMachineNode(SelectCode, DL, CurDAG->getVTList(ResType), Ops);
CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), SDValue(CSelectNode, 0));
return true;
>From 9295530ce379e9938843fe2ffd3284a0e71afb81 Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Thu, 28 May 2026 04:40:41 +0000
Subject: [PATCH 28/29] comments
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 1720d994d49a2..bc1387c479273 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -327,7 +327,7 @@ bool AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(SDNode *N) const {
bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
// This is special case for zext from setcc if it can be
- // selected to SALU. The pattern will be directly selected to `s_cselect`, to
+ // selected to SALU. The pattern will be directly selected to `s_cselect`,
// to avoid an intermediate i1 virtual register which will be interpreted as a
// lane mask.
if (N->isDivergent())
>From 2ea3bb4998bfed497ecc370fd357781efbe7e834 Mon Sep 17 00:00:00 2001
From: Zeng Wu <zengwu13 at amd.com>
Date: Fri, 29 May 2026 08:52:11 -0700
Subject: [PATCH 29/29] Update llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index bc1387c479273..cabb9f7c37163 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -342,7 +342,7 @@ bool AMDGPUDAGToDAGISel::preprocessZeroExtend(SDNode *N) const {
return false;
// TODO: To support the operand type is int64 if s_cmp_i64 is supported on
- // some targets
+ // TODO: Support i64 if s_cmp_i64 is available
if (CondNode->getOperand(0).getValueType() != MVT::i32)
return false;
More information about the llvm-commits
mailing list