[llvm] [AArch64][llvm] POE2: remove TPMAXn_ELn/TPMINn_ELn and create TPCRn_ELn registers (PR #200428)
Jonathan Thackray via llvm-commits
llvm-commits at lists.llvm.org
Fri May 29 08:07:41 PDT 2026
https://github.com/jthackray created https://github.com/llvm/llvm-project/pull/200428
Some POE2 system registers have been removed/created:
* `TPMAXn_ELn`/`TPMINn_ELn` system registers are now removed
* these encodings are reused in new `TPCRn_ELn` system registers
Adjusted testcases as appropriate.
>From 2d2f3d623b80cc4150a5d1293edb86ab74c2f320 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray <jonathan.thackray at arm.com>
Date: Mon, 11 May 2026 14:01:39 +0100
Subject: [PATCH] [AArch64][llvm] POE2: remove TPMAXn_ELn/TPMINn_ELn and create
TPCRn_ELn registers
Some POE2 system registers have been removed/created:
* `TPMAXn_ELn`/`TPMINn_ELn` system registers are now removed
* these encodings are reused in new `TPCRn_ELn` system registers
Adjusted testcases as appropriate.
---
.../Target/AArch64/AArch64SystemOperands.td | 13 +-
llvm/test/MC/AArch64/arm-poe2.s | 176 +++++-------------
2 files changed, 52 insertions(+), 137 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 5824bd9009257..ffbc3811194f2 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -2822,16 +2822,11 @@ def : RWSysReg<"NVHCRXMASK_EL2", 0b1, 0b100, 0b0001, 0b0101, 0b101>;
// S1POE2 Thread private state extension (FEAT_TPS/TPSP).
foreach n = 0-1 in {
- defvar nb = !cast<bits<1>>(n);
// Op0 Op1 CRn CRm Op2
- def : RWSysReg<"TPMIN"#n#"_EL0", 0b1, 0b011, 0b0010, 0b0010, {0b1,nb,0}>;
- def : RWSysReg<"TPMAX"#n#"_EL0", 0b1, 0b011, 0b0010, 0b0010, {0b1,nb,1}>;
- def : RWSysReg<"TPMIN"#n#"_EL1", 0b1, 0b000, 0b0010, 0b0010, {0b1,nb,0}>;
- def : RWSysReg<"TPMAX"#n#"_EL1", 0b1, 0b000, 0b0010, 0b0010, {0b1,nb,1}>;
- def : RWSysReg<"TPMIN"#n#"_EL2", 0b1, 0b100, 0b0010, 0b0010, {0b1,nb,0}>;
- def : RWSysReg<"TPMAX"#n#"_EL2", 0b1, 0b100, 0b0010, 0b0010, {0b1,nb,1}>;
- def : RWSysReg<"TPMIN"#n#"_EL12", 0b1, 0b101, 0b0010, 0b0010, {0b1,nb,0}>;
- def : RWSysReg<"TPMAX"#n#"_EL12", 0b1, 0b101, 0b0010, 0b0010, {0b1,nb,1}>;
+ def : RWSysReg<"TPCR"#n#"_EL0", 0b1, 0b011, 0b0010, 0b0010, {0b10,n}>;
+ def : RWSysReg<"TPCR"#n#"_EL1", 0b1, 0b000, 0b0010, 0b0010, {0b10,n}>;
+ def : RWSysReg<"TPCR"#n#"_EL2", 0b1, 0b100, 0b0010, 0b0010, {0b10,n}>;
+ def : RWSysReg<"TPCR"#n#"_EL12", 0b1, 0b101, 0b0010, 0b0010, {0b10,n}>;
}
class PLBIEntry<bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2, string name,
diff --git a/llvm/test/MC/AArch64/arm-poe2.s b/llvm/test/MC/AArch64/arm-poe2.s
index b9aa734cf5b68..dbed9ba599067 100644
--- a/llvm/test/MC/AArch64/arm-poe2.s
+++ b/llvm/test/MC/AArch64/arm-poe2.s
@@ -1372,85 +1372,45 @@ mrs x0, AFGDTP15_EL3
// CHECK-ENCODING: encoding: [0xe0,0x37,0x3e,0xd5]
// CHECK-UNKNOWN: d53e37e0 mrs x0, AFGDTP15_EL3
-mrs x2, TPMIN0_EL0
-// CHECK-INST: mrs x2, TPMIN0_EL0
+mrs x2, TPCR0_EL0
+// CHECK-INST: mrs x2, TPCR0_EL0
// CHECK-ENCODING: encoding: [0x82,0x22,0x3b,0xd5]
-// CHECK-UNKNOWN: d53b2282 mrs x2, TPMIN0_EL0
+// CHECK-UNKNOWN: d53b2282 mrs x2, TPCR0_EL0
-mrs x2, TPMAX0_EL0
-// CHECK-INST: mrs x2, TPMAX0_EL0
+mrs x2, TPCR1_EL0
+// CHECK-INST: mrs x2, TPCR1_EL0
// CHECK-ENCODING: encoding: [0xa2,0x22,0x3b,0xd5]
-// CHECK-UNKNOWN: d53b22a2 mrs x2, TPMAX0_EL0
+// CHECK-UNKNOWN: d53b22a2 mrs x2, TPCR1_EL0
-mrs x2, TPMIN1_EL0
-// CHECK-INST: mrs x2, TPMIN1_EL0
-// CHECK-ENCODING: encoding: [0xc2,0x22,0x3b,0xd5]
-// CHECK-UNKNOWN: d53b22c2 mrs x2, TPMIN1_EL0
-
-mrs x2, TPMAX1_EL0
-// CHECK-INST: mrs x2, TPMAX1_EL0
-// CHECK-ENCODING: encoding: [0xe2,0x22,0x3b,0xd5]
-// CHECK-UNKNOWN: d53b22e2 mrs x2, TPMAX1_EL0
-
-mrs x2, TPMIN0_EL1
-// CHECK-INST: mrs x2, TPMIN0_EL1
+mrs x2, TPCR0_EL1
+// CHECK-INST: mrs x2, TPCR0_EL1
// CHECK-ENCODING: encoding: [0x82,0x22,0x38,0xd5]
-// CHECK-UNKNOWN: d5382282 mrs x2, TPMIN0_EL1
+// CHECK-UNKNOWN: d5382282 mrs x2, TPCR0_EL1
-mrs x2, TPMAX0_EL1
-// CHECK-INST: mrs x2, TPMAX0_EL1
+mrs x2, TPCR1_EL1
+// CHECK-INST: mrs x2, TPCR1_EL1
// CHECK-ENCODING: encoding: [0xa2,0x22,0x38,0xd5]
-// CHECK-UNKNOWN: d53822a2 mrs x2, TPMAX0_EL1
-
-mrs x2, TPMIN1_EL1
-// CHECK-INST: mrs x2, TPMIN1_EL1
-// CHECK-ENCODING: encoding: [0xc2,0x22,0x38,0xd5]
-// CHECK-UNKNOWN: d53822c2 mrs x2, TPMIN1_EL1
-
-mrs x2, TPMAX1_EL1
-// CHECK-INST: mrs x2, TPMAX1_EL1
-// CHECK-ENCODING: encoding: [0xe2,0x22,0x38,0xd5]
-// CHECK-UNKNOWN: d53822e2 mrs x2, TPMAX1_EL1
+// CHECK-UNKNOWN: d53822a2 mrs x2, TPCR1_EL1
-mrs x2, TPMIN0_EL2
-// CHECK-INST: mrs x2, TPMIN0_EL2
+mrs x2, TPCR0_EL2
+// CHECK-INST: mrs x2, TPCR0_EL2
// CHECK-ENCODING: encoding: [0x82,0x22,0x3c,0xd5]
-// CHECK-UNKNOWN: d53c2282 mrs x2, TPMIN0_EL2
+// CHECK-UNKNOWN: d53c2282 mrs x2, TPCR0_EL2
-mrs x2, TPMAX0_EL2
-// CHECK-INST: mrs x2, TPMAX0_EL2
+mrs x2, TPCR1_EL2
+// CHECK-INST: mrs x2, TPCR1_EL2
// CHECK-ENCODING: encoding: [0xa2,0x22,0x3c,0xd5]
-// CHECK-UNKNOWN: d53c22a2 mrs x2, TPMAX0_EL2
+// CHECK-UNKNOWN: d53c22a2 mrs x2, TPCR1_EL2
-mrs x2, TPMIN1_EL2
-// CHECK-INST: mrs x2, TPMIN1_EL2
-// CHECK-ENCODING: encoding: [0xc2,0x22,0x3c,0xd5]
-// CHECK-UNKNOWN: d53c22c2 mrs x2, TPMIN1_EL2
-
-mrs x2, TPMAX1_EL2
-// CHECK-INST: mrs x2, TPMAX1_EL2
-// CHECK-ENCODING: encoding: [0xe2,0x22,0x3c,0xd5]
-// CHECK-UNKNOWN: d53c22e2 mrs x2, TPMAX1_EL2
-
-mrs x2, TPMIN0_EL12
-// CHECK-INST: mrs x2, TPMIN0_EL12
+mrs x2, TPCR0_EL12
+// CHECK-INST: mrs x2, TPCR0_EL12
// CHECK-ENCODING: encoding: [0x82,0x22,0x3d,0xd5]
-// CHECK-UNKNOWN: d53d2282 mrs x2, TPMIN0_EL12
+// CHECK-UNKNOWN: d53d2282 mrs x2, TPCR0_EL12
-mrs x2, TPMAX0_EL12
-// CHECK-INST: mrs x2, TPMAX0_EL12
+mrs x2, TPCR1_EL12
+// CHECK-INST: mrs x2, TPCR1_EL12
// CHECK-ENCODING: encoding: [0xa2,0x22,0x3d,0xd5]
-// CHECK-UNKNOWN: d53d22a2 mrs x2, TPMAX0_EL12
-
-mrs x2, TPMIN1_EL12
-// CHECK-INST: mrs x2, TPMIN1_EL12
-// CHECK-ENCODING: encoding: [0xc2,0x22,0x3d,0xd5]
-// CHECK-UNKNOWN: d53d22c2 mrs x2, TPMIN1_EL12
-
-mrs x2, TPMAX1_EL12
-// CHECK-INST: mrs x2, TPMAX1_EL12
-// CHECK-ENCODING: encoding: [0xe2,0x22,0x3d,0xd5]
-// CHECK-UNKNOWN: d53d22e2 mrs x2, TPMAX1_EL12
+// CHECK-UNKNOWN: d53d22a2 mrs x2, TPCR1_EL12
msr TPIDR3_EL0, x0
@@ -2808,85 +2768,45 @@ msr AFGDTP15_EL3, x0
// CHECK-ENCODING: encoding: [0xe0,0x37,0x1e,0xd5]
// CHECK-UNKNOWN: d51e37e0 msr AFGDTP15_EL3, x0
-msr TPMIN0_EL0, x2
-// CHECK-INST: msr TPMIN0_EL0, x2
+msr TPCR0_EL0, x2
+// CHECK-INST: msr TPCR0_EL0, x2
// CHECK-ENCODING: encoding: [0x82,0x22,0x1b,0xd5]
-// CHECK-UNKNOWN: d51b2282 msr TPMIN0_EL0, x2
+// CHECK-UNKNOWN: d51b2282 msr TPCR0_EL0, x2
-msr TPMAX0_EL0, x2
-// CHECK-INST: msr TPMAX0_EL0, x2
+msr TPCR1_EL0, x2
+// CHECK-INST: msr TPCR1_EL0, x2
// CHECK-ENCODING: encoding: [0xa2,0x22,0x1b,0xd5]
-// CHECK-UNKNOWN: d51b22a2 msr TPMAX0_EL0, x2
+// CHECK-UNKNOWN: d51b22a2 msr TPCR1_EL0, x2
-msr TPMIN1_EL0, x2
-// CHECK-INST: msr TPMIN1_EL0, x2
-// CHECK-ENCODING: encoding: [0xc2,0x22,0x1b,0xd5]
-// CHECK-UNKNOWN: d51b22c2 msr TPMIN1_EL0, x2
-
-msr TPMAX1_EL0, x2
-// CHECK-INST: msr TPMAX1_EL0, x2
-// CHECK-ENCODING: encoding: [0xe2,0x22,0x1b,0xd5]
-// CHECK-UNKNOWN: d51b22e2 msr TPMAX1_EL0, x2
-
-msr TPMIN0_EL1, x2
-// CHECK-INST: msr TPMIN0_EL1, x2
+msr TPCR0_EL1, x2
+// CHECK-INST: msr TPCR0_EL1, x2
// CHECK-ENCODING: encoding: [0x82,0x22,0x18,0xd5]
-// CHECK-UNKNOWN: d5182282 msr TPMIN0_EL1, x2
+// CHECK-UNKNOWN: d5182282 msr TPCR0_EL1, x2
-msr TPMAX0_EL1, x2
-// CHECK-INST: msr TPMAX0_EL1, x2
+msr TPCR1_EL1, x2
+// CHECK-INST: msr TPCR1_EL1, x2
// CHECK-ENCODING: encoding: [0xa2,0x22,0x18,0xd5]
-// CHECK-UNKNOWN: d51822a2 msr TPMAX0_EL1, x2
-
-msr TPMIN1_EL1, x2
-// CHECK-INST: msr TPMIN1_EL1, x2
-// CHECK-ENCODING: encoding: [0xc2,0x22,0x18,0xd5]
-// CHECK-UNKNOWN: d51822c2 msr TPMIN1_EL1, x2
-
-msr TPMAX1_EL1, x2
-// CHECK-INST: msr TPMAX1_EL1, x2
-// CHECK-ENCODING: encoding: [0xe2,0x22,0x18,0xd5]
-// CHECK-UNKNOWN: d51822e2 msr TPMAX1_EL1, x2
+// CHECK-UNKNOWN: d51822a2 msr TPCR1_EL1, x2
-msr TPMIN0_EL2, x2
-// CHECK-INST: msr TPMIN0_EL2, x2
+msr TPCR0_EL2, x2
+// CHECK-INST: msr TPCR0_EL2, x2
// CHECK-ENCODING: encoding: [0x82,0x22,0x1c,0xd5]
-// CHECK-UNKNOWN: d51c2282 msr TPMIN0_EL2, x2
+// CHECK-UNKNOWN: d51c2282 msr TPCR0_EL2, x2
-msr TPMAX0_EL2, x2
-// CHECK-INST: msr TPMAX0_EL2, x2
+msr TPCR1_EL2, x2
+// CHECK-INST: msr TPCR1_EL2, x2
// CHECK-ENCODING: encoding: [0xa2,0x22,0x1c,0xd5]
-// CHECK-UNKNOWN: d51c22a2 msr TPMAX0_EL2, x2
+// CHECK-UNKNOWN: d51c22a2 msr TPCR1_EL2, x2
-msr TPMIN1_EL2, x2
-// CHECK-INST: msr TPMIN1_EL2, x2
-// CHECK-ENCODING: encoding: [0xc2,0x22,0x1c,0xd5]
-// CHECK-UNKNOWN: d51c22c2 msr TPMIN1_EL2, x2
-
-msr TPMAX1_EL2, x2
-// CHECK-INST: msr TPMAX1_EL2, x2
-// CHECK-ENCODING: encoding: [0xe2,0x22,0x1c,0xd5]
-// CHECK-UNKNOWN: d51c22e2 msr TPMAX1_EL2, x2
-
-msr TPMIN0_EL12, x2
-// CHECK-INST: msr TPMIN0_EL12, x2
+msr TPCR0_EL12, x2
+// CHECK-INST: msr TPCR0_EL12, x2
// CHECK-ENCODING: encoding: [0x82,0x22,0x1d,0xd5]
-// CHECK-UNKNOWN: d51d2282 msr TPMIN0_EL12, x2
+// CHECK-UNKNOWN: d51d2282 msr TPCR0_EL12, x2
-msr TPMAX0_EL12, x2
-// CHECK-INST: msr TPMAX0_EL12, x2
+msr TPCR1_EL12, x2
+// CHECK-INST: msr TPCR1_EL12, x2
// CHECK-ENCODING: encoding: [0xa2,0x22,0x1d,0xd5]
-// CHECK-UNKNOWN: d51d22a2 msr TPMAX0_EL12, x2
-
-msr TPMIN1_EL12, x2
-// CHECK-INST: msr TPMIN1_EL12, x2
-// CHECK-ENCODING: encoding: [0xc2,0x22,0x1d,0xd5]
-// CHECK-UNKNOWN: d51d22c2 msr TPMIN1_EL12, x2
-
-msr TPMAX1_EL12, x2
-// CHECK-INST: msr TPMAX1_EL12, x2
-// CHECK-ENCODING: encoding: [0xe2,0x22,0x1d,0xd5]
-// CHECK-UNKNOWN: d51d22e2 msr TPMAX1_EL12, x2
+// CHECK-UNKNOWN: d51d22a2 msr TPCR1_EL12, x2
tchangef x0, x1
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