[llvm] Add SuperH (1-4a) target (PR #181287)
via llvm-commits
llvm-commits at lists.llvm.org
Thu May 28 20:15:58 PDT 2026
https://github.com/LunaTheFoxgirl updated https://github.com/llvm/llvm-project/pull/181287
>From 63a5058d7763eaf2d9be5db4ff04d5f8dd30664d Mon Sep 17 00:00:00 2001
From: LunaTheFoxgirl <luna at foxgirls.gay>
Date: Fri, 13 Feb 2026 02:37:18 +0100
Subject: [PATCH 1/3] sh4: initial commit
---
llvm/CMakeLists.txt | 1 +
llvm/lib/Target/SuperH/CMakeLists.txt | 25 ++++
.../Target/SuperH/MCTargetDesc/CMakeLists.txt | 12 ++
.../MCTargetDesc/SuperHMCTargetDesc.cpp | 34 ++++++
.../SuperH/MCTargetDesc/SuperHMCTargetDesc.h | 38 ++++++
llvm/lib/Target/SuperH/SuperH.td | 59 +++++++++
llvm/lib/Target/SuperH/SuperHInstrFormats.td | 21 ++++
llvm/lib/Target/SuperH/SuperHInstrInfo.td | 21 ++++
llvm/lib/Target/SuperH/SuperHRegisterInfo.td | 113 ++++++++++++++++++
llvm/lib/Target/SuperH/SuperHSchedule.td | 22 ++++
.../lib/Target/SuperH/SuperHTargetMachine.cpp | 40 +++++++
llvm/lib/Target/SuperH/SuperHTargetMachine.h | 38 ++++++
.../Target/SuperH/TargetInfo/CMakeLists.txt | 10 ++
.../SuperH/TargetInfo/SuperHTargetInfo.cpp | 23 ++++
.../SuperH/TargetInfo/SuperHTargetInfo.h | 20 ++++
15 files changed, 477 insertions(+)
create mode 100644 llvm/lib/Target/SuperH/CMakeLists.txt
create mode 100644 llvm/lib/Target/SuperH/MCTargetDesc/CMakeLists.txt
create mode 100644 llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCTargetDesc.cpp
create mode 100644 llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCTargetDesc.h
create mode 100644 llvm/lib/Target/SuperH/SuperH.td
create mode 100644 llvm/lib/Target/SuperH/SuperHInstrFormats.td
create mode 100644 llvm/lib/Target/SuperH/SuperHInstrInfo.td
create mode 100644 llvm/lib/Target/SuperH/SuperHRegisterInfo.td
create mode 100644 llvm/lib/Target/SuperH/SuperHSchedule.td
create mode 100644 llvm/lib/Target/SuperH/SuperHTargetMachine.cpp
create mode 100644 llvm/lib/Target/SuperH/SuperHTargetMachine.h
create mode 100644 llvm/lib/Target/SuperH/TargetInfo/CMakeLists.txt
create mode 100644 llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.cpp
create mode 100644 llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.h
diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt
index 2e2c269c0abbc..7b36ea47d04c9 100644
--- a/llvm/CMakeLists.txt
+++ b/llvm/CMakeLists.txt
@@ -540,6 +540,7 @@ set(LLVM_ALL_EXPERIMENTAL_TARGETS
DirectX
M68k
Xtensa
+ SuperH
)
# List of targets with JIT support:
diff --git a/llvm/lib/Target/SuperH/CMakeLists.txt b/llvm/lib/Target/SuperH/CMakeLists.txt
new file mode 100644
index 0000000000000..a12dcbc2e101d
--- /dev/null
+++ b/llvm/lib/Target/SuperH/CMakeLists.txt
@@ -0,0 +1,25 @@
+add_llvm_component_group(SuperH)
+
+set(LLVM_TARGET_DEFINITIONS SuperH.td)
+
+# add_public_tablegen_target(SuperHCommonTableGen)
+
+add_llvm_target(SuperHCodeGen
+ SuperHTargetMachine.cpp
+
+ LINK_COMPONENTS
+ AsmPrinter
+ CodeGen
+ Core
+ MC
+ SelectionDAG
+ Support
+ Target
+ TargetParser
+
+ ADD_TO_COMPONENT
+ SuperH
+ )
+
+add_subdirectory(TargetInfo)
+add_subdirectory(MCTargetDesc)
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/SuperH/MCTargetDesc/CMakeLists.txt
new file mode 100644
index 0000000000000..a9a69ea22dc05
--- /dev/null
+++ b/llvm/lib/Target/SuperH/MCTargetDesc/CMakeLists.txt
@@ -0,0 +1,12 @@
+add_llvm_component_library(LLVMSuperHDesc
+ SuperHMCTargetDesc.cpp
+
+ LINK_COMPONENTS
+ MC
+ MCDisassembler
+ Support
+ TargetParser
+
+ ADD_TO_COMPONENT
+ SuperH
+)
diff --git a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCTargetDesc.cpp b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCTargetDesc.cpp
new file mode 100644
index 0000000000000..d7ac60efb4563
--- /dev/null
+++ b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCTargetDesc.cpp
@@ -0,0 +1,34 @@
+//===-- SuperHMCTargetDesc.cpp - SuperH Target Descriptions ---------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file provides SuperH target specific descriptions.
+///
+//===----------------------------------------------------------------------===//
+
+#include "SuperHMCTargetDesc.h"
+#include "TargetInfo/SuperHTargetInfo.h"
+
+#include "llvm/MC/MCELFStreamer.h"
+#include "llvm/MC/MCInstPrinter.h"
+#include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCSymbol.h"
+#include "llvm/MC/MachineLocation.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/FormattedStream.h"
+
+using namespace llvm;
+
+extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY
+void LLVMInitializeSuperHTargetMC() {
+
+}
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCTargetDesc.h b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCTargetDesc.h
new file mode 100644
index 0000000000000..b1428a0b33366
--- /dev/null
+++ b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCTargetDesc.h
@@ -0,0 +1,38 @@
+//===-- SuperHMCTargetDesc.h - SuperH Target Descriptions -----------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file provides SuperH specific target descriptions.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_SUPERH_MCTARGETDESC_SUPERHMCTARGETDESC_H
+#define LLVM_LIB_TARGET_SUPERH_MCTARGETDESC_SUPERHMCTARGETDESC_H
+
+#include "llvm/MC/MCInstrDesc.h"
+#include "llvm/MC/MCObjectWriter.h"
+#include "llvm/Support/DataTypes.h"
+
+namespace llvm {
+class MCAsmBackend;
+class MCCodeEmitter;
+class MCContext;
+class MCInstrInfo;
+class MCRegisterInfo;
+class MCSubtargetInfo;
+class MCRelocationInfo;
+class MCTargetOptions;
+class Target;
+class Triple;
+class StringRef;
+class raw_ostream;
+class raw_pwrite_stream;
+
+}
+
+#endif // LLVM_LIB_TARGET_SUPERH_MCTARGETDESC_SUPERHMCTARGETDESC_H
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/SuperH.td b/llvm/lib/Target/SuperH/SuperH.td
new file mode 100644
index 0000000000000..ea768a5b8dc9d
--- /dev/null
+++ b/llvm/lib/Target/SuperH/SuperH.td
@@ -0,0 +1,59 @@
+//===- SuperH.td - Describe the SuperH Target Machine ------*- tablegen -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Target-independent interfaces
+//===----------------------------------------------------------------------===//
+
+include "llvm/Target/Target.td"
+
+//===----------------------------------------------------------------------===//
+// SuperH Subtarget features
+//===----------------------------------------------------------------------===//
+
+
+//===----------------------------------------------------------------------===//
+// SuperH Processors
+//===----------------------------------------------------------------------===//
+
+include "SuperHSchedule.td"
+
+class Proc<string Name, list<SubtargetFeature> Features>
+ : ProcessorModel<Name, GenericSHModel, Features>;
+
+def : Proc<"generic", [ ]>;
+def : Proc<"sh1", []>;
+def : Proc<"sh2", []>;
+def : Proc<"sh3", []>;
+def : Proc<"sh4", []>;
+def : Proc<"sh4a", []>;
+
+//===----------------------------------------------------------------------===//
+// Register File Description
+//===----------------------------------------------------------------------===//
+
+include "SuperHRegisterInfo.td"
+
+//===----------------------------------------------------------------------===//
+// Instruction Descriptions
+//===----------------------------------------------------------------------===//
+
+// include "SuperHInstrInfo.td"
+
+def SuperHInstrInfo : InstrInfo;
+
+//===----------------------------------------------------------------------===//
+// Target Declaration
+//===----------------------------------------------------------------------===//
+
+def SuperH : Target {
+ let InstructionSet = SuperHInstrInfo;
+
+}
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/SuperHInstrFormats.td b/llvm/lib/Target/SuperH/SuperHInstrFormats.td
new file mode 100644
index 0000000000000..d3bacb075c9ba
--- /dev/null
+++ b/llvm/lib/Target/SuperH/SuperHInstrFormats.td
@@ -0,0 +1,21 @@
+//===-- SuperHInstrFormats.td - SuperH Instruction Formats ---------*- tablegen -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+class SHInst<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : Instruction {
+ let Namespace = "SH";
+
+ dag OutOperandList = outs;
+ dag InOperandList = ins;
+ let AsmString = asmtr;
+ let Pattern = pattern;
+
+ field bits<16> Inst;
+ let Size = 2;
+}
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/SuperHInstrInfo.td b/llvm/lib/Target/SuperH/SuperHInstrInfo.td
new file mode 100644
index 0000000000000..a4451d7a502d5
--- /dev/null
+++ b/llvm/lib/Target/SuperH/SuperHInstrInfo.td
@@ -0,0 +1,21 @@
+//===-- SuperHInstrInfo.td - Main SuperH Instruction Definition -*- tablegen -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file describes the SuperH instruction set, defining the instructions
+/// and properties of the instructions which are needed for code generation,
+/// machine code emission, and analysis.
+///
+//===----------------------------------------------------------------------===//
+
+include "SuperHInstrFormats.td"
+
+//===----------------------------------------------------------------------===//
+// SuperH Type Profiles
+//===----------------------------------------------------------------------===//
+
diff --git a/llvm/lib/Target/SuperH/SuperHRegisterInfo.td b/llvm/lib/Target/SuperH/SuperHRegisterInfo.td
new file mode 100644
index 0000000000000..325d6520c1512
--- /dev/null
+++ b/llvm/lib/Target/SuperH/SuperHRegisterInfo.td
@@ -0,0 +1,113 @@
+//==-- SuperHRegisterInfo.td - SuperH register definitions ------*- tablegen -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file describes the SuperH Register file, defining the registers
+/// aliases between the registers, and the register classes built out of the
+/// registers.
+///
+//===----------------------------------------------------------------------===//
+
+// SuperH Registers
+class SHRegister<string N, bits<16> ENC,
+ list<Register> SUBREGS = [], list<SubRegIndex> SUBIDX,
+ list<string> ALTNAMES = []>
+ : Register<N, ALTNAMES> {
+ let Namespace = "SH";
+ let HWEncoding = ENC;
+ let SubRegs = SUBREGS;
+ let SubRegIndices = SUBIDX;
+}
+
+let Namespace = "SH" in {
+
+ // MAC registers
+ def sub_16bit_lo : SubRegIndex<16>;
+ def sub_16bit_hi : SubRegIndex<16, 16>;
+
+ // FP Registers
+ def sub_32bit_lo : SubRegIndex<32>;
+ def sub_32bit_hi : SubRegIndex<32, 32>;
+}
+
+//===----------------------------------------------------------------------===//
+// Registers
+//===----------------------------------------------------------------------===//
+
+let Namespace = "SH" in {
+
+ // GP Registers
+ def R0 : SHRegister<0, "r0>, DwarfRegNum<[ 0 ]>;
+ def R1 : SHRegister<1, "r1>, DwarfRegNum<[ 1 ]>;
+ def R2 : SHRegister<2, "r2>, DwarfRegNum<[ 2 ]>;
+ def R3 : SHRegister<3, "r3>, DwarfRegNum<[ 3 ]>;
+ def R4 : SHRegister<4, "r4>, DwarfRegNum<[ 4 ]>;
+ def R5 : SHRegister<5, "r5>, DwarfRegNum<[ 5 ]>;
+ def R6 : SHRegister<6, "r6>, DwarfRegNum<[ 6 ]>;
+ def R7 : SHRegister<7, "r7>, DwarfRegNum<[ 7 ]>;
+ def R8 : SHRegister<8, "r8>, DwarfRegNum<[ 8 ]>;
+ def R9 : SHRegister<9, "r9>, DwarfRegNum<[ 9 ]>;
+ def R10 : SHRegister<10, "r10>, DwarfRegNum<[ 10 ]>;
+ def R11 : SHRegister<11, "r11>, DwarfRegNum<[ 11 ]>;
+ def R12 : SHRegister<12, "r12>, DwarfRegNum<[ 12 ]>;
+ def R13 : SHRegister<13, "r13>, DwarfRegNum<[ 13 ]>;
+ def R14 : SHRegister<14, "r14, [ "fp" ]>, DwarfRegNum<[ 14 ]>;
+ def R15 : SHRegister<15, "r15, [ "sp" ]>, DwarfRegNum<[ 15 ]>;
+
+ // Control Registers
+ def SR : SHRegister<16, "sr">, DwarfRegNum<[ 22 ]>;
+ def GBR : SHRegister<17, "gbr">, DwarfRegNum<[ 18 ]>;
+ def VBR : SHRegister<18, "vbr">, DwarfRegNum<[ 19 ]>;
+
+ // System Registers
+ def MACH : SHRegister<19, "mach">, DwarfRegNum<[ 21 ]>;
+ def MACL : SHRegister<20, "macl">, DwarfRegNum<[ 21 ]>;
+ let SubRegIndices = [sub_16bit_lo, sub_16bit_hi] in {
+ def MAC : SHRegister<21, "mac", [], [MACL, MACH]>;
+ }
+ def PC : SHRegister<22, "pc">, DwarfRegNum<[ 16 ]>;
+ def PR : SHRegister<23, "pr">, DwarfRegNum<[ 17 ]>;
+
+ // FR Registers
+
+ // TODO: Add float registers
+}
+
+//===----------------------------------------------------------------------===//
+// Register Classes
+//===----------------------------------------------------------------------===//
+
+def GPR : RegisterClass<"SH", [i32], 32, (
+ add(
+ R0, R1, R2, R3, R4, R5, R6, R7, // Banked memory
+ R8, R9, R10, R11, R12, R13, R14, R15, // Non-banked memory.
+ )
+)>;
+
+// Control registers
+def CR : RegisterClass<"SH", [i32], 32, (add SR, GBR, VBR>) {
+ let CopyCost = -1;
+ let isAllocatable = 0;
+}
+
+// System registers.
+def SYSR : RegisterClass<"SH", [ i32 ], 32, (add MACH, MACL, PR, PC)> {
+ let CopyCost = -1;
+ let isAllocatable = 0;
+}
+
+// MAC register.
+def MACR : RegisterClass<"SH", [ i64 ], 64, (add MAC)> {
+ let CopyCost = -1;
+ let isAllocatable = 0;
+}
+
+def PCR : RegisterClass<"SH", [ i32 ], 32, (add PC)> {
+ let CopyCost = -1;
+ let isAllocatable = 0;
+}
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/SuperHSchedule.td b/llvm/lib/Target/SuperH/SuperHSchedule.td
new file mode 100644
index 0000000000000..fe0d13648349f
--- /dev/null
+++ b/llvm/lib/Target/SuperH/SuperHSchedule.td
@@ -0,0 +1,22 @@
+//===-- SuperHSchedule.td - SuperH Scheduling Definitions ------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file contains SuperH scheduler definitions.
+///
+//===----------------------------------------------------------------------===//
+
+/// SuperH Base Scheduling Model.
+class SuperHSchedModel : SchedMachineModel {
+ let LoadLatency = 4; // Word (Rn)
+ let HighLatency = 16; // Long ABS
+ let PostRAScheduler = 0;
+ let CompleteModel = 0;
+}
+
+def GenericSuperHModel : SuperHSchedModel;
diff --git a/llvm/lib/Target/SuperH/SuperHTargetMachine.cpp b/llvm/lib/Target/SuperH/SuperHTargetMachine.cpp
new file mode 100644
index 0000000000000..91673573b22b2
--- /dev/null
+++ b/llvm/lib/Target/SuperH/SuperHTargetMachine.cpp
@@ -0,0 +1,40 @@
+//===-- SuperHTargetMachine.cpp - Define TargetMachine for SuperH -----------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+#include "SuperHTargetMachine.h"
+#include "TargetInfo/SuperHTargetInfo.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/Compiler.h"
+#include <optional>
+
+using namespace llvm;
+
+extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSuperHTarget() {
+ RegisterTargetMachine<SuperHTargetMachine> SH(getTheSuperHTarget());
+}
+
+SuperHTargetMachine::~SuperHTargetMachine() { }
+
+/// Create a SuperH architecture model.
+SuperHTargetMachine::SuperHTargetMachine(const Target &T, const Triple &TT,
+ StringRef CPU, StringRef FS,
+ const TargetOptions &Options,
+ std::optional<Reloc::Model> RM,
+ std::optional<CodeModel::Model> CM,
+ CodeGenOptLevel OL, bool JIT)
+ : CodeGenTargetMachineImpl(
+ T, TT.computeDataLayout(), TT, CPU, FS, Options,
+ RM.value_or(Reloc::Static), getEffectiveCodeModel(CM, CodeModel::Small),
+ OL) {
+
+}
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/SuperHTargetMachine.h b/llvm/lib/Target/SuperH/SuperHTargetMachine.h
new file mode 100644
index 0000000000000..5da814b766f4a
--- /dev/null
+++ b/llvm/lib/Target/SuperH/SuperHTargetMachine.h
@@ -0,0 +1,38 @@
+//===-- SuperHTargetMachine.h - Define TargetMachine for SuperH ---*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the SuperH specific subclass of TargetMachine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_SPARC_SPARCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_SPARC_SPARCTARGETMACHINE_H
+
+#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
+#include "llvm/Target/TargetMachine.h"
+#include <optional>
+
+namespace llvm {
+
+class SuperHTargetMachine : public CodeGenTargetMachineImpl {
+private:
+
+protected:
+
+public:
+ SuperHTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
+ StringRef FS, const TargetOptions &Options,
+ std::optional<Reloc::Model> RM,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
+ bool JIT);
+ ~SuperHTargetMachine() override;
+
+};
+} // end namespace llvm
+
+#endif
diff --git a/llvm/lib/Target/SuperH/TargetInfo/CMakeLists.txt b/llvm/lib/Target/SuperH/TargetInfo/CMakeLists.txt
new file mode 100644
index 0000000000000..73abb4dbba519
--- /dev/null
+++ b/llvm/lib/Target/SuperH/TargetInfo/CMakeLists.txt
@@ -0,0 +1,10 @@
+add_llvm_component_library(LLVMSuperHInfo
+ SuperHTargetInfo.cpp
+
+ LINK_COMPONENTS
+ MC
+ Support
+
+ ADD_TO_COMPONENT
+ SuperH
+ )
diff --git a/llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.cpp b/llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.cpp
new file mode 100644
index 0000000000000..b676f36dc8d55
--- /dev/null
+++ b/llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.cpp
@@ -0,0 +1,23 @@
+//===-- SuperHTargetInfo.cpp - SuperH Target Implementation -----------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "TargetInfo/SuperHTargetInfo.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/Compiler.h"
+using namespace llvm;
+
+Target &llvm::getTheSuperHTarget() {
+ static Target TheSuperHTarget;
+ return TheSuperHTarget;
+}
+
+extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY
+void LLVMInitializeSuperHTargetInfo() {
+ RegisterTarget<Triple::superh, /*HasJIT=*/false> X(getTheSuperHTarget(),
+ "sh", "SuperH", "SuperH");
+}
diff --git a/llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.h b/llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.h
new file mode 100644
index 0000000000000..38b501e05d46e
--- /dev/null
+++ b/llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.h
@@ -0,0 +1,20 @@
+//===-- SuperHTargetInfo.h - SuperH Target Implementation ---------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_SUPERH_TARGETINFO_SUPERHTARGETINFO_H
+#define LLVM_LIB_TARGET_SUPERH_TARGETINFO_SUPERHTARGETINFO_H
+
+namespace llvm {
+
+class Target;
+
+Target &getTheSuperHTarget();
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_SUPERH_TARGETINFO_SUPERHTARGETINFO_H
>From e31622952c80e4579aba246c32c29e514104d1af Mon Sep 17 00:00:00 2001
From: LunaTheFoxgirl <luna at foxgirls.gay>
Date: Fri, 29 May 2026 02:41:44 +0200
Subject: [PATCH 2/3] Add self to Maintainers.md
---
llvm/Maintainers.md | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/llvm/Maintainers.md b/llvm/Maintainers.md
index 1b84d12fa51f3..911a0e9674856 100644
--- a/llvm/Maintainers.md
+++ b/llvm/Maintainers.md
@@ -354,6 +354,11 @@ nigelp at xmos.com (email), [nigelp-xmos](https://github.com/nigelp-xmos) (GitHub)
Andrei Safronov \
andrei.safronov at espressif.com (email), [andreisfr](https://github.com/andreisfr) (GitHub)
+#### SuperH backend
+
+Luna Nielsen \
+luna at foxgirls.gay (email), [LunaTheFoxgirl](https://github.com/LunaTheFoxgirl) (GitHub)
+
### Libraries and shared infrastructure
#### ADT, Support
>From 5bdf0fb053af407aa5df9281c138a300e9e5ad0c Mon Sep 17 00:00:00 2001
From: LunaTheFoxgirl <luna at foxgirls.gay>
Date: Fri, 29 May 2026 05:14:53 +0200
Subject: [PATCH 3/3] Flesh out register file and target cpu
---
llvm/include/llvm/TargetParser/Triple.h | 1 +
llvm/lib/Target/SuperH/SuperH.td | 33 ++-
llvm/lib/Target/SuperH/SuperHRegisterInfo.td | 220 ++++++++++++------
.../SuperH/TargetInfo/SuperHTargetInfo.cpp | 2 +-
llvm/lib/TargetParser/Triple.cpp | 6 +
5 files changed, 187 insertions(+), 75 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h
index 7b24db121818f..25b35bb99edb7 100644
--- a/llvm/include/llvm/TargetParser/Triple.h
+++ b/llvm/include/llvm/TargetParser/Triple.h
@@ -79,6 +79,7 @@ class Triple {
riscv64, // RISC-V (64-bit, little endian): riscv64
riscv32be, // RISC-V (32-bit, big endian): riscv32be
riscv64be, // RISC-V (64-bit, big endian): riscv64be
+ sh, // SuperH: sh
sparc, // Sparc: sparc
sparcv9, // Sparcv9: Sparcv9
sparcel, // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
diff --git a/llvm/lib/Target/SuperH/SuperH.td b/llvm/lib/Target/SuperH/SuperH.td
index ea768a5b8dc9d..cd7ef7e54f403 100644
--- a/llvm/lib/Target/SuperH/SuperH.td
+++ b/llvm/lib/Target/SuperH/SuperH.td
@@ -7,6 +7,8 @@
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
+// This is the top level entry point for the SuperH target.
+//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Target-independent interfaces
@@ -18,6 +20,24 @@ include "llvm/Target/Target.td"
// SuperH Subtarget features
//===----------------------------------------------------------------------===//
+def FeatureFPU : SubtargetFeature<"fpu", "HasFPU", "false",
+ "Enable FPU Support">;
+def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU", "true",
+ "Enable vector FPU instructions">;
+def FeatureSH1 : SubtargetFeature<"sh1", "SHArchVersion", "SH1",
+ "SH-1 ISA Support">;
+def FeatureSH2 : SubtargetFeature<"sh2", "SHArchVersion", "SH2",
+ "SH-2 ISA Support",
+ [FeatureSH1]>;
+def FeatureSH3 : SubtargetFeature<"sh3", "SHArchVersion", "SH3",
+ "SH-3 ISA Support",
+ [FeatureSH1, FeatureSH2]>;
+def FeatureSH4 : SubtargetFeature<"sh4", "SHArchVersion", "SH3",
+ "SH-4 ISA Support",
+ [FeatureSH1, FeatureSH2, FeatureSH3, FeatureFPU]>;
+def FeatureSH4A : SubtargetFeature<"sh4a", "SHArchVersion", "SH4A",
+ "SH-4A ISA Support",
+ [FeatureSH1, FeatureSH2, FeatureSH3, FeatureSH4, FeatureFPU]>;
//===----------------------------------------------------------------------===//
// SuperH Processors
@@ -28,12 +48,12 @@ include "SuperHSchedule.td"
class Proc<string Name, list<SubtargetFeature> Features>
: ProcessorModel<Name, GenericSHModel, Features>;
-def : Proc<"generic", [ ]>;
-def : Proc<"sh1", []>;
-def : Proc<"sh2", []>;
-def : Proc<"sh3", []>;
-def : Proc<"sh4", []>;
-def : Proc<"sh4a", []>;
+def : Proc<"generic", [FeatureSH4]>;
+def : Proc<"sh1", [FeatureSH1]>;
+def : Proc<"sh2", [FeatureSH2]>;
+def : Proc<"sh3", [FeatureSH3]>;
+def : Proc<"sh4", [FeatureSH4]>;
+def : Proc<"sh4a", [FeatureSH4A]>;
//===----------------------------------------------------------------------===//
// Register File Description
@@ -55,5 +75,4 @@ def SuperHInstrInfo : InstrInfo;
def SuperH : Target {
let InstructionSet = SuperHInstrInfo;
-
}
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/SuperHRegisterInfo.td b/llvm/lib/Target/SuperH/SuperHRegisterInfo.td
index 325d6520c1512..abf4cbfcc3ba2 100644
--- a/llvm/lib/Target/SuperH/SuperHRegisterInfo.td
+++ b/llvm/lib/Target/SuperH/SuperHRegisterInfo.td
@@ -13,101 +13,187 @@
///
//===----------------------------------------------------------------------===//
-// SuperH Registers
-class SHRegister<string N, bits<16> ENC,
- list<Register> SUBREGS = [], list<SubRegIndex> SUBIDX,
- list<string> ALTNAMES = []>
- : Register<N, ALTNAMES> {
- let Namespace = "SH";
- let HWEncoding = ENC;
- let SubRegs = SUBREGS;
- let SubRegIndices = SUBIDX;
-}
+//===----------------------------------------------------------------------===//
+// Declarations that describe the SuperH register file
+//===----------------------------------------------------------------------===//
let Namespace = "SH" in {
+ def sub_64_lo : SubRegIndex<64>;
+ def sub_64_hi : SubRegIndex<64, 64>;
+ def sub_32_lo : SubRegIndex<32>;
+ def sub_32_hi : SubRegIndex<32, 32>;
+
+ // Vector Registers
+ def sub_fv_x : SubRegIndex<32>;
+ def sub_fv_y : SubRegIndex<32, 32>;
+ def sub_fv_z : SubRegIndex<32, 64>;
+ def sub_fv_w : SubRegIndex<32, 96>;
+
+ // Matrix Register
+}
+
+class Unallocatable {
+ int CopyCost = -1;
+ bit isAllocatable = false;
+}
+
+class SHReg<bits<16> Enc, string n> : Register<n> {
+ let HWEncoding = Enc;
+ let Namespace = "SH";
+}
- // MAC registers
- def sub_16bit_lo : SubRegIndex<16>;
- def sub_16bit_hi : SubRegIndex<16, 16>;
+class SHRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
+ : RegisterWithSubRegs<n, subregs> {
+ let HWEncoding = Enc;
+ let Namespace = "SH";
+}
+
+// SH General Purpose Registers.
+class GPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>;
+
+// Control Registers
+class CtrlReg<bits<16> Enc, string n> : MipsReg<Enc, n>;
+
+// SH System Registers.
+class SysReg<bits<16> Enc, string n> : MipsReg<Enc, n>;
- // FP Registers
- def sub_32bit_lo : SubRegIndex<32>;
- def sub_32bit_hi : SubRegIndex<32, 32>;
+// 32-bit floating point registers
+class FRReg<bits<16> Enc, string n> : SHReg<Enc, n>;
+
+// 64-bit (alias) FPU registers
+class DRReg<bits<16> Enc, string n, list<Register> subregs>
+ : SHRegWithSubRegs<Enc, n, subregs> {
+ let SubRegIndices = [sub_32_lo, sub_32_hi];
+ let CoveredBySubRegs = 1;
+}
+
+// 32-bit (alias) VFPU registers
+class FVReg<bits<16> Enc, string n, list<Register> subregs>
+ : SHRegWithSubRegs<Enc, n, subregs> {
+ let SubRegIndices = [sub_fv_x, sub_fv_y, sub_fv_z, sub_fv_w];
+ let CoveredBySubRegs = 1;
}
+// 512-bit Matrix Register
+class MTRXReg<bits<16> Enc, string n> : SHReg<Enc, n>;
+
//===----------------------------------------------------------------------===//
// Registers
//===----------------------------------------------------------------------===//
let Namespace = "SH" in {
- // GP Registers
- def R0 : SHRegister<0, "r0>, DwarfRegNum<[ 0 ]>;
- def R1 : SHRegister<1, "r1>, DwarfRegNum<[ 1 ]>;
- def R2 : SHRegister<2, "r2>, DwarfRegNum<[ 2 ]>;
- def R3 : SHRegister<3, "r3>, DwarfRegNum<[ 3 ]>;
- def R4 : SHRegister<4, "r4>, DwarfRegNum<[ 4 ]>;
- def R5 : SHRegister<5, "r5>, DwarfRegNum<[ 5 ]>;
- def R6 : SHRegister<6, "r6>, DwarfRegNum<[ 6 ]>;
- def R7 : SHRegister<7, "r7>, DwarfRegNum<[ 7 ]>;
- def R8 : SHRegister<8, "r8>, DwarfRegNum<[ 8 ]>;
- def R9 : SHRegister<9, "r9>, DwarfRegNum<[ 9 ]>;
- def R10 : SHRegister<10, "r10>, DwarfRegNum<[ 10 ]>;
- def R11 : SHRegister<11, "r11>, DwarfRegNum<[ 11 ]>;
- def R12 : SHRegister<12, "r12>, DwarfRegNum<[ 12 ]>;
- def R13 : SHRegister<13, "r13>, DwarfRegNum<[ 13 ]>;
- def R14 : SHRegister<14, "r14, [ "fp" ]>, DwarfRegNum<[ 14 ]>;
- def R15 : SHRegister<15, "r15, [ "sp" ]>, DwarfRegNum<[ 15 ]>;
+ // General Purpose Registers
+ def R0 : SHGPRReg<0, "r0">, DwarfRegNum<[0]>;
+ def R1 : SHGPRReg<1, "r1">, DwarfRegNum<[1]>;
+ def R2 : SHGPRReg<2, "r2">, DwarfRegNum<[2]>;
+ def R3 : SHGPRReg<3, "r3">, DwarfRegNum<[3]>;
+ def R4 : SHGPRReg<4, "r4">, DwarfRegNum<[4]>;
+ def R5 : SHGPRReg<5, "r5">, DwarfRegNum<[5]>;
+ def R6 : SHGPRReg<6, "r6">, DwarfRegNum<[6]>;
+ def R7 : SHGPRReg<7, "r7">, DwarfRegNum<[7]>;
+ def R8 : SHGPRReg<8, "r8">, DwarfRegNum<[8]>;
+ def R9 : SHGPRReg<9, "r9">, DwarfRegNum<[9]>;
+ def R10 : SHGPRReg<10, "r10">, DwarfRegNum<[10]>;
+ def R11 : SHGPRReg<11, "r11">, DwarfRegNum<[11]>;
+ def R12 : SHGPRReg<12, "r12">, DwarfRegNum<[12]>;
+ def R13 : SHGPRReg<13, "r13">, DwarfRegNum<[13]>;
+ def R14 : SHGPRReg<14, "r14">, DwarfRegNum<[14]>;
+ def R15 : SHGPRReg<15, "r15">, DwarfRegNum<[15]>;
// Control Registers
- def SR : SHRegister<16, "sr">, DwarfRegNum<[ 22 ]>;
- def GBR : SHRegister<17, "gbr">, DwarfRegNum<[ 18 ]>;
- def VBR : SHRegister<18, "vbr">, DwarfRegNum<[ 19 ]>;
+ def SR : CtrlReg<0, "sr">; // Status Register
+ def GBR : CtrlReg<0, "gbr"; // Global Base Register
+ def VBR : CtrlReg<0, "vbr">; // Vector Base Register
+ def SGR : CtrlReg<0, "sgr">; // Saved General Register
+ def DBR : CtrlReg<0, "dbr">; // Debug Base Register
+ def SSR : CtrlReg<0, "ssr">; // Saved Status Register
+ def SPC : CtrlReg<0, "spc">; // Saved Program Counter
// System Registers
- def MACH : SHRegister<19, "mach">, DwarfRegNum<[ 21 ]>;
- def MACL : SHRegister<20, "macl">, DwarfRegNum<[ 21 ]>;
- let SubRegIndices = [sub_16bit_lo, sub_16bit_hi] in {
- def MAC : SHRegister<21, "mac", [], [MACL, MACH]>;
- }
- def PC : SHRegister<22, "pc">, DwarfRegNum<[ 16 ]>;
- def PR : SHRegister<23, "pr">, DwarfRegNum<[ 17 ]>;
-
- // FR Registers
-
- // TODO: Add float registers
+ def PR : SysReg<0, "pr">; // Procedure Register
+ def PC : SysReg<0, "pc">; // Program Counter
+ def MACL : SysReg<0, "macl">; // Mult & Accum Low
+ def MACH : SysReg<1, "mach">; // Mult & Accum Hi
+ def FPSCR : SysReg<0, "fpscr">; // FPU Status/Control Register
+ def FPUL : SysReg<0, "fpul">; // FPU Comms Register
+
+ // 32-bit floating point registers
+ foreach I = 0-15 in
+ def FR#I : FRReg<I, "fr"#I>, DwarfRegNum<[!add(I, 16)]>;
+ foreach I = 0-15 in
+ def XF#I : FRReg<!add(I, 16), "xf"#I>, DwarfRegNum<[!add(I, 32)]>;
+
+ // 64-bit floating point registers
+ foreach I = 0-7 in
+ def DR#I : DRReg<!shl(I, 1), "dr"#!shl(I, 1),
+ [!cast<FPReg>("FR"#!shl(I, 1)),
+ !cast<FPReg>("FR"#!add(!shl(I, 1), 1)]>;
+ foreach I = 0-7 in
+ def XD#I : DRReg<!shl(I, 1), "xd"#!shl(I, 1),
+ [!cast<FPReg>("XF"#!shl(I, 1)),
+ !cast<FPReg>("XF"#!add(!shl(I, 1), 1)]>;
+
+ // 128-bit floating point vector registers
+ foreach I = 0-3 in
+ def FV#I : FVReg<!shl(I, 2), "fv"#!shl(I, 2),
+ [!cast<FPReg>("FR"#!shl(I, 2)),
+ !cast<FPReg>("FR"#!add(!shl(I, 2), 1)),
+ !cast<FPReg>("FR"#!add(!shl(I, 2), 2)),
+ !cast<FPReg>("XF"#!add(!shl(I, 2), 3)]>;
+
+ // 512-bit matrix register (shadows XF registers)
+ // TODO: Add proper subregisters here.
+ def MtrxReg : MTRXReg<0, "xmtrx">;
}
//===----------------------------------------------------------------------===//
// Register Classes
//===----------------------------------------------------------------------===//
-def GPR : RegisterClass<"SH", [i32], 32, (
+def GPR : RegisterClass<"SH", [ i32 ], 32, (
add(
R0, R1, R2, R3, R4, R5, R6, R7, // Banked memory
R8, R9, R10, R11, R12, R13, R14, R15, // Non-banked memory.
)
)>;
-// Control registers
-def CR : RegisterClass<"SH", [i32], 32, (add SR, GBR, VBR>) {
- let CopyCost = -1;
- let isAllocatable = 0;
-}
+// 32-bit floating point registers.
+def FGR32 : RegisterClass<"SH", [f32], 32, (
+ add(
+ // FR
+ FR0, FR1, FR2, FR3, FR4, FR5, FR6, FR7,
+ FR8, FR9, FR10, FR11, FR12, FR13, FR14, FR15,
+
+ // XF
+ XF0, XF1, XF2, XF3, XF4, XF5, XF6, XF7,
+ XF8, XF9, XF10, XF11, XF12, XF13, XF14, XF15,
+ )
+)>;
-// System registers.
-def SYSR : RegisterClass<"SH", [ i32 ], 32, (add MACH, MACL, PR, PC)> {
- let CopyCost = -1;
- let isAllocatable = 0;
-}
+// 64-bit floating point registers.
+def FGR64 : RegisterClass<"SH", [f64], 64, (add
+ // DR
+ DR0, DR1, DR2, DR3, DR4, DR5, DR6, DR7,
+ DR8, DR9, DR10, DR11, DR12, DR13, DR14, DR15,
-// MAC register.
-def MACR : RegisterClass<"SH", [ i64 ], 64, (add MAC)> {
- let CopyCost = -1;
- let isAllocatable = 0;
-}
+ // XD
+ XD0, XD1, XD2, XD3, XD4, XD5, XD6, XD7,
+ XD8, XD9, XD10, XD11, XD12, XD13, XD14, XD15,
+)>;
+
+// Vector registers
+def VEC128 : RegisterClass<"SH", [v4f32], 128, (add
+ FV0, FV4, FV8, FV12)>;
+
+// Matrix register
+def MTRX512 : RegisterClass<"SH", [v16f32],
+ (add (sequence "FR%u", 0, 15), (sequence "XF%u", 0, 15))>;
-def PCR : RegisterClass<"SH", [ i32 ], 32, (add PC)> {
- let CopyCost = -1;
- let isAllocatable = 0;
-}
\ No newline at end of file
+// Control registers
+def CR : RegisterClass<"SH", [ i32 ], 32,
+ (add SR, GBR, VBR, SGR, DBR, SSR, SPC)>, Unallocatable;
+
+// System registers.
+def SR : RegisterClass<"SH", [ i32 ], 32,
+ (add PR, PC, MACL, MACH, FPSCR, FPUL)>, Unallocatable;
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.cpp b/llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.cpp
index b676f36dc8d55..4045218737a15 100644
--- a/llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.cpp
+++ b/llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.cpp
@@ -18,6 +18,6 @@ Target &llvm::getTheSuperHTarget() {
extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY
void LLVMInitializeSuperHTargetInfo() {
- RegisterTarget<Triple::superh, /*HasJIT=*/false> X(getTheSuperHTarget(),
+ RegisterTarget<Triple::sh, /*HasJIT=*/false> X(getTheSuperHTarget(),
"sh", "SuperH", "SuperH");
}
diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp
index c6515425b7eb5..593af6c736a70 100644
--- a/llvm/lib/TargetParser/Triple.cpp
+++ b/llvm/lib/TargetParser/Triple.cpp
@@ -106,6 +106,8 @@ StringRef Triple::getArchTypeName(ArchType Kind) {
return "riscv32be";
case riscv64be:
return "riscv64be";
+ case sh:
+ return "sh";
case shave:
return "shave";
case sparc:
@@ -1229,6 +1231,7 @@ static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
case Triple::riscv64:
case Triple::riscv32be:
case Triple::riscv64be:
+ case Triple::sh:
case Triple::shave:
case Triple::sparc:
case Triple::sparcel:
@@ -1992,6 +1995,7 @@ unsigned Triple::getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
case llvm::Triple::renderscript32:
case llvm::Triple::riscv32:
case llvm::Triple::riscv32be:
+ case llvm::Triple::sh:
case llvm::Triple::shave:
case llvm::Triple::sparc:
case llvm::Triple::sparcel:
@@ -2103,6 +2107,7 @@ Triple Triple::get32BitArchVariant() const {
case Triple::renderscript32:
case Triple::riscv32:
case Triple::riscv32be:
+ case Triple::sh:
case Triple::shave:
case Triple::sparc:
case Triple::sparcel:
@@ -2195,6 +2200,7 @@ Triple Triple::get64BitArchVariant() const {
case Triple::m68k:
case Triple::msp430:
case Triple::r600:
+ case Triple::sh:
case Triple::shave:
case Triple::sparcel:
case Triple::tce:
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