[llvm] [RISCV] Factor out common scheduling model part between SiFive P400 and P500. NFCI (PR #199796)

[Pengcheng Wang via llvm-commits]

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@@ -0,0 +1,862 @@
+//==----- RISCVSchedSiFive8.td - SiFive8 Scheduling Defs -----*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the common bits of scheduling models for the P400, P500,
+// and the P600 series cores.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_TARGET_RISCV_SIFIVE_RISCVSCHEDSIFIVE8_TD
+#define LLVM_TARGET_RISCV_SIFIVE_RISCVSCHEDSIFIVE8_TD
+
+multiclass SiFive8ProcResources<int num_iex, int num_fex, int num_vex = 1,
+                                bit shared_ldst_pipes = false,
+                                bit dedicated_ld_pipe = false,
+                                int num_branch_only_iex = 0> {
+  // Integer pipes
+  foreach i = !range(num_iex) in
+  def IEXQ#i  : ProcResource<1>;
+
+  if !gt(num_iex, 1) then
+    def IntArith  : ProcResGroup<!foreach(i, !range(!sub(num_iex, num_branch_only_iex)),
+                                          !cast<ProcResource>(NAME#"IEXQ"#i))>;
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wangpc-pp wrote:

I was thinking `!cast` should be aligned with `!range`. Never mind.

https://github.com/llvm/llvm-project/pull/199796