[llvm] [AMDGPU] Refactor insertRelease into insertWriteback + insertWait (NFC) (PR #199486)
Sameer Sahasrabuddhe via llvm-commits
llvm-commits at lists.llvm.org
Tue May 26 20:02:11 PDT 2026
================
@@ -442,17 +442,27 @@ class SICacheControl {
SIAtomicAddrSpace AddrSpace,
Position Pos) const = 0;
- /// Inserts any necessary instructions at position \p Pos relative to
- /// instruction \p MI to ensure previous memory instructions by this thread
- /// with address spaces \p AddrSpace have completed and can be observed by
- /// subsequent memory instructions by any thread executing in memory scope \p
- /// Scope. \p IsCrossAddrSpaceOrdering indicates if the memory ordering is
- /// between address spaces. Returns true iff any instructions inserted.
- virtual bool insertRelease(MachineBasicBlock::iterator &MI,
- SIAtomicScope Scope,
- SIAtomicAddrSpace AddrSpace,
- bool IsCrossAddrSpaceOrdering,
- Position Pos) const = 0;
+ /// Inserts any necessary writeback instructions at position \p Pos relative
+ /// to instruction \p MI to make previous memory operations by this thread
+ /// with address spaces \p AddrSpace available to other threads in memory
+ /// scope \p Scope. Does not insert waits; callers must call insertWait
+ /// separately. Returns true iff any instructions inserted.
+ virtual bool insertWriteback(MachineBasicBlock::iterator &MI,
+ SIAtomicScope Scope, SIAtomicAddrSpace AddrSpace,
+ Position Pos) const = 0;
+
+ /// Inserts writeback followed by an unconditional wait to implement a
+ /// release operation.
+ bool insertRelease(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
+ SIAtomicAddrSpace AddrSpace, bool IsCrossAddrSpaceOrdering,
+ Position Pos) const {
+ bool Changed = false;
+ Changed |= insertWriteback(MI, Scope, AddrSpace, Pos);
----------------
ssahasra wrote:
I'll go with @Pierre-vh's suggestion. It's preferable to have a patch complete in itself and let the next patch change things if/when it lands.
https://github.com/llvm/llvm-project/pull/199486
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