[llvm] [LV] Avoid stale VPTypeAnalysis cache in convertToStridedAccesses (PR #199222)
Mel Chen via llvm-commits
llvm-commits at lists.llvm.org
Fri May 22 08:57:29 PDT 2026
================
@@ -0,0 +1,136 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
+; RUN: opt < %s -passes=loop-vectorize -mtriple=riscv64 -mattr=+v -S | FileCheck %s
+
+define void @test(ptr %a, ptr %b, ptr %c, i32 %n, double %c0, double %c1, double %c2, i64 %c3) {
+; CHECK-LABEL: define void @test(
+; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i32 [[N:%.*]], double [[C0:%.*]], double [[C1:%.*]], double [[C2:%.*]], i64 [[C3:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[SMAX20:%.*]] = call i32 @llvm.smax.i32(i32 [[N]], i32 4)
+; CHECK-NEXT: [[TMP0:%.*]] = add nsw i32 [[SMAX20]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[TMP0]], 2
+; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i32 [[TMP1]], 1
+; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]]
+; CHECK: [[VECTOR_MEMCHECK]]:
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[A]], i64 8
+; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[C]], i64 8
+; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[N]], i32 4)
+; CHECK-NEXT: [[TMP3:%.*]] = add nsw i32 [[SMAX]], -1
+; CHECK-NEXT: [[TMP4:%.*]] = zext nneg i32 [[TMP3]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 2
+; CHECK-NEXT: [[TMP6:%.*]] = shl nuw nsw i64 [[TMP5]], 5
+; CHECK-NEXT: [[TMP7:%.*]] = add nuw nsw i64 [[TMP6]], 8
+; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP7]]
+; CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[C3]], 3
+; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP8]], 48
+; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP9]]
+; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[TMP8]], 56
+; CHECK-NEXT: [[SCEVGEP4:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP10]]
+; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[A]], [[SCEVGEP1]]
+; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[C]], [[SCEVGEP]]
+; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
+; CHECK-NEXT: [[BOUND05:%.*]] = icmp ult ptr [[A]], [[SCEVGEP2]]
+; CHECK-NEXT: [[BOUND16:%.*]] = icmp ult ptr [[B]], [[SCEVGEP]]
+; CHECK-NEXT: [[FOUND_CONFLICT7:%.*]] = and i1 [[BOUND05]], [[BOUND16]]
+; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT7]]
+; CHECK-NEXT: [[BOUND08:%.*]] = icmp ult ptr [[A]], [[SCEVGEP4]]
+; CHECK-NEXT: [[BOUND19:%.*]] = icmp ult ptr [[SCEVGEP3]], [[SCEVGEP]]
+; CHECK-NEXT: [[FOUND_CONFLICT10:%.*]] = and i1 [[BOUND08]], [[BOUND19]]
+; CHECK-NEXT: [[CONFLICT_RDX11:%.*]] = or i1 [[CONFLICT_RDX]], [[FOUND_CONFLICT10]]
+; CHECK-NEXT: [[BOUND012:%.*]] = icmp ult ptr [[C]], [[SCEVGEP2]]
+; CHECK-NEXT: [[BOUND113:%.*]] = icmp ult ptr [[B]], [[SCEVGEP1]]
+; CHECK-NEXT: [[FOUND_CONFLICT14:%.*]] = and i1 [[BOUND012]], [[BOUND113]]
+; CHECK-NEXT: [[CONFLICT_RDX15:%.*]] = or i1 [[CONFLICT_RDX11]], [[FOUND_CONFLICT14]]
+; CHECK-NEXT: [[BOUND016:%.*]] = icmp ult ptr [[C]], [[SCEVGEP4]]
+; CHECK-NEXT: [[BOUND117:%.*]] = icmp ult ptr [[SCEVGEP3]], [[SCEVGEP1]]
+; CHECK-NEXT: [[FOUND_CONFLICT18:%.*]] = and i1 [[BOUND016]], [[BOUND117]]
+; CHECK-NEXT: [[CONFLICT_RDX19:%.*]] = or i1 [[CONFLICT_RDX15]], [[FOUND_CONFLICT18]]
+; CHECK-NEXT: br i1 [[CONFLICT_RDX19]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x double> poison, double [[C0]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x double> [[BROADCAST_SPLATINSERT]], <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP11:%.*]] = fneg <vscale x 2 x double> [[BROADCAST_SPLAT]]
+; CHECK-NEXT: [[TMP12:%.*]] = fsub double 0.000000e+00, [[C1]]
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT27:%.*]] = insertelement <vscale x 2 x double> poison, double [[TMP12]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT28:%.*]] = shufflevector <vscale x 2 x double> [[BROADCAST_SPLATINSERT27]], <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr [8 x i8], ptr [[B]], i64 [[C3]]
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[TMP13]], i64 48
+; CHECK-NEXT: [[TMP15:%.*]] = load double, ptr [[TMP14]], align 8, !alias.scope [[META0:![0-9]+]]
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT25:%.*]] = insertelement <vscale x 2 x double> poison, double [[TMP15]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT26:%.*]] = shufflevector <vscale x 2 x double> [[BROADCAST_SPLATINSERT25]], <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT21:%.*]] = insertelement <vscale x 2 x double> poison, double [[C2]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT22:%.*]] = shufflevector <vscale x 2 x double> [[BROADCAST_SPLATINSERT21]], <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT23:%.*]] = insertelement <vscale x 2 x ptr> poison, ptr [[C]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT24:%.*]] = shufflevector <vscale x 2 x ptr> [[BROADCAST_SPLATINSERT23]], <vscale x 2 x ptr> poison, <vscale x 2 x i32> zeroinitializer
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[AVL:%.*]] = phi i32 [ [[TMP2]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP16:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 2, i1 true)
+; CHECK-NEXT: store double 0.000000e+00, ptr [[A]], align 8, !alias.scope [[META3:![0-9]+]], !noalias [[META5:![0-9]+]]
+; CHECK-NEXT: [[TMP17:%.*]] = shl i32 [[INDEX]], 5
+; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[B]], i32 [[TMP17]]
+; CHECK-NEXT: [[TMP19:%.*]] = call <vscale x 2 x double> @llvm.experimental.vp.strided.load.nxv2f64.p0.i32(ptr align 8 [[TMP18]], i32 32, <vscale x 2 x i1> splat (i1 true), i32 [[TMP16]]), !alias.scope [[META8:![0-9]+]]
+; CHECK-NEXT: [[TMP20:%.*]] = fsub <vscale x 2 x double> [[BROADCAST_SPLAT22]], [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = fmul <vscale x 2 x double> [[BROADCAST_SPLAT26]], [[TMP20]]
+; CHECK-NEXT: [[TMP22:%.*]] = call <vscale x 2 x double> @llvm.fmuladd.nxv2f64(<vscale x 2 x double> [[TMP11]], <vscale x 2 x double> [[BROADCAST_SPLAT28]], <vscale x 2 x double> [[TMP21]])
+; CHECK-NEXT: call void @llvm.vp.scatter.nxv2f64.nxv2p0(<vscale x 2 x double> [[TMP22]], <vscale x 2 x ptr> align 8 [[BROADCAST_SPLAT24]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP16]]), !alias.scope [[META9:![0-9]+]], !noalias [[META10:![0-9]+]]
+; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add nuw i32 [[TMP16]], [[INDEX]]
+; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP16]]
+; CHECK-NEXT: [[TMP23:%.*]] = icmp eq i32 [[AVL_NEXT]], 0
+; CHECK-NEXT: br i1 [[TMP23]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[EXIT:.*]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[NEG_C0:%.*]] = fneg double [[C0]]
+; CHECK-NEXT: [[IV_ADD:%.*]] = add i32 [[IV]], 1
+; CHECK-NEXT: [[IV_SEXT:%.*]] = sext i32 [[IV_ADD]] to i64
+; CHECK-NEXT: [[STRIDED_BASE:%.*]] = getelementptr [8 x i8], ptr [[B]], i64 [[IV_SEXT]]
+; CHECK-NEXT: [[NEG_C1:%.*]] = fsub double 0.000000e+00, [[C1]]
+; CHECK-NEXT: store double 0.000000e+00, ptr [[A]], align 8
+; CHECK-NEXT: [[UNIFORM_BASE:%.*]] = getelementptr [8 x i8], ptr [[B]], i64 [[C3]]
+; CHECK-NEXT: [[UNIFORM_PTR:%.*]] = getelementptr i8, ptr [[UNIFORM_BASE]], i64 48
+; CHECK-NEXT: [[UNIFORM_VAL:%.*]] = load double, ptr [[UNIFORM_PTR]], align 8
+; CHECK-NEXT: [[STRIDED_PTR:%.*]] = getelementptr i8, ptr [[STRIDED_BASE]], i64 -8
+; CHECK-NEXT: [[STRIDED_VAL:%.*]] = load double, ptr [[STRIDED_PTR]], align 8
+; CHECK-NEXT: [[DIFF:%.*]] = fsub double [[C2]], [[STRIDED_VAL]]
+; CHECK-NEXT: [[PROD:%.*]] = fmul double [[UNIFORM_VAL]], [[DIFF]]
+; CHECK-NEXT: [[RESULT:%.*]] = call double @llvm.fmuladd.f64(double [[NEG_C0]], double [[NEG_C1]], double [[PROD]])
+; CHECK-NEXT: store double [[RESULT]], ptr [[C]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add nsw i32 [[IV]], 4
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[IV_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP14:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [ 0, %entry ], [ %iv_next, %loop ]
+ %neg_c0 = fneg double %c0
+ %iv_add = add i32 %iv, 1
+ %iv_sext = sext i32 %iv_add to i64
+ %strided_base = getelementptr [8 x i8], ptr %b, i64 %iv_sext
+ %neg_c1 = fsub double 0.000000e+00, %c1
+ store double 0.000000e+00, ptr %a, align 8
+ %uniform_base = getelementptr [8 x i8], ptr %b, i64 %c3
+ %uniform_ptr = getelementptr i8, ptr %uniform_base, i64 48
+ %uniform_val = load double, ptr %uniform_ptr, align 8
+ %strided_ptr = getelementptr i8, ptr %strided_base, i64 -8
+ %strided_val = load double, ptr %strided_ptr, align 8
+ %diff = fsub double %c2, %strided_val
+ %prod = fmul double %uniform_val, %diff
+ %result = call double @llvm.fmuladd.f64(double %neg_c0, double %neg_c1, double %prod)
+ store double %result, ptr %c, align 8
+ %iv_next = add nsw i32 %iv, 4
+ %cmp = icmp slt i32 %iv_next, %n
+ br i1 %cmp, label %loop, label %exit
+
+exit:
+ ret void
+}
+
+declare double @llvm.fmuladd.f64(double, double, double)
----------------
Mel-Chen wrote:
done
https://github.com/llvm/llvm-project/pull/199222
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