[llvm] 7bcc8e6 - [CostModel][X86] Update VECREDUCE MINMAX costs based off llvm-mca analysis (#199208)
via llvm-commits
llvm-commits at lists.llvm.org
Sat May 23 01:13:43 PDT 2026
Author: Simon Pilgrim
Date: 2026-05-23T08:13:37Z
New Revision: 7bcc8e6f74bb8b38af3d539dc2cc36f8a16cc526
URL: https://github.com/llvm/llvm-project/commit/7bcc8e6f74bb8b38af3d539dc2cc36f8a16cc526
DIFF: https://github.com/llvm/llvm-project/commit/7bcc8e6f74bb8b38af3d539dc2cc36f8a16cc526.diff
LOG: [CostModel][X86] Update VECREDUCE MINMAX costs based off llvm-mca analysis (#199208)
Add full CostKinds, to improve a lot of reduction matching in
vectorcombine/slp passes
These are based off SMIN/UMIN numbers, and a few SMAX/UMAX numbers don't
always match, but are typically within +/-1
Added:
Modified:
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/test/Analysis/CostModel/X86/reduce-smax.ll
llvm/test/Analysis/CostModel/X86/reduce-smin.ll
llvm/test/Analysis/CostModel/X86/reduce-umax.ll
llvm/test/Analysis/CostModel/X86/reduce-umin.ll
llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smax.ll
llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smin.ll
llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umax.ll
llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umin.ll
llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
llvm/test/Transforms/SLPVectorizer/X86/horizontal-smax.ll
llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll
llvm/test/Transforms/VectorCombine/X86/fold-equivalent-reduction-cmp.ll
llvm/test/Transforms/VectorCombine/X86/fold-signbit-reduction-cmp.ll
llvm/test/Transforms/VectorCombine/X86/icmp-vector-reduce.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index e4a897b43e652..ad281af054f78 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -5904,7 +5904,7 @@ X86TTIImpl::getMinMaxReductionCost(Intrinsic::ID IID, VectorType *ValTy,
MVT MTy = LT.second;
- int ISD;
+ ISD::NodeType ISD;
if (ValTy->isIntOrIntVectorTy()) {
ISD = (IID == Intrinsic::umin || IID == Intrinsic::umax) ? ISD::UMIN
: ISD::SMIN;
@@ -5916,44 +5916,103 @@ X86TTIImpl::getMinMaxReductionCost(Intrinsic::ID IID, VectorType *ValTy,
: ISD::FMINIMUM;
}
- // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
- // and make it as the cost.
+ // We use llvm-mca across all supported CPUs to measure the cost stats.
+ static const CostKindTblEntry SSE2CostTbl[] = {
+ {ISD::SMIN, MVT::v2i64, {3, 4, 5, 6}},
+ {ISD::UMIN, MVT::v2i64, {3, 4, 5, 6}},
+ {ISD::SMIN, MVT::v2i32, {2, 2, 5, 6}},
+ {ISD::UMIN, MVT::v2i32, {2, 2, 5, 6}},
+ {ISD::SMIN, MVT::v4i32, {3, 7,11,12}},
+ {ISD::UMIN, MVT::v4i32, {4, 7,14,15}},
+ {ISD::SMIN, MVT::v2i16, {2, 3, 4, 4}},
+ {ISD::UMIN, MVT::v2i16, {2, 3, 4, 6}},
+ {ISD::SMIN, MVT::v4i16, {3, 5, 6, 6}},
+ {ISD::UMIN, MVT::v4i16, {3, 5, 8, 10}},
+ {ISD::SMIN, MVT::v8i16, {3, 8, 8, 8}},
+ {ISD::UMIN, MVT::v8i16, {4, 8,12,14}},
+ {ISD::SMIN, MVT::v2i8, {2, 3, 5, 6}},
+ {ISD::UMIN, MVT::v2i8, {2, 3, 4, 4}},
+ {ISD::SMIN, MVT::v4i8, {4, 6,12,13}},
+ {ISD::UMIN, MVT::v4i8, {3, 6, 7, 7}},
+ {ISD::SMIN, MVT::v8i8, {5, 9,18,19}},
+ {ISD::UMIN, MVT::v8i8, {4, 8, 9, 9}},
+ {ISD::SMIN, MVT::v16i8, {7,13,24,25}},
+ {ISD::UMIN, MVT::v16i8, {3,10,11,11}},
+ };
- static const CostTblEntry SSE2CostTbl[] = {
- {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw
- {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw
- {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw
+ static const CostKindTblEntry SSE41CostTbl[] = {
+ {ISD::SMIN, MVT::v2i64, {3, 4, 4, 6}},
+ {ISD::UMIN, MVT::v2i64, {3, 4, 4, 6}},
+ {ISD::SMIN, MVT::v2i32, {2, 2, 3, 3}},
+ {ISD::UMIN, MVT::v2i32, {2, 2, 3, 3}},
+ {ISD::SMIN, MVT::v4i32, {3, 4, 5, 5}},
+ {ISD::UMIN, MVT::v4i32, {3, 4, 5, 5}},
+ {ISD::UMIN, MVT::v2i16, {2, 3, 4, 4}},
+ {ISD::SMIN, MVT::v4i16, {3, 5, 6, 6}},
+ {ISD::UMIN, MVT::v4i16, {3, 5, 6, 6}},
+ {ISD::SMIN, MVT::v8i16, {2, 8, 4, 5}},
+ {ISD::UMIN, MVT::v8i16, {2, 5, 2, 2}},
+ {ISD::SMIN, MVT::v2i8, {2, 3, 4, 4}},
+ {ISD::SMIN, MVT::v4i8, {3, 6, 7, 7}},
+ {ISD::SMIN, MVT::v8i8, {4, 8, 9, 9}},
+ {ISD::SMIN, MVT::v16i8, {3,10, 7, 8}},
+ {ISD::UMIN, MVT::v16i8, {3, 8, 5, 5}},
};
- static const CostTblEntry SSE41CostTbl[] = {
- {ISD::SMIN, MVT::v2i16, 3}, // same as sse2
- {ISD::SMIN, MVT::v4i16, 5}, // same as sse2
- {ISD::UMIN, MVT::v2i16, 5}, // same as sse2
- {ISD::UMIN, MVT::v4i16, 7}, // same as sse2
- {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor
- {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax
- {ISD::SMIN, MVT::v2i8, 3}, // pminsb
- {ISD::SMIN, MVT::v4i8, 5}, // pminsb
- {ISD::SMIN, MVT::v8i8, 7}, // pminsb
- {ISD::SMIN, MVT::v16i8, 6},
- {ISD::UMIN, MVT::v2i8, 3}, // same as sse2
- {ISD::UMIN, MVT::v4i8, 5}, // same as sse2
- {ISD::UMIN, MVT::v8i8, 7}, // same as sse2
- {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax
+ static const CostKindTblEntry AVX1CostTbl[] = {
+ {ISD::SMIN, MVT::v4i64, {5,11, 7,10}},
+ {ISD::UMIN, MVT::v4i64, {6,12,10,13}},
+ {ISD::SMIN, MVT::v8i32, {4, 9, 7, 7}},
+ {ISD::UMIN, MVT::v8i32, {4, 9, 7, 7}},
+ {ISD::SMIN, MVT::v16i16, {3,15, 6, 7}},
+ {ISD::UMIN, MVT::v16i16, {2, 9, 4, 4}},
+ {ISD::SMIN, MVT::v32i8, {4,17, 8, 9}},
+ {ISD::UMIN, MVT::v32i8, {3,11, 6, 6}},
};
- static const CostTblEntry AVX1CostTbl[] = {
- {ISD::SMIN, MVT::v16i16, 6},
- {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax
- {ISD::SMIN, MVT::v32i8, 8},
- {ISD::UMIN, MVT::v32i8, 8},
+ static const CostKindTblEntry AVX2CostTbl[] = {
+ {ISD::SMIN, MVT::v4i64, {4,11, 7,10}},
+ {ISD::UMIN, MVT::v4i64, {4,12,10,13}},
+ {ISD::SMIN, MVT::v2i32, {1, 2, 3, 3}},
+ {ISD::UMIN, MVT::v2i32, {1, 2, 3, 3}},
+ {ISD::UMIN, MVT::v4i32, {2, 4, 5, 5}},
+ {ISD::SMIN, MVT::v4i32, {2, 4, 5, 5}},
+ {ISD::SMIN, MVT::v8i32, {3, 9, 7, 7}},
+ {ISD::UMIN, MVT::v8i32, {3, 9, 7, 7}},
+ {ISD::SMIN, MVT::v4i16, {2, 4, 5, 5}},
+ {ISD::UMIN, MVT::v4i16, {2, 4, 5, 5}},
+ {ISD::SMIN, MVT::v16i16, {2,15, 6, 7}},
+ {ISD::SMIN, MVT::v8i8, {3, 6, 7, 7}},
+ {ISD::UMIN, MVT::v8i8, {3, 6, 7, 7}},
+ {ISD::SMIN, MVT::v32i8, {3,17, 8, 9}},
+ };
+
+ static const CostKindTblEntry AVX512FCostTbl[] = {
+ {ISD::SMIN, MVT::v2i64, {2, 4, 3, 3}},
+ {ISD::UMIN, MVT::v2i64, {2, 4, 3, 3}},
+ {ISD::SMIN, MVT::v4i64, {3,10, 5, 5}},
+ {ISD::UMIN, MVT::v4i64, {3,10, 5, 5}},
+ {ISD::SMIN, MVT::v8i64, {5,16, 7, 7}},
+ {ISD::UMIN, MVT::v8i64, {5,16, 7, 7}},
+ {ISD::SMIN, MVT::v16i32, {4,12, 9, 9}},
+ {ISD::UMIN, MVT::v16i32, {4,12, 9, 9}},
};
- static const CostTblEntry AVX512BWCostTbl[] = {
- {ISD::SMIN, MVT::v32i16, 8},
- {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax
- {ISD::SMIN, MVT::v64i8, 10},
- {ISD::UMIN, MVT::v64i8, 10},
+ static const CostKindTblEntry AVX512BWCostTbl[] = {
+ {ISD::SMIN, MVT::v2i16, {1, 2, 3, 3}},
+ {ISD::UMIN, MVT::v2i16, {1, 2, 3, 3}},
+ {ISD::SMIN, MVT::v32i16, {2,19, 8, 9}},
+ {ISD::UMIN, MVT::v32i16, {2,12, 6, 6}},
+ {ISD::SMIN, MVT::v2i8, {1, 2, 3, 3}},
+ {ISD::UMIN, MVT::v2i8, {1, 2, 3, 3}},
+ {ISD::SMIN, MVT::v4i8, {2, 4, 5, 5}},
+ {ISD::UMIN, MVT::v4i8, {2, 4, 5, 5}},
+ {ISD::SMIN, MVT::v16i8, {2,10, 6, 7}},
+ {ISD::UMIN, MVT::v16i8, {2, 6, 4, 4}},
+ {ISD::SMIN, MVT::v32i8, {2,17, 8, 9}},
+ {ISD::UMIN, MVT::v32i8, {2,10, 6, 6}},
+ {ISD::SMIN, MVT::v64i8, {2,21,10,11}},
+ {ISD::UMIN, MVT::v64i8, {2,14, 8, 8}},
};
// Before legalizing the type, give a chance to look up illegal narrow types
@@ -5964,19 +6023,33 @@ X86TTIImpl::getMinMaxReductionCost(Intrinsic::ID IID, VectorType *ValTy,
MVT MTy = VT.getSimpleVT();
if (ST->hasBWI())
if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
- return Entry->Cost;
+ if (auto KindCost = Entry->Cost[CostKind])
+ return *KindCost;
+
+ if (ST->hasAVX512())
+ if (const auto *Entry = CostTableLookup(AVX512FCostTbl, ISD, MTy))
+ if (auto KindCost = Entry->Cost[CostKind])
+ return *KindCost;
+
+ if (ST->hasAVX2())
+ if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
+ if (auto KindCost = Entry->Cost[CostKind])
+ return *KindCost;
if (ST->hasAVX())
if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
- return Entry->Cost;
+ if (auto KindCost = Entry->Cost[CostKind])
+ return *KindCost;
if (ST->hasSSE41())
if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
- return Entry->Cost;
+ if (auto KindCost = Entry->Cost[CostKind])
+ return *KindCost;
if (ST->hasSSE2())
if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
- return Entry->Cost;
+ if (auto KindCost = Entry->Cost[CostKind])
+ return *KindCost;
}
auto *ValVTy = cast<FixedVectorType>(ValTy);
@@ -5996,19 +6069,33 @@ X86TTIImpl::getMinMaxReductionCost(Intrinsic::ID IID, VectorType *ValTy,
if (ST->hasBWI())
if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
- return MinMaxCost + Entry->Cost;
+ if (auto KindCost = Entry->Cost[CostKind])
+ return MinMaxCost + *KindCost;
+
+ if (ST->hasAVX512())
+ if (const auto *Entry = CostTableLookup(AVX512FCostTbl, ISD, MTy))
+ if (auto KindCost = Entry->Cost[CostKind])
+ return MinMaxCost + *KindCost;
+
+ if (ST->hasAVX2())
+ if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
+ if (auto KindCost = Entry->Cost[CostKind])
+ return MinMaxCost + *KindCost;
if (ST->hasAVX())
if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
- return MinMaxCost + Entry->Cost;
+ if (auto KindCost = Entry->Cost[CostKind])
+ return MinMaxCost + *KindCost;
if (ST->hasSSE41())
if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
- return MinMaxCost + Entry->Cost;
+ if (auto KindCost = Entry->Cost[CostKind])
+ return MinMaxCost + *KindCost;
if (ST->hasSSE2())
if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
- return MinMaxCost + Entry->Cost;
+ if (auto KindCost = Entry->Cost[CostKind])
+ return MinMaxCost + *KindCost;
unsigned ScalarSize = ValTy->getScalarSizeInBits();
diff --git a/llvm/test/Analysis/CostModel/X86/reduce-smax.ll b/llvm/test/Analysis/CostModel/X86/reduce-smax.ll
index f11229e313d3a..490fea16ae26a 100644
--- a/llvm/test/Analysis/CostModel/X86/reduce-smax.ll
+++ b/llvm/test/Analysis/CostModel/X86/reduce-smax.ll
@@ -12,50 +12,50 @@
define i32 @reduce_i64(i32 %arg) {
; SSE2-LABEL: 'reduce_i64'
; SSE2-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:17 Lat:10 SizeLat:17 for: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:32 Lat:18 SizeLat:32 for: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:18 CodeSize:62 Lat:34 SizeLat:62 for: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:34 CodeSize:122 Lat:66 SizeLat:122 for: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:4 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:20 Lat:12 SizeLat:21 for: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:15 CodeSize:50 Lat:28 SizeLat:51 for: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:31 CodeSize:110 Lat:60 SizeLat:111 for: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSSE3-LABEL: 'reduce_i64'
; SSSE3-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:6 CodeSize:17 Lat:10 SizeLat:17 for: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:10 CodeSize:32 Lat:18 SizeLat:32 for: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:18 CodeSize:62 Lat:34 SizeLat:62 for: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:34 CodeSize:122 Lat:66 SizeLat:122 for: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:4 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:7 CodeSize:20 Lat:12 SizeLat:21 for: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:15 CodeSize:50 Lat:28 SizeLat:51 for: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:31 CodeSize:110 Lat:60 SizeLat:111 for: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSE4-LABEL: 'reduce_i64'
; SSE4-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
-; SSE4-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:9 SizeLat:5 for: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
-; SSE4-NEXT: Cost Model: Found costs of RThru:8 CodeSize:6 Lat:16 SizeLat:8 for: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
-; SSE4-NEXT: Cost Model: Found costs of RThru:14 CodeSize:10 Lat:30 SizeLat:14 for: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
-; SSE4-NEXT: Cost Model: Found costs of RThru:26 CodeSize:18 Lat:58 SizeLat:26 for: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:6 CodeSize:6 Lat:11 SizeLat:9 for: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:12 CodeSize:10 Lat:25 SizeLat:15 for: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:24 CodeSize:18 Lat:53 SizeLat:27 for: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
; SSE4-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX1-LABEL: 'reduce_i64'
; AVX1-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:9 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:9 CodeSize:7 Lat:17 SizeLat:11 for: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:15 CodeSize:13 Lat:26 SizeLat:23 for: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:27 CodeSize:25 Lat:44 SizeLat:47 for: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:5 CodeSize:7 Lat:11 SizeLat:10 for: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:11 CodeSize:13 Lat:20 SizeLat:22 for: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:23 CodeSize:25 Lat:38 SizeLat:46 for: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX2-LABEL: 'reduce_i64'
; AVX2-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:4 Lat:9 SizeLat:5 for: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:17 SizeLat:9 for: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:9 Lat:24 SizeLat:12 for: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:13 CodeSize:13 Lat:38 SizeLat:18 for: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:7 Lat:11 SizeLat:10 for: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:9 Lat:18 SizeLat:13 for: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:13 Lat:32 SizeLat:19 for: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512-LABEL: 'reduce_i64'
; AVX512-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:3 CodeSize:3 Lat:7 SizeLat:3 for: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:5 CodeSize:5 Lat:11 SizeLat:5 for: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:15 SizeLat:7 for: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:8 CodeSize:8 Lat:18 SizeLat:8 for: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:4 SizeLat:3 for: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:10 SizeLat:5 for: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:5 CodeSize:7 Lat:16 SizeLat:7 for: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:6 CodeSize:8 Lat:19 SizeLat:8 for: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
; AVX512-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
@@ -68,51 +68,51 @@ define i32 @reduce_i64(i32 %arg) {
define i32 @reduce_i32(i32 %arg) {
; SSE2-LABEL: 'reduce_i32'
-; SSE2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:7 Lat:6 SizeLat:7 for: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:13 Lat:11 SizeLat:13 for: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:18 Lat:15 SizeLat:18 for: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:13 CodeSize:28 Lat:23 SizeLat:28 for: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:21 CodeSize:48 Lat:39 SizeLat:48 for: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:2 SizeLat:6 for: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:11 Lat:7 SizeLat:12 for: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:16 Lat:11 SizeLat:17 for: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:26 Lat:19 SizeLat:27 for: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:17 CodeSize:46 Lat:35 SizeLat:47 for: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSSE3-LABEL: 'reduce_i32'
-; SSSE3-NEXT: Cost Model: Found costs of RThru:4 CodeSize:7 Lat:6 SizeLat:7 for: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:7 CodeSize:13 Lat:11 SizeLat:13 for: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:9 CodeSize:18 Lat:15 SizeLat:18 for: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:13 CodeSize:28 Lat:23 SizeLat:28 for: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:21 CodeSize:48 Lat:39 SizeLat:48 for: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:2 SizeLat:6 for: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:3 CodeSize:11 Lat:7 SizeLat:12 for: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:5 CodeSize:16 Lat:11 SizeLat:17 for: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:9 CodeSize:26 Lat:19 SizeLat:27 for: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:17 CodeSize:46 Lat:35 SizeLat:47 for: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSE4-LABEL: 'reduce_i32'
-; SSE4-NEXT: Cost Model: Found costs of 3 for: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
-; SSE4-NEXT: Cost Model: Found costs of 5 for: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
-; SSE4-NEXT: Cost Model: Found costs of 6 for: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
-; SSE4-NEXT: Cost Model: Found costs of 8 for: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
-; SSE4-NEXT: Cost Model: Found costs of 12 for: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:4 CodeSize:6 Lat:5 SizeLat:6 for: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:6 CodeSize:8 Lat:7 SizeLat:8 for: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:10 CodeSize:12 Lat:11 SizeLat:12 for: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
; SSE4-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX1-LABEL: 'reduce_i32'
-; AVX1-NEXT: Cost Model: Found costs of 3 for: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
-; AVX1-NEXT: Cost Model: Found costs of 5 for: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
-; AVX1-NEXT: Cost Model: Found costs of 7 for: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:11 CodeSize:12 Lat:13 SizeLat:13 for: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:19 CodeSize:22 Lat:25 SizeLat:25 for: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:4 CodeSize:7 Lat:9 SizeLat:7 for: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:8 CodeSize:12 Lat:15 SizeLat:13 for: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:16 CodeSize:22 Lat:27 SizeLat:25 for: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX2-LABEL: 'reduce_i32'
-; AVX2-NEXT: Cost Model: Found costs of 3 for: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
-; AVX2-NEXT: Cost Model: Found costs of 5 for: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
-; AVX2-NEXT: Cost Model: Found costs of 7 for: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:8 Lat:8 SizeLat:9 for: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:10 Lat:10 SizeLat:13 for: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:9 SizeLat:7 for: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:8 Lat:10 SizeLat:9 for: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:10 Lat:12 SizeLat:13 for: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512-LABEL: 'reduce_i32'
-; AVX512-NEXT: Cost Model: Found costs of RThru:3 CodeSize:3 Lat:5 SizeLat:3 for: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:5 CodeSize:5 Lat:9 SizeLat:5 for: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:11 SizeLat:7 for: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:9 CodeSize:9 Lat:13 SizeLat:10 for: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:10 CodeSize:10 Lat:14 SizeLat:11 for: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:9 SizeLat:7 for: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:12 SizeLat:9 for: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:5 CodeSize:10 Lat:13 SizeLat:10 for: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
; AVX512-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
@@ -125,73 +125,73 @@ define i32 @reduce_i32(i32 %arg) {
define i32 @reduce_i16(i32 %arg) {
; SSE2-LABEL: 'reduce_i16'
-; SSE2-NEXT: Cost Model: Found costs of 3 for: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
-; SSE2-NEXT: Cost Model: Found costs of 5 for: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
-; SSE2-NEXT: Cost Model: Found costs of 7 for: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
-; SSE2-NEXT: Cost Model: Found costs of 8 for: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
-; SSE2-NEXT: Cost Model: Found costs of 10 for: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
-; SSE2-NEXT: Cost Model: Found costs of 14 for: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:5 SizeLat:6 for: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:8 Lat:8 SizeLat:8 for: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:9 SizeLat:9 for: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:11 Lat:11 SizeLat:11 for: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:15 Lat:15 SizeLat:15 for: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSSE3-LABEL: 'reduce_i16'
-; SSSE3-NEXT: Cost Model: Found costs of 3 for: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 5 for: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 7 for: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 8 for: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 10 for: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 14 for: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:5 SizeLat:6 for: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:3 CodeSize:8 Lat:8 SizeLat:8 for: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:9 SizeLat:9 for: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:6 CodeSize:11 Lat:11 SizeLat:11 for: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:10 CodeSize:15 Lat:15 SizeLat:15 for: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSE4-LABEL: 'reduce_i16'
-; SSE4-NEXT: Cost Model: Found costs of 3 for: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
-; SSE4-NEXT: Cost Model: Found costs of 5 for: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
-; SSE4-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
-; SSE4-NEXT: Cost Model: Found costs of 5 for: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
-; SSE4-NEXT: Cost Model: Found costs of 7 for: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
-; SSE4-NEXT: Cost Model: Found costs of 11 for: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:5 SizeLat:6 for: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:8 SizeLat:5 for: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:9 SizeLat:6 for: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:5 CodeSize:7 Lat:11 SizeLat:8 for: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:9 CodeSize:11 Lat:15 SizeLat:12 for: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
; SSE4-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX1-LABEL: 'reduce_i16'
-; AVX1-NEXT: Cost Model: Found costs of 3 for: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
-; AVX1-NEXT: Cost Model: Found costs of 5 for: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
-; AVX1-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
-; AVX1-NEXT: Cost Model: Found costs of 6 for: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:10 CodeSize:11 Lat:12 SizeLat:12 for: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:18 CodeSize:21 Lat:24 SizeLat:24 for: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:5 SizeLat:6 for: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:8 SizeLat:5 for: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:15 SizeLat:7 for: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:7 CodeSize:11 Lat:21 SizeLat:13 for: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:15 CodeSize:21 Lat:33 SizeLat:25 for: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX2-LABEL: 'reduce_i16'
-; AVX2-NEXT: Cost Model: Found costs of 3 for: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
-; AVX2-NEXT: Cost Model: Found costs of 5 for: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
-; AVX2-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
-; AVX2-NEXT: Cost Model: Found costs of 6 for: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:7 SizeLat:8 for: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:9 Lat:9 SizeLat:12 for: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:8 SizeLat:5 for: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:6 Lat:15 SizeLat:7 for: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:16 SizeLat:9 for: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:9 Lat:18 SizeLat:13 for: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512F-LABEL: 'reduce_i16'
-; AVX512F-NEXT: Cost Model: Found costs of 3 for: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 5 for: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 6 for: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:8 SizeLat:5 for: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:6 Lat:15 SizeLat:7 for: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:11 CodeSize:11 Lat:15 SizeLat:12 for: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:14 CodeSize:16 Lat:22 SizeLat:17 for: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512BW-LABEL: 'reduce_i16'
-; AVX512BW-NEXT: Cost Model: Found costs of 3 for: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 5 for: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 6 for: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 8 for: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 9 for: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:8 SizeLat:5 for: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:6 Lat:15 SizeLat:7 for: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:8 Lat:19 SizeLat:9 for: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:3 CodeSize:9 Lat:20 SizeLat:10 for: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
; AVX512BW-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512DQ-LABEL: 'reduce_i16'
-; AVX512DQ-NEXT: Cost Model: Found costs of 3 for: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 5 for: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 6 for: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:8 SizeLat:5 for: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:6 Lat:15 SizeLat:7 for: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:11 CodeSize:11 Lat:15 SizeLat:12 for: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:14 CodeSize:16 Lat:22 SizeLat:17 for: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
@@ -207,81 +207,81 @@ define i32 @reduce_i16(i32 %arg) {
define i32 @reduce_i8(i32 %arg) {
; SSE2-LABEL: 'reduce_i8'
-; SSE2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:7 Lat:6 SizeLat:7 for: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:13 Lat:11 SizeLat:13 for: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:19 Lat:16 SizeLat:19 for: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:13 CodeSize:25 Lat:21 SizeLat:25 for: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:15 CodeSize:30 Lat:25 SizeLat:30 for: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:19 CodeSize:40 Lat:33 SizeLat:40 for: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:27 CodeSize:60 Lat:49 SizeLat:60 for: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:3 SizeLat:6 for: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:12 Lat:6 SizeLat:13 for: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:18 Lat:9 SizeLat:19 for: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:24 Lat:13 SizeLat:25 for: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:29 Lat:17 SizeLat:30 for: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:13 CodeSize:39 Lat:25 SizeLat:40 for: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:21 CodeSize:59 Lat:41 SizeLat:60 for: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSSE3-LABEL: 'reduce_i8'
-; SSSE3-NEXT: Cost Model: Found costs of RThru:4 CodeSize:7 Lat:6 SizeLat:7 for: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:7 CodeSize:13 Lat:11 SizeLat:13 for: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:10 CodeSize:19 Lat:16 SizeLat:19 for: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:13 CodeSize:25 Lat:21 SizeLat:25 for: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:15 CodeSize:30 Lat:25 SizeLat:30 for: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:19 CodeSize:40 Lat:33 SizeLat:40 for: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:27 CodeSize:60 Lat:49 SizeLat:60 for: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:3 SizeLat:6 for: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:4 CodeSize:12 Lat:6 SizeLat:13 for: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:5 CodeSize:18 Lat:9 SizeLat:19 for: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:7 CodeSize:24 Lat:13 SizeLat:25 for: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:9 CodeSize:29 Lat:17 SizeLat:30 for: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:13 CodeSize:39 Lat:25 SizeLat:40 for: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:21 CodeSize:59 Lat:41 SizeLat:60 for: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSE4-LABEL: 'reduce_i8'
-; SSE4-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 7 for: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 9 for: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 13 for: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:8 SizeLat:9 for: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:10 SizeLat:8 for: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:4 CodeSize:8 Lat:11 SizeLat:9 for: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:6 CodeSize:10 Lat:13 SizeLat:11 for: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:10 CodeSize:14 Lat:17 SizeLat:15 for: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
; SSE4-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX1-LABEL: 'reduce_i8'
-; AVX1-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of 8 for: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:12 CodeSize:13 Lat:14 SizeLat:14 for: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:20 CodeSize:23 Lat:26 SizeLat:26 for: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:8 SizeLat:9 for: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:10 SizeLat:8 for: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:4 CodeSize:8 Lat:17 SizeLat:9 for: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:8 CodeSize:13 Lat:23 SizeLat:15 for: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:16 CodeSize:23 Lat:35 SizeLat:27 for: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX2-LABEL: 'reduce_i8'
-; AVX2-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of 8 for: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:9 Lat:9 SizeLat:10 for: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:11 CodeSize:11 Lat:11 SizeLat:14 for: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:10 SizeLat:8 for: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:8 Lat:17 SizeLat:9 for: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:18 SizeLat:11 for: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:11 Lat:20 SizeLat:15 for: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512F-LABEL: 'reduce_i8'
-; AVX512F-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 8 for: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:10 SizeLat:8 for: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:8 Lat:17 SizeLat:9 for: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:13 CodeSize:13 Lat:17 SizeLat:14 for: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:16 CodeSize:18 Lat:24 SizeLat:19 for: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512BW-LABEL: 'reduce_i8'
-; AVX512BW-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 8 for: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 10 for: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 11 for: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:6 Lat:10 SizeLat:7 for: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:8 Lat:17 SizeLat:9 for: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:10 Lat:21 SizeLat:11 for: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:3 CodeSize:11 Lat:22 SizeLat:12 for: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
; AVX512BW-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512DQ-LABEL: 'reduce_i8'
-; AVX512DQ-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 8 for: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:10 SizeLat:8 for: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:3 CodeSize:8 Lat:17 SizeLat:9 for: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:13 CodeSize:13 Lat:17 SizeLat:14 for: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:16 CodeSize:18 Lat:24 SizeLat:19 for: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
diff --git a/llvm/test/Analysis/CostModel/X86/reduce-smin.ll b/llvm/test/Analysis/CostModel/X86/reduce-smin.ll
index 5ae31798de6c5..36b1bcec20c06 100644
--- a/llvm/test/Analysis/CostModel/X86/reduce-smin.ll
+++ b/llvm/test/Analysis/CostModel/X86/reduce-smin.ll
@@ -12,50 +12,50 @@
define i32 @reduce_i64(i32 %arg) {
; SSE2-LABEL: 'reduce_i64'
; SSE2-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:17 Lat:10 SizeLat:17 for: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:32 Lat:18 SizeLat:32 for: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:18 CodeSize:62 Lat:34 SizeLat:62 for: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:34 CodeSize:122 Lat:66 SizeLat:122 for: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:4 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:20 Lat:12 SizeLat:21 for: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:15 CodeSize:50 Lat:28 SizeLat:51 for: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:31 CodeSize:110 Lat:60 SizeLat:111 for: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSSE3-LABEL: 'reduce_i64'
; SSSE3-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:6 CodeSize:17 Lat:10 SizeLat:17 for: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:10 CodeSize:32 Lat:18 SizeLat:32 for: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:18 CodeSize:62 Lat:34 SizeLat:62 for: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:34 CodeSize:122 Lat:66 SizeLat:122 for: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:4 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:7 CodeSize:20 Lat:12 SizeLat:21 for: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:15 CodeSize:50 Lat:28 SizeLat:51 for: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:31 CodeSize:110 Lat:60 SizeLat:111 for: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSE4-LABEL: 'reduce_i64'
; SSE4-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
-; SSE4-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:9 SizeLat:5 for: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
-; SSE4-NEXT: Cost Model: Found costs of RThru:8 CodeSize:6 Lat:16 SizeLat:8 for: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
-; SSE4-NEXT: Cost Model: Found costs of RThru:14 CodeSize:10 Lat:30 SizeLat:14 for: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
-; SSE4-NEXT: Cost Model: Found costs of RThru:26 CodeSize:18 Lat:58 SizeLat:26 for: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:6 CodeSize:6 Lat:11 SizeLat:9 for: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:12 CodeSize:10 Lat:25 SizeLat:15 for: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:24 CodeSize:18 Lat:53 SizeLat:27 for: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
; SSE4-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX1-LABEL: 'reduce_i64'
; AVX1-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:9 SizeLat:5 for: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:9 CodeSize:7 Lat:17 SizeLat:9 for: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:15 CodeSize:13 Lat:26 SizeLat:21 for: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:27 CodeSize:25 Lat:44 SizeLat:45 for: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:5 CodeSize:7 Lat:11 SizeLat:10 for: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:11 CodeSize:13 Lat:20 SizeLat:22 for: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:23 CodeSize:25 Lat:38 SizeLat:46 for: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX2-LABEL: 'reduce_i64'
; AVX2-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:4 Lat:9 SizeLat:5 for: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:17 SizeLat:9 for: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:9 Lat:24 SizeLat:12 for: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:13 CodeSize:13 Lat:38 SizeLat:18 for: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:7 Lat:11 SizeLat:10 for: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:9 Lat:18 SizeLat:13 for: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:13 Lat:32 SizeLat:19 for: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512-LABEL: 'reduce_i64'
; AVX512-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:3 CodeSize:3 Lat:7 SizeLat:3 for: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:5 CodeSize:5 Lat:11 SizeLat:5 for: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:15 SizeLat:7 for: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:8 CodeSize:8 Lat:18 SizeLat:8 for: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:4 SizeLat:3 for: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:10 SizeLat:5 for: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:5 CodeSize:7 Lat:16 SizeLat:7 for: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:6 CodeSize:8 Lat:19 SizeLat:8 for: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
; AVX512-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
@@ -68,51 +68,51 @@ define i32 @reduce_i64(i32 %arg) {
define i32 @reduce_i32(i32 %arg) {
; SSE2-LABEL: 'reduce_i32'
-; SSE2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:7 Lat:6 SizeLat:7 for: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:13 Lat:11 SizeLat:13 for: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:18 Lat:15 SizeLat:18 for: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:13 CodeSize:28 Lat:23 SizeLat:28 for: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:21 CodeSize:48 Lat:39 SizeLat:48 for: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:2 SizeLat:6 for: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:11 Lat:7 SizeLat:12 for: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:16 Lat:11 SizeLat:17 for: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:26 Lat:19 SizeLat:27 for: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:17 CodeSize:46 Lat:35 SizeLat:47 for: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSSE3-LABEL: 'reduce_i32'
-; SSSE3-NEXT: Cost Model: Found costs of RThru:4 CodeSize:7 Lat:6 SizeLat:7 for: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:7 CodeSize:13 Lat:11 SizeLat:13 for: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:9 CodeSize:18 Lat:15 SizeLat:18 for: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:13 CodeSize:28 Lat:23 SizeLat:28 for: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:21 CodeSize:48 Lat:39 SizeLat:48 for: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:2 SizeLat:6 for: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:3 CodeSize:11 Lat:7 SizeLat:12 for: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:5 CodeSize:16 Lat:11 SizeLat:17 for: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:9 CodeSize:26 Lat:19 SizeLat:27 for: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:17 CodeSize:46 Lat:35 SizeLat:47 for: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSE4-LABEL: 'reduce_i32'
-; SSE4-NEXT: Cost Model: Found costs of 3 for: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
-; SSE4-NEXT: Cost Model: Found costs of 5 for: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
-; SSE4-NEXT: Cost Model: Found costs of 6 for: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
-; SSE4-NEXT: Cost Model: Found costs of 8 for: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
-; SSE4-NEXT: Cost Model: Found costs of 12 for: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:4 CodeSize:6 Lat:5 SizeLat:6 for: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:6 CodeSize:8 Lat:7 SizeLat:8 for: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:10 CodeSize:12 Lat:11 SizeLat:12 for: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
; SSE4-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX1-LABEL: 'reduce_i32'
-; AVX1-NEXT: Cost Model: Found costs of 3 for: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
-; AVX1-NEXT: Cost Model: Found costs of 5 for: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
-; AVX1-NEXT: Cost Model: Found costs of 7 for: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:11 CodeSize:12 Lat:13 SizeLat:13 for: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:19 CodeSize:22 Lat:25 SizeLat:25 for: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:4 CodeSize:7 Lat:9 SizeLat:7 for: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:8 CodeSize:12 Lat:15 SizeLat:13 for: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:16 CodeSize:22 Lat:27 SizeLat:25 for: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX2-LABEL: 'reduce_i32'
-; AVX2-NEXT: Cost Model: Found costs of 3 for: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
-; AVX2-NEXT: Cost Model: Found costs of 5 for: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
-; AVX2-NEXT: Cost Model: Found costs of 7 for: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:8 Lat:8 SizeLat:9 for: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:10 Lat:10 SizeLat:13 for: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:9 SizeLat:7 for: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:8 Lat:10 SizeLat:9 for: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:10 Lat:12 SizeLat:13 for: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512-LABEL: 'reduce_i32'
-; AVX512-NEXT: Cost Model: Found costs of RThru:3 CodeSize:3 Lat:5 SizeLat:3 for: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:5 CodeSize:5 Lat:9 SizeLat:5 for: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:11 SizeLat:7 for: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:9 CodeSize:9 Lat:13 SizeLat:10 for: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:10 CodeSize:10 Lat:14 SizeLat:11 for: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:9 SizeLat:7 for: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:12 SizeLat:9 for: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:5 CodeSize:10 Lat:13 SizeLat:10 for: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
; AVX512-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
@@ -125,73 +125,73 @@ define i32 @reduce_i32(i32 %arg) {
define i32 @reduce_i16(i32 %arg) {
; SSE2-LABEL: 'reduce_i16'
-; SSE2-NEXT: Cost Model: Found costs of 3 for: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
-; SSE2-NEXT: Cost Model: Found costs of 5 for: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
-; SSE2-NEXT: Cost Model: Found costs of 7 for: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
-; SSE2-NEXT: Cost Model: Found costs of 8 for: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
-; SSE2-NEXT: Cost Model: Found costs of 10 for: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
-; SSE2-NEXT: Cost Model: Found costs of 14 for: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:5 SizeLat:6 for: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:8 Lat:8 SizeLat:8 for: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:9 SizeLat:9 for: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:11 Lat:11 SizeLat:11 for: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:15 Lat:15 SizeLat:15 for: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSSE3-LABEL: 'reduce_i16'
-; SSSE3-NEXT: Cost Model: Found costs of 3 for: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 5 for: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 7 for: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 8 for: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 10 for: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 14 for: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:5 SizeLat:6 for: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:3 CodeSize:8 Lat:8 SizeLat:8 for: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:9 SizeLat:9 for: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:6 CodeSize:11 Lat:11 SizeLat:11 for: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:10 CodeSize:15 Lat:15 SizeLat:15 for: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSE4-LABEL: 'reduce_i16'
-; SSE4-NEXT: Cost Model: Found costs of 3 for: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
-; SSE4-NEXT: Cost Model: Found costs of 5 for: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
-; SSE4-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
-; SSE4-NEXT: Cost Model: Found costs of 5 for: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
-; SSE4-NEXT: Cost Model: Found costs of 7 for: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
-; SSE4-NEXT: Cost Model: Found costs of 11 for: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:5 SizeLat:6 for: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:8 SizeLat:5 for: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:9 SizeLat:6 for: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:5 CodeSize:7 Lat:11 SizeLat:8 for: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:9 CodeSize:11 Lat:15 SizeLat:12 for: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
; SSE4-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX1-LABEL: 'reduce_i16'
-; AVX1-NEXT: Cost Model: Found costs of 3 for: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
-; AVX1-NEXT: Cost Model: Found costs of 5 for: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
-; AVX1-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
-; AVX1-NEXT: Cost Model: Found costs of 6 for: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:10 CodeSize:11 Lat:12 SizeLat:12 for: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:18 CodeSize:21 Lat:24 SizeLat:24 for: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:5 SizeLat:6 for: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:8 SizeLat:5 for: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:15 SizeLat:7 for: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:7 CodeSize:11 Lat:21 SizeLat:13 for: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:15 CodeSize:21 Lat:33 SizeLat:25 for: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX2-LABEL: 'reduce_i16'
-; AVX2-NEXT: Cost Model: Found costs of 3 for: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
-; AVX2-NEXT: Cost Model: Found costs of 5 for: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
-; AVX2-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
-; AVX2-NEXT: Cost Model: Found costs of 6 for: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:7 SizeLat:8 for: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:9 Lat:9 SizeLat:12 for: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:8 SizeLat:5 for: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:6 Lat:15 SizeLat:7 for: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:16 SizeLat:9 for: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:9 Lat:18 SizeLat:13 for: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512F-LABEL: 'reduce_i16'
-; AVX512F-NEXT: Cost Model: Found costs of 3 for: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 5 for: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 6 for: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:8 SizeLat:5 for: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:6 Lat:15 SizeLat:7 for: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:11 CodeSize:11 Lat:15 SizeLat:12 for: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:14 CodeSize:16 Lat:22 SizeLat:17 for: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512BW-LABEL: 'reduce_i16'
-; AVX512BW-NEXT: Cost Model: Found costs of 3 for: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 5 for: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 6 for: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 8 for: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 9 for: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:8 SizeLat:5 for: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:6 Lat:15 SizeLat:7 for: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:8 Lat:19 SizeLat:9 for: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:3 CodeSize:9 Lat:20 SizeLat:10 for: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
; AVX512BW-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512DQ-LABEL: 'reduce_i16'
-; AVX512DQ-NEXT: Cost Model: Found costs of 3 for: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 5 for: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 6 for: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:8 SizeLat:5 for: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:6 Lat:15 SizeLat:7 for: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:11 CodeSize:11 Lat:15 SizeLat:12 for: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:14 CodeSize:16 Lat:22 SizeLat:17 for: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
@@ -207,81 +207,81 @@ define i32 @reduce_i16(i32 %arg) {
define i32 @reduce_i8(i32 %arg) {
; SSE2-LABEL: 'reduce_i8'
-; SSE2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:7 Lat:6 SizeLat:7 for: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:13 Lat:11 SizeLat:13 for: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:19 Lat:16 SizeLat:19 for: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:13 CodeSize:25 Lat:21 SizeLat:25 for: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:15 CodeSize:30 Lat:25 SizeLat:30 for: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:19 CodeSize:40 Lat:33 SizeLat:40 for: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:27 CodeSize:60 Lat:49 SizeLat:60 for: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:3 SizeLat:6 for: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:12 Lat:6 SizeLat:13 for: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:18 Lat:9 SizeLat:19 for: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:24 Lat:13 SizeLat:25 for: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:29 Lat:17 SizeLat:30 for: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:13 CodeSize:39 Lat:25 SizeLat:40 for: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:21 CodeSize:59 Lat:41 SizeLat:60 for: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSSE3-LABEL: 'reduce_i8'
-; SSSE3-NEXT: Cost Model: Found costs of RThru:4 CodeSize:7 Lat:6 SizeLat:7 for: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:7 CodeSize:13 Lat:11 SizeLat:13 for: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:10 CodeSize:19 Lat:16 SizeLat:19 for: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:13 CodeSize:25 Lat:21 SizeLat:25 for: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:15 CodeSize:30 Lat:25 SizeLat:30 for: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:19 CodeSize:40 Lat:33 SizeLat:40 for: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:27 CodeSize:60 Lat:49 SizeLat:60 for: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:3 SizeLat:6 for: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:4 CodeSize:12 Lat:6 SizeLat:13 for: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:5 CodeSize:18 Lat:9 SizeLat:19 for: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:7 CodeSize:24 Lat:13 SizeLat:25 for: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:9 CodeSize:29 Lat:17 SizeLat:30 for: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:13 CodeSize:39 Lat:25 SizeLat:40 for: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:21 CodeSize:59 Lat:41 SizeLat:60 for: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSE4-LABEL: 'reduce_i8'
-; SSE4-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 7 for: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 9 for: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 13 for: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:8 SizeLat:9 for: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:10 SizeLat:8 for: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:4 CodeSize:8 Lat:11 SizeLat:9 for: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:6 CodeSize:10 Lat:13 SizeLat:11 for: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:10 CodeSize:14 Lat:17 SizeLat:15 for: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
; SSE4-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX1-LABEL: 'reduce_i8'
-; AVX1-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of 8 for: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:12 CodeSize:13 Lat:14 SizeLat:14 for: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:20 CodeSize:23 Lat:26 SizeLat:26 for: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:8 SizeLat:9 for: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:10 SizeLat:8 for: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:4 CodeSize:8 Lat:17 SizeLat:9 for: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:8 CodeSize:13 Lat:23 SizeLat:15 for: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:16 CodeSize:23 Lat:35 SizeLat:27 for: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX2-LABEL: 'reduce_i8'
-; AVX2-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of 8 for: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:9 Lat:9 SizeLat:10 for: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:11 CodeSize:11 Lat:11 SizeLat:14 for: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:10 SizeLat:8 for: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:8 Lat:17 SizeLat:9 for: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:18 SizeLat:11 for: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:11 Lat:20 SizeLat:15 for: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512F-LABEL: 'reduce_i8'
-; AVX512F-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 8 for: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:10 SizeLat:8 for: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:8 Lat:17 SizeLat:9 for: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:13 CodeSize:13 Lat:17 SizeLat:14 for: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:16 CodeSize:18 Lat:24 SizeLat:19 for: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512BW-LABEL: 'reduce_i8'
-; AVX512BW-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 8 for: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 10 for: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 11 for: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:6 Lat:10 SizeLat:7 for: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:8 Lat:17 SizeLat:9 for: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:10 Lat:21 SizeLat:11 for: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:3 CodeSize:11 Lat:22 SizeLat:12 for: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
; AVX512BW-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512DQ-LABEL: 'reduce_i8'
-; AVX512DQ-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 8 for: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:10 SizeLat:8 for: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:3 CodeSize:8 Lat:17 SizeLat:9 for: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:13 CodeSize:13 Lat:17 SizeLat:14 for: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:16 CodeSize:18 Lat:24 SizeLat:19 for: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
diff --git a/llvm/test/Analysis/CostModel/X86/reduce-umax.ll b/llvm/test/Analysis/CostModel/X86/reduce-umax.ll
index 3025192ddf35b..85d76a24de15a 100644
--- a/llvm/test/Analysis/CostModel/X86/reduce-umax.ll
+++ b/llvm/test/Analysis/CostModel/X86/reduce-umax.ll
@@ -12,50 +12,50 @@
define i32 @reduce_i64(i32 %arg) {
; SSE2-LABEL: 'reduce_i64'
; SSE2-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:17 Lat:10 SizeLat:17 for: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:32 Lat:18 SizeLat:32 for: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:18 CodeSize:62 Lat:34 SizeLat:62 for: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:34 CodeSize:122 Lat:66 SizeLat:122 for: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:4 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:20 Lat:12 SizeLat:21 for: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:15 CodeSize:50 Lat:28 SizeLat:51 for: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:31 CodeSize:110 Lat:60 SizeLat:111 for: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSSE3-LABEL: 'reduce_i64'
; SSSE3-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:6 CodeSize:17 Lat:10 SizeLat:17 for: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:10 CodeSize:32 Lat:18 SizeLat:32 for: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:18 CodeSize:62 Lat:34 SizeLat:62 for: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:34 CodeSize:122 Lat:66 SizeLat:122 for: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:4 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:7 CodeSize:20 Lat:12 SizeLat:21 for: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:15 CodeSize:50 Lat:28 SizeLat:51 for: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:31 CodeSize:110 Lat:60 SizeLat:111 for: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSE4-LABEL: 'reduce_i64'
; SSE4-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
-; SSE4-NEXT: Cost Model: Found costs of RThru:4 CodeSize:8 Lat:13 SizeLat:9 for: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
-; SSE4-NEXT: Cost Model: Found costs of RThru:6 CodeSize:14 Lat:24 SizeLat:16 for: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
-; SSE4-NEXT: Cost Model: Found costs of RThru:10 CodeSize:26 Lat:46 SizeLat:30 for: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
-; SSE4-NEXT: Cost Model: Found costs of RThru:18 CodeSize:50 Lat:90 SizeLat:58 for: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:5 CodeSize:10 Lat:15 SizeLat:13 for: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:9 CodeSize:22 Lat:37 SizeLat:27 for: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:17 CodeSize:46 Lat:81 SizeLat:55 for: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
; SSE4-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX1-LABEL: 'reduce_i64'
; AVX1-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:7 Lat:10 SizeLat:9 for: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:11 CodeSize:13 Lat:19 SizeLat:17 for: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:20 CodeSize:24 Lat:29 SizeLat:34 for: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:38 CodeSize:46 Lat:49 SizeLat:68 for: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:10 Lat:12 SizeLat:13 for: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:15 CodeSize:21 Lat:22 SizeLat:30 for: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:33 CodeSize:43 Lat:42 SizeLat:64 for: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX2-LABEL: 'reduce_i64'
; AVX2-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:7 Lat:10 SizeLat:8 for: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:13 Lat:19 SizeLat:15 for: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:18 Lat:27 SizeLat:23 for: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:13 CodeSize:28 Lat:43 SizeLat:39 for: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:10 Lat:12 SizeLat:13 for: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:15 Lat:20 SizeLat:21 for: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:25 Lat:36 SizeLat:37 for: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512-LABEL: 'reduce_i64'
; AVX512-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:3 CodeSize:3 Lat:7 SizeLat:3 for: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:5 CodeSize:5 Lat:11 SizeLat:5 for: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:15 SizeLat:7 for: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:8 CodeSize:8 Lat:18 SizeLat:8 for: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:4 SizeLat:3 for: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:10 SizeLat:5 for: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:5 CodeSize:7 Lat:16 SizeLat:7 for: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:6 CodeSize:8 Lat:19 SizeLat:8 for: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
; AVX512-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
@@ -68,51 +68,51 @@ define i32 @reduce_i64(i32 %arg) {
define i32 @reduce_i32(i32 %arg) {
; SSE2-LABEL: 'reduce_i32'
-; SSE2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:10 Lat:7 SizeLat:10 for: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:19 Lat:13 SizeLat:19 for: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:27 Lat:18 SizeLat:27 for: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:13 CodeSize:43 Lat:28 SizeLat:43 for: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:21 CodeSize:75 Lat:48 SizeLat:75 for: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:2 SizeLat:6 for: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:14 Lat:7 SizeLat:15 for: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:22 Lat:12 SizeLat:23 for: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:38 Lat:22 SizeLat:39 for: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:18 CodeSize:70 Lat:42 SizeLat:71 for: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSSE3-LABEL: 'reduce_i32'
-; SSSE3-NEXT: Cost Model: Found costs of RThru:4 CodeSize:10 Lat:7 SizeLat:10 for: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:7 CodeSize:19 Lat:13 SizeLat:19 for: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:9 CodeSize:27 Lat:18 SizeLat:27 for: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:13 CodeSize:43 Lat:28 SizeLat:43 for: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:21 CodeSize:75 Lat:48 SizeLat:75 for: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:2 SizeLat:6 for: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:4 CodeSize:14 Lat:7 SizeLat:15 for: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:6 CodeSize:22 Lat:12 SizeLat:23 for: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:10 CodeSize:38 Lat:22 SizeLat:39 for: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:18 CodeSize:70 Lat:42 SizeLat:71 for: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSE4-LABEL: 'reduce_i32'
-; SSE4-NEXT: Cost Model: Found costs of 3 for: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
-; SSE4-NEXT: Cost Model: Found costs of 5 for: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
-; SSE4-NEXT: Cost Model: Found costs of 6 for: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
-; SSE4-NEXT: Cost Model: Found costs of 8 for: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
-; SSE4-NEXT: Cost Model: Found costs of 12 for: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:4 CodeSize:6 Lat:5 SizeLat:6 for: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:6 CodeSize:8 Lat:7 SizeLat:8 for: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:10 CodeSize:12 Lat:11 SizeLat:12 for: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
; SSE4-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX1-LABEL: 'reduce_i32'
-; AVX1-NEXT: Cost Model: Found costs of 3 for: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
-; AVX1-NEXT: Cost Model: Found costs of 5 for: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
-; AVX1-NEXT: Cost Model: Found costs of 7 for: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:11 CodeSize:12 Lat:13 SizeLat:13 for: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:19 CodeSize:22 Lat:25 SizeLat:25 for: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:4 CodeSize:7 Lat:9 SizeLat:7 for: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:8 CodeSize:12 Lat:15 SizeLat:13 for: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:16 CodeSize:22 Lat:27 SizeLat:25 for: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX2-LABEL: 'reduce_i32'
-; AVX2-NEXT: Cost Model: Found costs of 3 for: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
-; AVX2-NEXT: Cost Model: Found costs of 5 for: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
-; AVX2-NEXT: Cost Model: Found costs of 7 for: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:8 Lat:8 SizeLat:9 for: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:10 Lat:10 SizeLat:13 for: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:9 SizeLat:7 for: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:8 Lat:10 SizeLat:9 for: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:10 Lat:12 SizeLat:13 for: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512-LABEL: 'reduce_i32'
-; AVX512-NEXT: Cost Model: Found costs of RThru:3 CodeSize:3 Lat:5 SizeLat:3 for: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:5 CodeSize:5 Lat:9 SizeLat:5 for: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:11 SizeLat:7 for: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:9 CodeSize:9 Lat:13 SizeLat:10 for: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:10 CodeSize:10 Lat:14 SizeLat:11 for: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:9 SizeLat:7 for: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:12 SizeLat:9 for: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:5 CodeSize:10 Lat:13 SizeLat:10 for: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
; AVX512-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
@@ -125,73 +125,73 @@ define i32 @reduce_i32(i32 %arg) {
define i32 @reduce_i16(i32 %arg) {
; SSE2-LABEL: 'reduce_i16'
-; SSE2-NEXT: Cost Model: Found costs of 5 for: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
-; SSE2-NEXT: Cost Model: Found costs of 7 for: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
-; SSE2-NEXT: Cost Model: Found costs of 9 for: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:12 Lat:12 SizeLat:12 for: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:12 CodeSize:18 Lat:18 SizeLat:18 for: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:30 Lat:30 SizeLat:30 for: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:6 for: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:8 Lat:5 SizeLat:10 for: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:12 Lat:8 SizeLat:14 for: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:15 Lat:11 SizeLat:17 for: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:21 Lat:17 SizeLat:23 for: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:11 CodeSize:33 Lat:29 SizeLat:35 for: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSSE3-LABEL: 'reduce_i16'
-; SSSE3-NEXT: Cost Model: Found costs of 5 for: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 7 for: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 9 for: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:10 CodeSize:12 Lat:12 SizeLat:12 for: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:12 CodeSize:18 Lat:18 SizeLat:18 for: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:16 CodeSize:30 Lat:30 SizeLat:30 for: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:6 for: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:3 CodeSize:8 Lat:5 SizeLat:10 for: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:4 CodeSize:12 Lat:8 SizeLat:14 for: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:5 CodeSize:15 Lat:11 SizeLat:17 for: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:7 CodeSize:21 Lat:17 SizeLat:23 for: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:11 CodeSize:33 Lat:29 SizeLat:35 for: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSE4-LABEL: 'reduce_i16'
-; SSE4-NEXT: Cost Model: Found costs of 5 for: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
-; SSE4-NEXT: Cost Model: Found costs of 7 for: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
-; SSE4-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
-; SSE4-NEXT: Cost Model: Found costs of 5 for: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
-; SSE4-NEXT: Cost Model: Found costs of 7 for: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
-; SSE4-NEXT: Cost Model: Found costs of 11 for: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:5 SizeLat:6 for: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:5 SizeLat:2 for: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:3 Lat:6 SizeLat:3 for: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:5 CodeSize:5 Lat:8 SizeLat:5 for: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:9 CodeSize:9 Lat:12 SizeLat:9 for: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
; SSE4-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX1-LABEL: 'reduce_i16'
-; AVX1-NEXT: Cost Model: Found costs of 5 for: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
-; AVX1-NEXT: Cost Model: Found costs of 7 for: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
-; AVX1-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
-; AVX1-NEXT: Cost Model: Found costs of 6 for: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:10 CodeSize:11 Lat:12 SizeLat:12 for: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:18 CodeSize:21 Lat:24 SizeLat:24 for: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:5 SizeLat:6 for: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:5 SizeLat:2 for: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:9 SizeLat:4 for: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:9 Lat:15 SizeLat:10 for: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:14 CodeSize:19 Lat:27 SizeLat:22 for: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX2-LABEL: 'reduce_i16'
-; AVX2-NEXT: Cost Model: Found costs of 5 for: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
-; AVX2-NEXT: Cost Model: Found costs of 7 for: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
-; AVX2-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
-; AVX2-NEXT: Cost Model: Found costs of 6 for: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:7 SizeLat:8 for: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:9 Lat:9 SizeLat:12 for: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:5 SizeLat:2 for: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:9 SizeLat:4 for: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:10 SizeLat:6 for: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:7 Lat:12 SizeLat:10 for: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512F-LABEL: 'reduce_i16'
-; AVX512F-NEXT: Cost Model: Found costs of 5 for: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 7 for: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 6 for: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:5 SizeLat:2 for: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:9 SizeLat:4 for: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:11 CodeSize:11 Lat:15 SizeLat:12 for: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:14 CodeSize:16 Lat:22 SizeLat:17 for: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512BW-LABEL: 'reduce_i16'
-; AVX512BW-NEXT: Cost Model: Found costs of 5 for: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 7 for: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 6 for: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 8 for: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 9 for: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:5 SizeLat:2 for: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:9 SizeLat:4 for: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:6 Lat:12 SizeLat:6 for: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:13 SizeLat:7 for: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
; AVX512BW-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512DQ-LABEL: 'reduce_i16'
-; AVX512DQ-NEXT: Cost Model: Found costs of 5 for: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 7 for: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 6 for: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:5 SizeLat:2 for: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:9 SizeLat:4 for: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:11 CodeSize:11 Lat:15 SizeLat:12 for: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:14 CodeSize:16 Lat:22 SizeLat:17 for: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
@@ -207,81 +207,81 @@ define i32 @reduce_i16(i32 %arg) {
define i32 @reduce_i8(i32 %arg) {
; SSE2-LABEL: 'reduce_i8'
-; SSE2-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of 9 for: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of 10 for: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of 12 for: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of 16 for: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:8 SizeLat:9 for: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:11 Lat:10 SizeLat:11 for: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:12 Lat:11 SizeLat:12 for: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:14 Lat:13 SizeLat:14 for: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:18 Lat:17 SizeLat:18 for: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSSE3-LABEL: 'reduce_i8'
-; SSSE3-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 9 for: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 10 for: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 12 for: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 16 for: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:8 SizeLat:9 for: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:3 CodeSize:11 Lat:10 SizeLat:11 for: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:4 CodeSize:12 Lat:11 SizeLat:12 for: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:6 CodeSize:14 Lat:13 SizeLat:14 for: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:10 CodeSize:18 Lat:17 SizeLat:18 for: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSE4-LABEL: 'reduce_i8'
-; SSE4-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 7 for: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 9 for: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 13 for: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:8 SizeLat:9 for: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:8 SizeLat:5 for: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:4 CodeSize:6 Lat:9 SizeLat:6 for: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:6 CodeSize:8 Lat:11 SizeLat:8 for: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:10 CodeSize:12 Lat:15 SizeLat:12 for: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
; SSE4-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX1-LABEL: 'reduce_i8'
-; AVX1-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of 8 for: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:12 CodeSize:13 Lat:14 SizeLat:14 for: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:20 CodeSize:23 Lat:26 SizeLat:26 for: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:8 SizeLat:9 for: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:8 SizeLat:5 for: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:11 SizeLat:6 for: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:7 CodeSize:11 Lat:17 SizeLat:12 for: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:15 CodeSize:21 Lat:29 SizeLat:24 for: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX2-LABEL: 'reduce_i8'
-; AVX2-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of 8 for: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:9 Lat:9 SizeLat:10 for: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:11 CodeSize:11 Lat:11 SizeLat:14 for: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:8 SizeLat:5 for: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:11 SizeLat:6 for: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:7 Lat:12 SizeLat:8 for: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:9 Lat:14 SizeLat:12 for: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512F-LABEL: 'reduce_i8'
-; AVX512F-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 8 for: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:8 SizeLat:5 for: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:11 SizeLat:6 for: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:13 CodeSize:13 Lat:17 SizeLat:14 for: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:16 CodeSize:18 Lat:24 SizeLat:19 for: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512BW-LABEL: 'reduce_i8'
-; AVX512BW-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 8 for: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 10 for: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 11 for: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:6 SizeLat:4 for: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:6 Lat:10 SizeLat:6 for: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:8 Lat:14 SizeLat:8 for: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:3 CodeSize:9 Lat:15 SizeLat:9 for: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
; AVX512BW-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512DQ-LABEL: 'reduce_i8'
-; AVX512DQ-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 8 for: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:8 SizeLat:5 for: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:11 SizeLat:6 for: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:13 CodeSize:13 Lat:17 SizeLat:14 for: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:16 CodeSize:18 Lat:24 SizeLat:19 for: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
diff --git a/llvm/test/Analysis/CostModel/X86/reduce-umin.ll b/llvm/test/Analysis/CostModel/X86/reduce-umin.ll
index 51d06a925f4c9..845302fb15df0 100644
--- a/llvm/test/Analysis/CostModel/X86/reduce-umin.ll
+++ b/llvm/test/Analysis/CostModel/X86/reduce-umin.ll
@@ -12,50 +12,50 @@
define i32 @reduce_i64(i32 %arg) {
; SSE2-LABEL: 'reduce_i64'
; SSE2-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:17 Lat:10 SizeLat:17 for: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:32 Lat:18 SizeLat:32 for: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:18 CodeSize:62 Lat:34 SizeLat:62 for: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:34 CodeSize:122 Lat:66 SizeLat:122 for: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:4 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:20 Lat:12 SizeLat:21 for: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:15 CodeSize:50 Lat:28 SizeLat:51 for: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:31 CodeSize:110 Lat:60 SizeLat:111 for: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSSE3-LABEL: 'reduce_i64'
; SSSE3-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:6 CodeSize:17 Lat:10 SizeLat:17 for: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:10 CodeSize:32 Lat:18 SizeLat:32 for: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:18 CodeSize:62 Lat:34 SizeLat:62 for: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:34 CodeSize:122 Lat:66 SizeLat:122 for: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:4 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:7 CodeSize:20 Lat:12 SizeLat:21 for: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:15 CodeSize:50 Lat:28 SizeLat:51 for: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:31 CodeSize:110 Lat:60 SizeLat:111 for: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSE4-LABEL: 'reduce_i64'
; SSE4-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
-; SSE4-NEXT: Cost Model: Found costs of RThru:4 CodeSize:8 Lat:13 SizeLat:9 for: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
-; SSE4-NEXT: Cost Model: Found costs of RThru:6 CodeSize:14 Lat:24 SizeLat:16 for: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
-; SSE4-NEXT: Cost Model: Found costs of RThru:10 CodeSize:26 Lat:46 SizeLat:30 for: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
-; SSE4-NEXT: Cost Model: Found costs of RThru:18 CodeSize:50 Lat:90 SizeLat:58 for: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:5 CodeSize:10 Lat:15 SizeLat:13 for: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:9 CodeSize:22 Lat:37 SizeLat:27 for: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:17 CodeSize:46 Lat:81 SizeLat:55 for: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
; SSE4-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX1-LABEL: 'reduce_i64'
; AVX1-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:7 Lat:10 SizeLat:9 for: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:11 CodeSize:13 Lat:19 SizeLat:17 for: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:20 CodeSize:24 Lat:29 SizeLat:34 for: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:38 CodeSize:46 Lat:49 SizeLat:68 for: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:10 Lat:12 SizeLat:13 for: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:15 CodeSize:21 Lat:22 SizeLat:30 for: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:33 CodeSize:43 Lat:42 SizeLat:64 for: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX2-LABEL: 'reduce_i64'
; AVX2-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:7 Lat:10 SizeLat:8 for: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:13 Lat:19 SizeLat:15 for: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:18 Lat:27 SizeLat:23 for: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:13 CodeSize:28 Lat:43 SizeLat:39 for: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:6 for: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:10 Lat:12 SizeLat:13 for: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:15 Lat:20 SizeLat:21 for: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:25 Lat:36 SizeLat:37 for: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512-LABEL: 'reduce_i64'
; AVX512-NEXT: Cost Model: Found costs of 0 for: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:3 CodeSize:3 Lat:7 SizeLat:3 for: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:5 CodeSize:5 Lat:11 SizeLat:5 for: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:15 SizeLat:7 for: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:8 CodeSize:8 Lat:18 SizeLat:8 for: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:4 SizeLat:3 for: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:10 SizeLat:5 for: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:5 CodeSize:7 Lat:16 SizeLat:7 for: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:6 CodeSize:8 Lat:19 SizeLat:8 for: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
; AVX512-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
@@ -68,51 +68,51 @@ define i32 @reduce_i64(i32 %arg) {
define i32 @reduce_i32(i32 %arg) {
; SSE2-LABEL: 'reduce_i32'
-; SSE2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:10 Lat:7 SizeLat:10 for: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:19 Lat:13 SizeLat:19 for: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:27 Lat:18 SizeLat:27 for: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:13 CodeSize:43 Lat:28 SizeLat:43 for: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:21 CodeSize:75 Lat:48 SizeLat:75 for: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:2 SizeLat:6 for: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:14 Lat:7 SizeLat:15 for: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:22 Lat:12 SizeLat:23 for: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:38 Lat:22 SizeLat:39 for: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:18 CodeSize:70 Lat:42 SizeLat:71 for: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSSE3-LABEL: 'reduce_i32'
-; SSSE3-NEXT: Cost Model: Found costs of RThru:4 CodeSize:10 Lat:7 SizeLat:10 for: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:7 CodeSize:19 Lat:13 SizeLat:19 for: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:9 CodeSize:27 Lat:18 SizeLat:27 for: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:13 CodeSize:43 Lat:28 SizeLat:43 for: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:21 CodeSize:75 Lat:48 SizeLat:75 for: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:2 SizeLat:6 for: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:4 CodeSize:14 Lat:7 SizeLat:15 for: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:6 CodeSize:22 Lat:12 SizeLat:23 for: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:10 CodeSize:38 Lat:22 SizeLat:39 for: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:18 CodeSize:70 Lat:42 SizeLat:71 for: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSE4-LABEL: 'reduce_i32'
-; SSE4-NEXT: Cost Model: Found costs of 3 for: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
-; SSE4-NEXT: Cost Model: Found costs of 5 for: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
-; SSE4-NEXT: Cost Model: Found costs of 6 for: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
-; SSE4-NEXT: Cost Model: Found costs of 8 for: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
-; SSE4-NEXT: Cost Model: Found costs of 12 for: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:4 CodeSize:6 Lat:5 SizeLat:6 for: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:6 CodeSize:8 Lat:7 SizeLat:8 for: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:10 CodeSize:12 Lat:11 SizeLat:12 for: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
; SSE4-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX1-LABEL: 'reduce_i32'
-; AVX1-NEXT: Cost Model: Found costs of 3 for: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
-; AVX1-NEXT: Cost Model: Found costs of 5 for: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
-; AVX1-NEXT: Cost Model: Found costs of 7 for: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:11 CodeSize:12 Lat:13 SizeLat:13 for: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:19 CodeSize:22 Lat:25 SizeLat:25 for: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:4 CodeSize:7 Lat:9 SizeLat:7 for: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:8 CodeSize:12 Lat:15 SizeLat:13 for: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:16 CodeSize:22 Lat:27 SizeLat:25 for: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX2-LABEL: 'reduce_i32'
-; AVX2-NEXT: Cost Model: Found costs of 3 for: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
-; AVX2-NEXT: Cost Model: Found costs of 5 for: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
-; AVX2-NEXT: Cost Model: Found costs of 7 for: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:8 Lat:8 SizeLat:9 for: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:10 Lat:10 SizeLat:13 for: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:9 SizeLat:7 for: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:8 Lat:10 SizeLat:9 for: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:10 Lat:12 SizeLat:13 for: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512-LABEL: 'reduce_i32'
-; AVX512-NEXT: Cost Model: Found costs of RThru:3 CodeSize:3 Lat:5 SizeLat:3 for: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:5 CodeSize:5 Lat:9 SizeLat:5 for: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:11 SizeLat:7 for: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:9 CodeSize:9 Lat:13 SizeLat:10 for: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
-; AVX512-NEXT: Cost Model: Found costs of RThru:10 CodeSize:10 Lat:14 SizeLat:11 for: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:9 SizeLat:7 for: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:12 SizeLat:9 for: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
+; AVX512-NEXT: Cost Model: Found costs of RThru:5 CodeSize:10 Lat:13 SizeLat:10 for: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
; AVX512-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
@@ -125,73 +125,73 @@ define i32 @reduce_i32(i32 %arg) {
define i32 @reduce_i16(i32 %arg) {
; SSE2-LABEL: 'reduce_i16'
-; SSE2-NEXT: Cost Model: Found costs of 5 for: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
-; SSE2-NEXT: Cost Model: Found costs of 7 for: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
-; SSE2-NEXT: Cost Model: Found costs of 9 for: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:12 Lat:12 SizeLat:12 for: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:12 CodeSize:18 Lat:18 SizeLat:18 for: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
-; SSE2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:30 Lat:30 SizeLat:30 for: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:6 for: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:8 Lat:5 SizeLat:10 for: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:12 Lat:8 SizeLat:14 for: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:15 Lat:11 SizeLat:17 for: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:21 Lat:17 SizeLat:23 for: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:11 CodeSize:33 Lat:29 SizeLat:35 for: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSSE3-LABEL: 'reduce_i16'
-; SSSE3-NEXT: Cost Model: Found costs of 5 for: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 7 for: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 9 for: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:10 CodeSize:12 Lat:12 SizeLat:12 for: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:12 CodeSize:18 Lat:18 SizeLat:18 for: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
-; SSSE3-NEXT: Cost Model: Found costs of RThru:16 CodeSize:30 Lat:30 SizeLat:30 for: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:6 for: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:3 CodeSize:8 Lat:5 SizeLat:10 for: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:4 CodeSize:12 Lat:8 SizeLat:14 for: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:5 CodeSize:15 Lat:11 SizeLat:17 for: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:7 CodeSize:21 Lat:17 SizeLat:23 for: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:11 CodeSize:33 Lat:29 SizeLat:35 for: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSE4-LABEL: 'reduce_i16'
-; SSE4-NEXT: Cost Model: Found costs of 5 for: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
-; SSE4-NEXT: Cost Model: Found costs of 7 for: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
-; SSE4-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
-; SSE4-NEXT: Cost Model: Found costs of 5 for: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
-; SSE4-NEXT: Cost Model: Found costs of 7 for: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
-; SSE4-NEXT: Cost Model: Found costs of 11 for: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:5 SizeLat:6 for: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:5 SizeLat:2 for: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:3 Lat:6 SizeLat:3 for: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:5 CodeSize:5 Lat:8 SizeLat:5 for: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:9 CodeSize:9 Lat:12 SizeLat:9 for: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
; SSE4-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX1-LABEL: 'reduce_i16'
-; AVX1-NEXT: Cost Model: Found costs of 5 for: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
-; AVX1-NEXT: Cost Model: Found costs of 7 for: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
-; AVX1-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
-; AVX1-NEXT: Cost Model: Found costs of 6 for: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:10 CodeSize:11 Lat:12 SizeLat:12 for: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:18 CodeSize:21 Lat:24 SizeLat:24 for: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:5 SizeLat:6 for: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:5 SizeLat:2 for: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:9 SizeLat:4 for: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:9 Lat:15 SizeLat:10 for: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:14 CodeSize:19 Lat:27 SizeLat:22 for: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX2-LABEL: 'reduce_i16'
-; AVX2-NEXT: Cost Model: Found costs of 5 for: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
-; AVX2-NEXT: Cost Model: Found costs of 7 for: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
-; AVX2-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
-; AVX2-NEXT: Cost Model: Found costs of 6 for: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:7 SizeLat:8 for: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:9 Lat:9 SizeLat:12 for: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:5 SizeLat:2 for: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:9 SizeLat:4 for: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:10 SizeLat:6 for: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:7 Lat:12 SizeLat:10 for: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512F-LABEL: 'reduce_i16'
-; AVX512F-NEXT: Cost Model: Found costs of 5 for: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 7 for: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 6 for: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:5 SizeLat:2 for: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:9 SizeLat:4 for: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:11 CodeSize:11 Lat:15 SizeLat:12 for: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:14 CodeSize:16 Lat:22 SizeLat:17 for: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512BW-LABEL: 'reduce_i16'
-; AVX512BW-NEXT: Cost Model: Found costs of 5 for: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 7 for: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 6 for: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 8 for: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 9 for: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:5 SizeLat:2 for: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:9 SizeLat:4 for: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:6 Lat:12 SizeLat:6 for: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:13 SizeLat:7 for: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
; AVX512BW-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512DQ-LABEL: 'reduce_i16'
-; AVX512DQ-NEXT: Cost Model: Found costs of 5 for: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 7 for: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 4 for: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 6 for: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:5 SizeLat:2 for: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:9 SizeLat:4 for: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:11 CodeSize:11 Lat:15 SizeLat:12 for: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:14 CodeSize:16 Lat:22 SizeLat:17 for: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
@@ -207,81 +207,81 @@ define i32 @reduce_i16(i32 %arg) {
define i32 @reduce_i8(i32 %arg) {
; SSE2-LABEL: 'reduce_i8'
-; SSE2-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of 9 for: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of 10 for: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of 12 for: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
-; SSE2-NEXT: Cost Model: Found costs of 16 for: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:8 SizeLat:9 for: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:11 Lat:10 SizeLat:11 for: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:12 Lat:11 SizeLat:12 for: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:14 Lat:13 SizeLat:14 for: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
+; SSE2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:18 Lat:17 SizeLat:18 for: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSSE3-LABEL: 'reduce_i8'
-; SSSE3-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 9 for: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 10 for: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 12 for: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
-; SSSE3-NEXT: Cost Model: Found costs of 16 for: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:8 SizeLat:9 for: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:3 CodeSize:11 Lat:10 SizeLat:11 for: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:4 CodeSize:12 Lat:11 SizeLat:12 for: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:6 CodeSize:14 Lat:13 SizeLat:14 for: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
+; SSSE3-NEXT: Cost Model: Found costs of RThru:10 CodeSize:18 Lat:17 SizeLat:18 for: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; SSE4-LABEL: 'reduce_i8'
-; SSE4-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 7 for: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 9 for: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
-; SSE4-NEXT: Cost Model: Found costs of 13 for: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:8 SizeLat:9 for: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:8 SizeLat:5 for: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:4 CodeSize:6 Lat:9 SizeLat:6 for: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:6 CodeSize:8 Lat:11 SizeLat:8 for: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
+; SSE4-NEXT: Cost Model: Found costs of RThru:10 CodeSize:12 Lat:15 SizeLat:12 for: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
; SSE4-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX1-LABEL: 'reduce_i8'
-; AVX1-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of 8 for: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:12 CodeSize:13 Lat:14 SizeLat:14 for: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
-; AVX1-NEXT: Cost Model: Found costs of RThru:20 CodeSize:23 Lat:26 SizeLat:26 for: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:4 CodeSize:9 Lat:8 SizeLat:9 for: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:8 SizeLat:5 for: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:11 SizeLat:6 for: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:7 CodeSize:11 Lat:17 SizeLat:12 for: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
+; AVX1-NEXT: Cost Model: Found costs of RThru:15 CodeSize:21 Lat:29 SizeLat:24 for: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX2-LABEL: 'reduce_i8'
-; AVX2-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of 8 for: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:9 Lat:9 SizeLat:10 for: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
-; AVX2-NEXT: Cost Model: Found costs of RThru:11 CodeSize:11 Lat:11 SizeLat:14 for: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:8 SizeLat:5 for: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:11 SizeLat:6 for: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:7 Lat:12 SizeLat:8 for: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
+; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:9 Lat:14 SizeLat:12 for: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512F-LABEL: 'reduce_i8'
-; AVX512F-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
-; AVX512F-NEXT: Cost Model: Found costs of 8 for: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:8 SizeLat:5 for: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:11 SizeLat:6 for: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:13 CodeSize:13 Lat:17 SizeLat:14 for: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:16 CodeSize:18 Lat:24 SizeLat:19 for: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
; AVX512F-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512BW-LABEL: 'reduce_i8'
-; AVX512BW-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 8 for: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 10 for: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
-; AVX512BW-NEXT: Cost Model: Found costs of 11 for: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:2 SizeLat:3 for: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:4 SizeLat:5 for: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:6 SizeLat:4 for: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:6 Lat:10 SizeLat:6 for: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:8 Lat:14 SizeLat:8 for: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:3 CodeSize:9 Lat:15 SizeLat:9 for: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
; AVX512BW-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512DQ-LABEL: 'reduce_i8'
-; AVX512DQ-NEXT: Cost Model: Found costs of 3 for: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 5 for: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 7 for: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 6 for: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
-; AVX512DQ-NEXT: Cost Model: Found costs of 8 for: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:3 SizeLat:4 for: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:3 CodeSize:7 Lat:6 SizeLat:7 for: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:3 CodeSize:5 Lat:8 SizeLat:5 for: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:3 CodeSize:6 Lat:11 SizeLat:6 for: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:13 CodeSize:13 Lat:17 SizeLat:14 for: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:16 CodeSize:18 Lat:24 SizeLat:19 for: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
; AVX512DQ-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smax.ll b/llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smax.ll
index ec8cd82b96a37..35045b4d4e6c5 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smax.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smax.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64 | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v2 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v3 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v4 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s
;
; 128-bit Vectors
@@ -14,10 +14,8 @@
define i64 @test_reduce_v2i64(<2 x i64> %a0) {
; CHECK-LABEL: @test_reduce_v2i64(
-; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i64> [[A0:%.*]], <2 x i64> poison, <2 x i32> <i32 1, i32 poison>
-; CHECK-NEXT: [[TMP2:%.*]] = tail call <2 x i64> @llvm.smax.v2i64(<2 x i64> [[A0]], <2 x i64> [[TMP1]])
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP2]], i64 0
-; CHECK-NEXT: ret i64 [[TMP4]]
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> [[A0:%.*]])
+; CHECK-NEXT: ret i64 [[TMP1]]
;
%1 = shufflevector <2 x i64> %a0, <2 x i64> undef, <2 x i32> <i32 1, i32 undef>
%2 = icmp sgt <2 x i64> %a0, %1
@@ -28,11 +26,7 @@ define i64 @test_reduce_v2i64(<2 x i64> %a0) {
define i32 @test_reduce_v4i32(<4 x i32> %a0) {
; CHECK-LABEL: @test_reduce_v4i32(
-; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A0:%.*]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[A0]], <4 x i32> [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP4:%.*]] = tail call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMP2]], <4 x i32> [[TMP3]])
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[TMP4]], i64 0
+; CHECK-NEXT: [[TMP7:%.*]] = tail call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[A0:%.*]])
; CHECK-NEXT: ret i32 [[TMP7]]
;
%1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
@@ -89,17 +83,9 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) {
;
define i64 @test_reduce_v4i64(<4 x i64> %a0) {
-; SSE-LABEL: @test_reduce_v4i64(
-; SSE-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[A0:%.*]])
-; SSE-NEXT: ret i64 [[TMP1]]
-;
-; AVX-LABEL: @test_reduce_v4i64(
-; AVX-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> <i32 2, i32 3, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP2:%.*]] = tail call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[A0]], <4 x i64> [[TMP1]])
-; AVX-NEXT: [[TMP3:%.*]] = shufflevector <4 x i64> [[TMP2]], <4 x i64> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP4:%.*]] = tail call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[TMP2]], <4 x i64> [[TMP3]])
-; AVX-NEXT: [[TMP5:%.*]] = extractelement <4 x i64> [[TMP4]], i64 0
-; AVX-NEXT: ret i64 [[TMP5]]
+; CHECK-LABEL: @test_reduce_v4i64(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[A0:%.*]])
+; CHECK-NEXT: ret i64 [[TMP1]]
;
%1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
%2 = icmp sgt <4 x i64> %a0, %1
@@ -112,19 +98,9 @@ define i64 @test_reduce_v4i64(<4 x i64> %a0) {
}
define i32 @test_reduce_v8i32(<8 x i32> %a0) {
-; SSE-LABEL: @test_reduce_v8i32(
-; SSE-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> [[A0:%.*]])
-; SSE-NEXT: ret i32 [[TMP1]]
-;
-; AVX-LABEL: @test_reduce_v8i32(
-; AVX-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A0:%.*]], <8 x i32> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP2:%.*]] = tail call <8 x i32> @llvm.smax.v8i32(<8 x i32> [[A0]], <8 x i32> [[TMP1]])
-; AVX-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[TMP2]], <8 x i32> poison, <8 x i32> <i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP4:%.*]] = tail call <8 x i32> @llvm.smax.v8i32(<8 x i32> [[TMP2]], <8 x i32> [[TMP3]])
-; AVX-NEXT: [[TMP5:%.*]] = shufflevector <8 x i32> [[TMP4]], <8 x i32> poison, <8 x i32> <i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP6:%.*]] = tail call <8 x i32> @llvm.smax.v8i32(<8 x i32> [[TMP4]], <8 x i32> [[TMP5]])
-; AVX-NEXT: [[TMP7:%.*]] = extractelement <8 x i32> [[TMP6]], i64 0
-; AVX-NEXT: ret i32 [[TMP7]]
+; CHECK-LABEL: @test_reduce_v8i32(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> [[A0:%.*]])
+; CHECK-NEXT: ret i32 [[TMP1]]
;
%1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = icmp sgt <8 x i32> %a0, %1
@@ -189,23 +165,9 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) {
;
define i64 @test_reduce_v8i64(<8 x i64> %a0) {
-; SSE-LABEL: @test_reduce_v8i64(
-; SSE-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> [[A0:%.*]])
-; SSE-NEXT: ret i64 [[TMP1]]
-;
-; AVX2-LABEL: @test_reduce_v8i64(
-; AVX2-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> [[A0:%.*]])
-; AVX2-NEXT: ret i64 [[TMP1]]
-;
-; AVX512-LABEL: @test_reduce_v8i64(
-; AVX512-NEXT: [[TMP1:%.*]] = shufflevector <8 x i64> [[A0:%.*]], <8 x i64> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP2:%.*]] = tail call <8 x i64> @llvm.smax.v8i64(<8 x i64> [[A0]], <8 x i64> [[TMP1]])
-; AVX512-NEXT: [[TMP3:%.*]] = shufflevector <8 x i64> [[TMP2]], <8 x i64> poison, <8 x i32> <i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP4:%.*]] = tail call <8 x i64> @llvm.smax.v8i64(<8 x i64> [[TMP2]], <8 x i64> [[TMP3]])
-; AVX512-NEXT: [[TMP5:%.*]] = shufflevector <8 x i64> [[TMP4]], <8 x i64> poison, <8 x i32> <i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP6:%.*]] = tail call <8 x i64> @llvm.smax.v8i64(<8 x i64> [[TMP4]], <8 x i64> [[TMP5]])
-; AVX512-NEXT: [[TMP7:%.*]] = extractelement <8 x i64> [[TMP6]], i64 0
-; AVX512-NEXT: ret i64 [[TMP7]]
+; CHECK-LABEL: @test_reduce_v8i64(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> [[A0:%.*]])
+; CHECK-NEXT: ret i64 [[TMP1]]
;
%1 = shufflevector <8 x i64> %a0, <8 x i64> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = icmp sgt <8 x i64> %a0, %1
@@ -221,25 +183,9 @@ define i64 @test_reduce_v8i64(<8 x i64> %a0) {
}
define i32 @test_reduce_v16i32(<16 x i32> %a0) {
-; SSE-LABEL: @test_reduce_v16i32(
-; SSE-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> [[A0:%.*]])
-; SSE-NEXT: ret i32 [[TMP1]]
-;
-; AVX2-LABEL: @test_reduce_v16i32(
-; AVX2-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> [[A0:%.*]])
-; AVX2-NEXT: ret i32 [[TMP1]]
-;
-; AVX512-LABEL: @test_reduce_v16i32(
-; AVX512-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[A0:%.*]], <16 x i32> poison, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP2:%.*]] = tail call <16 x i32> @llvm.smax.v16i32(<16 x i32> [[A0]], <16 x i32> [[TMP1]])
-; AVX512-NEXT: [[TMP3:%.*]] = shufflevector <16 x i32> [[TMP2]], <16 x i32> poison, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP4:%.*]] = tail call <16 x i32> @llvm.smax.v16i32(<16 x i32> [[TMP2]], <16 x i32> [[TMP3]])
-; AVX512-NEXT: [[TMP5:%.*]] = shufflevector <16 x i32> [[TMP4]], <16 x i32> poison, <16 x i32> <i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP6:%.*]] = tail call <16 x i32> @llvm.smax.v16i32(<16 x i32> [[TMP4]], <16 x i32> [[TMP5]])
-; AVX512-NEXT: [[TMP7:%.*]] = shufflevector <16 x i32> [[TMP6]], <16 x i32> poison, <16 x i32> <i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP8:%.*]] = tail call <16 x i32> @llvm.smax.v16i32(<16 x i32> [[TMP6]], <16 x i32> [[TMP7]])
-; AVX512-NEXT: [[TMP9:%.*]] = extractelement <16 x i32> [[TMP8]], i64 0
-; AVX512-NEXT: ret i32 [[TMP9]]
+; CHECK-LABEL: @test_reduce_v16i32(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> [[A0:%.*]])
+; CHECK-NEXT: ret i32 [[TMP1]]
;
%1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = icmp sgt <16 x i32> %a0, %1
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smin.ll b/llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smin.ll
index 650947d240ace..965bba2a3976e 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smin.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smin.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64 | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v2 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v3 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v4 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s
;
; 128-bit Vectors
@@ -14,10 +14,8 @@
define i64 @test_reduce_v2i64(<2 x i64> %a0) {
; CHECK-LABEL: @test_reduce_v2i64(
-; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i64> [[A0:%.*]], <2 x i64> poison, <2 x i32> <i32 1, i32 poison>
-; CHECK-NEXT: [[TMP2:%.*]] = tail call <2 x i64> @llvm.smin.v2i64(<2 x i64> [[A0]], <2 x i64> [[TMP1]])
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP2]], i64 0
-; CHECK-NEXT: ret i64 [[TMP4]]
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> [[A0:%.*]])
+; CHECK-NEXT: ret i64 [[TMP1]]
;
%1 = shufflevector <2 x i64> %a0, <2 x i64> undef, <2 x i32> <i32 1, i32 undef>
%2 = icmp slt <2 x i64> %a0, %1
@@ -28,11 +26,7 @@ define i64 @test_reduce_v2i64(<2 x i64> %a0) {
define i32 @test_reduce_v4i32(<4 x i32> %a0) {
; CHECK-LABEL: @test_reduce_v4i32(
-; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A0:%.*]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[A0]], <4 x i32> [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP4:%.*]] = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[TMP2]], <4 x i32> [[TMP3]])
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[TMP4]], i64 0
+; CHECK-NEXT: [[TMP7:%.*]] = tail call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> [[A0:%.*]])
; CHECK-NEXT: ret i32 [[TMP7]]
;
%1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
@@ -89,17 +83,9 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) {
;
define i64 @test_reduce_v4i64(<4 x i64> %a0) {
-; SSE-LABEL: @test_reduce_v4i64(
-; SSE-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> [[A0:%.*]])
-; SSE-NEXT: ret i64 [[TMP1]]
-;
-; AVX-LABEL: @test_reduce_v4i64(
-; AVX-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> <i32 2, i32 3, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP2:%.*]] = tail call <4 x i64> @llvm.smin.v4i64(<4 x i64> [[A0]], <4 x i64> [[TMP1]])
-; AVX-NEXT: [[TMP3:%.*]] = shufflevector <4 x i64> [[TMP2]], <4 x i64> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP4:%.*]] = tail call <4 x i64> @llvm.smin.v4i64(<4 x i64> [[TMP2]], <4 x i64> [[TMP3]])
-; AVX-NEXT: [[TMP5:%.*]] = extractelement <4 x i64> [[TMP4]], i64 0
-; AVX-NEXT: ret i64 [[TMP5]]
+; CHECK-LABEL: @test_reduce_v4i64(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> [[A0:%.*]])
+; CHECK-NEXT: ret i64 [[TMP1]]
;
%1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
%2 = icmp slt <4 x i64> %a0, %1
@@ -112,19 +98,9 @@ define i64 @test_reduce_v4i64(<4 x i64> %a0) {
}
define i32 @test_reduce_v8i32(<8 x i32> %a0) {
-; SSE-LABEL: @test_reduce_v8i32(
-; SSE-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> [[A0:%.*]])
-; SSE-NEXT: ret i32 [[TMP1]]
-;
-; AVX-LABEL: @test_reduce_v8i32(
-; AVX-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A0:%.*]], <8 x i32> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP2:%.*]] = tail call <8 x i32> @llvm.smin.v8i32(<8 x i32> [[A0]], <8 x i32> [[TMP1]])
-; AVX-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[TMP2]], <8 x i32> poison, <8 x i32> <i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP4:%.*]] = tail call <8 x i32> @llvm.smin.v8i32(<8 x i32> [[TMP2]], <8 x i32> [[TMP3]])
-; AVX-NEXT: [[TMP5:%.*]] = shufflevector <8 x i32> [[TMP4]], <8 x i32> poison, <8 x i32> <i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP6:%.*]] = tail call <8 x i32> @llvm.smin.v8i32(<8 x i32> [[TMP4]], <8 x i32> [[TMP5]])
-; AVX-NEXT: [[TMP7:%.*]] = extractelement <8 x i32> [[TMP6]], i64 0
-; AVX-NEXT: ret i32 [[TMP7]]
+; CHECK-LABEL: @test_reduce_v8i32(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> [[A0:%.*]])
+; CHECK-NEXT: ret i32 [[TMP1]]
;
%1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = icmp slt <8 x i32> %a0, %1
@@ -189,23 +165,9 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) {
;
define i64 @test_reduce_v8i64(<8 x i64> %a0) {
-; SSE-LABEL: @test_reduce_v8i64(
-; SSE-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> [[A0:%.*]])
-; SSE-NEXT: ret i64 [[TMP1]]
-;
-; AVX2-LABEL: @test_reduce_v8i64(
-; AVX2-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> [[A0:%.*]])
-; AVX2-NEXT: ret i64 [[TMP1]]
-;
-; AVX512-LABEL: @test_reduce_v8i64(
-; AVX512-NEXT: [[TMP1:%.*]] = shufflevector <8 x i64> [[A0:%.*]], <8 x i64> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP2:%.*]] = tail call <8 x i64> @llvm.smin.v8i64(<8 x i64> [[A0]], <8 x i64> [[TMP1]])
-; AVX512-NEXT: [[TMP3:%.*]] = shufflevector <8 x i64> [[TMP2]], <8 x i64> poison, <8 x i32> <i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP4:%.*]] = tail call <8 x i64> @llvm.smin.v8i64(<8 x i64> [[TMP2]], <8 x i64> [[TMP3]])
-; AVX512-NEXT: [[TMP5:%.*]] = shufflevector <8 x i64> [[TMP4]], <8 x i64> poison, <8 x i32> <i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP6:%.*]] = tail call <8 x i64> @llvm.smin.v8i64(<8 x i64> [[TMP4]], <8 x i64> [[TMP5]])
-; AVX512-NEXT: [[TMP7:%.*]] = extractelement <8 x i64> [[TMP6]], i64 0
-; AVX512-NEXT: ret i64 [[TMP7]]
+; CHECK-LABEL: @test_reduce_v8i64(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> [[A0:%.*]])
+; CHECK-NEXT: ret i64 [[TMP1]]
;
%1 = shufflevector <8 x i64> %a0, <8 x i64> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = icmp slt <8 x i64> %a0, %1
@@ -221,25 +183,9 @@ define i64 @test_reduce_v8i64(<8 x i64> %a0) {
}
define i32 @test_reduce_v16i32(<16 x i32> %a0) {
-; SSE-LABEL: @test_reduce_v16i32(
-; SSE-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> [[A0:%.*]])
-; SSE-NEXT: ret i32 [[TMP1]]
-;
-; AVX2-LABEL: @test_reduce_v16i32(
-; AVX2-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> [[A0:%.*]])
-; AVX2-NEXT: ret i32 [[TMP1]]
-;
-; AVX512-LABEL: @test_reduce_v16i32(
-; AVX512-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[A0:%.*]], <16 x i32> poison, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP2:%.*]] = tail call <16 x i32> @llvm.smin.v16i32(<16 x i32> [[A0]], <16 x i32> [[TMP1]])
-; AVX512-NEXT: [[TMP3:%.*]] = shufflevector <16 x i32> [[TMP2]], <16 x i32> poison, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP4:%.*]] = tail call <16 x i32> @llvm.smin.v16i32(<16 x i32> [[TMP2]], <16 x i32> [[TMP3]])
-; AVX512-NEXT: [[TMP5:%.*]] = shufflevector <16 x i32> [[TMP4]], <16 x i32> poison, <16 x i32> <i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP6:%.*]] = tail call <16 x i32> @llvm.smin.v16i32(<16 x i32> [[TMP4]], <16 x i32> [[TMP5]])
-; AVX512-NEXT: [[TMP7:%.*]] = shufflevector <16 x i32> [[TMP6]], <16 x i32> poison, <16 x i32> <i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP8:%.*]] = tail call <16 x i32> @llvm.smin.v16i32(<16 x i32> [[TMP6]], <16 x i32> [[TMP7]])
-; AVX512-NEXT: [[TMP9:%.*]] = extractelement <16 x i32> [[TMP8]], i64 0
-; AVX512-NEXT: ret i32 [[TMP9]]
+; CHECK-LABEL: @test_reduce_v16i32(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> [[A0:%.*]])
+; CHECK-NEXT: ret i32 [[TMP1]]
;
%1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = icmp slt <16 x i32> %a0, %1
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umax.ll b/llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umax.ll
index f7d5a99bc0da0..8a26fc17645c3 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umax.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umax.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64 | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v2 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v3 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v4 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s
;
; 128-bit Vectors
@@ -14,10 +14,8 @@
define i64 @test_reduce_v2i64(<2 x i64> %a0) {
; CHECK-LABEL: @test_reduce_v2i64(
-; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i64> [[A0:%.*]], <2 x i64> poison, <2 x i32> <i32 1, i32 poison>
-; CHECK-NEXT: [[TMP2:%.*]] = tail call <2 x i64> @llvm.umax.v2i64(<2 x i64> [[A0]], <2 x i64> [[TMP1]])
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP2]], i64 0
-; CHECK-NEXT: ret i64 [[TMP4]]
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> [[A0:%.*]])
+; CHECK-NEXT: ret i64 [[TMP1]]
;
%1 = shufflevector <2 x i64> %a0, <2 x i64> undef, <2 x i32> <i32 1, i32 undef>
%2 = icmp ugt <2 x i64> %a0, %1
@@ -28,11 +26,7 @@ define i64 @test_reduce_v2i64(<2 x i64> %a0) {
define i32 @test_reduce_v4i32(<4 x i32> %a0) {
; CHECK-LABEL: @test_reduce_v4i32(
-; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A0:%.*]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[A0]], <4 x i32> [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP4:%.*]] = tail call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[TMP2]], <4 x i32> [[TMP3]])
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[TMP4]], i64 0
+; CHECK-NEXT: [[TMP7:%.*]] = tail call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[A0:%.*]])
; CHECK-NEXT: ret i32 [[TMP7]]
;
%1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
@@ -89,17 +83,9 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) {
;
define i64 @test_reduce_v4i64(<4 x i64> %a0) {
-; SSE-LABEL: @test_reduce_v4i64(
-; SSE-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> [[A0:%.*]])
-; SSE-NEXT: ret i64 [[TMP1]]
-;
-; AVX-LABEL: @test_reduce_v4i64(
-; AVX-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> <i32 2, i32 3, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP2:%.*]] = tail call <4 x i64> @llvm.umax.v4i64(<4 x i64> [[A0]], <4 x i64> [[TMP1]])
-; AVX-NEXT: [[TMP3:%.*]] = shufflevector <4 x i64> [[TMP2]], <4 x i64> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP4:%.*]] = tail call <4 x i64> @llvm.umax.v4i64(<4 x i64> [[TMP2]], <4 x i64> [[TMP3]])
-; AVX-NEXT: [[TMP5:%.*]] = extractelement <4 x i64> [[TMP4]], i64 0
-; AVX-NEXT: ret i64 [[TMP5]]
+; CHECK-LABEL: @test_reduce_v4i64(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> [[A0:%.*]])
+; CHECK-NEXT: ret i64 [[TMP1]]
;
%1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
%2 = icmp ugt <4 x i64> %a0, %1
@@ -112,19 +98,9 @@ define i64 @test_reduce_v4i64(<4 x i64> %a0) {
}
define i32 @test_reduce_v8i32(<8 x i32> %a0) {
-; SSE-LABEL: @test_reduce_v8i32(
-; SSE-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> [[A0:%.*]])
-; SSE-NEXT: ret i32 [[TMP1]]
-;
-; AVX-LABEL: @test_reduce_v8i32(
-; AVX-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A0:%.*]], <8 x i32> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP2:%.*]] = tail call <8 x i32> @llvm.umax.v8i32(<8 x i32> [[A0]], <8 x i32> [[TMP1]])
-; AVX-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[TMP2]], <8 x i32> poison, <8 x i32> <i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP4:%.*]] = tail call <8 x i32> @llvm.umax.v8i32(<8 x i32> [[TMP2]], <8 x i32> [[TMP3]])
-; AVX-NEXT: [[TMP5:%.*]] = shufflevector <8 x i32> [[TMP4]], <8 x i32> poison, <8 x i32> <i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP6:%.*]] = tail call <8 x i32> @llvm.umax.v8i32(<8 x i32> [[TMP4]], <8 x i32> [[TMP5]])
-; AVX-NEXT: [[TMP7:%.*]] = extractelement <8 x i32> [[TMP6]], i64 0
-; AVX-NEXT: ret i32 [[TMP7]]
+; CHECK-LABEL: @test_reduce_v8i32(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> [[A0:%.*]])
+; CHECK-NEXT: ret i32 [[TMP1]]
;
%1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = icmp ugt <8 x i32> %a0, %1
@@ -189,23 +165,9 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) {
;
define i64 @test_reduce_v8i64(<8 x i64> %a0) {
-; SSE-LABEL: @test_reduce_v8i64(
-; SSE-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> [[A0:%.*]])
-; SSE-NEXT: ret i64 [[TMP1]]
-;
-; AVX2-LABEL: @test_reduce_v8i64(
-; AVX2-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> [[A0:%.*]])
-; AVX2-NEXT: ret i64 [[TMP1]]
-;
-; AVX512-LABEL: @test_reduce_v8i64(
-; AVX512-NEXT: [[TMP1:%.*]] = shufflevector <8 x i64> [[A0:%.*]], <8 x i64> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP2:%.*]] = tail call <8 x i64> @llvm.umax.v8i64(<8 x i64> [[A0]], <8 x i64> [[TMP1]])
-; AVX512-NEXT: [[TMP3:%.*]] = shufflevector <8 x i64> [[TMP2]], <8 x i64> poison, <8 x i32> <i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP4:%.*]] = tail call <8 x i64> @llvm.umax.v8i64(<8 x i64> [[TMP2]], <8 x i64> [[TMP3]])
-; AVX512-NEXT: [[TMP5:%.*]] = shufflevector <8 x i64> [[TMP4]], <8 x i64> poison, <8 x i32> <i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP6:%.*]] = tail call <8 x i64> @llvm.umax.v8i64(<8 x i64> [[TMP4]], <8 x i64> [[TMP5]])
-; AVX512-NEXT: [[TMP7:%.*]] = extractelement <8 x i64> [[TMP6]], i64 0
-; AVX512-NEXT: ret i64 [[TMP7]]
+; CHECK-LABEL: @test_reduce_v8i64(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> [[A0:%.*]])
+; CHECK-NEXT: ret i64 [[TMP1]]
;
%1 = shufflevector <8 x i64> %a0, <8 x i64> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = icmp ugt <8 x i64> %a0, %1
@@ -221,25 +183,9 @@ define i64 @test_reduce_v8i64(<8 x i64> %a0) {
}
define i32 @test_reduce_v16i32(<16 x i32> %a0) {
-; SSE-LABEL: @test_reduce_v16i32(
-; SSE-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> [[A0:%.*]])
-; SSE-NEXT: ret i32 [[TMP1]]
-;
-; AVX2-LABEL: @test_reduce_v16i32(
-; AVX2-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> [[A0:%.*]])
-; AVX2-NEXT: ret i32 [[TMP1]]
-;
-; AVX512-LABEL: @test_reduce_v16i32(
-; AVX512-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[A0:%.*]], <16 x i32> poison, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP2:%.*]] = tail call <16 x i32> @llvm.umax.v16i32(<16 x i32> [[A0]], <16 x i32> [[TMP1]])
-; AVX512-NEXT: [[TMP3:%.*]] = shufflevector <16 x i32> [[TMP2]], <16 x i32> poison, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP4:%.*]] = tail call <16 x i32> @llvm.umax.v16i32(<16 x i32> [[TMP2]], <16 x i32> [[TMP3]])
-; AVX512-NEXT: [[TMP5:%.*]] = shufflevector <16 x i32> [[TMP4]], <16 x i32> poison, <16 x i32> <i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP6:%.*]] = tail call <16 x i32> @llvm.umax.v16i32(<16 x i32> [[TMP4]], <16 x i32> [[TMP5]])
-; AVX512-NEXT: [[TMP7:%.*]] = shufflevector <16 x i32> [[TMP6]], <16 x i32> poison, <16 x i32> <i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP8:%.*]] = tail call <16 x i32> @llvm.umax.v16i32(<16 x i32> [[TMP6]], <16 x i32> [[TMP7]])
-; AVX512-NEXT: [[TMP9:%.*]] = extractelement <16 x i32> [[TMP8]], i64 0
-; AVX512-NEXT: ret i32 [[TMP9]]
+; CHECK-LABEL: @test_reduce_v16i32(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> [[A0:%.*]])
+; CHECK-NEXT: ret i32 [[TMP1]]
;
%1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = icmp ugt <16 x i32> %a0, %1
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umin.ll b/llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umin.ll
index e2fc523dd271c..a28c2eeb43084 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umin.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umin.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64 | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
-; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v2 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v3 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=i686-- -mcpu=x86-64-v4 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s
+; RUN: opt < %s -passes="default<O2>" -S -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s
;
; 128-bit Vectors
@@ -14,10 +14,8 @@
define i64 @test_reduce_v2i64(<2 x i64> %a0) {
; CHECK-LABEL: @test_reduce_v2i64(
-; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i64> [[A0:%.*]], <2 x i64> poison, <2 x i32> <i32 1, i32 poison>
-; CHECK-NEXT: [[TMP2:%.*]] = tail call <2 x i64> @llvm.umin.v2i64(<2 x i64> [[A0]], <2 x i64> [[TMP1]])
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP2]], i64 0
-; CHECK-NEXT: ret i64 [[TMP4]]
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> [[A0:%.*]])
+; CHECK-NEXT: ret i64 [[TMP1]]
;
%1 = shufflevector <2 x i64> %a0, <2 x i64> undef, <2 x i32> <i32 1, i32 undef>
%2 = icmp ult <2 x i64> %a0, %1
@@ -28,11 +26,7 @@ define i64 @test_reduce_v2i64(<2 x i64> %a0) {
define i32 @test_reduce_v4i32(<4 x i32> %a0) {
; CHECK-LABEL: @test_reduce_v4i32(
-; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A0:%.*]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x i32> @llvm.umin.v4i32(<4 x i32> [[A0]], <4 x i32> [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP4:%.*]] = tail call <4 x i32> @llvm.umin.v4i32(<4 x i32> [[TMP2]], <4 x i32> [[TMP3]])
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[TMP4]], i64 0
+; CHECK-NEXT: [[TMP7:%.*]] = tail call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[A0:%.*]])
; CHECK-NEXT: ret i32 [[TMP7]]
;
%1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
@@ -89,17 +83,9 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) {
;
define i64 @test_reduce_v4i64(<4 x i64> %a0) {
-; SSE-LABEL: @test_reduce_v4i64(
-; SSE-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> [[A0:%.*]])
-; SSE-NEXT: ret i64 [[TMP1]]
-;
-; AVX-LABEL: @test_reduce_v4i64(
-; AVX-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> <i32 2, i32 3, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP2:%.*]] = tail call <4 x i64> @llvm.umin.v4i64(<4 x i64> [[A0]], <4 x i64> [[TMP1]])
-; AVX-NEXT: [[TMP3:%.*]] = shufflevector <4 x i64> [[TMP2]], <4 x i64> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP4:%.*]] = tail call <4 x i64> @llvm.umin.v4i64(<4 x i64> [[TMP2]], <4 x i64> [[TMP3]])
-; AVX-NEXT: [[TMP5:%.*]] = extractelement <4 x i64> [[TMP4]], i64 0
-; AVX-NEXT: ret i64 [[TMP5]]
+; CHECK-LABEL: @test_reduce_v4i64(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> [[A0:%.*]])
+; CHECK-NEXT: ret i64 [[TMP1]]
;
%1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
%2 = icmp ult <4 x i64> %a0, %1
@@ -112,19 +98,9 @@ define i64 @test_reduce_v4i64(<4 x i64> %a0) {
}
define i32 @test_reduce_v8i32(<8 x i32> %a0) {
-; SSE-LABEL: @test_reduce_v8i32(
-; SSE-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> [[A0:%.*]])
-; SSE-NEXT: ret i32 [[TMP1]]
-;
-; AVX-LABEL: @test_reduce_v8i32(
-; AVX-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A0:%.*]], <8 x i32> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP2:%.*]] = tail call <8 x i32> @llvm.umin.v8i32(<8 x i32> [[A0]], <8 x i32> [[TMP1]])
-; AVX-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[TMP2]], <8 x i32> poison, <8 x i32> <i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP4:%.*]] = tail call <8 x i32> @llvm.umin.v8i32(<8 x i32> [[TMP2]], <8 x i32> [[TMP3]])
-; AVX-NEXT: [[TMP5:%.*]] = shufflevector <8 x i32> [[TMP4]], <8 x i32> poison, <8 x i32> <i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP6:%.*]] = tail call <8 x i32> @llvm.umin.v8i32(<8 x i32> [[TMP4]], <8 x i32> [[TMP5]])
-; AVX-NEXT: [[TMP7:%.*]] = extractelement <8 x i32> [[TMP6]], i64 0
-; AVX-NEXT: ret i32 [[TMP7]]
+; CHECK-LABEL: @test_reduce_v8i32(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> [[A0:%.*]])
+; CHECK-NEXT: ret i32 [[TMP1]]
;
%1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = icmp ult <8 x i32> %a0, %1
@@ -189,23 +165,9 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) {
;
define i64 @test_reduce_v8i64(<8 x i64> %a0) {
-; SSE-LABEL: @test_reduce_v8i64(
-; SSE-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> [[A0:%.*]])
-; SSE-NEXT: ret i64 [[TMP1]]
-;
-; AVX2-LABEL: @test_reduce_v8i64(
-; AVX2-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> [[A0:%.*]])
-; AVX2-NEXT: ret i64 [[TMP1]]
-;
-; AVX512-LABEL: @test_reduce_v8i64(
-; AVX512-NEXT: [[TMP1:%.*]] = shufflevector <8 x i64> [[A0:%.*]], <8 x i64> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP2:%.*]] = tail call <8 x i64> @llvm.umin.v8i64(<8 x i64> [[A0]], <8 x i64> [[TMP1]])
-; AVX512-NEXT: [[TMP3:%.*]] = shufflevector <8 x i64> [[TMP2]], <8 x i64> poison, <8 x i32> <i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP4:%.*]] = tail call <8 x i64> @llvm.umin.v8i64(<8 x i64> [[TMP2]], <8 x i64> [[TMP3]])
-; AVX512-NEXT: [[TMP5:%.*]] = shufflevector <8 x i64> [[TMP4]], <8 x i64> poison, <8 x i32> <i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP6:%.*]] = tail call <8 x i64> @llvm.umin.v8i64(<8 x i64> [[TMP4]], <8 x i64> [[TMP5]])
-; AVX512-NEXT: [[TMP7:%.*]] = extractelement <8 x i64> [[TMP6]], i64 0
-; AVX512-NEXT: ret i64 [[TMP7]]
+; CHECK-LABEL: @test_reduce_v8i64(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> [[A0:%.*]])
+; CHECK-NEXT: ret i64 [[TMP1]]
;
%1 = shufflevector <8 x i64> %a0, <8 x i64> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = icmp ult <8 x i64> %a0, %1
@@ -221,25 +183,9 @@ define i64 @test_reduce_v8i64(<8 x i64> %a0) {
}
define i32 @test_reduce_v16i32(<16 x i32> %a0) {
-; SSE-LABEL: @test_reduce_v16i32(
-; SSE-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> [[A0:%.*]])
-; SSE-NEXT: ret i32 [[TMP1]]
-;
-; AVX2-LABEL: @test_reduce_v16i32(
-; AVX2-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> [[A0:%.*]])
-; AVX2-NEXT: ret i32 [[TMP1]]
-;
-; AVX512-LABEL: @test_reduce_v16i32(
-; AVX512-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[A0:%.*]], <16 x i32> poison, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP2:%.*]] = tail call <16 x i32> @llvm.umin.v16i32(<16 x i32> [[A0]], <16 x i32> [[TMP1]])
-; AVX512-NEXT: [[TMP3:%.*]] = shufflevector <16 x i32> [[TMP2]], <16 x i32> poison, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP4:%.*]] = tail call <16 x i32> @llvm.umin.v16i32(<16 x i32> [[TMP2]], <16 x i32> [[TMP3]])
-; AVX512-NEXT: [[TMP5:%.*]] = shufflevector <16 x i32> [[TMP4]], <16 x i32> poison, <16 x i32> <i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP6:%.*]] = tail call <16 x i32> @llvm.umin.v16i32(<16 x i32> [[TMP4]], <16 x i32> [[TMP5]])
-; AVX512-NEXT: [[TMP7:%.*]] = shufflevector <16 x i32> [[TMP6]], <16 x i32> poison, <16 x i32> <i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[TMP8:%.*]] = tail call <16 x i32> @llvm.umin.v16i32(<16 x i32> [[TMP6]], <16 x i32> [[TMP7]])
-; AVX512-NEXT: [[TMP9:%.*]] = extractelement <16 x i32> [[TMP8]], i64 0
-; AVX512-NEXT: ret i32 [[TMP9]]
+; CHECK-LABEL: @test_reduce_v16i32(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> [[A0:%.*]])
+; CHECK-NEXT: ret i32 [[TMP1]]
;
%1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = icmp ult <16 x i32> %a0, %1
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll b/llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
index b6f1659c1bc59..b2b9363565277 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown-linux -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,DEFAULT,SSE2
; RUN: opt < %s -mtriple=x86_64-unknown-linux -mcpu=x86-64-v2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,DEFAULT,SSE4
-; RUN: opt < %s -mtriple=x86_64-unknown-linux -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,DEFAULT,AVX
-; RUN: opt < %s -mtriple=x86_64-unknown-linux -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,DEFAULT,AVX
+; RUN: opt < %s -mtriple=x86_64-unknown-linux -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,DEFAULT,AVX,AVX1
+; RUN: opt < %s -mtriple=x86_64-unknown-linux -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,DEFAULT,AVX,AVX2
; RUN: opt < %s -mtriple=x86_64-unknown-linux -mcpu=skx -passes=slp-vectorizer -S -slp-threshold=-100 | FileCheck %s --check-prefixes=CHECK,THRESH
@arr = local_unnamed_addr global [32 x i32] zeroinitializer, align 16
@@ -765,70 +765,24 @@ define float @maxf32(float) {
}
define i32 @maxi8_mutiple_uses(i32) {
-; SSE2-LABEL: @maxi8_mutiple_uses(
-; SSE2-NEXT: [[TMP2:%.*]] = load i32, ptr @arr, align 16
-; SSE2-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 1), align 4
-; SSE2-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[TMP2]], [[TMP3]]
-; SSE2-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i32 [[TMP2]], i32 [[TMP3]]
-; SSE2-NEXT: [[TMP6:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
-; SSE2-NEXT: [[TMP7:%.*]] = icmp sgt i32 [[TMP5]], [[TMP6]]
-; SSE2-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], i32 [[TMP5]], i32 [[TMP6]]
-; SSE2-NEXT: [[TMP9:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 3), align 4
-; SSE2-NEXT: [[TMP10:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]]
-; SSE2-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i32 [[TMP8]], i32 [[TMP9]]
-; SSE2-NEXT: [[TMP12:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 4), align 16
-; SSE2-NEXT: [[TMP13:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]]
-; SSE2-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i32 [[TMP11]], i32 [[TMP12]]
-; SSE2-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 5), align 4
-; SSE2-NEXT: [[TMP16:%.*]] = icmp sgt i32 [[TMP14]], [[TMP15]]
-; SSE2-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP14]], i32 [[TMP15]]
-; SSE2-NEXT: [[TMP18:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 6), align 8
-; SSE2-NEXT: [[TMP19:%.*]] = icmp sgt i32 [[TMP17]], [[TMP18]]
-; SSE2-NEXT: [[TMP20:%.*]] = select i1 [[TMP19]], i32 [[TMP17]], i32 [[TMP18]]
-; SSE2-NEXT: [[TMP21:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 7), align 4
-; SSE2-NEXT: [[TMP22:%.*]] = icmp sgt i32 [[TMP20]], [[TMP21]]
-; SSE2-NEXT: [[TMP23:%.*]] = select i1 [[TMP22]], i32 [[TMP20]], i32 [[TMP21]]
-; SSE2-NEXT: [[TMP24:%.*]] = select i1 [[TMP4]], i32 3, i32 4
-; SSE2-NEXT: store i32 [[TMP24]], ptr @var, align 8
-; SSE2-NEXT: ret i32 [[TMP23]]
-;
-; SSE4-LABEL: @maxi8_mutiple_uses(
-; SSE4-NEXT: [[TMP2:%.*]] = load i32, ptr @arr, align 16
-; SSE4-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 1), align 4
-; SSE4-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[TMP2]], [[TMP3]]
-; SSE4-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i32 [[TMP2]], i32 [[TMP3]]
-; SSE4-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
-; SSE4-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 6), align 8
-; SSE4-NEXT: [[TMP8:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 7), align 4
-; SSE4-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP6]])
-; SSE4-NEXT: [[OP_RDX:%.*]] = icmp sgt i32 [[TMP9]], [[TMP7]]
-; SSE4-NEXT: [[OP_RDX1:%.*]] = select i1 [[OP_RDX]], i32 [[TMP9]], i32 [[TMP7]]
-; SSE4-NEXT: [[OP_RDX2:%.*]] = icmp sgt i32 [[TMP8]], [[TMP5]]
-; SSE4-NEXT: [[OP_RDX3:%.*]] = select i1 [[OP_RDX2]], i32 [[TMP8]], i32 [[TMP5]]
-; SSE4-NEXT: [[OP_RDX4:%.*]] = icmp sgt i32 [[OP_RDX1]], [[OP_RDX3]]
-; SSE4-NEXT: [[OP_RDX5:%.*]] = select i1 [[OP_RDX4]], i32 [[OP_RDX1]], i32 [[OP_RDX3]]
-; SSE4-NEXT: [[TMP10:%.*]] = select i1 [[TMP4]], i32 3, i32 4
-; SSE4-NEXT: store i32 [[TMP10]], ptr @var, align 8
-; SSE4-NEXT: ret i32 [[OP_RDX5]]
-;
-; AVX-LABEL: @maxi8_mutiple_uses(
-; AVX-NEXT: [[TMP2:%.*]] = load i32, ptr @arr, align 16
-; AVX-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 1), align 4
-; AVX-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[TMP2]], [[TMP3]]
-; AVX-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i32 [[TMP2]], i32 [[TMP3]]
-; AVX-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
-; AVX-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 6), align 8
-; AVX-NEXT: [[TMP8:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 7), align 4
-; AVX-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP6]])
-; AVX-NEXT: [[OP_RDX:%.*]] = icmp sgt i32 [[TMP9]], [[TMP7]]
-; AVX-NEXT: [[OP_RDX1:%.*]] = select i1 [[OP_RDX]], i32 [[TMP9]], i32 [[TMP7]]
-; AVX-NEXT: [[OP_RDX2:%.*]] = icmp sgt i32 [[TMP8]], [[TMP5]]
-; AVX-NEXT: [[OP_RDX3:%.*]] = select i1 [[OP_RDX2]], i32 [[TMP8]], i32 [[TMP5]]
-; AVX-NEXT: [[OP_RDX4:%.*]] = icmp sgt i32 [[OP_RDX1]], [[OP_RDX3]]
-; AVX-NEXT: [[OP_RDX5:%.*]] = select i1 [[OP_RDX4]], i32 [[OP_RDX1]], i32 [[OP_RDX3]]
-; AVX-NEXT: [[TMP10:%.*]] = select i1 [[TMP4]], i32 3, i32 4
-; AVX-NEXT: store i32 [[TMP10]], ptr @var, align 8
-; AVX-NEXT: ret i32 [[OP_RDX5]]
+; DEFAULT-LABEL: @maxi8_mutiple_uses(
+; DEFAULT-NEXT: [[TMP2:%.*]] = load i32, ptr @arr, align 16
+; DEFAULT-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 1), align 4
+; DEFAULT-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[TMP2]], [[TMP3]]
+; DEFAULT-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i32 [[TMP2]], i32 [[TMP3]]
+; DEFAULT-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
+; DEFAULT-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 6), align 8
+; DEFAULT-NEXT: [[TMP8:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 7), align 4
+; DEFAULT-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP6]])
+; DEFAULT-NEXT: [[OP_RDX:%.*]] = icmp sgt i32 [[TMP9]], [[TMP7]]
+; DEFAULT-NEXT: [[OP_RDX1:%.*]] = select i1 [[OP_RDX]], i32 [[TMP9]], i32 [[TMP7]]
+; DEFAULT-NEXT: [[OP_RDX2:%.*]] = icmp sgt i32 [[TMP8]], [[TMP5]]
+; DEFAULT-NEXT: [[OP_RDX3:%.*]] = select i1 [[OP_RDX2]], i32 [[TMP8]], i32 [[TMP5]]
+; DEFAULT-NEXT: [[OP_RDX4:%.*]] = icmp sgt i32 [[OP_RDX1]], [[OP_RDX3]]
+; DEFAULT-NEXT: [[OP_RDX5:%.*]] = select i1 [[OP_RDX4]], i32 [[OP_RDX1]], i32 [[OP_RDX3]]
+; DEFAULT-NEXT: [[TMP10:%.*]] = select i1 [[TMP4]], i32 3, i32 4
+; DEFAULT-NEXT: store i32 [[TMP10]], ptr @var, align 8
+; DEFAULT-NEXT: ret i32 [[OP_RDX5]]
;
; THRESH-LABEL: @maxi8_mutiple_uses(
; THRESH-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @arr, align 16
@@ -944,76 +898,20 @@ define i32 @maxi8_mutiple_uses2(i32) {
}
define i32 @maxi8_wrong_parent(i32) {
-; SSE2-LABEL: @maxi8_wrong_parent(
-; SSE2-NEXT: [[TMP2:%.*]] = load i32, ptr @arr, align 16
-; SSE2-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 1), align 4
-; SSE2-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[TMP2]], [[TMP3]]
-; SSE2-NEXT: br label [[PP:%.*]]
-; SSE2: pp:
-; SSE2-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i32 [[TMP2]], i32 [[TMP3]]
-; SSE2-NEXT: [[TMP6:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
-; SSE2-NEXT: [[TMP7:%.*]] = icmp sgt i32 [[TMP5]], [[TMP6]]
-; SSE2-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], i32 [[TMP5]], i32 [[TMP6]]
-; SSE2-NEXT: [[TMP9:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 3), align 4
-; SSE2-NEXT: [[TMP10:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]]
-; SSE2-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i32 [[TMP8]], i32 [[TMP9]]
-; SSE2-NEXT: [[TMP12:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 4), align 16
-; SSE2-NEXT: [[TMP13:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]]
-; SSE2-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i32 [[TMP11]], i32 [[TMP12]]
-; SSE2-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 5), align 4
-; SSE2-NEXT: [[TMP16:%.*]] = icmp sgt i32 [[TMP14]], [[TMP15]]
-; SSE2-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP14]], i32 [[TMP15]]
-; SSE2-NEXT: [[TMP18:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 6), align 8
-; SSE2-NEXT: [[TMP19:%.*]] = icmp sgt i32 [[TMP17]], [[TMP18]]
-; SSE2-NEXT: [[TMP20:%.*]] = select i1 [[TMP19]], i32 [[TMP17]], i32 [[TMP18]]
-; SSE2-NEXT: [[TMP21:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 7), align 4
-; SSE2-NEXT: [[TMP22:%.*]] = icmp sgt i32 [[TMP20]], [[TMP21]]
-; SSE2-NEXT: [[TMP23:%.*]] = select i1 [[TMP22]], i32 [[TMP20]], i32 [[TMP21]]
-; SSE2-NEXT: ret i32 [[TMP23]]
-;
-; SSE4-LABEL: @maxi8_wrong_parent(
-; SSE4-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @arr, align 16
-; SSE4-NEXT: br label [[PP:%.*]]
-; SSE4: pp:
-; SSE4-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
-; SSE4-NEXT: [[TMP8:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 6), align 8
-; SSE4-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
-; SSE4-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP8]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; SSE4-NEXT: [[TMP10:%.*]] = shufflevector <2 x i32> [[TMP8]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
-; SSE4-NEXT: [[TMP11:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> [[TMP10]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 poison, i32 poison>
-; SSE4-NEXT: [[TMP9:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; SSE4-NEXT: [[TMP7:%.*]] = shufflevector <8 x i32> [[TMP11]], <8 x i32> [[TMP9]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
-; SSE4-NEXT: [[OP_RDX7:%.*]] = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> [[TMP7]])
-; SSE4-NEXT: ret i32 [[OP_RDX7]]
-;
-; AVX-LABEL: @maxi8_wrong_parent(
-; AVX-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @arr, align 16
-; AVX-NEXT: br label [[PP:%.*]]
-; AVX: pp:
-; AVX-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
-; AVX-NEXT: [[TMP7:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 6), align 8
-; AVX-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP7]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP8:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP7]], <2 x i32> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; AVX-NEXT: [[RDX_OP:%.*]] = icmp sgt <4 x i32> [[TMP4]], [[TMP6]]
-; AVX-NEXT: [[RDX_OP1:%.*]] = select <4 x i1> [[RDX_OP]], <4 x i32> [[TMP4]], <4 x i32> [[TMP6]]
-; AVX-NEXT: [[OP_RDX7:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[RDX_OP1]])
-; AVX-NEXT: ret i32 [[OP_RDX7]]
-;
-; THRESH-LABEL: @maxi8_wrong_parent(
-; THRESH-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @arr, align 16
-; THRESH-NEXT: br label [[PP:%.*]]
-; THRESH: pp:
-; THRESH-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
-; THRESH-NEXT: [[TMP4:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 6), align 8
-; THRESH-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
-; THRESH-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; THRESH-NEXT: [[TMP10:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
-; THRESH-NEXT: [[TMP11:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> [[TMP10]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 poison, i32 poison>
-; THRESH-NEXT: [[TMP9:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; THRESH-NEXT: [[TMP7:%.*]] = shufflevector <8 x i32> [[TMP11]], <8 x i32> [[TMP9]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
-; THRESH-NEXT: [[TMP8:%.*]] = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> [[TMP7]])
-; THRESH-NEXT: ret i32 [[TMP8]]
+; CHECK-LABEL: @maxi8_wrong_parent(
+; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @arr, align 16
+; CHECK-NEXT: br label [[PP:%.*]]
+; CHECK: pp:
+; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
+; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 6), align 8
+; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> [[TMP7]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> [[TMP9]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
+; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> [[TMP10]])
+; CHECK-NEXT: ret i32 [[TMP11]]
;
%2 = load i32, ptr @arr, align 16
%3 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 1), align 4
@@ -1184,18 +1082,49 @@ define i16 @smin_intrinsic_rdx_v8i16(ptr %p0) {
}
define i64 @umax_intrinsic_rdx_v4i64(ptr %p0) {
-; DEFAULT-LABEL: @umax_intrinsic_rdx_v4i64(
-; DEFAULT-NEXT: [[P1:%.*]] = getelementptr inbounds i64, ptr [[P0:%.*]], i64 1
-; DEFAULT-NEXT: [[P2:%.*]] = getelementptr inbounds i64, ptr [[P0]], i64 2
-; DEFAULT-NEXT: [[P3:%.*]] = getelementptr inbounds i64, ptr [[P0]], i64 3
-; DEFAULT-NEXT: [[T0:%.*]] = load i64, ptr [[P0]], align 4
-; DEFAULT-NEXT: [[T1:%.*]] = load i64, ptr [[P1]], align 4
-; DEFAULT-NEXT: [[T2:%.*]] = load i64, ptr [[P2]], align 4
-; DEFAULT-NEXT: [[T3:%.*]] = load i64, ptr [[P3]], align 4
-; DEFAULT-NEXT: [[M10:%.*]] = tail call i64 @llvm.umax.i64(i64 [[T1]], i64 [[T0]])
-; DEFAULT-NEXT: [[M32:%.*]] = tail call i64 @llvm.umax.i64(i64 [[T3]], i64 [[T2]])
-; DEFAULT-NEXT: [[M:%.*]] = tail call i64 @llvm.umax.i64(i64 [[M32]], i64 [[M10]])
-; DEFAULT-NEXT: ret i64 [[M]]
+; SSE2-LABEL: @umax_intrinsic_rdx_v4i64(
+; SSE2-NEXT: [[P1:%.*]] = getelementptr inbounds i64, ptr [[P0:%.*]], i64 1
+; SSE2-NEXT: [[P2:%.*]] = getelementptr inbounds i64, ptr [[P0]], i64 2
+; SSE2-NEXT: [[P3:%.*]] = getelementptr inbounds i64, ptr [[P0]], i64 3
+; SSE2-NEXT: [[T0:%.*]] = load i64, ptr [[P0]], align 4
+; SSE2-NEXT: [[T1:%.*]] = load i64, ptr [[P1]], align 4
+; SSE2-NEXT: [[T2:%.*]] = load i64, ptr [[P2]], align 4
+; SSE2-NEXT: [[T3:%.*]] = load i64, ptr [[P3]], align 4
+; SSE2-NEXT: [[M10:%.*]] = tail call i64 @llvm.umax.i64(i64 [[T1]], i64 [[T0]])
+; SSE2-NEXT: [[M32:%.*]] = tail call i64 @llvm.umax.i64(i64 [[T3]], i64 [[T2]])
+; SSE2-NEXT: [[M:%.*]] = tail call i64 @llvm.umax.i64(i64 [[M32]], i64 [[M10]])
+; SSE2-NEXT: ret i64 [[M]]
+;
+; SSE4-LABEL: @umax_intrinsic_rdx_v4i64(
+; SSE4-NEXT: [[P1:%.*]] = getelementptr inbounds i64, ptr [[P0:%.*]], i64 1
+; SSE4-NEXT: [[P2:%.*]] = getelementptr inbounds i64, ptr [[P0]], i64 2
+; SSE4-NEXT: [[P3:%.*]] = getelementptr inbounds i64, ptr [[P0]], i64 3
+; SSE4-NEXT: [[T0:%.*]] = load i64, ptr [[P0]], align 4
+; SSE4-NEXT: [[T1:%.*]] = load i64, ptr [[P1]], align 4
+; SSE4-NEXT: [[T2:%.*]] = load i64, ptr [[P2]], align 4
+; SSE4-NEXT: [[T3:%.*]] = load i64, ptr [[P3]], align 4
+; SSE4-NEXT: [[M10:%.*]] = tail call i64 @llvm.umax.i64(i64 [[T1]], i64 [[T0]])
+; SSE4-NEXT: [[M32:%.*]] = tail call i64 @llvm.umax.i64(i64 [[T3]], i64 [[T2]])
+; SSE4-NEXT: [[M:%.*]] = tail call i64 @llvm.umax.i64(i64 [[M32]], i64 [[M10]])
+; SSE4-NEXT: ret i64 [[M]]
+;
+; AVX1-LABEL: @umax_intrinsic_rdx_v4i64(
+; AVX1-NEXT: [[P1:%.*]] = getelementptr inbounds i64, ptr [[P0:%.*]], i64 1
+; AVX1-NEXT: [[P2:%.*]] = getelementptr inbounds i64, ptr [[P0]], i64 2
+; AVX1-NEXT: [[P3:%.*]] = getelementptr inbounds i64, ptr [[P0]], i64 3
+; AVX1-NEXT: [[T0:%.*]] = load i64, ptr [[P0]], align 4
+; AVX1-NEXT: [[T1:%.*]] = load i64, ptr [[P1]], align 4
+; AVX1-NEXT: [[T2:%.*]] = load i64, ptr [[P2]], align 4
+; AVX1-NEXT: [[T3:%.*]] = load i64, ptr [[P3]], align 4
+; AVX1-NEXT: [[M10:%.*]] = tail call i64 @llvm.umax.i64(i64 [[T1]], i64 [[T0]])
+; AVX1-NEXT: [[M32:%.*]] = tail call i64 @llvm.umax.i64(i64 [[T3]], i64 [[T2]])
+; AVX1-NEXT: [[M:%.*]] = tail call i64 @llvm.umax.i64(i64 [[M32]], i64 [[M10]])
+; AVX1-NEXT: ret i64 [[M]]
+;
+; AVX2-LABEL: @umax_intrinsic_rdx_v4i64(
+; AVX2-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr [[P0:%.*]], align 4
+; AVX2-NEXT: [[TMP2:%.*]] = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> [[TMP1]])
+; AVX2-NEXT: ret i64 [[TMP2]]
;
; THRESH-LABEL: @umax_intrinsic_rdx_v4i64(
; THRESH-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr [[P0:%.*]], align 4
@@ -1300,3 +1229,5 @@ define void @PR49730() {
%t14 = call i32 @llvm.umin.i32(i32 %t13, i32 93)
ret void
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/horizontal-smax.ll b/llvm/test/Transforms/SLPVectorizer/X86/horizontal-smax.ll
index 15538789e46e2..ff3d59848cefc 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/horizontal-smax.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/horizontal-smax.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -mtriple=x86_64-unknown-linux -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE2
-; RUN: opt < %s -mtriple=x86_64-unknown-linux -mcpu=x86-64-v2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE4
-; RUN: opt < %s -mtriple=x86_64-unknown-linux -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX
-; RUN: opt < %s -mtriple=x86_64-unknown-linux -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX
+; RUN: opt < %s -mtriple=x86_64-unknown-linux -passes=slp-vectorizer -S | FileCheck %s
+; RUN: opt < %s -mtriple=x86_64-unknown-linux -mcpu=x86-64-v2 -passes=slp-vectorizer -S | FileCheck %s
+; RUN: opt < %s -mtriple=x86_64-unknown-linux -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s
+; RUN: opt < %s -mtriple=x86_64-unknown-linux -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s
@arr = local_unnamed_addr global [32 x i32] zeroinitializer, align 16
@@ -22,25 +22,10 @@ define i32 @smax_v2i32(i32) {
}
define i32 @smax_v4i32(i32) {
-; SSE2-LABEL: @smax_v4i32(
-; SSE2-NEXT: [[TMP2:%.*]] = load i32, ptr @arr, align 16
-; SSE2-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 1), align 4
-; SSE2-NEXT: [[TMP4:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
-; SSE2-NEXT: [[TMP5:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 3), align 4
-; SSE2-NEXT: [[TMP6:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP2]], i32 [[TMP3]])
-; SSE2-NEXT: [[TMP7:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP6]], i32 [[TMP4]])
-; SSE2-NEXT: [[TMP8:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP7]], i32 [[TMP5]])
-; SSE2-NEXT: ret i32 [[TMP8]]
-;
-; SSE4-LABEL: @smax_v4i32(
-; SSE4-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @arr, align 16
-; SSE4-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP2]])
-; SSE4-NEXT: ret i32 [[TMP3]]
-;
-; AVX-LABEL: @smax_v4i32(
-; AVX-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @arr, align 16
-; AVX-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP2]])
-; AVX-NEXT: ret i32 [[TMP3]]
+; CHECK-LABEL: @smax_v4i32(
+; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @arr, align 16
+; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP2]])
+; CHECK-NEXT: ret i32 [[TMP3]]
;
%2 = load i32, ptr @arr, align 16
%3 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 1), align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll b/llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll
index c3dfaf81b97bb..eef0e092200b3 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll
@@ -21,21 +21,13 @@ define void @n() local_unnamed_addr #0 {
; CHECK-NEXT: [[TMP6:%.*]] = icmp slt <32 x i32> [[TMP5]], zeroinitializer
; CHECK-NEXT: [[TMP7:%.*]] = sub nsw <32 x i32> zeroinitializer, [[TMP5]]
; CHECK-NEXT: [[TMP8:%.*]] = select <32 x i1> [[TMP6]], <32 x i32> [[TMP7]], <32 x i32> [[TMP5]]
-; CHECK-NEXT: [[TMP37:%.*]] = extractelement <32 x i32> [[TMP8]], i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <32 x i32> [[TMP8]], <32 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: [[TMP37:%.*]] = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> [[TMP9]])
; CHECK-NEXT: [[OP_RDX:%.*]] = icmp slt i32 [[TMP37]], [[B_0]]
; CHECK-NEXT: [[OP_RDX1:%.*]] = select i1 [[OP_RDX]], i32 [[TMP37]], i32 [[B_0]]
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <32 x i32> [[TMP8]], i32 1
-; CHECK-NEXT: [[CMP12_1:%.*]] = icmp slt i32 [[TMP10]], [[OP_RDX1]]
-; CHECK-NEXT: [[SUB_116:%.*]] = select i1 [[CMP12_1]], i32 [[TMP10]], i32 [[OP_RDX1]]
-; CHECK-NEXT: [[NEG_117:%.*]] = extractelement <32 x i32> [[TMP8]], i32 2
-; CHECK-NEXT: [[TMP38:%.*]] = icmp slt i32 [[NEG_117]], [[SUB_116]]
-; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP38]], i32 [[NEG_117]], i32 [[SUB_116]]
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <32 x i32> [[TMP8]], i32 3
-; CHECK-NEXT: [[CMP12_3:%.*]] = icmp slt i32 [[TMP12]], [[TMP39]]
-; CHECK-NEXT: [[SPEC_SELECT8_3:%.*]] = select i1 [[CMP12_3]], i32 [[TMP12]], i32 [[TMP39]]
; CHECK-NEXT: [[TMP13:%.*]] = extractelement <32 x i32> [[TMP8]], i32 4
-; CHECK-NEXT: [[CMP12_118:%.*]] = icmp slt i32 [[TMP13]], [[SPEC_SELECT8_3]]
-; CHECK-NEXT: [[SPEC_SELECT8_120:%.*]] = select i1 [[CMP12_118]], i32 [[TMP13]], i32 [[SPEC_SELECT8_3]]
+; CHECK-NEXT: [[CMP12_118:%.*]] = icmp slt i32 [[TMP13]], [[OP_RDX1]]
+; CHECK-NEXT: [[SPEC_SELECT8_120:%.*]] = select i1 [[CMP12_118]], i32 [[TMP13]], i32 [[OP_RDX1]]
; CHECK-NEXT: [[TMP41:%.*]] = extractelement <32 x i32> [[TMP8]], i32 5
; CHECK-NEXT: [[CMP12_1_1:%.*]] = icmp slt i32 [[TMP41]], [[SPEC_SELECT8_120]]
; CHECK-NEXT: [[NARROW:%.*]] = or i1 [[CMP12_1_1]], [[CMP12_118]]
diff --git a/llvm/test/Transforms/VectorCombine/X86/fold-equivalent-reduction-cmp.ll b/llvm/test/Transforms/VectorCombine/X86/fold-equivalent-reduction-cmp.ll
index 0edf6530c1c3b..f103da3ee7342 100644
--- a/llvm/test/Transforms/VectorCombine/X86/fold-equivalent-reduction-cmp.ll
+++ b/llvm/test/Transforms/VectorCombine/X86/fold-equivalent-reduction-cmp.ll
@@ -4,7 +4,7 @@
define i1 @or_eq_0(<4 x i32> %x) {
; CHECK-LABEL: define i1 @or_eq_0(
; CHECK-SAME: <4 x i32> [[X:%.*]]) #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[RED]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -16,7 +16,7 @@ define i1 @or_eq_0(<4 x i32> %x) {
define i1 @or_ne_0(<4 x i32> %x) {
; CHECK-LABEL: define i1 @or_ne_0(
; CHECK-SAME: <4 x i32> [[X:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[RED]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -28,7 +28,7 @@ define i1 @or_ne_0(<4 x i32> %x) {
define i1 @or_slt_0(<4 x i32> %x) {
; CHECK-LABEL: define i1 @or_slt_0(
; CHECK-SAME: <4 x i32> [[X:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[RED]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -40,7 +40,7 @@ define i1 @or_slt_0(<4 x i32> %x) {
define i1 @or_sgt_m1(<4 x i32> %x) {
; CHECK-LABEL: define i1 @or_sgt_m1(
; CHECK-SAME: <4 x i32> [[X:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[RED]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -52,7 +52,7 @@ define i1 @or_sgt_m1(<4 x i32> %x) {
define i1 @and_eq_allones(<4 x i32> %x) {
; CHECK-LABEL: define i1 @and_eq_allones(
; CHECK-SAME: <4 x i32> [[X:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[RED]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -64,7 +64,7 @@ define i1 @and_eq_allones(<4 x i32> %x) {
define i1 @and_ne_allones(<4 x i32> %x) {
; CHECK-LABEL: define i1 @and_ne_allones(
; CHECK-SAME: <4 x i32> [[X:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[RED]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -76,7 +76,7 @@ define i1 @and_ne_allones(<4 x i32> %x) {
define i1 @and_slt_0(<4 x i32> %x) {
; CHECK-LABEL: define i1 @and_slt_0(
; CHECK-SAME: <4 x i32> [[X:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[RED]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -88,7 +88,7 @@ define i1 @and_slt_0(<4 x i32> %x) {
define i1 @and_sgt_m1(<4 x i32> %x) {
; CHECK-LABEL: define i1 @and_sgt_m1(
; CHECK-SAME: <4 x i32> [[X:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[RED]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -232,7 +232,7 @@ define i1 @umax_eq_0_i8(<16 x i8> %x) {
define i1 @umin_eq_allones_i64(<2 x i64> %x) {
; CHECK-LABEL: define i1 @umin_eq_allones_i64(
; CHECK-SAME: <2 x i64> [[X:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[TMP1]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
diff --git a/llvm/test/Transforms/VectorCombine/X86/fold-signbit-reduction-cmp.ll b/llvm/test/Transforms/VectorCombine/X86/fold-signbit-reduction-cmp.ll
index 5bfc55d5a37ed..e24053604adec 100644
--- a/llvm/test/Transforms/VectorCombine/X86/fold-signbit-reduction-cmp.ll
+++ b/llvm/test/Transforms/VectorCombine/X86/fold-signbit-reduction-cmp.ll
@@ -4,7 +4,7 @@
define i1 @or_eq_0(<4 x i32> %x) {
; CHECK-LABEL: define i1 @or_eq_0(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -17,7 +17,7 @@ define i1 @or_eq_0(<4 x i32> %x) {
define i1 @or_ne_0(<4 x i32> %x) {
; CHECK-LABEL: define i1 @or_ne_0(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -30,7 +30,7 @@ define i1 @or_ne_0(<4 x i32> %x) {
define i1 @or_eq_max(<4 x i32> %x) {
; CHECK-LABEL: define i1 @or_eq_max(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -43,7 +43,7 @@ define i1 @or_eq_max(<4 x i32> %x) {
define i1 @or_ne_max(<4 x i32> %x) {
; CHECK-LABEL: define i1 @or_ne_max(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -56,7 +56,7 @@ define i1 @or_ne_max(<4 x i32> %x) {
define i1 @umax_eq_0(<4 x i32> %x) {
; CHECK-LABEL: define i1 @umax_eq_0(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -69,7 +69,7 @@ define i1 @umax_eq_0(<4 x i32> %x) {
define i1 @umax_ne_0(<4 x i32> %x) {
; CHECK-LABEL: define i1 @umax_ne_0(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -82,7 +82,7 @@ define i1 @umax_ne_0(<4 x i32> %x) {
define i1 @umax_eq_max(<4 x i32> %x) {
; CHECK-LABEL: define i1 @umax_eq_max(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -95,7 +95,7 @@ define i1 @umax_eq_max(<4 x i32> %x) {
define i1 @umax_ne_max(<4 x i32> %x) {
; CHECK-LABEL: define i1 @umax_ne_max(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -108,7 +108,7 @@ define i1 @umax_ne_max(<4 x i32> %x) {
define i1 @and_eq_0(<4 x i32> %x) {
; CHECK-LABEL: define i1 @and_eq_0(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -121,7 +121,7 @@ define i1 @and_eq_0(<4 x i32> %x) {
define i1 @and_ne_0(<4 x i32> %x) {
; CHECK-LABEL: define i1 @and_ne_0(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -134,7 +134,7 @@ define i1 @and_ne_0(<4 x i32> %x) {
define i1 @and_eq_max(<4 x i32> %x) {
; CHECK-LABEL: define i1 @and_eq_max(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -147,7 +147,7 @@ define i1 @and_eq_max(<4 x i32> %x) {
define i1 @and_ne_max(<4 x i32> %x) {
; CHECK-LABEL: define i1 @and_ne_max(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -160,7 +160,7 @@ define i1 @and_ne_max(<4 x i32> %x) {
define i1 @umin_eq_0(<4 x i32> %x) {
; CHECK-LABEL: define i1 @umin_eq_0(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -173,7 +173,7 @@ define i1 @umin_eq_0(<4 x i32> %x) {
define i1 @umin_ne_0(<4 x i32> %x) {
; CHECK-LABEL: define i1 @umin_ne_0(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -186,7 +186,7 @@ define i1 @umin_ne_0(<4 x i32> %x) {
define i1 @umin_eq_max(<4 x i32> %x) {
; CHECK-LABEL: define i1 @umin_eq_max(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -199,7 +199,7 @@ define i1 @umin_eq_max(<4 x i32> %x) {
define i1 @umin_ne_max(<4 x i32> %x) {
; CHECK-LABEL: define i1 @umin_ne_max(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -212,9 +212,8 @@ define i1 @umin_ne_max(<4 x i32> %x) {
define i1 @add_eq_0(<4 x i32> %x) {
; CHECK-LABEL: define i1 @add_eq_0(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[SHR:%.*]] = lshr <4 x i32> [[X]], splat (i32 31)
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[SHR]])
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[RED]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
%shr = lshr <4 x i32> %x, splat (i32 31)
@@ -226,9 +225,8 @@ define i1 @add_eq_0(<4 x i32> %x) {
define i1 @add_ne_0(<4 x i32> %x) {
; CHECK-LABEL: define i1 @add_ne_0(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[SHR:%.*]] = lshr <4 x i32> [[X]], splat (i32 31)
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[SHR]])
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[RED]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
%shr = lshr <4 x i32> %x, splat (i32 31)
@@ -240,9 +238,8 @@ define i1 @add_ne_0(<4 x i32> %x) {
define i1 @add_eq_max(<4 x i32> %x) {
; CHECK-LABEL: define i1 @add_eq_max(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[SHR:%.*]] = lshr <4 x i32> [[X]], splat (i32 31)
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[SHR]])
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[RED]], 4
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
%shr = lshr <4 x i32> %x, splat (i32 31)
@@ -254,9 +251,8 @@ define i1 @add_eq_max(<4 x i32> %x) {
define i1 @add_ne_max(<4 x i32> %x) {
; CHECK-LABEL: define i1 @add_ne_max(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[SHR:%.*]] = lshr <4 x i32> [[X]], splat (i32 31)
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[SHR]])
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[RED]], 4
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
%shr = lshr <4 x i32> %x, splat (i32 31)
@@ -268,9 +264,8 @@ define i1 @add_ne_max(<4 x i32> %x) {
define i1 @add_ult_max(<4 x i32> %x) {
; CHECK-LABEL: define i1 @add_ult_max(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[SHR:%.*]] = lshr <4 x i32> [[X]], splat (i32 31)
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[SHR]])
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[RED]], 4
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
%shr = lshr <4 x i32> %x, splat (i32 31)
@@ -282,9 +277,8 @@ define i1 @add_ult_max(<4 x i32> %x) {
define i1 @add_ugt_max_minus_1(<4 x i32> %x) {
; CHECK-LABEL: define i1 @add_ugt_max_minus_1(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[SHR:%.*]] = lshr <4 x i32> [[X]], splat (i32 31)
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[SHR]])
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[RED]], 3
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
%shr = lshr <4 x i32> %x, splat (i32 31)
@@ -296,9 +290,8 @@ define i1 @add_ugt_max_minus_1(<4 x i32> %x) {
define i1 @ashr_add_eq_0(<4 x i32> %x) {
; CHECK-LABEL: define i1 @ashr_add_eq_0(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[X]], splat (i32 31)
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[SHR]])
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[RED]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
%shr = ashr <4 x i32> %x, splat (i32 31)
@@ -310,7 +303,7 @@ define i1 @ashr_add_eq_0(<4 x i32> %x) {
define i1 @or_eq_0_v8i16(<8 x i16> %x) {
; CHECK-LABEL: define i1 @or_eq_0_v8i16(
; CHECK-SAME: <8 x i16> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i16 [[TMP1]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -428,9 +421,8 @@ define i1 @negative_add_numelts_overflow(<8 x i2> %x) {
define i1 @ashr_add_eq_allneg(<4 x i32> %x) {
; CHECK-LABEL: define i1 @ashr_add_eq_allneg(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[X]], splat (i32 31)
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[SHR]])
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[RED]], -4
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
%shr = ashr <4 x i32> %x, splat (i32 31)
@@ -442,9 +434,8 @@ define i1 @ashr_add_eq_allneg(<4 x i32> %x) {
define i1 @ashr_add_ne_allneg(<4 x i32> %x) {
; CHECK-LABEL: define i1 @ashr_add_ne_allneg(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[X]], splat (i32 31)
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[SHR]])
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[RED]], -4
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
%shr = ashr <4 x i32> %x, splat (i32 31)
@@ -456,8 +447,7 @@ define i1 @ashr_add_ne_allneg(<4 x i32> %x) {
define i1 @ashr_add_sgt_minus1(<4 x i32> %x) {
; CHECK-LABEL: define i1 @ashr_add_sgt_minus1(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[X]], splat (i32 31)
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[SHR]])
+; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[RED]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -470,8 +460,7 @@ define i1 @ashr_add_sgt_minus1(<4 x i32> %x) {
define i1 @ashr_add_slt_0(<4 x i32> %x) {
; CHECK-LABEL: define i1 @ashr_add_slt_0(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[X]], splat (i32 31)
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[SHR]])
+; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[RED]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -484,9 +473,8 @@ define i1 @ashr_add_slt_0(<4 x i32> %x) {
define i1 @ashr_add_slt_minus3(<4 x i32> %x) {
; CHECK-LABEL: define i1 @ashr_add_slt_minus3(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[X]], splat (i32 31)
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[SHR]])
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[RED]], -3
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
%shr = ashr <4 x i32> %x, splat (i32 31)
@@ -498,9 +486,8 @@ define i1 @ashr_add_slt_minus3(<4 x i32> %x) {
define i1 @ashr_add_sgt_minus4(<4 x i32> %x) {
; CHECK-LABEL: define i1 @ashr_add_sgt_minus4(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[X]], splat (i32 31)
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[SHR]])
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[RED]], -4
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
%shr = ashr <4 x i32> %x, splat (i32 31)
@@ -512,9 +499,8 @@ define i1 @ashr_add_sgt_minus4(<4 x i32> %x) {
define i1 @ashr_add_eq_allneg_v8i16(<8 x i16> %x) {
; CHECK-LABEL: define i1 @ashr_add_eq_allneg_v8i16(
; CHECK-SAME: <8 x i16> [[X:%.*]]) {
-; CHECK-NEXT: [[SHR:%.*]] = ashr <8 x i16> [[X]], splat (i16 15)
-; CHECK-NEXT: [[RED:%.*]] = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> [[SHR]])
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[RED]], -8
+; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> [[X]])
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i16 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
%shr = ashr <8 x i16> %x, splat (i16 15)
@@ -753,7 +739,7 @@ define i1 @multi_add_lshr_eq_0(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: define i1 @multi_add_lshr_eq_0(
; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or <4 x i32> [[B]], [[A]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP1]])
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[TMP1]])
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -769,7 +755,7 @@ define i1 @multi_add_lshr_ne_0(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: define i1 @multi_add_lshr_ne_0(
; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or <4 x i32> [[B]], [[A]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP1]])
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[TMP1]])
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -785,7 +771,7 @@ define i1 @multi_add_lshr_eq_8(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: define i1 @multi_add_lshr_eq_8(
; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[B]], [[A]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[TMP1]])
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[TMP1]])
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -801,7 +787,7 @@ define i1 @multi_add_lshr_ne_8(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: define i1 @multi_add_lshr_ne_8(
; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[B]], [[A]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[TMP1]])
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[TMP1]])
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -817,7 +803,7 @@ define i1 @multi_or_lshr_eq_0(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: define i1 @multi_or_lshr_eq_0(
; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or <4 x i32> [[B]], [[A]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP1]])
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[TMP1]])
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -833,7 +819,7 @@ define i1 @multi_and_lshr_eq_1(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: define i1 @multi_and_lshr_eq_1(
; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[B]], [[A]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[TMP1]])
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[TMP1]])
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -850,7 +836,7 @@ define i1 @multi_triple_add_lshr_eq_0(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or <4 x i32> [[C]], [[B]]
; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i32> [[TMP1]], [[A]]
-; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP2]])
+; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[TMP2]])
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -869,7 +855,7 @@ define i1 @multi_triple_add_lshr_eq_12(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[C]], [[B]]
; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i32> [[TMP1]], [[A]]
-; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[TMP2]])
+; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[TMP2]])
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -887,7 +873,7 @@ define i1 @multi_add_ashr_eq_0(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: define i1 @multi_add_ashr_eq_0(
; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or <4 x i32> [[B]], [[A]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP1]])
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[TMP1]])
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -903,7 +889,7 @@ define i1 @multi_add_ashr_eq_minus8(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: define i1 @multi_add_ashr_eq_minus8(
; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[B]], [[A]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[TMP1]])
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[TMP1]])
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -919,7 +905,7 @@ define i1 @multi_add_ashr_sgt_minus1(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: define i1 @multi_add_ashr_sgt_minus1(
; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or <4 x i32> [[B]], [[A]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP1]])
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[TMP1]])
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -935,7 +921,7 @@ define i1 @multi_add_ashr_slt_minus7(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: define i1 @multi_add_ashr_slt_minus7(
; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[B]], [[A]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[TMP1]])
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[TMP1]])
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -951,7 +937,7 @@ define i1 @multi_umax_or_tree_eq_0(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: define i1 @multi_umax_or_tree_eq_0(
; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or <4 x i32> [[B]], [[A]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP1]])
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[TMP1]])
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], -1
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -967,7 +953,7 @@ define i1 @multi_umin_and_tree_eq_1(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: define i1 @multi_umin_and_tree_eq_1(
; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[B]], [[A]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[TMP1]])
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[TMP1]])
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -1070,7 +1056,7 @@ define i1 @negative_multi_op_mismatch(<4 x i32> %a, <4 x i32> %b) {
; CHECK-NEXT: [[SA:%.*]] = lshr <4 x i32> [[A]], splat (i32 31)
; CHECK-NEXT: [[SB:%.*]] = lshr <4 x i32> [[B]], splat (i32 31)
; CHECK-NEXT: [[SUM:%.*]] = add <4 x i32> [[SA]], [[SB]]
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[SUM]])
+; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[SUM]])
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[RED]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
diff --git a/llvm/test/Transforms/VectorCombine/X86/icmp-vector-reduce.ll b/llvm/test/Transforms/VectorCombine/X86/icmp-vector-reduce.ll
index f5b5eea889385..3d8a9e329a791 100644
--- a/llvm/test/Transforms/VectorCombine/X86/icmp-vector-reduce.ll
+++ b/llvm/test/Transforms/VectorCombine/X86/icmp-vector-reduce.ll
@@ -4,7 +4,7 @@
define i1 @or_zext(<4 x i16> %x) {
; CHECK-LABEL: define i1 @or_zext(
; CHECK-SAME: <4 x i16> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -17,7 +17,7 @@ define i1 @or_zext(<4 x i16> %x) {
define i1 @or_zext_i3(<4 x i3> %x) {
; CHECK-LABEL: define i1 @or_zext_i3(
; CHECK-SAME: <4 x i3> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i3 @llvm.vector.reduce.or.v4i3(<4 x i3> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i3 @llvm.vector.reduce.umax.v4i3(<4 x i3> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i3 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -59,7 +59,7 @@ define i1 @or_sext(<4 x i16> %x) {
define i1 @or_neg(<4 x i32> %x) {
; CHECK-LABEL: define i1 @or_neg(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -72,7 +72,7 @@ define i1 @or_neg(<4 x i32> %x) {
define i1 @or_mul(<4 x i32> %x) {
; CHECK-LABEL: define i1 @or_mul(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -85,7 +85,7 @@ define i1 @or_mul(<4 x i32> %x) {
define i1 @or_shl(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: define i1 @or_shl(
; CHECK-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -163,7 +163,7 @@ define i1 @umin_shl(<4 x i32> %x, <4 x i32> %y) {
define i1 @umax_zext(<4 x i16> %x) {
; CHECK-LABEL: define i1 @umax_zext(
; CHECK-SAME: <4 x i16> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -176,7 +176,7 @@ define i1 @umax_zext(<4 x i16> %x) {
define i1 @umax_sext(<4 x i16> %x) {
; CHECK-LABEL: define i1 @umax_sext(
; CHECK-SAME: <4 x i16> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -189,7 +189,7 @@ define i1 @umax_sext(<4 x i16> %x) {
define i1 @umax_neg(<4 x i32> %x) {
; CHECK-LABEL: define i1 @umax_neg(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -202,7 +202,7 @@ define i1 @umax_neg(<4 x i32> %x) {
define i1 @umax_mul(<4 x i32> %x) {
; CHECK-LABEL: define i1 @umax_mul(
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -215,7 +215,7 @@ define i1 @umax_mul(<4 x i32> %x) {
define i1 @umax_shl(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: define i1 @umax_shl(
; CHECK-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -385,7 +385,7 @@ define i1 @add_zext(<4 x i16> %x) {
; CHECK-LABEL: define i1 @add_zext(
; CHECK-SAME: <4 x i16> [[X:%.*]]) {
; CHECK-NEXT: [[AND:%.*]] = and <4 x i16> [[X]], splat (i16 8191)
-; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> [[AND]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> [[AND]])
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -400,7 +400,7 @@ define i1 @add_sext(<4 x i16> %x) {
; CHECK-LABEL: define i1 @add_sext(
; CHECK-SAME: <4 x i16> [[X:%.*]]) {
; CHECK-NEXT: [[AND:%.*]] = and <4 x i16> [[X]], splat (i16 8191)
-; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> [[AND]])
+; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> [[AND]])
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -620,7 +620,7 @@ define void @or_zext_two_blocks(<4 x i16> %x) {
; CHECK-SAME: <4 x i16> [[X:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[A:%.*]] = zext <4 x i16> [[X]] to <4 x i32>
-; CHECK-NEXT: [[TMP0:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[X]])
+; CHECK-NEXT: [[TMP0:%.*]] = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[TMP0]], 0
; CHECK-NEXT: br i1 [[CMP]], label %[[THEN:.*]], label %[[EXIT:.*]]
; CHECK: [[THEN]]:
@@ -648,7 +648,7 @@ define void @or_shl_two_blocks(<4 x i32> %x, <4 x i32> %y) {
; CHECK-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[A:%.*]] = shl nuw <4 x i32> [[X]], [[Y]]
-; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X]])
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[RED]], 0
; CHECK-NEXT: br i1 [[CMP]], label %[[THEN:.*]], label %[[EXIT:.*]]
; CHECK: [[THEN]]:
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