[llvm] [AArch64] Address issue reported in PR#196029 (PR #199122)
Sushant Gokhale via llvm-commits
llvm-commits at lists.llvm.org
Thu May 21 23:17:41 PDT 2026
https://github.com/sushgokh updated https://github.com/llvm/llvm-project/pull/199122
>From d3d9292b4812d4a939e83ca37504d8d44427e91a Mon Sep 17 00:00:00 2001
From: sgokhale <sgokhale at nvidia.com>
Date: Thu, 21 May 2026 14:48:21 -0700
Subject: [PATCH 1/2] [AArch64] Address issue reported in PR#196029
For certain types of truncating stores, the lowering action is set to custom although no custom lowering exists for them.
Add a guard to prevent such false entry.
Addresses issue reported in PR#196029
---
.../lib/Target/AArch64/AArch64ISelLowering.cpp | 18 +++++++++++++-----
.../AArch64/sve-fixed-length-trunc-stores.ll | 13 +++++++++++++
2 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index fddd3f96ba66c..1164701905c5f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1762,11 +1762,19 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
}
// SVE supports truncating stores of 64 and 128-bit vectors
- setTruncStoreAction(MVT::v2i64, MVT::v2i8, Custom);
- setTruncStoreAction(MVT::v2i64, MVT::v2i16, Custom);
- setTruncStoreAction(MVT::v2i64, MVT::v2i32, Custom);
- setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
- setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
+ auto UseSVE = [&](MVT VT) {
+ return useSVEForFixedLengthVectorVT(
+ VT, /*OverrideNEON=*/Subtarget->useSVEForFixedLengthVectors());
+ };
+ if (UseSVE(MVT::v2i64)) {
+ setTruncStoreAction(MVT::v2i64, MVT::v2i8, Custom);
+ setTruncStoreAction(MVT::v2i64, MVT::v2i16, Custom);
+ setTruncStoreAction(MVT::v2i64, MVT::v2i32, Custom);
+ }
+ if (UseSVE(MVT::v2i32)) {
+ setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
+ setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
+ }
for (auto VT : {MVT::nxv2f16, MVT::nxv4f16, MVT::nxv8f16, MVT::nxv2f32,
MVT::nxv4f32, MVT::nxv2f64}) {
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
index f4fc2ff121cd5..2436fd616895b 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
@@ -202,4 +202,17 @@ define void @store_trunc_v32i16i8(ptr %ap, ptr %dest) #0 {
ret void
}
+define void @store_trunc_v4i64i32(ptr %src, ptr %dest) vscale_range(1,0) "target-features"="+neon,+sve" {
+; CHECK-LABEL: store_trunc_v4i64i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q1, q0, [x0]
+; CHECK-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: str q0, [x1]
+; CHECK-NEXT: ret
+ %ld = load <4 x i64>, ptr %src, align 4
+ %trunc = trunc <4 x i64> %ld to <4 x i32>
+ store <4 x i32> %trunc, ptr %dest, align 8
+ ret void
+}
+
attributes #0 = { "target-features"="+sve" }
>From c1df4237d7094ff21d243ca8c4ffc3bcd8f02e97 Mon Sep 17 00:00:00 2001
From: sgokhale <sgokhale at nvidia.com>
Date: Thu, 21 May 2026 23:15:54 -0700
Subject: [PATCH 2/2] Amend previous patch
---
.../Target/AArch64/AArch64ISelLowering.cpp | 22 ++++++++-----------
.../AArch64/sve-fixed-length-trunc-stores.ll | 18 +++++++++++++--
2 files changed, 25 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 1164701905c5f..cc1f0cd5c945e 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1762,19 +1762,15 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
}
// SVE supports truncating stores of 64 and 128-bit vectors
- auto UseSVE = [&](MVT VT) {
- return useSVEForFixedLengthVectorVT(
- VT, /*OverrideNEON=*/Subtarget->useSVEForFixedLengthVectors());
- };
- if (UseSVE(MVT::v2i64)) {
- setTruncStoreAction(MVT::v2i64, MVT::v2i8, Custom);
- setTruncStoreAction(MVT::v2i64, MVT::v2i16, Custom);
- setTruncStoreAction(MVT::v2i64, MVT::v2i32, Custom);
- }
- if (UseSVE(MVT::v2i32)) {
- setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
- setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
- }
+ auto VT = MVT::v2i64;
+ if (useSVEForFixedLengthVectorVT(
+ VT, /*OverrideNEON=*/Subtarget->useSVEForFixedLengthVectors()))
+ setTruncStoreAction(VT, MVT::v2i32, Custom);
+
+ setTruncStoreAction(MVT::v2i64, MVT::v2i8, Custom);
+ setTruncStoreAction(MVT::v2i64, MVT::v2i16, Custom);
+ setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
+ setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
for (auto VT : {MVT::nxv2f16, MVT::nxv4f16, MVT::nxv8f16, MVT::nxv2f32,
MVT::nxv4f32, MVT::nxv2f64}) {
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
index 2436fd616895b..e8a348453e332 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
@@ -202,8 +202,22 @@ define void @store_trunc_v32i16i8(ptr %ap, ptr %dest) #0 {
ret void
}
-define void @store_trunc_v4i64i32(ptr %src, ptr %dest) vscale_range(1,0) "target-features"="+neon,+sve" {
-; CHECK-LABEL: store_trunc_v4i64i32:
+define void @store_trunc_v4i64i32_neon_sve(ptr %src, ptr %dest) vscale_range(1,0) "target-features"="+neon,+sve" {
+; CHECK-LABEL: store_trunc_v4i64i32_neon_sve:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q1, q0, [x0]
+; CHECK-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: str q0, [x1]
+; CHECK-NEXT: ret
+ %ld = load <4 x i64>, ptr %src, align 4
+ %trunc = trunc <4 x i64> %ld to <4 x i32>
+ store <4 x i32> %trunc, ptr %dest, align 8
+ ret void
+}
+
+
+define void @store_trunc_v4i64i32_sve_only(ptr %src, ptr %dest) vscale_range(1,0) #0 {
+; CHECK-LABEL: store_trunc_v4i64i32_sve_only:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q1, q0, [x0]
; CHECK-NEXT: uzp1 v0.4s, v1.4s, v0.4s
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