[llvm] [AMDGPU][True16] Create tests that will demonstrate true16 G_SEXTLOAD/G_ZEXTLOAD legalization changes (PR #198669)
Domenic Nutile via llvm-commits
llvm-commits at lists.llvm.org
Thu May 21 10:54:09 PDT 2026
https://github.com/saxlungs updated https://github.com/llvm/llvm-project/pull/198669
>From bbfe1b51cb5a7481755aa2e4ad755c1ce9e3be61 Mon Sep 17 00:00:00 2001
From: Domenic Nutile <domenic.nutile at gmail.com>
Date: Tue, 19 May 2026 15:20:35 -0400
Subject: [PATCH 1/2] [AMDGPU][True16] Create tests that will demonstrate
true16 G_SEXTLOAD/G_ZEXTLOAD legalization changes
---
.../legalize-sextload-zextload-s16-true16.mir | 376 ++++++++++++++++++
1 file changed, 376 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-zextload-s16-true16.mir
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-zextload-s16-true16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-zextload-s16-true16.mir
new file mode 100644
index 0000000000000..e7aa04ec35783
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-zextload-s16-true16.mir
@@ -0,0 +1,376 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -run-pass=legalizer %s -o - | FileCheck --allow-unused-prefixes --check-prefixes=GFX11,GFX11-TRUE16 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -run-pass=legalizer %s -o - | FileCheck --allow-unused-prefixes --check-prefixes=GFX11,GFX11-FAKE16 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 -run-pass=legalizer %s -o - | FileCheck --allow-unused-prefixes --check-prefixes=GFX12,GFX12-TRUE16 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 -run-pass=legalizer %s -o - | FileCheck --allow-unused-prefixes --check-prefixes=GFX12,GFX12-FAKE16 %s
+#
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -run-pass=legalizer,amdgpu-postlegalizer-combiner,amdgpu-regbankselect,amdgpu-regbanklegalize,amdgpu-regbank-combiner %s -o - | FileCheck --allow-unused-prefixes --check-prefixes=GFX11-TO-COMBINER,GFX11-TO-COMBINER-TRUE16 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -run-pass=legalizer,amdgpu-postlegalizer-combiner,amdgpu-regbankselect,amdgpu-regbanklegalize,amdgpu-regbank-combiner %s -o - | FileCheck --allow-unused-prefixes --check-prefixes=GFX11-TO-COMBINER,GFX11-TO-COMBINER-FAKE16 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 -run-pass=legalizer,amdgpu-postlegalizer-combiner,amdgpu-regbankselect,amdgpu-regbanklegalize,amdgpu-regbank-combiner %s -o - | FileCheck --allow-unused-prefixes --check-prefixes=GFX12-TO-COMBINER,GFX12-TO-COMBINER-TRUE16 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 -run-pass=legalizer,amdgpu-postlegalizer-combiner,amdgpu-regbankselect,amdgpu-regbanklegalize,amdgpu-regbank-combiner %s -o - | FileCheck --allow-unused-prefixes --check-prefixes=GFX12-TO-COMBINER,GFX12-TO-COMBINER-FAKE16 %s
+
+---
+name: test_sextload_global_s16_from_s8
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2
+
+ ; GFX11-LABEL: name: test_sextload_global_s16_from_s8
+ ; GFX11: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
+ ; GFX11-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
+ ; GFX11-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
+ ; GFX11-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; GFX11-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXTLOAD]], [[C1]]
+ ; GFX11-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
+ ; GFX11-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
+ ; GFX11-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
+ ; GFX11-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ;
+ ; GFX12-LABEL: name: test_sextload_global_s16_from_s8
+ ; GFX12: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
+ ; GFX12-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
+ ; GFX12-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
+ ; GFX12-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; GFX12-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXTLOAD]], [[C1]]
+ ; GFX12-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
+ ; GFX12-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
+ ; GFX12-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
+ ; GFX12-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; GFX12-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ;
+ ; GFX11-TO-COMBINER-LABEL: name: test_sextload_global_s16_from_s8
+ ; GFX11-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX11-TO-COMBINER-NEXT: {{ $}}
+ ; GFX11-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX11-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
+ ; GFX11-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_I8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_I8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 1)
+ ; GFX11-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_I8_]](<2 x s16>)
+ ;
+ ; GFX12-TO-COMBINER-LABEL: name: test_sextload_global_s16_from_s8
+ ; GFX12-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX12-TO-COMBINER-NEXT: {{ $}}
+ ; GFX12-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX12-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
+ ; GFX12-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_I8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_I8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 1)
+ ; GFX12-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_I8_]](<2 x s16>)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(<2 x s16>) = COPY $vgpr2
+ %2:_(s16) = G_SEXTLOAD %0 :: (load (s8), addrspace 1)
+ %3:_(s32) = G_CONSTANT i32 0
+ %4:_(<2 x s16>) = G_INSERT_VECTOR_ELT %1:_, %2:_(s16), %3:_(s32)
+ $vgpr0 = COPY %4
+...
+
+---
+name: test_sextload_local_s16_from_s8
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2
+
+ ; GFX11-LABEL: name: test_sextload_local_s16_from_s8
+ ; GFX11: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
+ ; GFX11-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 3)
+ ; GFX11-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
+ ; GFX11-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; GFX11-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXTLOAD]], [[C1]]
+ ; GFX11-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
+ ; GFX11-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
+ ; GFX11-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
+ ; GFX11-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ;
+ ; GFX12-LABEL: name: test_sextload_local_s16_from_s8
+ ; GFX12: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
+ ; GFX12-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 3)
+ ; GFX12-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
+ ; GFX12-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; GFX12-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXTLOAD]], [[C1]]
+ ; GFX12-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
+ ; GFX12-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
+ ; GFX12-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
+ ; GFX12-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; GFX12-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ;
+ ; GFX11-TO-COMBINER-LABEL: name: test_sextload_local_s16_from_s8
+ ; GFX11-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX11-TO-COMBINER-NEXT: {{ $}}
+ ; GFX11-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX11-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
+ ; GFX11-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_I8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_I8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 3)
+ ; GFX11-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_I8_]](<2 x s16>)
+ ;
+ ; GFX12-TO-COMBINER-LABEL: name: test_sextload_local_s16_from_s8
+ ; GFX12-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX12-TO-COMBINER-NEXT: {{ $}}
+ ; GFX12-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX12-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
+ ; GFX12-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_I8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_I8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 3)
+ ; GFX12-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_I8_]](<2 x s16>)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(<2 x s16>) = COPY $vgpr2
+ %2:_(s16) = G_SEXTLOAD %0 :: (load (s8), addrspace 3)
+ %3:_(s32) = G_CONSTANT i32 0
+ %4:_(<2 x s16>) = G_INSERT_VECTOR_ELT %1:_, %2:_(s16), %3:_(s32)
+ $vgpr0 = COPY %4
+...
+
+---
+name: test_sextload_private_s16_from_s8
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2
+
+ ; GFX11-LABEL: name: test_sextload_private_s16_from_s8
+ ; GFX11: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
+ ; GFX11-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 5)
+ ; GFX11-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
+ ; GFX11-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; GFX11-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXTLOAD]], [[C1]]
+ ; GFX11-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
+ ; GFX11-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
+ ; GFX11-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
+ ; GFX11-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ;
+ ; GFX12-LABEL: name: test_sextload_private_s16_from_s8
+ ; GFX12: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
+ ; GFX12-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 5)
+ ; GFX12-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
+ ; GFX12-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; GFX12-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXTLOAD]], [[C1]]
+ ; GFX12-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
+ ; GFX12-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
+ ; GFX12-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
+ ; GFX12-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; GFX12-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ;
+ ; GFX11-TO-COMBINER-LABEL: name: test_sextload_private_s16_from_s8
+ ; GFX11-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX11-TO-COMBINER-NEXT: {{ $}}
+ ; GFX11-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX11-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
+ ; GFX11-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_I8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_I8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 5)
+ ; GFX11-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_I8_]](<2 x s16>)
+ ;
+ ; GFX12-TO-COMBINER-LABEL: name: test_sextload_private_s16_from_s8
+ ; GFX12-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX12-TO-COMBINER-NEXT: {{ $}}
+ ; GFX12-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX12-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
+ ; GFX12-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_I8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_I8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 5)
+ ; GFX12-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_I8_]](<2 x s16>)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(<2 x s16>) = COPY $vgpr2
+ %2:_(s16) = G_SEXTLOAD %0 :: (load (s8), addrspace 5)
+ %3:_(s32) = G_CONSTANT i32 0
+ %4:_(<2 x s16>) = G_INSERT_VECTOR_ELT %1:_, %2:_(s16), %3:_(s32)
+ $vgpr0 = COPY %4
+...
+
+---
+name: test_zextload_global_s16_from_s8
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2
+
+ ; GFX11-LABEL: name: test_zextload_global_s16_from_s8
+ ; GFX11: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
+ ; GFX11-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
+ ; GFX11-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
+ ; GFX11-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD]], [[C]](s32)
+ ; GFX11-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
+ ; GFX11-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; GFX11-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ;
+ ; GFX12-LABEL: name: test_zextload_global_s16_from_s8
+ ; GFX12: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
+ ; GFX12-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
+ ; GFX12-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
+ ; GFX12-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD]], [[C]](s32)
+ ; GFX12-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
+ ; GFX12-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; GFX12-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; GFX12-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ;
+ ; GFX11-TO-COMBINER-LABEL: name: test_zextload_global_s16_from_s8
+ ; GFX11-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX11-TO-COMBINER-NEXT: {{ $}}
+ ; GFX11-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX11-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
+ ; GFX11-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_U8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_U8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 1)
+ ; GFX11-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_U8_]](<2 x s16>)
+ ;
+ ; GFX12-TO-COMBINER-LABEL: name: test_zextload_global_s16_from_s8
+ ; GFX12-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX12-TO-COMBINER-NEXT: {{ $}}
+ ; GFX12-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX12-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
+ ; GFX12-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_U8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_U8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 1)
+ ; GFX12-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_U8_]](<2 x s16>)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(<2 x s16>) = COPY $vgpr2
+ %2:_(s16) = G_ZEXTLOAD %0 :: (load (s8), addrspace 1)
+ %3:_(s32) = G_CONSTANT i32 0
+ %4:_(<2 x s16>) = G_INSERT_VECTOR_ELT %1:_, %2:_(s16), %3:_(s32)
+ $vgpr0 = COPY %4
+...
+
+---
+name: test_zextload_local_s16_from_s8
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2
+
+ ; GFX11-LABEL: name: test_zextload_local_s16_from_s8
+ ; GFX11: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
+ ; GFX11-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 3)
+ ; GFX11-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
+ ; GFX11-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD]], [[C]](s32)
+ ; GFX11-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
+ ; GFX11-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; GFX11-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ;
+ ; GFX12-LABEL: name: test_zextload_local_s16_from_s8
+ ; GFX12: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
+ ; GFX12-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 3)
+ ; GFX12-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
+ ; GFX12-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD]], [[C]](s32)
+ ; GFX12-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
+ ; GFX12-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; GFX12-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; GFX12-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ;
+ ; GFX11-TO-COMBINER-LABEL: name: test_zextload_local_s16_from_s8
+ ; GFX11-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX11-TO-COMBINER-NEXT: {{ $}}
+ ; GFX11-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX11-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
+ ; GFX11-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_U8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_U8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 3)
+ ; GFX11-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_U8_]](<2 x s16>)
+ ;
+ ; GFX12-TO-COMBINER-LABEL: name: test_zextload_local_s16_from_s8
+ ; GFX12-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX12-TO-COMBINER-NEXT: {{ $}}
+ ; GFX12-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX12-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
+ ; GFX12-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_U8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_U8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 3)
+ ; GFX12-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_U8_]](<2 x s16>)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(<2 x s16>) = COPY $vgpr2
+ %2:_(s16) = G_ZEXTLOAD %0 :: (load (s8), addrspace 3)
+ %3:_(s32) = G_CONSTANT i32 0
+ %4:_(<2 x s16>) = G_INSERT_VECTOR_ELT %1:_, %2:_(s16), %3:_(s32)
+ $vgpr0 = COPY %4
+...
+
+---
+name: test_zextload_private_s16_from_s8
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2
+
+ ; GFX11-LABEL: name: test_zextload_private_s16_from_s8
+ ; GFX11: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
+ ; GFX11-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 5)
+ ; GFX11-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
+ ; GFX11-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD]], [[C]](s32)
+ ; GFX11-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
+ ; GFX11-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; GFX11-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ;
+ ; GFX12-LABEL: name: test_zextload_private_s16_from_s8
+ ; GFX12: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
+ ; GFX12-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 5)
+ ; GFX12-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
+ ; GFX12-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD]], [[C]](s32)
+ ; GFX12-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
+ ; GFX12-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; GFX12-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+ ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; GFX12-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ;
+ ; GFX11-TO-COMBINER-LABEL: name: test_zextload_private_s16_from_s8
+ ; GFX11-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX11-TO-COMBINER-NEXT: {{ $}}
+ ; GFX11-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX11-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
+ ; GFX11-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_U8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_U8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 5)
+ ; GFX11-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_U8_]](<2 x s16>)
+ ;
+ ; GFX12-TO-COMBINER-LABEL: name: test_zextload_private_s16_from_s8
+ ; GFX12-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX12-TO-COMBINER-NEXT: {{ $}}
+ ; GFX12-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX12-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
+ ; GFX12-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_U8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_U8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 5)
+ ; GFX12-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_U8_]](<2 x s16>)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(<2 x s16>) = COPY $vgpr2
+ %2:_(s16) = G_ZEXTLOAD %0 :: (load (s8), addrspace 5)
+ %3:_(s32) = G_CONSTANT i32 0
+ %4:_(<2 x s16>) = G_INSERT_VECTOR_ELT %1:_, %2:_(s16), %3:_(s32)
+ $vgpr0 = COPY %4
+...
>From 3260fd78c766cdf5287f768b2d330f7a2f3dca26 Mon Sep 17 00:00:00 2001
From: Domenic Nutile <domenic.nutile at gmail.com>
Date: Wed, 20 May 2026 13:26:17 -0400
Subject: [PATCH 2/2] PR feedback
---
.../legalize-sextload-s16-true16.mir | 87 ++++
.../legalize-sextload-zextload-s16-true16.mir | 376 ------------------
.../CodeGen/AMDGPU/GlobalISel/load-d16.ll | 6 +-
3 files changed, 92 insertions(+), 377 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-s16-true16.mir
delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-zextload-s16-true16.mir
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-s16-true16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-s16-true16.mir
new file mode 100644
index 0000000000000..99f4418e7a978
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-s16-true16.mir
@@ -0,0 +1,87 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 -run-pass=legalizer %s -o - | FileCheck --check-prefixes=TRUE16 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 -run-pass=legalizer %s -o - | FileCheck --check-prefixes=FAKE16 %s
+
+---
+name: test_sextload_global_s16_from_s8
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2
+
+ ; TRUE16-LABEL: name: test_sextload_global_s16_from_s8
+ ; TRUE16: liveins: $vgpr0_vgpr1, $vgpr2
+ ; TRUE16-NEXT: {{ $}}
+ ; TRUE16-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; TRUE16-NEXT: [[COPY1:%[0-9]+]]:_(p5) = COPY $vgpr2
+ ; TRUE16-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY1]](p5) :: (load (s8), addrspace 5)
+ ; TRUE16-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXTLOAD]](s32)
+ ; TRUE16-NEXT: G_STORE [[TRUNC]](s16), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ;
+ ; FAKE16-LABEL: name: test_sextload_global_s16_from_s8
+ ; FAKE16: liveins: $vgpr0_vgpr1, $vgpr2
+ ; FAKE16-NEXT: {{ $}}
+ ; FAKE16-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; FAKE16-NEXT: [[COPY1:%[0-9]+]]:_(p5) = COPY $vgpr2
+ ; FAKE16-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY1]](p5) :: (load (s8), addrspace 5)
+ ; FAKE16-NEXT: G_STORE [[SEXTLOAD]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(p5) = COPY $vgpr2
+ %2:_(s16) = G_SEXTLOAD %1 :: (load (s8), addrspace 5)
+ G_STORE %2(s16), %0(p1) :: (store (s16), addrspace 1)
+...
+
+---
+name: test_sextload_local_s16_from_s8
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; TRUE16-LABEL: name: test_sextload_local_s16_from_s8
+ ; TRUE16: liveins: $vgpr0, $vgpr1
+ ; TRUE16-NEXT: {{ $}}
+ ; TRUE16-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; TRUE16-NEXT: [[COPY1:%[0-9]+]]:_(p5) = COPY $vgpr1
+ ; TRUE16-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY1]](p5) :: (load (s8), addrspace 5)
+ ; TRUE16-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXTLOAD]](s32)
+ ; TRUE16-NEXT: G_STORE [[TRUNC]](s16), [[COPY]](p3) :: (store (s16), addrspace 3)
+ ;
+ ; FAKE16-LABEL: name: test_sextload_local_s16_from_s8
+ ; FAKE16: liveins: $vgpr0, $vgpr1
+ ; FAKE16-NEXT: {{ $}}
+ ; FAKE16-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; FAKE16-NEXT: [[COPY1:%[0-9]+]]:_(p5) = COPY $vgpr1
+ ; FAKE16-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY1]](p5) :: (load (s8), addrspace 5)
+ ; FAKE16-NEXT: G_STORE [[SEXTLOAD]](s32), [[COPY]](p3) :: (store (s16), addrspace 3)
+ %0:_(p3) = COPY $vgpr0
+ %1:_(p5) = COPY $vgpr1
+ %2:_(s16) = G_SEXTLOAD %1 :: (load (s8), addrspace 5)
+ G_STORE %2(s16), %0(p3) :: (store (s16), addrspace 3)
+...
+
+---
+name: test_sextload_private_s16_from_s8
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; TRUE16-LABEL: name: test_sextload_private_s16_from_s8
+ ; TRUE16: liveins: $vgpr0, $vgpr1
+ ; TRUE16-NEXT: {{ $}}
+ ; TRUE16-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
+ ; TRUE16-NEXT: [[COPY1:%[0-9]+]]:_(p5) = COPY $vgpr1
+ ; TRUE16-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY1]](p5) :: (load (s8), addrspace 5)
+ ; TRUE16-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXTLOAD]](s32)
+ ; TRUE16-NEXT: G_STORE [[TRUNC]](s16), [[COPY]](p5) :: (store (s16), addrspace 5)
+ ;
+ ; FAKE16-LABEL: name: test_sextload_private_s16_from_s8
+ ; FAKE16: liveins: $vgpr0, $vgpr1
+ ; FAKE16-NEXT: {{ $}}
+ ; FAKE16-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
+ ; FAKE16-NEXT: [[COPY1:%[0-9]+]]:_(p5) = COPY $vgpr1
+ ; FAKE16-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY1]](p5) :: (load (s8), addrspace 5)
+ ; FAKE16-NEXT: G_STORE [[SEXTLOAD]](s32), [[COPY]](p5) :: (store (s16), addrspace 5)
+ %0:_(p5) = COPY $vgpr0
+ %1:_(p5) = COPY $vgpr1
+ %2:_(s16) = G_SEXTLOAD %1 :: (load (s8), addrspace 5)
+ G_STORE %2(s16), %0(p5) :: (store (s16), addrspace 5)
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-zextload-s16-true16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-zextload-s16-true16.mir
deleted file mode 100644
index e7aa04ec35783..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-zextload-s16-true16.mir
+++ /dev/null
@@ -1,376 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -run-pass=legalizer %s -o - | FileCheck --allow-unused-prefixes --check-prefixes=GFX11,GFX11-TRUE16 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -run-pass=legalizer %s -o - | FileCheck --allow-unused-prefixes --check-prefixes=GFX11,GFX11-FAKE16 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 -run-pass=legalizer %s -o - | FileCheck --allow-unused-prefixes --check-prefixes=GFX12,GFX12-TRUE16 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 -run-pass=legalizer %s -o - | FileCheck --allow-unused-prefixes --check-prefixes=GFX12,GFX12-FAKE16 %s
-#
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -run-pass=legalizer,amdgpu-postlegalizer-combiner,amdgpu-regbankselect,amdgpu-regbanklegalize,amdgpu-regbank-combiner %s -o - | FileCheck --allow-unused-prefixes --check-prefixes=GFX11-TO-COMBINER,GFX11-TO-COMBINER-TRUE16 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -run-pass=legalizer,amdgpu-postlegalizer-combiner,amdgpu-regbankselect,amdgpu-regbanklegalize,amdgpu-regbank-combiner %s -o - | FileCheck --allow-unused-prefixes --check-prefixes=GFX11-TO-COMBINER,GFX11-TO-COMBINER-FAKE16 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 -run-pass=legalizer,amdgpu-postlegalizer-combiner,amdgpu-regbankselect,amdgpu-regbanklegalize,amdgpu-regbank-combiner %s -o - | FileCheck --allow-unused-prefixes --check-prefixes=GFX12-TO-COMBINER,GFX12-TO-COMBINER-TRUE16 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 -run-pass=legalizer,amdgpu-postlegalizer-combiner,amdgpu-regbankselect,amdgpu-regbanklegalize,amdgpu-regbank-combiner %s -o - | FileCheck --allow-unused-prefixes --check-prefixes=GFX12-TO-COMBINER,GFX12-TO-COMBINER-FAKE16 %s
-
----
-name: test_sextload_global_s16_from_s8
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1, $vgpr2
-
- ; GFX11-LABEL: name: test_sextload_global_s16_from_s8
- ; GFX11: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX11-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
- ; GFX11-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX11-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX11-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXTLOAD]], [[C1]]
- ; GFX11-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
- ; GFX11-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
- ; GFX11-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
- ; GFX11-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
- ; GFX12-LABEL: name: test_sextload_global_s16_from_s8
- ; GFX12: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX12-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
- ; GFX12-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX12-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX12-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXTLOAD]], [[C1]]
- ; GFX12-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
- ; GFX12-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
- ; GFX12-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
- ; GFX12-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX12-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
- ; GFX11-TO-COMBINER-LABEL: name: test_sextload_global_s16_from_s8
- ; GFX11-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX11-TO-COMBINER-NEXT: {{ $}}
- ; GFX11-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX11-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
- ; GFX11-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_I8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_I8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 1)
- ; GFX11-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_I8_]](<2 x s16>)
- ;
- ; GFX12-TO-COMBINER-LABEL: name: test_sextload_global_s16_from_s8
- ; GFX12-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX12-TO-COMBINER-NEXT: {{ $}}
- ; GFX12-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX12-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
- ; GFX12-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_I8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_I8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 1)
- ; GFX12-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_I8_]](<2 x s16>)
- %0:_(p1) = COPY $vgpr0_vgpr1
- %1:_(<2 x s16>) = COPY $vgpr2
- %2:_(s16) = G_SEXTLOAD %0 :: (load (s8), addrspace 1)
- %3:_(s32) = G_CONSTANT i32 0
- %4:_(<2 x s16>) = G_INSERT_VECTOR_ELT %1:_, %2:_(s16), %3:_(s32)
- $vgpr0 = COPY %4
-...
-
----
-name: test_sextload_local_s16_from_s8
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1, $vgpr2
-
- ; GFX11-LABEL: name: test_sextload_local_s16_from_s8
- ; GFX11: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX11-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 3)
- ; GFX11-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX11-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX11-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXTLOAD]], [[C1]]
- ; GFX11-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
- ; GFX11-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
- ; GFX11-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
- ; GFX11-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
- ; GFX12-LABEL: name: test_sextload_local_s16_from_s8
- ; GFX12: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX12-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 3)
- ; GFX12-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX12-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX12-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXTLOAD]], [[C1]]
- ; GFX12-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
- ; GFX12-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
- ; GFX12-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
- ; GFX12-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX12-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
- ; GFX11-TO-COMBINER-LABEL: name: test_sextload_local_s16_from_s8
- ; GFX11-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX11-TO-COMBINER-NEXT: {{ $}}
- ; GFX11-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX11-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
- ; GFX11-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_I8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_I8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 3)
- ; GFX11-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_I8_]](<2 x s16>)
- ;
- ; GFX12-TO-COMBINER-LABEL: name: test_sextload_local_s16_from_s8
- ; GFX12-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX12-TO-COMBINER-NEXT: {{ $}}
- ; GFX12-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX12-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
- ; GFX12-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_I8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_I8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 3)
- ; GFX12-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_I8_]](<2 x s16>)
- %0:_(p1) = COPY $vgpr0_vgpr1
- %1:_(<2 x s16>) = COPY $vgpr2
- %2:_(s16) = G_SEXTLOAD %0 :: (load (s8), addrspace 3)
- %3:_(s32) = G_CONSTANT i32 0
- %4:_(<2 x s16>) = G_INSERT_VECTOR_ELT %1:_, %2:_(s16), %3:_(s32)
- $vgpr0 = COPY %4
-...
-
----
-name: test_sextload_private_s16_from_s8
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1, $vgpr2
-
- ; GFX11-LABEL: name: test_sextload_private_s16_from_s8
- ; GFX11: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX11-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 5)
- ; GFX11-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX11-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX11-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXTLOAD]], [[C1]]
- ; GFX11-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
- ; GFX11-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
- ; GFX11-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
- ; GFX11-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
- ; GFX12-LABEL: name: test_sextload_private_s16_from_s8
- ; GFX12: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX12-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 5)
- ; GFX12-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX12-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX12-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXTLOAD]], [[C1]]
- ; GFX12-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
- ; GFX12-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
- ; GFX12-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
- ; GFX12-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX12-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
- ; GFX11-TO-COMBINER-LABEL: name: test_sextload_private_s16_from_s8
- ; GFX11-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX11-TO-COMBINER-NEXT: {{ $}}
- ; GFX11-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX11-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
- ; GFX11-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_I8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_I8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 5)
- ; GFX11-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_I8_]](<2 x s16>)
- ;
- ; GFX12-TO-COMBINER-LABEL: name: test_sextload_private_s16_from_s8
- ; GFX12-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX12-TO-COMBINER-NEXT: {{ $}}
- ; GFX12-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX12-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
- ; GFX12-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_I8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_I8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 5)
- ; GFX12-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_I8_]](<2 x s16>)
- %0:_(p1) = COPY $vgpr0_vgpr1
- %1:_(<2 x s16>) = COPY $vgpr2
- %2:_(s16) = G_SEXTLOAD %0 :: (load (s8), addrspace 5)
- %3:_(s32) = G_CONSTANT i32 0
- %4:_(<2 x s16>) = G_INSERT_VECTOR_ELT %1:_, %2:_(s16), %3:_(s32)
- $vgpr0 = COPY %4
-...
-
----
-name: test_zextload_global_s16_from_s8
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1, $vgpr2
-
- ; GFX11-LABEL: name: test_zextload_global_s16_from_s8
- ; GFX11: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX11-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
- ; GFX11-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX11-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD]], [[C]](s32)
- ; GFX11-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
- ; GFX11-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; GFX11-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
- ; GFX12-LABEL: name: test_zextload_global_s16_from_s8
- ; GFX12: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX12-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
- ; GFX12-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX12-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD]], [[C]](s32)
- ; GFX12-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
- ; GFX12-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; GFX12-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX12-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
- ; GFX11-TO-COMBINER-LABEL: name: test_zextload_global_s16_from_s8
- ; GFX11-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX11-TO-COMBINER-NEXT: {{ $}}
- ; GFX11-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX11-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
- ; GFX11-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_U8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_U8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 1)
- ; GFX11-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_U8_]](<2 x s16>)
- ;
- ; GFX12-TO-COMBINER-LABEL: name: test_zextload_global_s16_from_s8
- ; GFX12-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX12-TO-COMBINER-NEXT: {{ $}}
- ; GFX12-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX12-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
- ; GFX12-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_U8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_U8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 1)
- ; GFX12-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_U8_]](<2 x s16>)
- %0:_(p1) = COPY $vgpr0_vgpr1
- %1:_(<2 x s16>) = COPY $vgpr2
- %2:_(s16) = G_ZEXTLOAD %0 :: (load (s8), addrspace 1)
- %3:_(s32) = G_CONSTANT i32 0
- %4:_(<2 x s16>) = G_INSERT_VECTOR_ELT %1:_, %2:_(s16), %3:_(s32)
- $vgpr0 = COPY %4
-...
-
----
-name: test_zextload_local_s16_from_s8
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1, $vgpr2
-
- ; GFX11-LABEL: name: test_zextload_local_s16_from_s8
- ; GFX11: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX11-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 3)
- ; GFX11-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX11-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD]], [[C]](s32)
- ; GFX11-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
- ; GFX11-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; GFX11-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
- ; GFX12-LABEL: name: test_zextload_local_s16_from_s8
- ; GFX12: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX12-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 3)
- ; GFX12-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX12-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD]], [[C]](s32)
- ; GFX12-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
- ; GFX12-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; GFX12-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX12-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
- ; GFX11-TO-COMBINER-LABEL: name: test_zextload_local_s16_from_s8
- ; GFX11-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX11-TO-COMBINER-NEXT: {{ $}}
- ; GFX11-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX11-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
- ; GFX11-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_U8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_U8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 3)
- ; GFX11-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_U8_]](<2 x s16>)
- ;
- ; GFX12-TO-COMBINER-LABEL: name: test_zextload_local_s16_from_s8
- ; GFX12-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX12-TO-COMBINER-NEXT: {{ $}}
- ; GFX12-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX12-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
- ; GFX12-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_U8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_U8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 3)
- ; GFX12-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_U8_]](<2 x s16>)
- %0:_(p1) = COPY $vgpr0_vgpr1
- %1:_(<2 x s16>) = COPY $vgpr2
- %2:_(s16) = G_ZEXTLOAD %0 :: (load (s8), addrspace 3)
- %3:_(s32) = G_CONSTANT i32 0
- %4:_(<2 x s16>) = G_INSERT_VECTOR_ELT %1:_, %2:_(s16), %3:_(s32)
- $vgpr0 = COPY %4
-...
-
----
-name: test_zextload_private_s16_from_s8
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1, $vgpr2
-
- ; GFX11-LABEL: name: test_zextload_private_s16_from_s8
- ; GFX11: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX11-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 5)
- ; GFX11-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX11-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD]], [[C]](s32)
- ; GFX11-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
- ; GFX11-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; GFX11-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
- ; GFX12-LABEL: name: test_zextload_private_s16_from_s8
- ; GFX12: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX12-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 5)
- ; GFX12-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX12-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD]], [[C]](s32)
- ; GFX12-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
- ; GFX12-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; GFX12-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX12-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
- ; GFX11-TO-COMBINER-LABEL: name: test_zextload_private_s16_from_s8
- ; GFX11-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX11-TO-COMBINER-NEXT: {{ $}}
- ; GFX11-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX11-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
- ; GFX11-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_U8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_U8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 5)
- ; GFX11-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_U8_]](<2 x s16>)
- ;
- ; GFX12-TO-COMBINER-LABEL: name: test_zextload_private_s16_from_s8
- ; GFX12-TO-COMBINER: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX12-TO-COMBINER-NEXT: {{ $}}
- ; GFX12-TO-COMBINER-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX12-TO-COMBINER-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2
- ; GFX12-TO-COMBINER-NEXT: [[AMDGPU_LOAD_D16_LO_U8_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_LOAD_D16_LO_U8 [[COPY]](p1), [[COPY1]] :: (load (s8), addrspace 5)
- ; GFX12-TO-COMBINER-NEXT: $vgpr0 = COPY [[AMDGPU_LOAD_D16_LO_U8_]](<2 x s16>)
- %0:_(p1) = COPY $vgpr0_vgpr1
- %1:_(<2 x s16>) = COPY $vgpr2
- %2:_(s16) = G_ZEXTLOAD %0 :: (load (s8), addrspace 5)
- %3:_(s32) = G_CONSTANT i32 0
- %4:_(<2 x s16>) = G_INSERT_VECTOR_ELT %1:_, %2:_(s16), %3:_(s32)
- $vgpr0 = COPY %4
-...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-d16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-d16.ll
index 5d5b752b27a3c..166f439a61430 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-d16.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GFX12 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck --check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX12,GFX12-FAKE16 %s
define amdgpu_ps void @load_P0_B16_D16(<2 x i16> %vec, ptr addrspace(0) %ptra, ptr addrspace(0) %out) {
; GFX12-LABEL: load_P0_B16_D16:
@@ -410,3 +411,6 @@ define amdgpu_ps void @zextload_P5_i8_D16_Hi(<2 x i16> %vec, ptr addrspace(5) %p
store <2 x i16> %res, ptr addrspace(5) %out
ret void
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX12-FAKE16: {{.*}}
+; GFX12-TRUE16: {{.*}}
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