[clang] [llvm] [AMDGPU] Use 1-iteration Newton-Raphson refinement for FP32 reciprocal. (PR #194716)

[Jay Foad via llvm-commits]

jayfoad wrote:

> > That's right: +-0 and +-inf is still handled by full division.
> 
> v_rcp itself handles these cases correctly. Only the NR fixup messes them up. So how about a structure like:
> 
> ```
> y = rcp(x);
> if (x not 0 or inf) {
>   do the NR fixup
> }
> ```
> 
> This avoids having the complete 12-instruction fdiv expansion bloating the code.

Actually you can use `v_div_fixup_f32` to handle the 0 and inf cases, just as it was intended:
```
y = rcp(x);
do the NR fixup
y = div_fixup(y, x, 1.0);
```

https://github.com/llvm/llvm-project/pull/194716