[llvm] [AArch64][GlobalIsel] Simplify and nest csel operands in AArch64 GlobalIsel (PR #198608)
via llvm-commits
llvm-commits at lists.llvm.org
Tue May 19 11:56:29 PDT 2026
https://github.com/LumioseSil created https://github.com/llvm/llvm-project/pull/198608
None
>From da537bb9bbee4de2f0af8d1b9e27914544cf7c29 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Tue, 19 May 2026 14:50:23 -0400
Subject: [PATCH] Simplify and nest csel operands in AArch64 GlobalIsel
---
.../GISel/AArch64InstructionSelector.cpp | 14 +-
.../AArch64/GlobalISel/fold-fp-select.mir | 20 +--
.../AArch64/GlobalISel/select-static.mir | 153 +++++++++---------
.../CodeGen/AArch64/GlobalISel/select.mir | 5 +-
.../test/CodeGen/AArch64/bf16-instructions.ll | 12 +-
llvm/test/CodeGen/AArch64/f16-instructions.ll | 46 ++----
llvm/test/CodeGen/AArch64/fast-isel-select.ll | 9 +-
.../half-precision-signof-no-assert.ll | 3 +-
.../CodeGen/AArch64/strict-fp-int-promote.ll | 12 +-
9 files changed, 124 insertions(+), 150 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index cf650fd5c4e72..364f433f4e9b8 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -4490,15 +4490,13 @@ MachineInstr *AArch64InstructionSelector::emitCSetForFCmp(
if (CC2 == AArch64CC::AL)
return emitCSINC(/*Dst=*/Dst, /*Src1=*/ZReg, /*Src2=*/ZReg, InvCC1,
MIRBuilder);
+
+ // Match SelectionDAG: cset(CC1) then csinc Dst, Tmp, wzr, inv(CC2).
const TargetRegisterClass *RC = &AArch64::GPR32RegClass;
- Register Def1Reg = MRI.createVirtualRegister(RC);
- Register Def2Reg = MRI.createVirtualRegister(RC);
- auto InvCC2 = AArch64CC::getInvertedCondCode(CC2);
- emitCSINC(/*Dst=*/Def1Reg, /*Src1=*/ZReg, /*Src2=*/ZReg, InvCC1, MIRBuilder);
- emitCSINC(/*Dst=*/Def2Reg, /*Src1=*/ZReg, /*Src2=*/ZReg, InvCC2, MIRBuilder);
- auto OrMI = MIRBuilder.buildInstr(AArch64::ORRWrr, {Dst}, {Def1Reg, Def2Reg});
- constrainSelectedInstRegOperands(*OrMI, TII, TRI, RBI);
- return &*OrMI;
+ Register TmpReg = MRI.createVirtualRegister(RC);
+ emitCSINC(/*Dst=*/TmpReg, /*Src1=*/ZReg, /*Src2=*/ZReg, InvCC1, MIRBuilder);
+ return emitCSINC(/*Dst=*/Dst, /*Src1=*/TmpReg, /*Src2=*/ZReg,
+ AArch64CC::getInvertedCondCode(CC2), MIRBuilder);
}
MachineInstr *AArch64InstructionSelector::emitFPCompare(
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
index 15d67c3d1668b..be32186d6f1ac 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
@@ -156,9 +156,8 @@ body: |
; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv, implicit $fpcr
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
- ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
- ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
- ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[ORRWrr]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr [[CSINCWr]], $wzr, 7, implicit $nzcv
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[CSINCWr1]], 0, implicit-def $nzcv
; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
@@ -189,9 +188,8 @@ body: |
; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv, implicit $fpcr
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
- ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
- ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
- ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[ORRWrr]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr [[CSINCWr]], $wzr, 13, implicit $nzcv
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[CSINCWr1]], 0, implicit-def $nzcv
; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
@@ -280,9 +278,8 @@ body: |
; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
; CHECK-NEXT: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv, implicit $fpcr
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
- ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
- ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
- ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[ORRWrr]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr [[CSINCWr]], $wzr, 7, implicit $nzcv
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[CSINCWr1]], 0, implicit-def $nzcv
; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 1, implicit $nzcv
; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
@@ -313,9 +310,8 @@ body: |
; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
; CHECK-NEXT: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv, implicit $fpcr
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
- ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
- ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
- ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[ORRWrr]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr [[CSINCWr]], $wzr, 13, implicit $nzcv
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[CSINCWr1]], 0, implicit-def $nzcv
; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv
; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
index df13c02374fed..305a5d2d98601 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
@@ -1,4 +1,5 @@
-# RUN: llc -O0 -mtriple=aarch64 -run-pass=instruction-select -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,LINUX-DEFAULT
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=aarch64 -run-pass=instruction-select -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
@@ -25,23 +26,21 @@
...
---
-# CHECK-LABEL: name: frame_index
name: frame_index
legalized: true
regBankSelected: true
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr }
stack:
- { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
-# CHECK: body:
-# CHECK: %0:gpr64sp = ADDXri %stack.0.ptr0, 0, 0
body: |
bb.0:
+ ; CHECK-LABEL: name: frame_index
+ ; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri %stack.0.ptr0, 0, 0
+ ; CHECK-NEXT: $x0 = COPY [[ADDXri]]
%0(p0) = G_FRAME_INDEX %stack.0.ptr0
$x0 = COPY %0(p0)
...
@@ -49,16 +48,19 @@ body: |
---
---
-# CHECK-LABEL: name: ptr_mask
name: ptr_mask
legalized: true
regBankSelected: true
-# CHECK: body:
-# CHECK: %2:gpr64sp = ANDXri %0, 8060
body: |
bb.0:
liveins: $x0
+ ; CHECK-LABEL: name: ptr_mask
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 8060
+ ; CHECK-NEXT: $x0 = COPY [[ANDXri]]
%0:gpr(p0) = COPY $x0
%const:gpr(s64) = G_CONSTANT i64 -8
%1:gpr(p0) = G_PTRMASK %0, %const
@@ -67,50 +69,42 @@ body: |
---
# Global defined in the same linkage unit so no GOT is needed
-# CHECK-LABEL: name: global_local
name: global_local
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
-# CHECK: body:
-# LINUX-DEFAULT: %0:gpr64common = MOVaddr target-flags(aarch64-page) @var_local, target-flags(aarch64-pageoff, aarch64-nc) @var_local
body: |
bb.0:
+ ; CHECK-LABEL: name: global_local
+ ; CHECK: [[MOVaddr:%[0-9]+]]:gpr64common = MOVaddr target-flags(aarch64-page) @var_local, target-flags(aarch64-pageoff, aarch64-nc) @var_local
+ ; CHECK-NEXT: $x0 = COPY [[MOVaddr]]
%0(p0) = G_GLOBAL_VALUE @var_local
$x0 = COPY %0(p0)
...
---
-# CHECK-LABEL: name: global_got
name: global_got
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
-# CHECK: body:
-# LINUX-DEFAULT: %0:gpr64common = MOVaddr target-flags(aarch64-page) @var_got, target-flags(aarch64-pageoff, aarch64-nc) @var_got
body: |
bb.0:
+ ; CHECK-LABEL: name: global_got
+ ; CHECK: [[MOVaddr:%[0-9]+]]:gpr64common = MOVaddr target-flags(aarch64-page) @var_got, target-flags(aarch64-pageoff, aarch64-nc) @var_got
+ ; CHECK-NEXT: $x0 = COPY [[MOVaddr]]
%0(p0) = G_GLOBAL_VALUE @var_got
$x0 = COPY %0(p0)
...
---
-# CHECK-LABEL: name: icmp
name: icmp
legalized: true
regBankSelected: true
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 3, class: gpr32, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 4, class: gpr64, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 5, class: gpr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@@ -125,20 +119,28 @@ registers:
- { id: 10, class: gpr }
- { id: 11, class: gpr }
-# CHECK: body:
-# CHECK: SUBSWrr %0, %0, implicit-def $nzcv
-# CHECK: %1:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
-# CHECK: SUBSXrr %2, %2, implicit-def $nzcv
-# CHECK: %3:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
-# CHECK: SUBSXrr %4, %4, implicit-def $nzcv
-# CHECK: %5:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
body: |
bb.0:
liveins: $w0, $x0
+ ; CHECK-LABEL: name: icmp
+ ; CHECK: liveins: $w0, $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY1]], [[COPY1]], implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY [[CSINCWr1]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[SUBSXrr1:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY2]], implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr2:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY [[CSINCWr2]]
%0(s32) = COPY $w0
%1(s32) = G_ICMP intpred(eq), %0, %0
$w0 = COPY %1
@@ -153,37 +155,34 @@ body: |
...
---
-# CHECK-LABEL: name: fcmp
name: fcmp
legalized: true
regBankSelected: true
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 2, class: fpr64, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 3, class: gpr32, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 4, class: gpr32, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 5, class: gpr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
- { id: 2, class: fpr }
- { id: 3, class: gpr }
-# CHECK: body:
-# CHECK: nofpexcept FCMPSrr %0, %0, implicit-def $nzcv
-# CHECK: [[TST_MI:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
-# CHECK: [[TST_GT:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
-# CHECK: %1:gpr32 = ORRWrr [[TST_MI]], [[TST_GT]]
-# CHECK: nofpexcept FCMPDrr %2, %2, implicit-def $nzcv
-# CHECK: %3:gpr32 = CSINCWr $wzr, $wzr, 4, implicit $nzcv
body: |
bb.0:
liveins: $w0, $x0
+ ; CHECK-LABEL: name: fcmp
+ ; CHECK: liveins: $w0, $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+ ; CHECK-NEXT: nofpexcept FCMPSrr [[COPY]], [[COPY]], implicit-def $nzcv, implicit $fpcr
+ ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
+ ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr [[CSINCWr]], $wzr, 13, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY [[CSINCWr1]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK-NEXT: nofpexcept FCMPDrr [[COPY1]], [[COPY1]], implicit-def $nzcv, implicit $fpcr
+ ; CHECK-NEXT: [[CSINCWr2:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 4, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY [[CSINCWr2]]
%0(s32) = COPY $s0
%1(s32) = G_FCMP floatpred(one), %0, %0
$w0 = COPY %1
@@ -195,27 +194,35 @@ body: |
...
---
-# CHECK-LABEL: name: phi
name: phi
legalized: true
regBankSelected: true
tracksRegLiveness: true
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 2, class: fpr32, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 3, class: gpr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
- { id: 2, class: fpr }
-# CHECK: body:
-# CHECK: bb.1:
-# CHECK: %2:fpr32 = PHI %0, %bb.0, %2, %bb.1
body: |
+ ; CHECK-LABEL: name: phi
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $s0, $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:fpr32 = PHI [[COPY]], %bb.0, [[PHI]], %bb.1
+ ; CHECK-NEXT: TBNZW [[COPY1]], 0, %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $s0 = COPY [[PHI]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
bb.0:
liveins: $s0, $w0
successors: %bb.1
@@ -233,23 +240,11 @@ body: |
...
---
-# CHECK-LABEL: name: select
name: select
legalized: true
regBankSelected: true
tracksRegLiveness: true
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 3, class: gpr32, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 4, class: gpr64, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 5, class: gpr64, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 6, class: gpr64, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 7, class: gpr64, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 8, class: gpr64, preferred-register: '', flags: [ ] }
-# CHECK-NEXT: - { id: 9, class: gpr64, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@@ -262,16 +257,28 @@ registers:
- { id: 8, class: gpr }
- { id: 9, class: gpr }
-# CHECK: body:
-# CHECK: ANDSWri %0, 0, implicit-def $nzcv
-# CHECK: %3:gpr32 = CSELWr %1, %2, 1, implicit $nzcv
-# CHECK: ANDSWri %0, 0, implicit-def $nzcv
-# CHECK: %6:gpr64 = CSELXr %4, %5, 1, implicit $nzcv
-# CHECK: ANDSWri %0, 0, implicit-def $nzcv
-# CHECK: %9:gpr64 = CSELXr %7, %8, 1, implicit $nzcv
body: |
bb.0:
liveins: $w0, $w1, $w2
+ ; CHECK-LABEL: name: select
+ ; CHECK: liveins: $w0, $w1, $w2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY1]], [[COPY2]], 1, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY [[CSELWr]]
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: [[ANDSWri1:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[COPY3]], [[COPY4]], 1, implicit $nzcv
+ ; CHECK-NEXT: $x0 = COPY [[CSELXr]]
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: [[ANDSWri2:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSELXr1:%[0-9]+]]:gpr64 = CSELXr [[COPY5]], [[COPY6]], 1, implicit $nzcv
+ ; CHECK-NEXT: $x0 = COPY [[CSELXr1]]
%0:gpr(s32) = COPY $w0
%1(s32) = COPY $w1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
index b3613f52c4ec6..5185e5e96f683 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
@@ -152,9 +152,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: nofpexcept FCMPSrr [[COPY]], [[COPY]], implicit-def $nzcv, implicit $fpcr
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
- ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
- ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[ORRWrr]]
+ ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr [[CSINCWr]], $wzr, 13, implicit $nzcv
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[CSINCWr1]]
; CHECK-NEXT: $w0 = COPY [[COPY1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: nofpexcept FCMPDrr [[COPY2]], [[COPY2]], implicit-def $nzcv, implicit $fpcr
diff --git a/llvm/test/CodeGen/AArch64/bf16-instructions.ll b/llvm/test/CodeGen/AArch64/bf16-instructions.ll
index 3942c0efdb28a..348bd8495af81 100644
--- a/llvm/test/CodeGen/AArch64/bf16-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/bf16-instructions.ll
@@ -775,8 +775,7 @@ define i1 @test_fcmp_ueq(bfloat %a, bfloat %b) #0 {
; CHECK-CVT-GI-NEXT: shll v1.4s, v1.4h, #16
; CHECK-CVT-GI-NEXT: fcmp s0, s1
; CHECK-CVT-GI-NEXT: cset w8, eq
-; CHECK-CVT-GI-NEXT: cset w9, vs
-; CHECK-CVT-GI-NEXT: orr w0, w8, w9
+; CHECK-CVT-GI-NEXT: csinc w0, w8, wzr, vc
; CHECK-CVT-GI-NEXT: ret
;
; CHECK-BF16-GI-LABEL: test_fcmp_ueq:
@@ -787,8 +786,7 @@ define i1 @test_fcmp_ueq(bfloat %a, bfloat %b) #0 {
; CHECK-BF16-GI-NEXT: shll v1.4s, v1.4h, #16
; CHECK-BF16-GI-NEXT: fcmp s0, s1
; CHECK-BF16-GI-NEXT: cset w8, eq
-; CHECK-BF16-GI-NEXT: cset w9, vs
-; CHECK-BF16-GI-NEXT: orr w0, w8, w9
+; CHECK-BF16-GI-NEXT: csinc w0, w8, wzr, vc
; CHECK-BF16-GI-NEXT: ret
%r = fcmp ueq bfloat %a, %b
ret i1 %r
@@ -1045,8 +1043,7 @@ define i1 @test_fcmp_one(bfloat %a, bfloat %b) #0 {
; CHECK-CVT-GI-NEXT: shll v1.4s, v1.4h, #16
; CHECK-CVT-GI-NEXT: fcmp s0, s1
; CHECK-CVT-GI-NEXT: cset w8, mi
-; CHECK-CVT-GI-NEXT: cset w9, gt
-; CHECK-CVT-GI-NEXT: orr w0, w8, w9
+; CHECK-CVT-GI-NEXT: csinc w0, w8, wzr, le
; CHECK-CVT-GI-NEXT: ret
;
; CHECK-BF16-GI-LABEL: test_fcmp_one:
@@ -1057,8 +1054,7 @@ define i1 @test_fcmp_one(bfloat %a, bfloat %b) #0 {
; CHECK-BF16-GI-NEXT: shll v1.4s, v1.4h, #16
; CHECK-BF16-GI-NEXT: fcmp s0, s1
; CHECK-BF16-GI-NEXT: cset w8, mi
-; CHECK-BF16-GI-NEXT: cset w9, gt
-; CHECK-BF16-GI-NEXT: orr w0, w8, w9
+; CHECK-BF16-GI-NEXT: csinc w0, w8, wzr, le
; CHECK-BF16-GI-NEXT: ret
%r = fcmp one bfloat %a, %b
ret i1 %r
diff --git a/llvm/test/CodeGen/AArch64/f16-instructions.ll b/llvm/test/CodeGen/AArch64/f16-instructions.ll
index 7ffe5ae10f838..c13494e38f2b6 100644
--- a/llvm/test/CodeGen/AArch64/f16-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/f16-instructions.ll
@@ -403,12 +403,12 @@ define i1 @test_fcmp_ueq(half %a, half %b) #0 {
; CHECK-CVT-SD-NEXT: csinc w0, w8, wzr, vc
; CHECK-CVT-SD-NEXT: ret
;
-; CHECK-FP16-SD-LABEL: test_fcmp_ueq:
-; CHECK-FP16-SD: // %bb.0:
-; CHECK-FP16-SD-NEXT: fcmp h0, h1
-; CHECK-FP16-SD-NEXT: cset w8, eq
-; CHECK-FP16-SD-NEXT: csinc w0, w8, wzr, vc
-; CHECK-FP16-SD-NEXT: ret
+; CHECK-FP16-LABEL: test_fcmp_ueq:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcmp h0, h1
+; CHECK-FP16-NEXT: cset w8, eq
+; CHECK-FP16-NEXT: csinc w0, w8, wzr, vc
+; CHECK-FP16-NEXT: ret
;
; CHECK-CVT-GI-LABEL: test_fcmp_ueq:
; CHECK-CVT-GI: // %bb.0:
@@ -416,17 +416,8 @@ define i1 @test_fcmp_ueq(half %a, half %b) #0 {
; CHECK-CVT-GI-NEXT: fcvt s1, h1
; CHECK-CVT-GI-NEXT: fcmp s0, s1
; CHECK-CVT-GI-NEXT: cset w8, eq
-; CHECK-CVT-GI-NEXT: cset w9, vs
-; CHECK-CVT-GI-NEXT: orr w0, w8, w9
+; CHECK-CVT-GI-NEXT: csinc w0, w8, wzr, vc
; CHECK-CVT-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: test_fcmp_ueq:
-; CHECK-FP16-GI: // %bb.0:
-; CHECK-FP16-GI-NEXT: fcmp h0, h1
-; CHECK-FP16-GI-NEXT: cset w8, eq
-; CHECK-FP16-GI-NEXT: cset w9, vs
-; CHECK-FP16-GI-NEXT: orr w0, w8, w9
-; CHECK-FP16-GI-NEXT: ret
%r = fcmp ueq half %a, %b
ret i1 %r
}
@@ -571,12 +562,12 @@ define i1 @test_fcmp_one(half %a, half %b) #0 {
; CHECK-CVT-SD-NEXT: csinc w0, w8, wzr, le
; CHECK-CVT-SD-NEXT: ret
;
-; CHECK-FP16-SD-LABEL: test_fcmp_one:
-; CHECK-FP16-SD: // %bb.0:
-; CHECK-FP16-SD-NEXT: fcmp h0, h1
-; CHECK-FP16-SD-NEXT: cset w8, mi
-; CHECK-FP16-SD-NEXT: csinc w0, w8, wzr, le
-; CHECK-FP16-SD-NEXT: ret
+; CHECK-FP16-LABEL: test_fcmp_one:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcmp h0, h1
+; CHECK-FP16-NEXT: cset w8, mi
+; CHECK-FP16-NEXT: csinc w0, w8, wzr, le
+; CHECK-FP16-NEXT: ret
;
; CHECK-CVT-GI-LABEL: test_fcmp_one:
; CHECK-CVT-GI: // %bb.0:
@@ -584,17 +575,8 @@ define i1 @test_fcmp_one(half %a, half %b) #0 {
; CHECK-CVT-GI-NEXT: fcvt s1, h1
; CHECK-CVT-GI-NEXT: fcmp s0, s1
; CHECK-CVT-GI-NEXT: cset w8, mi
-; CHECK-CVT-GI-NEXT: cset w9, gt
-; CHECK-CVT-GI-NEXT: orr w0, w8, w9
+; CHECK-CVT-GI-NEXT: csinc w0, w8, wzr, le
; CHECK-CVT-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: test_fcmp_one:
-; CHECK-FP16-GI: // %bb.0:
-; CHECK-FP16-GI-NEXT: fcmp h0, h1
-; CHECK-FP16-GI-NEXT: cset w8, mi
-; CHECK-FP16-GI-NEXT: cset w9, gt
-; CHECK-FP16-GI-NEXT: orr w0, w8, w9
-; CHECK-FP16-GI-NEXT: ret
%r = fcmp one half %a, %b
ret i1 %r
}
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-select.ll b/llvm/test/CodeGen/AArch64/fast-isel-select.ll
index 6e55bf4968e78..c065606632d94 100644
--- a/llvm/test/CodeGen/AArch64/fast-isel-select.ll
+++ b/llvm/test/CodeGen/AArch64/fast-isel-select.ll
@@ -246,8 +246,7 @@ define float @select_fcmp_one(float %x, float %y, float %a, float %b) {
; CHECK-GISEL: ; %bb.0:
; CHECK-GISEL-NEXT: fcmp s0, s1
; CHECK-GISEL-NEXT: cset w8, mi
-; CHECK-GISEL-NEXT: cset w9, gt
-; CHECK-GISEL-NEXT: orr w8, w8, w9
+; CHECK-GISEL-NEXT: csinc w8, w8, wzr, le
; CHECK-GISEL-NEXT: tst w8, #0x1
; CHECK-GISEL-NEXT: fcsel s0, s2, s3, ne
; CHECK-GISEL-NEXT: ret
@@ -297,8 +296,7 @@ define float @select_fcmp_ueq(float %x, float %y, float %a, float %b) {
; CHECK-GISEL: ; %bb.0:
; CHECK-GISEL-NEXT: fcmp s0, s1
; CHECK-GISEL-NEXT: cset w8, eq
-; CHECK-GISEL-NEXT: cset w9, vs
-; CHECK-GISEL-NEXT: orr w8, w8, w9
+; CHECK-GISEL-NEXT: csinc w8, w8, wzr, vc
; CHECK-GISEL-NEXT: tst w8, #0x1
; CHECK-GISEL-NEXT: fcsel s0, s2, s3, ne
; CHECK-GISEL-NEXT: ret
@@ -378,8 +376,7 @@ define float @select_fcmp_true(float %x, float %a, float %b) {
; CHECK-GISEL: ; %bb.0:
; CHECK-GISEL-NEXT: fcmp s0, s0
; CHECK-GISEL-NEXT: cset w8, eq
-; CHECK-GISEL-NEXT: cset w9, vs
-; CHECK-GISEL-NEXT: orr w8, w8, w9
+; CHECK-GISEL-NEXT: csinc w8, w8, wzr, vc
; CHECK-GISEL-NEXT: tst w8, #0x1
; CHECK-GISEL-NEXT: fcsel s0, s1, s2, ne
; CHECK-GISEL-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/half-precision-signof-no-assert.ll b/llvm/test/CodeGen/AArch64/half-precision-signof-no-assert.ll
index 4bf2b8c7e6a57..12f6f64cf8b1a 100644
--- a/llvm/test/CodeGen/AArch64/half-precision-signof-no-assert.ll
+++ b/llvm/test/CodeGen/AArch64/half-precision-signof-no-assert.ll
@@ -54,8 +54,7 @@ define ptr @fn(ptr %in, ptr %out) {
; CHECK-GI-NEXT: fcvt s0, h0
; CHECK-GI-NEXT: fcmp s0, #0.0
; CHECK-GI-NEXT: cset w8, mi
-; CHECK-GI-NEXT: cset w9, gt
-; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: csinc w8, w8, wzr, le
; CHECK-GI-NEXT: ucvtf s0, w8
; CHECK-GI-NEXT: fcvt h0, s0
; CHECK-GI-NEXT: bif v0.8b, v2.8b, v1.8b
diff --git a/llvm/test/CodeGen/AArch64/strict-fp-int-promote.ll b/llvm/test/CodeGen/AArch64/strict-fp-int-promote.ll
index 0f7ea36949da5..7c70f5461a219 100644
--- a/llvm/test/CodeGen/AArch64/strict-fp-int-promote.ll
+++ b/llvm/test/CodeGen/AArch64/strict-fp-int-promote.ll
@@ -12,7 +12,7 @@ declare float @llvm.experimental.constrained.uitofp.f32.i16(i16, metadata, metad
define i32 @test() #0 {
; CHECK-LABEL: test:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #1
+; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: scvtf s0, w8
; CHECK-NEXT: fcmp s0, s0
; CHECK-NEXT: cset w0, eq
@@ -20,9 +20,9 @@ define i32 @test() #0 {
;
; SUBOPTIMAL-LABEL: test:
; SUBOPTIMAL: // %bb.0: // %entry
-; SUBOPTIMAL-NEXT: mov w8, #1
+; SUBOPTIMAL-NEXT: mov w8, #1 // =0x1
; SUBOPTIMAL-NEXT: scvtf s0, w8
-; SUBOPTIMAL-NEXT: mov w8, #1
+; SUBOPTIMAL-NEXT: mov w8, #1 // =0x1
; SUBOPTIMAL-NEXT: scvtf s1, w8
; SUBOPTIMAL-NEXT: fcmp s0, s1
; SUBOPTIMAL-NEXT: cset w8, eq
@@ -39,7 +39,7 @@ entry:
define i32 @test2() #0 {
; CHECK-LABEL: test2:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #1
+; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: scvtf s0, w8
; CHECK-NEXT: ucvtf s1, w8
; CHECK-NEXT: fcmp s0, s1
@@ -48,9 +48,9 @@ define i32 @test2() #0 {
;
; SUBOPTIMAL-LABEL: test2:
; SUBOPTIMAL: // %bb.0: // %entry
-; SUBOPTIMAL-NEXT: mov w8, #1
+; SUBOPTIMAL-NEXT: mov w8, #1 // =0x1
; SUBOPTIMAL-NEXT: scvtf s0, w8
-; SUBOPTIMAL-NEXT: mov w8, #1
+; SUBOPTIMAL-NEXT: mov w8, #1 // =0x1
; SUBOPTIMAL-NEXT: ucvtf s1, w8
; SUBOPTIMAL-NEXT: fcmp s0, s1
; SUBOPTIMAL-NEXT: cset w8, eq
More information about the llvm-commits
mailing list