[llvm] [AMDGPU] Do not combine V_ASHRREV_I16* to make sdwa (PR #198491)

[Matt Arsenault via llvm-commits]

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@@ -708,19 +708,17 @@ SIPeepholeSDWA::matchSDWAOperand(MachineInstr &MI) {
   }
 
   case AMDGPU::V_LSHRREV_B16_e32:
-  case AMDGPU::V_ASHRREV_I16_e32:
   case AMDGPU::V_LSHLREV_B16_e32:
   case AMDGPU::V_LSHRREV_B16_e64:
   case AMDGPU::V_LSHRREV_B16_opsel_e64:
-  case AMDGPU::V_ASHRREV_I16_e64:
   case AMDGPU::V_LSHLREV_B16_opsel_e64:
   case AMDGPU::V_LSHLREV_B16_e64: {
+    // V_ASHRREV_I16_e32 and V_ASHRREV_I16_e64 are
+    // not included here because they zero-fill the high 16-bits.
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arsenm wrote:

I thought this changed in gfx9, and was controlled by the opsel bit. the gfx8 behavior was 0 high, then preserve high?

https://github.com/llvm/llvm-project/pull/198491