[llvm] [AMDGPU] Add llvm.amdgcn.s.prefetch.inst intrinsic (PR #192440)

[Matt Arsenault via llvm-commits]

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@@ -3196,6 +3196,22 @@ bool AMDGPUInstructionSelector::selectG_GLOBAL_VALUE(
     DstReg, IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass, *MRI);
 }
 
+bool AMDGPUInstructionSelector::selectG_BLOCK_ADDR(MachineInstr &I) const {
+  MachineBasicBlock *BB = I.getParent();
+  const DebugLoc &DL = I.getDebugLoc();
+  Register DstReg = I.getOperand(0).getReg();
+  const BlockAddress *BA = I.getOperand(1).getBlockAddress();
+
+  BuildMI(*BB, &I, DL, TII.get(AMDGPU::SI_PC_ADD_REL_OFFSET64), DstReg)
+      .addBlockAddress(BA);
+
+  if (!MRI->getRegClassOrNull(DstReg))
+    MRI->setRegClass(DstReg, &AMDGPU::SReg_64RegClass);
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arsenm wrote:

Better to avoid hardcoding the class, use constrainSelectedInstRegOperands? Or better, let tablegen take care of it 

https://github.com/llvm/llvm-project/pull/192440