[llvm] [AMDGPU][GlobalISel] Combine rcp(sqrt(x)) into rsq for pseudo-scalar instructions (PR #198785)

[Jay Foad via llvm-commits]

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@@ -1620,25 +1620,37 @@ define float @v_recip_sqrt_f32_afn_ulp25_contract(float %x) {
 ; CODEGEN-IEEE-GISEL-NEXT:    v_rsq_f32_e32 v0, v0
 ; CODEGEN-IEEE-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; IR-IEEE-LABEL: v_recip_sqrt_f32_afn_ulp25_contract:
-; IR-IEEE:       ; %bb.0:
-; IR-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; IR-IEEE-NEXT:    v_sqrt_f32_e32 v0, v0
-; IR-IEEE-NEXT:    v_rcp_f32_e32 v0, v0
-; IR-IEEE-NEXT:    s_setpc_b64 s[30:31]
+; IR-IEEE-SDAG-LABEL: v_recip_sqrt_f32_afn_ulp25_contract:
+; IR-IEEE-SDAG:       ; %bb.0:
+; IR-IEEE-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; IR-IEEE-SDAG-NEXT:    v_sqrt_f32_e32 v0, v0
+; IR-IEEE-SDAG-NEXT:    v_rcp_f32_e32 v0, v0
+; IR-IEEE-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; IR-IEEE-GISEL-LABEL: v_recip_sqrt_f32_afn_ulp25_contract:
+; IR-IEEE-GISEL:       ; %bb.0:
+; IR-IEEE-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; IR-IEEE-GISEL-NEXT:    v_rsq_f32_e32 v0, v0
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jayfoad wrote:

Should probably investigate whether it's OK to use v_rsq here, and why SelectionDAG does not.

https://github.com/llvm/llvm-project/pull/198785