[llvm] 75ae202 - [AArch64][GlobalISel] Add sign bits for G_FCMEQ (#198314)

[via llvm-commits]

Author: David Green
Date: 2026-05-19T12:56:32+01:00
New Revision: 75ae202145b316883caa6074e9c94431ef152c26

URL: https://github.com/llvm/llvm-project/commit/75ae202145b316883caa6074e9c94431ef152c26
DIFF: https://github.com/llvm/llvm-project/commit/75ae202145b316883caa6074e9c94431ef152c26.diff

LOG: [AArch64][GlobalISel] Add sign bits for G_FCMEQ (#198314)

This adds basic num-sign-bits for G_FCMEQ, G_FCMGE and G_FCMGT, which
all produce either all-ones or all-zeros in each vector lane. This
function apparently goes in AArch64ISelLowering.

Added: 
    llvm/test/CodeGen/AArch64/GlobalISel/knownbits-fcmeq.mir

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/lib/Target/AArch64/AArch64ISelLowering.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 8c93adac0adf9..c90da5df1a7e9 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -2992,6 +2992,25 @@ unsigned AArch64TargetLowering::ComputeNumSignBitsForTargetNode(
   return 1;
 }
 
+unsigned AArch64TargetLowering::computeNumSignBitsForTargetInstr(
+    GISelValueTracking &Analysis, Register R, const APInt &DemandedElts,
+    const MachineRegisterInfo &MRI, unsigned Depth) const {
+  const MachineInstr *MI = MRI.getVRegDef(R);
+  if (!MI)
+    return 1;
+
+  switch (MI->getOpcode()) {
+  case AArch64::G_FCMEQ:
+  case AArch64::G_FCMGE:
+  case AArch64::G_FCMGT: {
+    LLT VT = MRI.getType(R);
+    return VT.getScalarSizeInBits();
+  }
+  default:
+    return 1;
+  }
+}
+
 MVT AArch64TargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
                                                   EVT) const {
   return MVT::i64;

diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 25cab4d3eed7e..808d297d54e10 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -91,6 +91,12 @@ class AArch64TargetLowering : public TargetLowering {
                                            const SelectionDAG &DAG,
                                            unsigned Depth) const override;
 
+  unsigned computeNumSignBitsForTargetInstr(GISelValueTracking &Analysis,
+                                            Register R,
+                                            const APInt &DemandedElts,
+                                            const MachineRegisterInfo &MRI,
+                                            unsigned Depth = 0) const override;
+
   MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const override {
     if ((AS == ARM64AS::PTR32_SPTR) || (AS == ARM64AS::PTR32_UPTR)) {
       // These are 32-bit pointers created using the `__ptr32` extension or

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-fcmeq.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-fcmeq.mir
new file mode 100644
index 0000000000000..a72734f9d5a4b
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-fcmeq.mir
@@ -0,0 +1,45 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64 -passes='print<gisel-value-tracking>' -filetype=null %s 2>&1 | FileCheck %s
+
+---
+name: FCMEQ
+body: |
+  bb.1:
+    liveins: $q0, $q1
+  ; CHECK-LABEL: name: @FCMEQ
+  ; CHECK-NEXT: %0:fpr KnownBits:???????????????? SignBits:1
+  ; CHECK-NEXT: %1:fpr KnownBits:???????????????? SignBits:1
+  ; CHECK-NEXT: %2:fpr KnownBits:???????????????? SignBits:16
+    %0:fpr(<8 x f16>) = COPY $q0
+    %1:fpr(<8 x f16>) = COPY $q1
+    %2:fpr(<8 x i16>) = G_FCMEQ %0:fpr, %1:fpr(<8 x f16>)
+    $q0 = COPY %2:fpr(<8 x i16>)
+...
+---
+name: FCMGE
+body: |
+  bb.1:
+    liveins: $q0, $q1
+  ; CHECK-LABEL: name: @FCMGE
+  ; CHECK-NEXT: %0:fpr KnownBits:???????????????????????????????? SignBits:1
+  ; CHECK-NEXT: %1:fpr KnownBits:???????????????????????????????? SignBits:1
+  ; CHECK-NEXT: %2:fpr KnownBits:???????????????????????????????? SignBits:32
+    %0:fpr(<4 x f32>) = COPY $q0
+    %1:fpr(<4 x f32>) = COPY $q1
+    %2:fpr(<4 x i32>) = G_FCMGE %0:fpr, %1:fpr(<4 x f32>)
+    $q0 = COPY %2:fpr(<4 x i32>)
+...
+---
+name: FCMGT
+body: |
+  bb.1:
+    liveins: $q0, $q1
+  ; CHECK-LABEL: name: @FCMGT
+  ; CHECK-NEXT: %0:fpr KnownBits:???????????????????????????????????????????????????????????????? SignBits:1
+  ; CHECK-NEXT: %1:fpr KnownBits:???????????????????????????????????????????????????????????????? SignBits:1
+  ; CHECK-NEXT: %2:fpr KnownBits:???????????????????????????????????????????????????????????????? SignBits:64
+    %0:fpr(<2 x f64>) = COPY $q0
+    %1:fpr(<2 x f64>) = COPY $q1
+    %2:fpr(<2 x i64>) = G_FCMGT %0:fpr, %1:fpr(<2 x f64>)
+    $q0 = COPY %2:fpr(<2 x i64>)
+...