[llvm] [AMDGPU][GlobalISel] Add RegBankLegalize rules for G_FPTOSI_SAT/G_FPTOUI_SAT (PR #198208)
via llvm-commits
llvm-commits at lists.llvm.org
Sun May 17 12:28:23 PDT 2026
https://github.com/asadium updated https://github.com/llvm/llvm-project/pull/198208
>From bc6a46b94d860098a86bfc2d879f0d68d4d06a73 Mon Sep 17 00:00:00 2001
From: Asad <asadmhm at pm.me>
Date: Sun, 17 May 2026 14:56:49 -0400
Subject: [PATCH] [AMDGPU][GlobalISel] Add RegBankLegalize rules for
G_FPTOSI_SAT/G_FPTOUI_SAT
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 2 +-
.../AMDGPU/GlobalISel/fp-int-conversions.ll | 222 ++++++++++++++++++
.../GlobalISel/regbankselect-fptosi-sat.mir | 36 +++
.../GlobalISel/regbankselect-fptoui-sat.mir | 36 +++
.../GlobalISel/regbankselect-salu-float.mir | 72 ++++++
5 files changed, 367 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 524c65227c8b0..c2a6d8f432b2b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1431,7 +1431,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S16, {{Sgpr16}, {Sgpr16}}, hasPST)
.Uni(S16, {{UniInVgprS16}, {Vgpr16}}, !hasPST);
- addRulesForGOpcs({G_FPTOUI, G_FPTOSI})
+ addRulesForGOpcs({G_FPTOUI, G_FPTOSI, G_FPTOUI_SAT, G_FPTOSI_SAT})
.Any({{UniS16, S16}, {{UniInVgprS16}, {Vgpr16}}})
.Any({{DivS16, S16}, {{Vgpr16}, {Vgpr16}}})
.Any({{UniS32, S16}, {{Sgpr32}, {Sgpr16}}}, hasSALUFloat)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
index 6b611d396044c..dafba5e3ccacf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
@@ -226,6 +226,228 @@ define amdgpu_ps void @v_fptosi_f64_to_i32(double %x, ptr addrspace(1) %out) {
ret void
}
+define amdgpu_ps void @s_fptoui_sat_f16_to_i16(half inreg %x, ptr addrspace(1) %out) {
+; PREGFX12-FAKE16-LABEL: s_fptoui_sat_f16_to_i16:
+; PREGFX12-FAKE16: ; %bb.0:
+; PREGFX12-FAKE16: v_cvt_u16_f16_e32 v2, s0
+;
+; TRUE16-LABEL: s_fptoui_sat_f16_to_i16:
+; TRUE16: ; %bb.0:
+; TRUE16: v_cvt_u16_f16_e32 v2.l, s0
+;
+; GFX12-LABEL: s_fptoui_sat_f16_to_i16:
+; GFX12: ; %bb.0:
+; GFX12: v_cvt_u16_f16_e32 v2.l, s0
+ %result = call i16 @llvm.fptoui.sat.i16.f16(half %x)
+ store i16 %result, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @s_fptosi_sat_f16_to_i16(half inreg %x, ptr addrspace(1) %out) {
+; PREGFX12-FAKE16-LABEL: s_fptosi_sat_f16_to_i16:
+; PREGFX12-FAKE16: ; %bb.0:
+; PREGFX12-FAKE16: v_cvt_i16_f16_e32 v2, s0
+;
+; TRUE16-LABEL: s_fptosi_sat_f16_to_i16:
+; TRUE16: ; %bb.0:
+; TRUE16: v_cvt_i16_f16_e32 v2.l, s0
+;
+; GFX12-LABEL: s_fptosi_sat_f16_to_i16:
+; GFX12: ; %bb.0:
+; GFX12: v_cvt_i16_f16_e32 v2.l, s0
+ %result = call i16 @llvm.fptosi.sat.i16.f16(half %x)
+ store i16 %result, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @v_fptoui_sat_f16_to_i16(half %x, ptr addrspace(1) %out) {
+; PREGFX12-FAKE16-LABEL: v_fptoui_sat_f16_to_i16:
+; PREGFX12-FAKE16: ; %bb.0:
+; PREGFX12-FAKE16: v_cvt_u16_f16_e32 v0, v0
+;
+; TRUE16-LABEL: v_fptoui_sat_f16_to_i16:
+; TRUE16: ; %bb.0:
+; TRUE16: v_cvt_u16_f16_e32 v0.l, v0.l
+;
+; GFX12-LABEL: v_fptoui_sat_f16_to_i16:
+; GFX12: ; %bb.0:
+; GFX12: v_cvt_u16_f16_e32 v0.l, v0.l
+ %result = call i16 @llvm.fptoui.sat.i16.f16(half %x)
+ store i16 %result, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @v_fptosi_sat_f16_to_i16(half %x, ptr addrspace(1) %out) {
+; PREGFX12-FAKE16-LABEL: v_fptosi_sat_f16_to_i16:
+; PREGFX12-FAKE16: ; %bb.0:
+; PREGFX12-FAKE16: v_cvt_i16_f16_e32 v0, v0
+;
+; TRUE16-LABEL: v_fptosi_sat_f16_to_i16:
+; TRUE16: ; %bb.0:
+; TRUE16: v_cvt_i16_f16_e32 v0.l, v0.l
+;
+; GFX12-LABEL: v_fptosi_sat_f16_to_i16:
+; GFX12: ; %bb.0:
+; GFX12: v_cvt_i16_f16_e32 v0.l, v0.l
+ %result = call i16 @llvm.fptosi.sat.i16.f16(half %x)
+ store i16 %result, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @s_fptoui_sat_f16_to_i32(half inreg %x, ptr addrspace(1) %out) {
+; PREGFX12-LABEL: s_fptoui_sat_f16_to_i32:
+; PREGFX12: ; %bb.0:
+; PREGFX12: v_cvt_f32_f16_e32 v2, s0
+; PREGFX12: v_cvt_u32_f32_e32 v2, v2
+;
+; GFX12-LABEL: s_fptoui_sat_f16_to_i32:
+; GFX12: ; %bb.0:
+; GFX12: s_cvt_f32_f16 s0, s0
+; GFX12: s_cvt_u32_f32 s0, s0
+; GFX12: v_mov_b32_e32 v2, s0
+ %result = call i32 @llvm.fptoui.sat.i32.f16(half %x)
+ store i32 %result, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @s_fptosi_sat_f16_to_i32(half inreg %x, ptr addrspace(1) %out) {
+; PREGFX12-LABEL: s_fptosi_sat_f16_to_i32:
+; PREGFX12: ; %bb.0:
+; PREGFX12: v_cvt_f32_f16_e32 v2, s0
+; PREGFX12: v_cvt_i32_f32_e32 v2, v2
+;
+; GFX12-LABEL: s_fptosi_sat_f16_to_i32:
+; GFX12: ; %bb.0:
+; GFX12: s_cvt_f32_f16 s0, s0
+; GFX12: s_cvt_i32_f32 s0, s0
+; GFX12: v_mov_b32_e32 v2, s0
+ %result = call i32 @llvm.fptosi.sat.i32.f16(half %x)
+ store i32 %result, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @v_fptoui_sat_f16_to_i32(half %x, ptr addrspace(1) %out) {
+; PREGFX12-FAKE16-LABEL: v_fptoui_sat_f16_to_i32:
+; PREGFX12-FAKE16: ; %bb.0:
+; PREGFX12-FAKE16: v_cvt_f32_f16_e32 v0, v0
+; PREGFX12-FAKE16: v_cvt_u32_f32_e32 v0, v0
+;
+; TRUE16-LABEL: v_fptoui_sat_f16_to_i32:
+; TRUE16: ; %bb.0:
+; TRUE16: v_cvt_f32_f16_e32 v0, v0.l
+; TRUE16: v_cvt_u32_f32_e32 v0, v0
+;
+; GFX12-LABEL: v_fptoui_sat_f16_to_i32:
+; GFX12: ; %bb.0:
+; GFX12: v_cvt_f32_f16_e32 v0, v0.l
+; GFX12: v_cvt_u32_f32_e32 v0, v0
+ %result = call i32 @llvm.fptoui.sat.i32.f16(half %x)
+ store i32 %result, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @v_fptosi_sat_f16_to_i32(half %x, ptr addrspace(1) %out) {
+; PREGFX12-FAKE16-LABEL: v_fptosi_sat_f16_to_i32:
+; PREGFX12-FAKE16: ; %bb.0:
+; PREGFX12-FAKE16: v_cvt_f32_f16_e32 v0, v0
+; PREGFX12-FAKE16: v_cvt_i32_f32_e32 v0, v0
+;
+; TRUE16-LABEL: v_fptosi_sat_f16_to_i32:
+; TRUE16: ; %bb.0:
+; TRUE16: v_cvt_f32_f16_e32 v0, v0.l
+; TRUE16: v_cvt_i32_f32_e32 v0, v0
+;
+; GFX12-LABEL: v_fptosi_sat_f16_to_i32:
+; GFX12: ; %bb.0:
+; GFX12: v_cvt_f32_f16_e32 v0, v0.l
+; GFX12: v_cvt_i32_f32_e32 v0, v0
+ %result = call i32 @llvm.fptosi.sat.i32.f16(half %x)
+ store i32 %result, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @s_fptoui_sat_f32_to_i32(float inreg %x, ptr addrspace(1) %out) {
+; PREGFX12-LABEL: s_fptoui_sat_f32_to_i32:
+; PREGFX12: ; %bb.0:
+; PREGFX12: v_cvt_u32_f32_e32 v2, s0
+;
+; GFX12-LABEL: s_fptoui_sat_f32_to_i32:
+; GFX12: ; %bb.0:
+; GFX12: s_cvt_u32_f32 s0, s0
+; GFX12: v_mov_b32_e32 v2, s0
+ %result = call i32 @llvm.fptoui.sat.i32.f32(float %x)
+ store i32 %result, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @s_fptosi_sat_f32_to_i32(float inreg %x, ptr addrspace(1) %out) {
+; PREGFX12-LABEL: s_fptosi_sat_f32_to_i32:
+; PREGFX12: ; %bb.0:
+; PREGFX12: v_cvt_i32_f32_e32 v2, s0
+;
+; GFX12-LABEL: s_fptosi_sat_f32_to_i32:
+; GFX12: ; %bb.0:
+; GFX12: s_cvt_i32_f32 s0, s0
+; GFX12: v_mov_b32_e32 v2, s0
+ %result = call i32 @llvm.fptosi.sat.i32.f32(float %x)
+ store i32 %result, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @v_fptoui_sat_f32_to_i32(float %x, ptr addrspace(1) %out) {
+; GCN-LABEL: v_fptoui_sat_f32_to_i32:
+; GCN: ; %bb.0:
+; GCN: v_cvt_u32_f32_e32 v0, v0
+ %result = call i32 @llvm.fptoui.sat.i32.f32(float %x)
+ store i32 %result, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @v_fptosi_sat_f32_to_i32(float %x, ptr addrspace(1) %out) {
+; GCN-LABEL: v_fptosi_sat_f32_to_i32:
+; GCN: ; %bb.0:
+; GCN: v_cvt_i32_f32_e32 v0, v0
+ %result = call i32 @llvm.fptosi.sat.i32.f32(float %x)
+ store i32 %result, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @s_fptoui_sat_f64_to_i32(double inreg %x, ptr addrspace(1) %out) {
+; GCN-LABEL: s_fptoui_sat_f64_to_i32:
+; GCN: ; %bb.0:
+; GCN: v_cvt_u32_f64_e32 v2, s[0:1]
+ %result = call i32 @llvm.fptoui.sat.i32.f64(double %x)
+ store i32 %result, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @s_fptosi_sat_f64_to_i32(double inreg %x, ptr addrspace(1) %out) {
+; GCN-LABEL: s_fptosi_sat_f64_to_i32:
+; GCN: ; %bb.0:
+; GCN: v_cvt_i32_f64_e32 v2, s[0:1]
+ %result = call i32 @llvm.fptosi.sat.i32.f64(double %x)
+ store i32 %result, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @v_fptoui_sat_f64_to_i32(double %x, ptr addrspace(1) %out) {
+; GCN-LABEL: v_fptoui_sat_f64_to_i32:
+; GCN: ; %bb.0:
+; GCN: v_cvt_u32_f64_e32 v0, v[0:1]
+ %result = call i32 @llvm.fptoui.sat.i32.f64(double %x)
+ store i32 %result, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @v_fptosi_sat_f64_to_i32(double %x, ptr addrspace(1) %out) {
+; GCN-LABEL: v_fptosi_sat_f64_to_i32:
+; GCN: ; %bb.0:
+; GCN: v_cvt_i32_f64_e32 v0, v[0:1]
+ %result = call i32 @llvm.fptosi.sat.i32.f64(double %x)
+ store i32 %result, ptr addrspace(1) %out
+ ret void
+}
+
define amdgpu_ps void @s_uitofp_i16_to_f16(i16 inreg %x, ptr addrspace(1) %out) {
; PREGFX12-FAKE16-LABEL: s_uitofp_i16_to_f16:
; PREGFX12-FAKE16: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir
new file mode 100644
index 0000000000000..29db4e85e3737
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir
@@ -0,0 +1,36 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize -o - %s | FileCheck %s
+
+---
+name: fptosi_sat_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: fptosi_sat_s
+ ; CHECK: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[FPTOSI_SAT:%[0-9]+]]:vgpr(s32) = G_FPTOSI_SAT [[COPY1]](s32)
+ ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[FPTOSI_SAT]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = G_FPTOSI_SAT %0
+...
+
+---
+name: fptosi_sat_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; CHECK-LABEL: name: fptosi_sat_v
+ ; CHECK: liveins: $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[FPTOSI_SAT:%[0-9]+]]:vgpr(s32) = G_FPTOSI_SAT [[COPY]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = G_FPTOSI_SAT %0
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir
new file mode 100644
index 0000000000000..893665f82128e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir
@@ -0,0 +1,36 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize -o - %s | FileCheck %s
+
+---
+name: fptoui_sat_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: fptoui_sat_s
+ ; CHECK: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[FPTOUI_SAT:%[0-9]+]]:vgpr(s32) = G_FPTOUI_SAT [[COPY1]](s32)
+ ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[FPTOUI_SAT]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = G_FPTOUI_SAT %0
+...
+
+---
+name: fptoui_sat_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; CHECK-LABEL: name: fptoui_sat_v
+ ; CHECK: liveins: $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[FPTOUI_SAT:%[0-9]+]]:vgpr(s32) = G_FPTOUI_SAT [[COPY]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = G_FPTOUI_SAT %0
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
index a0ea49d002803..a030c2a213342 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
@@ -51,6 +51,38 @@ body: |
%1:_(s32) = G_FPTOUI %0(s32)
...
+---
+name: fptosi_sat_f32_to_i32
+legalized: true
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; GFX1150-LABEL: name: fptosi_sat_f32_to_i32
+ ; GFX1150: liveins: $sgpr0
+ ; GFX1150-NEXT: {{ $}}
+ ; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX1150-NEXT: [[FPTOSI_SAT:%[0-9]+]]:sgpr(s32) = G_FPTOSI_SAT [[COPY]](s32)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = G_FPTOSI_SAT %0(s32)
+...
+
+---
+name: fptoui_sat_f32_to_u32
+legalized: true
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; GFX1150-LABEL: name: fptoui_sat_f32_to_u32
+ ; GFX1150: liveins: $sgpr0
+ ; GFX1150-NEXT: {{ $}}
+ ; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX1150-NEXT: [[FPTOUI_SAT:%[0-9]+]]:sgpr(s32) = G_FPTOUI_SAT [[COPY]](s32)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = G_FPTOUI_SAT %0(s32)
+...
+
---
name: sitofp_i32_to_f32
legalized: true
@@ -181,6 +213,46 @@ body: |
%2:_(s16) = G_FPTOUI %0(s16)
...
+---
+name: fptosi_sat_f64_to_i32
+legalized: true
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+
+ ; GFX1150-LABEL: name: fptosi_sat_f64_to_i32
+ ; GFX1150: liveins: $sgpr0, $sgpr1
+ ; GFX1150-NEXT: {{ $}}
+ ; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; GFX1150-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; GFX1150-NEXT: [[FPTOSI_SAT:%[0-9]+]]:vgpr(s32) = G_FPTOSI_SAT [[COPY1]](s64)
+ ; GFX1150-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[FPTOSI_SAT]]
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s32) = G_FPTOSI_SAT %0(s64)
+...
+
+---
+name: fptoui_sat_f16_to_u16
+legalized: true
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; GFX1150-LABEL: name: fptoui_sat_f16_to_u16
+ ; GFX1150: liveins: $sgpr0
+ ; GFX1150-NEXT: {{ $}}
+ ; GFX1150-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX1150-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX1150-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
+ ; GFX1150-NEXT: [[FPTOUI_SAT:%[0-9]+]]:vgpr(s16) = G_FPTOUI_SAT [[COPY1]](s16)
+ ; GFX1150-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FPTOUI_SAT]](s16)
+ ; GFX1150-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[ANYEXT]]
+ ; GFX1150-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[AMDGPU_READANYLANE]](s32)
+ %1:_(s32) = COPY $sgpr0
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:_(s16) = G_FPTOUI_SAT %0(s16)
+...
+
---
name: sitofp_i32_to_f64
legalized: true
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