[llvm] [AMDGPU] Less-constrained scheduling for ASYNCMARK (PR #197638)

[Sameer Sahasrabuddhe via llvm-commits]

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@@ -11443,7 +11443,24 @@ void SIInstrInfo::enforceOperandRCAlignment(MachineInstr &MI,
   MI.addOperand(MachineOperand::CreateReg(NewVR, false, true));
 }
 
+bool SIInstrInfo::isAsyncLDSDMA(const MachineInstr &MI) const {
+  if (!isLDSDMA(MI))
+    return false;
+  if (usesASYNC_CNT(MI))
+    return true;
+  const MachineOperand *Async = getNamedOperand(MI, AMDGPU::OpName::IsAsync);
+  return Async && Async->getImm();
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ssahasra wrote:

> This isn't correct, there could be other async ops besides LDSDMA, hence that Async MO
This function body was simply moved from its existing place, but renamed incorrectly. It's not a new change in this PR. The function `isLDSDMA()` doesn't actually mean what it says. When we pile on more things like laneshared registers, we will have to refactor that function. But at its own level, `isAsync()` is doing the right thing and should retain its current name. See the edit that I suggested below.

https://github.com/llvm/llvm-project/pull/197638