[llvm] c897de2 - [AMDGPU] Add VIMAGE and VSAMPLE encodings for gfx13 (#197011)
via llvm-commits
llvm-commits at lists.llvm.org
Wed May 13 07:10:21 PDT 2026
Author: Mariusz Sikora
Date: 2026-05-13T16:10:14+02:00
New Revision: c897de2f003b8ea147924998e0085d5d43e2b0c0
URL: https://github.com/llvm/llvm-project/commit/c897de2f003b8ea147924998e0085d5d43e2b0c0
DIFF: https://github.com/llvm/llvm-project/commit/c897de2f003b8ea147924998e0085d5d43e2b0c0.diff
LOG: [AMDGPU] Add VIMAGE and VSAMPLE encodings for gfx13 (#197011)
Added:
llvm/test/MC/AMDGPU/gfx13_asm_vimage.s
llvm/test/MC/AMDGPU/gfx13_asm_vimage_alias.s
llvm/test/MC/AMDGPU/gfx13_asm_vsample.s
Modified:
llvm/lib/Target/AMDGPU/AMDGPU.td
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
llvm/lib/Target/AMDGPU/MIMGInstructions.td
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.flt.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.pk.add.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.d16.dim.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.d16.dim.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.dim.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.getlod.dim.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index e75c5fdbf4ebc..261c3dd6c6123 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1558,6 +1558,7 @@ def FeatureGFX13 : GCNSubtargetFeatureGeneration<"GFX13",
FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
FeatureA16, FeatureFastDenormalF32, FeatureG16,
FeatureUnalignedBufferAccess, FeatureUnalignedScratchAccess, FeatureImageInsts,
+ FeatureExtendedImageInsts,
FeatureUnalignedDSAccess, FeatureTrue16BitInsts,
FeatureDefaultComponentBroadcast, FeatureMaxHardClauseLength32,
FeatureAtomicFMinFMaxF32GlobalInsts, FeatureAtomicFMinFMaxF32FlatInsts,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 8568bc94361b2..9297c42754d17 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -2089,6 +2089,7 @@ bool AMDGPUInstructionSelector::selectImageIntrinsic(
const bool IsGFX10Plus = AMDGPU::isGFX10Plus(STI);
const bool IsGFX11Plus = AMDGPU::isGFX11Plus(STI);
const bool IsGFX12Plus = AMDGPU::isGFX12Plus(STI);
+ const bool IsGFX13Plus = AMDGPU::isGFX13Plus(STI);
const unsigned ArgOffset = MI.getNumExplicitDefs() + 1;
@@ -2214,7 +2215,10 @@ bool AMDGPUInstructionSelector::selectImageIntrinsic(
++NumVDataDwords;
int Opcode = -1;
- if (IsGFX12Plus) {
+ if (IsGFX13Plus) {
+ Opcode = AMDGPU::getMIMGOpcode(IntrOpcode, AMDGPU::MIMGEncGfx13,
+ NumVDataDwords, NumVAddrDwords);
+ } else if (IsGFX12Plus) {
Opcode = AMDGPU::getMIMGOpcode(IntrOpcode, AMDGPU::MIMGEncGfx12,
NumVDataDwords, NumVAddrDwords);
} else if (IsGFX11Plus) {
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index d46d11220bbe1..ea928386b80c6 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -1332,7 +1332,8 @@ void AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
// VIMAGE insts other than BVH never use vaddr4.
IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA ||
Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA ||
- Info->MIMGEncoding == AMDGPU::MIMGEncGfx12;
+ Info->MIMGEncoding == AMDGPU::MIMGEncGfx12 ||
+ Info->MIMGEncoding == AMDGPU::MIMGEncGfx13;
if (!IsNSA) {
if (!IsVSample && AddrSize > 12)
AddrSize = 16;
diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
index c8e698882ed28..0f31697f15688 100644
--- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -27,6 +27,7 @@ def MIMGEncGfx10NSA : MIMGEncoding;
def MIMGEncGfx11Default : MIMGEncoding;
def MIMGEncGfx11NSA : MIMGEncoding;
def MIMGEncGfx12 : MIMGEncoding;
+def MIMGEncGfx13 : MIMGEncoding;
def MIMGEncoding : GenericEnum {
let FilterClass = "MIMGEncoding";
@@ -100,12 +101,14 @@ def MIMG {
int NOP = -1;
}
-class mimgopc <int gfx12, int gfx11, int gfx10m, int vi = gfx10m, int si = gfx10m> {
+class mimgopc <int gfx13, int gfx12, int gfx11, int gfx10m, int vi = gfx10m, int si = gfx10m> {
+ field bits<8> GFX13 = gfx13;
field bits<8> GFX12 = gfx12;
field bits<8> GFX11 = gfx11;
field bits<8> GFX10M = gfx10m; // GFX10minus for all but atomics
field bits<8> VI = vi; // VI is only used for atomic/sampler/gather instructions
field bits<8> SI = si; // SI is only used for atomic instructions
+ bit HAS_GFX13 = !ne(gfx13, MIMG.NOP);
bit HAS_GFX12 = !ne(gfx12, MIMG.NOP);
bit HAS_GFX11 = !ne(gfx11, MIMG.NOP);
bit HAS_GFX10M = !ne(gfx10m, MIMG.NOP);
@@ -226,16 +229,6 @@ class MIMG <dag outs, string dns = "">
bits<8> VAddrOperands;
}
-class VIMAGE <dag outs, string dns = ""> : MIMG<outs, dns> {
- let MIMG = 0;
- let VIMAGE = 1;
-}
-
-class VSAMPLE <dag outs, string dns = ""> : MIMG<outs, dns> {
- let MIMG = 0;
- let VSAMPLE = 1;
-}
-
def MIMGInfoTable : GenericTable {
let FilterClass = "MIMG";
let CppTypeName = "MIMGInfo";
@@ -381,13 +374,15 @@ class MIMG_nsa_gfx11<int op, dag outs, int num_addrs, string dns="",
let nsa = nsah.NSA;
}
-class VIMAGE_gfx12<int op, dag outs, int num_addrs, string dns="",
- list<RegisterOperand> addr_types=[]>
- : VIMAGE<outs, dns>, VIMAGEe<op> {
- let SubtargetPredicate = isGFX12Plus;
- let AssemblerPredicate = isGFX12Plus;
+class VIMAGE<int op, dag outs, int num_addrs, Predicate pred,
+ MIMGEncoding encoding, string dns="", list<RegisterOperand> addr_types=[]>
+ : MIMG<outs, dns>, VIMAGEe<op> {
+ let MIMG = 0;
+ let VIMAGE = 1;
+ let SubtargetPredicate = pred;
+ let AssemblerPredicate = pred;
- let MIMGEncoding = MIMGEncGfx12;
+ let MIMGEncoding = encoding;
let VAddrOperands = num_addrs;
MIMGNSAHelper nsah = !if(!empty(addr_types),
@@ -403,13 +398,15 @@ class VIMAGE_gfx12<int op, dag outs, int num_addrs, string dns="",
let vaddr4 = !if(!lt(num_addrs, 5), 0, ?);
}
-class VSAMPLE_gfx12<int op, dag outs, int num_addrs, string dns="",
- RegisterOperand Addr3RC>
- : VSAMPLE<outs, dns>, VSAMPLEe<op> {
- let SubtargetPredicate = isGFX12Plus;
- let AssemblerPredicate = isGFX12Plus;
+class VSAMPLE<int op, dag outs, int num_addrs, Predicate pred,
+ MIMGEncoding encoding, string dns="", RegisterOperand Addr3RC>
+ : MIMG<outs, dns>, VSAMPLEe<op> {
+ let MIMG = 0;
+ let VSAMPLE = 1;
+ let SubtargetPredicate = pred;
+ let AssemblerPredicate = pred;
- let MIMGEncoding = MIMGEncGfx12;
+ let MIMGEncoding = encoding;
let VAddrOperands = num_addrs;
PartialNSAHelper nsah = PartialNSAHelper<num_addrs, 4, Addr3RC>;
@@ -499,10 +496,9 @@ class MIMG_NoSampler_nsa_gfx11<mimgopc op, string opcode,
#!if(BaseOpcode.HasD16, "$d16", "");
}
-class VIMAGE_NoSampler_gfx12<mimgopc op, string opcode,
- RegisterOperand DataRC, int num_addrs,
- string dns="">
- : VIMAGE_gfx12<op.GFX12, (outs DataRC:$vdata), num_addrs, dns> {
+class VIMAGE_NoSampler<int op, string opcode, RegisterOperand DataRC,
+ int num_addrs, GFXGen gfxGen, MIMGEncoding encoding, bit enableDisasm>
+ : VIMAGE<op, (outs DataRC:$vdata), num_addrs, gfxGen.AssemblerPredicate, encoding, !if(enableDisasm, gfxGen.DecoderNamespace, "")> {
let InOperandList = !con(AddrIns,
(ins SReg_256_XNULL:$rsrc, DMask:$dmask, Dim:$dim,
CPol:$cpol, R128A16:$r128, A16:$a16, TFE:$tfe),
@@ -511,10 +507,20 @@ class VIMAGE_NoSampler_gfx12<mimgopc op, string opcode,
#!if(BaseOpcode.HasD16, "$d16", "");
}
-class VSAMPLE_Sampler_gfx12<mimgopc op, string opcode, RegisterOperand DataRC,
- int num_addrs, RegisterOperand Addr3RC = VGPROp_32,
- string dns="">
- : VSAMPLE_gfx12<op.GFX12, (outs DataRC:$vdata), num_addrs, dns, Addr3RC> {
+class VIMAGE_NoSampler_gfx12<mimgopc op, string opcode,
+ RegisterOperand DataRC, int num_addrs,
+ bit enableDisasm=0>
+ : VIMAGE_NoSampler<op.GFX12, opcode, DataRC, num_addrs, GFX12Gen, MIMGEncGfx12, enableDisasm>;
+
+class VIMAGE_NoSampler_gfx13<mimgopc op, string opcode,
+ RegisterOperand DataRC, int num_addrs,
+ bit enableDisasm=0>
+ : VIMAGE_NoSampler<op.GFX13, opcode, DataRC, num_addrs, GFX13Gen, MIMGEncGfx13, enableDisasm>;
+
+class VSAMPLE_Sampler<int op, string opcode, RegisterOperand DataRC,
+ int num_addrs, GFXGen gfxGen, MIMGEncoding enc, RegisterOperand Addr3RC = VGPROp_32,
+ bit enableDisasm=0>
+ : VSAMPLE<op, (outs DataRC:$vdata), num_addrs, gfxGen.AssemblerPredicate, enc, !if(enableDisasm, gfxGen.DecoderNamespace, ""), Addr3RC> {
let InOperandList = !con(AddrIns,
(ins SReg_256_XNULL:$rsrc),
!if(BaseOpcode.Sampler, (ins SReg_128_XNULL:$samp), (ins)),
@@ -528,10 +534,19 @@ class VSAMPLE_Sampler_gfx12<mimgopc op, string opcode, RegisterOperand DataRC,
#!if(BaseOpcode.HasD16, "$d16", "");
}
-class VSAMPLE_Sampler_nortn_gfx12<mimgopc op, string opcode,
+class VSAMPLE_Sampler_gfx12<mimgopc op, string opcode, RegisterOperand DataRC,
int num_addrs, RegisterOperand Addr3RC = VGPROp_32,
- string dns="">
- : VSAMPLE_gfx12<op.GFX12, (outs), num_addrs, dns, Addr3RC> {
+ bit enableDisasm=0>
+ : VSAMPLE_Sampler<op.GFX12, opcode, DataRC, num_addrs, GFX12Gen, MIMGEncGfx12, Addr3RC, enableDisasm>;
+
+class VSAMPLE_Sampler_gfx13<mimgopc op, string opcode, RegisterOperand DataRC,
+ int num_addrs, RegisterOperand Addr3RC = VGPROp_32_Lo256,
+ bit enableDisasm=0>
+ : VSAMPLE_Sampler<op.GFX13, opcode, DataRC, num_addrs, GFX13Gen, MIMGEncGfx13, Addr3RC, enableDisasm>;
+
+class VSAMPLE_Sampler_nortn<int op, string opcode, GFXGen gfxGen, MIMGEncoding enc, int num_addrs,
+ RegisterOperand Addr3RC = VGPROp_32, bit enableDisasm=0>
+ : VSAMPLE<op, (outs), num_addrs, gfxGen.AssemblerPredicate, enc, !if(enableDisasm, gfxGen.DecoderNamespace, ""), Addr3RC> {
let InOperandList = !con(AddrIns,
(ins SReg_256_XNULL:$rsrc),
!if(BaseOpcode.Sampler, (ins SReg_128_XNULL:$samp), (ins)),
@@ -547,6 +562,16 @@ class VSAMPLE_Sampler_nortn_gfx12<mimgopc op, string opcode,
let vdata = 0;
}
+class VSAMPLE_Sampler_nortn_gfx12<mimgopc op, string opcode,
+ int num_addrs, RegisterOperand Addr3RC = VGPROp_32,
+ bit enableDisasm=0>
+ : VSAMPLE_Sampler_nortn<op.GFX12, opcode, GFX12Gen, MIMGEncGfx12, num_addrs, Addr3RC, enableDisasm>;
+
+class VSAMPLE_Sampler_nortn_gfx13<mimgopc op, string opcode,
+ int num_addrs, RegisterOperand Addr3RC = VGPROp_32_Lo256,
+ bit enableDisasm=0>
+ : VSAMPLE_Sampler_nortn<op.GFX13, opcode, GFX13Gen, MIMGEncGfx13, num_addrs, Addr3RC, enableDisasm>;
+
multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
RegisterOperand dst_rc, bit enableDisasm,
bit ExtendedImageInst = 1,
@@ -576,6 +601,15 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
def _V1_gfx12 : VIMAGE_NoSampler_gfx12<op, asm, dst_rc, 1>;
}
}
+ if op.HAS_GFX13 then {
+ if isVSample then {
+ let samp = 0 in
+ def _V1_gfx13 : VSAMPLE_Sampler_gfx13<op, asm, dst_rc, 1>;
+ }
+ else {
+ def _V1_gfx13 : VIMAGE_NoSampler_gfx13<op, asm, dst_rc, 1>;
+ }
+ }
}
let VAddrDwords = 2 in {
let ssamp = 0 in {
@@ -600,6 +634,15 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
def _V2_gfx12 : VIMAGE_NoSampler_gfx12<op, asm, dst_rc, 2>;
}
}
+ if op.HAS_GFX13 then {
+ if isVSample then {
+ let samp = 0 in
+ def _V2_gfx13 : VSAMPLE_Sampler_gfx13<op, asm, dst_rc, 2>;
+ }
+ else {
+ def _V2_gfx13 : VIMAGE_NoSampler_gfx13<op, asm, dst_rc, 2>;
+ }
+ }
}
let VAddrDwords = 3 in {
let ssamp = 0 in {
@@ -624,6 +667,15 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
def _V3_gfx12 : VIMAGE_NoSampler_gfx12<op, asm, dst_rc, 3>;
}
}
+ if op.HAS_GFX13 then {
+ if isVSample then {
+ let samp = 0 in
+ def _V3_gfx13 : VSAMPLE_Sampler_gfx13<op, asm, dst_rc, 3>;
+ }
+ else {
+ def _V3_gfx13 : VIMAGE_NoSampler_gfx13<op, asm, dst_rc, 3>;
+ }
+ }
}
let VAddrDwords = 4 in {
let ssamp = 0 in {
@@ -644,12 +696,19 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
if op.HAS_GFX12 then {
if isVSample then {
let samp = 0 in
- def _V4_gfx12 : VSAMPLE_Sampler_gfx12<op, asm, dst_rc, 4, VGPROp_32,
- !if(enableDisasm, "GFX12", "")>;
+ def _V4_gfx12 : VSAMPLE_Sampler_gfx12<op, asm, dst_rc, 4, VGPROp_32, enableDisasm>;
+ }
+ else {
+ def _V4_gfx12 : VIMAGE_NoSampler_gfx12<op, asm, dst_rc, 4, enableDisasm>;
+ }
+ }
+ if op.HAS_GFX13 then {
+ if isVSample then {
+ let samp = 0 in
+ def _V4_gfx13 : VSAMPLE_Sampler_gfx13<op, asm, dst_rc, 4, VGPROp_32_Lo256, enableDisasm>;
}
else {
- def _V4_gfx12 : VIMAGE_NoSampler_gfx12<op, asm, dst_rc, 4,
- !if(enableDisasm, "GFX12", "")>;
+ def _V4_gfx13 : VIMAGE_NoSampler_gfx13<op, asm, dst_rc, 4, enableDisasm>;
}
}
}
@@ -759,10 +818,9 @@ class MIMG_Store_nsa_gfx11<mimgopc op, string opcode,
#!if(BaseOpcode.HasD16, "$d16", "");
}
-class VIMAGE_Store_gfx12<mimgopc op, string opcode,
- RegisterOperand DataRC, int num_addrs,
- string dns="">
- : VIMAGE_gfx12<op.GFX12, (outs), num_addrs, dns> {
+class VIMAGE_Store<int op, string opcode, RegisterOperand DataRC,
+ int num_addrs, GFXGen gfxGen, MIMGEncoding encoding, bit enableDisasm>
+ : VIMAGE<op, (outs), num_addrs, gfxGen.AssemblerPredicate, encoding, !if(enableDisasm, gfxGen.DecoderNamespace, "")> {
let InOperandList = !con((ins DataRC:$vdata),
AddrIns,
(ins SReg_256_XNULL:$rsrc, DMask:$dmask, Dim:$dim,
@@ -772,6 +830,16 @@ class VIMAGE_Store_gfx12<mimgopc op, string opcode,
#!if(BaseOpcode.HasD16, "$d16", "");
}
+class VIMAGE_Store_gfx12<mimgopc op, string opcode,
+ RegisterOperand DataRC, int num_addrs,
+ bit enableDisasm=0>
+ : VIMAGE_Store<op.GFX12, opcode, DataRC, num_addrs, GFX12Gen, MIMGEncGfx12, enableDisasm>;
+
+class VIMAGE_Store_gfx13<mimgopc op, string opcode,
+ RegisterOperand DataRC, int num_addrs,
+ bit enableDisasm=0>
+ : VIMAGE_Store<op.GFX13, opcode, DataRC, num_addrs, GFX13Gen, MIMGEncGfx13, enableDisasm>;
+
multiclass MIMG_Store_Addr_Helper <mimgopc op, string asm,
RegisterOperand data_rc,
bit enableDisasm> {
@@ -796,6 +864,9 @@ multiclass MIMG_Store_Addr_Helper <mimgopc op, string asm,
if op.HAS_GFX12 then {
def _V1_gfx12 : VIMAGE_Store_gfx12 <op, asm, data_rc, 1>;
}
+ if op.HAS_GFX13 then {
+ def _V1_gfx13 : VIMAGE_Store_gfx13 <op, asm, data_rc, 1>;
+ }
}
let VAddrDwords = 2 in {
let ssamp = 0 in {
@@ -813,6 +884,9 @@ multiclass MIMG_Store_Addr_Helper <mimgopc op, string asm,
if op.HAS_GFX12 then {
def _V2_gfx12 : VIMAGE_Store_gfx12 <op, asm, data_rc, 2>;
}
+ if op.HAS_GFX13 then {
+ def _V2_gfx13 : VIMAGE_Store_gfx13 <op, asm, data_rc, 2>;
+ }
}
let VAddrDwords = 3 in {
let ssamp = 0 in {
@@ -830,6 +904,9 @@ multiclass MIMG_Store_Addr_Helper <mimgopc op, string asm,
if op.HAS_GFX12 then {
def _V3_gfx12 : VIMAGE_Store_gfx12 <op, asm, data_rc, 3>;
}
+ if op.HAS_GFX13 then {
+ def _V3_gfx13 : VIMAGE_Store_gfx13 <op, asm, data_rc, 3>;
+ }
}
let VAddrDwords = 4 in {
let ssamp = 0 in {
@@ -847,8 +924,10 @@ multiclass MIMG_Store_Addr_Helper <mimgopc op, string asm,
}
}
if op.HAS_GFX12 then {
- def _V4_gfx12 : VIMAGE_Store_gfx12 <op, asm, data_rc, 4,
- !if(enableDisasm, "GFX12", "")>;
+ def _V4_gfx12 : VIMAGE_Store_gfx12 <op, asm, data_rc, 4, enableDisasm>;
+ }
+ if op.HAS_GFX13 then {
+ def _V4_gfx13 : VIMAGE_Store_gfx13 <op, asm, data_rc, 4, enableDisasm>;
}
}
}
@@ -976,10 +1055,9 @@ class MIMG_Atomic_nsa_gfx11<mimgopc op, string opcode,
let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe";
}
-class VIMAGE_Atomic_gfx12<mimgopc op, string opcode, RegisterOperand DataRC,
- int num_addrs, string renamed, bit noRtn = 0, bit enableDisasm = 0>
- : VIMAGE_gfx12<op.GFX12, !if(noRtn, (outs), (outs DataRC:$vdst)), num_addrs,
- !if(enableDisasm, "GFX12", "")> {
+class VIMAGE_Atomic<int op, string opcode, RegisterOperand DataRC,
+ int num_addrs, GFXGen gfxGen, MIMGEncoding encoding, string renamed, bit noRtn = 0, bit enableDisasm = 0>
+ : VIMAGE<op, !if(noRtn, (outs), (outs DataRC:$vdst)), num_addrs, gfxGen.AssemblerPredicate, encoding, !if(enableDisasm, gfxGen.DecoderNamespace, "")> {
let Constraints = !if(noRtn, "", "$vdst = $vdata");
let isCodeGenOnly = noRtn;
let InOperandList = !con((ins DataRC:$vdata),
@@ -990,6 +1068,16 @@ class VIMAGE_Atomic_gfx12<mimgopc op, string opcode, RegisterOperand DataRC,
", $rsrc$dmask$dim$cpol$r128$a16$tfe";
}
+class VIMAGE_Atomic_gfx12<mimgopc op, string opcode,
+ RegisterOperand DataRC, int num_addrs, string renamed,
+ bit noRtn = 0, bit enableDisasm=0>
+ : VIMAGE_Atomic<op.GFX12, opcode, DataRC, num_addrs, GFX12Gen, MIMGEncGfx12, renamed, noRtn, enableDisasm>;
+
+class VIMAGE_Atomic_gfx13<mimgopc op, string opcode,
+ RegisterOperand DataRC, int num_addrs, string renamed,
+ bit noRtn = 0, bit enableDisasm=0>
+ : VIMAGE_Atomic<op.GFX13, opcode, DataRC, num_addrs, GFX13Gen, MIMGEncGfx13, renamed, noRtn, enableDisasm>;
+
multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
RegisterOperand data_rc,
bit enableDasm = 0,
@@ -1019,6 +1107,9 @@ multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
if op.HAS_GFX12 then {
def _V1_gfx12 : VIMAGE_Atomic_gfx12 <op, asm, data_rc, 1, renamed, noRtn>;
}
+ if op.HAS_GFX13 then {
+ def _V1_gfx13 : VIMAGE_Atomic_gfx13 <op, asm, data_rc, 1, renamed, noRtn>;
+ }
}
let VAddrDwords = 2 in {
let ssamp = 0 in {
@@ -1041,6 +1132,9 @@ multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
if op.HAS_GFX12 then {
def _V2_gfx12 : VIMAGE_Atomic_gfx12 <op, asm, data_rc, 2, renamed, noRtn>;
}
+ if op.HAS_GFX13 then {
+ def _V2_gfx13 : VIMAGE_Atomic_gfx13 <op, asm, data_rc, 2, renamed, noRtn>;
+ }
}
let VAddrDwords = 3 in {
let ssamp = 0 in {
@@ -1063,6 +1157,9 @@ multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
if op.HAS_GFX12 then {
def _V3_gfx12 : VIMAGE_Atomic_gfx12 <op, asm, data_rc, 3, renamed, noRtn>;
}
+ if op.HAS_GFX13 then {
+ def _V3_gfx13 : VIMAGE_Atomic_gfx13 <op, asm, data_rc, 3, renamed, noRtn>;
+ }
}
let VAddrDwords = 4 in {
let ssamp = 0 in {
@@ -1085,6 +1182,9 @@ multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
if op.HAS_GFX12 then {
def _V4_gfx12 : VIMAGE_Atomic_gfx12 <op, asm, data_rc, 4, renamed, noRtn, enableDasm>;
}
+ if op.HAS_GFX13 then {
+ def _V4_gfx13 : VIMAGE_Atomic_gfx13 <op, asm, data_rc, 4, renamed, noRtn, enableDasm>;
+ }
}
}
if !and(op.HAS_GFX12, !not(!empty(renamed))) then
@@ -1406,8 +1506,11 @@ multiclass MIMG_Sampler_Src_Helper <mimgopc op, string asm,
let VAddrDwords = addr.NumWords in {
if op.HAS_GFX12 then {
def _V # addr.NumWords # _gfx12
- : VSAMPLE_Sampler_gfx12<op, asm, dst_rc, addr.NumWords, addr.RegClass,
- !if(!and(enableDisasm, addr.Disassemble), "GFX12", "")>;
+ : VSAMPLE_Sampler_gfx12<op, asm, dst_rc, addr.NumWords, addr.RegClass, !and(enableDisasm, addr.Disassemble)>;
+ }
+ if op.HAS_GFX13 then {
+ def _V # addr.NumWords # _gfx13
+ : VSAMPLE_Sampler_gfx13<op, asm, dst_rc, addr.NumWords, addr.RegClass, !and(enableDisasm, addr.Disassemble)>;
}
}
}
@@ -1469,6 +1572,15 @@ multiclass MIMG_Sampler_NoReturn <mimgopc op, AMDGPUSampleVariant sample, bit wq
}
}
}
+
+ foreach addr = MIMG_Sampler_AddrSizes<sample, isG16, 4/*MaxNSASize*/, 1>.PartialNSAInstrs in {
+ let VAddrDwords = addr.NumWords in {
+ if op.HAS_GFX13 then {
+ def _V # addr.NumWords # _gfx13
+ : VSAMPLE_Sampler_nortn_gfx13<op, asm, addr.NumWords, addr.RegClass>;
+ }
+ }
+ }
}
}
@@ -1574,11 +1686,11 @@ class MIMG_IntersectRay_nsa_gfx11<mimgopc op, string opcode, int num_addrs,
class VIMAGE_IntersectRay_gfx12<mimgopc op, string opcode, int num_addrs,
bit isDual, bit isBVH8,
list<RegisterOperand> addr_types>
- : VIMAGE_gfx12<op.GFX12, !if(!or(isDual, isBVH8),
+ : VIMAGE<op.GFX12, !if(!or(isDual, isBVH8),
(outs VReg_320:$vdata, VReg_96:$ray_origin_out,
VReg_96:$ray_dir_out),
(outs VReg_128:$vdata)),
- num_addrs, "GFX12", addr_types> {
+ num_addrs, isGFX12Only, MIMGEncGfx12, "GFX12", addr_types> {
let Constraints = !if(!or(isDual, isBVH8),
"$ray_origin_out = $vaddr2, $ray_dir_out = $vaddr3", "");
let InOperandList = !con(nsah.AddrIns, (ins SReg_128_XNULL:$rsrc),
@@ -1662,155 +1774,155 @@ multiclass MIMG_MSAA_Load <mimgopc op, string asm> {
//===----------------------------------------------------------------------===//
let OtherPredicates = [HasImageInsts] in {
-defm IMAGE_LOAD : MIMG_NoSampler <mimgopc<0x00, 0x00, 0x00>, "image_load", 1>;
-defm IMAGE_LOAD_MIP : MIMG_NoSampler <mimgopc<0x01, 0x01, 0x01>, "image_load_mip", 1, 1>;
-defm IMAGE_LOAD_PCK : MIMG_NoSampler <mimgopc<0x02, 0x02, 0x02>, "image_load_pck", 0>;
-defm IMAGE_LOAD_PCK_SGN : MIMG_NoSampler <mimgopc<0x03, 0x03, 0x03>, "image_load_pck_sgn", 0>;
-defm IMAGE_LOAD_MIP_PCK : MIMG_NoSampler <mimgopc<0x04, 0x04, 0x04>, "image_load_mip_pck", 0, 1>;
-defm IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoSampler <mimgopc<0x05, 0x05, 0x05>, "image_load_mip_pck_sgn", 0, 1>;
-defm IMAGE_STORE : MIMG_Store <mimgopc<0x06, 0x06, 0x08>, "image_store", 1>;
-defm IMAGE_STORE_MIP : MIMG_Store <mimgopc<0x07, 0x07, 0x09>, "image_store_mip", 1, 1>;
-defm IMAGE_STORE_PCK : MIMG_Store <mimgopc<0x08, 0x08, 0x0a>, "image_store_pck", 0>;
-defm IMAGE_STORE_MIP_PCK : MIMG_Store <mimgopc<0x09, 0x09, 0x0b>, "image_store_mip_pck", 0, 1>;
-
-defm IMAGE_GET_RESINFO : MIMG_NoSampler <mimgopc<0x17, 0x17, 0x0e, 0x0e, 0x0e>, "image_get_resinfo", 0, 1, 1>;
-
-defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimgopc<0x0a, 0x0a, 0x0f, 0x10, 0x0f>, "image_atomic_swap">;
-defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimgopc<0x0b, 0x0b, 0x10, 0x11, 0x10>, "image_atomic_cmpswap", 1>;
-defm IMAGE_ATOMIC_ADD : MIMG_Atomic_Renamed <mimgopc<0x0c, 0x0c, 0x11, 0x12, 0x11>, "image_atomic_add", "image_atomic_add_uint">;
-defm IMAGE_ATOMIC_SUB : MIMG_Atomic_Renamed <mimgopc<0x0d, 0x0d, 0x12, 0x13, 0x12>, "image_atomic_sub", "image_atomic_sub_uint">;
-defm IMAGE_ATOMIC_RSUB : MIMG_Atomic <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x13>, "image_atomic_rsub">;
-defm IMAGE_ATOMIC_SMIN : MIMG_Atomic_Renamed <mimgopc<0x0e, 0x0e, 0x14>, "image_atomic_smin", "image_atomic_min_int">;
-defm IMAGE_ATOMIC_UMIN : MIMG_Atomic_Renamed <mimgopc<0x0f, 0x0f, 0x15>, "image_atomic_umin", "image_atomic_min_uint">;
-defm IMAGE_ATOMIC_SMAX : MIMG_Atomic_Renamed <mimgopc<0x10, 0x10, 0x16>, "image_atomic_smax", "image_atomic_max_int">;
-defm IMAGE_ATOMIC_UMAX : MIMG_Atomic_Renamed <mimgopc<0x11, 0x11, 0x17>, "image_atomic_umax", "image_atomic_max_uint">;
-defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimgopc<0x12, 0x12, 0x18>, "image_atomic_and">;
-defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimgopc<0x13, 0x13, 0x19>, "image_atomic_or">;
-defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimgopc<0x14, 0x14, 0x1a>, "image_atomic_xor">;
-defm IMAGE_ATOMIC_INC : MIMG_Atomic_Renamed <mimgopc<0x15, 0x15, 0x1b>, "image_atomic_inc", "image_atomic_inc_uint">;
-defm IMAGE_ATOMIC_DEC : MIMG_Atomic_Renamed <mimgopc<0x16, 0x16, 0x1c>, "image_atomic_dec", "image_atomic_dec_uint">;
-defm IMAGE_ATOMIC_FCMPSWAP : MIMG_Atomic <mimgopc<MIMG.NOP, MIMG.NOP, 0x1d, MIMG.NOP>, "image_atomic_fcmpswap", 1, 1>;
-defm IMAGE_ATOMIC_FMIN : MIMG_Atomic <mimgopc<MIMG.NOP, MIMG.NOP, 0x1e, MIMG.NOP>, "image_atomic_fmin", 0, 1>;
-defm IMAGE_ATOMIC_FMAX : MIMG_Atomic <mimgopc<MIMG.NOP, MIMG.NOP, 0x1f, MIMG.NOP>, "image_atomic_fmax", 0, 1>;
-defm IMAGE_ATOMIC_PK_ADD_F16 : MIMG_Atomic <mimgopc<0x86, MIMG.NOP, MIMG.NOP, MIMG.NOP, MIMG.NOP>, "image_atomic_pk_add_f16", 0, 1>;
-defm IMAGE_ATOMIC_PK_ADD_BF16 : MIMG_Atomic <mimgopc<0x87, MIMG.NOP, MIMG.NOP, MIMG.NOP, MIMG.NOP>, "image_atomic_pk_add_bf16", 0, 1>;
-defm IMAGE_ATOMIC_ADD_FLT : MIMG_Atomic <mimgopc<0x83, MIMG.NOP, MIMG.NOP, MIMG.NOP>, "image_atomic_add_flt", 0, 1>;
-defm IMAGE_ATOMIC_MIN_FLT : MIMG_Atomic <mimgopc<0x84, MIMG.NOP, MIMG.NOP, MIMG.NOP>, "image_atomic_min_num_flt", 0, 1, "image_atomic_min_flt">;
-defm IMAGE_ATOMIC_MAX_FLT : MIMG_Atomic <mimgopc<0x85, MIMG.NOP, MIMG.NOP, MIMG.NOP>, "image_atomic_max_num_flt", 0, 1, "image_atomic_max_flt">;
+defm IMAGE_LOAD : MIMG_NoSampler <mimgopc<0x00, 0x00, 0x00, 0x00>, "image_load", 1>;
+defm IMAGE_LOAD_MIP : MIMG_NoSampler <mimgopc<0x01, 0x01, 0x01, 0x01>, "image_load_mip", 1, 1>;
+defm IMAGE_LOAD_PCK : MIMG_NoSampler <mimgopc<0x02, 0x02, 0x02, 0x02>, "image_load_pck", 0>;
+defm IMAGE_LOAD_PCK_SGN : MIMG_NoSampler <mimgopc<0x03, 0x03, 0x03, 0x03>, "image_load_pck_sgn", 0>;
+defm IMAGE_LOAD_MIP_PCK : MIMG_NoSampler <mimgopc<0x04, 0x04, 0x04, 0x04>, "image_load_mip_pck", 0, 1>;
+defm IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoSampler <mimgopc<0x05, 0x05, 0x05, 0x05>, "image_load_mip_pck_sgn", 0, 1>;
+defm IMAGE_STORE : MIMG_Store <mimgopc<0x08, 0x06, 0x06, 0x08>, "image_store", 1>;
+defm IMAGE_STORE_MIP : MIMG_Store <mimgopc<0x09, 0x07, 0x07, 0x09>, "image_store_mip", 1, 1>;
+defm IMAGE_STORE_PCK : MIMG_Store <mimgopc<0x0a, 0x08, 0x08, 0x0a>, "image_store_pck", 0>;
+defm IMAGE_STORE_MIP_PCK : MIMG_Store <mimgopc<0x0b, 0x09, 0x09, 0x0b>, "image_store_mip_pck", 0, 1>;
+
+defm IMAGE_GET_RESINFO : MIMG_NoSampler <mimgopc<0x0e, 0x17, 0x17, 0x0e, 0x0e, 0x0e>, "image_get_resinfo", 0, 1, 1>;
+
+defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimgopc<0x0f, 0x0a, 0x0a, 0x0f, 0x10, 0x0f>, "image_atomic_swap">;
+defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimgopc<0x10, 0x0b, 0x0b, 0x10, 0x11, 0x10>, "image_atomic_cmpswap", 1>;
+defm IMAGE_ATOMIC_ADD : MIMG_Atomic_Renamed <mimgopc<0x11, 0x0c, 0x0c, 0x11, 0x12, 0x11>, "image_atomic_add", "image_atomic_add_uint">;
+defm IMAGE_ATOMIC_SUB : MIMG_Atomic_Renamed <mimgopc<0x12, 0x0d, 0x0d, 0x12, 0x13, 0x12>, "image_atomic_sub", "image_atomic_sub_uint">;
+defm IMAGE_ATOMIC_RSUB : MIMG_Atomic <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x13>, "image_atomic_rsub">;
+defm IMAGE_ATOMIC_SMIN : MIMG_Atomic_Renamed <mimgopc<0x14, 0x0e, 0x0e, 0x14>, "image_atomic_smin", "image_atomic_min_int">;
+defm IMAGE_ATOMIC_UMIN : MIMG_Atomic_Renamed <mimgopc<0x15, 0x0f, 0x0f, 0x15>, "image_atomic_umin", "image_atomic_min_uint">;
+defm IMAGE_ATOMIC_SMAX : MIMG_Atomic_Renamed <mimgopc<0x16, 0x10, 0x10, 0x16>, "image_atomic_smax", "image_atomic_max_int">;
+defm IMAGE_ATOMIC_UMAX : MIMG_Atomic_Renamed <mimgopc<0x17, 0x11, 0x11, 0x17>, "image_atomic_umax", "image_atomic_max_uint">;
+defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimgopc<0x18, 0x12, 0x12, 0x18>, "image_atomic_and">;
+defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimgopc<0x19, 0x13, 0x13, 0x19>, "image_atomic_or">;
+defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimgopc<0x1a, 0x14, 0x14, 0x1a>, "image_atomic_xor">;
+defm IMAGE_ATOMIC_INC : MIMG_Atomic_Renamed <mimgopc<0x1b, 0x15, 0x15, 0x1b>, "image_atomic_inc", "image_atomic_inc_uint">;
+defm IMAGE_ATOMIC_DEC : MIMG_Atomic_Renamed <mimgopc<0x1c, 0x16, 0x16, 0x1c>, "image_atomic_dec", "image_atomic_dec_uint">;
+defm IMAGE_ATOMIC_FCMPSWAP : MIMG_Atomic <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x1d, MIMG.NOP>, "image_atomic_fcmpswap", 1, 1>;
+defm IMAGE_ATOMIC_FMIN : MIMG_Atomic <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x1e, MIMG.NOP>, "image_atomic_fmin", 0, 1>;
+defm IMAGE_ATOMIC_FMAX : MIMG_Atomic <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x1f, MIMG.NOP>, "image_atomic_fmax", 0, 1>;
+defm IMAGE_ATOMIC_PK_ADD_F16 : MIMG_Atomic <mimgopc<0x86, 0x86, MIMG.NOP, MIMG.NOP, MIMG.NOP, MIMG.NOP>, "image_atomic_pk_add_f16", 0, 1>;
+defm IMAGE_ATOMIC_PK_ADD_BF16 : MIMG_Atomic <mimgopc<0x87, 0x87, MIMG.NOP, MIMG.NOP, MIMG.NOP, MIMG.NOP>, "image_atomic_pk_add_bf16", 0, 1>;
+defm IMAGE_ATOMIC_ADD_FLT : MIMG_Atomic <mimgopc<0x83, 0x83, MIMG.NOP, MIMG.NOP, MIMG.NOP>, "image_atomic_add_flt", 0, 1>;
+defm IMAGE_ATOMIC_MIN_FLT : MIMG_Atomic <mimgopc<0x1e, 0x84, MIMG.NOP, MIMG.NOP, MIMG.NOP>, "image_atomic_min_num_flt", 0, 1, "image_atomic_min_flt">;
+defm IMAGE_ATOMIC_MAX_FLT : MIMG_Atomic <mimgopc<0x1f, 0x85, MIMG.NOP, MIMG.NOP, MIMG.NOP>, "image_atomic_max_num_flt", 0, 1, "image_atomic_max_flt">;
let AssemblerPredicate = isGFX12Plus in {
def : AMDGPUMnemonicAlias<"image_atomic_fmin", "image_atomic_min_flt">;
def : AMDGPUMnemonicAlias<"image_atomic_fmax", "image_atomic_max_flt">;
}
-defm IMAGE_SAMPLE : MIMG_Sampler_WQM <mimgopc<0x1b, 0x1b, 0x20>, AMDGPUSample, 1>;
+defm IMAGE_SAMPLE : MIMG_Sampler_WQM <mimgopc<0x20, 0x1b, 0x1b, 0x20>, AMDGPUSample, 1>;
let OtherPredicates = [HasImageInsts, HasExtendedImageInsts] in {
-defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <mimgopc<0x40, 0x40, 0x21>, AMDGPUSample_cl>;
-defm IMAGE_SAMPLE_D : MIMG_Sampler <mimgopc<0x1c, 0x1c, 0x22>, AMDGPUSample_d>;
-defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <mimgopc<0x41, 0x41, 0x23>, AMDGPUSample_d_cl>;
-defm IMAGE_SAMPLE_L : MIMG_Sampler <mimgopc<0x1d, 0x1d, 0x24>, AMDGPUSample_l, 1>;
-defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <mimgopc<0x1e, 0x1e, 0x25>, AMDGPUSample_b>;
-defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <mimgopc<0x42, 0x42, 0x26>, AMDGPUSample_b_cl>;
-defm IMAGE_SAMPLE_LZ : MIMG_Sampler <mimgopc<0x1f, 0x1f, 0x27>, AMDGPUSample_lz, 1>;
-defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <mimgopc<0x20, 0x20, 0x28>, AMDGPUSample_c>;
-defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <mimgopc<0x43, 0x43, 0x29>, AMDGPUSample_c_cl>;
-defm IMAGE_SAMPLE_C_D : MIMG_Sampler <mimgopc<0x21, 0x21, 0x2a>, AMDGPUSample_c_d>;
-defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <mimgopc<0x44, 0x44, 0x2b>, AMDGPUSample_c_d_cl>;
-defm IMAGE_SAMPLE_C_L : MIMG_Sampler <mimgopc<0x22, 0x22, 0x2c>, AMDGPUSample_c_l>;
-defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <mimgopc<0x23, 0x23, 0x2d>, AMDGPUSample_c_b>;
-defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <mimgopc<0x45, 0x45, 0x2e>, AMDGPUSample_c_b_cl>;
-defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <mimgopc<0x24, 0x24, 0x2f>, AMDGPUSample_c_lz>;
-defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <mimgopc<0x25, 0x25, 0x30>, AMDGPUSample_o>;
-defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <mimgopc<0x46, 0x46, 0x31>, AMDGPUSample_cl_o>;
-defm IMAGE_SAMPLE_D_O : MIMG_Sampler <mimgopc<0x26, 0x26, 0x32>, AMDGPUSample_d_o>;
-defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <mimgopc<0x47, 0x47, 0x33>, AMDGPUSample_d_cl_o>;
-defm IMAGE_SAMPLE_L_O : MIMG_Sampler <mimgopc<0x27, 0x27, 0x34>, AMDGPUSample_l_o>;
-defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <mimgopc<0x28, 0x28, 0x35>, AMDGPUSample_b_o>;
-defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <mimgopc<0x48, 0x48, 0x36>, AMDGPUSample_b_cl_o>;
-defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <mimgopc<0x29, 0x29, 0x37>, AMDGPUSample_lz_o>;
-defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <mimgopc<0x2a, 0x2a, 0x38>, AMDGPUSample_c_o>;
-defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <mimgopc<0x49, 0x49, 0x39>, AMDGPUSample_c_cl_o>;
-defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <mimgopc<0x2b, 0x2b, 0x3a>, AMDGPUSample_c_d_o>;
-defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <mimgopc<0x4a, 0x4a, 0x3b>, AMDGPUSample_c_d_cl_o>;
-defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <mimgopc<0x2c, 0x2c, 0x3c>, AMDGPUSample_c_l_o>;
-defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <mimgopc<0x4b, 0x4b, 0x3e>, AMDGPUSample_c_b_cl_o>;
-defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <mimgopc<0x2d, 0x2d, 0x3d>, AMDGPUSample_c_b_o>;
-defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <mimgopc<0x2e, 0x2e, 0x3f>, AMDGPUSample_c_lz_o>;
-defm IMAGE_GATHER4 : MIMG_Gather_WQM <mimgopc<0x2f, 0x2f, 0x40>, AMDGPUSample>;
-defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <mimgopc<0x60, 0x60, 0x41>, AMDGPUSample_cl>;
-defm IMAGE_GATHER4_L : MIMG_Gather <mimgopc<0x30, 0x30, 0x44>, AMDGPUSample_l>;
-defm IMAGE_GATHER4_B : MIMG_Gather_WQM <mimgopc<0x31, 0x31, 0x45>, AMDGPUSample_b>;
-defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <mimgopc<0x61, 0x61, 0x46>, AMDGPUSample_b_cl>;
-defm IMAGE_GATHER4_LZ : MIMG_Gather <mimgopc<0x32, 0x32, 0x47>, AMDGPUSample_lz>;
-defm IMAGE_GATHER4_C : MIMG_Gather_WQM <mimgopc<0x33, 0x33, 0x48>, AMDGPUSample_c>;
-defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <mimgopc<0x62, 0x62, 0x49>, AMDGPUSample_c_cl>;
-defm IMAGE_GATHER4_C_L : MIMG_Gather <mimgopc<0x63, 0x63, 0x4c>, AMDGPUSample_c_l>;
-defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <mimgopc<0x64, 0x64, 0x4d>, AMDGPUSample_c_b>;
-defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <mimgopc<0x65, 0x65, 0x4e>, AMDGPUSample_c_b_cl>;
-defm IMAGE_GATHER4_C_LZ : MIMG_Gather <mimgopc<0x34, 0x34, 0x4f>, AMDGPUSample_c_lz>;
-defm IMAGE_GATHER4_O : MIMG_Gather_WQM <mimgopc<0x35, 0x35, 0x50>, AMDGPUSample_o>;
-defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <mimgopc<MIMG.NOP, MIMG.NOP, 0x51>, AMDGPUSample_cl_o>;
-defm IMAGE_GATHER4_L_O : MIMG_Gather <mimgopc<MIMG.NOP, MIMG.NOP, 0x54>, AMDGPUSample_l_o>;
-defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <mimgopc<MIMG.NOP, MIMG.NOP, 0x55>, AMDGPUSample_b_o>;
-defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <mimgopc<MIMG.NOP, MIMG.NOP, 0x56>, AMDGPUSample_b_cl_o>;
-defm IMAGE_GATHER4_LZ_O : MIMG_Gather <mimgopc<0x36, 0x36, 0x57>, AMDGPUSample_lz_o>;
-defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <mimgopc<MIMG.NOP, MIMG.NOP, 0x58>, AMDGPUSample_c_o>;
-defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <mimgopc<MIMG.NOP, MIMG.NOP, 0x59>, AMDGPUSample_c_cl_o>;
-defm IMAGE_GATHER4_C_L_O : MIMG_Gather <mimgopc<MIMG.NOP, MIMG.NOP, 0x5c>, AMDGPUSample_c_l_o>;
-defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <mimgopc<MIMG.NOP, MIMG.NOP, 0x5d>, AMDGPUSample_c_b_o>;
-defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <mimgopc<MIMG.NOP, MIMG.NOP, 0x5e>, AMDGPUSample_c_b_cl_o>;
-defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <mimgopc<0x37, 0x37, 0x5f>, AMDGPUSample_c_lz_o>;
+defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <mimgopc<0x21, 0x40, 0x40, 0x21>, AMDGPUSample_cl>;
+defm IMAGE_SAMPLE_D : MIMG_Sampler <mimgopc<0x22, 0x1c, 0x1c, 0x22>, AMDGPUSample_d>;
+defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <mimgopc<0x23, 0x41, 0x41, 0x23>, AMDGPUSample_d_cl>;
+defm IMAGE_SAMPLE_L : MIMG_Sampler <mimgopc<0x24, 0x1d, 0x1d, 0x24>, AMDGPUSample_l, 1>;
+defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <mimgopc<0x25, 0x1e, 0x1e, 0x25>, AMDGPUSample_b>;
+defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <mimgopc<0x26, 0x42, 0x42, 0x26>, AMDGPUSample_b_cl>;
+defm IMAGE_SAMPLE_LZ : MIMG_Sampler <mimgopc<0x27, 0x1f, 0x1f, 0x27>, AMDGPUSample_lz, 1>;
+defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <mimgopc<0x28, 0x20, 0x20, 0x28>, AMDGPUSample_c>;
+defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <mimgopc<0x29, 0x43, 0x43, 0x29>, AMDGPUSample_c_cl>;
+defm IMAGE_SAMPLE_C_D : MIMG_Sampler <mimgopc<0x2a, 0x21, 0x21, 0x2a>, AMDGPUSample_c_d>;
+defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <mimgopc<0x2b, 0x44, 0x44, 0x2b>, AMDGPUSample_c_d_cl>;
+defm IMAGE_SAMPLE_C_L : MIMG_Sampler <mimgopc<0x2c, 0x22, 0x22, 0x2c>, AMDGPUSample_c_l>;
+defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <mimgopc<0x2d, 0x23, 0x23, 0x2d>, AMDGPUSample_c_b>;
+defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <mimgopc<0x2e, 0x45, 0x45, 0x2e>, AMDGPUSample_c_b_cl>;
+defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <mimgopc<0x2f, 0x24, 0x24, 0x2f>, AMDGPUSample_c_lz>;
+defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <mimgopc<0x30, 0x25, 0x25, 0x30>, AMDGPUSample_o>;
+defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <mimgopc<0x31, 0x46, 0x46, 0x31>, AMDGPUSample_cl_o>;
+defm IMAGE_SAMPLE_D_O : MIMG_Sampler <mimgopc<0x32, 0x26, 0x26, 0x32>, AMDGPUSample_d_o>;
+defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <mimgopc<0x33, 0x47, 0x47, 0x33>, AMDGPUSample_d_cl_o>;
+defm IMAGE_SAMPLE_L_O : MIMG_Sampler <mimgopc<0x34, 0x27, 0x27, 0x34>, AMDGPUSample_l_o>;
+defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <mimgopc<0x35, 0x28, 0x28, 0x35>, AMDGPUSample_b_o>;
+defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <mimgopc<0x36, 0x48, 0x48, 0x36>, AMDGPUSample_b_cl_o>;
+defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <mimgopc<0x37, 0x29, 0x29, 0x37>, AMDGPUSample_lz_o>;
+defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <mimgopc<0x38, 0x2a, 0x2a, 0x38>, AMDGPUSample_c_o>;
+defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <mimgopc<0x39, 0x49, 0x49, 0x39>, AMDGPUSample_c_cl_o>;
+defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <mimgopc<0x3a, 0x2b, 0x2b, 0x3a>, AMDGPUSample_c_d_o>;
+defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <mimgopc<0x3b, 0x4a, 0x4a, 0x3b>, AMDGPUSample_c_d_cl_o>;
+defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <mimgopc<0x3c, 0x2c, 0x2c, 0x3c>, AMDGPUSample_c_l_o>;
+defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <mimgopc<0x3e, 0x4b, 0x4b, 0x3e>, AMDGPUSample_c_b_cl_o>;
+defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <mimgopc<0x3d, 0x2d, 0x2d, 0x3d>, AMDGPUSample_c_b_o>;
+defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <mimgopc<0x3f, 0x2e, 0x2e, 0x3f>, AMDGPUSample_c_lz_o>;
+defm IMAGE_GATHER4 : MIMG_Gather_WQM <mimgopc<0x40, 0x2f, 0x2f, 0x40>, AMDGPUSample>;
+defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <mimgopc<0x41, 0x60, 0x60, 0x41>, AMDGPUSample_cl>;
+defm IMAGE_GATHER4_L : MIMG_Gather <mimgopc<0x44, 0x30, 0x30, 0x44>, AMDGPUSample_l>;
+defm IMAGE_GATHER4_B : MIMG_Gather_WQM <mimgopc<0x45, 0x31, 0x31, 0x45>, AMDGPUSample_b>;
+defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <mimgopc<0x46, 0x61, 0x61, 0x46>, AMDGPUSample_b_cl>;
+defm IMAGE_GATHER4_LZ : MIMG_Gather <mimgopc<0x47, 0x32, 0x32, 0x47>, AMDGPUSample_lz>;
+defm IMAGE_GATHER4_C : MIMG_Gather_WQM <mimgopc<0x48, 0x33, 0x33, 0x48>, AMDGPUSample_c>;
+defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <mimgopc<0x49, 0x62, 0x62, 0x49>, AMDGPUSample_c_cl>;
+defm IMAGE_GATHER4_C_L : MIMG_Gather <mimgopc<0x4c, 0x63, 0x63, 0x4c>, AMDGPUSample_c_l>;
+defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <mimgopc<0x4d, 0x64, 0x64, 0x4d>, AMDGPUSample_c_b>;
+defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <mimgopc<0x4e, 0x65, 0x65, 0x4e>, AMDGPUSample_c_b_cl>;
+defm IMAGE_GATHER4_C_LZ : MIMG_Gather <mimgopc<0x4f, 0x34, 0x34, 0x4f>, AMDGPUSample_c_lz>;
+defm IMAGE_GATHER4_O : MIMG_Gather_WQM <mimgopc<0x50, 0x35, 0x35, 0x50>, AMDGPUSample_o>;
+defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x51>, AMDGPUSample_cl_o>;
+defm IMAGE_GATHER4_L_O : MIMG_Gather <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x54>, AMDGPUSample_l_o>;
+defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x55>, AMDGPUSample_b_o>;
+defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x56>, AMDGPUSample_b_cl_o>;
+defm IMAGE_GATHER4_LZ_O : MIMG_Gather <mimgopc<0x57, 0x36, 0x36, 0x57>, AMDGPUSample_lz_o>;
+defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x58>, AMDGPUSample_c_o>;
+defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x59>, AMDGPUSample_c_cl_o>;
+defm IMAGE_GATHER4_C_L_O : MIMG_Gather <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x5c>, AMDGPUSample_c_l_o>;
+defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x5d>, AMDGPUSample_c_b_o>;
+defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x5e>, AMDGPUSample_c_b_cl_o>;
+defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <mimgopc<0x5f, 0x37, 0x37, 0x5f>, AMDGPUSample_c_lz_o>;
let OtherPredicates = [HasImageInsts, HasExtendedImageInsts, isGFX9Plus] in
-defm IMAGE_GATHER4H : MIMG_Gather <mimgopc<0x90, 0x90, 0x61, 0x42>, AMDGPUSample, 1, "image_gather4h">;
-
-defm IMAGE_GET_LOD : MIMG_Sampler <mimgopc<0x38, 0x38, 0x60>, AMDGPUSample, 0, 1, 0, 1, "image_get_lod">;
-
-defm IMAGE_SAMPLE_CD : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, 0x68>, AMDGPUSample_cd>;
-defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, 0x69>, AMDGPUSample_cd_cl>;
-defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, 0x6a>, AMDGPUSample_c_cd>;
-defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, 0x6b>, AMDGPUSample_c_cd_cl>;
-defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, 0x6c>, AMDGPUSample_cd_o>;
-defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, 0x6d>, AMDGPUSample_cd_cl_o>;
-defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, 0x6e>, AMDGPUSample_c_cd_o>;
-defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, 0x6f>, AMDGPUSample_c_cd_cl_o>;
+defm IMAGE_GATHER4H : MIMG_Gather <mimgopc<0x61, 0x90, 0x90, 0x61, 0x42>, AMDGPUSample, 1, "image_gather4h">;
+
+defm IMAGE_GET_LOD : MIMG_Sampler <mimgopc<0x60, 0x38, 0x38, 0x60>, AMDGPUSample, 0, 1, 0, 1, "image_get_lod">;
+
+defm IMAGE_SAMPLE_CD : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x68>, AMDGPUSample_cd>;
+defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x69>, AMDGPUSample_cd_cl>;
+defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x6a>, AMDGPUSample_c_cd>;
+defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x6b>, AMDGPUSample_c_cd_cl>;
+defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x6c>, AMDGPUSample_cd_o>;
+defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x6d>, AMDGPUSample_cd_cl_o>;
+defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x6e>, AMDGPUSample_c_cd_o>;
+defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x6f>, AMDGPUSample_c_cd_cl_o>;
} // End OtherPredicates = [HasImageInsts, HasExtendedImageInsts]
let OtherPredicates = [HasImageInsts, HasExtendedImageInsts, HasG16] in {
-defm IMAGE_SAMPLE_D_G16 : MIMG_Sampler <mimgopc<0x39, 0x39, 0xa2>, AMDGPUSample_d, 0, 0, 1>;
-defm IMAGE_SAMPLE_D_CL_G16 : MIMG_Sampler <mimgopc<0x5f, 0x5f, 0xa3>, AMDGPUSample_d_cl, 0, 0, 1>;
-defm IMAGE_SAMPLE_C_D_G16 : MIMG_Sampler <mimgopc<0x3a, 0x3a, 0xaa>, AMDGPUSample_c_d, 0, 0, 1>;
-defm IMAGE_SAMPLE_C_D_CL_G16 : MIMG_Sampler <mimgopc<0x54, 0x54, 0xab>, AMDGPUSample_c_d_cl, 0, 0, 1>;
-defm IMAGE_SAMPLE_D_O_G16 : MIMG_Sampler <mimgopc<0x3b, 0x3b, 0xb2>, AMDGPUSample_d_o, 0, 0, 1>;
-defm IMAGE_SAMPLE_D_CL_O_G16 : MIMG_Sampler <mimgopc<0x55, 0x55, 0xb3>, AMDGPUSample_d_cl_o, 0, 0, 1>;
-defm IMAGE_SAMPLE_C_D_O_G16 : MIMG_Sampler <mimgopc<0x3c, 0x3c, 0xba>, AMDGPUSample_c_d_o, 0, 0, 1>;
-defm IMAGE_SAMPLE_C_D_CL_O_G16 : MIMG_Sampler <mimgopc<0x56, 0x56, 0xbb>, AMDGPUSample_c_d_cl_o, 0, 0, 1>;
-defm IMAGE_SAMPLE_CD_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, 0xe8>, AMDGPUSample_cd, 0, 0, 1>;
-defm IMAGE_SAMPLE_CD_CL_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, 0xe9>, AMDGPUSample_cd_cl, 0, 0, 1>;
-defm IMAGE_SAMPLE_C_CD_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, 0xea>, AMDGPUSample_c_cd, 0, 0, 1>;
-defm IMAGE_SAMPLE_C_CD_CL_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, 0xeb>, AMDGPUSample_c_cd_cl, 0, 0, 1>;
-defm IMAGE_SAMPLE_CD_O_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, 0xec>, AMDGPUSample_cd_o, 0, 0, 1>;
-defm IMAGE_SAMPLE_CD_CL_O_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, 0xed>, AMDGPUSample_cd_cl_o, 0, 0, 1>;
-defm IMAGE_SAMPLE_C_CD_O_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, 0xee>, AMDGPUSample_c_cd_o, 0, 0, 1>;
-defm IMAGE_SAMPLE_C_CD_CL_O_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, 0xef>, AMDGPUSample_c_cd_cl_o, 0, 0, 1>;
+defm IMAGE_SAMPLE_D_G16 : MIMG_Sampler <mimgopc<0xa2, 0x39, 0x39, 0xa2>, AMDGPUSample_d, 0, 0, 1>;
+defm IMAGE_SAMPLE_D_CL_G16 : MIMG_Sampler <mimgopc<0xa3, 0x5f, 0x5f, 0xa3>, AMDGPUSample_d_cl, 0, 0, 1>;
+defm IMAGE_SAMPLE_C_D_G16 : MIMG_Sampler <mimgopc<0xaa, 0x3a, 0x3a, 0xaa>, AMDGPUSample_c_d, 0, 0, 1>;
+defm IMAGE_SAMPLE_C_D_CL_G16 : MIMG_Sampler <mimgopc<0xab, 0x54, 0x54, 0xab>, AMDGPUSample_c_d_cl, 0, 0, 1>;
+defm IMAGE_SAMPLE_D_O_G16 : MIMG_Sampler <mimgopc<0xb2, 0x3b, 0x3b, 0xb2>, AMDGPUSample_d_o, 0, 0, 1>;
+defm IMAGE_SAMPLE_D_CL_O_G16 : MIMG_Sampler <mimgopc<0xb3, 0x55, 0x55, 0xb3>, AMDGPUSample_d_cl_o, 0, 0, 1>;
+defm IMAGE_SAMPLE_C_D_O_G16 : MIMG_Sampler <mimgopc<0xba, 0x3c, 0x3c, 0xba>, AMDGPUSample_c_d_o, 0, 0, 1>;
+defm IMAGE_SAMPLE_C_D_CL_O_G16 : MIMG_Sampler <mimgopc<0xbb, 0x56, 0x56, 0xbb>, AMDGPUSample_c_d_cl_o, 0, 0, 1>;
+defm IMAGE_SAMPLE_CD_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0xe8>, AMDGPUSample_cd, 0, 0, 1>;
+defm IMAGE_SAMPLE_CD_CL_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0xe9>, AMDGPUSample_cd_cl, 0, 0, 1>;
+defm IMAGE_SAMPLE_C_CD_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0xea>, AMDGPUSample_c_cd, 0, 0, 1>;
+defm IMAGE_SAMPLE_C_CD_CL_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0xeb>, AMDGPUSample_c_cd_cl, 0, 0, 1>;
+defm IMAGE_SAMPLE_CD_O_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0xec>, AMDGPUSample_cd_o, 0, 0, 1>;
+defm IMAGE_SAMPLE_CD_CL_O_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0xed>, AMDGPUSample_cd_cl_o, 0, 0, 1>;
+defm IMAGE_SAMPLE_C_CD_O_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0xee>, AMDGPUSample_c_cd_o, 0, 0, 1>;
+defm IMAGE_SAMPLE_C_CD_CL_O_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0xef>, AMDGPUSample_c_cd_cl_o, 0, 0, 1>;
} // End OtherPredicates = [HasImageInsts, HasExtendedImageInsts, HasG16]
//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", mimgopc<0x7e>>;
//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", mimgopc<0x7f>>;
let OtherPredicates = [HasImageInsts, HasGFX10_AEncoding, isGFX10Only] in
-defm IMAGE_MSAA_LOAD_X : MIMG_NoSampler <mimgopc<MIMG.NOP, MIMG.NOP, 0x80>, "image_msaa_load", 1, 0, 0, 1>;
+defm IMAGE_MSAA_LOAD_X : MIMG_NoSampler <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x80>, "image_msaa_load", 1, 0, 0, 1>;
let OtherPredicates = [HasImageInsts, HasGFX10_AEncoding] in {
-defm IMAGE_MSAA_LOAD : MIMG_MSAA_Load <mimgopc<0x18, 0x18, MIMG.NOP>, "image_msaa_load">;
+defm IMAGE_MSAA_LOAD : MIMG_MSAA_Load <mimgopc<0x80, 0x18, 0x18, MIMG.NOP>, "image_msaa_load">;
-defm IMAGE_BVH_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<0x19, 0x19, 0xe6>, "image_bvh_intersect_ray", 0, 0, 0>;
-defm IMAGE_BVH_INTERSECT_RAY_a16 : MIMG_IntersectRay<mimgopc<0x19, 0x19, 0xe6>, "image_bvh_intersect_ray", 0, 1, 0>;
-defm IMAGE_BVH64_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<0x1a, 0x1a, 0xe7>, "image_bvh64_intersect_ray", 1, 0, 0>;
-defm IMAGE_BVH64_INTERSECT_RAY_a16 : MIMG_IntersectRay<mimgopc<0x1a, 0x1a, 0xe7>, "image_bvh64_intersect_ray", 1, 1, 0>;
+defm IMAGE_BVH_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<MIMG.NOP, 0x19, 0x19, 0xe6>, "image_bvh_intersect_ray", 0, 0, 0>;
+defm IMAGE_BVH_INTERSECT_RAY_a16 : MIMG_IntersectRay<mimgopc<MIMG.NOP, 0x19, 0x19, 0xe6>, "image_bvh_intersect_ray", 0, 1, 0>;
+defm IMAGE_BVH64_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<MIMG.NOP, 0x1a, 0x1a, 0xe7>, "image_bvh64_intersect_ray", 1, 0, 0>;
+defm IMAGE_BVH64_INTERSECT_RAY_a16 : MIMG_IntersectRay<mimgopc<MIMG.NOP, 0x1a, 0x1a, 0xe7>, "image_bvh64_intersect_ray", 1, 1, 0>;
} // End OtherPredicates = [HasImageInsts, HasGFX10_AEncoding]
-defm IMAGE_BVH_DUAL_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<0x80, MIMG.NOP, MIMG.NOP>, "image_bvh_dual_intersect_ray", 1, 0, 1>;
-defm IMAGE_BVH8_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<0x81, MIMG.NOP, MIMG.NOP>, "image_bvh8_intersect_ray", 1, 0, 0, 1>;
+defm IMAGE_BVH_DUAL_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<MIMG.NOP, 0x80, MIMG.NOP, MIMG.NOP>, "image_bvh_dual_intersect_ray", 1, 0, 1>;
+defm IMAGE_BVH8_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<MIMG.NOP, 0x81, MIMG.NOP, MIMG.NOP>, "image_bvh8_intersect_ray", 1, 0, 0, 1>;
let SubtargetPredicate = isGFX12Plus in {
def : AMDGPUMnemonicAlias<"bvh_intersect_ray", "image_bvh_intersect_ray">;
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 6c88bc7145eda..5973231eb5656 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -10120,6 +10120,7 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
bool IsGFX10Plus = AMDGPU::isGFX10Plus(*Subtarget);
bool IsGFX11Plus = AMDGPU::isGFX11Plus(*Subtarget);
bool IsGFX12Plus = AMDGPU::isGFX12Plus(*Subtarget);
+ bool IsGFX13 = AMDGPU::isGFX13(*Subtarget);
SmallVector<EVT, 3> ResultTypes(Op->values());
SmallVector<EVT, 3> OrigResultTypes(Op->values());
@@ -10447,7 +10448,10 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
UseNSA ? VAddrs.size() : VAddr.getValueType().getSizeInBits() / 32;
int Opcode = -1;
- if (IsGFX12Plus) {
+ if (IsGFX13) {
+ Opcode = AMDGPU::getMIMGOpcode(IntrOpcode, AMDGPU::MIMGEncGfx13,
+ NumVDataDwords, NumVAddrDwords);
+ } else if (IsGFX12Plus) {
Opcode = AMDGPU::getMIMGOpcode(IntrOpcode, AMDGPU::MIMGEncGfx12,
NumVDataDwords, NumVAddrDwords);
} else if (IsGFX11Plus) {
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index 768d9c1f91470..2d9aaf6abda7b 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -1481,6 +1481,10 @@ foreach size = ["64", "96", "128", "160", "192", "224", "256", "288", "320", "35
def VGPROp_#size#_Align2 : RegisterOperand<!cast<RegisterClassLike>("VReg_"#size#_Align2)>;
}
+def VGPROp_32_Lo256 : RegisterOperand<VGPR_32_Lo256> {
+ let DecoderMethod = "DecodeVGPR_32RegisterClass";
+}
+
def VGPROp_16_Lo128 : RegisterOperand<VGPR_16_Lo128> {
let DecoderMethod = "DecodeVGPR_16_Lo128RegisterClass";
let EncoderMethod = "getMachineOpValueT16Lo128";
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
index 713f82e5ae71d..6c3523abe7eb4 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
@@ -2,7 +2,8 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12PLUS %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 < %s | FileCheck -check-prefixes=GFX12PLUS %s
define amdgpu_ps <4 x float> @load_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
; GFX9-LABEL: load_1d:
@@ -17,11 +18,11 @@ define amdgpu_ps <4 x float> @load_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords)
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -41,11 +42,11 @@ define amdgpu_ps <4 x float> @load_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords)
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%t = extractelement <2 x i16> %coords, i32 1
@@ -66,11 +67,11 @@ define amdgpu_ps <4 x float> @load_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_l
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -92,11 +93,11 @@ define amdgpu_ps <4 x float> @load_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_cube:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_cube:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -118,11 +119,11 @@ define amdgpu_ps <4 x float> @load_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coo
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%slice = extractelement <2 x i16> %coords, i32 1
@@ -143,11 +144,11 @@ define amdgpu_ps <4 x float> @load_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coo
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -169,11 +170,11 @@ define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2dmsaa:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2dmsaa:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -195,11 +196,11 @@ define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16>
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2darraymsaa:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2darraymsaa:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -222,11 +223,11 @@ define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load_mip v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load_mip v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%mip = extractelement <2 x i16> %coords, i32 1
@@ -247,11 +248,11 @@ define amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -273,11 +274,11 @@ define amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -300,11 +301,11 @@ define amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, <2 x i16> %co
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_cube:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_cube:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -327,11 +328,11 @@ define amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, <2 x i16>
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_1darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_1darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%slice = extractelement <2 x i16> %coords_lo, i32 1
@@ -353,11 +354,11 @@ define amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, <2 x i16>
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_2darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_2darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -378,10 +379,10 @@ define amdgpu_ps void @store_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x
; GFX10PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm a16
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%s = extractelement <2 x i16> %coords, i32 0
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -399,10 +400,10 @@ define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x
; GFX10PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm a16
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%t = extractelement <2 x i16> %coords, i32 1
@@ -421,10 +422,10 @@ define amdgpu_ps void @store_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x
; GFX10PLUS-NEXT: image_store v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -444,10 +445,10 @@ define amdgpu_ps void @store_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2
; GFX10PLUS-NEXT: image_store v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm a16
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_cube:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_cube:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -467,10 +468,10 @@ define amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata,
; GFX10PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm a16
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_1darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_1darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%slice = extractelement <2 x i16> %coords, i32 1
@@ -489,10 +490,10 @@ define amdgpu_ps void @store_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata,
; GFX10PLUS-NEXT: image_store v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm a16
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_2darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_2darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -512,10 +513,10 @@ define amdgpu_ps void @store_2dmsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, <
; GFX10PLUS-NEXT: image_store v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_2dmsaa:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_2dmsaa:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -535,10 +536,10 @@ define amdgpu_ps void @store_2darraymsaa(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX10PLUS-NEXT: image_store v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_2darraymsaa:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_2darraymsaa:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -559,10 +560,10 @@ define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <
; GFX10PLUS-NEXT: image_store_mip v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm a16
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_mip_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store_mip v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_mip_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store_mip v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%mip = extractelement <2 x i16> %coords, i32 1
@@ -581,10 +582,10 @@ define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <
; GFX10PLUS-NEXT: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm a16
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_mip_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_mip_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -604,10 +605,10 @@ define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <
; GFX10PLUS-NEXT: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_mip_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_mip_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -628,10 +629,10 @@ define amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata,
; GFX10PLUS-NEXT: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm a16
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_mip_cube:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_mip_cube:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -652,10 +653,10 @@ define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX10PLUS-NEXT: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm a16
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_mip_1darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_mip_1darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%slice = extractelement <2 x i16> %coords_lo, i32 1
@@ -675,10 +676,10 @@ define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX10PLUS-NEXT: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm a16
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_mip_2darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_mip_2darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -701,11 +702,11 @@ define amdgpu_ps <4 x float> @getresinfo_1d(<8 x i32> inreg %rsrc, <2 x i16> %co
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%mip = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
@@ -725,11 +726,11 @@ define amdgpu_ps <4 x float> @getresinfo_2d(<8 x i32> inreg %rsrc, <2 x i16> %co
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%mip = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
@@ -749,11 +750,11 @@ define amdgpu_ps <4 x float> @getresinfo_3d(<8 x i32> inreg %rsrc, <2 x i16> %co
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%mip = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.3d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
@@ -773,11 +774,11 @@ define amdgpu_ps <4 x float> @getresinfo_cube(<8 x i32> inreg %rsrc, <2 x i16> %
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_cube:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_cube:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%mip = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.cube.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
@@ -797,11 +798,11 @@ define amdgpu_ps <4 x float> @getresinfo_1darray(<8 x i32> inreg %rsrc, <2 x i16
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_1darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_1darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%mip = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.1darray.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
@@ -821,11 +822,11 @@ define amdgpu_ps <4 x float> @getresinfo_2darray(<8 x i32> inreg %rsrc, <2 x i16
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_2darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_2darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%mip = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2darray.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
@@ -845,11 +846,11 @@ define amdgpu_ps <4 x float> @getresinfo_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16>
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_2dmsaa:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_2dmsaa:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%mip = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2dmsaa.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
@@ -869,11 +870,11 @@ define amdgpu_ps <4 x float> @getresinfo_2darraymsaa(<8 x i32> inreg %rsrc, <2 x
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_2darraymsaa:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_2darraymsaa:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%mip = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2darraymsaa.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
@@ -893,11 +894,11 @@ define amdgpu_ps float @load_1d_V1(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_V1:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v0, v0, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_V1:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v0, v0, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%v = call float @llvm.amdgcn.image.load.1d.f32.i16(i32 8, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -917,11 +918,11 @@ define amdgpu_ps <2 x float> @load_1d_V2(<8 x i32> inreg %rsrc, <2 x i16> %coord
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_V2:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x9 dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_V2:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x9 dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%v = call <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i16(i32 9, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -939,10 +940,10 @@ define amdgpu_ps void @store_1d_V1(<8 x i32> inreg %rsrc, float %vdata, <2 x i16
; GFX10PLUS-NEXT: image_store v0, v1, s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_1D unorm a16
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_1d_V1:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v0, v1, s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_1d_V1:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v0, v1, s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%s = extractelement <2 x i16> %coords, i32 0
call void @llvm.amdgcn.image.store.1d.f32.i16(float %vdata, i32 2, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -960,10 +961,10 @@ define amdgpu_ps void @store_1d_V2(<8 x i32> inreg %rsrc, <2 x float> %vdata, <2
; GFX10PLUS-NEXT: image_store v[0:1], v2, s[0:7] dmask:0xc dim:SQ_RSRC_IMG_1D unorm a16
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_1d_V2:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:1], v2, s[0:7] dmask:0xc dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_1d_V2:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:1], v2, s[0:7] dmask:0xc dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%s = extractelement <2 x i16> %coords, i32 0
call void @llvm.amdgcn.image.store.1d.v2f32.i16(<2 x float> %vdata, i32 12, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -983,11 +984,11 @@ define amdgpu_ps <4 x float> @load_1d_glc(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_glc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_glc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 1)
@@ -1007,11 +1008,11 @@ define amdgpu_ps <4 x float> @load_1d_slc(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_slc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_HT a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_slc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_HT a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)
@@ -1031,11 +1032,11 @@ define amdgpu_ps <4 x float> @load_1d_glc_slc(<8 x i32> inreg %rsrc, <2 x i16> %
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_glc_slc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_LU a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_glc_slc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_LU a16
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 3)
@@ -1053,10 +1054,10 @@ define amdgpu_ps void @store_1d_glc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <
; GFX10PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm glc a16
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_1d_glc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_NT a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_1d_glc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_NT a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%s = extractelement <2 x i16> %coords, i32 0
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 1)
@@ -1074,10 +1075,10 @@ define amdgpu_ps void @store_1d_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <
; GFX10PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm slc a16
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_1d_slc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_HT a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_1d_slc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_HT a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%s = extractelement <2 x i16> %coords, i32 0
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)
@@ -1095,10 +1096,10 @@ define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdat
; GFX10PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm glc slc a16
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_1d_glc_slc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_WB a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_1d_glc_slc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_WB a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%s = extractelement <2 x i16> %coords, i32 0
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 3)
@@ -1114,9 +1115,9 @@ define amdgpu_ps <4 x float> @getresinfo_dmask0(<8 x i32> inreg %rsrc, <4 x floa
; GFX10PLUS: ; %bb.0: ; %main_body
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_dmask0:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_dmask0:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%mip = extractelement <2 x i16> %coords, i32 0
%r = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i16(i32 0, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll
index 69720ac5d8058..0fde6eac0ec52 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll
@@ -2,7 +2,8 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX9 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX10 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX11 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX12PLUS,GFX13 %s
define amdgpu_ps <4 x float> @load_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
; GFX9-LABEL: load_1d:
@@ -23,11 +24,11 @@ define amdgpu_ps <4 x float> @load_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords)
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
-; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -53,11 +54,11 @@ define amdgpu_ps <4 x float> @load_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords)
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
-; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%t = extractelement <2 x i16> %coords, i32 1
@@ -84,11 +85,11 @@ define amdgpu_ps <4 x float> @load_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_l
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 ; encoding: [0x42,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
-; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 ; encoding: [0x42,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -116,11 +117,11 @@ define amdgpu_ps <4 x float> @load_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_cube:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
-; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_cube:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -148,11 +149,11 @@ define amdgpu_ps <4 x float> @load_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coo
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16 ; encoding: [0x44,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
-; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16 ; encoding: [0x44,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%slice = extractelement <2 x i16> %coords, i32 1
@@ -179,11 +180,11 @@ define amdgpu_ps <4 x float> @load_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coo
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
-; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -211,11 +212,11 @@ define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2dmsaa:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA a16 ; encoding: [0x46,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
-; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2dmsaa:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA a16 ; encoding: [0x46,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -243,11 +244,11 @@ define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16>
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2darraymsaa:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 ; encoding: [0x47,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
-; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2darraymsaa:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 ; encoding: [0x47,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -276,11 +277,11 @@ define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load_mip v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x40,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
-; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load_mip v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x40,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%mip = extractelement <2 x i16> %coords, i32 1
@@ -307,11 +308,11 @@ define amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x40,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
-; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x40,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -339,11 +340,11 @@ define amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 ; encoding: [0x42,0x40,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
-; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 ; encoding: [0x42,0x40,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -372,11 +373,11 @@ define amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, <2 x i16> %co
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_cube:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x40,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
-; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_cube:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x40,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -405,11 +406,11 @@ define amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, <2 x i16>
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_1darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16 ; encoding: [0x44,0x40,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
-; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_1darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16 ; encoding: [0x44,0x40,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%slice = extractelement <2 x i16> %coords_lo, i32 1
@@ -437,11 +438,11 @@ define amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, <2 x i16>
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_2darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x40,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
-; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_2darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x40,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -471,6 +472,11 @@ define amdgpu_ps void @store_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x80,0xc1,0xd3,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+;
+; GFX13-LABEL: store_1d:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x00,0xc2,0xd3,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00]
+; GFX13-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
main_body:
%s = extractelement <2 x i16> %coords, i32 0
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -497,6 +503,11 @@ define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x80,0xc1,0xd3,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+;
+; GFX13-LABEL: store_2d:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x00,0xc2,0xd3,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00]
+; GFX13-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%t = extractelement <2 x i16> %coords, i32 1
@@ -524,6 +535,11 @@ define amdgpu_ps void @store_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 ; encoding: [0x42,0x80,0xc1,0xd3,0x00,0x00,0x00,0x00,0x04,0x05,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+;
+; GFX13-LABEL: store_3d:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 ; encoding: [0x42,0x00,0xc2,0xd3,0x00,0x00,0x00,0x00,0x04,0x05,0x00,0x00]
+; GFX13-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -552,6 +568,11 @@ define amdgpu_ps void @store_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x80,0xc1,0xd3,0x00,0x00,0x00,0x00,0x04,0x05,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+;
+; GFX13-LABEL: store_cube:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x00,0xc2,0xd3,0x00,0x00,0x00,0x00,0x04,0x05,0x00,0x00]
+; GFX13-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -580,6 +601,11 @@ define amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata,
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16 ; encoding: [0x44,0x80,0xc1,0xd3,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+;
+; GFX13-LABEL: store_1darray:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16 ; encoding: [0x44,0x00,0xc2,0xd3,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00]
+; GFX13-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%slice = extractelement <2 x i16> %coords, i32 1
@@ -607,6 +633,11 @@ define amdgpu_ps void @store_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata,
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x80,0xc1,0xd3,0x00,0x00,0x00,0x00,0x04,0x05,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+;
+; GFX13-LABEL: store_2darray:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x00,0xc2,0xd3,0x00,0x00,0x00,0x00,0x04,0x05,0x00,0x00]
+; GFX13-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -635,6 +666,11 @@ define amdgpu_ps void @store_2dmsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, <
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA a16 ; encoding: [0x46,0x80,0xc1,0xd3,0x00,0x00,0x00,0x00,0x04,0x05,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+;
+; GFX13-LABEL: store_2dmsaa:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA a16 ; encoding: [0x46,0x00,0xc2,0xd3,0x00,0x00,0x00,0x00,0x04,0x05,0x00,0x00]
+; GFX13-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -663,6 +699,11 @@ define amdgpu_ps void @store_2darraymsaa(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 ; encoding: [0x47,0x80,0xc1,0xd3,0x00,0x00,0x00,0x00,0x04,0x05,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+;
+; GFX13-LABEL: store_2darraymsaa:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 ; encoding: [0x47,0x00,0xc2,0xd3,0x00,0x00,0x00,0x00,0x04,0x05,0x00,0x00]
+; GFX13-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -692,6 +733,11 @@ define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: image_store_mip v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0xc0,0xc1,0xd3,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+;
+; GFX13-LABEL: store_mip_1d:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_store_mip v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x40,0xc2,0xd3,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00]
+; GFX13-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%mip = extractelement <2 x i16> %coords, i32 1
@@ -719,6 +765,11 @@ define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0xc0,0xc1,0xd3,0x00,0x00,0x00,0x00,0x04,0x05,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+;
+; GFX13-LABEL: store_mip_2d:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x40,0xc2,0xd3,0x00,0x00,0x00,0x00,0x04,0x05,0x00,0x00]
+; GFX13-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -747,6 +798,11 @@ define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 ; encoding: [0x42,0xc0,0xc1,0xd3,0x00,0x00,0x00,0x00,0x04,0x05,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+;
+; GFX13-LABEL: store_mip_3d:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 ; encoding: [0x42,0x40,0xc2,0xd3,0x00,0x00,0x00,0x00,0x04,0x05,0x00,0x00]
+; GFX13-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -776,6 +832,11 @@ define amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata,
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0xc0,0xc1,0xd3,0x00,0x00,0x00,0x00,0x04,0x05,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+;
+; GFX13-LABEL: store_mip_cube:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x40,0xc2,0xd3,0x00,0x00,0x00,0x00,0x04,0x05,0x00,0x00]
+; GFX13-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -805,6 +866,11 @@ define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16 ; encoding: [0x44,0xc0,0xc1,0xd3,0x00,0x00,0x00,0x00,0x04,0x05,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+;
+; GFX13-LABEL: store_mip_1darray:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16 ; encoding: [0x44,0x40,0xc2,0xd3,0x00,0x00,0x00,0x00,0x04,0x05,0x00,0x00]
+; GFX13-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%slice = extractelement <2 x i16> %coords_lo, i32 1
@@ -833,6 +899,11 @@ define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0xc0,0xc1,0xd3,0x00,0x00,0x00,0x00,0x04,0x05,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+;
+; GFX13-LABEL: store_mip_2darray:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x40,0xc2,0xd3,0x00,0x00,0x00,0x00,0x04,0x05,0x00,0x00]
+; GFX13-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
main_body:
%s = extractelement <2 x i16> %coords_lo, i32 0
%t = extractelement <2 x i16> %coords_lo, i32 1
@@ -866,6 +937,12 @@ define amdgpu_ps <4 x float> @getresinfo_1d(<8 x i32> inreg %rsrc, <2 x i16> %co
; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0xc0,0xc5,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX13-LABEL: getresinfo_1d:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x80,0xc3,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+; GFX13-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX13-NEXT: ; return to shader part epilog
main_body:
%mip = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
@@ -896,6 +973,12 @@ define amdgpu_ps <4 x float> @getresinfo_2d(<8 x i32> inreg %rsrc, <2 x i16> %co
; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0xc0,0xc5,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX13-LABEL: getresinfo_2d:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x80,0xc3,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+; GFX13-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX13-NEXT: ; return to shader part epilog
main_body:
%mip = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
@@ -926,6 +1009,12 @@ define amdgpu_ps <4 x float> @getresinfo_3d(<8 x i32> inreg %rsrc, <2 x i16> %co
; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 ; encoding: [0x42,0xc0,0xc5,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX13-LABEL: getresinfo_3d:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 ; encoding: [0x42,0x80,0xc3,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+; GFX13-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX13-NEXT: ; return to shader part epilog
main_body:
%mip = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.3d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
@@ -956,6 +1045,12 @@ define amdgpu_ps <4 x float> @getresinfo_cube(<8 x i32> inreg %rsrc, <2 x i16> %
; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0xc0,0xc5,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX13-LABEL: getresinfo_cube:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x80,0xc3,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+; GFX13-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX13-NEXT: ; return to shader part epilog
main_body:
%mip = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.cube.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
@@ -986,6 +1081,12 @@ define amdgpu_ps <4 x float> @getresinfo_1darray(<8 x i32> inreg %rsrc, <2 x i16
; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16 ; encoding: [0x44,0xc0,0xc5,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX13-LABEL: getresinfo_1darray:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16 ; encoding: [0x44,0x80,0xc3,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+; GFX13-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX13-NEXT: ; return to shader part epilog
main_body:
%mip = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.1darray.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
@@ -1016,6 +1117,12 @@ define amdgpu_ps <4 x float> @getresinfo_2darray(<8 x i32> inreg %rsrc, <2 x i16
; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0xc0,0xc5,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX13-LABEL: getresinfo_2darray:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x80,0xc3,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+; GFX13-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX13-NEXT: ; return to shader part epilog
main_body:
%mip = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2darray.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
@@ -1046,6 +1153,12 @@ define amdgpu_ps <4 x float> @getresinfo_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16>
; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA a16 ; encoding: [0x46,0xc0,0xc5,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX13-LABEL: getresinfo_2dmsaa:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA a16 ; encoding: [0x46,0x80,0xc3,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+; GFX13-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX13-NEXT: ; return to shader part epilog
main_body:
%mip = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2dmsaa.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
@@ -1076,6 +1189,12 @@ define amdgpu_ps <4 x float> @getresinfo_2darraymsaa(<8 x i32> inreg %rsrc, <2 x
; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 ; encoding: [0x47,0xc0,0xc5,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX13-LABEL: getresinfo_2darraymsaa:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 ; encoding: [0x47,0x80,0xc3,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+; GFX13-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX13-NEXT: ; return to shader part epilog
main_body:
%mip = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2darraymsaa.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
@@ -1101,11 +1220,11 @@ define amdgpu_ps float @load_1d_V1(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_V1:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v0, v0, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x00,0x00,0xd2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
-; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_V1:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v0, v0, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x00,0x00,0xd2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%v = call float @llvm.amdgcn.image.load.1d.f32.i16(i32 8, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -1131,11 +1250,11 @@ define amdgpu_ps <2 x float> @load_1d_V2(<8 x i32> inreg %rsrc, <2 x i16> %coord
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_V2:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x9 dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x00,0x40,0xd2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
-; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_V2:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x9 dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x00,0x40,0xd2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%v = call <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i16(i32 9, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -1162,6 +1281,11 @@ define amdgpu_ps void @store_1d_V1(<8 x i32> inreg %rsrc, float %vdata, <2 x i16
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: image_store v0, v1, s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x80,0x81,0xd0,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+;
+; GFX13-LABEL: store_1d_V1:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_store v0, v1, s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x00,0x82,0xd0,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
+; GFX13-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
main_body:
%s = extractelement <2 x i16> %coords, i32 0
call void @llvm.amdgcn.image.store.1d.f32.i16(float %vdata, i32 2, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -1188,6 +1312,11 @@ define amdgpu_ps void @store_1d_V2(<8 x i32> inreg %rsrc, <2 x float> %vdata, <2
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: image_store v[0:1], v2, s[0:7] dmask:0xc dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x80,0x01,0xd3,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+;
+; GFX13-LABEL: store_1d_V2:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_store v[0:1], v2, s[0:7] dmask:0xc dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x00,0x02,0xd3,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00]
+; GFX13-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
main_body:
%s = extractelement <2 x i16> %coords, i32 0
call void @llvm.amdgcn.image.store.1d.v2f32.i16(<2 x float> %vdata, i32 12, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -1213,11 +1342,11 @@ define amdgpu_ps <4 x float> @load_1d_glc(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_glc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT a16 ; encoding: [0x40,0x00,0xc0,0xd3,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00]
-; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_glc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT a16 ; encoding: [0x40,0x00,0xc0,0xd3,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00]
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 1)
@@ -1243,11 +1372,11 @@ define amdgpu_ps <4 x float> @load_1d_slc(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_slc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_HT a16 ; encoding: [0x40,0x00,0xc0,0xd3,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
-; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_slc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_HT a16 ; encoding: [0x40,0x00,0xc0,0xd3,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)
@@ -1273,11 +1402,11 @@ define amdgpu_ps <4 x float> @load_1d_glc_slc(<8 x i32> inreg %rsrc, <2 x i16> %
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_glc_slc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_LU a16 ; encoding: [0x40,0x00,0xc0,0xd3,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00]
-; GFX12-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_glc_slc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_LU a16 ; encoding: [0x40,0x00,0xc0,0xd3,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00]
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%s = extractelement <2 x i16> %coords, i32 0
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 3)
@@ -1304,6 +1433,11 @@ define amdgpu_ps void @store_1d_glc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_NT a16 ; encoding: [0x40,0x80,0xc1,0xd3,0x00,0x00,0x10,0x00,0x04,0x00,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+;
+; GFX13-LABEL: store_1d_glc:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_NT a16 ; encoding: [0x40,0x00,0xc2,0xd3,0x00,0x00,0x10,0x00,0x04,0x00,0x00,0x00]
+; GFX13-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
main_body:
%s = extractelement <2 x i16> %coords, i32 0
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 1)
@@ -1330,6 +1464,11 @@ define amdgpu_ps void @store_1d_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_HT a16 ; encoding: [0x40,0x80,0xc1,0xd3,0x00,0x00,0x20,0x00,0x04,0x00,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+;
+; GFX13-LABEL: store_1d_slc:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_HT a16 ; encoding: [0x40,0x00,0xc2,0xd3,0x00,0x00,0x20,0x00,0x04,0x00,0x00,0x00]
+; GFX13-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
main_body:
%s = extractelement <2 x i16> %coords, i32 0
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)
@@ -1356,6 +1495,11 @@ define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdat
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_WB a16 ; encoding: [0x40,0x80,0xc1,0xd3,0x00,0x00,0x30,0x00,0x04,0x00,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+;
+; GFX13-LABEL: store_1d_glc_slc:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_WB a16 ; encoding: [0x40,0x00,0xc2,0xd3,0x00,0x00,0x30,0x00,0x04,0x00,0x00,0x00]
+; GFX13-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
main_body:
%s = extractelement <2 x i16> %coords, i32 0
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 3)
@@ -1375,9 +1519,9 @@ define amdgpu_ps <4 x float> @getresinfo_dmask0(<8 x i32> inreg %rsrc, <4 x floa
; GFX11: ; %bb.0: ; %main_body
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_dmask0:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_dmask0:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%mip = extractelement <2 x i16> %coords, i32 0
%r = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i16(i32 0, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll
index eacdd9108bf14..1ab7405d2dd6e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll
@@ -4,13 +4,14 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -early-live-intervals < %s | FileCheck -check-prefixes=GCN,GFX90A %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GFX10 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GFX10 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GFX12PLUS %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GFX12PLUS %s
; GCN-LABEL: {{^}}atomic_swap_1d:
; GFX6789: image_atomic_swap v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX90A: image_atomic_swap v0, v{{[02468]}}, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX10: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ;
-; GFX12: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_swap_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -22,7 +23,7 @@ main_body:
; GFX6789: image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 unorm glc{{$}}
; GFX90A: image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 unorm glc{{$}}
; GFX10: image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc ;
-; GFX12: image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
define amdgpu_ps <2 x float> @atomic_swap_1d_i64(<8 x i32> inreg %rsrc, i64 %data, i32 %s) {
main_body:
%v = call i64 @llvm.amdgcn.image.atomic.swap.1d.i64.i32(i64 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -34,7 +35,7 @@ main_body:
; GFX6789: image_atomic_swap v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX90A: image_atomic_swap v0, v{{[02468]}}, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX10: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ;
-; GFX12: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_swap_1d_float(<8 x i32> inreg %rsrc, float %data, i32 %s) {
main_body:
%v = call float @llvm.amdgcn.image.atomic.swap.1d.f32.i32(float %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -45,7 +46,7 @@ main_body:
; GFX6789: image_atomic_add v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX90A: image_atomic_add v0, v{{[02468]}}, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX10: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ;
-; GFX12: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_add_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -57,7 +58,7 @@ main_body:
; GFX6789: image_atomic_sub v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX90A: image_atomic_sub v0, v{{[02468]}}, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX10: image_atomic_sub v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ;
-; GFX12: image_atomic_sub_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_sub_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_sub_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.sub.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -69,7 +70,7 @@ main_body:
; GFX6789: image_atomic_smin v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX90A: image_atomic_smin v0, v{{[02468]}}, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX10: image_atomic_smin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ;
-; GFX12: image_atomic_min_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_min_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_smin_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.smin.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -81,7 +82,7 @@ main_body:
; GFX6789: image_atomic_umin v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX90A: image_atomic_umin v0, v{{[02468]}}, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX10: image_atomic_umin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ;
-; GFX12: image_atomic_min_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_min_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_umin_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.umin.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -93,7 +94,7 @@ main_body:
; GFX6789: image_atomic_smax v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX90A: image_atomic_smax v0, v{{[02468]}}, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX10: image_atomic_smax v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ;
-; GFX12: image_atomic_max_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_max_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_smax_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.smax.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -105,7 +106,7 @@ main_body:
; GFX6789: image_atomic_umax v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX90A: image_atomic_umax v0, v{{[02468]}}, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX10: image_atomic_umax v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ;
-; GFX12: image_atomic_max_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_max_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_umax_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.umax.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -117,7 +118,7 @@ main_body:
; GFX6789: image_atomic_and v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX90A: image_atomic_and v0, v{{[02468]}}, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX10: image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ;
-; GFX12: image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_and_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.and.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -129,7 +130,7 @@ main_body:
; GFX6789: image_atomic_or v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX90A: image_atomic_or v0, v{{[02468]}}, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX10: image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ;
-; GFX12: image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_or_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.or.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -141,7 +142,7 @@ main_body:
; GFX6789: image_atomic_xor v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX90A: image_atomic_xor v0, v{{[02468]}}, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX10: image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ;
-; GFX12: image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_xor_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.xor.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -153,7 +154,7 @@ main_body:
; GFX6789: image_atomic_inc v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX90A: image_atomic_inc v0, v{{[02468]}}, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX10: image_atomic_inc v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ;
-; GFX12: image_atomic_inc_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_inc_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_inc_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.inc.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -165,7 +166,7 @@ main_body:
; GFX6789: image_atomic_dec v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX90A: image_atomic_dec v0, v{{[02468]}}, s[0:7] dmask:0x1 unorm glc{{$}}
; GFX10: image_atomic_dec v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ;
-; GFX12: image_atomic_dec_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_dec_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_dec_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.dec.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -177,7 +178,7 @@ main_body:
; GFX6789: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 unorm glc{{$}}
; GFX90A: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 unorm glc{{$}}
; GFX10: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc ;
-; GFX12: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_cmpswap_1d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %swap, i32 %s) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i32(i32 %cmp, i32 %swap, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -189,7 +190,7 @@ main_body:
; GFX6789: image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf unorm glc{{$}}
; GFX90A: image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf unorm glc{{$}}
; GFX10: image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm glc ;
-; GFX12: image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ;
define amdgpu_ps <2 x float> @atomic_cmpswap_1d_64(<8 x i32> inreg %rsrc, i64 %cmp, i64 %swap, i32 %s) {
main_body:
%v = call i64 @llvm.amdgcn.image.atomic.cmpswap.1d.i64.i32(i64 %cmp, i64 %swap, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -201,7 +202,7 @@ main_body:
; GFX6789: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 unorm glc{{$}}
; GFX90A: image_atomic_add v0, v[{{[02468]}}:{{[13579]}}], s[0:7] dmask:0x1 unorm glc{{$}}
; GFX10: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm glc ;
-; GFX12: image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_add_2d(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.add.2d.i32.i32(i32 %data, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
@@ -213,7 +214,7 @@ main_body:
; GFX6789: image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 unorm glc{{$}}
; GFX90A: image_atomic_add v0, v[{{[02468]}}:{{[02468]}}], s[0:7] dmask:0x1 unorm glc{{$}}
; GFX10: image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm glc ;
-; GFX12: image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_add_3d(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %r) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.add.3d.i32.i32(i32 %data, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 0, i32 0)
@@ -225,7 +226,7 @@ main_body:
; GFX6789: image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 unorm glc da{{$}}
; GFX90A: image_atomic_add v0, v[{{[02468]}}:{{[02468]}}], s[0:7] dmask:0x1 unorm glc da{{$}}
; GFX10: image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE unorm glc ;
-; GFX12: image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_add_cube(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %face) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.add.cube.i32.i32(i32 %data, i32 %s, i32 %t, i32 %face, <8 x i32> %rsrc, i32 0, i32 0)
@@ -237,7 +238,7 @@ main_body:
; GFX6789: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 unorm glc da{{$}}
; GFX90A: image_atomic_add v0, v[{{[02468]}}:{{[13579]}}], s[0:7] dmask:0x1 unorm glc da{{$}}
; GFX10: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc ;
-; GFX12: image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_add_1darray(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %slice) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.add.1darray.i32.i32(i32 %data, i32 %s, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)
@@ -249,7 +250,7 @@ main_body:
; GFX6789: image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 unorm glc da{{$}}
; GFX90A: image_atomic_add v0, v[{{[02468]}}:{{[02468]}}], s[0:7] dmask:0x1 unorm glc da{{$}}
; GFX10: image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY unorm glc ;
-; GFX12: image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_add_2darray(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %slice) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.add.2darray.i32.i32(i32 %data, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)
@@ -261,7 +262,7 @@ main_body:
; GFX6789: image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 unorm glc{{$}}
; GFX90A: image_atomic_add v0, v[{{[02468]}}:{{[02468]}}], s[0:7] dmask:0x1 unorm glc{{$}}
; GFX10: image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm glc ;
-; GFX12: image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_add_2dmsaa(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %fragid) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.add.2dmsaa.i32.i32(i32 %data, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
@@ -273,7 +274,7 @@ main_body:
; GFX6789: image_atomic_add v0, v[1:4], s[0:7] dmask:0x1 unorm glc da{{$}}
; GFX90A: image_atomic_add v0, v[{{[02468]}}:{{[13579]}}], s[0:7] dmask:0x1 unorm glc da{{$}}
; GFX10: image_atomic_add v0, v[1:4], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm glc ;
-; GFX12: image_atomic_add_uint v0, [v1, v2, v3, v4], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY th:TH_ATOMIC_RETURN ;
+; GFX12PLUS: image_atomic_add_uint v0, [v1, v2, v3, v4], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY th:TH_ATOMIC_RETURN ;
define amdgpu_ps float @atomic_add_2darraymsaa(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %slice, i32 %fragid) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.add.2darraymsaa.i32.i32(i32 %data, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
@@ -285,7 +286,7 @@ main_body:
; GFX6789: image_atomic_add v0, v1, s[0:7] dmask:0x1 unorm glc slc{{$}}
; GFX90A: image_atomic_add v0, v{{[02468]}}, s[0:7] dmask:0x1 unorm glc slc{{$}}
; GFX10: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc slc ;
-; GFX12: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT_RETURN ;
+; GFX12PLUS: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT_RETURN ;
define amdgpu_ps float @atomic_add_1d_slc(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 2)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.flt.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.flt.ll
index 377207de4f445..cbde19a8ad499 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.flt.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.flt.ll
@@ -1,35 +1,37 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
-; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12PLUS %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12PLUS %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1310 < %s | FileCheck -check-prefixes=GFX12PLUS %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1310 < %s | FileCheck -check-prefixes=GFX12PLUS %s
define amdgpu_ps float @atomic_min_flt_1d(<8 x i32> inreg %rsrc, float %data, i32 %s) {
-; GFX12-LABEL: atomic_min_flt_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_atomic_min_flt v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: atomic_min_flt_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_atomic_min_flt v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call float @llvm.amdgcn.image.atomic.min.flt.1d.f32.f32(float %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
ret float %v
}
define amdgpu_ps float @atomic_max_flt_1d(<8 x i32> inreg %rsrc, float %data, i32 %s) {
-; GFX12-LABEL: atomic_max_flt_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_atomic_max_flt v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: atomic_max_flt_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_atomic_max_flt v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call float @llvm.amdgcn.image.atomic.max.flt.1d.f32.f32(float %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
ret float %v
}
define amdgpu_ps float @atomic_add_flt_1d(<8 x i32> inreg %rsrc, float %data, i32 %s) {
-; GFX12-LABEL: atomic_add_flt_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_atomic_add_flt v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: atomic_add_flt_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_atomic_add_flt v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call float @llvm.amdgcn.image.atomic.add.flt.1d.f32.f32(float %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
ret float %v
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.pk.add.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.pk.add.ll
index c34200aa83f3d..67b30b76d14c3 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.pk.add.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.pk.add.ll
@@ -1,19 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -global-isel=0 -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12-SDAG %s
-; RUN: llc -mtriple=amdgcn -global-isel=1 -global-isel-abort=2 -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12-GISEL %s
+; RUN: llc -mtriple=amdgcn -global-isel=0 -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12PLUS %s
+; RUN: llc -mtriple=amdgcn -global-isel=1 -global-isel-abort=2 -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12PLUS %s
+; RUN: llc -mtriple=amdgcn -global-isel=0 -mcpu=gfx1310 < %s | FileCheck -check-prefixes=GFX12PLUS %s
+; RUN: llc -mtriple=amdgcn -global-isel=1 -global-isel-abort=2 -mcpu=gfx1310 < %s | FileCheck -check-prefixes=GFX12PLUS %s
define amdgpu_ps float @atomic_pk_add_f16_1d_v2(<8 x i32> inreg %rsrc, <2 x half> %data, i32 %s) {
-; GFX12-SDAG-LABEL: atomic_pk_add_f16_1d_v2:
-; GFX12-SDAG: ; %bb.0: ; %main_body
-; GFX12-SDAG-NEXT: image_atomic_pk_add_f16 v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: atomic_pk_add_f16_1d_v2:
-; GFX12-GISEL: ; %bb.0: ; %main_body
-; GFX12-GISEL-NEXT: image_atomic_pk_add_f16 v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: atomic_pk_add_f16_1d_v2:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_atomic_pk_add_f16 v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%out = call <2 x half> @llvm.amdgcn.image.atomic.pk.add.f16.1d.v2f16.v2f16(<2 x half> %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
%out_float = bitcast <2 x half> %out to float
@@ -21,17 +17,11 @@ main_body:
}
define amdgpu_ps float @atomic_pk_add_f16_1d_v2_nt(<8 x i32> inreg %rsrc, <2 x half> %data, i32 %s) {
-; GFX12-SDAG-LABEL: atomic_pk_add_f16_1d_v2_nt:
-; GFX12-SDAG: ; %bb.0: ; %main_body
-; GFX12-SDAG-NEXT: image_atomic_pk_add_f16 v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT_RETURN
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: atomic_pk_add_f16_1d_v2_nt:
-; GFX12-GISEL: ; %bb.0: ; %main_body
-; GFX12-GISEL-NEXT: image_atomic_pk_add_f16 v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT_RETURN
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: atomic_pk_add_f16_1d_v2_nt:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_atomic_pk_add_f16 v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT_RETURN
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%out = call <2 x half> @llvm.amdgcn.image.atomic.pk.add.f16.1d.v2f16.v2f16(<2 x half> %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 2)
%out_float = bitcast <2 x half> %out to float
@@ -39,34 +29,22 @@ main_body:
}
define amdgpu_ps float @atomic_pk_add_f16_1d_v2_noret(<8 x i32> inreg %rsrc, <2 x half> %data, i32 %s) {
-; GFX12-SDAG-LABEL: atomic_pk_add_f16_1d_v2_noret:
-; GFX12-SDAG: ; %bb.0: ; %main_body
-; GFX12-SDAG-NEXT: image_atomic_pk_add_f16 v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
-; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
-; GFX12-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: atomic_pk_add_f16_1d_v2_noret:
-; GFX12-GISEL: ; %bb.0: ; %main_body
-; GFX12-GISEL-NEXT: image_atomic_pk_add_f16 v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
-; GFX12-GISEL-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: atomic_pk_add_f16_1d_v2_noret:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_atomic_pk_add_f16 v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%unused = call <2 x half> @llvm.amdgcn.image.atomic.pk.add.f16.1d.v2f16.v2f16(<2 x half> %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
ret float 1.0
}
define amdgpu_ps float @atomic_pk_add_f16_1d_v4(<8 x i32> inreg %rsrc, <4 x half> %data, i32 %s) {
-; GFX12-SDAG-LABEL: atomic_pk_add_f16_1d_v4:
-; GFX12-SDAG: ; %bb.0: ; %main_body
-; GFX12-SDAG-NEXT: image_atomic_pk_add_f16 v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: atomic_pk_add_f16_1d_v4:
-; GFX12-GISEL: ; %bb.0: ; %main_body
-; GFX12-GISEL-NEXT: image_atomic_pk_add_f16 v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: atomic_pk_add_f16_1d_v4:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_atomic_pk_add_f16 v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%out = call <4 x half> @llvm.amdgcn.image.atomic.pk.add.f16.1d.v4f16.v4f16(<4 x half> %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
%out_v2f32 = bitcast <4 x half> %out to <2 x float>
@@ -75,42 +53,26 @@ main_body:
}
define amdgpu_ps float @atomic_pk_add_f16_1d_v4_noret(<8 x i32> inreg %rsrc, <4 x half> %data, i32 %s) {
-; GFX12-SDAG-LABEL: atomic_pk_add_f16_1d_v4_noret:
-; GFX12-SDAG: ; %bb.0: ; %main_body
-; GFX12-SDAG-NEXT: image_atomic_pk_add_f16 v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D
-; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
-; GFX12-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: atomic_pk_add_f16_1d_v4_noret:
-; GFX12-GISEL: ; %bb.0: ; %main_body
-; GFX12-GISEL-NEXT: image_atomic_pk_add_f16 v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
-; GFX12-GISEL-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: atomic_pk_add_f16_1d_v4_noret:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_atomic_pk_add_f16 v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%unused = call <4 x half> @llvm.amdgcn.image.atomic.pk.add.f16.1d.v4f16.v4f16(<4 x half> %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
ret float 1.0
}
define amdgpu_ps float @atomic_pk_add_bf16_1d_v2(<8 x i32> inreg %rsrc, <2 x bfloat> %data, i32 %s) {
-; GFX12-SDAG-LABEL: atomic_pk_add_bf16_1d_v2:
-; GFX12-SDAG: ; %bb.0: ; %main_body
-; GFX12-SDAG-NEXT: image_atomic_pk_add_bf16 v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN
-; GFX12-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: flat_store_b32 v[1:2], v0
-; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
-; GFX12-SDAG-NEXT: s_wait_dscnt 0x0
-; GFX12-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: atomic_pk_add_bf16_1d_v2:
-; GFX12-GISEL: ; %bb.0: ; %main_body
-; GFX12-GISEL-NEXT: image_atomic_pk_add_bf16 v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: flat_store_b32 v[1:2], v0
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
-; GFX12-GISEL-NEXT: s_wait_dscnt 0x0
-; GFX12-GISEL-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: atomic_pk_add_bf16_1d_v2:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_atomic_pk_add_bf16 v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN
+; GFX12PLUS-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: flat_store_b32 v[1:2], v0
+; GFX12PLUS-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX12PLUS-NEXT: s_wait_dscnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%out = call <2 x bfloat> @llvm.amdgcn.image.atomic.pk.add.bf16.1d.v2bf16.v2bf16(<2 x bfloat> %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
store <2 x bfloat> %out, ptr null
@@ -118,42 +80,26 @@ main_body:
}
define amdgpu_ps float @atomic_pk_add_bf16_1d_v2_noret(<8 x i32> inreg %rsrc, <2 x bfloat> %data, i32 %s) {
-; GFX12-SDAG-LABEL: atomic_pk_add_bf16_1d_v2_noret:
-; GFX12-SDAG: ; %bb.0: ; %main_body
-; GFX12-SDAG-NEXT: image_atomic_pk_add_bf16 v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
-; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
-; GFX12-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: atomic_pk_add_bf16_1d_v2_noret:
-; GFX12-GISEL: ; %bb.0: ; %main_body
-; GFX12-GISEL-NEXT: image_atomic_pk_add_bf16 v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
-; GFX12-GISEL-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: atomic_pk_add_bf16_1d_v2_noret:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_atomic_pk_add_bf16 v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%unused = call <2 x bfloat> @llvm.amdgcn.image.atomic.pk.add.bf16.1d.v2bf16.v2bf16(<2 x bfloat> %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
ret float 1.0
}
define amdgpu_ps float @atomic_pk_add_bf16_1d_v4(<8 x i32> inreg %rsrc, <4 x bfloat> %data, i32 %s) {
-; GFX12-SDAG-LABEL: atomic_pk_add_bf16_1d_v4:
-; GFX12-SDAG: ; %bb.0: ; %main_body
-; GFX12-SDAG-NEXT: image_atomic_pk_add_bf16 v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN
-; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: flat_store_b64 v[2:3], v[0:1]
-; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
-; GFX12-SDAG-NEXT: s_wait_dscnt 0x0
-; GFX12-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: atomic_pk_add_bf16_1d_v4:
-; GFX12-GISEL: ; %bb.0: ; %main_body
-; GFX12-GISEL-NEXT: image_atomic_pk_add_bf16 v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: flat_store_b64 v[2:3], v[0:1]
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
-; GFX12-GISEL-NEXT: s_wait_dscnt 0x0
-; GFX12-GISEL-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: atomic_pk_add_bf16_1d_v4:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_atomic_pk_add_bf16 v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN
+; GFX12PLUS-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: flat_store_b64 v[2:3], v[0:1]
+; GFX12PLUS-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX12PLUS-NEXT: s_wait_dscnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%out = call <4 x bfloat> @llvm.amdgcn.image.atomic.pk.add.bf16.1d.v4bf16.v4bf16(<4 x bfloat> %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
store <4 x bfloat> %out, ptr null
@@ -161,34 +107,22 @@ main_body:
}
define amdgpu_ps float @atomic_pk_add_bf16_1d_v4_noret(<8 x i32> inreg %rsrc, <4 x bfloat> %data, i32 %s) {
-; GFX12-SDAG-LABEL: atomic_pk_add_bf16_1d_v4_noret:
-; GFX12-SDAG: ; %bb.0: ; %main_body
-; GFX12-SDAG-NEXT: image_atomic_pk_add_bf16 v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D
-; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
-; GFX12-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: atomic_pk_add_bf16_1d_v4_noret:
-; GFX12-GISEL: ; %bb.0: ; %main_body
-; GFX12-GISEL-NEXT: image_atomic_pk_add_bf16 v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
-; GFX12-GISEL-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: atomic_pk_add_bf16_1d_v4_noret:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_atomic_pk_add_bf16 v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%unused = call <4 x bfloat> @llvm.amdgcn.image.atomic.pk.add.bf16.1d.v4bf16.v4bf16(<4 x bfloat> %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
ret float 1.0
}
define amdgpu_ps float @atomic_pk_add_bf16_1d_v4_nt(<8 x i32> inreg %rsrc, <4 x bfloat> %data, i32 %s) {
-; GFX12-SDAG-LABEL: atomic_pk_add_bf16_1d_v4_nt:
-; GFX12-SDAG: ; %bb.0: ; %main_body
-; GFX12-SDAG-NEXT: image_atomic_pk_add_bf16 v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT
-; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 1.0
-; GFX12-SDAG-NEXT: ; return to shader part epilog
-;
-; GFX12-GISEL-LABEL: atomic_pk_add_bf16_1d_v4_nt:
-; GFX12-GISEL: ; %bb.0: ; %main_body
-; GFX12-GISEL-NEXT: image_atomic_pk_add_bf16 v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
-; GFX12-GISEL-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: atomic_pk_add_bf16_1d_v4_nt:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_atomic_pk_add_bf16 v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT
+; GFX12PLUS-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%unused = call <4 x bfloat> @llvm.amdgcn.image.atomic.pk.add.bf16.1d.v4bf16.v4bf16(<4 x bfloat> %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 2)
ret float 1.0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.d16.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.d16.dim.ll
index dc9b8f122984b..2e575096198be 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.d16.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.d16.dim.ll
@@ -3,12 +3,13 @@
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 | FileCheck -check-prefixes=GCN,PACKED,GFX89 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 | FileCheck -check-prefixes=GCN,GFX10 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 | FileCheck -check-prefixes=GCN,GFX10 %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 | FileCheck -check-prefixes=GCN,GFX12 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 | FileCheck -check-prefixes=GCN,GFX12PLUS %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1310 | FileCheck -check-prefixes=GCN,GFX12PLUS %s
; GCN-LABEL: {{^}}image_load_f16:
; GFX89: image_load v0, v[0:1], s[0:7] dmask:0x1 unorm d16{{$}}
; GFX10: image_load v0, v[0:1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm d16{{$}}
-; GFX12: image_load v0, [v0, v1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D d16
+; GFX12PLUS: image_load v0, [v0, v1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D d16
define amdgpu_ps half @image_load_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
main_body:
%tex = call half @llvm.amdgcn.image.load.2d.f16.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
@@ -20,7 +21,7 @@ main_body:
; PACKED: image_load v0, v[0:1], s[0:7] dmask:0x3 unorm d16{{$}}
; GFX81: image_load v0, v[0:1], s[0:7] dmask:0x3 unorm d16{{$}}
; GFX10: image_load v0, v[0:1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm d16{{$}}
-; GFX12: image_load v0, [v0, v1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D d16
+; GFX12PLUS: image_load v0, [v0, v1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D d16
define amdgpu_ps float @image_load_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
main_body:
%tex = call <2 x half> @llvm.amdgcn.image.load.2d.v2f16.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
@@ -32,7 +33,7 @@ main_body:
; UNPACKED: image_load v[0:2], v[0:1], s[0:7] dmask:0x7 unorm d16{{$}}
; PACKED: image_load v[0:1], v[0:1], s[0:7] dmask:0x7 unorm d16{{$}}
; GFX10: image_load v[0:1], v[0:1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D unorm d16{{$}}
-; GFX12: image_load v[0:1], [v0, v1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D d16
+; GFX12PLUS: image_load v[0:1], [v0, v1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D d16
define amdgpu_ps <2 x float> @image_load_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
main_body:
%tex = call <3 x half> @llvm.amdgcn.image.load.2d.v3f16.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
@@ -46,7 +47,7 @@ main_body:
; PACKED: image_load v[0:1], v[0:1], s[0:7] dmask:0xf unorm d16{{$}}
; GFX81: image_load v[0:1], v[0:1], s[0:7] dmask:0xf unorm d16{{$}}
; GFX10: image_load v[0:1], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm d16{{$}}
-; GFX12: image_load v[0:1], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D d16
+; GFX12PLUS: image_load v[0:1], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D d16
define amdgpu_ps <2 x float> @image_load_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
main_body:
%tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
@@ -59,7 +60,7 @@ main_body:
; PACKED: image_load_mip v[0:1], v[0:2], s[0:7] dmask:0xf unorm d16{{$}}
; GFX81: image_load_mip v[0:1], v[0:2], s[0:7] dmask:0xf unorm d16{{$}}
; GFX10: image_load_mip v[0:1], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm d16{{$}}
-; GFX12: image_load_mip v[0:1], [v0, v1, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D d16
+; GFX12PLUS: image_load_mip v[0:1], [v0, v1, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D d16
define amdgpu_ps <2 x float> @image_load_mip_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %mip) {
main_body:
%tex = call <4 x half> @llvm.amdgcn.image.load.mip.2d.v4f16.i32(i32 15, i32 %s, i32 %t, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
@@ -72,7 +73,7 @@ main_body:
; PACKED: image_load v0, v[0:2], s[0:7] dmask:0x3 unorm d16{{$}}
; GFX81: image_load v0, v[0:2], s[0:7] dmask:0x3 unorm d16{{$}}
; GFX10: image_load v0, v[0:2], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm d16{{$}}
-; GFX12: image_load v0, [v0, v1, v2], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D d16
+; GFX12PLUS: image_load v0, [v0, v1, v2], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D d16
define amdgpu_ps float @image_load_3d_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %r) {
main_body:
%tex = call <2 x half> @llvm.amdgcn.image.load.3d.v2f16.i32(i32 3, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 0, i32 0)
@@ -86,7 +87,7 @@ main_body:
; PACKED: image_load v[0:1], v[0:2], s[0:7] dmask:0x7 unorm d16
; GFX81: image_load v[0:1], v[0:2], s[0:7] dmask:0x7 unorm d16
; GFX10: image_load v[0:1], v[0:2], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_3D unorm d16{{$}}
-; GFX12: image_load v[0:1], [v0, v1, v2], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_3D d16
+; GFX12PLUS: image_load v[0:1], [v0, v1, v2], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_3D d16
define amdgpu_ps <2 x float> @image_load_3d_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %r) {
main_body:
%tex = call <3 x half> @llvm.amdgcn.image.load.3d.v3f16.i32(i32 7, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 0, i32 0)
@@ -98,7 +99,7 @@ main_body:
; GCN-LABEL: {{^}}image_store_f16
; GFX89: image_store v2, v[0:1], s[0:7] dmask:0x1 unorm d16{{$}}
; GFX10: image_store v2, v[0:1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm d16{{$}}
-; GFX12: image_store v2, [v0, v1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D d16
+; GFX12PLUS: image_store v2, [v0, v1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D d16
define amdgpu_ps void @image_store_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, half %data) {
main_body:
call void @llvm.amdgcn.image.store.2d.f16.i32(half %data, i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
@@ -112,7 +113,7 @@ main_body:
; PACKED: image_store v2, v[0:1], s[0:7] dmask:0x3 unorm d16{{$}}
; GFX81: image_store v[2:3], v[0:1], s[0:7] dmask:0x3 unorm d16{{$}}
; GFX10: image_store v2, v[0:1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm d16{{$}}
-; GFX12: image_store v2, [v0, v1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D d16
+; GFX12PLUS: image_store v2, [v0, v1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D d16
define amdgpu_ps void @image_store_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, float %in) {
main_body:
%data = bitcast float %in to <2 x half>
@@ -125,7 +126,7 @@ main_body:
; PACKED: image_store v[2:3], v[0:1], s[0:7] dmask:0x7 unorm d16
; GFX81: image_store v[2:4], v[0:1], s[0:7] dmask:0x7 unorm d16
; GFX10: image_store v[2:3], v[0:1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D unorm d16{{$}}
-; GFX12: image_store v[2:3], [v0, v1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D d16
+; GFX12PLUS: image_store v[2:3], [v0, v1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D d16
define amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <2 x float> %in) {
main_body:
%r = bitcast <2 x float> %in to <4 x half>
@@ -143,7 +144,7 @@ main_body:
; PACKED: image_store v[2:3], v[0:1], s[0:7] dmask:0xf unorm d16{{$}}
; GFX81: image_store v[2:5], v[0:1], s[0:7] dmask:0xf unorm d16{{$}}
; GFX10: image_store v[2:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm d16{{$}}
-; GFX12: image_store v[2:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D d16
+; GFX12PLUS: image_store v[2:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D d16
define amdgpu_ps void @image_store_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <2 x float> %in) {
main_body:
%data = bitcast <2 x float> %in to <4 x half>
@@ -160,7 +161,7 @@ main_body:
; PACKED: image_store_mip v[2:3], v[0:1], s[0:7] dmask:0xf unorm d16{{$}}
; GFX81: image_store_mip v[2:5], v[0:1], s[0:7] dmask:0xf unorm d16{{$}}
; GFX10: image_store_mip v[2:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm d16{{$}}
-; GFX12: image_store_mip v[2:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D d16
+; GFX12PLUS: image_store_mip v[2:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D d16
define amdgpu_ps void @image_store_mip_1d_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %mip, <2 x float> %in) {
main_body:
%data = bitcast <2 x float> %in to <4 x half>
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
index 4d9f0943a802d..f1278ececbe03 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
@@ -5,7 +5,8 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-enable-prt-strict-null < %s | FileCheck -check-prefixes=NOPRT %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX13 %s
define amdgpu_ps <4 x float> @load_1d(<8 x i32> inreg %rsrc, i32 %s) {
; VERDE-LABEL: load_1d:
@@ -38,11 +39,11 @@ define amdgpu_ps <4 x float> @load_1d(<8 x i32> inreg %rsrc, i32 %s) {
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -143,18 +144,18 @@ define amdgpu_ps <4 x float> @load_1d_tfe(<8 x i32> inreg %rsrc, ptr addrspace(1
; GFX11-NEXT: global_store_b32 v6, v4, s[8:9]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_tfe:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, 0
-; GFX12-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6
-; GFX12-NEXT: v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v6
-; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
-; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
-; GFX12-NEXT: v_mov_b32_e32 v4, v10
-; GFX12-NEXT: image_load v[0:4], v5, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D tfe
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: global_store_b32 v6, v4, s[8:9]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_tfe:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, 0
+; GFX12PLUS-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6
+; GFX12PLUS-NEXT: v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v6
+; GFX12PLUS-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GFX12PLUS-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
+; GFX12PLUS-NEXT: v_mov_b32_e32 v4, v10
+; GFX12PLUS-NEXT: image_load v[0:4], v5, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D tfe
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: global_store_b32 v6, v4, s[8:9]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.load.1d.v4f32i32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
@@ -258,13 +259,13 @@ define amdgpu_ps <4 x float> @load_1d_lwe(<8 x i32> inreg %rsrc, ptr addrspace(1
; GFX11-NEXT: global_store_b32 v6, v4, s[8:9]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_lwe:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:4], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: v_mov_b32_e32 v5, 0
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: global_store_b32 v5, v4, s[8:9]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_lwe:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:4], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: v_mov_b32_e32 v5, 0
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: global_store_b32 v5, v4, s[8:9]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>, i32} @llvm.amdgcn.image.load.1d.v4f32i32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 2, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
@@ -304,11 +305,11 @@ define amdgpu_ps <4 x float> @load_2d(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -426,6 +427,20 @@ define amdgpu_ps <4 x float> @load_2d_tfe(<8 x i32> inreg %rsrc, ptr addrspace(1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b32 v7, v4, s[8:9]
; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX13-LABEL: load_2d_tfe:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v5, v1
+; GFX13-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v8, v7
+; GFX13-NEXT: v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v10, v7
+; GFX13-NEXT: v_mov_b32_e32 v11, v7
+; GFX13-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8
+; GFX13-NEXT: v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10
+; GFX13-NEXT: v_mov_b32_e32 v4, v11
+; GFX13-NEXT: image_load v[0:4], [v6, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D tfe
+; GFX13-NEXT: s_wait_loadcnt 0x0
+; GFX13-NEXT: global_store_b32 v7, v4, s[8:9]
+; GFX13-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.load.2d.v4f32i32.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
@@ -465,11 +480,11 @@ define amdgpu_ps <4 x float> @load_3d(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], [v0, v1, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], [v0, v1, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -579,19 +594,19 @@ define amdgpu_ps <4 x float> @load_3d_tfe_lwe(<8 x i32> inreg %rsrc, ptr addrspa
; GFX11-NEXT: global_store_b32 v8, v4, s[8:9]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_3d_tfe_lwe:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_dual_mov_b32 v7, v0 :: v_dual_mov_b32 v8, 0
-; GFX12-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v6, v1
-; GFX12-NEXT: v_dual_mov_b32 v9, v8 :: v_dual_mov_b32 v10, v8
-; GFX12-NEXT: v_dual_mov_b32 v11, v8 :: v_dual_mov_b32 v12, v8
-; GFX12-NEXT: v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9
-; GFX12-NEXT: v_dual_mov_b32 v2, v10 :: v_dual_mov_b32 v3, v11
-; GFX12-NEXT: v_mov_b32_e32 v4, v12
-; GFX12-NEXT: image_load v[0:4], [v7, v6, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D tfe
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: global_store_b32 v8, v4, s[8:9]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_3d_tfe_lwe:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: v_dual_mov_b32 v7, v0 :: v_dual_mov_b32 v8, 0
+; GFX12PLUS-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v6, v1
+; GFX12PLUS-NEXT: v_dual_mov_b32 v9, v8 :: v_dual_mov_b32 v10, v8
+; GFX12PLUS-NEXT: v_dual_mov_b32 v11, v8 :: v_dual_mov_b32 v12, v8
+; GFX12PLUS-NEXT: v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9
+; GFX12PLUS-NEXT: v_dual_mov_b32 v2, v10 :: v_dual_mov_b32 v3, v11
+; GFX12PLUS-NEXT: v_mov_b32_e32 v4, v12
+; GFX12PLUS-NEXT: image_load v[0:4], [v7, v6, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D tfe
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: global_store_b32 v8, v4, s[8:9]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.load.3d.v4f32i32.i32(i32 15, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 3, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
@@ -631,11 +646,11 @@ define amdgpu_ps <4 x float> @load_cube(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_cube:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], [v0, v1, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_cube:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], [v0, v1, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.cube.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -745,13 +760,13 @@ define amdgpu_ps <4 x float> @load_cube_lwe(<8 x i32> inreg %rsrc, ptr addrspace
; GFX11-NEXT: global_store_b32 v8, v4, s[8:9]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_cube_lwe:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:4], [v0, v1, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE
-; GFX12-NEXT: v_mov_b32_e32 v5, 0
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: global_store_b32 v5, v4, s[8:9]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_cube_lwe:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:4], [v0, v1, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE
+; GFX12PLUS-NEXT: v_mov_b32_e32 v5, 0
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: global_store_b32 v5, v4, s[8:9]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.load.cube.v4f32i32.i32(i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 2, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
@@ -791,11 +806,11 @@ define amdgpu_ps <4 x float> @load_1darray(<8 x i32> inreg %rsrc, i32 %s, i32 %s
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.1darray.v4f32.i32(i32 15, i32 %s, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -913,6 +928,20 @@ define amdgpu_ps <4 x float> @load_1darray_tfe(<8 x i32> inreg %rsrc, ptr addrsp
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b32 v7, v4, s[8:9]
; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX13-LABEL: load_1darray_tfe:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v5, v1
+; GFX13-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v8, v7
+; GFX13-NEXT: v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v10, v7
+; GFX13-NEXT: v_mov_b32_e32 v11, v7
+; GFX13-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8
+; GFX13-NEXT: v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10
+; GFX13-NEXT: v_mov_b32_e32 v4, v11
+; GFX13-NEXT: image_load v[0:4], [v6, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY tfe
+; GFX13-NEXT: s_wait_loadcnt 0x0
+; GFX13-NEXT: global_store_b32 v7, v4, s[8:9]
+; GFX13-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.load.1darray.v4f32i32.i32(i32 15, i32 %s, i32 %slice, <8 x i32> %rsrc, i32 1, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
@@ -952,11 +981,11 @@ define amdgpu_ps <4 x float> @load_2darray(<8 x i32> inreg %rsrc, i32 %s, i32 %t
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], [v0, v1, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], [v0, v1, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.2darray.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -1066,13 +1095,13 @@ define amdgpu_ps <4 x float> @load_2darray_lwe(<8 x i32> inreg %rsrc, ptr addrsp
; GFX11-NEXT: global_store_b32 v8, v4, s[8:9]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2darray_lwe:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:4], [v0, v1, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX12-NEXT: v_mov_b32_e32 v5, 0
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: global_store_b32 v5, v4, s[8:9]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2darray_lwe:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:4], [v0, v1, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12PLUS-NEXT: v_mov_b32_e32 v5, 0
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: global_store_b32 v5, v4, s[8:9]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.load.2darray.v4f32i32.i32(i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 2, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
@@ -1112,11 +1141,11 @@ define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2dmsaa:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], [v0, v1, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2dmsaa:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], [v0, v1, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.2dmsaa.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -1226,19 +1255,19 @@ define amdgpu_ps <4 x float> @load_2dmsaa_both(<8 x i32> inreg %rsrc, ptr addrsp
; GFX11-NEXT: global_store_b32 v8, v4, s[8:9]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2dmsaa_both:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_dual_mov_b32 v7, v0 :: v_dual_mov_b32 v8, 0
-; GFX12-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v6, v1
-; GFX12-NEXT: v_dual_mov_b32 v9, v8 :: v_dual_mov_b32 v10, v8
-; GFX12-NEXT: v_dual_mov_b32 v11, v8 :: v_dual_mov_b32 v12, v8
-; GFX12-NEXT: v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9
-; GFX12-NEXT: v_dual_mov_b32 v2, v10 :: v_dual_mov_b32 v3, v11
-; GFX12-NEXT: v_mov_b32_e32 v4, v12
-; GFX12-NEXT: image_load v[0:4], [v7, v6, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA tfe
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: global_store_b32 v8, v4, s[8:9]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2dmsaa_both:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: v_dual_mov_b32 v7, v0 :: v_dual_mov_b32 v8, 0
+; GFX12PLUS-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v6, v1
+; GFX12PLUS-NEXT: v_dual_mov_b32 v9, v8 :: v_dual_mov_b32 v10, v8
+; GFX12PLUS-NEXT: v_dual_mov_b32 v11, v8 :: v_dual_mov_b32 v12, v8
+; GFX12PLUS-NEXT: v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9
+; GFX12PLUS-NEXT: v_dual_mov_b32 v2, v10 :: v_dual_mov_b32 v3, v11
+; GFX12PLUS-NEXT: v_mov_b32_e32 v4, v12
+; GFX12PLUS-NEXT: image_load v[0:4], [v7, v6, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA tfe
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: global_store_b32 v8, v4, s[8:9]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.load.2dmsaa.v4f32i32.i32(i32 15, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 3, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
@@ -1278,11 +1307,11 @@ define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, i32 %s, i3
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2darraymsaa:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], [v0, v1, v2, v3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2darraymsaa:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], [v0, v1, v2, v3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -1410,6 +1439,21 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> inreg %rsrc, ptr ad
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b32 v9, v4, s[8:9]
; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX13-LABEL: load_2darraymsaa_tfe:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v5, v3
+; GFX13-NEXT: v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v7, v1
+; GFX13-NEXT: v_dual_mov_b32 v8, v0 :: v_dual_mov_b32 v10, v9
+; GFX13-NEXT: v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v12, v9
+; GFX13-NEXT: v_mov_b32_e32 v13, v9
+; GFX13-NEXT: v_dual_mov_b32 v0, v9 :: v_dual_mov_b32 v1, v10
+; GFX13-NEXT: v_dual_mov_b32 v2, v11 :: v_dual_mov_b32 v3, v12
+; GFX13-NEXT: v_mov_b32_e32 v4, v13
+; GFX13-NEXT: image_load v[0:4], [v8, v7, v6, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY tfe
+; GFX13-NEXT: s_wait_loadcnt 0x0
+; GFX13-NEXT: global_store_b32 v9, v4, s[8:9]
+; GFX13-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.load.2darraymsaa.v4f32i32.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 1, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
@@ -1449,11 +1493,11 @@ define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, i32 %s, i32 %mi
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load_mip v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i32(i32 15, i32 %s, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -1558,13 +1602,13 @@ define amdgpu_ps <4 x float> @load_mip_1d_lwe(<8 x i32> inreg %rsrc, ptr addrspa
; GFX11-NEXT: global_store_b32 v7, v4, s[8:9]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_1d_lwe:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load_mip v[0:4], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: v_mov_b32_e32 v5, 0
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: global_store_b32 v5, v4, s[8:9]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_1d_lwe:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load_mip v[0:4], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: v_mov_b32_e32 v5, 0
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: global_store_b32 v5, v4, s[8:9]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.load.mip.1d.v4f32i32.i32(i32 15, i32 %s, i32 %mip, <8 x i32> %rsrc, i32 2, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
@@ -1604,11 +1648,11 @@ define amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load_mip v[0:3], [v0, v1, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load_mip v[0:3], [v0, v1, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -1718,19 +1762,19 @@ define amdgpu_ps <4 x float> @load_mip_2d_tfe(<8 x i32> inreg %rsrc, ptr addrspa
; GFX11-NEXT: global_store_b32 v8, v4, s[8:9]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_2d_tfe:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_dual_mov_b32 v7, v0 :: v_dual_mov_b32 v8, 0
-; GFX12-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v6, v1
-; GFX12-NEXT: v_dual_mov_b32 v9, v8 :: v_dual_mov_b32 v10, v8
-; GFX12-NEXT: v_dual_mov_b32 v11, v8 :: v_dual_mov_b32 v12, v8
-; GFX12-NEXT: v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9
-; GFX12-NEXT: v_dual_mov_b32 v2, v10 :: v_dual_mov_b32 v3, v11
-; GFX12-NEXT: v_mov_b32_e32 v4, v12
-; GFX12-NEXT: image_load_mip v[0:4], [v7, v6, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D tfe
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: global_store_b32 v8, v4, s[8:9]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_2d_tfe:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: v_dual_mov_b32 v7, v0 :: v_dual_mov_b32 v8, 0
+; GFX12PLUS-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v6, v1
+; GFX12PLUS-NEXT: v_dual_mov_b32 v9, v8 :: v_dual_mov_b32 v10, v8
+; GFX12PLUS-NEXT: v_dual_mov_b32 v11, v8 :: v_dual_mov_b32 v12, v8
+; GFX12PLUS-NEXT: v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9
+; GFX12PLUS-NEXT: v_dual_mov_b32 v2, v10 :: v_dual_mov_b32 v3, v11
+; GFX12PLUS-NEXT: v_mov_b32_e32 v4, v12
+; GFX12PLUS-NEXT: image_load_mip v[0:4], [v7, v6, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D tfe
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: global_store_b32 v8, v4, s[8:9]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.load.mip.2d.v4f32i32.i32(i32 15, i32 %s, i32 %t, i32 %mip, <8 x i32> %rsrc, i32 1, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
@@ -1784,14 +1828,14 @@ define amdgpu_ps float @load_1d_V2_tfe_dmask0(<8 x i32> inreg %rsrc, i32 %s) {
; GFX10PLUS-NEXT: v_mov_b32_e32 v0, v2
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_V2_tfe_dmask0:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-NEXT: v_mov_b32_e32 v2, v1
-; GFX12-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v0, v2
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_V2_tfe_dmask0:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: v_mov_b32_e32 v1, 0
+; GFX12PLUS-NEXT: v_mov_b32_e32 v2, v1
+; GFX12PLUS-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: v_mov_b32_e32 v0, v2
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<2 x float>,i32} @llvm.amdgcn.image.load.1d.v2f32i32.i32(i32 0, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
%v.err = extractvalue {<2 x float>, i32} %v, 1
@@ -1844,14 +1888,14 @@ define amdgpu_ps float @load_1d_V1_tfe_dmask0(<8 x i32> inreg %rsrc, i32 %s) {
; GFX10PLUS-NEXT: v_mov_b32_e32 v0, v2
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_V1_tfe_dmask0:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-NEXT: v_mov_b32_e32 v2, v1
-; GFX12-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v0, v2
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_V1_tfe_dmask0:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: v_mov_b32_e32 v1, 0
+; GFX12PLUS-NEXT: v_mov_b32_e32 v2, v1
+; GFX12PLUS-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: v_mov_b32_e32 v0, v2
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {float,i32} @llvm.amdgcn.image.load.1d.f32i32.i32(i32 0, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
%v.err = extractvalue {float, i32} %v, 1
@@ -1904,14 +1948,14 @@ define amdgpu_ps float @load_mip_2d_tfe_dmask0(<8 x i32> inreg %rsrc, i32 %s, i3
; GFX10PLUS-NEXT: v_mov_b32_e32 v0, v4
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_2d_tfe_dmask0:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_mov_b32_e32 v3, 0
-; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: image_load_mip v[3:4], [v0, v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v0, v4
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_2d_tfe_dmask0:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: v_mov_b32_e32 v3, 0
+; GFX12PLUS-NEXT: v_mov_b32_e32 v4, v3
+; GFX12PLUS-NEXT: image_load_mip v[3:4], [v0, v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: v_mov_b32_e32 v0, v4
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.load.mip.2d.v4f32i32.i32(i32 0, i32 %s, i32 %t, i32 %mip, <8 x i32> %rsrc, i32 1, i32 0)
%v.err = extractvalue {<4 x float>, i32} %v, 1
@@ -1964,14 +2008,14 @@ define amdgpu_ps float @load_mip_2d_tfe_nouse(<8 x i32> inreg %rsrc, i32 %s, i32
; GFX10PLUS-NEXT: v_mov_b32_e32 v0, v4
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_2d_tfe_nouse:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_mov_b32_e32 v3, 0
-; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: image_load_mip v[3:4], [v0, v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v0, v4
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_2d_tfe_nouse:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: v_mov_b32_e32 v3, 0
+; GFX12PLUS-NEXT: v_mov_b32_e32 v4, v3
+; GFX12PLUS-NEXT: image_load_mip v[3:4], [v0, v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: v_mov_b32_e32 v0, v4
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.load.mip.2d.v4f32i32.i32(i32 15, i32 %s, i32 %t, i32 %mip, <8 x i32> %rsrc, i32 1, i32 0)
%v.err = extractvalue {<4 x float>, i32} %v, 1
@@ -2024,14 +2068,14 @@ define amdgpu_ps float @load_mip_2d_tfe_nouse_V2(<8 x i32> inreg %rsrc, i32 %s,
; GFX10PLUS-NEXT: v_mov_b32_e32 v0, v4
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_2d_tfe_nouse_V2:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_mov_b32_e32 v3, 0
-; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: image_load_mip v[3:4], [v0, v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v0, v4
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_2d_tfe_nouse_V2:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: v_mov_b32_e32 v3, 0
+; GFX12PLUS-NEXT: v_mov_b32_e32 v4, v3
+; GFX12PLUS-NEXT: image_load_mip v[3:4], [v0, v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: v_mov_b32_e32 v0, v4
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<2 x float>,i32} @llvm.amdgcn.image.load.mip.2d.v2f32i32.i32(i32 6, i32 %s, i32 %t, i32 %mip, <8 x i32> %rsrc, i32 1, i32 0)
%v.err = extractvalue {<2 x float>, i32} %v, 1
@@ -2084,14 +2128,14 @@ define amdgpu_ps float @load_mip_2d_tfe_nouse_V1(<8 x i32> inreg %rsrc, i32 %s,
; GFX10PLUS-NEXT: v_mov_b32_e32 v0, v4
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_2d_tfe_nouse_V1:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_mov_b32_e32 v3, 0
-; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: image_load_mip v[3:4], [v0, v1, v2], s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_2D tfe
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v0, v4
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_2d_tfe_nouse_V1:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: v_mov_b32_e32 v3, 0
+; GFX12PLUS-NEXT: v_mov_b32_e32 v4, v3
+; GFX12PLUS-NEXT: image_load_mip v[3:4], [v0, v1, v2], s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_2D tfe
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: v_mov_b32_e32 v0, v4
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {float, i32} @llvm.amdgcn.image.load.mip.2d.f32i32.i32(i32 2, i32 %s, i32 %t, i32 %mip, <8 x i32> %rsrc, i32 1, i32 0)
%v.err = extractvalue {float, i32} %v, 1
@@ -2186,17 +2230,17 @@ define amdgpu_ps <4 x float> @load_1d_tfe_V4_dmask3(<8 x i32> inreg %rsrc, ptr a
; GFX11-NEXT: global_store_b32 v5, v3, s[8:9]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_tfe_V4_dmask3:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_dual_mov_b32 v4, v0 :: v_dual_mov_b32 v5, 0
-; GFX12-NEXT: v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v7, v5
-; GFX12-NEXT: v_mov_b32_e32 v8, v5
-; GFX12-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
-; GFX12-NEXT: v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
-; GFX12-NEXT: image_load v[0:3], v4, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D tfe
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: global_store_b32 v5, v3, s[8:9]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_tfe_V4_dmask3:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: v_dual_mov_b32 v4, v0 :: v_dual_mov_b32 v5, 0
+; GFX12PLUS-NEXT: v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v7, v5
+; GFX12PLUS-NEXT: v_mov_b32_e32 v8, v5
+; GFX12PLUS-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX12PLUS-NEXT: v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
+; GFX12PLUS-NEXT: image_load v[0:3], v4, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D tfe
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: global_store_b32 v5, v3, s[8:9]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.load.1d.v4f32i32.i32(i32 7, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
@@ -2285,16 +2329,16 @@ define amdgpu_ps <4 x float> @load_1d_tfe_V4_dmask2(<8 x i32> inreg %rsrc, ptr a
; GFX11-NEXT: global_store_b32 v4, v2, s[8:9]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_tfe_V4_dmask2:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v4, 0
-; GFX12-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
-; GFX12-NEXT: v_mov_b32_e32 v2, v6
-; GFX12-NEXT: image_load v[0:2], v3, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D tfe
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: global_store_b32 v4, v2, s[8:9]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_tfe_V4_dmask2:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v4, 0
+; GFX12PLUS-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
+; GFX12PLUS-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX12PLUS-NEXT: v_mov_b32_e32 v2, v6
+; GFX12PLUS-NEXT: image_load v[0:2], v3, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D tfe
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: global_store_b32 v4, v2, s[8:9]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.load.1d.v4f32i32.i32(i32 6, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
@@ -2375,15 +2419,15 @@ define amdgpu_ps <4 x float> @load_1d_tfe_V4_dmask1(<8 x i32> inreg %rsrc, ptr a
; GFX11-NEXT: global_store_b32 v3, v1, s[8:9]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_tfe_V4_dmask1:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, 0
-; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_mov_b32 v1, v4
-; GFX12-NEXT: image_load v[0:1], v2, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D tfe
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: global_store_b32 v3, v1, s[8:9]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_tfe_V4_dmask1:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, 0
+; GFX12PLUS-NEXT: v_mov_b32_e32 v4, v3
+; GFX12PLUS-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_mov_b32 v1, v4
+; GFX12PLUS-NEXT: image_load v[0:1], v2, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D tfe
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: global_store_b32 v3, v1, s[8:9]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.load.1d.v4f32i32.i32(i32 8, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
@@ -2464,15 +2508,15 @@ define amdgpu_ps <2 x float> @load_1d_tfe_V2_dmask1(<8 x i32> inreg %rsrc, ptr a
; GFX11-NEXT: global_store_b32 v3, v1, s[8:9]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_tfe_V2_dmask1:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, 0
-; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_mov_b32 v1, v4
-; GFX12-NEXT: image_load v[0:1], v2, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D tfe
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: global_store_b32 v3, v1, s[8:9]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_tfe_V2_dmask1:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, 0
+; GFX12PLUS-NEXT: v_mov_b32_e32 v4, v3
+; GFX12PLUS-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_mov_b32 v1, v4
+; GFX12PLUS-NEXT: image_load v[0:1], v2, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D tfe
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: global_store_b32 v3, v1, s[8:9]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<2 x float>,i32} @llvm.amdgcn.image.load.1d.v2f32i32.i32(i32 8, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
%v.vec = extractvalue {<2 x float>, i32} %v, 0
@@ -2513,11 +2557,11 @@ define amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load_mip v[0:3], [v0, v1, v2, v3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load_mip v[0:3], [v0, v1, v2, v3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.mip.3d.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %r, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -2554,11 +2598,11 @@ define amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, i32 %s, i32 %
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_cube:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load_mip v[0:3], [v0, v1, v2, v3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_cube:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load_mip v[0:3], [v0, v1, v2, v3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.mip.cube.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -2595,11 +2639,11 @@ define amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, i32 %s, i3
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_1darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load_mip v[0:3], [v0, v1, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_1darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load_mip v[0:3], [v0, v1, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.mip.1darray.v4f32.i32(i32 15, i32 %s, i32 %slice, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -2636,11 +2680,11 @@ define amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, i32 %s, i3
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_mip_2darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load_mip v[0:3], [v0, v1, v2, v3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_mip_2darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load_mip v[0:3], [v0, v1, v2, v3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.mip.2darray.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -2672,10 +2716,10 @@ define amdgpu_ps void @store_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %
; GFX10PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
ret void
@@ -2707,10 +2751,10 @@ define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %
; GFX10PLUS-NEXT: image_store v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
ret void
@@ -2742,10 +2786,10 @@ define amdgpu_ps void @store_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %
; GFX10PLUS-NEXT: image_store v[0:3], v[4:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], [v4, v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], [v4, v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.3d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 0, i32 0)
ret void
@@ -2777,10 +2821,10 @@ define amdgpu_ps void @store_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32
; GFX10PLUS-NEXT: image_store v[0:3], v[4:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_cube:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], [v4, v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_cube:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], [v4, v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.cube.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)
ret void
@@ -2812,10 +2856,10 @@ define amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata,
; GFX10PLUS-NEXT: image_store v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_1darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_1darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.1darray.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)
ret void
@@ -2847,10 +2891,10 @@ define amdgpu_ps void @store_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata,
; GFX10PLUS-NEXT: image_store v[0:3], v[4:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_2darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], [v4, v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_2darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], [v4, v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.2darray.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)
ret void
@@ -2882,10 +2926,10 @@ define amdgpu_ps void @store_2dmsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, i
; GFX10PLUS-NEXT: image_store v[0:3], v[4:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA unorm
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_2dmsaa:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], [v4, v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_2dmsaa:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], [v4, v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.2dmsaa.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
ret void
@@ -2917,10 +2961,10 @@ define amdgpu_ps void @store_2darraymsaa(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX10PLUS-NEXT: image_store v[0:3], v[4:7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_2darraymsaa:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], [v4, v5, v6, v7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_2darraymsaa:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], [v4, v5, v6, v7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.2darraymsaa.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
ret void
@@ -2952,10 +2996,10 @@ define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i
; GFX10PLUS-NEXT: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_mip_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_mip_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store_mip v[0:3], [v4, v5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.mip.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret void
@@ -2987,10 +3031,10 @@ define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i
; GFX10PLUS-NEXT: image_store_mip v[0:3], v[4:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_mip_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store_mip v[0:3], [v4, v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_mip_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store_mip v[0:3], [v4, v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.mip.2d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret void
@@ -3022,10 +3066,10 @@ define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i
; GFX10PLUS-NEXT: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_mip_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store_mip v[0:3], [v4, v5, v6, v7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_mip_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store_mip v[0:3], [v4, v5, v6, v7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.mip.3d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %r, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret void
@@ -3057,10 +3101,10 @@ define amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata,
; GFX10PLUS-NEXT: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_mip_cube:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store_mip v[0:3], [v4, v5, v6, v7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_mip_cube:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store_mip v[0:3], [v4, v5, v6, v7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.mip.cube.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %slice, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret void
@@ -3092,10 +3136,10 @@ define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX10PLUS-NEXT: image_store_mip v[0:3], v[4:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_mip_1darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store_mip v[0:3], [v4, v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_mip_1darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store_mip v[0:3], [v4, v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.mip.1darray.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %slice, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret void
@@ -3127,10 +3171,10 @@ define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX10PLUS-NEXT: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_mip_2darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store_mip v[0:3], [v4, v5, v6, v7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_mip_2darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store_mip v[0:3], [v4, v5, v6, v7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.mip.2darray.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %slice, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret void
@@ -3167,11 +3211,11 @@ define amdgpu_ps <4 x float> @getresinfo_1d(<8 x i32> inreg %rsrc, i32 %mip) {
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i32(i32 15, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -3208,11 +3252,11 @@ define amdgpu_ps <4 x float> @getresinfo_2d(<8 x i32> inreg %rsrc, i32 %mip) {
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2d.v4f32.i32(i32 15, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -3249,11 +3293,11 @@ define amdgpu_ps <4 x float> @getresinfo_3d(<8 x i32> inreg %rsrc, i32 %mip) {
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.3d.v4f32.i32(i32 15, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -3290,11 +3334,11 @@ define amdgpu_ps <4 x float> @getresinfo_cube(<8 x i32> inreg %rsrc, i32 %mip) {
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_cube:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_cube:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.cube.v4f32.i32(i32 15, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -3331,11 +3375,11 @@ define amdgpu_ps <4 x float> @getresinfo_1darray(<8 x i32> inreg %rsrc, i32 %mip
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_1darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_1darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.1darray.v4f32.i32(i32 15, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -3372,11 +3416,11 @@ define amdgpu_ps <4 x float> @getresinfo_2darray(<8 x i32> inreg %rsrc, i32 %mip
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_2darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_2darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2darray.v4f32.i32(i32 15, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -3413,11 +3457,11 @@ define amdgpu_ps <4 x float> @getresinfo_2dmsaa(<8 x i32> inreg %rsrc, i32 %mip)
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_2dmsaa:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_2dmsaa:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2dmsaa.v4f32.i32(i32 15, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -3454,11 +3498,11 @@ define amdgpu_ps <4 x float> @getresinfo_2darraymsaa(<8 x i32> inreg %rsrc, i32
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_2darraymsaa:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_2darraymsaa:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2darraymsaa.v4f32.i32(i32 15, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -3495,11 +3539,11 @@ define amdgpu_ps float @load_1d_V1(<8 x i32> inreg %rsrc, i32 %s) {
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_V1:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v0, v0, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_V1:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v0, v0, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call float @llvm.amdgcn.image.load.1d.f32.i32(i32 8, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
ret float %v
@@ -3536,11 +3580,11 @@ define amdgpu_ps <2 x float> @load_1d_V2(<8 x i32> inreg %rsrc, i32 %s) {
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_V2:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x9 dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_V2:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x9 dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i32(i32 9, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
ret <2 x float> %v
@@ -3572,10 +3616,10 @@ define amdgpu_ps void @store_1d_V1(<8 x i32> inreg %rsrc, float %vdata, i32 %s)
; GFX10PLUS-NEXT: image_store v0, v1, s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_1d_V1:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v0, v1, s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_1d_V1:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v0, v1, s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.1d.f32.i32(float %vdata, i32 2, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
ret void
@@ -3607,10 +3651,10 @@ define amdgpu_ps void @store_1d_V2(<8 x i32> inreg %rsrc, <2 x float> %vdata, i3
; GFX10PLUS-NEXT: image_store v[0:1], v2, s[0:7] dmask:0xc dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_1d_V2:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:1], v2, s[0:7] dmask:0xc dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_1d_V2:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:1], v2, s[0:7] dmask:0xc dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.1d.v2f32.i32(<2 x float> %vdata, i32 12, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
ret void
@@ -3647,11 +3691,11 @@ define amdgpu_ps <4 x float> @load_1d_glc(<8 x i32> inreg %rsrc, i32 %s) {
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_glc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_glc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 1)
ret <4 x float> %v
@@ -3688,11 +3732,11 @@ define amdgpu_ps <4 x float> @load_1d_slc(<8 x i32> inreg %rsrc, i32 %s) {
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_slc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_HT
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_slc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_HT
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 2)
ret <4 x float> %v
@@ -3729,11 +3773,11 @@ define amdgpu_ps <4 x float> @load_1d_glc_slc(<8 x i32> inreg %rsrc, i32 %s) {
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_1d_glc_slc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_LU
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_1d_glc_slc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_LU
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 3)
ret <4 x float> %v
@@ -3765,10 +3809,10 @@ define amdgpu_ps void @store_1d_glc(<8 x i32> inreg %rsrc, <4 x float> %vdata, i
; GFX10PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm glc
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_1d_glc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_NT
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_1d_glc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_NT
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 1)
ret void
@@ -3800,10 +3844,10 @@ define amdgpu_ps void @store_1d_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, i
; GFX10PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm slc
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_1d_slc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_HT
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_1d_slc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_HT
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 2)
ret void
@@ -3835,10 +3879,10 @@ define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdat
; GFX10PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm glc slc
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: store_1d_glc_slc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_WB
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_1d_glc_slc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_WB
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 3)
ret void
@@ -3875,11 +3919,11 @@ define amdgpu_ps <3 x float> @getresinfo_dmask7(<8 x i32> inreg %rsrc, <4 x floa
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_dmask7:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_get_resinfo v[0:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_dmask7:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_get_resinfo v[0:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%r = call <3 x float> @llvm.amdgcn.image.getresinfo.1d.v3f32.i32(i32 7, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret <3 x float> %r
@@ -3916,11 +3960,11 @@ define amdgpu_ps <2 x float> @getresinfo_dmask3(<8 x i32> inreg %rsrc, <4 x floa
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_dmask3:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_get_resinfo v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_dmask3:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_get_resinfo v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%r = call <2 x float> @llvm.amdgcn.image.getresinfo.1d.v2f32.i32(i32 3, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret <2 x float> %r
@@ -3957,11 +4001,11 @@ define amdgpu_ps float @getresinfo_dmask1(<8 x i32> inreg %rsrc, <4 x float> %vd
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_dmask1:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_get_resinfo v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_dmask1:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_get_resinfo v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%r = call float @llvm.amdgcn.image.getresinfo.1d.f32.i32(i32 1, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret float %r
@@ -3988,9 +4032,9 @@ define amdgpu_ps <4 x float> @getresinfo_dmask0(<8 x i32> inreg %rsrc, <4 x floa
; GFX10PLUS: ; %bb.0: ; %main_body
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: getresinfo_dmask0:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: getresinfo_dmask0:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%r = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i32(i32 0, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %r
@@ -4039,13 +4083,13 @@ define amdgpu_ps void @image_store_wait(<8 x i32> inreg %arg, <8 x i32> inreg %a
; GFX10PLUS-NEXT: image_store v[0:3], v4, s[16:23] dmask:0xf dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT: s_endpgm
;
-; GFX12-LABEL: image_store_wait:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: image_load v[0:3], v4, s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: image_store v[0:3], v4, s[16:23] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: image_store_wait:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: image_load v[0:3], v4, s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: image_store v[0:3], v4, s[16:23] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %arg3, i32 15, i32 %arg4, <8 x i32> %arg, i32 0, i32 0)
%data = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %arg4, <8 x i32> %arg1, i32 0, i32 0)
@@ -4118,15 +4162,15 @@ define amdgpu_ps float @image_load_mmo(<8 x i32> inreg %rsrc, ptr addrspace(3) %
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: image_load_mmo:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: image_load v1, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-NEXT: ds_store_2addr_b32 v0, v2, v2 offset1:4
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v0, v1
-; GFX12-NEXT: s_wait_dscnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: image_load_mmo:
+; GFX12PLUS: ; %bb.0:
+; GFX12PLUS-NEXT: image_load v1, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: v_mov_b32_e32 v2, 0
+; GFX12PLUS-NEXT: ds_store_2addr_b32 v0, v2, v2 offset1:4
+; GFX12PLUS-NEXT: s_wait_loadcnt 0x0
+; GFX12PLUS-NEXT: v_mov_b32_e32 v0, v1
+; GFX12PLUS-NEXT: s_wait_dscnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
store float 0.000000e+00, ptr addrspace(3) %lds
%c0 = extractelement <2 x i32> %c, i32 0
%c1 = extractelement <2 x i32> %c, i32 1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
index d45705edce2c8..2b63fe1f79951 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
@@ -3,8 +3,10 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS-FAKE16 %s
define amdgpu_ps <4 x float> @gather4_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {
; GFX9-LABEL: gather4_2d:
@@ -48,25 +50,25 @@ define amdgpu_ps <4 x float> @gather4_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: gather4_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: gather4_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: gather4_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: gather4_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f16(i32 1, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -116,25 +118,25 @@ define amdgpu_ps <4 x float> @gather4_cube(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: gather4_cube:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: gather4_cube:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: gather4_cube:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: gather4_cube:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.cube.v4f32.f16(i32 1, half %s, half %t, half %face, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -184,25 +186,25 @@ define amdgpu_ps <4 x float> @gather4_2darray(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: gather4_2darray:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: gather4_2darray:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: gather4_2darray:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: gather4_2darray:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.2darray.v4f32.f16(i32 1, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -250,25 +252,25 @@ define amdgpu_ps <4 x float> @gather4_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: gather4_c_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_gather4_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: gather4_c_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_gather4_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: gather4_c_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_gather4_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: gather4_c_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_gather4_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.2d.v4f32.f32(i32 1, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -318,25 +320,25 @@ define amdgpu_ps <4 x float> @gather4_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: gather4_cl_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_gather4_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: gather4_cl_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_gather4_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: gather4_cl_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_gather4_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: gather4_cl_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_gather4_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.cl.2d.v4f32.f16(i32 1, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -386,25 +388,25 @@ define amdgpu_ps <4 x float> @gather4_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: gather4_c_cl_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_gather4_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: gather4_c_cl_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_gather4_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: gather4_c_cl_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_gather4_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: gather4_c_cl_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_gather4_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.cl.2d.v4f32.f32(i32 1, float %zcompare, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -452,25 +454,25 @@ define amdgpu_ps <4 x float> @gather4_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: gather4_b_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_gather4_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: gather4_b_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_gather4_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: gather4_b_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_gather4_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: gather4_b_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_gather4_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.b.2d.v4f32.f16.f16(i32 1, half %bias, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -518,25 +520,25 @@ define amdgpu_ps <4 x float> @gather4_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: gather4_c_b_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_gather4_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: gather4_c_b_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_gather4_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: gather4_c_b_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_gather4_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: gather4_c_b_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_gather4_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.2d.v4f32.f16.f16(i32 1, half %bias, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -589,25 +591,25 @@ define amdgpu_ps <4 x float> @gather4_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: gather4_b_cl_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_gather4_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: gather4_b_cl_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_gather4_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: gather4_b_cl_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_gather4_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: gather4_b_cl_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_gather4_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.2d.v4f32.f16.f16(i32 1, half %bias, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -658,25 +660,25 @@ define amdgpu_ps <4 x float> @gather4_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: gather4_c_b_cl_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_gather4_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: gather4_c_b_cl_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_gather4_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: gather4_c_b_cl_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_gather4_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: gather4_c_b_cl_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_gather4_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.2d.v4f32.f16.f16(i32 1, half %bias, float %zcompare, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -714,19 +716,19 @@ define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: gather4_l_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: image_gather4_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: gather4_l_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: image_gather4_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: gather4_l_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: image_gather4_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: gather4_l_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_gather4_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f16(i32 1, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -764,19 +766,19 @@ define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: gather4_c_l_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: image_gather4_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: gather4_c_l_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-FAKE16-NEXT: image_gather4_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: gather4_c_l_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12PLUS-TRUE16-NEXT: image_gather4_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: gather4_c_l_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_gather4_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f32(i32 1, float %zcompare, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -812,19 +814,19 @@ define amdgpu_ps <4 x float> @gather4_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: gather4_lz_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: gather4_lz_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: gather4_lz_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: gather4_lz_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f16(i32 1, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -860,19 +862,19 @@ define amdgpu_ps <4 x float> @gather4_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: gather4_c_lz_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: image_gather4_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: gather4_c_lz_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-FAKE16-NEXT: image_gather4_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: gather4_c_lz_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12PLUS-TRUE16-NEXT: image_gather4_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: gather4_c_lz_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_gather4_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.2d.v4f32.f32(i32 1, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.d16.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.d16.dim.ll
index c0cc07988fe6d..ba8c1ebdae2c6 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.d16.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.d16.dim.ll
@@ -6,7 +6,8 @@
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx10-1-generic --amdhsa-code-object-version=6 | FileCheck -check-prefixes=GCN,GFX10 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 | FileCheck -check-prefixes=GCN,GFX10 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx11-generic --amdhsa-code-object-version=6 | FileCheck -check-prefixes=GCN,GFX10 %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 | FileCheck -check-prefixes=GCN,GFX12 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 | FileCheck -check-prefixes=GCN,GFX12PLUS %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1310 | FileCheck -check-prefixes=GCN,GFX12PLUS %s
; GCN-LABEL: {{^}}image_gather4_b_2d_v4f16:
; UNPACKED: image_gather4_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x4 d16{{$}}
@@ -14,7 +15,7 @@
; GFX810: image_gather4_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x4 d16{{$}}
; GFX9: image_gather4_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x4 d16{{$}}
; GFX10: image_gather4_b v[0:1], v[0:2], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D d16{{$}}
-; GFX12: image_gather4_b v[0:1], [v0, v1, v2], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D d16{{$}}
+; GFX12PLUS: image_gather4_b v[0:1], [v0, v1, v2], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D d16{{$}}
define amdgpu_ps <2 x float> @image_gather4_b_2d_v4f16(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %s, float %t) {
main_body:
%tex = call <4 x half> @llvm.amdgcn.image.gather4.b.2d.v4f16.f32.f32(i32 4, float %bias, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.dim.ll
index f6abd13fb77a1..ef4f34050229d 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.dim.ll
@@ -2,12 +2,13 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,PREGFX12,GFX6789 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,PREGFX12,GFX10 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,PREGFX12,GFX10 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GFX12PLUS %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GFX12PLUS %s
; GCN-LABEL: {{^}}gather4_2d:
; GFX6789: image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1{{$}}
; GFX10: image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
-; GFX12: image_gather4 v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
+; GFX12PLUS: image_gather4 v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
define amdgpu_ps <4 x float> @gather4_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
@@ -22,7 +23,7 @@ main_body:
; PREGFX12: v_mov_b32_e32 v4, v0
; GFX6789: image_gather4 v[0:4], v[5:6], s[0:7], s[8:11] dmask:0x1 tfe{{$}}
; GFX10: image_gather4 v[0:4], v[5:6], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe ;
-; GFX12: image_gather4 v[0:4], [v6, v5], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe ;
+; GFX12PLUS: image_gather4 v[0:4], [v6, v5], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe ;
define amdgpu_ps <4 x float> @gather4_2d_tfe(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
main_body:
%v = call { <4 x float>, i32 } @llvm.amdgcn.image.gather4.2d.sl_v4f32i32s.f32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 1, i32 0)
@@ -33,7 +34,7 @@ main_body:
; GCN-LABEL: {{^}}gather4_cube:
; GFX6789: image_gather4 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 da{{$}}
; GFX10: image_gather4 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ;
-; GFX12: image_gather4 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ;
+; GFX12PLUS: image_gather4 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ;
define amdgpu_ps <4 x float> @gather4_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %face) {
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.cube.v4f32.f32(i32 1, float %s, float %t, float %face, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
@@ -43,7 +44,7 @@ main_body:
; GCN-LABEL: {{^}}gather4_2darray:
; GFX6789: image_gather4 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 da{{$}}
; GFX10: image_gather4 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY ;
-; GFX12: image_gather4 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY ;
+; GFX12PLUS: image_gather4 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY ;
define amdgpu_ps <4 x float> @gather4_2darray(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %slice) {
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.2darray.v4f32.f32(i32 1, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
@@ -53,7 +54,7 @@ main_body:
; GCN-LABEL: {{^}}gather4_c_2d:
; GFX6789: image_gather4_c v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1{{$}}
; GFX10: image_gather4_c v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
-; GFX12: image_gather4_c v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
+; GFX12PLUS: image_gather4_c v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
define amdgpu_ps <4 x float> @gather4_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t) {
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.2d.v4f32.f32(i32 1, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
@@ -63,7 +64,7 @@ main_body:
; GCN-LABEL: {{^}}gather4_cl_2d:
; GFX6789: image_gather4_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1{{$}}
; GFX10: image_gather4_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
-; GFX12: image_gather4_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
+; GFX12PLUS: image_gather4_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
define amdgpu_ps <4 x float> @gather4_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %clamp) {
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.cl.2d.v4f32.f32(i32 1, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
@@ -73,7 +74,7 @@ main_body:
; GCN-LABEL: {{^}}gather4_c_cl_2d:
; GFX6789: image_gather4_c_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1{{$}}
; GFX10: image_gather4_c_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
-; GFX12: image_gather4_c_cl v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
+; GFX12PLUS: image_gather4_c_cl v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
define amdgpu_ps <4 x float> @gather4_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t, float %clamp) {
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.cl.2d.v4f32.f32(i32 1, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
@@ -83,7 +84,7 @@ main_body:
; GCN-LABEL: {{^}}gather4_b_2d:
; GFX6789: image_gather4_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1{{$}}
; GFX10: image_gather4_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
-; GFX12: image_gather4_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
+; GFX12PLUS: image_gather4_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
define amdgpu_ps <4 x float> @gather4_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %s, float %t) {
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.b.2d.v4f32.f32.f32(i32 1, float %bias, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
@@ -93,7 +94,7 @@ main_body:
; GCN-LABEL: {{^}}gather4_c_b_2d:
; GFX6789: image_gather4_c_b v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1{{$}}
; GFX10: image_gather4_c_b v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
-; GFX12: image_gather4_c_b v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
+; GFX12PLUS: image_gather4_c_b v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
define amdgpu_ps <4 x float> @gather4_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, float %s, float %t) {
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.2d.v4f32.f32.f32(i32 1, float %bias, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
@@ -103,7 +104,7 @@ main_body:
; GCN-LABEL: {{^}}gather4_b_cl_2d:
; GFX6789: image_gather4_b_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1{{$}}
; GFX10: image_gather4_b_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
-; GFX12: image_gather4_b_cl v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
+; GFX12PLUS: image_gather4_b_cl v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
define amdgpu_ps <4 x float> @gather4_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %s, float %t, float %clamp) {
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.2d.v4f32.f32.f32(i32 1, float %bias, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
@@ -113,7 +114,7 @@ main_body:
; GCN-LABEL: {{^}}gather4_c_b_cl_2d:
; GFX6789: image_gather4_c_b_cl v[0:3], v[0:4], s[0:7], s[8:11] dmask:0x1{{$}}
; GFX10: image_gather4_c_b_cl v[0:3], v[0:4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
-; GFX12: image_gather4_c_b_cl v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
+; GFX12PLUS: image_gather4_c_b_cl v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
define amdgpu_ps <4 x float> @gather4_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, float %s, float %t, float %clamp) {
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.2d.v4f32.f32.f32(i32 1, float %bias, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
@@ -123,7 +124,7 @@ main_body:
; GCN-LABEL: {{^}}gather4_l_2d:
; GFX6789: image_gather4_l v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1{{$}}
; GFX10: image_gather4_l v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
-; GFX12: image_gather4_l v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
+; GFX12PLUS: image_gather4_l v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %lod) {
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f32(i32 1, float %s, float %t, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
@@ -133,7 +134,7 @@ main_body:
; GCN-LABEL: {{^}}gather4_c_l_2d:
; GFX6789: image_gather4_c_l v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1{{$}}
; GFX10: image_gather4_c_l v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
-; GFX12: image_gather4_c_l v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
+; GFX12PLUS: image_gather4_c_l v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t, float %lod) {
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f32(i32 1, float %zcompare, float %s, float %t, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
@@ -143,7 +144,7 @@ main_body:
; GCN-LABEL: {{^}}gather4_lz_2d:
; GFX6789: image_gather4_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1{{$}}
; GFX10: image_gather4_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
-; GFX12: image_gather4_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
+; GFX12PLUS: image_gather4_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
define amdgpu_ps <4 x float> @gather4_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
@@ -153,7 +154,7 @@ main_body:
; GCN-LABEL: {{^}}gather4_c_lz_2d:
; GFX6789: image_gather4_c_lz v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1{{$}}
; GFX10: image_gather4_c_lz v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
-; GFX12: image_gather4_c_lz v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
+; GFX12PLUS: image_gather4_c_lz v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
define amdgpu_ps <4 x float> @gather4_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t) {
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.2d.v4f32.f32(i32 1, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
@@ -163,7 +164,7 @@ main_body:
; GCN-LABEL: {{^}}gather4_2d_dmask_2:
; GFX6789: image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x2{{$}}
; GFX10: image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x2 dim:SQ_RSRC_IMG_2D ;
-; GFX12: image_gather4 v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x2 dim:SQ_RSRC_IMG_2D ;
+; GFX12PLUS: image_gather4 v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x2 dim:SQ_RSRC_IMG_2D ;
define amdgpu_ps <4 x float> @gather4_2d_dmask_2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32 2, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
@@ -173,7 +174,7 @@ main_body:
; GCN-LABEL: {{^}}gather4_2d_dmask_4:
; GFX6789: image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x4{{$}}
; GFX10: image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D ;
-; GFX12: image_gather4 v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D ;
+; GFX12PLUS: image_gather4 v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D ;
define amdgpu_ps <4 x float> @gather4_2d_dmask_4(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32 4, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
@@ -183,7 +184,7 @@ main_body:
; GCN-LABEL: {{^}}gather4_2d_dmask_8:
; GFX6789: image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x8{{$}}
; GFX10: image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x8 dim:SQ_RSRC_IMG_2D ;
-; GFX12: image_gather4 v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x8 dim:SQ_RSRC_IMG_2D ;
+; GFX12PLUS: image_gather4 v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x8 dim:SQ_RSRC_IMG_2D ;
define amdgpu_ps <4 x float> @gather4_2d_dmask_8(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32 8, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.getlod.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.getlod.dim.ll
index 360b8cb6c0cc7..8b643ed7b10a6 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.getlod.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.getlod.dim.ll
@@ -2,14 +2,15 @@
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 | FileCheck --check-prefixes=GCN,PRE-GFX10,PRE-GFX12 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 | FileCheck --check-prefixes=GCN,GFX10,PRE-GFX12 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 | FileCheck --check-prefixes=GCN,GFX10,PRE-GFX12 %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 | FileCheck --check-prefixes=GCN,GFX12 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 | FileCheck --check-prefixes=GCN,GFX12PLUS %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1310 | FileCheck --check-prefixes=GCN,GFX12PLUS %s
; GCN-LABEL: {{^}}getlod_1d:
; PRE-GFX10: image_get_lod v[0:3], v0, s[0:7], s[8:11] dmask:0xf{{$}}
; GFX10: image_get_lod v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12: image_get_lod v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS: image_get_lod v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; PRE-GFX12: s_waitcnt vmcnt(0)
-; GFX12: s_wait_samplecnt 0x0
+; GFX12PLUS: s_wait_samplecnt 0x0
define amdgpu_ps <4 x float> @getlod_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
main_body:
%r = call <4 x float> @llvm.amdgcn.image.getlod.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
@@ -19,9 +20,9 @@ main_body:
; GCN-LABEL: {{^}}getlod_2d:
; PRE-GFX10: image_get_lod v[0:1], v[0:1], s[0:7], s[8:11] dmask:0x3{{$}}
; GFX10: image_get_lod v[0:1], v[0:1], s[0:7], s[8:11] dmask:0x3 dim:SQ_RSRC_IMG_2D
-; GFX12: image_get_lod v[0:1], [v0, v1], s[0:7], s[8:11] dmask:0x3 dim:SQ_RSRC_IMG_2D
+; GFX12PLUS: image_get_lod v[0:1], [v0, v1], s[0:7], s[8:11] dmask:0x3 dim:SQ_RSRC_IMG_2D
; PRE-GFX12: s_waitcnt vmcnt(0)
-; GFX12: s_wait_samplecnt 0x0
+; GFX12PLUS: s_wait_samplecnt 0x0
define amdgpu_ps <2 x float> @getlod_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
main_body:
%r = call <2 x float> @llvm.amdgcn.image.getlod.2d.v2f32.f32(i32 3, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll
index 96f084e8ce38b..2a02658dea712 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll
@@ -1,12 +1,13 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,GFX10 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX10 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12PLUS %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 < %s | FileCheck -check-prefixes=GCN,GFX12PLUS %s
; GCN-LABEL: {{^}}load.f16.1d:
; GFX9: image_load v0, v0, s[0:7] dmask:0x1 unorm a16 d16
; GFX10: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm a16 d16
-; GFX12: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D a16 d16
+; GFX12PLUS: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D a16 d16
define amdgpu_ps <4 x half> @load.f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
main_body:
%x = extractelement <2 x i16> %coords, i32 0
@@ -17,7 +18,7 @@ main_body:
; GCN-LABEL: {{^}}load.v2f16.1d:
; GFX9: image_load v0, v0, s[0:7] dmask:0x3 unorm a16 d16
; GFX10: image_load v0, v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm a16 d16
-; GFX12: image_load v0, v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D a16 d16
+; GFX12PLUS: image_load v0, v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D a16 d16
define amdgpu_ps <4 x half> @load.v2f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
main_body:
%x = extractelement <2 x i16> %coords, i32 0
@@ -28,7 +29,7 @@ main_body:
; GCN-LABEL: {{^}}load.v3f16.1d:
; GFX9: image_load v[0:1], v0, s[0:7] dmask:0x7 unorm a16 d16
; GFX10: image_load v[0:1], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm a16 d16
-; GFX12: image_load v[0:1], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D a16 d16
+; GFX12PLUS: image_load v[0:1], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D a16 d16
define amdgpu_ps <4 x half> @load.v3f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
main_body:
%x = extractelement <2 x i16> %coords, i32 0
@@ -39,7 +40,7 @@ main_body:
; GCN-LABEL: {{^}}load.v4f16.1d:
; GFX9: image_load v[0:1], v0, s[0:7] dmask:0xf unorm a16 d16
; GFX10: image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm a16 d16
-; GFX12: image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16 d16
+; GFX12PLUS: image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16 d16
define amdgpu_ps <4 x half> @load.v4f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
main_body:
%x = extractelement <2 x i16> %coords, i32 0
@@ -50,7 +51,7 @@ main_body:
; GCN-LABEL: {{^}}load.f16.2d:
; GFX9: image_load v0, v0, s[0:7] dmask:0x1 unorm a16 d16
; GFX10: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm a16 d16
-; GFX12: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 d16
+; GFX12PLUS: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 d16
define amdgpu_ps <4 x half> @load.f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
main_body:
%x = extractelement <2 x i16> %coords, i32 0
@@ -62,7 +63,7 @@ main_body:
; GCN-LABEL: {{^}}load.v2f16.2d:
; GFX9: image_load v0, v0, s[0:7] dmask:0x3 unorm a16 d16
; GFX10: image_load v0, v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm a16 d16
-; GFX12: image_load v0, v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D a16 d16
+; GFX12PLUS: image_load v0, v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D a16 d16
define amdgpu_ps <4 x half> @load.v2f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
main_body:
%x = extractelement <2 x i16> %coords, i32 0
@@ -74,7 +75,7 @@ main_body:
; GCN-LABEL: {{^}}load.v3f16.2d:
; GFX9: image_load v[0:1], v0, s[0:7] dmask:0x7 unorm a16 d16
; GFX10: image_load v[0:1], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D unorm a16 d16
-; GFX12: image_load v[0:1], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D a16 d16
+; GFX12PLUS: image_load v[0:1], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D a16 d16
define amdgpu_ps <4 x half> @load.v3f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
main_body:
%x = extractelement <2 x i16> %coords, i32 0
@@ -86,7 +87,7 @@ main_body:
; GCN-LABEL: {{^}}load.v4f16.2d:
; GFX9: image_load v[0:1], v0, s[0:7] dmask:0xf unorm a16 d16
; GFX10: image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm a16 d16
-; GFX12: image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16 d16
+; GFX12PLUS: image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16 d16
define amdgpu_ps <4 x half> @load.v4f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
main_body:
%x = extractelement <2 x i16> %coords, i32 0
@@ -98,7 +99,7 @@ main_body:
; GCN-LABEL: {{^}}load.f16.3d:
; GFX9: image_load v0, v[0:1], s[0:7] dmask:0x1 unorm a16 d16
; GFX10: image_load v0, v[0:1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm a16 d16
-; GFX12: image_load v0, [v0, v1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D a16 d16
+; GFX12PLUS: image_load v0, [v0, v1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D a16 d16
define amdgpu_ps <4 x half> @load.f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
main_body:
%x = extractelement <2 x i16> %coords_lo, i32 0
@@ -111,7 +112,7 @@ main_body:
; GCN-LABEL: {{^}}load.v2f16.3d:
; GFX9: image_load v0, v[0:1], s[0:7] dmask:0x3 unorm a16 d16
; GFX10: image_load v0, v[0:1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm a16 d16
-; GFX12: image_load v0, [v0, v1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D a16 d16
+; GFX12PLUS: image_load v0, [v0, v1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D a16 d16
define amdgpu_ps <4 x half> @load.v2f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
main_body:
%x = extractelement <2 x i16> %coords_lo, i32 0
@@ -124,7 +125,7 @@ main_body:
; GCN-LABEL: {{^}}load.v3f16.3d:
; GFX9: image_load v[0:1], v[0:1], s[0:7] dmask:0x7 unorm a16 d16
; GFX10: image_load v[0:1], v[0:1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_3D unorm a16 d16
-; GFX12: image_load v[0:1], [v0, v1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_3D a16 d16
+; GFX12PLUS: image_load v[0:1], [v0, v1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_3D a16 d16
define amdgpu_ps <4 x half> @load.v3f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
main_body:
%x = extractelement <2 x i16> %coords_lo, i32 0
@@ -137,7 +138,7 @@ main_body:
; GCN-LABEL: {{^}}load.v4f16.3d:
; GFX9: image_load v[0:1], v[0:1], s[0:7] dmask:0xf unorm a16 d16
; GFX10: image_load v[0:1], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 d16
-; GFX12: image_load v[0:1], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 d16
+; GFX12PLUS: image_load v[0:1], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 d16
define amdgpu_ps <4 x half> @load.v4f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
main_body:
%x = extractelement <2 x i16> %coords_lo, i32 0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll
index 77bfe6b1cd091..77cdc4e67d318 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll
@@ -1,12 +1,13 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,GFX10 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX10 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12PLUS %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 < %s | FileCheck -check-prefixes=GCN,GFX12PLUS %s
; GCN-LABEL: {{^}}load.f32.1d:
; GFX9: image_load v0, v0, s[0:7] dmask:0x1 unorm a16
; GFX10: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm a16
-; GFX12: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D a16
define amdgpu_ps <4 x float> @load.f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
main_body:
%x = extractelement <2 x i16> %coords, i32 0
@@ -17,7 +18,7 @@ main_body:
; GCN-LABEL: {{^}}load.v2f32.1d:
; GFX9: image_load v[0:1], v0, s[0:7] dmask:0x3 unorm a16
; GFX10: image_load v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm a16
-; GFX12: image_load v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS: image_load v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D a16
define amdgpu_ps <4 x float> @load.v2f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
main_body:
%x = extractelement <2 x i16> %coords, i32 0
@@ -28,7 +29,7 @@ main_body:
; GCN-LABEL: {{^}}load.v3f32.1d:
; GFX9: image_load v[0:2], v0, s[0:7] dmask:0x7 unorm a16
; GFX10: image_load v[0:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm a16
-; GFX12: image_load v[0:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS: image_load v[0:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D a16
define amdgpu_ps <4 x float> @load.v3f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
main_body:
%x = extractelement <2 x i16> %coords, i32 0
@@ -39,7 +40,7 @@ main_body:
; GCN-LABEL: {{^}}load.v4f32.1d:
; GFX9: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16
; GFX10: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm a16
-; GFX12: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16
define amdgpu_ps <4 x float> @load.v4f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
main_body:
%x = extractelement <2 x i16> %coords, i32 0
@@ -50,7 +51,7 @@ main_body:
; GCN-LABEL: {{^}}load.f32.2d:
; GFX9: image_load v0, v0, s[0:7] dmask:0x1 unorm a16
; GFX10: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm a16
-; GFX12: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
define amdgpu_ps <4 x float> @load.f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
main_body:
%x = extractelement <2 x i16> %coords, i32 0
@@ -62,7 +63,7 @@ main_body:
; GCN-LABEL: {{^}}load.v2f32.2d:
; GFX9: image_load v[0:1], v0, s[0:7] dmask:0x3 unorm a16
; GFX10: image_load v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm a16
-; GFX12: image_load v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS: image_load v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D a16
define amdgpu_ps <4 x float> @load.v2f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
main_body:
%x = extractelement <2 x i16> %coords, i32 0
@@ -74,7 +75,7 @@ main_body:
; GCN-LABEL: {{^}}load.v3f32.2d:
; GFX9: image_load v[0:2], v0, s[0:7] dmask:0x7 unorm a16
; GFX10: image_load v[0:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D unorm a16
-; GFX12: image_load v[0:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS: image_load v[0:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D a16
define amdgpu_ps <4 x float> @load.v3f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
main_body:
%x = extractelement <2 x i16> %coords, i32 0
@@ -86,7 +87,7 @@ main_body:
; GCN-LABEL: {{^}}load.v4f32.2d:
; GFX9: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16
; GFX10: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm a16
-; GFX12: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16
define amdgpu_ps <4 x float> @load.v4f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
main_body:
%x = extractelement <2 x i16> %coords, i32 0
@@ -98,7 +99,7 @@ main_body:
; GCN-LABEL: {{^}}load.f32.3d:
; GFX9: image_load v0, v[0:1], s[0:7] dmask:0x1 unorm a16
; GFX10: image_load v0, v[0:1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm a16
-; GFX12: image_load v0, [v0, v1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D a16
+; GFX12PLUS: image_load v0, [v0, v1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D a16
define amdgpu_ps <4 x float> @load.f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
main_body:
%x = extractelement <2 x i16> %coords_lo, i32 0
@@ -111,7 +112,7 @@ main_body:
; GCN-LABEL: {{^}}load.v2f32.3d:
; GFX9: image_load v[0:1], v[0:1], s[0:7] dmask:0x3 unorm a16
; GFX10: image_load v[0:1], v[0:1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm a16
-; GFX12: image_load v[0:1], [v0, v1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D a16
+; GFX12PLUS: image_load v[0:1], [v0, v1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D a16
define amdgpu_ps <4 x float> @load.v2f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
main_body:
%x = extractelement <2 x i16> %coords_lo, i32 0
@@ -124,7 +125,7 @@ main_body:
; GCN-LABEL: {{^}}load.v3f32.3d:
; GFX9: image_load v[0:2], v[0:1], s[0:7] dmask:0x7 unorm a16
; GFX10: image_load v[0:2], v[0:1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_3D unorm a16
-; GFX12: image_load v[0:2], [v0, v1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_3D a16
+; GFX12PLUS: image_load v[0:2], [v0, v1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_3D a16
define amdgpu_ps <4 x float> @load.v3f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
main_body:
%x = extractelement <2 x i16> %coords_lo, i32 0
@@ -137,7 +138,7 @@ main_body:
; GCN-LABEL: {{^}}load.v4f32.3d:
; GFX9: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16
; GFX10: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16
-; GFX12: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX12PLUS: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16
define amdgpu_ps <4 x float> @load.v4f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
main_body:
%x = extractelement <2 x i16> %coords_lo, i32 0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
index 3d64ef16a3c8c..0a6c56e9c8040 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
@@ -1,21 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-TRUE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-FAKE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-TRUE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-TRUE16,GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-FAKE16,GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-TRUE16,GFX13 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-FAKE16,GFX13 %s
define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %fragid) {
; GFX11-LABEL: load_2dmsaa:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: image_msaa_load v[0:3], v[0:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm ; encoding: [0x98,0x01,0x60,0xf0,0x00,0x00,0x00,0x00]
-; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-NEXT: image_msaa_load v[0:3], v[0:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm
+; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2dmsaa:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_msaa_load v[0:3], [v0, v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm ; encoding: [0x06,0x20,0x46,0xe4,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x00]
-; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2dmsaa:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_msaa_load v[0:3], [v0, v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32.i32(i32 1, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -24,37 +26,37 @@ main_body:
define amdgpu_ps <4 x float> @load_2dmsaa_both(<8 x i32> inreg %rsrc, ptr addrspace(1) inreg %out, i32 %s, i32 %t, i32 %fragid) {
; GFX11-LABEL: load_2dmsaa_both:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v8, 0 ; encoding: [0x00,0x01,0x10,0xca,0x80,0x00,0x08,0x05]
-; GFX11-NEXT: v_dual_mov_b32 v7, v2 :: v_dual_mov_b32 v6, v1 ; encoding: [0x02,0x01,0x10,0xca,0x01,0x01,0x06,0x07]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) ; encoding: [0x42,0x02,0x87,0xbf]
-; GFX11-NEXT: v_mov_b32_e32 v9, v8 ; encoding: [0x08,0x03,0x12,0x7e]
-; GFX11-NEXT: v_mov_b32_e32 v10, v8 ; encoding: [0x08,0x03,0x14,0x7e]
-; GFX11-NEXT: v_mov_b32_e32 v11, v8 ; encoding: [0x08,0x03,0x16,0x7e]
-; GFX11-NEXT: v_mov_b32_e32 v12, v8 ; encoding: [0x08,0x03,0x18,0x7e]
-; GFX11-NEXT: v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9 ; encoding: [0x08,0x01,0x10,0xca,0x09,0x01,0x00,0x00]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; encoding: [0x93,0x01,0x87,0xbf]
-; GFX11-NEXT: v_dual_mov_b32 v2, v10 :: v_dual_mov_b32 v3, v11 ; encoding: [0x0a,0x01,0x10,0xca,0x0b,0x01,0x02,0x02]
-; GFX11-NEXT: v_mov_b32_e32 v4, v12 ; encoding: [0x0c,0x03,0x08,0x7e]
-; GFX11-NEXT: image_msaa_load v[0:4], v[5:7], s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_2D_MSAA unorm tfe lwe ; encoding: [0x98,0x02,0x60,0xf0,0x05,0x00,0x60,0x00]
-; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
-; GFX11-NEXT: global_store_b32 v8, v4, s[8:9] ; encoding: [0x00,0x00,0x6a,0xdc,0x08,0x04,0x08,0x00]
+; GFX11-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v8, 0
+; GFX11-NEXT: v_dual_mov_b32 v7, v2 :: v_dual_mov_b32 v6, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_mov_b32_e32 v9, v8
+; GFX11-NEXT: v_mov_b32_e32 v10, v8
+; GFX11-NEXT: v_mov_b32_e32 v11, v8
+; GFX11-NEXT: v_mov_b32_e32 v12, v8
+; GFX11-NEXT: v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_mov_b32 v2, v10 :: v_dual_mov_b32 v3, v11
+; GFX11-NEXT: v_mov_b32_e32 v4, v12
+; GFX11-NEXT: image_msaa_load v[0:4], v[5:7], s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_2D_MSAA unorm tfe lwe
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: global_store_b32 v8, v4, s[8:9]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2dmsaa_both:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_dual_mov_b32 v7, v0 :: v_dual_mov_b32 v8, 0 ; encoding: [0x00,0x01,0x10,0xca,0x80,0x00,0x08,0x07]
-; GFX12-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v6, v1 ; encoding: [0x02,0x01,0x10,0xca,0x01,0x01,0x06,0x05]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; encoding: [0x22,0x01,0x87,0xbf]
-; GFX12-NEXT: v_dual_mov_b32 v9, v8 :: v_dual_mov_b32 v10, v8 ; encoding: [0x08,0x01,0x10,0xca,0x08,0x01,0x0a,0x09]
-; GFX12-NEXT: v_dual_mov_b32 v11, v8 :: v_dual_mov_b32 v12, v8 ; encoding: [0x08,0x01,0x10,0xca,0x08,0x01,0x0c,0x0b]
-; GFX12-NEXT: v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9 ; encoding: [0x08,0x01,0x10,0xca,0x09,0x01,0x00,0x00]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) ; encoding: [0x92,0x01,0x87,0xbf]
-; GFX12-NEXT: v_dual_mov_b32 v2, v10 :: v_dual_mov_b32 v3, v11 ; encoding: [0x0a,0x01,0x10,0xca,0x0b,0x01,0x02,0x02]
-; GFX12-NEXT: v_mov_b32_e32 v4, v12 ; encoding: [0x0c,0x03,0x08,0x7e]
-; GFX12-NEXT: image_msaa_load v[0:4], [v7, v6, v5], s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_2D_MSAA unorm tfe lwe ; encoding: [0x0e,0x20,0x86,0xe4,0x00,0x01,0x00,0x00,0x07,0x06,0x05,0x00]
-; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT: global_store_b32 v8, v4, s[8:9] ; encoding: [0x08,0x80,0x06,0xee,0x00,0x00,0x00,0x02,0x08,0x00,0x00,0x00]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2dmsaa_both:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: v_dual_mov_b32 v7, v0 :: v_dual_mov_b32 v8, 0
+; GFX12PLUS-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v6, v1
+; GFX12PLUS-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12PLUS-NEXT: v_dual_mov_b32 v9, v8 :: v_dual_mov_b32 v10, v8
+; GFX12PLUS-NEXT: v_dual_mov_b32 v11, v8 :: v_dual_mov_b32 v12, v8
+; GFX12PLUS-NEXT: v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9
+; GFX12PLUS-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12PLUS-NEXT: v_dual_mov_b32 v2, v10 :: v_dual_mov_b32 v3, v11
+; GFX12PLUS-NEXT: v_mov_b32_e32 v4, v12
+; GFX12PLUS-NEXT: image_msaa_load v[0:4], [v7, v6, v5], s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_2D_MSAA unorm tfe lwe
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: global_store_b32 v8, v4, s[8:9]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32i32.i32(i32 2, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 3, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
@@ -66,15 +68,15 @@ main_body:
define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %slice, i32 %fragid) {
; GFX11-LABEL: load_2darraymsaa:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: image_msaa_load v[0:3], v[0:3], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm ; encoding: [0x9c,0x04,0x60,0xf0,0x00,0x00,0x00,0x00]
-; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-NEXT: image_msaa_load v[0:3], v[0:3], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm
+; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2darraymsaa:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_msaa_load v[0:3], [v0, v1, v2, v3], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm ; encoding: [0x07,0x20,0x06,0xe5,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03]
-; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2darraymsaa:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_msaa_load v[0:3], [v0, v1, v2, v3], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.msaa.load.2darraymsaa.v4f32.i32(i32 4, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -83,38 +85,55 @@ main_body:
define amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> inreg %rsrc, ptr addrspace(1) inreg %out, i32 %s, i32 %t, i32 %slice, i32 %fragid) {
; GFX11-LABEL: load_2darraymsaa_tfe:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v8, v3 ; encoding: [0x80,0x00,0x10,0xca,0x03,0x01,0x08,0x09]
-; GFX11-NEXT: v_dual_mov_b32 v7, v2 :: v_dual_mov_b32 v6, v1 ; encoding: [0x02,0x01,0x10,0xca,0x01,0x01,0x06,0x07]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) ; encoding: [0x42,0x02,0x87,0xbf]
-; GFX11-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v10, v9 ; encoding: [0x00,0x01,0x10,0xca,0x09,0x01,0x0a,0x05]
-; GFX11-NEXT: v_mov_b32_e32 v11, v9 ; encoding: [0x09,0x03,0x16,0x7e]
-; GFX11-NEXT: v_mov_b32_e32 v12, v9 ; encoding: [0x09,0x03,0x18,0x7e]
-; GFX11-NEXT: v_mov_b32_e32 v13, v9 ; encoding: [0x09,0x03,0x1a,0x7e]
-; GFX11-NEXT: v_dual_mov_b32 v0, v9 :: v_dual_mov_b32 v1, v10 ; encoding: [0x09,0x01,0x10,0xca,0x0a,0x01,0x00,0x00]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; encoding: [0x93,0x01,0x87,0xbf]
-; GFX11-NEXT: v_dual_mov_b32 v2, v11 :: v_dual_mov_b32 v3, v12 ; encoding: [0x0b,0x01,0x10,0xca,0x0c,0x01,0x02,0x02]
-; GFX11-NEXT: v_mov_b32_e32 v4, v13 ; encoding: [0x0d,0x03,0x08,0x7e]
-; GFX11-NEXT: image_msaa_load v[0:4], v[5:8], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe ; encoding: [0x9c,0x08,0x60,0xf0,0x05,0x00,0x20,0x00]
-; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
-; GFX11-NEXT: global_store_b32 v9, v4, s[8:9] ; encoding: [0x00,0x00,0x6a,0xdc,0x09,0x04,0x08,0x00]
+; GFX11-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v8, v3
+; GFX11-NEXT: v_dual_mov_b32 v7, v2 :: v_dual_mov_b32 v6, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v10, v9
+; GFX11-NEXT: v_mov_b32_e32 v11, v9
+; GFX11-NEXT: v_mov_b32_e32 v12, v9
+; GFX11-NEXT: v_mov_b32_e32 v13, v9
+; GFX11-NEXT: v_dual_mov_b32 v0, v9 :: v_dual_mov_b32 v1, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_mov_b32 v2, v11 :: v_dual_mov_b32 v3, v12
+; GFX11-NEXT: v_mov_b32_e32 v4, v13
+; GFX11-NEXT: image_msaa_load v[0:4], v[5:8], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: global_store_b32 v9, v4, s[8:9]
; GFX11-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: load_2darraymsaa_tfe:
; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_mov_b32_e32 v9, 0 ; encoding: [0x80,0x02,0x12,0x7e]
-; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v6, v2 ; encoding: [0x03,0x01,0x10,0xca,0x02,0x01,0x06,0x05]
-; GFX12-NEXT: v_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v8, v0 ; encoding: [0x01,0x01,0x10,0xca,0x00,0x01,0x08,0x07]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; encoding: [0x23,0x01,0x87,0xbf]
-; GFX12-NEXT: v_dual_mov_b32 v10, v9 :: v_dual_mov_b32 v11, v9 ; encoding: [0x09,0x01,0x10,0xca,0x09,0x01,0x0a,0x0a]
-; GFX12-NEXT: v_dual_mov_b32 v12, v9 :: v_dual_mov_b32 v13, v9 ; encoding: [0x09,0x01,0x10,0xca,0x09,0x01,0x0c,0x0c]
-; GFX12-NEXT: v_dual_mov_b32 v0, v9 :: v_dual_mov_b32 v1, v10 ; encoding: [0x09,0x01,0x10,0xca,0x0a,0x01,0x00,0x00]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) ; encoding: [0x92,0x01,0x87,0xbf]
-; GFX12-NEXT: v_dual_mov_b32 v2, v11 :: v_dual_mov_b32 v3, v12 ; encoding: [0x0b,0x01,0x10,0xca,0x0c,0x01,0x02,0x02]
-; GFX12-NEXT: v_mov_b32_e32 v4, v13 ; encoding: [0x0d,0x03,0x08,0x7e]
-; GFX12-NEXT: image_msaa_load v[0:4], [v8, v7, v6, v5], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe ; encoding: [0x0f,0x20,0x06,0xe6,0x00,0x00,0x00,0x00,0x08,0x07,0x06,0x05]
-; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT: global_store_b32 v9, v4, s[8:9] ; encoding: [0x08,0x80,0x06,0xee,0x00,0x00,0x00,0x02,0x09,0x00,0x00,0x00]
+; GFX12-NEXT: v_mov_b32_e32 v9, 0
+; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v6, v2
+; GFX12-NEXT: v_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v8, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_dual_mov_b32 v10, v9 :: v_dual_mov_b32 v11, v9
+; GFX12-NEXT: v_dual_mov_b32 v12, v9 :: v_dual_mov_b32 v13, v9
+; GFX12-NEXT: v_dual_mov_b32 v0, v9 :: v_dual_mov_b32 v1, v10
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-NEXT: v_dual_mov_b32 v2, v11 :: v_dual_mov_b32 v3, v12
+; GFX12-NEXT: v_mov_b32_e32 v4, v13
+; GFX12-NEXT: image_msaa_load v[0:4], [v8, v7, v6, v5], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: global_store_b32 v9, v4, s[8:9]
; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX13-LABEL: load_2darraymsaa_tfe:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v5, v3
+; GFX13-NEXT: v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v7, v1
+; GFX13-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX13-NEXT: v_dual_mov_b32 v8, v0 :: v_dual_mov_b32 v10, v9
+; GFX13-NEXT: v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v12, v9
+; GFX13-NEXT: v_mov_b32_e32 v13, v9
+; GFX13-NEXT: v_dual_mov_b32 v0, v9 :: v_dual_mov_b32 v1, v10
+; GFX13-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX13-NEXT: v_dual_mov_b32 v2, v11 :: v_dual_mov_b32 v3, v12
+; GFX13-NEXT: v_mov_b32_e32 v4, v13
+; GFX13-NEXT: image_msaa_load v[0:4], [v8, v7, v6, v5], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe
+; GFX13-NEXT: s_wait_samplecnt 0x0
+; GFX13-NEXT: global_store_b32 v9, v4, s[8:9]
+; GFX13-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.msaa.load.2darraymsaa.v4f32i32.i32(i32 8, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 1, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
@@ -126,15 +145,15 @@ main_body:
define amdgpu_ps <4 x float> @load_2dmsaa_glc(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %fragid) {
; GFX11-LABEL: load_2dmsaa_glc:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: image_msaa_load v[0:3], v[0:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm glc ; encoding: [0x98,0x41,0x60,0xf0,0x00,0x00,0x00,0x00]
-; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-NEXT: image_msaa_load v[0:3], v[0:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm glc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2dmsaa_glc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_msaa_load v[0:3], [v0, v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm th:TH_LOAD_NT ; encoding: [0x06,0x20,0x46,0xe4,0x00,0x00,0x10,0x00,0x00,0x01,0x02,0x00]
-; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2dmsaa_glc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_msaa_load v[0:3], [v0, v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm th:TH_LOAD_NT
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32.i32(i32 1, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 1)
ret <4 x float> %v
@@ -143,15 +162,15 @@ main_body:
define amdgpu_ps <4 x float> @load_2dmsaa_slc(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %fragid) {
; GFX11-LABEL: load_2dmsaa_slc:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: image_msaa_load v[0:3], v[0:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm slc ; encoding: [0x98,0x11,0x60,0xf0,0x00,0x00,0x00,0x00]
-; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-NEXT: image_msaa_load v[0:3], v[0:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm slc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2dmsaa_slc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_msaa_load v[0:3], [v0, v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm th:TH_LOAD_HT ; encoding: [0x06,0x20,0x46,0xe4,0x00,0x00,0x20,0x00,0x00,0x01,0x02,0x00]
-; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2dmsaa_slc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_msaa_load v[0:3], [v0, v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm th:TH_LOAD_HT
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32.i32(i32 1, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 2)
ret <4 x float> %v
@@ -160,15 +179,15 @@ main_body:
define amdgpu_ps <4 x float> @load_2dmsaa_glc_slc(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %fragid) {
; GFX11-LABEL: load_2dmsaa_glc_slc:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: image_msaa_load v[0:3], v[0:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm glc slc ; encoding: [0x98,0x51,0x60,0xf0,0x00,0x00,0x00,0x00]
-; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-NEXT: image_msaa_load v[0:3], v[0:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm glc slc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2dmsaa_glc_slc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_msaa_load v[0:3], [v0, v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm th:TH_LOAD_LU ; encoding: [0x06,0x20,0x46,0xe4,0x00,0x00,0x30,0x00,0x00,0x01,0x02,0x00]
-; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2dmsaa_glc_slc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_msaa_load v[0:3], [v0, v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm th:TH_LOAD_LU
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32.i32(i32 1, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 3)
ret <4 x float> %v
@@ -177,15 +196,15 @@ main_body:
define amdgpu_ps <4 x half> @load_2dmsaa_d16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %fragid) {
; GFX11-LABEL: load_2dmsaa_d16:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: image_msaa_load v[0:1], v[0:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm d16 ; encoding: [0x98,0x01,0x62,0xf0,0x00,0x00,0x00,0x00]
-; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-NEXT: image_msaa_load v[0:1], v[0:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm d16
+; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2dmsaa_d16:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_msaa_load v[0:1], [v0, v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm d16 ; encoding: [0x26,0x20,0x46,0xe4,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x00]
-; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2dmsaa_d16:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_msaa_load v[0:1], [v0, v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm d16
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x half> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f16.i32(i32 1, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x half> %v
@@ -194,32 +213,32 @@ main_body:
define amdgpu_ps <4 x half> @load_2dmsaa_tfe_d16(<8 x i32> inreg %rsrc, ptr addrspace(1) inreg %out, i32 %s, i32 %t, i32 %fragid) {
; GFX11-LABEL: load_2dmsaa_tfe_d16:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v6, 0 ; encoding: [0x00,0x01,0x10,0xca,0x80,0x00,0x06,0x03]
-; GFX11-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1 ; encoding: [0x02,0x01,0x10,0xca,0x01,0x01,0x04,0x05]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; encoding: [0x22,0x01,0x87,0xbf]
-; GFX11-NEXT: v_mov_b32_e32 v7, v6 ; encoding: [0x06,0x03,0x0e,0x7e]
-; GFX11-NEXT: v_mov_b32_e32 v8, v6 ; encoding: [0x06,0x03,0x10,0x7e]
-; GFX11-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7 ; encoding: [0x06,0x01,0x10,0xca,0x07,0x01,0x00,0x00]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; encoding: [0x02,0x00,0x87,0xbf]
-; GFX11-NEXT: v_mov_b32_e32 v2, v8 ; encoding: [0x08,0x03,0x04,0x7e]
-; GFX11-NEXT: image_msaa_load v[0:2], v[3:5], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm tfe d16 ; encoding: [0x98,0x01,0x62,0xf0,0x03,0x00,0x20,0x00]
-; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
-; GFX11-NEXT: global_store_b32 v6, v2, s[8:9] ; encoding: [0x00,0x00,0x6a,0xdc,0x06,0x02,0x08,0x00]
+; GFX11-NEXT: v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v6, 0
+; GFX11-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mov_b32_e32 v7, v6
+; GFX11-NEXT: v_mov_b32_e32 v8, v6
+; GFX11-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_mov_b32_e32 v2, v8
+; GFX11-NEXT: image_msaa_load v[0:2], v[3:5], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm tfe d16
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: global_store_b32 v6, v2, s[8:9]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2dmsaa_tfe_d16:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, 0 ; encoding: [0x00,0x01,0x10,0xca,0x80,0x00,0x06,0x05]
-; GFX12-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v1 ; encoding: [0x02,0x01,0x10,0xca,0x01,0x01,0x04,0x03]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; encoding: [0x92,0x00,0x87,0xbf]
-; GFX12-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6 ; encoding: [0x06,0x01,0x10,0xca,0x06,0x01,0x08,0x07]
-; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7 ; encoding: [0x06,0x01,0x10,0xca,0x07,0x01,0x00,0x00]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) ; encoding: [0x02,0x00,0x87,0xbf]
-; GFX12-NEXT: v_mov_b32_e32 v2, v8 ; encoding: [0x08,0x03,0x04,0x7e]
-; GFX12-NEXT: image_msaa_load v[0:2], [v5, v4, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm tfe d16 ; encoding: [0x2e,0x20,0x46,0xe4,0x00,0x00,0x00,0x00,0x05,0x04,0x03,0x00]
-; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT: global_store_b32 v6, v2, s[8:9] ; encoding: [0x08,0x80,0x06,0xee,0x00,0x00,0x00,0x01,0x06,0x00,0x00,0x00]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2dmsaa_tfe_d16:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, 0
+; GFX12PLUS-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v1
+; GFX12PLUS-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12PLUS-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6
+; GFX12PLUS-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GFX12PLUS-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12PLUS-NEXT: v_mov_b32_e32 v2, v8
+; GFX12PLUS-NEXT: image_msaa_load v[0:2], [v5, v4, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm tfe d16
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: global_store_b32 v6, v2, s[8:9]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x half>,i32} @llvm.amdgcn.image.msaa.load.2dmsaa.v4f16i32.i32(i32 1, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 1, i32 0)
%v.vec = extractvalue {<4 x half>, i32} %v, 0
@@ -231,15 +250,15 @@ main_body:
define amdgpu_ps <4 x half> @load_2darraymsaa_d16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %slice, i32 %fragid) {
; GFX11-LABEL: load_2darraymsaa_d16:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: image_msaa_load v[0:1], v[0:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm d16 ; encoding: [0x9c,0x01,0x62,0xf0,0x00,0x00,0x00,0x00]
-; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-NEXT: image_msaa_load v[0:1], v[0:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm d16
+; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2darraymsaa_d16:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_msaa_load v[0:1], [v0, v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm d16 ; encoding: [0x27,0x20,0x46,0xe4,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03]
-; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2darraymsaa_d16:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_msaa_load v[0:1], [v0, v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm d16
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x half> @llvm.amdgcn.image.msaa.load.2darraymsaa.v4f16.i32(i32 1, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x half> %v
@@ -248,32 +267,32 @@ main_body:
define amdgpu_ps <4 x half> @load_2darraymsaa_tfe_d16(<8 x i32> inreg %rsrc, ptr addrspace(1) inreg %out, i32 %s, i32 %t, i32 %slice, i32 %fragid) {
; GFX11-LABEL: load_2darraymsaa_tfe_d16:
; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v7, 0 ; encoding: [0x00,0x01,0x10,0xca,0x80,0x00,0x06,0x06]
-; GFX11-NEXT: v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v5, v1 ; encoding: [0x02,0x01,0x10,0xca,0x01,0x01,0x04,0x04]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; encoding: [0x22,0x01,0x87,0xbf]
-; GFX11-NEXT: v_mov_b32_e32 v8, v7 ; encoding: [0x07,0x03,0x10,0x7e]
-; GFX11-NEXT: v_mov_b32_e32 v9, v7 ; encoding: [0x07,0x03,0x12,0x7e]
-; GFX11-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8 ; encoding: [0x07,0x01,0x10,0xca,0x08,0x01,0x00,0x00]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; encoding: [0x02,0x00,0x87,0xbf]
-; GFX11-NEXT: v_mov_b32_e32 v2, v9 ; encoding: [0x09,0x03,0x04,0x7e]
-; GFX11-NEXT: image_msaa_load v[0:2], [v6, v5, v4, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe d16 ; encoding: [0x9d,0x01,0x62,0xf0,0x06,0x00,0x20,0x00,0x05,0x04,0x03,0x00]
-; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
-; GFX11-NEXT: global_store_b32 v7, v2, s[8:9] ; encoding: [0x00,0x00,0x6a,0xdc,0x07,0x02,0x08,0x00]
+; GFX11-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v7, 0
+; GFX11-NEXT: v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mov_b32_e32 v8, v7
+; GFX11-NEXT: v_mov_b32_e32 v9, v7
+; GFX11-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_mov_b32_e32 v2, v9
+; GFX11-NEXT: image_msaa_load v[0:2], [v6, v5, v4, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe d16
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: global_store_b32 v7, v2, s[8:9]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: load_2darraymsaa_tfe_d16:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v7, 0 ; encoding: [0x00,0x01,0x10,0xca,0x80,0x00,0x06,0x06]
-; GFX12-NEXT: v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v5, v1 ; encoding: [0x02,0x01,0x10,0xca,0x01,0x01,0x04,0x04]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; encoding: [0x92,0x00,0x87,0xbf]
-; GFX12-NEXT: v_dual_mov_b32 v8, v7 :: v_dual_mov_b32 v9, v7 ; encoding: [0x07,0x01,0x10,0xca,0x07,0x01,0x08,0x08]
-; GFX12-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8 ; encoding: [0x07,0x01,0x10,0xca,0x08,0x01,0x00,0x00]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) ; encoding: [0x02,0x00,0x87,0xbf]
-; GFX12-NEXT: v_mov_b32_e32 v2, v9 ; encoding: [0x09,0x03,0x04,0x7e]
-; GFX12-NEXT: image_msaa_load v[0:2], [v6, v5, v4, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe d16 ; encoding: [0x2f,0x20,0x46,0xe4,0x00,0x00,0x00,0x00,0x06,0x05,0x04,0x03]
-; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT: global_store_b32 v7, v2, s[8:9] ; encoding: [0x08,0x80,0x06,0xee,0x00,0x00,0x00,0x01,0x07,0x00,0x00,0x00]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: load_2darraymsaa_tfe_d16:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v7, 0
+; GFX12PLUS-NEXT: v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v5, v1
+; GFX12PLUS-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12PLUS-NEXT: v_dual_mov_b32 v8, v7 :: v_dual_mov_b32 v9, v7
+; GFX12PLUS-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8
+; GFX12PLUS-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12PLUS-NEXT: v_mov_b32_e32 v2, v9
+; GFX12PLUS-NEXT: image_msaa_load v[0:2], [v6, v5, v4, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe d16
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: global_store_b32 v7, v2, s[8:9]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x half>,i32} @llvm.amdgcn.image.msaa.load.2darraymsaa.v4f16i32.i32(i32 1, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 1, i32 0)
%v.vec = extractvalue {<4 x half>, i32} %v, 0
@@ -285,33 +304,33 @@ main_body:
define amdgpu_ps <4 x float> @load_2dmsaa_a16(<8 x i32> inreg %rsrc, i16 %s, i16 %t, i16 %fragid) {
; GFX11-TRUE16-LABEL: load_2dmsaa_a16:
; GFX11-TRUE16: ; %bb.0: ; %main_body
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l ; encoding: [0x02,0x39,0x06,0x7e]
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l ; encoding: [0x00,0x39,0x04,0x7e]
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l ; encoding: [0x01,0x39,0x04,0x7f]
-; GFX11-TRUE16-NEXT: image_msaa_load v[0:3], v[2:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16 ; encoding: [0x98,0x01,0x61,0xf0,0x02,0x00,0x00,0x00]
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
+; GFX11-TRUE16-NEXT: image_msaa_load v[0:3], v[2:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: load_2dmsaa_a16:
; GFX11-FAKE16: ; %bb.0: ; %main_body
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX11-FAKE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16 ; encoding: [0x99,0x01,0x61,0xf0,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00]
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: load_2dmsaa_a16:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l ; encoding: [0x01,0x39,0x00,0x7f]
-; GFX12-TRUE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16 ; encoding: [0x46,0x20,0x46,0xe4,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00]
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: load_2dmsaa_a16:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
;
-; GFX12-FAKE16-LABEL: load_2dmsaa_a16:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX12-FAKE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16 ; encoding: [0x46,0x20,0x46,0xe4,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00]
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-FAKE16-LABEL: load_2dmsaa_a16:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32.i16(i32 1, i16 %s, i16 %t, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -320,37 +339,37 @@ main_body:
define amdgpu_ps <4 x float> @load_2darraymsaa_a16(<8 x i32> inreg %rsrc, i16 %s, i16 %t, i16 %slice, i16 %fragid) {
; GFX11-TRUE16-LABEL: load_2darraymsaa_a16:
; GFX11-TRUE16: ; %bb.0: ; %main_body
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l ; encoding: [0x02,0x39,0x08,0x7e]
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v3.l ; encoding: [0x03,0x39,0x08,0x7f]
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l ; encoding: [0x00,0x39,0x06,0x7e]
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v1.l ; encoding: [0x01,0x39,0x06,0x7f]
-; GFX11-TRUE16-NEXT: image_msaa_load v[0:3], v[3:4], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; encoding: [0x9c,0x04,0x61,0xf0,0x03,0x00,0x00,0x00]
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v1.l
+; GFX11-TRUE16-NEXT: image_msaa_load v[0:3], v[3:4], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: load_2darraymsaa_a16:
; GFX11-FAKE16: ; %bb.0: ; %main_body
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v0, 0x5040100 ; encoding: [0x01,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX11-FAKE16-NEXT: image_msaa_load v[0:3], v[1:2], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; encoding: [0x9c,0x04,0x61,0xf0,0x01,0x00,0x00,0x00]
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT: image_msaa_load v[0:3], v[1:2], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: load_2darraymsaa_a16:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l ; encoding: [0x03,0x39,0x04,0x7f]
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l ; encoding: [0x01,0x39,0x00,0x7f]
-; GFX12-TRUE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; encoding: [0x47,0x20,0x06,0xe5,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00]
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: load_2darraymsaa_a16:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
;
-; GFX12-FAKE16-LABEL: load_2darraymsaa_a16:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX12-FAKE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; encoding: [0x47,0x20,0x06,0xe5,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00]
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-FAKE16-LABEL: load_2darraymsaa_a16:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.msaa.load.2darraymsaa.v4f32.i16(i32 4, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
@@ -371,5 +390,3 @@ declare <4 x float> @llvm.amdgcn.image.msaa.load.2darraymsaa.v4f32.i16(i32, i16,
attributes #0 = { nounwind }
attributes #1 = { nounwind readonly }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GCN: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
index 437f438efc554..a68c87a64be82 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
@@ -3,8 +3,10 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-FAKE16 %s
define amdgpu_ps <4 x float> @sample_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s) {
; GFX9-LABEL: sample_1d:
@@ -34,14 +36,14 @@ define amdgpu_ps <4 x float> @sample_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f16(i32 15, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -89,25 +91,25 @@ define amdgpu_ps <4 x float> @sample_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f16(i32 15, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -157,25 +159,25 @@ define amdgpu_ps <4 x float> @sample_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_3d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_3d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_3d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_3d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f16(i32 15, half %s, half %t, half %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -225,25 +227,25 @@ define amdgpu_ps <4 x float> @sample_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_cube:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_cube:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_cube:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_cube:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f16(i32 15, half %s, half %t, half %face, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -291,25 +293,25 @@ define amdgpu_ps <4 x float> @sample_1darray(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_1darray:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_1darray:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_1darray:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_1darray:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.1darray.v4f32.f16(i32 15, half %s, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -359,25 +361,25 @@ define amdgpu_ps <4 x float> @sample_2darray(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_2darray:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_2darray:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_2darray:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_2darray:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.2darray.v4f32.f16(i32 15, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -411,14 +413,14 @@ define amdgpu_ps <4 x float> @sample_c_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f16(i32 15, float %zcompare, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -466,25 +468,25 @@ define amdgpu_ps <4 x float> @sample_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_c_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_sample_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_c_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_sample_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_c_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_sample_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_c_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_sample_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f16(i32 15, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -532,25 +534,25 @@ define amdgpu_ps <4 x float> @sample_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_cl_1d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_sample_cl v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_cl_1d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_sample_cl v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_cl_1d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_sample_cl v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_cl_1d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_sample_cl v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.cl.1d.v4f32.f16(i32 15, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -600,25 +602,25 @@ define amdgpu_ps <4 x float> @sample_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_cl_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_sample_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_cl_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_sample_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_cl_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_sample_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_cl_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_sample_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.cl.2d.v4f32.f16(i32 15, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -666,25 +668,25 @@ define amdgpu_ps <4 x float> @sample_c_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_c_cl_1d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_sample_c_cl v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_c_cl_1d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_sample_c_cl v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_c_cl_1d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_sample_c_cl v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_c_cl_1d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_sample_c_cl v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.cl.1d.v4f32.f16(i32 15, float %zcompare, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -734,25 +736,25 @@ define amdgpu_ps <4 x float> @sample_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_c_cl_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_sample_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_c_cl_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_sample_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_c_cl_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_sample_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_c_cl_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_sample_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.cl.2d.v4f32.f16(i32 15, float %zcompare, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -786,14 +788,14 @@ define amdgpu_ps <4 x float> @sample_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_b_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_b_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f16.f16(i32 15, half %bias, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -841,25 +843,25 @@ define amdgpu_ps <4 x float> @sample_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_b_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_sample_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_b_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_sample_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_b_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_sample_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_b_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_sample_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.b.2d.v4f32.f16.f16(i32 15, half %bias, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -893,14 +895,14 @@ define amdgpu_ps <4 x float> @sample_c_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_b_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_b_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.b.1d.v4f32.f16.f16(i32 15, half %bias, float %zcompare, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -948,25 +950,25 @@ define amdgpu_ps <4 x float> @sample_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_c_b_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_sample_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_c_b_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_sample_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_c_b_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_sample_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_c_b_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_sample_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.b.2d.v4f32.f16.f16(i32 15, half %bias, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1014,25 +1016,25 @@ define amdgpu_ps <4 x float> @sample_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_b_cl_1d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_sample_b_cl v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_b_cl_1d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_sample_b_cl v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_b_cl_1d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_sample_b_cl v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_b_cl_1d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_sample_b_cl v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.b.cl.1d.v4f32.f16.f16(i32 15, half %bias, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1085,25 +1087,25 @@ define amdgpu_ps <4 x float> @sample_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_b_cl_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_sample_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_b_cl_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_sample_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_b_cl_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_sample_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_b_cl_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_sample_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.b.cl.2d.v4f32.f16.f16(i32 15, half %bias, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1151,25 +1153,25 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_c_b_cl_1d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_sample_c_b_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_c_b_cl_1d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_sample_c_b_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_c_b_cl_1d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_sample_c_b_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_c_b_cl_1d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_sample_c_b_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.1d.v4f32.f16.f16(i32 15, half %bias, float %zcompare, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1220,25 +1222,25 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_c_b_cl_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-TRUE16-NEXT: image_sample_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_c_b_cl_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-FAKE16-NEXT: image_sample_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_c_b_cl_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: image_sample_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_c_b_cl_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-FAKE16-NEXT: image_sample_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.2d.v4f32.f16.f16(i32 15, half %bias, float %zcompare, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1263,11 +1265,11 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_d_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_d_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f16(i32 15, half %dsdh, half %dsdv, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1314,23 +1316,23 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_d_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_d_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_d_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_d_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f16(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1382,28 +1384,28 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_d_3d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.h, v7.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v3, v[7:9]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_d_3d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v10, v8
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v8, v5
-; GFX12-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v9, v7, v6, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v3, v[8:10]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_d_3d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v9.l, v8.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v8.h, v7.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v3, v[7:9]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_d_3d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_mov_b32_e32 v10, v8
+; GFX12PLUS-FAKE16-NEXT: v_mov_b32_e32 v8, v5
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v9, v7, v6, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v3, v[8:10]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f16(i32 15, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, half %s, half %t, half %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1428,11 +1430,11 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_d_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_d_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f32.f16(i32 15, float %zcompare, half %dsdh, half %dsdv, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1478,23 +1480,23 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_c_d_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_c_d_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v5, v6, v5, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_c_d_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_c_d_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v5, v6, v5, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f32.f16(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1530,19 +1532,19 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_d_cl_1d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
-; GFX12-TRUE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_d_cl_1d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_d_cl_1d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_d_cl_1d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f16(i32 15, half %dsdh, half %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1590,23 +1592,23 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_d_cl_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_d_cl_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_d_cl_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_d_cl_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f16(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1642,19 +1644,19 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_c_d_cl_1d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l
-; GFX12-TRUE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_c_d_cl_1d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_c_d_cl_1d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_c_d_cl_1d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f32.f16(i32 15, float %zcompare, half %dsdh, half %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1700,25 +1702,25 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_c_d_cl_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v7.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.h, v6.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[7:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_c_d_cl_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v6, v6, v5, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[6:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_c_d_cl_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v8.l, v7.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v7.h, v6.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[7:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_c_d_cl_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v6, v6, v5, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[6:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f32.f16(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1754,19 +1756,19 @@ define amdgpu_ps <4 x float> @sample_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_l_1d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: image_sample_l v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_l_1d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_l v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_l_1d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_l v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_l_1d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_l v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.l.1d.v4f32.f16(i32 15, half %s, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1804,19 +1806,19 @@ define amdgpu_ps <4 x float> @sample_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_l_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: image_sample_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_l_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_l_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_l_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f16(i32 15, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1852,19 +1854,19 @@ define amdgpu_ps <4 x float> @sample_c_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_c_l_1d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: image_sample_c_l v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_c_l_1d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_c_l v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_c_l_1d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_c_l v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_c_l_1d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_c_l v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.1d.v4f32.f16(i32 15, float %zcompare, half %s, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1902,19 +1904,19 @@ define amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_c_l_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: image_sample_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_c_l_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_c_l_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_c_l_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.2d.v4f32.f16(i32 15, float %zcompare, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1939,11 +1941,11 @@ define amdgpu_ps <4 x float> @sample_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_lz_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_lz_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.lz.1d.v4f32.f16(i32 15, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1979,19 +1981,19 @@ define amdgpu_ps <4 x float> @sample_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_lz_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_lz_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_lz_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_lz_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f16(i32 15, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -2016,11 +2018,11 @@ define amdgpu_ps <4 x float> @sample_c_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_lz_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_lz_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.lz.1d.v4f32.f16(i32 15, float %zcompare, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -2056,19 +2058,19 @@ define amdgpu_ps <4 x float> @sample_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_c_lz_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: image_sample_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_c_lz_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_c_lz_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_c_lz_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.lz.2d.v4f32.f16(i32 15, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -2120,26 +2122,26 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_c_d_o_2darray_V1:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.h, v7.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.h, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
-; GFX12-TRUE16-NEXT: image_sample_c_d_o_g16 v0, [v0, v1, v2, v[7:9]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_c_d_o_2darray_V1:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v7, v7, v6, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v6, v5, v4, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_c_d_o_g16 v0, [v0, v1, v2, v[6:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v9.l, v8.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v8.h, v7.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v7.h, v5.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_c_d_o_g16 v0, [v0, v1, v2, v[7:9]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v7, v7, v6, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v6, v5, v4, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_c_d_o_g16 v0, [v0, v1, v2, v[6:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f16.f16(i32 4, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret float %v
@@ -2191,26 +2193,26 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_c_d_o_2darray_V2:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.h, v7.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.h, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
-; GFX12-TRUE16-NEXT: image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[7:9]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_c_d_o_2darray_V2:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v7, v7, v6, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v6, v5, v4, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[6:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v9.l, v8.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v8.h, v7.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v7.h, v5.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[7:9]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v7, v7, v6, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v6, v5, v4, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[6:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f32.f16(i32 6, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <2 x float> %v
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
index 5a35c696c6e44..2021ed60425cd 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
@@ -5,8 +5,10 @@
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-TRUE16 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-FAKE16 %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-TRUE16 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 | FileCheck -check-prefixes=GFX12PLUS,GFX12-FAKE16 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1310 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-TRUE16 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1310 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 | FileCheck -check-prefixes=GFX12PLUS,GFX13-FAKE16 %s
define amdgpu_ps half @image_sample_2d_f16(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
; TONGA-LABEL: image_sample_2d_f16:
@@ -45,14 +47,14 @@ define amdgpu_ps half @image_sample_2d_f16(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: image_sample_2d_f16:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v0, [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D d16
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: image_sample_2d_f16:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v0, [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D d16
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%tex = call half @llvm.amdgcn.image.sample.2d.f16.f32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret half %tex
@@ -152,20 +154,20 @@ define amdgpu_ps half @image_sample_2d_f16_tfe(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-FAKE16-NEXT: global_store_b32 v4, v1, s[12:13]
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: image_sample_2d_f16_tfe:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s14, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX12-TRUE16-NEXT: image_sample v[3:4], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe d16
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
-; GFX12-TRUE16-NEXT: global_store_b32 v2, v4, s[12:13]
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: image_sample_2d_f16_tfe:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: s_mov_b32 s14, exec_lo
+; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX12PLUS-TRUE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12PLUS-TRUE16-NEXT: v_mov_b32_e32 v4, v3
+; GFX12PLUS-TRUE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14
+; GFX12PLUS-TRUE16-NEXT: image_sample v[3:4], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe d16
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
+; GFX12PLUS-TRUE16-NEXT: global_store_b32 v2, v4, s[12:13]
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-FAKE16-LABEL: image_sample_2d_f16_tfe:
; GFX12-FAKE16: ; %bb.0: ; %main_body
@@ -180,6 +182,19 @@ define amdgpu_ps half @image_sample_2d_f16_tfe(<8 x i32> inreg %rsrc, <4 x i32>
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: global_store_b32 v4, v1, s[12:13]
; GFX12-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX13-FAKE16-LABEL: image_sample_2d_f16_tfe:
+; GFX13-FAKE16: ; %bb.0: ; %main_body
+; GFX13-FAKE16-NEXT: s_mov_b32 s14, exec_lo
+; GFX13-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX13-FAKE16-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v2, v1
+; GFX13-FAKE16-NEXT: v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v5, v4
+; GFX13-FAKE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX13-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14
+; GFX13-FAKE16-NEXT: image_sample v[0:1], [v3, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe d16
+; GFX13-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX13-FAKE16-NEXT: global_store_b32 v4, v1, s[12:13]
+; GFX13-FAKE16-NEXT: ; return to shader part epilog
main_body:
%tex = call {half,i32} @llvm.amdgcn.image.sample.2d.f16i32.f32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 1, i32 0)
%tex.vec = extractvalue {half, i32} %tex, 0
@@ -215,11 +230,11 @@ define amdgpu_ps float @image_sample_c_d_1d_v2f16(<8 x i32> inreg %rsrc, <4 x i3
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: image_sample_c_d_1d_v2f16:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_c_d v0, [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0x3 dim:SQ_RSRC_IMG_1D d16
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: image_sample_c_d_1d_v2f16:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_c_d v0, [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0x3 dim:SQ_RSRC_IMG_1D d16
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%tex = call <2 x half> @llvm.amdgcn.image.sample.c.d.1d.v2f16.f32.f32(i32 3, float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
%r = bitcast <2 x half> %tex to float
@@ -278,14 +293,14 @@ define amdgpu_ps <2 x float> @image_sample_c_d_1d_v2f16_tfe(<8 x i32> inreg %rsr
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: image_sample_c_d_1d_v2f16_tfe:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v0
-; GFX12-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-NEXT: v_mov_b32_e32 v1, v0
-; GFX12-NEXT: image_sample_c_d v[0:1], [v5, v4, v2, v3], s[0:7], s[8:11] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe d16
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: image_sample_c_d_1d_v2f16_tfe:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v0
+; GFX12PLUS-NEXT: v_mov_b32_e32 v0, 0
+; GFX12PLUS-NEXT: v_mov_b32_e32 v1, v0
+; GFX12PLUS-NEXT: image_sample_c_d v[0:1], [v5, v4, v2, v3], s[0:7], s[8:11] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe d16
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%tex = call {<2 x half>,i32} @llvm.amdgcn.image.sample.c.d.1d.v2f16i32.f32.f32(i32 3, float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 1, i32 0)
%tex.vec = extractvalue {<2 x half>, i32} %tex, 0
@@ -337,14 +352,14 @@ define amdgpu_ps <2 x float> @image_sample_b_2d_v3f16(<8 x i32> inreg %rsrc, <4
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: image_sample_b_2d_v3f16:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_b v[0:1], [v0, v1, v2], s[0:7], s[8:11] dmask:0x7 dim:SQ_RSRC_IMG_2D d16
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: image_sample_b_2d_v3f16:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_b v[0:1], [v0, v1, v2], s[0:7], s[8:11] dmask:0x7 dim:SQ_RSRC_IMG_2D d16
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%tex = call <3 x half> @llvm.amdgcn.image.sample.b.2d.v3f16.f32.f32(i32 7, float %bias, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
%tex_wide = shufflevector <3 x half> %tex, <3 x half> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@@ -428,17 +443,17 @@ define amdgpu_ps <4 x float> @image_sample_b_2d_v3f16_tfe(<8 x i32> inreg %rsrc,
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: image_sample_b_2d_v3f16_tfe:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v0, 0
-; GFX12-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v1
-; GFX12-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v2, v0
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_b v[0:2], [v5, v4, v3], s[0:7], s[8:11] dmask:0x7 dim:SQ_RSRC_IMG_2D tfe d16
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: image_sample_b_2d_v3f16_tfe:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v0, 0
+; GFX12PLUS-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v1
+; GFX12PLUS-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v2, v0
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_b v[0:2], [v5, v4, v3], s[0:7], s[8:11] dmask:0x7 dim:SQ_RSRC_IMG_2D tfe d16
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%tex = call {<3 x half>,i32} @llvm.amdgcn.image.sample.b.2d.v3f16i32.f32.f32(i32 7, float %bias, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 1, i32 0)
%tex.vec = extractvalue {<3 x half>, i32} %tex, 0
@@ -494,14 +509,14 @@ define amdgpu_ps <2 x float> @image_sample_b_2d_v4f16(<8 x i32> inreg %rsrc, <4
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: image_sample_b_2d_v4f16:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_b v[0:1], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D d16
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: image_sample_b_2d_v4f16:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_b v[0:1], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D d16
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%tex = call <4 x half> @llvm.amdgcn.image.sample.b.2d.v4f16.f32.f32(i32 15, float %bias, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
%r = bitcast <4 x half> %tex to <2 x float>
@@ -585,17 +600,17 @@ define amdgpu_ps <4 x float> @image_sample_b_2d_v4f16_tfe(<8 x i32> inreg %rsrc,
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: image_sample_b_2d_v4f16_tfe:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v0, 0
-; GFX12-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v1
-; GFX12-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v2, v0
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_b v[0:2], [v5, v4, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D tfe d16
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: image_sample_b_2d_v4f16_tfe:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v0, 0
+; GFX12PLUS-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v1
+; GFX12PLUS-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v2, v0
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_b v[0:2], [v5, v4, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D tfe d16
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%tex = call {<4 x half>,i32} @llvm.amdgcn.image.sample.b.2d.v4f16i32.f32.f32(i32 15, float %bias, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 1, i32 0)
%tex.vec = extractvalue {<4 x half>, i32} %tex, 0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
index 8b60aa0e48cda..75c9b121eb23a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
@@ -6,7 +6,8 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx10-1-generic --amdhsa-code-object-version=6 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx11-generic --amdhsa-code-object-version=6 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX13 %s
define amdgpu_ps <4 x float> @sample_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
; VERDE-LABEL: sample_1d:
@@ -36,14 +37,14 @@ define amdgpu_ps <4 x float> @sample_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -130,21 +131,21 @@ define amdgpu_ps <4 x float> @sample_1d_tfe(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-NEXT: global_store_b32 v6, v4, s[12:13]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_1d_tfe:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s14, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, 0
-; GFX12-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6
-; GFX12-NEXT: v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v6
-; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
-; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
-; GFX12-NEXT: v_mov_b32_e32 v4, v10
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT: image_sample v[0:4], v5, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D tfe
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: global_store_b32 v6, v4, s[12:13]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_1d_tfe:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s14, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, 0
+; GFX12PLUS-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6
+; GFX12PLUS-NEXT: v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v6
+; GFX12PLUS-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GFX12PLUS-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
+; GFX12PLUS-NEXT: v_mov_b32_e32 v4, v10
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s14
+; GFX12PLUS-NEXT: image_sample v[0:4], v5, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D tfe
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: global_store_b32 v6, v4, s[12:13]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.sample.1d.v4f32i32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 1, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
@@ -201,6 +202,17 @@ define amdgpu_ps <2 x float> @sample_1d_tfe_adjust_writemask_1(<8 x i32> inreg %
; GFX12-NEXT: image_sample v[0:1], v2, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX13-LABEL: sample_1d_tfe_adjust_writemask_1:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: s_mov_b32 s12, exec_lo
+; GFX13-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX13-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v0, 0
+; GFX13-NEXT: v_mov_b32_e32 v1, v0
+; GFX13-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX13-NEXT: image_sample v[0:1], v2, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
+; GFX13-NEXT: s_wait_samplecnt 0x0
+; GFX13-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.sample.1d.v4f32i32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 1, i32 0)
%res.vec = extractvalue {<4 x float>,i32} %v, 0
@@ -260,6 +272,17 @@ define amdgpu_ps <2 x float> @sample_1d_tfe_adjust_writemask_2(<8 x i32> inreg %
; GFX12-NEXT: image_sample v[0:1], v2, s[0:7], s[8:11] dmask:0x2 dim:SQ_RSRC_IMG_1D tfe
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX13-LABEL: sample_1d_tfe_adjust_writemask_2:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: s_mov_b32 s12, exec_lo
+; GFX13-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX13-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v0, 0
+; GFX13-NEXT: v_mov_b32_e32 v1, v0
+; GFX13-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX13-NEXT: image_sample v[0:1], v2, s[0:7], s[8:11] dmask:0x2 dim:SQ_RSRC_IMG_1D tfe
+; GFX13-NEXT: s_wait_samplecnt 0x0
+; GFX13-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.sample.1d.v4f32i32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 1, i32 0)
%res.vec = extractvalue {<4 x float>,i32} %v, 0
@@ -319,6 +342,17 @@ define amdgpu_ps <2 x float> @sample_1d_tfe_adjust_writemask_3(<8 x i32> inreg %
; GFX12-NEXT: image_sample v[0:1], v2, s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_1D tfe
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX13-LABEL: sample_1d_tfe_adjust_writemask_3:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: s_mov_b32 s12, exec_lo
+; GFX13-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX13-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v0, 0
+; GFX13-NEXT: v_mov_b32_e32 v1, v0
+; GFX13-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX13-NEXT: image_sample v[0:1], v2, s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_1D tfe
+; GFX13-NEXT: s_wait_samplecnt 0x0
+; GFX13-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.sample.1d.v4f32i32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 1, i32 0)
%res.vec = extractvalue {<4 x float>,i32} %v, 0
@@ -378,6 +412,17 @@ define amdgpu_ps <2 x float> @sample_1d_tfe_adjust_writemask_4(<8 x i32> inreg %
; GFX12-NEXT: image_sample v[0:1], v2, s[0:7], s[8:11] dmask:0x8 dim:SQ_RSRC_IMG_1D tfe
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX13-LABEL: sample_1d_tfe_adjust_writemask_4:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: s_mov_b32 s12, exec_lo
+; GFX13-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX13-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v0, 0
+; GFX13-NEXT: v_mov_b32_e32 v1, v0
+; GFX13-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX13-NEXT: image_sample v[0:1], v2, s[0:7], s[8:11] dmask:0x8 dim:SQ_RSRC_IMG_1D tfe
+; GFX13-NEXT: s_wait_samplecnt 0x0
+; GFX13-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.sample.1d.v4f32i32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 1, i32 0)
%res.vec = extractvalue {<4 x float>,i32} %v, 0
@@ -441,16 +486,16 @@ define amdgpu_ps <4 x float> @sample_1d_tfe_adjust_writemask_12(<8 x i32> inreg
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_1d_tfe_adjust_writemask_12:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v0, 0
-; GFX12-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v2, v0
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:2], v3, s[0:7], s[8:11] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_1d_tfe_adjust_writemask_12:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v0, 0
+; GFX12PLUS-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v2, v0
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:2], v3, s[0:7], s[8:11] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.sample.1d.v4f32i32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 1, i32 0)
%res.vec = extractvalue {<4 x float>,i32} %v, 0
@@ -516,16 +561,16 @@ define amdgpu_ps <4 x float> @sample_1d_tfe_adjust_writemask_24(<8 x i32> inreg
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_1d_tfe_adjust_writemask_24:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v0, 0
-; GFX12-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v2, v0
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:2], v3, s[0:7], s[8:11] dmask:0xa dim:SQ_RSRC_IMG_1D tfe
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_1d_tfe_adjust_writemask_24:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v0, 0
+; GFX12PLUS-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v2, v0
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:2], v3, s[0:7], s[8:11] dmask:0xa dim:SQ_RSRC_IMG_1D tfe
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.sample.1d.v4f32i32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 1, i32 0)
%res.vec = extractvalue {<4 x float>,i32} %v, 0
@@ -594,6 +639,18 @@ define amdgpu_ps <4 x float> @sample_1d_tfe_adjust_writemask_134(<8 x i32> inreg
; GFX12-NEXT: image_sample v[0:3], v4, s[0:7], s[8:11] dmask:0xd dim:SQ_RSRC_IMG_1D tfe
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX13-LABEL: sample_1d_tfe_adjust_writemask_134:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: s_mov_b32 s12, exec_lo
+; GFX13-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX13-NEXT: v_dual_mov_b32 v4, v0 :: v_dual_mov_b32 v0, 0
+; GFX13-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v2, v0
+; GFX13-NEXT: v_mov_b32_e32 v3, v0
+; GFX13-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX13-NEXT: image_sample v[0:3], v4, s[0:7], s[8:11] dmask:0xd dim:SQ_RSRC_IMG_1D tfe
+; GFX13-NEXT: s_wait_samplecnt 0x0
+; GFX13-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.sample.1d.v4f32i32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 1, i32 0)
%res.vec = extractvalue {<4 x float>,i32} %v, 0
@@ -690,21 +747,21 @@ define amdgpu_ps <4 x float> @sample_1d_lwe(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-NEXT: global_store_b32 v6, v4, s[12:13]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_1d_lwe:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s14, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, 0
-; GFX12-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6
-; GFX12-NEXT: v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v6
-; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
-; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
-; GFX12-NEXT: v_mov_b32_e32 v4, v10
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT: image_sample v[0:4], v5, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D lwe
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: global_store_b32 v6, v4, s[12:13]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_1d_lwe:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s14, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, 0
+; GFX12PLUS-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6
+; GFX12PLUS-NEXT: v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v6
+; GFX12PLUS-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GFX12PLUS-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
+; GFX12PLUS-NEXT: v_mov_b32_e32 v4, v10
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s14
+; GFX12PLUS-NEXT: image_sample v[0:4], v5, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D lwe
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: global_store_b32 v6, v4, s[12:13]
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.sample.1d.v4f32i32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 2, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
@@ -741,14 +798,14 @@ define amdgpu_ps <4 x float> @sample_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -782,14 +839,14 @@ define amdgpu_ps <4 x float> @sample_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32 15, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -823,14 +880,14 @@ define amdgpu_ps <4 x float> @sample_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_cube:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_CUBE
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_cube:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_CUBE
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f32(i32 15, float %s, float %t, float %face, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -864,14 +921,14 @@ define amdgpu_ps <4 x float> @sample_1darray(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_1darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_1darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.1darray.v4f32.f32(i32 15, float %s, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -905,14 +962,14 @@ define amdgpu_ps <4 x float> @sample_2darray(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_2darray:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_2darray:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.2darray.v4f32.f32(i32 15, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -946,14 +1003,14 @@ define amdgpu_ps <4 x float> @sample_c_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32(i32 15, float %zcompare, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -987,14 +1044,14 @@ define amdgpu_ps <4 x float> @sample_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_c v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_c v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f32(i32 15, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1028,14 +1085,14 @@ define amdgpu_ps <4 x float> @sample_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_cl_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_cl v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_cl_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_cl v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.cl.1d.v4f32.f32(i32 15, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1069,14 +1126,14 @@ define amdgpu_ps <4 x float> @sample_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_cl_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_cl_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.cl.2d.v4f32.f32(i32 15, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1110,14 +1167,14 @@ define amdgpu_ps <4 x float> @sample_c_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_cl_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_c_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_cl_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_c_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.cl.1d.v4f32.f32(i32 15, float %zcompare, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1151,14 +1208,14 @@ define amdgpu_ps <4 x float> @sample_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_cl_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_c_cl v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_cl_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_c_cl v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.cl.2d.v4f32.f32(i32 15, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1192,14 +1249,14 @@ define amdgpu_ps <4 x float> @sample_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_b_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_b_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32.f32(i32 15, float %bias, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1233,14 +1290,14 @@ define amdgpu_ps <4 x float> @sample_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_b_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_b_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.b.2d.v4f32.f32.f32(i32 15, float %bias, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1274,14 +1331,14 @@ define amdgpu_ps <4 x float> @sample_c_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_b_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_b_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.b.1d.v4f32.f32.f32(i32 15, float %bias, float %zcompare, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1315,14 +1372,14 @@ define amdgpu_ps <4 x float> @sample_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_b_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_c_b v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_b_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_c_b v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.b.2d.v4f32.f32.f32(i32 15, float %bias, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1356,14 +1413,14 @@ define amdgpu_ps <4 x float> @sample_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_b_cl_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_b_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_b_cl_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_b_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.b.cl.1d.v4f32.f32.f32(i32 15, float %bias, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1397,14 +1454,14 @@ define amdgpu_ps <4 x float> @sample_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_b_cl_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_b_cl v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_b_cl_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_b_cl v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.b.cl.2d.v4f32.f32.f32(i32 15, float %bias, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1438,14 +1495,14 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_b_cl_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_c_b_cl v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_b_cl_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_c_b_cl v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.1d.v4f32.f32.f32(i32 15, float %bias, float %zcompare, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1479,14 +1536,14 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_b_cl_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample_c_b_cl v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_b_cl_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample_c_b_cl v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.2d.v4f32.f32.f32(i32 15, float %bias, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1511,11 +1568,11 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_d_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_d v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_d_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_d v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f32.f32(i32 15, float %dsdh, float %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1540,11 +1597,11 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_d_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_d v[0:3], [v0, v1, v2, v[3:5]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_d_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_d v[0:3], [v0, v1, v2, v[3:5]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f32(i32 15, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1569,11 +1626,11 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_d_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_c_d v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_d_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_c_d v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f32.f32(i32 15, float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1598,11 +1655,11 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_d_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_c_d v[0:3], [v0, v1, v2, v[3:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_d_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_c_d v[0:3], [v0, v1, v2, v[3:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f32.f32(i32 15, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1627,11 +1684,11 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_d_cl_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_d_cl v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_d_cl_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_d_cl v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f32.f32(i32 15, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1656,11 +1713,11 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_d_cl_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_d_cl v[0:3], [v0, v1, v2, v[3:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_d_cl_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_d_cl v[0:3], [v0, v1, v2, v[3:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f32.f32(i32 15, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1685,11 +1742,11 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_d_cl_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_c_d_cl v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_d_cl_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_c_d_cl v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f32.f32(i32 15, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1714,11 +1771,11 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_d_cl_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_c_d_cl v[0:3], [v0, v1, v2, v[3:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_d_cl_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_c_d_cl v[0:3], [v0, v1, v2, v[3:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f32.f32(i32 15, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1743,11 +1800,11 @@ define amdgpu_ps <4 x float> @sample_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_l_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_l v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_l_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_l v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.l.1d.v4f32.f32(i32 15, float %s, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1772,11 +1829,11 @@ define amdgpu_ps <4 x float> @sample_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_l_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_l v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_l_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_l v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f32(i32 15, float %s, float %t, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1801,11 +1858,11 @@ define amdgpu_ps <4 x float> @sample_c_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_l_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_c_l v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_l_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_c_l v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.1d.v4f32.f32(i32 15, float %zcompare, float %s, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1830,11 +1887,11 @@ define amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_l_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_c_l v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_l_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_c_l v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.2d.v4f32.f32(i32 15, float %zcompare, float %s, float %t, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1859,11 +1916,11 @@ define amdgpu_ps <4 x float> @sample_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_lz_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_lz_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.lz.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1888,11 +1945,11 @@ define amdgpu_ps <4 x float> @sample_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_lz_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_lz_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32 15, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1917,11 +1974,11 @@ define amdgpu_ps <4 x float> @sample_c_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_lz_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_lz_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.lz.1d.v4f32.f32(i32 15, float %zcompare, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1946,11 +2003,11 @@ define amdgpu_ps <4 x float> @sample_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_lz_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_c_lz v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_lz_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_c_lz v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.lz.2d.v4f32.f32(i32 15, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -1975,11 +2032,11 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_d_o_2darray_V1:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_c_d_o v0, [v0, v1, v2, v[3:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_d_o_2darray_V1:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_c_d_o v0, [v0, v1, v2, v[3:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f32.f32(i32 4, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret float %v
@@ -2045,6 +2102,16 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1_tfe(<8 x i32> inreg %rsrc, <4 x
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: global_store_b32 v11, v1, s[12:13]
; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX13-LABEL: sample_c_d_o_2darray_V1_tfe:
+; GFX13: ; %bb.0: ; %main_body
+; GFX13-NEXT: v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v9, v1
+; GFX13-NEXT: v_dual_mov_b32 v10, v0 :: v_dual_mov_b32 v12, v11
+; GFX13-NEXT: v_dual_mov_b32 v0, v11 :: v_dual_mov_b32 v1, v12
+; GFX13-NEXT: image_sample_c_d_o v[0:1], [v10, v9, v2, v[3:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY tfe
+; GFX13-NEXT: s_wait_samplecnt 0x0
+; GFX13-NEXT: global_store_b32 v11, v1, s[12:13]
+; GFX13-NEXT: ; return to shader part epilog
main_body:
%v = call {float,i32} @llvm.amdgcn.image.sample.c.d.o.2darray.f32i32.f32.f32(i32 4, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 1, i32 0)
%v.vec = extractvalue {float, i32} %v, 0
@@ -2072,11 +2139,11 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_d_o_2darray_V2:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_c_d_o v[0:1], [v0, v1, v2, v[3:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_d_o_2darray_V2:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_c_d_o v[0:1], [v0, v1, v2, v[3:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f32.f32(i32 6, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <2 x float> %v
@@ -2129,14 +2196,14 @@ define amdgpu_ps <4 x float> @sample_c_d_o_2darray_V2_tfe(<8 x i32> inreg %rsrc,
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_d_o_2darray_V2_tfe:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_dual_mov_b32 v11, v0 :: v_dual_mov_b32 v0, 0
-; GFX12-NEXT: v_dual_mov_b32 v9, v2 :: v_dual_mov_b32 v10, v1
-; GFX12-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v2, v0
-; GFX12-NEXT: image_sample_c_d_o v[0:2], [v11, v10, v9, v[3:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY tfe
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_d_o_2darray_V2_tfe:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: v_dual_mov_b32 v11, v0 :: v_dual_mov_b32 v0, 0
+; GFX12PLUS-NEXT: v_dual_mov_b32 v9, v2 :: v_dual_mov_b32 v10, v1
+; GFX12PLUS-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v2, v0
+; GFX12PLUS-NEXT: image_sample_c_d_o v[0:2], [v11, v10, v9, v[3:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY tfe
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call {<2 x float>, i32} @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32i32.f32.f32(i32 6, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 1, i32 0)
%v.vec = extractvalue {<2 x float>, i32} %v, 0
@@ -2178,14 +2245,14 @@ define amdgpu_ps <4 x float> @sample_1d_unorm(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_1d_unorm:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D unorm
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_1d_unorm:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D unorm
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 1, i32 0, i32 0)
ret <4 x float> %v
@@ -2219,14 +2286,14 @@ define amdgpu_ps <4 x float> @sample_1d_glc(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_1d_glc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_1d_glc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 1)
ret <4 x float> %v
@@ -2260,14 +2327,14 @@ define amdgpu_ps <4 x float> @sample_1d_slc(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_1d_slc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_HT
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_1d_slc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_HT
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 2)
ret <4 x float> %v
@@ -2301,14 +2368,14 @@ define amdgpu_ps <4 x float> @sample_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_1d_glc_slc:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_LU
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_1d_glc_slc:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_LU
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 3)
ret <4 x float> %v
@@ -2342,14 +2409,14 @@ define amdgpu_ps float @adjust_writemask_sample_0(<8 x i32> inreg %rsrc, <4 x i3
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: adjust_writemask_sample_0:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: adjust_writemask_sample_0:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%r = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
%elt0 = extractelement <4 x float> %r, i32 0
@@ -2384,14 +2451,14 @@ define amdgpu_ps <2 x float> @adjust_writemask_sample_01(<8 x i32> inreg %rsrc,
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: adjust_writemask_sample_01:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:1], v0, s[0:7], s[8:11] dmask:0x3 dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: adjust_writemask_sample_01:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:1], v0, s[0:7], s[8:11] dmask:0x3 dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%r = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
%out = shufflevector <4 x float> %r, <4 x float> poison, <2 x i32> <i32 0, i32 1>
@@ -2426,14 +2493,14 @@ define amdgpu_ps <3 x float> @adjust_writemask_sample_012(<8 x i32> inreg %rsrc,
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: adjust_writemask_sample_012:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:2], v0, s[0:7], s[8:11] dmask:0x7 dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: adjust_writemask_sample_012:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:2], v0, s[0:7], s[8:11] dmask:0x7 dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%r = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
%out = shufflevector <4 x float> %r, <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2>
@@ -2468,14 +2535,14 @@ define amdgpu_ps <2 x float> @adjust_writemask_sample_12(<8 x i32> inreg %rsrc,
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: adjust_writemask_sample_12:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:1], v0, s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: adjust_writemask_sample_12:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:1], v0, s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%r = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
%out = shufflevector <4 x float> %r, <4 x float> poison, <2 x i32> <i32 1, i32 2>
@@ -2510,14 +2577,14 @@ define amdgpu_ps <2 x float> @adjust_writemask_sample_03(<8 x i32> inreg %rsrc,
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: adjust_writemask_sample_03:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:1], v0, s[0:7], s[8:11] dmask:0x9 dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: adjust_writemask_sample_03:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:1], v0, s[0:7], s[8:11] dmask:0x9 dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%r = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
%out = shufflevector <4 x float> %r, <4 x float> poison, <2 x i32> <i32 0, i32 3>
@@ -2552,14 +2619,14 @@ define amdgpu_ps <2 x float> @adjust_writemask_sample_13(<8 x i32> inreg %rsrc,
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: adjust_writemask_sample_13:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:1], v0, s[0:7], s[8:11] dmask:0xa dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: adjust_writemask_sample_13:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:1], v0, s[0:7], s[8:11] dmask:0xa dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%r = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
%out = shufflevector <4 x float> %r, <4 x float> poison, <2 x i32> <i32 1, i32 3>
@@ -2594,14 +2661,14 @@ define amdgpu_ps <3 x float> @adjust_writemask_sample_123(<8 x i32> inreg %rsrc,
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: adjust_writemask_sample_123:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:2], v0, s[0:7], s[8:11] dmask:0xe dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: adjust_writemask_sample_123:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:2], v0, s[0:7], s[8:11] dmask:0xe dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%r = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
%out = shufflevector <4 x float> %r, <4 x float> poison, <3 x i32> <i32 1, i32 2, i32 3>
@@ -2621,9 +2688,9 @@ define amdgpu_ps <4 x float> @adjust_writemask_sample_none_enabled(<8 x i32> inr
; GFX10PLUS: ; %bb.0: ; %main_body
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: adjust_writemask_sample_none_enabled:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: adjust_writemask_sample_none_enabled:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%r = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 0, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %r
@@ -2657,14 +2724,14 @@ define amdgpu_ps <2 x float> @adjust_writemask_sample_123_to_12(<8 x i32> inreg
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: adjust_writemask_sample_123_to_12:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:1], v0, s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: adjust_writemask_sample_123_to_12:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:1], v0, s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%r = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 14, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
%out = shufflevector <4 x float> %r, <4 x float> poison, <2 x i32> <i32 0, i32 1>
@@ -2699,14 +2766,14 @@ define amdgpu_ps <2 x float> @adjust_writemask_sample_013_to_13(<8 x i32> inreg
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: adjust_writemask_sample_013_to_13:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:1], v0, s[0:7], s[8:11] dmask:0xa dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: adjust_writemask_sample_013_to_13:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:1], v0, s[0:7], s[8:11] dmask:0xa dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%r = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 11, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
%out = shufflevector <4 x float> %r, <4 x float> poison, <2 x i32> <i32 1, i32 2>
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
index e7b048dda1c1f..270e150ee082a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
@@ -2,8 +2,10 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX10 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-vopd=0 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-vopd=0 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-vopd=0 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-vopd=0 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-vopd=0 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-vopd=0 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX12-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+real-true16 -amdgpu-enable-vopd=0 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX13-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=-real-true16 -amdgpu-enable-vopd=0 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX13-FAKE16 %s
define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {
; GFX10-LABEL: sample_d_1d:
@@ -18,11 +20,29 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_d_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x00]
-; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12-TRUE16-LABEL: sample_d_1d:
+; GFX12-TRUE16: ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x00]
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_d_1d:
+; GFX12-FAKE16: ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x00]
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX13-TRUE16-LABEL: sample_d_1d:
+; GFX13-TRUE16: ; %bb.0: ; %main_body
+; GFX13-TRUE16-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0xe8,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x00]
+; GFX13-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX13-FAKE16-LABEL: sample_d_1d:
+; GFX13-FAKE16: ; %bb.0: ; %main_body
+; GFX13-FAKE16-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0xe8,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x00]
+; GFX13-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -68,6 +88,22 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX12-FAKE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x02,0x04,0x05]
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX12-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX13-TRUE16-LABEL: sample_d_2d:
+; GFX13-TRUE16: ; %bb.0: ; %main_body
+; GFX13-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l ; encoding: [0x03,0x39,0x04,0x7f]
+; GFX13-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l ; encoding: [0x01,0x39,0x00,0x7f]
+; GFX13-TRUE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0xe8,0xe7,0x00,0x00,0x00,0x04,0x00,0x02,0x04,0x05]
+; GFX13-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX13-FAKE16-LABEL: sample_d_2d:
+; GFX13-FAKE16: ; %bb.0: ; %main_body
+; GFX13-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd7,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX13-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd7,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX13-FAKE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0xe8,0xe7,0x00,0x00,0x00,0x04,0x00,0x02,0x04,0x05]
+; GFX13-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -115,6 +151,22 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX12-FAKE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v3, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x40,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x02,0x03,0x05]
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX12-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX13-TRUE16-LABEL: sample_d_3d:
+; GFX13-TRUE16: ; %bb.0: ; %main_body
+; GFX13-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l ; encoding: [0x04,0x39,0x06,0x7f]
+; GFX13-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l ; encoding: [0x01,0x39,0x00,0x7f]
+; GFX13-TRUE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v3, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0xe8,0xe7,0x00,0x00,0x00,0x04,0x00,0x02,0x03,0x05]
+; GFX13-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX13-FAKE16-LABEL: sample_d_3d:
+; GFX13-FAKE16: ; %bb.0: ; %main_body
+; GFX13-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100 ; encoding: [0x03,0x00,0x44,0xd7,0x04,0x07,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX13-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd7,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX13-FAKE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v3, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0xe8,0xe7,0x00,0x00,0x00,0x04,0x00,0x02,0x03,0x05]
+; GFX13-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -133,11 +185,29 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_d_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
-; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12-TRUE16-LABEL: sample_c_d_1d:
+; GFX12-TRUE16: ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_1d:
+; GFX12-FAKE16: ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX13-TRUE16-LABEL: sample_c_d_1d:
+; GFX13-TRUE16: ; %bb.0: ; %main_body
+; GFX13-TRUE16-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0xea,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
+; GFX13-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX13-FAKE16-LABEL: sample_c_d_1d:
+; GFX13-FAKE16: ; %bb.0: ; %main_body
+; GFX13-FAKE16-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0xea,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
+; GFX13-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -183,6 +253,22 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX12-FAKE16-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v3, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x03,0x05]
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX12-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX13-TRUE16-LABEL: sample_c_d_2d:
+; GFX13-TRUE16: ; %bb.0: ; %main_body
+; GFX13-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l ; encoding: [0x04,0x39,0x06,0x7f]
+; GFX13-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l ; encoding: [0x02,0x39,0x02,0x7f]
+; GFX13-TRUE16-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v3, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0xea,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x03,0x05]
+; GFX13-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX13-FAKE16-LABEL: sample_c_d_2d:
+; GFX13-FAKE16: ; %bb.0: ; %main_body
+; GFX13-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100 ; encoding: [0x03,0x00,0x44,0xd7,0x04,0x07,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX13-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100 ; encoding: [0x01,0x00,0x44,0xd7,0x02,0x03,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX13-FAKE16-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v3, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0xea,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x03,0x05]
+; GFX13-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -201,11 +287,29 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_d_cl_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0xd7,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
-; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12-TRUE16-LABEL: sample_d_cl_1d:
+; GFX12-TRUE16: ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0xd7,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_d_cl_1d:
+; GFX12-FAKE16: ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0xd7,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX13-TRUE16-LABEL: sample_d_cl_1d:
+; GFX13-TRUE16: ; %bb.0: ; %main_body
+; GFX13-TRUE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0xe8,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
+; GFX13-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX13-FAKE16-LABEL: sample_d_cl_1d:
+; GFX13-FAKE16: ; %bb.0: ; %main_body
+; GFX13-FAKE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0xe8,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
+; GFX13-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -251,6 +355,22 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX12-FAKE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0xd7,0xe7,0x00,0x00,0x00,0x04,0x00,0x02,0x04,0x05]
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX12-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX13-TRUE16-LABEL: sample_d_cl_2d:
+; GFX13-TRUE16: ; %bb.0: ; %main_body
+; GFX13-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l ; encoding: [0x03,0x39,0x04,0x7f]
+; GFX13-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l ; encoding: [0x01,0x39,0x00,0x7f]
+; GFX13-TRUE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0xe8,0xe7,0x00,0x00,0x00,0x04,0x00,0x02,0x04,0x05]
+; GFX13-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX13-FAKE16-LABEL: sample_d_cl_2d:
+; GFX13-FAKE16: ; %bb.0: ; %main_body
+; GFX13-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd7,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX13-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd7,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX13-FAKE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0xe8,0xe7,0x00,0x00,0x00,0x04,0x00,0x02,0x04,0x05]
+; GFX13-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -269,11 +389,29 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_d_cl_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0xd5,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
-; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12-TRUE16-LABEL: sample_c_d_cl_1d:
+; GFX12-TRUE16: ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0xd5,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_cl_1d:
+; GFX12-FAKE16: ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0xd5,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX13-TRUE16-LABEL: sample_c_d_cl_1d:
+; GFX13-TRUE16: ; %bb.0: ; %main_body
+; GFX13-TRUE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0xea,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
+; GFX13-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX13-FAKE16-LABEL: sample_c_d_cl_1d:
+; GFX13-FAKE16: ; %bb.0: ; %main_body
+; GFX13-FAKE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0xea,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
+; GFX13-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -321,6 +459,22 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX12-FAKE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[5:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0xd5,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x03,0x05]
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX12-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX13-TRUE16-LABEL: sample_c_d_cl_2d:
+; GFX13-TRUE16: ; %bb.0: ; %main_body
+; GFX13-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l ; encoding: [0x04,0x39,0x06,0x7f]
+; GFX13-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l ; encoding: [0x02,0x39,0x02,0x7f]
+; GFX13-TRUE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[5:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0xea,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x03,0x05]
+; GFX13-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX13-FAKE16-LABEL: sample_c_d_cl_2d:
+; GFX13-FAKE16: ; %bb.0: ; %main_body
+; GFX13-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100 ; encoding: [0x03,0x00,0x44,0xd7,0x04,0x07,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX13-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100 ; encoding: [0x01,0x00,0x44,0xd7,0x02,0x03,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX13-FAKE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[5:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0xea,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x03,0x05]
+; GFX13-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -373,6 +527,25 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32>
; GFX12-FAKE16-NEXT: image_sample_c_d_o_g16 v0, [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0x0f,0xe5,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x05]
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX12-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX13-TRUE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX13-TRUE16: ; %bb.0: ; %main_body
+; GFX13-TRUE16-NEXT: v_mov_b32_e32 v9, v5 ; encoding: [0x05,0x03,0x12,0x7e]
+; GFX13-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.l ; encoding: [0x04,0x39,0x0a,0x7e]
+; GFX13-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l ; encoding: [0x03,0x39,0x04,0x7f]
+; GFX13-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; encoding: [0x03,0x00,0xae,0xbf]
+; GFX13-TRUE16-NEXT: v_mov_b16_e32 v5.h, v9.l ; encoding: [0x09,0x39,0x0a,0x7f]
+; GFX13-TRUE16-NEXT: image_sample_c_d_o_g16 v0, [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0x2e,0xe5,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x05]
+; GFX13-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX13-FAKE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX13-FAKE16: ; %bb.0: ; %main_body
+; GFX13-FAKE16-NEXT: v_perm_b32 v5, v5, v4, 0x5040100 ; encoding: [0x05,0x00,0x44,0xd7,0x05,0x09,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX13-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd7,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX13-FAKE16-NEXT: image_sample_c_d_o_g16 v0, [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0x2e,0xe5,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x05]
+; GFX13-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f16.f32.f32(i32 4, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret float %v
@@ -425,6 +598,25 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4
; GFX12-FAKE16-NEXT: image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0x8f,0xe5,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x05]
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX12-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX13-TRUE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX13-TRUE16: ; %bb.0: ; %main_body
+; GFX13-TRUE16-NEXT: v_mov_b32_e32 v9, v5 ; encoding: [0x05,0x03,0x12,0x7e]
+; GFX13-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.l ; encoding: [0x04,0x39,0x0a,0x7e]
+; GFX13-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l ; encoding: [0x03,0x39,0x04,0x7f]
+; GFX13-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; encoding: [0x03,0x00,0xae,0xbf]
+; GFX13-TRUE16-NEXT: v_mov_b16_e32 v5.h, v9.l ; encoding: [0x09,0x39,0x0a,0x7f]
+; GFX13-TRUE16-NEXT: image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0xae,0xe5,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x05]
+; GFX13-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX13-FAKE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX13-FAKE16: ; %bb.0: ; %main_body
+; GFX13-FAKE16-NEXT: v_perm_b32 v5, v5, v4, 0x5040100 ; encoding: [0x05,0x00,0x44,0xd7,0x05,0x09,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX13-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd7,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX13-FAKE16-NEXT: image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0xae,0xe5,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x05]
+; GFX13-FAKE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX13-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32 6, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <2 x float> %v
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
index 45cebaf449d54..33d641247bc82 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
@@ -2,8 +2,10 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-FAKE16 %s
define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {
; GFX10-LABEL: sample_d_1d:
@@ -18,11 +20,11 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_d_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_d_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -53,21 +55,21 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_d_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_d_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_d_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_d_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -100,21 +102,21 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_d_3d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v3, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_d_3d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v3, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_d_3d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v3, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_d_3d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v3, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -133,11 +135,11 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_d_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_d_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -168,21 +170,21 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_c_d_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v3, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_c_d_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v3, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_c_d_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v3, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_c_d_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v3, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -201,11 +203,11 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_d_cl_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_d_cl_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -236,21 +238,21 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_d_cl_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_d_cl_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_d_cl_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_d_cl_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -269,11 +271,11 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_c_d_cl_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_c_d_cl_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -306,21 +308,21 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_c_d_cl_2d:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[5:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_c_d_cl_2d:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[5:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_c_d_cl_2d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[5:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_c_d_cl_2d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[5:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -355,23 +357,23 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_c_d_o_2darray_V1:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v9, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v9.l
-; GFX12-TRUE16-NEXT: image_sample_c_d_o_g16 v0, [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_c_d_o_2darray_V1:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v4, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_c_d_o_g16 v0, [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b32_e32 v9, v5
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v5.h, v9.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_c_d_o_g16 v0, [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v5, v5, v4, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_c_d_o_g16 v0, [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f16.f32.f32(i32 4, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret float %v
@@ -406,23 +408,23 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sample_c_d_o_2darray_V2:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v9, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v9.l
-; GFX12-TRUE16-NEXT: image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: sample_c_d_o_2darray_V2:
-; GFX12-FAKE16: ; %bb.0: ; %main_body
-; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v4, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-FAKE16-NEXT: image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: ; return to shader part epilog
+; GFX12PLUS-TRUE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: v_mov_b32_e32 v9, v5
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
+; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v5.h, v9.l
+; GFX12PLUS-TRUE16-NEXT: image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v5, v5, v4, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12PLUS-FAKE16-NEXT: image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32 6, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <2 x float> %v
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
index d8358460962a7..d673b0d66ab7a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
@@ -1,265 +1,267 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-SDAG %s
-; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-GISEL,GFX10-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-SDAG %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-SDAG %s
-; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-GISEL,GFX11-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-GISEL,GFX11-GISEL-FAKE16 %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10_11,GFX10_11-SDAG %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10_11,GFX10_11-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10_11,GFX10_11-SDAG %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10_11,GFX10_11-SDAG %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-SDAG %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-SDAG %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-GISEL,GFX12PLUS-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-GISEL,GFX12PLUS-GISEL-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1310 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-SDAG %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1310 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-SDAG %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1310 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-GISEL,GFX12PLUS-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1310 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-GISEL,GFX12PLUS-GISEL-FAKE16 %s
define amdgpu_ps void @sample_1d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
-; GFX10PLUS-LABEL: sample_1d_nortn:
-; GFX10PLUS: ; %bb.0: ; %main_body
-; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10PLUS-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-NEXT: s_endpgm
+; GFX10_11-LABEL: sample_1d_nortn:
+; GFX10_11: ; %bb.0: ; %main_body
+; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX10_11-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-NEXT: s_endpgm
;
-; GFX12-LABEL: sample_1d_nortn:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: sample_1d_nortn:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret void
}
define amdgpu_ps void @sample_2d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
-; GFX10PLUS-LABEL: sample_2d_nortn:
-; GFX10PLUS: ; %bb.0: ; %main_body
-; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10PLUS-NEXT: image_sample off, v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX10PLUS-NEXT: s_endpgm
+; GFX10_11-LABEL: sample_2d_nortn:
+; GFX10_11: ; %bb.0: ; %main_body
+; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX10_11-NEXT: image_sample off, v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX10_11-NEXT: s_endpgm
;
-; GFX12-LABEL: sample_2d_nortn:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: image_sample off, [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: sample_2d_nortn:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: image_sample off, [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.sample.2d.nortn.f32(i32 15, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret void
}
define amdgpu_ps void @sample_3d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %r) {
-; GFX10PLUS-LABEL: sample_3d_nortn:
-; GFX10PLUS: ; %bb.0: ; %main_body
-; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10PLUS-NEXT: image_sample off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
-; GFX10PLUS-NEXT: s_endpgm
+; GFX10_11-LABEL: sample_3d_nortn:
+; GFX10_11: ; %bb.0: ; %main_body
+; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX10_11-NEXT: image_sample off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
+; GFX10_11-NEXT: s_endpgm
;
-; GFX12-LABEL: sample_3d_nortn:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: image_sample off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: sample_3d_nortn:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: image_sample off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.sample.3d.nortn.f32(i32 15, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret void
}
define amdgpu_ps void @sample_cube_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %face) {
-; GFX10PLUS-LABEL: sample_cube_nortn:
-; GFX10PLUS: ; %bb.0: ; %main_body
-; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10PLUS-NEXT: image_sample off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_CUBE
-; GFX10PLUS-NEXT: s_endpgm
+; GFX10_11-LABEL: sample_cube_nortn:
+; GFX10_11: ; %bb.0: ; %main_body
+; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX10_11-NEXT: image_sample off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_CUBE
+; GFX10_11-NEXT: s_endpgm
;
-; GFX12-LABEL: sample_cube_nortn:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: image_sample off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_CUBE
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: sample_cube_nortn:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: image_sample off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_CUBE
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.sample.cube.nortn.f32(i32 15, float %s, float %t, float %face, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret void
}
define amdgpu_ps void @sample_1darray_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %slice) {
-; GFX10PLUS-LABEL: sample_1darray_nortn:
-; GFX10PLUS: ; %bb.0: ; %main_body
-; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10PLUS-NEXT: image_sample off, v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
-; GFX10PLUS-NEXT: s_endpgm
+; GFX10_11-LABEL: sample_1darray_nortn:
+; GFX10_11: ; %bb.0: ; %main_body
+; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX10_11-NEXT: image_sample off, v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
+; GFX10_11-NEXT: s_endpgm
;
-; GFX12-LABEL: sample_1darray_nortn:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: image_sample off, [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: sample_1darray_nortn:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: image_sample off, [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.sample.1darray.nortn.f32(i32 15, float %s, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret void
}
define amdgpu_ps void @sample_2darray_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %slice) {
-; GFX10PLUS-LABEL: sample_2darray_nortn:
-; GFX10PLUS: ; %bb.0: ; %main_body
-; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10PLUS-NEXT: image_sample off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX10PLUS-NEXT: s_endpgm
+; GFX10_11-LABEL: sample_2darray_nortn:
+; GFX10_11: ; %bb.0: ; %main_body
+; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX10_11-NEXT: image_sample off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX10_11-NEXT: s_endpgm
;
-; GFX12-LABEL: sample_2darray_nortn:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: image_sample off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: sample_2darray_nortn:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: image_sample off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.sample.2darray.nortn.f32(i32 15, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret void
}
define amdgpu_ps void @sample_b_1d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s) {
-; GFX10PLUS-LABEL: sample_b_1d_nortn:
-; GFX10PLUS: ; %bb.0: ; %main_body
-; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10PLUS-NEXT: image_sample_b off, v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-NEXT: s_endpgm
+; GFX10_11-LABEL: sample_b_1d_nortn:
+; GFX10_11: ; %bb.0: ; %main_body
+; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX10_11-NEXT: image_sample_b off, v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-NEXT: s_endpgm
;
-; GFX12-LABEL: sample_b_1d_nortn:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: image_sample_b off, [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: sample_b_1d_nortn:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: image_sample_b off, [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.sample.b.1d.nortn.f32(i32 15, float %zcompare, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret void
}
define amdgpu_ps void @sample_b_2d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t) {
-; GFX10PLUS-LABEL: sample_b_2d_nortn:
-; GFX10PLUS: ; %bb.0: ; %main_body
-; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10PLUS-NEXT: image_sample_b off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX10PLUS-NEXT: s_endpgm
+; GFX10_11-LABEL: sample_b_2d_nortn:
+; GFX10_11: ; %bb.0: ; %main_body
+; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX10_11-NEXT: image_sample_b off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX10_11-NEXT: s_endpgm
;
-; GFX12-LABEL: sample_b_2d_nortn:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: image_sample_b off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: sample_b_2d_nortn:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: image_sample_b off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.sample.b.2d.nortn.f32(i32 15, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret void
}
define amdgpu_ps void @sample_c_1d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s) {
-; GFX10PLUS-LABEL: sample_c_1d_nortn:
-; GFX10PLUS: ; %bb.0: ; %main_body
-; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10PLUS-NEXT: image_sample_c off, v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-NEXT: s_endpgm
+; GFX10_11-LABEL: sample_c_1d_nortn:
+; GFX10_11: ; %bb.0: ; %main_body
+; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX10_11-NEXT: image_sample_c off, v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-NEXT: s_endpgm
;
-; GFX12-LABEL: sample_c_1d_nortn:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: image_sample_c off, [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: sample_c_1d_nortn:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: image_sample_c off, [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.sample.c.1d.nortn.f32(i32 15, float %zcompare, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret void
}
define amdgpu_ps void @sample_c_2d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t) {
-; GFX10PLUS-LABEL: sample_c_2d_nortn:
-; GFX10PLUS: ; %bb.0: ; %main_body
-; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10PLUS-NEXT: image_sample_c off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX10PLUS-NEXT: s_endpgm
+; GFX10_11-LABEL: sample_c_2d_nortn:
+; GFX10_11: ; %bb.0: ; %main_body
+; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX10_11-NEXT: image_sample_c off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX10_11-NEXT: s_endpgm
;
-; GFX12-LABEL: sample_c_2d_nortn:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: image_sample_c off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: sample_c_2d_nortn:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: image_sample_c off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.sample.c.2d.nortn.f32(i32 15, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret void
}
define amdgpu_ps void @sample_d_1d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dsdv, float %s) {
-; GFX10PLUS-LABEL: sample_d_1d_nortn:
-; GFX10PLUS: ; %bb.0: ; %main_body
-; GFX10PLUS-NEXT: image_sample_d off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-NEXT: s_endpgm
+; GFX10_11-LABEL: sample_d_1d_nortn:
+; GFX10_11: ; %bb.0: ; %main_body
+; GFX10_11-NEXT: image_sample_d off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-NEXT: s_endpgm
;
-; GFX12-LABEL: sample_d_1d_nortn:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_d off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: sample_d_1d_nortn:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_d off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.sample.d.1d.nortn.f32.f32(i32 15, float %dsdh, float %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret void
}
define amdgpu_ps void @sample_d_2d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t) {
-; GFX10PLUS-LABEL: sample_d_2d_nortn:
-; GFX10PLUS: ; %bb.0: ; %main_body
-; GFX10PLUS-NEXT: image_sample_d off, v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX10PLUS-NEXT: s_endpgm
+; GFX10_11-LABEL: sample_d_2d_nortn:
+; GFX10_11: ; %bb.0: ; %main_body
+; GFX10_11-NEXT: image_sample_d off, v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX10_11-NEXT: s_endpgm
;
-; GFX12-LABEL: sample_d_2d_nortn:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_d off, [v0, v1, v2, v[3:5]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: sample_d_2d_nortn:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_d off, [v0, v1, v2, v[3:5]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.sample.d.2d.nortn.f32.f32(i32 15, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret void
}
define amdgpu_ps void @sample_l_1d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %lod) {
-; GFX10PLUS-LABEL: sample_l_1d_nortn:
-; GFX10PLUS: ; %bb.0: ; %main_body
-; GFX10PLUS-NEXT: image_sample_l off, v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-NEXT: s_endpgm
+; GFX10_11-LABEL: sample_l_1d_nortn:
+; GFX10_11: ; %bb.0: ; %main_body
+; GFX10_11-NEXT: image_sample_l off, v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-NEXT: s_endpgm
;
-; GFX12-LABEL: sample_l_1d_nortn:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_l off, [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: sample_l_1d_nortn:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_l off, [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.sample.l.1d.nortn.f32(i32 15, float %s, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret void
}
define amdgpu_ps void @sample_l_2d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %lod) {
-; GFX10PLUS-LABEL: sample_l_2d_nortn:
-; GFX10PLUS: ; %bb.0: ; %main_body
-; GFX10PLUS-NEXT: image_sample_l off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX10PLUS-NEXT: s_endpgm
+; GFX10_11-LABEL: sample_l_2d_nortn:
+; GFX10_11: ; %bb.0: ; %main_body
+; GFX10_11-NEXT: image_sample_l off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX10_11-NEXT: s_endpgm
;
-; GFX12-LABEL: sample_l_2d_nortn:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_sample_l off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: sample_l_2d_nortn:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_sample_l off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12PLUS-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.sample.l.2d.nortn.f32(i32 15, float %s, float %t, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret void
}
define amdgpu_ps <4 x float> @sample_nortn_mix_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
-; GFX10PLUS-LABEL: sample_nortn_mix_1:
-; GFX10PLUS: ; %bb.0: ; %main_body
-; GFX10PLUS-NEXT: s_mov_b32 s12, exec_lo
-; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX10PLUS-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
-; GFX10PLUS-NEXT: ; return to shader part epilog
+; GFX10_11-LABEL: sample_nortn_mix_1:
+; GFX10_11: ; %bb.0: ; %main_body
+; GFX10_11-NEXT: s_mov_b32 s12, exec_lo
+; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX10_11-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX10_11-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-NEXT: s_waitcnt vmcnt(0)
+; GFX10_11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_nortn_mix_1:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_nortn_mix_1:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
%v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
@@ -267,27 +269,27 @@ main_body:
}
define amdgpu_ps <4 x float> @sample_nortn_mix_2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
-; GFX10PLUS-LABEL: sample_nortn_mix_2:
-; GFX10PLUS: ; %bb.0: ; %main_body
-; GFX10PLUS-NEXT: s_mov_b32 s12, exec_lo
-; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10PLUS-NEXT: v_mov_b32_e32 v4, v0
-; GFX10PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX10PLUS-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)
-; GFX10PLUS-NEXT: ; return to shader part epilog
+; GFX10_11-LABEL: sample_nortn_mix_2:
+; GFX10_11: ; %bb.0: ; %main_body
+; GFX10_11-NEXT: s_mov_b32 s12, exec_lo
+; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX10_11-NEXT: v_mov_b32_e32 v4, v0
+; GFX10_11-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX10_11-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-NEXT: s_waitcnt vmcnt(0)
+; GFX10_11-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: sample_nortn_mix_2:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT: v_mov_b32_e32 v4, v0
-; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12PLUS-LABEL: sample_nortn_mix_2:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-NEXT: v_mov_b32_e32 v4, v0
+; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
@@ -295,53 +297,53 @@ main_body:
}
define amdgpu_ps <4 x float> @sample_nortn_mix_3(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
-; GFX10PLUS-SDAG-LABEL: sample_nortn_mix_3:
-; GFX10PLUS-SDAG: ; %bb.0: ; %main_body
-; GFX10PLUS-SDAG-NEXT: s_mov_b32 s12, exec_lo
-; GFX10PLUS-SDAG-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10PLUS-SDAG-NEXT: image_sample v1, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-SDAG-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX10PLUS-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-SDAG-NEXT: s_waitcnt vmcnt(1)
-; GFX10PLUS-SDAG-NEXT: image_sample v[0:3], v1, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX10PLUS-SDAG-NEXT: ; return to shader part epilog
+; GFX10_11-SDAG-LABEL: sample_nortn_mix_3:
+; GFX10_11-SDAG: ; %bb.0: ; %main_body
+; GFX10_11-SDAG-NEXT: s_mov_b32 s12, exec_lo
+; GFX10_11-SDAG-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX10_11-SDAG-NEXT: image_sample v1, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
+; GFX10_11-SDAG-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX10_11-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-SDAG-NEXT: s_waitcnt vmcnt(1)
+; GFX10_11-SDAG-NEXT: image_sample v[0:3], v1, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX10_11-SDAG-NEXT: ; return to shader part epilog
;
-; GFX10PLUS-GISEL-LABEL: sample_nortn_mix_3:
-; GFX10PLUS-GISEL: ; %bb.0: ; %main_body
-; GFX10PLUS-GISEL-NEXT: s_mov_b32 s12, exec_lo
-; GFX10PLUS-GISEL-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10PLUS-GISEL-NEXT: image_sample v[1:4], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-GISEL-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX10PLUS-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-GISEL-NEXT: s_waitcnt vmcnt(1)
-; GFX10PLUS-GISEL-NEXT: image_sample v[0:3], v1, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX10PLUS-GISEL-NEXT: ; return to shader part epilog
+; GFX10_11-GISEL-LABEL: sample_nortn_mix_3:
+; GFX10_11-GISEL: ; %bb.0: ; %main_body
+; GFX10_11-GISEL-NEXT: s_mov_b32 s12, exec_lo
+; GFX10_11-GISEL-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX10_11-GISEL-NEXT: image_sample v[1:4], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-GISEL-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX10_11-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-GISEL-NEXT: s_waitcnt vmcnt(1)
+; GFX10_11-GISEL-NEXT: image_sample v[0:3], v1, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX10_11-GISEL-NEXT: ; return to shader part epilog
;
-; GFX12-SDAG-LABEL: sample_nortn_mix_3:
-; GFX12-SDAG: ; %bb.0: ; %main_body
-; GFX12-SDAG-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-SDAG-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-SDAG-NEXT: image_sample v1, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
-; GFX12-SDAG-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x1
-; GFX12-SDAG-NEXT: image_sample v[0:3], v1, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: ; return to shader part epilog
+; GFX12PLUS-SDAG-LABEL: sample_nortn_mix_3:
+; GFX12PLUS-SDAG: ; %bb.0: ; %main_body
+; GFX12PLUS-SDAG-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-SDAG-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-SDAG-NEXT: image_sample v1, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-SDAG-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-SDAG-NEXT: s_wait_samplecnt 0x1
+; GFX12PLUS-SDAG-NEXT: image_sample v[0:3], v1, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-SDAG-NEXT: ; return to shader part epilog
;
-; GFX12-GISEL-LABEL: sample_nortn_mix_3:
-; GFX12-GISEL: ; %bb.0: ; %main_body
-; GFX12-GISEL-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-GISEL-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-GISEL-NEXT: image_sample v[1:4], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-GISEL-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x1
-; GFX12-GISEL-NEXT: image_sample v[0:3], v1, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: ; return to shader part epilog
+; GFX12PLUS-GISEL-LABEL: sample_nortn_mix_3:
+; GFX12PLUS-GISEL: ; %bb.0: ; %main_body
+; GFX12PLUS-GISEL-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-GISEL-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-GISEL-NEXT: image_sample v[1:4], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-GISEL-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-GISEL-NEXT: s_wait_samplecnt 0x1
+; GFX12PLUS-GISEL-NEXT: image_sample v[0:3], v1, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-GISEL-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
%v.0 = extractelement <4 x float> %v, i32 0
@@ -351,73 +353,73 @@ main_body:
}
define amdgpu_ps <4 x float> @sample_nortn_mix_4(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
-; GFX10PLUS-SDAG-LABEL: sample_nortn_mix_4:
-; GFX10PLUS-SDAG: ; %bb.0: ; %main_body
-; GFX10PLUS-SDAG-NEXT: s_mov_b32 s12, exec_lo
-; GFX10PLUS-SDAG-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10PLUS-SDAG-NEXT: image_sample v4, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-SDAG-NEXT: s_waitcnt vmcnt(1)
-; GFX10PLUS-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-SDAG-NEXT: image_sample v[0:3], v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-SDAG-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX10PLUS-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-SDAG-NEXT: s_waitcnt vmcnt(2)
-; GFX10PLUS-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX10PLUS-SDAG-NEXT: ; return to shader part epilog
+; GFX10_11-SDAG-LABEL: sample_nortn_mix_4:
+; GFX10_11-SDAG: ; %bb.0: ; %main_body
+; GFX10_11-SDAG-NEXT: s_mov_b32 s12, exec_lo
+; GFX10_11-SDAG-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX10_11-SDAG-NEXT: image_sample v4, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
+; GFX10_11-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-SDAG-NEXT: s_waitcnt vmcnt(1)
+; GFX10_11-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-SDAG-NEXT: image_sample v[0:3], v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-SDAG-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX10_11-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-SDAG-NEXT: s_waitcnt vmcnt(2)
+; GFX10_11-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX10_11-SDAG-NEXT: ; return to shader part epilog
;
-; GFX10PLUS-GISEL-LABEL: sample_nortn_mix_4:
-; GFX10PLUS-GISEL: ; %bb.0: ; %main_body
-; GFX10PLUS-GISEL-NEXT: s_mov_b32 s12, exec_lo
-; GFX10PLUS-GISEL-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX10PLUS-GISEL-NEXT: image_sample v[4:7], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-GISEL-NEXT: s_waitcnt vmcnt(1)
-; GFX10PLUS-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-GISEL-NEXT: image_sample v[0:3], v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-GISEL-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX10PLUS-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-GISEL-NEXT: s_waitcnt vmcnt(2)
-; GFX10PLUS-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX10PLUS-GISEL-NEXT: ; return to shader part epilog
+; GFX10_11-GISEL-LABEL: sample_nortn_mix_4:
+; GFX10_11-GISEL: ; %bb.0: ; %main_body
+; GFX10_11-GISEL-NEXT: s_mov_b32 s12, exec_lo
+; GFX10_11-GISEL-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX10_11-GISEL-NEXT: image_sample v[4:7], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-GISEL-NEXT: s_waitcnt vmcnt(1)
+; GFX10_11-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-GISEL-NEXT: image_sample v[0:3], v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-GISEL-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX10_11-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-GISEL-NEXT: s_waitcnt vmcnt(2)
+; GFX10_11-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX10_11-GISEL-NEXT: ; return to shader part epilog
;
-; GFX12-SDAG-LABEL: sample_nortn_mix_4:
-; GFX12-SDAG: ; %bb.0: ; %main_body
-; GFX12-SDAG-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-SDAG-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-SDAG-NEXT: image_sample v4, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
-; GFX12-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x1
-; GFX12-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-SDAG-NEXT: image_sample v[0:3], v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-SDAG-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x2
-; GFX12-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: ; return to shader part epilog
+; GFX12PLUS-SDAG-LABEL: sample_nortn_mix_4:
+; GFX12PLUS-SDAG: ; %bb.0: ; %main_body
+; GFX12PLUS-SDAG-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-SDAG-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-SDAG-NEXT: image_sample v4, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-SDAG-NEXT: s_wait_samplecnt 0x1
+; GFX12PLUS-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-SDAG-NEXT: image_sample v[0:3], v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-SDAG-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-SDAG-NEXT: s_wait_samplecnt 0x2
+; GFX12PLUS-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-SDAG-NEXT: ; return to shader part epilog
;
-; GFX12-GISEL-LABEL: sample_nortn_mix_4:
-; GFX12-GISEL: ; %bb.0: ; %main_body
-; GFX12-GISEL-NEXT: s_mov_b32 s12, exec_lo
-; GFX12-GISEL-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-GISEL-NEXT: image_sample v[4:7], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x1
-; GFX12-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-GISEL-NEXT: image_sample v[0:3], v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-GISEL-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX12-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x2
-; GFX12-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: ; return to shader part epilog
+; GFX12PLUS-GISEL-LABEL: sample_nortn_mix_4:
+; GFX12PLUS-GISEL: ; %bb.0: ; %main_body
+; GFX12PLUS-GISEL-NEXT: s_mov_b32 s12, exec_lo
+; GFX12PLUS-GISEL-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12PLUS-GISEL-NEXT: image_sample v[4:7], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-GISEL-NEXT: s_wait_samplecnt 0x1
+; GFX12PLUS-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-GISEL-NEXT: image_sample v[0:3], v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-GISEL-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-GISEL-NEXT: s_wait_samplecnt 0x2
+; GFX12PLUS-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-GISEL-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
%v.0 = extractelement <4 x float> %v, i32 0
@@ -435,52 +437,38 @@ main_body:
}
define amdgpu_ps void @sample_d_1d_g16_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {
-; GFX10PLUS-SDAG-LABEL: sample_d_1d_g16_nortn:
-; GFX10PLUS-SDAG: ; %bb.0: ; %main_body
-; GFX10PLUS-SDAG-NEXT: image_sample_d_g16 off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10PLUS-SDAG-NEXT: s_endpgm
+; GFX10_11-SDAG-LABEL: sample_d_1d_g16_nortn:
+; GFX10_11-SDAG: ; %bb.0: ; %main_body
+; GFX10_11-SDAG-NEXT: image_sample_d_g16 off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-SDAG-NEXT: s_endpgm
;
-; GFX10-GISEL-LABEL: sample_d_1d_g16_nortn:
-; GFX10-GISEL: ; %bb.0: ; %main_body
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX10-GISEL-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX10-GISEL-NEXT: image_sample_d_g16 off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10-GISEL-NEXT: s_endpgm
+; GFX10_11-GISEL-LABEL: sample_d_1d_g16_nortn:
+; GFX10_11-GISEL: ; %bb.0: ; %main_body
+; GFX10_11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10_11-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX10_11-GISEL-NEXT: v_lshl_or_b32 v0, s0, 16, v0
+; GFX10_11-GISEL-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GFX10_11-GISEL-NEXT: image_sample_d_g16 off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX10_11-GISEL-NEXT: s_endpgm
;
-; GFX11-GISEL-TRUE16-LABEL: sample_d_1d_g16_nortn:
-; GFX11-GISEL-TRUE16: ; %bb.0: ; %main_body
-; GFX11-GISEL-TRUE16-NEXT: image_sample_d_g16 off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX11-GISEL-TRUE16-NEXT: s_endpgm
+; GFX12PLUS-SDAG-LABEL: sample_d_1d_g16_nortn:
+; GFX12PLUS-SDAG: ; %bb.0: ; %main_body
+; GFX12PLUS-SDAG-NEXT: image_sample_d_g16 off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-SDAG-NEXT: s_endpgm
;
-; GFX11-GISEL-FAKE16-LABEL: sample_d_1d_g16_nortn:
-; GFX11-GISEL-FAKE16: ; %bb.0: ; %main_body
-; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX11-GISEL-FAKE16-NEXT: image_sample_d_g16 off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX11-GISEL-FAKE16-NEXT: s_endpgm
+; GFX12PLUS-GISEL-TRUE16-LABEL: sample_d_1d_g16_nortn:
+; GFX12PLUS-GISEL-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-GISEL-TRUE16-NEXT: image_sample_d_g16 off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-GISEL-TRUE16-NEXT: s_endpgm
;
-; GFX12-SDAG-LABEL: sample_d_1d_g16_nortn:
-; GFX12-SDAG: ; %bb.0: ; %main_body
-; GFX12-SDAG-NEXT: image_sample_d_g16 off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-SDAG-NEXT: s_endpgm
-;
-; GFX12-GISEL-TRUE16-LABEL: sample_d_1d_g16_nortn:
-; GFX12-GISEL-TRUE16: ; %bb.0: ; %main_body
-; GFX12-GISEL-TRUE16-NEXT: image_sample_d_g16 off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-GISEL-TRUE16-NEXT: s_endpgm
-;
-; GFX12-GISEL-FAKE16-LABEL: sample_d_1d_g16_nortn:
-; GFX12-GISEL-FAKE16: ; %bb.0: ; %main_body
-; GFX12-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, s0, 16, v0
-; GFX12-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-GISEL-FAKE16-NEXT: image_sample_d_g16 off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12-GISEL-FAKE16-NEXT: s_endpgm
+; GFX12PLUS-GISEL-FAKE16-LABEL: sample_d_1d_g16_nortn:
+; GFX12PLUS-GISEL-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX12PLUS-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12PLUS-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, s0, 16, v0
+; GFX12PLUS-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GFX12PLUS-GISEL-FAKE16-NEXT: image_sample_d_g16 off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-GISEL-FAKE16-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.sample.d.1d.nortn.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll
index 382c9c92c8c78..7148eecb5b70c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll
@@ -2,7 +2,8 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12PLUS %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 < %s | FileCheck -check-prefixes=GFX12PLUS %s
define amdgpu_ps void @store_f16_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {
; GFX9-LABEL: store_f16_1d:
@@ -20,10 +21,10 @@ define amdgpu_ps void @store_f16_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2
; GFX11-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm a16 d16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_f16_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D a16 d16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_f16_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D a16 d16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords, i32 0
%bitcast = bitcast <2 x i32> %val to <4 x half>
@@ -47,10 +48,10 @@ define amdgpu_ps void @store_v2f16_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords,
; GFX11-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm a16 d16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_v2f16_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D a16 d16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_v2f16_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D a16 d16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords, i32 0
%bitcast = bitcast <2 x i32> %val to <4 x half>
@@ -74,10 +75,10 @@ define amdgpu_ps void @store_v3f16_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords,
; GFX11-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm a16 d16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_v3f16_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D a16 d16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_v3f16_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D a16 d16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords, i32 0
%bitcast = bitcast <2 x i32> %val to <4 x half>
@@ -101,10 +102,10 @@ define amdgpu_ps void @store_v4f16_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords,
; GFX11-NEXT: image_store v[1:2], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm a16 d16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_v4f16_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[1:2], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16 d16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_v4f16_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[1:2], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16 d16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords, i32 0
%bitcast = bitcast <2 x i32> %val to <4 x half>
@@ -128,10 +129,10 @@ define amdgpu_ps void @store_f16_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2
; GFX11-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm a16 d16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_f16_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 d16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_f16_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 d16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords, i32 0
%y = extractelement <2 x i16> %coords, i32 1
@@ -156,10 +157,10 @@ define amdgpu_ps void @store_v2f16_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords,
; GFX11-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm a16 d16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_v2f16_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D a16 d16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_v2f16_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D a16 d16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords, i32 0
%y = extractelement <2 x i16> %coords, i32 1
@@ -184,10 +185,10 @@ define amdgpu_ps void @store_v3f16_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords,
; GFX11-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D unorm a16 d16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_v3f16_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D a16 d16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_v3f16_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D a16 d16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords, i32 0
%y = extractelement <2 x i16> %coords, i32 1
@@ -212,10 +213,10 @@ define amdgpu_ps void @store_v4f16_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords,
; GFX11-NEXT: image_store v[1:2], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm a16 d16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_v4f16_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[1:2], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16 d16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_v4f16_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[1:2], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16 d16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords, i32 0
%y = extractelement <2 x i16> %coords, i32 1
@@ -240,10 +241,10 @@ define amdgpu_ps void @store_f16_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo,
; GFX11-NEXT: image_store v[2:3], v[0:1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm a16 d16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_f16_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[2:3], [v0, v1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D a16 d16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_f16_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[2:3], [v0, v1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D a16 d16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords_lo, i32 0
%y = extractelement <2 x i16> %coords_lo, i32 1
@@ -269,10 +270,10 @@ define amdgpu_ps void @store_v2f16_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_l
; GFX11-NEXT: image_store v[2:3], v[0:1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm a16 d16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_v2f16_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[2:3], [v0, v1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D a16 d16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_v2f16_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[2:3], [v0, v1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D a16 d16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords_lo, i32 0
%y = extractelement <2 x i16> %coords_lo, i32 1
@@ -298,10 +299,10 @@ define amdgpu_ps void @store_v3f16_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_l
; GFX11-NEXT: image_store v[2:3], v[0:1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_3D unorm a16 d16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_v3f16_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[2:3], [v0, v1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_3D a16 d16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_v3f16_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[2:3], [v0, v1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_3D a16 d16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords_lo, i32 0
%y = extractelement <2 x i16> %coords_lo, i32 1
@@ -327,10 +328,10 @@ define amdgpu_ps void @store_v4f16_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_l
; GFX11-NEXT: image_store v[2:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 d16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_v4f16_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[2:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 d16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_v4f16_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[2:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 d16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords_lo, i32 0
%y = extractelement <2 x i16> %coords_lo, i32 1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll
index 51e17f2ccdb9f..8685ecd46728d 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll
@@ -2,7 +2,8 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12PLUS %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 < %s | FileCheck -check-prefixes=GFX12PLUS %s
define amdgpu_ps void @store_f32_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) {
; GFX9-LABEL: store_f32_1d:
@@ -20,10 +21,10 @@ define amdgpu_ps void @store_f32_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4
; GFX11-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm a16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_f32_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_f32_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords, i32 0
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %val, i32 1, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
@@ -46,10 +47,10 @@ define amdgpu_ps void @store_v2f32_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords,
; GFX11-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm a16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_v2f32_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_v2f32_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords, i32 0
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %val, i32 3, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
@@ -72,10 +73,10 @@ define amdgpu_ps void @store_v3f32_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords,
; GFX11-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm a16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_v3f32_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_v3f32_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords, i32 0
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %val, i32 7, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
@@ -98,10 +99,10 @@ define amdgpu_ps void @store_v4f32_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords,
; GFX11-NEXT: image_store v[1:4], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm a16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_v4f32_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[1:4], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_v4f32_1d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[1:4], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords, i32 0
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %val, i32 15, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
@@ -124,10 +125,10 @@ define amdgpu_ps void @store_f32_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4
; GFX11-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm a16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_f32_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_f32_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords, i32 0
%y = extractelement <2 x i16> %coords, i32 1
@@ -151,10 +152,10 @@ define amdgpu_ps void @store_v2f32_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords,
; GFX11-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm a16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_v2f32_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_v2f32_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords, i32 0
%y = extractelement <2 x i16> %coords, i32 1
@@ -178,10 +179,10 @@ define amdgpu_ps void @store_v3f32_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords,
; GFX11-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D unorm a16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_v3f32_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_v3f32_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords, i32 0
%y = extractelement <2 x i16> %coords, i32 1
@@ -205,10 +206,10 @@ define amdgpu_ps void @store_v4f32_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords,
; GFX11-NEXT: image_store v[1:4], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm a16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_v4f32_2d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[1:4], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_v4f32_2d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[1:4], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords, i32 0
%y = extractelement <2 x i16> %coords, i32 1
@@ -232,10 +233,10 @@ define amdgpu_ps void @store_f32_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo,
; GFX11-NEXT: image_store v[2:5], v[0:1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm a16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_f32_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[2:5], [v0, v1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_f32_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[2:5], [v0, v1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords_lo, i32 0
%y = extractelement <2 x i16> %coords_lo, i32 1
@@ -260,10 +261,10 @@ define amdgpu_ps void @store_v2f32_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_l
; GFX11-NEXT: image_store v[2:5], v[0:1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm a16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_v2f32_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[2:5], [v0, v1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_v2f32_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[2:5], [v0, v1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords_lo, i32 0
%y = extractelement <2 x i16> %coords_lo, i32 1
@@ -288,10 +289,10 @@ define amdgpu_ps void @store_v3f32_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_l
; GFX11-NEXT: image_store v[2:5], v[0:1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_3D unorm a16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_v3f32_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[2:5], [v0, v1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_3D a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_v3f32_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[2:5], [v0, v1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_3D a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords_lo, i32 0
%y = extractelement <2 x i16> %coords_lo, i32 1
@@ -316,10 +317,10 @@ define amdgpu_ps void @store_v4f32_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_l
; GFX11-NEXT: image_store v[2:5], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16
; GFX11-NEXT: s_endpgm
;
-; GFX12-LABEL: store_v4f32_3d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: image_store v[2:5], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16
-; GFX12-NEXT: s_endpgm
+; GFX12PLUS-LABEL: store_v4f32_3d:
+; GFX12PLUS: ; %bb.0: ; %main_body
+; GFX12PLUS-NEXT: image_store v[2:5], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX12PLUS-NEXT: s_endpgm
main_body:
%x = extractelement <2 x i16> %coords_lo, i32 0
%y = extractelement <2 x i16> %coords_lo, i32 1
diff --git a/llvm/test/MC/AMDGPU/gfx13_asm_vimage.s b/llvm/test/MC/AMDGPU/gfx13_asm_vimage.s
new file mode 100644
index 0000000000000..3bb23043b5787
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx13_asm_vimage.s
@@ -0,0 +1,1030 @@
+// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1310 -show-encoding %s | FileCheck --check-prefixes=GFX13 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1310 -show-encoding %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1310 -show-encoding -disassemble | FileCheck --check-prefixes=GFX13 %s
+
+image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
+// GFX13: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_load v[1:4], [v2, v3], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+// GFX13: image_load v[1:4], [v2, v3], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0xc0,0xd3,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+
+image_load v[4:7], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_3D
+// GFX13: image_load v[4:7], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0xc0,0xd3,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_load v[252:255], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_load v[252:255], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0xc0,0xd3,0xfc,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_load v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_load v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x00,0xc0,0xd3,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_load v[0:3], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_load v[0:3], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0xc0,0xd3,0x00,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_load v[0:3], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_load v[0:3], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0x00,0xc0,0xd3,0x00,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_load v[0:3], [v4, v5, v6, v7], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_load v[0:3], [v4, v5, v6, v7], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x00,0xc0,0xd3,0x00,0x10,0x00,0x00,0x04,0x05,0x06,0x07]
+
+image_load v[0:1], v255, s[0:7] dmask:0x9 dim:1D
+// GFX13: image_load v[0:1], v255, s[0:7] dmask:0x9 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x40,0xd2,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+
+image_load v255, [v254, v255], s[0:7] dmask:0x1 dim:2D
+// GFX13: image_load v255, [v254, v255], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x40,0xd0,0xff,0x00,0x00,0x00,0xfe,0xff,0x00,0x00]
+
+image_load v0, [v2, v22, v222], s[0:7] dmask:0x1 dim:3D
+// GFX13: image_load v0, [v2, v22, v222], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x02,0x16,0xde,0x00]
+
+image_load v0, [v2, v3, v4], s[0:7] dmask:0x1 dim:CUBE
+// GFX13: image_load v0, [v2, v3, v4], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x02,0x03,0x04,0x00]
+
+image_load v0, [v2, v3], s[0:7] dmask:0x1 dim:1D_ARRAY
+// GFX13: image_load v0, [v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x02,0x03,0x00,0x00]
+
+image_load v0, [v2, v3, v4], s[0:7] dmask:0x1 dim:2D_ARRAY
+// GFX13: image_load v0, [v2, v3, v4], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x02,0x03,0x04,0x00]
+
+image_load v0, [v2, v3, v4], s[0:7] dmask:0x1 dim:2D_MSAA
+// GFX13: image_load v0, [v2, v3, v4], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x02,0x03,0x04,0x00]
+
+image_load v0, [v2, v3, v4, v5], s[0:7] dmask:0x1 dim:2D_MSAA_ARRAY
+// GFX13: image_load v0, [v2, v3, v4, v5], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x02,0x03,0x04,0x05]
+
+image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+// GFX13: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_load v[1:4], v2, s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_load v[1:4], v2, s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x00,0xc0,0xd3,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00]
+
+image_load v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+// GFX13: image_load v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_3D a16 ; encoding: [0x42,0x00,0xc0,0xd3,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_load v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_load v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x00,0xc0,0xd3,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_load v[0:3], v4, s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
+// GFX13: image_load v[0:3], v4, s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16 ; encoding: [0x44,0x00,0xc0,0xd3,0x00,0x10,0x00,0x00,0x04,0x00,0x00,0x00]
+
+image_load v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_load v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x00,0xc0,0xd3,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_load v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA a16
+// GFX13: image_load v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA a16 ; encoding: [0x46,0x00,0xc0,0xd3,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_load v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16
+// GFX13: image_load v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 ; encoding: [0x47,0x00,0xc0,0xd3,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D d16
+// GFX13: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D d16 ; encoding: [0x20,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_load v0, v0, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D d16
+// GFX13: image_load v0, v0, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D d16 ; encoding: [0x20,0x00,0x80,0xd1,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_load v[0:1], v0, s[0:7] dmask:0xe dim:SQ_RSRC_IMG_1D d16
+// GFX13: image_load v[0:1], v0, s[0:7] dmask:0xe dim:SQ_RSRC_IMG_1D d16 ; encoding: [0x20,0x00,0x80,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D d16
+// GFX13: image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D d16 ; encoding: [0x20,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_load v1, [v0, v1], s[16:23] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_load v1, [v0, v1], s[16:23] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x40,0xd0,0x01,0x20,0x00,0x00,0x00,0x01,0x00,0x00]
+
+image_load v[1:2], [v0, v1], s[16:23] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe
+// GFX13: image_load v[1:2], [v0, v1], s[16:23] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x01,0x00,0x40,0xd0,0x01,0x20,0x80,0x00,0x00,0x01,0x00,0x00]
+
+image_load v[1:2], [v0, v1], s[16:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
+// GFX13: image_load v[1:2], [v0, v1], s[16:23] dmask:0x3 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0xc0,0xd0,0x01,0x20,0x00,0x00,0x00,0x01,0x00,0x00]
+
+image_load v[1:3], [v0, v1], s[16:23] dmask:0x3 dim:SQ_RSRC_IMG_2D tfe
+// GFX13: image_load v[1:3], [v0, v1], s[16:23] dmask:0x3 dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x01,0x00,0xc0,0xd0,0x01,0x20,0x80,0x00,0x00,0x01,0x00,0x00]
+
+image_load v[1:3], [v0, v1], s[16:23] dmask:0x7 dim:SQ_RSRC_IMG_2D
+// GFX13: image_load v[1:3], [v0, v1], s[16:23] dmask:0x7 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0xc0,0xd1,0x01,0x20,0x00,0x00,0x00,0x01,0x00,0x00]
+
+image_load v[1:4], [v0, v1], s[16:23] dmask:0x7 dim:SQ_RSRC_IMG_2D tfe
+// GFX13: image_load v[1:4], [v0, v1], s[16:23] dmask:0x7 dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x01,0x00,0xc0,0xd1,0x01,0x20,0x80,0x00,0x00,0x01,0x00,0x00]
+
+image_load v[1:4], [v0, v1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D
+// GFX13: image_load v[1:4], [v0, v1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0xc0,0xd3,0x01,0x20,0x00,0x00,0x00,0x01,0x00,0x00]
+
+image_load v[1:5], [v0, v1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D tfe
+// GFX13: image_load v[1:5], [v0, v1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x01,0x00,0xc0,0xd3,0x01,0x20,0x80,0x00,0x00,0x01,0x00,0x00]
+
+// FIXME: This test is incorrect because r128 assumes a 128-bit RSRC.
+image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
+// GFX13: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_CU
+// GFX13: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_SE
+// GFX13: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_SE ; encoding: [0x00,0x00,0x40,0xd0,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00]
+
+image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_DEV
+// GFX13: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_DEV ; encoding: [0x00,0x00,0x40,0xd0,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00]
+
+image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_SYS
+// GFX13: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_SYS ; encoding: [0x00,0x00,0x40,0xd0,0x00,0x00,0x0c,0x00,0x00,0x00,0x00,0x00]
+
+image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_RT
+// GFX13: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT
+// GFX13: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT ; encoding: [0x00,0x00,0x40,0xd0,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00]
+
+image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_HT
+// GFX13: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_HT ; encoding: [0x00,0x00,0x40,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
+
+image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_LU
+// GFX13: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_LU ; encoding: [0x00,0x00,0x40,0xd0,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00]
+
+image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT_RT
+// GFX13: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT_RT ; encoding: [0x00,0x00,0x40,0xd0,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00]
+
+image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_RT_NT
+// GFX13: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_RT_NT ; encoding: [0x00,0x00,0x40,0xd0,0x00,0x00,0x50,0x00,0x00,0x00,0x00,0x00]
+
+image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT_HT
+// GFX13: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT_HT ; encoding: [0x00,0x00,0x40,0xd0,0x00,0x00,0x60,0x00,0x00,0x00,0x00,0x00]
+
+image_load v[0:2], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY th:TH_LOAD_HT scope:SCOPE_SE a16 tfe d16
+// GFX13: image_load v[0:2], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY th:TH_LOAD_HT scope:SCOPE_SE a16 tfe d16 ; encoding: [0x65,0x00,0xc0,0xd3,0x00,0x10,0xa4,0x00,0x04,0x05,0x00,0x00]
+
+// FIXME: This test is incorrect because r128 assumes a 128-bit RSRC.
+image_load v[0:2], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY th:TH_LOAD_HT scope:SCOPE_SE r128 a16 tfe d16
+// GFX13: image_load v[0:2], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY th:TH_LOAD_HT scope:SCOPE_SE r128 a16 tfe d16 ; encoding: [0x75,0x00,0xc0,0xd3,0x00,0x10,0xa4,0x00,0x04,0x05,0x00,0x00]
+
+image_load v[4:7], [v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+// GFX13: image_load v[4:7], [v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0xc0,0xd3,0x04,0x08,0x00,0x00,0x01,0x00,0x00,0x00]
+
+image_load v[1:4], [v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_3D
+// GFX13: image_load v[1:4], [v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0xc0,0xd3,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00]
+
+image_load v[1:4], [v3, v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_load v[1:4], [v3, v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x00,0xc0,0xd3,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00]
+
+image_load_mip v[252:255], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
+// GFX13: image_load_mip v[252:255], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0xc0,0xd3,0xfc,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
+
+image_load_mip v[253:255], [v255, v254], s[0:7] dmask:0xe dim:SQ_RSRC_IMG_1D
+// GFX13: image_load_mip v[253:255], [v255, v254], s[0:7] dmask:0xe dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0x80,0xd3,0xfd,0x00,0x00,0x00,0xff,0xfe,0x00,0x00]
+
+image_load_mip v[254:255], [v254, v255, v253], s[0:7] dmask:0xc dim:SQ_RSRC_IMG_2D
+// GFX13: image_load_mip v[254:255], [v254, v255, v253], s[0:7] dmask:0xc dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0x00,0xd3,0xfe,0x00,0x00,0x00,0xfe,0xff,0xfd,0x00]
+
+image_load_mip v255, [v254, v255, v253, v252], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_3D
+// GFX13: image_load_mip v255, [v254, v255, v253, v252], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x40,0x00,0xd2,0xff,0x00,0x00,0x00,0xfe,0xff,0xfd,0xfc]
+
+image_load_mip v255, [v254, v255, v253, v252], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_load_mip v255, [v254, v255, v253, v252], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x40,0x00,0xd2,0xff,0x00,0x00,0x00,0xfe,0xff,0xfd,0xfc]
+
+image_load_mip v255, [v254, v255, v253], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_load_mip v255, [v254, v255, v253], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x40,0x00,0xd2,0xff,0x00,0x00,0x00,0xfe,0xff,0xfd,0x00]
+
+image_load_mip v255, [v254, v255, v253, v255], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_load_mip v255, [v254, v255, v253, v255], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x40,0x00,0xd2,0xff,0x00,0x00,0x00,0xfe,0xff,0xfd,0xff]
+
+image_load_mip v[252:255], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT
+// GFX13: image_load_mip v[252:255], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT ; encoding: [0x00,0x40,0xc0,0xd3,0xfc,0x00,0x10,0x00,0x00,0x01,0x00,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_load_pck v5, v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x40,0xd0,0x05,0x10,0x00,0x00,0x01,0x00,0x00,0x00]
+
+image_load_pck v[5:6], [v1, v2], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D
+// GFX13: image_load_pck v[5:6], [v1, v2], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0xc0,0xd0,0x05,0x10,0x00,0x00,0x01,0x02,0x00,0x00]
+
+image_load_pck v[5:6], [v1, v2, v3], s[8:15] dmask:0xc dim:SQ_RSRC_IMG_3D
+// GFX13: image_load_pck v[5:6], [v1, v2, v3], s[8:15] dmask:0xc dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0x00,0xd3,0x05,0x10,0x00,0x00,0x01,0x02,0x03,0x00]
+
+image_load_pck v[5:6], [v1, v2, v3], s[8:15] dmask:0xa dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_load_pck v[5:6], [v1, v2, v3], s[8:15] dmask:0xa dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x80,0xd2,0x05,0x10,0x00,0x00,0x01,0x02,0x03,0x00]
+
+image_load_pck v[5:7], [v1, v2], s[8:15] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_load_pck v[5:7], [v1, v2], s[8:15] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x80,0xc0,0xd2,0x05,0x10,0x00,0x00,0x01,0x02,0x00,0x00]
+
+image_load_pck v[5:7], [v1, v2, v3], s[8:15] dmask:0xd dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_load_pck v[5:7], [v1, v2, v3], s[8:15] dmask:0xd dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0x40,0xd3,0x05,0x10,0x00,0x00,0x01,0x02,0x03,0x00]
+
+image_load_pck v[5:7], [v1, v2, v3], s[8:15] dmask:0x7 dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_load_pck v[5:7], [v1, v2, v3], s[8:15] dmask:0x7 dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0x80,0xc0,0xd1,0x05,0x10,0x00,0x00,0x01,0x02,0x03,0x00]
+
+image_load_pck v[5:8], [v1, v2, v3, v4], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_load_pck v[5:8], [v1, v2, v3, v4], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x80,0xc0,0xd3,0x05,0x10,0x00,0x00,0x01,0x02,0x03,0x04]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x40,0xd0,0x05,0x10,0x00,0x00,0x01,0x00,0x00,0x00]
+
+image_load_pck_sgn v[5:6], [v1, v2], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D
+// GFX13: image_load_pck_sgn v[5:6], [v1, v2], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0xc0,0xd0,0x05,0x10,0x00,0x00,0x01,0x02,0x00,0x00]
+
+image_load_pck_sgn v[5:6], [v1, v2, v3], s[8:15] dmask:0xc dim:SQ_RSRC_IMG_3D
+// GFX13: image_load_pck_sgn v[5:6], [v1, v2, v3], s[8:15] dmask:0xc dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0xc0,0x00,0xd3,0x05,0x10,0x00,0x00,0x01,0x02,0x03,0x00]
+
+image_load_pck_sgn v[5:6], [v1, v2, v3], s[8:15] dmask:0xa dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_load_pck_sgn v[5:6], [v1, v2, v3], s[8:15] dmask:0xa dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x80,0xd2,0x05,0x10,0x00,0x00,0x01,0x02,0x03,0x00]
+
+image_load_pck_sgn v[5:7], [v1, v2], s[8:15] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_load_pck_sgn v[5:7], [v1, v2], s[8:15] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0xc0,0xc0,0xd2,0x05,0x10,0x00,0x00,0x01,0x02,0x00,0x00]
+
+image_load_pck_sgn v[5:7], [v1, v2, v3], s[8:15] dmask:0xd dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_load_pck_sgn v[5:7], [v1, v2, v3], s[8:15] dmask:0xd dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0x40,0xd3,0x05,0x10,0x00,0x00,0x01,0x02,0x03,0x00]
+
+image_load_pck_sgn v[5:7], [v1, v2, v3], s[8:15] dmask:0x7 dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_load_pck_sgn v[5:7], [v1, v2, v3], s[8:15] dmask:0x7 dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0xc0,0xc0,0xd1,0x05,0x10,0x00,0x00,0x01,0x02,0x03,0x00]
+
+image_load_pck_sgn v[5:8], [v1, v2, v3, v4], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_load_pck_sgn v[5:8], [v1, v2, v3, v4], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0xc0,0xc0,0xd3,0x05,0x10,0x00,0x00,0x01,0x02,0x03,0x04]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT
+// GFX13: image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT ; encoding: [0x00,0xc0,0x40,0xd0,0x05,0x10,0x10,0x00,0x01,0x00,0x00,0x00]
+
+image_load_mip_pck v5, [v0, v1], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_load_mip_pck v5, [v0, v1], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x41,0xd0,0x05,0x10,0x00,0x00,0x00,0x01,0x00,0x00]
+
+image_load_mip_pck v[5:6], [v0, v1, v2], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D
+// GFX13: image_load_mip_pck v[5:6], [v0, v1, v2], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0xc1,0xd0,0x05,0x10,0x00,0x00,0x00,0x01,0x02,0x00]
+
+image_load_mip_pck v[5:6], [v0, v1, v2, v3], s[8:15] dmask:0xc dim:SQ_RSRC_IMG_3D
+// GFX13: image_load_mip_pck v[5:6], [v0, v1, v2, v3], s[8:15] dmask:0xc dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0x01,0xd3,0x05,0x10,0x00,0x00,0x00,0x01,0x02,0x03]
+
+image_load_mip_pck v[5:6], [v0, v1, v2, v3], s[8:15] dmask:0xa dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_load_mip_pck v[5:6], [v0, v1, v2, v3], s[8:15] dmask:0xa dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0x81,0xd2,0x05,0x10,0x00,0x00,0x00,0x01,0x02,0x03]
+
+image_load_mip_pck v[5:7], [v0, v1, v2], s[8:15] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_load_mip_pck v[5:7], [v0, v1, v2], s[8:15] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x00,0xc1,0xd2,0x05,0x10,0x00,0x00,0x00,0x01,0x02,0x00]
+
+image_load_mip_pck v[5:7], [v0, v1, v2, v3], s[8:15] dmask:0xd dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_load_mip_pck v[5:7], [v0, v1, v2, v3], s[8:15] dmask:0xd dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0x41,0xd3,0x05,0x10,0x00,0x00,0x00,0x01,0x02,0x03]
+
+image_load_mip_pck v5, [v0, v1], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT
+// GFX13: image_load_mip_pck v5, [v0, v1], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT ; encoding: [0x00,0x00,0x41,0xd0,0x05,0x10,0x10,0x00,0x00,0x01,0x00,0x00]
+
+image_load_mip_pck_sgn v5, [v0, v1], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_load_mip_pck_sgn v5, [v0, v1], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0x41,0xd0,0x05,0x10,0x00,0x00,0x00,0x01,0x00,0x00]
+
+image_load_mip_pck_sgn v[5:6], [v0, v1, v2], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D
+// GFX13: image_load_mip_pck_sgn v[5:6], [v0, v1, v2], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0xc1,0xd0,0x05,0x10,0x00,0x00,0x00,0x01,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], [v0, v1, v2, v3], s[8:15] dmask:0xc dim:SQ_RSRC_IMG_3D
+// GFX13: image_load_mip_pck_sgn v[5:6], [v0, v1, v2, v3], s[8:15] dmask:0xc dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x40,0x01,0xd3,0x05,0x10,0x00,0x00,0x00,0x01,0x02,0x03]
+
+image_load_mip_pck_sgn v[5:6], [v0, v1, v2, v3], s[8:15] dmask:0xa dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_load_mip_pck_sgn v[5:6], [v0, v1, v2, v3], s[8:15] dmask:0xa dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x40,0x81,0xd2,0x05,0x10,0x00,0x00,0x00,0x01,0x02,0x03]
+
+image_load_mip_pck_sgn v[5:7], [v0, v1, v2], s[8:15] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_load_mip_pck_sgn v[5:7], [v0, v1, v2], s[8:15] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x40,0xc1,0xd2,0x05,0x10,0x00,0x00,0x00,0x01,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:7], [v0, v1, v2, v3], s[8:15] dmask:0xd dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_load_mip_pck_sgn v[5:7], [v0, v1, v2, v3], s[8:15] dmask:0xd dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x40,0x41,0xd3,0x05,0x10,0x00,0x00,0x00,0x01,0x02,0x03]
+
+image_load_mip_pck_sgn v5, [v0, v1], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT
+// GFX13: image_load_mip_pck_sgn v5, [v0, v1], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT ; encoding: [0x00,0x40,0x41,0xd0,0x05,0x10,0x10,0x00,0x00,0x01,0x00,0x00]
+
+image_store v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
+// GFX13: image_store v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0xc2,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_store v[1:4], [v2, v3], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+// GFX13: image_store v[1:4], [v2, v3], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0xc2,0xd3,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+
+image_store v[4:7], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_3D
+// GFX13: image_store v[4:7], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0xc2,0xd3,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_store v[252:255], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_store v[252:255], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0xc2,0xd3,0xfc,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_store v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_store v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x00,0xc2,0xd3,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_store v[0:3], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_store v[0:3], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0xc2,0xd3,0x00,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_store v[0:3], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_store v[0:3], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0x00,0xc2,0xd3,0x00,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_store v[0:3], [v4, v5, v6, v7], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_store v[0:3], [v4, v5, v6, v7], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x00,0xc2,0xd3,0x00,0x10,0x00,0x00,0x04,0x05,0x06,0x07]
+
+image_store v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+// GFX13: image_store v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x00,0xc2,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_store v[1:4], v2, s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_store v[1:4], v2, s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x00,0xc2,0xd3,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00]
+
+image_store v[4:7], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+// GFX13: image_store v[4:7], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_3D a16 ; encoding: [0x42,0x00,0xc2,0xd3,0x04,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_store v[252:255], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_store v[252:255], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x00,0xc2,0xd3,0xfc,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_store v[0:3], v4, s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
+// GFX13: image_store v[0:3], v4, s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16 ; encoding: [0x44,0x00,0xc2,0xd3,0x00,0x10,0x00,0x00,0x04,0x00,0x00,0x00]
+
+image_store v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_store v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x00,0xc2,0xd3,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_store v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA a16
+// GFX13: image_store v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA a16 ; encoding: [0x46,0x00,0xc2,0xd3,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_store v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16
+// GFX13: image_store v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 ; encoding: [0x47,0x00,0xc2,0xd3,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D d16
+// GFX13: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D d16 ; encoding: [0x20,0x00,0x42,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_store v0, v0, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D d16
+// GFX13: image_store v0, v0, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D d16 ; encoding: [0x20,0x00,0x82,0xd1,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_store v[0:1], v0, s[0:7] dmask:0xe dim:SQ_RSRC_IMG_1D d16
+// GFX13: image_store v[0:1], v0, s[0:7] dmask:0xe dim:SQ_RSRC_IMG_1D d16 ; encoding: [0x20,0x00,0x82,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_store v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D d16
+// GFX13: image_store v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D d16 ; encoding: [0x20,0x00,0xc2,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_store v1, [v0, v1], s[16:23] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_store v1, [v0, v1], s[16:23] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x42,0xd0,0x01,0x20,0x00,0x00,0x00,0x01,0x00,0x00]
+
+image_store v[1:2], [v0, v1], s[16:23] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe
+// GFX13: image_store v[1:2], [v0, v1], s[16:23] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x01,0x00,0x42,0xd0,0x01,0x20,0x80,0x00,0x00,0x01,0x00,0x00]
+
+image_store v[1:2], [v0, v1], s[16:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
+// GFX13: image_store v[1:2], [v0, v1], s[16:23] dmask:0x3 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0xc2,0xd0,0x01,0x20,0x00,0x00,0x00,0x01,0x00,0x00]
+
+image_store v[1:3], [v0, v1], s[16:23] dmask:0x3 dim:SQ_RSRC_IMG_2D tfe
+// GFX13: image_store v[1:3], [v0, v1], s[16:23] dmask:0x3 dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x01,0x00,0xc2,0xd0,0x01,0x20,0x80,0x00,0x00,0x01,0x00,0x00]
+
+image_store v[1:3], [v0, v1], s[16:23] dmask:0x7 dim:SQ_RSRC_IMG_2D
+// GFX13: image_store v[1:3], [v0, v1], s[16:23] dmask:0x7 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0xc2,0xd1,0x01,0x20,0x00,0x00,0x00,0x01,0x00,0x00]
+
+image_store v[1:4], [v0, v1], s[16:23] dmask:0x7 dim:SQ_RSRC_IMG_2D tfe
+// GFX13: image_store v[1:4], [v0, v1], s[16:23] dmask:0x7 dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x01,0x00,0xc2,0xd1,0x01,0x20,0x80,0x00,0x00,0x01,0x00,0x00]
+
+image_store v[1:4], [v0, v1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D
+// GFX13: image_store v[1:4], [v0, v1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0xc2,0xd3,0x01,0x20,0x00,0x00,0x00,0x01,0x00,0x00]
+
+image_store v[1:5], [v0, v1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D tfe
+// GFX13: image_store v[1:5], [v0, v1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x01,0x00,0xc2,0xd3,0x01,0x20,0x80,0x00,0x00,0x01,0x00,0x00]
+
+// FIXME: This test is incorrect because r128 assumes a 128-bit RSRC.
+image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
+// GFX13: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0x00,0x42,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_CU
+// GFX13: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x42,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_SE
+// GFX13: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_SE ; encoding: [0x00,0x00,0x42,0xd0,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00]
+
+image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_DEV
+// GFX13: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_DEV ; encoding: [0x00,0x00,0x42,0xd0,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00]
+
+image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_SYS
+// GFX13: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_SYS ; encoding: [0x00,0x00,0x42,0xd0,0x00,0x00,0x0c,0x00,0x00,0x00,0x00,0x00]
+
+image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_RT
+// GFX13: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x42,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_NT
+// GFX13: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_NT ; encoding: [0x00,0x00,0x42,0xd0,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00]
+
+image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_HT
+// GFX13: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_HT ; encoding: [0x00,0x00,0x42,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
+
+image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_WB
+// GFX13: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_WB ; encoding: [0x00,0x00,0x42,0xd0,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00]
+
+image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_NT_RT
+// GFX13: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_NT_RT ; encoding: [0x00,0x00,0x42,0xd0,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00]
+
+image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_RT_NT
+// GFX13: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_RT_NT ; encoding: [0x00,0x00,0x42,0xd0,0x00,0x00,0x50,0x00,0x00,0x00,0x00,0x00]
+
+image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_NT_HT
+// GFX13: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_NT_HT ; encoding: [0x00,0x00,0x42,0xd0,0x00,0x00,0x60,0x00,0x00,0x00,0x00,0x00]
+
+image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_NT_WB
+// GFX13: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_NT_WB ; encoding: [0x00,0x00,0x42,0xd0,0x00,0x00,0x70,0x00,0x00,0x00,0x00,0x00]
+
+image_store v[1:4], [v2, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+// GFX13: image_store v[1:4], [v2, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0xc2,0xd3,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00]
+
+image_store v[1:4], [v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_3D
+// GFX13: image_store v[1:4], [v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0xc2,0xd3,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00]
+
+image_store v[1:4], [v3, v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_store v[1:4], [v3, v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x00,0xc2,0xd3,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00]
+
+image_store_mip v[252:255], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
+// GFX13: image_store_mip v[252:255], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0xc2,0xd3,0xfc,0x00,0x00,0x00,0x00,0x01,0x00,0x00]
+
+image_store_mip v[253:255], [v255, v254], s[0:7] dmask:0xe dim:SQ_RSRC_IMG_1D
+// GFX13: image_store_mip v[253:255], [v255, v254], s[0:7] dmask:0xe dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0x82,0xd3,0xfd,0x00,0x00,0x00,0xff,0xfe,0x00,0x00]
+
+image_store_mip v[254:255], [v254, v255, v253], s[0:7] dmask:0xc dim:SQ_RSRC_IMG_2D
+// GFX13: image_store_mip v[254:255], [v254, v255, v253], s[0:7] dmask:0xc dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0x02,0xd3,0xfe,0x00,0x00,0x00,0xfe,0xff,0xfd,0x00]
+
+image_store_mip v255, [v254, v255, v253, v252], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_3D
+// GFX13: image_store_mip v255, [v254, v255, v253, v252], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x40,0x02,0xd2,0xff,0x00,0x00,0x00,0xfe,0xff,0xfd,0xfc]
+
+image_store_mip v255, [v254, v255, v253, v252], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_store_mip v255, [v254, v255, v253, v252], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x40,0x02,0xd2,0xff,0x00,0x00,0x00,0xfe,0xff,0xfd,0xfc]
+
+image_store_mip v255, [v254, v255, v253], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_store_mip v255, [v254, v255, v253], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x40,0x02,0xd2,0xff,0x00,0x00,0x00,0xfe,0xff,0xfd,0x00]
+
+image_store_mip v255, [v254, v255, v253, v255], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_store_mip v255, [v254, v255, v253, v255], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x40,0x02,0xd2,0xff,0x00,0x00,0x00,0xfe,0xff,0xfd,0xff]
+
+image_store_mip v[252:255], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_NT
+// GFX13: image_store_mip v[252:255], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_NT ; encoding: [0x00,0x40,0xc2,0xd3,0xfc,0x00,0x10,0x00,0x00,0x01,0x00,0x00]
+
+image_store_pck v5, v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_store_pck v5, v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x42,0xd0,0x05,0x10,0x00,0x00,0x01,0x00,0x00,0x00]
+
+image_store_pck v[5:6], [v1, v2], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D
+// GFX13: image_store_pck v[5:6], [v1, v2], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0xc2,0xd0,0x05,0x10,0x00,0x00,0x01,0x02,0x00,0x00]
+
+image_store_pck v[5:6], [v1, v2, v3], s[8:15] dmask:0xc dim:SQ_RSRC_IMG_3D
+// GFX13: image_store_pck v[5:6], [v1, v2, v3], s[8:15] dmask:0xc dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0x02,0xd3,0x05,0x10,0x00,0x00,0x01,0x02,0x03,0x00]
+
+image_store_pck v[5:6], [v1, v2, v3], s[8:15] dmask:0xa dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_store_pck v[5:6], [v1, v2, v3], s[8:15] dmask:0xa dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x82,0xd2,0x05,0x10,0x00,0x00,0x01,0x02,0x03,0x00]
+
+image_store_pck v[5:7], [v1, v2], s[8:15] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_store_pck v[5:7], [v1, v2], s[8:15] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x80,0xc2,0xd2,0x05,0x10,0x00,0x00,0x01,0x02,0x00,0x00]
+
+image_store_pck v[5:7], [v1, v2, v3], s[8:15] dmask:0xd dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_store_pck v[5:7], [v1, v2, v3], s[8:15] dmask:0xd dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0x42,0xd3,0x05,0x10,0x00,0x00,0x01,0x02,0x03,0x00]
+
+image_store_pck v[5:7], [v1, v2, v3], s[8:15] dmask:0x7 dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_store_pck v[5:7], [v1, v2, v3], s[8:15] dmask:0x7 dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0x80,0xc2,0xd1,0x05,0x10,0x00,0x00,0x01,0x02,0x03,0x00]
+
+image_store_pck v[5:8], [v1, v2, v3, v4], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_store_pck v[5:8], [v1, v2, v3, v4], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x80,0xc2,0xd3,0x05,0x10,0x00,0x00,0x01,0x02,0x03,0x04]
+
+image_store_mip_pck v5, [v0, v1], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_store_mip_pck v5, [v0, v1], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x42,0xd0,0x05,0x10,0x00,0x00,0x00,0x01,0x00,0x00]
+
+image_store_mip_pck v[5:6], [v0, v1, v2], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D
+// GFX13: image_store_mip_pck v[5:6], [v0, v1, v2], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0xc2,0xd0,0x05,0x10,0x00,0x00,0x00,0x01,0x02,0x00]
+
+image_store_mip_pck v[5:6], [v0, v1, v2, v3], s[8:15] dmask:0xc dim:SQ_RSRC_IMG_3D
+// GFX13: image_store_mip_pck v[5:6], [v0, v1, v2, v3], s[8:15] dmask:0xc dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0xc0,0x02,0xd3,0x05,0x10,0x00,0x00,0x00,0x01,0x02,0x03]
+
+image_store_mip_pck v[5:6], [v0, v1, v2, v3], s[8:15] dmask:0xa dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_store_mip_pck v[5:6], [v0, v1, v2, v3], s[8:15] dmask:0xa dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x82,0xd2,0x05,0x10,0x00,0x00,0x00,0x01,0x02,0x03]
+
+image_store_mip_pck v[5:7], [v0, v1, v2], s[8:15] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_store_mip_pck v[5:7], [v0, v1, v2], s[8:15] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0xc0,0xc2,0xd2,0x05,0x10,0x00,0x00,0x00,0x01,0x02,0x00]
+
+image_store_mip_pck v[5:7], [v0, v1, v2, v3], s[8:15] dmask:0xd dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_store_mip_pck v[5:7], [v0, v1, v2, v3], s[8:15] dmask:0xd dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0x42,0xd3,0x05,0x10,0x00,0x00,0x00,0x01,0x02,0x03]
+
+image_store_mip_pck v5, [v0, v1], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_NT
+// GFX13: image_store_mip_pck v5, [v0, v1], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_NT ; encoding: [0x00,0xc0,0x42,0xd0,0x05,0x10,0x10,0x00,0x00,0x01,0x00,0x00]
+
+image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x43,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_swap v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_atomic_swap v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x43,0xd0,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+
+image_atomic_swap v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D
+// GFX13: image_atomic_swap v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0xc0,0x43,0xd0,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_swap v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_atomic_swap v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x43,0xd0,0xff,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_swap v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_atomic_swap v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0xc0,0xc3,0xd0,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_swap v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_atomic_swap v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0xc3,0xd0,0x01,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_swap v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_atomic_swap v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0xc0,0xc3,0xd0,0x03,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_swap v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_atomic_swap v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0xc0,0xc3,0xd0,0xfe,0xc0,0x00,0x00,0x04,0x05,0x06,0x07]
+
+image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_CU
+// GFX13: image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x43,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_SE
+// GFX13: image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_SE ; encoding: [0x00,0xc0,0x43,0xd0,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_DEV
+// GFX13: image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_DEV ; encoding: [0x00,0xc0,0x43,0xd0,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_SYS
+// GFX13: image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_SYS ; encoding: [0x00,0xc0,0x43,0xd0,0x00,0x00,0x0c,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN
+// GFX13: image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; encoding: [0x00,0xc0,0x43,0xd0,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RT
+// GFX13: image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x43,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RT_RETURN
+// GFX13: image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; encoding: [0x00,0xc0,0x43,0xd0,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT
+// GFX13: image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT ; encoding: [0x00,0xc0,0x43,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT_RETURN
+// GFX13: image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT_RETURN ; encoding: [0x00,0xc0,0x43,0xd0,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_CASCADE_RT scope:SCOPE_DEV
+// GFX13: image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_CASCADE_RT scope:SCOPE_DEV ; encoding: [0x00,0xc0,0x43,0xd0,0x00,0x00,0x48,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_CASCADE_NT scope:SCOPE_SYS
+// GFX13: image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_CASCADE_NT scope:SCOPE_SYS ; encoding: [0x00,0xc0,0x43,0xd0,0x00,0x00,0x6c,0x00,0x00,0x00,0x00,0x00]
+
+// FIXME: This test is incorrect because r128 assumes a 128-bit RSRC.
+image_atomic_swap v0, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D r128
+// GFX13: image_atomic_swap v0, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D r128 ; encoding: [0x11,0xc0,0x43,0xd0,0x00,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+
+image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D a16
+// GFX13: image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0xc0,0x43,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_swap v1, v2, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_atomic_swap v1, v2, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0xc0,0x43,0xd0,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00]
+
+image_atomic_swap v4, [v4, v5], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D a16
+// GFX13: image_atomic_swap v4, [v4, v5], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D a16 ; encoding: [0x42,0xc0,0x43,0xd0,0x04,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_swap v255, [v4, v5], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_atomic_swap v255, [v4, v5], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0xc0,0x43,0xd0,0xff,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_swap v[0:1], v4, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY a16
+// GFX13: image_atomic_swap v[0:1], v4, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY a16 ; encoding: [0x44,0xc0,0xc3,0xd0,0x00,0x10,0x00,0x00,0x04,0x00,0x00,0x00]
+
+image_atomic_swap v[1:2], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_atomic_swap v[1:2], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0xc0,0xc3,0xd0,0x01,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_swap v[3:4], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA a16
+// GFX13: image_atomic_swap v[3:4], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA a16 ; encoding: [0x46,0xc0,0xc3,0xd0,0x03,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_swap v[254:255], [v4, v5], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16
+// GFX13: image_atomic_swap v[254:255], [v4, v5], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 ; encoding: [0x47,0xc0,0xc3,0xd0,0xfe,0xc0,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_swap v1, [v2, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_atomic_swap v1, [v2, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x43,0xd0,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00]
+
+image_atomic_swap v1, [v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_3D
+// GFX13: image_atomic_swap v1, [v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0xc0,0x43,0xd0,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00]
+
+image_atomic_swap v1, [v3, v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_atomic_swap v1, [v3, v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0xc0,0x43,0xd0,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00]
+
+image_atomic_cmpswap v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_cmpswap v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0xc4,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_cmpswap v[1:2], [v2, v3], s[4:11] dmask:0x3 dim:SQ_RSRC_IMG_2D
+// GFX13: image_atomic_cmpswap v[1:2], [v2, v3], s[4:11] dmask:0x3 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0xc4,0xd0,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+
+image_atomic_cmpswap v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_atomic_cmpswap v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0xc4,0xd0,0x03,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_cmpswap v[254:255], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_atomic_cmpswap v[254:255], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0xc4,0xd0,0xfe,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_cmpswap v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_atomic_cmpswap v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x00,0xc4,0xd3,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_cmpswap v[1:4], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_atomic_cmpswap v[1:4], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0xc4,0xd3,0x01,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_cmpswap v[4:7], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_atomic_cmpswap v[4:7], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0x00,0xc4,0xd3,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_cmpswap v[252:255], [v4, v5, v6, v7], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_atomic_cmpswap v[252:255], [v4, v5, v6, v7], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x00,0xc4,0xd3,0xfc,0xc0,0x00,0x00,0x04,0x05,0x06,0x07]
+
+image_atomic_cmpswap v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT
+// GFX13: image_atomic_cmpswap v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT ; encoding: [0x00,0x00,0xc4,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_add_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_add_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0x44,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_add_uint v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_atomic_add_uint v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0x44,0xd0,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+
+image_atomic_add_uint v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D
+// GFX13: image_atomic_add_uint v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x40,0x44,0xd0,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_add_uint v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_atomic_add_uint v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x40,0x44,0xd0,0xff,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_add_uint v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_atomic_add_uint v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x40,0xc4,0xd0,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_add_uint v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_atomic_add_uint v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x40,0xc4,0xd0,0x01,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_add_uint v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_atomic_add_uint v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0x40,0xc4,0xd0,0x03,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_add_uint v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_atomic_add_uint v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x40,0xc4,0xd0,0xfe,0xc0,0x00,0x00,0x04,0x05,0x06,0x07]
+
+image_atomic_add_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT
+// GFX13: image_atomic_add_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT ; encoding: [0x00,0x40,0x44,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_add_uint v1, [v2, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_atomic_add_uint v1, [v2, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0x44,0xd0,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00]
+
+image_atomic_add_uint v1, [v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_3D
+// GFX13: image_atomic_add_uint v1, [v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x40,0x44,0xd0,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00]
+
+image_atomic_add_uint v1, [v3, v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_atomic_add_uint v1, [v3, v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x40,0x44,0xd0,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00]
+
+image_atomic_sub_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_sub_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x44,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_sub_uint v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_atomic_sub_uint v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x44,0xd0,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+
+image_atomic_sub_uint v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D
+// GFX13: image_atomic_sub_uint v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0x44,0xd0,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_sub_uint v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_atomic_sub_uint v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x44,0xd0,0xff,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_sub_uint v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_atomic_sub_uint v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x80,0xc4,0xd0,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_sub_uint v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_atomic_sub_uint v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0xc4,0xd0,0x01,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_sub_uint v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_atomic_sub_uint v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0x80,0xc4,0xd0,0x03,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_sub_uint v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_atomic_sub_uint v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x80,0xc4,0xd0,0xfe,0xc0,0x00,0x00,0x04,0x05,0x06,0x07]
+
+image_atomic_sub_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT
+// GFX13: image_atomic_sub_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT ; encoding: [0x00,0x80,0x44,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_min_int v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_min_int v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x45,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_min_int v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_atomic_min_int v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x45,0xd0,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+
+image_atomic_min_int v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D
+// GFX13: image_atomic_min_int v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0x45,0xd0,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_min_int v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_atomic_min_int v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0x45,0xd0,0xff,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_min_int v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_atomic_min_int v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x00,0xc5,0xd0,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_min_int v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_atomic_min_int v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0xc5,0xd0,0x01,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_min_int v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_atomic_min_int v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0x00,0xc5,0xd0,0x03,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_min_int v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_atomic_min_int v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x00,0xc5,0xd0,0xfe,0xc0,0x00,0x00,0x04,0x05,0x06,0x07]
+
+image_atomic_min_int v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT
+// GFX13: image_atomic_min_int v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT ; encoding: [0x00,0x00,0x45,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_min_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_min_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0x45,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_min_uint v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_atomic_min_uint v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0x45,0xd0,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+
+image_atomic_min_uint v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D
+// GFX13: image_atomic_min_uint v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x40,0x45,0xd0,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_min_uint v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_atomic_min_uint v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x40,0x45,0xd0,0xff,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_min_uint v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_atomic_min_uint v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x40,0xc5,0xd0,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_min_uint v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_atomic_min_uint v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x40,0xc5,0xd0,0x01,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_min_uint v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_atomic_min_uint v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0x40,0xc5,0xd0,0x03,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_min_uint v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_atomic_min_uint v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x40,0xc5,0xd0,0xfe,0xc0,0x00,0x00,0x04,0x05,0x06,0x07]
+
+image_atomic_min_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT
+// GFX13: image_atomic_min_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT ; encoding: [0x00,0x40,0x45,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_max_int v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_max_int v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x45,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_max_int v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_atomic_max_int v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x45,0xd0,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+
+image_atomic_max_int v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D
+// GFX13: image_atomic_max_int v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0x45,0xd0,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_max_int v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_atomic_max_int v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x45,0xd0,0xff,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_max_int v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_atomic_max_int v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x80,0xc5,0xd0,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_max_int v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_atomic_max_int v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0xc5,0xd0,0x01,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_max_int v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_atomic_max_int v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0x80,0xc5,0xd0,0x03,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_max_int v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_atomic_max_int v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x80,0xc5,0xd0,0xfe,0xc0,0x00,0x00,0x04,0x05,0x06,0x07]
+
+image_atomic_max_int v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT
+// GFX13: image_atomic_max_int v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT ; encoding: [0x00,0x80,0x45,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_max_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_max_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x45,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_max_uint v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_atomic_max_uint v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x45,0xd0,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+
+image_atomic_max_uint v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D
+// GFX13: image_atomic_max_uint v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0xc0,0x45,0xd0,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_max_uint v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_atomic_max_uint v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x45,0xd0,0xff,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_max_uint v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_atomic_max_uint v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0xc0,0xc5,0xd0,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_max_uint v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_atomic_max_uint v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0xc5,0xd0,0x01,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_max_uint v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_atomic_max_uint v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0xc0,0xc5,0xd0,0x03,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_max_uint v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_atomic_max_uint v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0xc0,0xc5,0xd0,0xfe,0xc0,0x00,0x00,0x04,0x05,0x06,0x07]
+
+image_atomic_max_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT
+// GFX13: image_atomic_max_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT ; encoding: [0x00,0xc0,0x45,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_and v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_and v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x46,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_and v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_atomic_and v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x46,0xd0,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+
+image_atomic_and v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D
+// GFX13: image_atomic_and v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0x46,0xd0,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_and v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_atomic_and v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0x46,0xd0,0xff,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_and v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_atomic_and v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x00,0xc6,0xd0,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_and v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_atomic_and v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0xc6,0xd0,0x01,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_and v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_atomic_and v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0x00,0xc6,0xd0,0x03,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_and v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_atomic_and v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x00,0xc6,0xd0,0xfe,0xc0,0x00,0x00,0x04,0x05,0x06,0x07]
+
+image_atomic_or v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_or v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0x46,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_or v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_atomic_or v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0x46,0xd0,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+
+image_atomic_or v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D
+// GFX13: image_atomic_or v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x40,0x46,0xd0,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_or v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_atomic_or v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x40,0x46,0xd0,0xff,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_or v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_atomic_or v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x40,0xc6,0xd0,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_or v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_atomic_or v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x40,0xc6,0xd0,0x01,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_or v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_atomic_or v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0x40,0xc6,0xd0,0x03,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_or v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_atomic_or v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x40,0xc6,0xd0,0xfe,0xc0,0x00,0x00,0x04,0x05,0x06,0x07]
+
+image_atomic_or v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT
+// GFX13: image_atomic_or v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT ; encoding: [0x00,0x40,0x46,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_xor v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_xor v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x46,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_xor v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_atomic_xor v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x46,0xd0,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+
+image_atomic_xor v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D
+// GFX13: image_atomic_xor v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0x46,0xd0,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_xor v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_atomic_xor v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x46,0xd0,0xff,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_xor v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_atomic_xor v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x80,0xc6,0xd0,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_xor v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_atomic_xor v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0xc6,0xd0,0x01,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_xor v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_atomic_xor v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0x80,0xc6,0xd0,0x03,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_xor v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_atomic_xor v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x80,0xc6,0xd0,0xfe,0xc0,0x00,0x00,0x04,0x05,0x06,0x07]
+
+image_atomic_xor v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT
+// GFX13: image_atomic_xor v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT ; encoding: [0x00,0x80,0x46,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_inc_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_inc_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x46,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_inc_uint v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_atomic_inc_uint v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x46,0xd0,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+
+image_atomic_inc_uint v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D
+// GFX13: image_atomic_inc_uint v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0xc0,0x46,0xd0,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_inc_uint v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_atomic_inc_uint v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x46,0xd0,0xff,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_inc_uint v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_atomic_inc_uint v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0xc0,0xc6,0xd0,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_inc_uint v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_atomic_inc_uint v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0xc6,0xd0,0x01,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_inc_uint v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_atomic_inc_uint v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0xc0,0xc6,0xd0,0x03,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_inc_uint v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_atomic_inc_uint v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0xc0,0xc6,0xd0,0xfe,0xc0,0x00,0x00,0x04,0x05,0x06,0x07]
+
+image_atomic_inc_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT
+// GFX13: image_atomic_inc_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT ; encoding: [0x00,0xc0,0x46,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_dec_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_dec_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x47,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_dec_uint v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_atomic_dec_uint v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x47,0xd0,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+
+image_atomic_dec_uint v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D
+// GFX13: image_atomic_dec_uint v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0x47,0xd0,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_dec_uint v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_atomic_dec_uint v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0x47,0xd0,0xff,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_dec_uint v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_atomic_dec_uint v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x00,0xc7,0xd0,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_dec_uint v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_atomic_dec_uint v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0xc7,0xd0,0x01,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_dec_uint v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_atomic_dec_uint v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0x00,0xc7,0xd0,0x03,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_dec_uint v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_atomic_dec_uint v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x00,0xc7,0xd0,0xfe,0xc0,0x00,0x00,0x04,0x05,0x06,0x07]
+
+image_atomic_dec_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT
+// GFX13: image_atomic_dec_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT ; encoding: [0x00,0x00,0x47,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_pk_add_f16 v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_pk_add_f16 v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x61,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_pk_add_f16 v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_atomic_pk_add_f16 v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x61,0xd0,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+
+image_atomic_pk_add_f16 v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D
+// GFX13: image_atomic_pk_add_f16 v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0x61,0xd0,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_pk_add_f16 v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_atomic_pk_add_f16 v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x61,0xd0,0xff,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_pk_add_f16 v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_atomic_pk_add_f16 v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x80,0xe1,0xd0,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_pk_add_f16 v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_atomic_pk_add_f16 v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0xe1,0xd0,0x01,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_pk_add_f16 v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_atomic_pk_add_f16 v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0x80,0xe1,0xd0,0x03,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_pk_add_f16 v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_atomic_pk_add_f16 v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x80,0xe1,0xd0,0xfe,0xc0,0x00,0x00,0x04,0x05,0x06,0x07]
+
+image_atomic_pk_add_f16 v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT
+// GFX13: image_atomic_pk_add_f16 v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT ; encoding: [0x00,0x80,0x61,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_pk_add_bf16 v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_pk_add_bf16 v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x61,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_pk_add_bf16 v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_atomic_pk_add_bf16 v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x61,0xd0,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+
+image_atomic_pk_add_bf16 v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D
+// GFX13: image_atomic_pk_add_bf16 v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0xc0,0x61,0xd0,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_pk_add_bf16 v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_atomic_pk_add_bf16 v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x61,0xd0,0xff,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_pk_add_bf16 v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_atomic_pk_add_bf16 v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0xc0,0xe1,0xd0,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_pk_add_bf16 v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_atomic_pk_add_bf16 v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0xe1,0xd0,0x01,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_pk_add_bf16 v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_atomic_pk_add_bf16 v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0xc0,0xe1,0xd0,0x03,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_pk_add_bf16 v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_atomic_pk_add_bf16 v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0xc0,0xe1,0xd0,0xfe,0xc0,0x00,0x00,0x04,0x05,0x06,0x07]
+
+image_atomic_pk_add_bf16 v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT
+// GFX13: image_atomic_pk_add_bf16 v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT ; encoding: [0x00,0xc0,0x61,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_add_flt v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_add_flt v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x60,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_add_flt v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_atomic_add_flt v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x60,0xd0,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+
+image_atomic_add_flt v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D
+// GFX13: image_atomic_add_flt v4, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0xc0,0x60,0xd0,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_add_flt v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_atomic_add_flt v255, [v4, v5, v6], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x60,0xd0,0xff,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_add_flt v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_atomic_add_flt v[0:1], [v4, v5], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0xc0,0xe0,0xd0,0x00,0x10,0x00,0x00,0x04,0x05,0x00,0x00]
+
+image_atomic_add_flt v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_atomic_add_flt v[1:2], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0xe0,0xd0,0x01,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_add_flt v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_atomic_add_flt v[3:4], [v4, v5, v6], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0xc0,0xe0,0xd0,0x03,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+
+image_atomic_add_flt v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_atomic_add_flt v[254:255], [v4, v5, v6, v7], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0xc0,0xe0,0xd0,0xfe,0xc0,0x00,0x00,0x04,0x05,0x06,0x07]
+
+image_get_resinfo v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_get_resinfo v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x43,0xd0,0x04,0xc0,0x00,0x00,0x20,0x00,0x00,0x00]
+
+image_get_resinfo v4, v32, s[96:103] dmask:0x2 dim:SQ_RSRC_IMG_2D
+// GFX13: image_get_resinfo v4, v32, s[96:103] dmask:0x2 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x83,0xd0,0x04,0xc0,0x00,0x00,0x20,0x00,0x00,0x00]
+
+image_get_resinfo v4, v32, s[96:103] dmask:0x8 dim:SQ_RSRC_IMG_3D
+// GFX13: image_get_resinfo v4, v32, s[96:103] dmask:0x8 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0x03,0xd2,0x04,0xc0,0x00,0x00,0x20,0x00,0x00,0x00]
+
+image_get_resinfo v[4:5], v32, s[96:103] dmask:0x5 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_get_resinfo v[4:5], v32, s[96:103] dmask:0x5 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x43,0xd1,0x04,0xc0,0x00,0x00,0x20,0x00,0x00,0x00]
+
+image_get_resinfo v[4:5], v32, s[96:103] dmask:0xa dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_get_resinfo v[4:5], v32, s[96:103] dmask:0xa dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x80,0x83,0xd2,0x04,0xc0,0x00,0x00,0x20,0x00,0x00,0x00]
+
+image_get_resinfo v[4:6], v32, s[96:103] dmask:0xb dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_get_resinfo v[4:6], v32, s[96:103] dmask:0xb dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0xc3,0xd2,0x04,0xc0,0x00,0x00,0x20,0x00,0x00,0x00]
+
+image_get_resinfo v[4:6], v32, s[96:103] dmask:0xe dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_get_resinfo v[4:6], v32, s[96:103] dmask:0xe dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0x80,0x83,0xd3,0x04,0xc0,0x00,0x00,0x20,0x00,0x00,0x00]
+
+image_get_resinfo v[4:7], v32, s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// GFX13: image_get_resinfo v[4:7], v32, s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x80,0xc3,0xd3,0x04,0xc0,0x00,0x00,0x20,0x00,0x00,0x00]
+
+image_get_resinfo v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_RT
+// GFX13: image_get_resinfo v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x43,0xd0,0x04,0xc0,0x00,0x00,0x20,0x00,0x00,0x00]
+
+image_get_resinfo v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT
+// GFX13: image_get_resinfo v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT ; encoding: [0x00,0x80,0x43,0xd0,0x04,0xc0,0x10,0x00,0x20,0x00,0x00,0x00]
+
+image_get_resinfo v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_HT
+// GFX13: image_get_resinfo v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_HT ; encoding: [0x00,0x80,0x43,0xd0,0x04,0xc0,0x20,0x00,0x20,0x00,0x00,0x00]
+
+image_get_resinfo v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_LU
+// GFX13: image_get_resinfo v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_LU ; encoding: [0x00,0x80,0x43,0xd0,0x04,0xc0,0x30,0x00,0x20,0x00,0x00,0x00]
+
+image_get_resinfo v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT_RT
+// GFX13: image_get_resinfo v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT_RT ; encoding: [0x00,0x80,0x43,0xd0,0x04,0xc0,0x40,0x00,0x20,0x00,0x00,0x00]
+
+image_get_resinfo v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_RT_NT
+// GFX13: image_get_resinfo v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_RT_NT ; encoding: [0x00,0x80,0x43,0xd0,0x04,0xc0,0x50,0x00,0x20,0x00,0x00,0x00]
+
+image_get_resinfo v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT_HT
+// GFX13: image_get_resinfo v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT_HT ; encoding: [0x00,0x80,0x43,0xd0,0x04,0xc0,0x60,0x00,0x20,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx13_asm_vimage_alias.s b/llvm/test/MC/AMDGPU/gfx13_asm_vimage_alias.s
new file mode 100644
index 0000000000000..70b2c1e74460d
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx13_asm_vimage_alias.s
@@ -0,0 +1,27 @@
+// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1310 -show-encoding %s | FileCheck --check-prefixes=GFX13 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1310 -show-encoding %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1310 -show-encoding -disassemble | FileCheck --check-prefixes=GFX13 %s
+
+image_atomic_add v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_add_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0x44,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_sub v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_sub_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x44,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_smin v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_min_int v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x45,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_umin v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_min_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0x45,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_smax v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_max_int v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x45,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_umax v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_max_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x45,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_inc v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_inc_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x46,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
+image_atomic_dec v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_atomic_dec_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x47,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx13_asm_vsample.s b/llvm/test/MC/AMDGPU/gfx13_asm_vsample.s
new file mode 100644
index 0000000000000..57aa768a1b26c
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx13_asm_vsample.s
@@ -0,0 +1,1208 @@
+// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1310 -show-encoding %s | FileCheck --check-prefixes=GFX13 %s
+
+image_sample v64, v32, s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample v64, v32, s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x48,0xe4,0x40,0x08,0x00,0x32,0x20,0x00,0x00,0x00]
+
+image_sample v64, [v32, v33], s[4:11], s[100:103] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample v64, [v32, v33], s[4:11], s[100:103] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x08,0xe6,0x40,0x08,0x00,0x32,0x20,0x21,0x00,0x00]
+
+image_sample v[64:65], [v32, v33, v34], s[4:11], s[100:103] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample v[64:65], [v32, v33, v34], s[4:11], s[100:103] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0xc8,0xe4,0x40,0x08,0x00,0x32,0x20,0x21,0x22,0x00]
+
+image_sample v[64:65], [v32, v33, v34], s[4:11], s[100:103] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample v[64:65], [v32, v33, v34], s[4:11], s[100:103] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0x08,0xe7,0x40,0x08,0x00,0x32,0x20,0x21,0x22,0x00]
+
+image_sample v[64:66], [v32, v33], s[4:11], s[100:103] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample v[64:66], [v32, v33], s[4:11], s[100:103] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x00,0xc8,0xe6,0x40,0x08,0x00,0x32,0x20,0x21,0x00,0x00]
+
+image_sample v[64:67], [v32, v33, v34], s[4:11], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample v[64:67], [v32, v33, v34], s[4:11], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0xc8,0xe7,0x40,0x08,0x00,0x32,0x20,0x21,0x22,0x00]
+
+image_sample v0, v1, s[0:7], s[100:103] dmask:0x2 dim:SQ_RSRC_IMG_1D a16
+// GFX13: image_sample v0, v1, s[0:7], s[100:103] dmask:0x2 dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x00,0x88,0xe4,0x00,0x00,0x00,0x32,0x01,0x00,0x00,0x00]
+
+image_sample v2, v3, s[4:11], s[96:99] dmask:0x4 dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_sample v2, v3, s[4:11], s[96:99] dmask:0x4 dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x00,0x08,0xe5,0x02,0x08,0x00,0x30,0x03,0x00,0x00,0x00]
+
+image_sample v[4:5], [v6, v7], s[8:15], s[92:95] dmask:0x6 dim:SQ_RSRC_IMG_3D a16
+// GFX13: image_sample v[4:5], [v6, v7], s[8:15], s[92:95] dmask:0x6 dim:SQ_RSRC_IMG_3D a16 ; encoding: [0x42,0x00,0x88,0xe5,0x04,0x10,0x00,0x2e,0x06,0x07,0x00,0x00]
+
+image_sample v[8:9], [v10, v11], s[12:19], s[88:91] dmask:0x9 dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_sample v[8:9], [v10, v11], s[12:19], s[88:91] dmask:0x9 dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x00,0x48,0xe6,0x08,0x18,0x00,0x2c,0x0a,0x0b,0x00,0x00]
+
+image_sample v[12:14], v15, s[16:23], s[84:87] dmask:0x7 dim:SQ_RSRC_IMG_1D_ARRAY a16
+// GFX13: image_sample v[12:14], v15, s[16:23], s[84:87] dmask:0x7 dim:SQ_RSRC_IMG_1D_ARRAY a16 ; encoding: [0x44,0x00,0xc8,0xe5,0x0c,0x20,0x00,0x2a,0x0f,0x00,0x00,0x00]
+
+image_sample v[16:19], [v20, v21], s[20:27], s[80:83] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_sample v[16:19], [v20, v21], s[20:27], s[80:83] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x00,0xc8,0xe7,0x10,0x28,0x00,0x28,0x14,0x15,0x00,0x00]
+
+image_sample v[22:24], v25, s[24:31], s[76:79] dmask:0xd dim:SQ_RSRC_IMG_1D unorm
+// GFX13: image_sample v[22:24], v25, s[24:31], s[76:79] dmask:0xd dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0x20,0x48,0xe7,0x16,0x30,0x00,0x26,0x19,0x00,0x00,0x00]
+
+// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
+image_sample v[22:24], v25, s[24:31], s[76:79] dmask:0xd dim:SQ_RSRC_IMG_1D r128
+// GFX13: image_sample v[22:24], v25, s[24:31], s[76:79] dmask:0xd dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0x00,0x48,0xe7,0x16,0x30,0x00,0x26,0x19,0x00,0x00,0x00]
+
+image_sample v26, [v27, v28], s[28:35], s[72:75] dmask:0x1 dim:SQ_RSRC_IMG_2D scope:SCOPE_CU
+// GFX13: image_sample v26, [v27, v28], s[28:35], s[72:75] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x48,0xe4,0x1a,0x38,0x00,0x24,0x1b,0x1c,0x00,0x00]
+
+image_sample v26, [v27, v28], s[28:35], s[72:75] dmask:0x2 dim:SQ_RSRC_IMG_2D scope:SCOPE_SE
+// GFX13: image_sample v26, [v27, v28], s[28:35], s[72:75] dmask:0x2 dim:SQ_RSRC_IMG_2D scope:SCOPE_SE ; encoding: [0x01,0x00,0x88,0xe4,0x1a,0x38,0x04,0x24,0x1b,0x1c,0x00,0x00]
+
+image_sample v26, [v27, v28], s[28:35], s[72:75] dmask:0x4 dim:SQ_RSRC_IMG_2D scope:SCOPE_DEV
+// GFX13: image_sample v26, [v27, v28], s[28:35], s[72:75] dmask:0x4 dim:SQ_RSRC_IMG_2D scope:SCOPE_DEV ; encoding: [0x01,0x00,0x08,0xe5,0x1a,0x38,0x08,0x24,0x1b,0x1c,0x00,0x00]
+
+image_sample v26, [v27, v28], s[28:35], s[72:75] dmask:0x8 dim:SQ_RSRC_IMG_2D scope:SCOPE_SYS
+// GFX13: image_sample v26, [v27, v28], s[28:35], s[72:75] dmask:0x8 dim:SQ_RSRC_IMG_2D scope:SCOPE_SYS ; encoding: [0x01,0x00,0x08,0xe6,0x1a,0x38,0x0c,0x24,0x1b,0x1c,0x00,0x00]
+
+image_sample v[29:30], [v31, v32, v33], s[32:39], s[68:71] dmask:0x3 dim:SQ_RSRC_IMG_3D th:TH_LOAD_RT
+// GFX13: image_sample v[29:30], [v31, v32, v33], s[32:39], s[68:71] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0xc8,0xe4,0x1d,0x40,0x00,0x22,0x1f,0x20,0x21,0x00]
+
+image_sample v[29:30], [v31, v32, v33], s[32:39], s[68:71] dmask:0x5 dim:SQ_RSRC_IMG_3D th:TH_LOAD_NT
+// GFX13: image_sample v[29:30], [v31, v32, v33], s[32:39], s[68:71] dmask:0x5 dim:SQ_RSRC_IMG_3D th:TH_LOAD_NT ; encoding: [0x02,0x00,0x48,0xe5,0x1d,0x40,0x10,0x22,0x1f,0x20,0x21,0x00]
+
+image_sample v[29:30], [v31, v32, v33], s[32:39], s[68:71] dmask:0x9 dim:SQ_RSRC_IMG_3D th:TH_LOAD_HT
+// GFX13: image_sample v[29:30], [v31, v32, v33], s[32:39], s[68:71] dmask:0x9 dim:SQ_RSRC_IMG_3D th:TH_LOAD_HT ; encoding: [0x02,0x00,0x48,0xe6,0x1d,0x40,0x20,0x22,0x1f,0x20,0x21,0x00]
+
+image_sample v[29:30], [v31, v32, v33], s[32:39], s[68:71] dmask:0x6 dim:SQ_RSRC_IMG_3D th:TH_LOAD_LU
+// GFX13: image_sample v[29:30], [v31, v32, v33], s[32:39], s[68:71] dmask:0x6 dim:SQ_RSRC_IMG_3D th:TH_LOAD_LU ; encoding: [0x02,0x00,0x88,0xe5,0x1d,0x40,0x30,0x22,0x1f,0x20,0x21,0x00]
+
+image_sample v[29:30], [v31, v32, v33], s[32:39], s[68:71] dmask:0xa dim:SQ_RSRC_IMG_3D th:TH_LOAD_NT_RT
+// GFX13: image_sample v[29:30], [v31, v32, v33], s[32:39], s[68:71] dmask:0xa dim:SQ_RSRC_IMG_3D th:TH_LOAD_NT_RT ; encoding: [0x02,0x00,0x88,0xe6,0x1d,0x40,0x40,0x22,0x1f,0x20,0x21,0x00]
+
+image_sample v[29:30], [v31, v32, v33], s[32:39], s[68:71] dmask:0xc dim:SQ_RSRC_IMG_3D th:TH_LOAD_RT_NT
+// GFX13: image_sample v[29:30], [v31, v32, v33], s[32:39], s[68:71] dmask:0xc dim:SQ_RSRC_IMG_3D th:TH_LOAD_RT_NT ; encoding: [0x02,0x00,0x08,0xe7,0x1d,0x40,0x50,0x22,0x1f,0x20,0x21,0x00]
+
+image_sample v[29:30], [v31, v32, v33], s[32:39], s[68:71] dmask:0x3 dim:SQ_RSRC_IMG_3D th:TH_LOAD_NT_HT
+// GFX13: image_sample v[29:30], [v31, v32, v33], s[32:39], s[68:71] dmask:0x3 dim:SQ_RSRC_IMG_3D th:TH_LOAD_NT_HT ; encoding: [0x02,0x00,0xc8,0xe4,0x1d,0x40,0x60,0x22,0x1f,0x20,0x21,0x00]
+
+image_sample v[34:35], v37, s[36:43], s[64:67] dmask:0x3 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample v[34:35], v37, s[36:43], s[64:67] dmask:0x3 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0xc8,0xe4,0x22,0x48,0x00,0x20,0x25,0x00,0x00,0x00]
+
+image_sample v[34:36], v37, s[36:43], s[64:67] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
+// GFX13: image_sample v[34:36], v37, s[36:43], s[64:67] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe ; encoding: [0x08,0x00,0xc8,0xe4,0x22,0x48,0x00,0x20,0x25,0x00,0x00,0x00]
+
+image_sample v34, v37, s[36:43], s[64:67] dmask:0x3 dim:SQ_RSRC_IMG_1D d16
+// GFX13: image_sample v34, v37, s[36:43], s[64:67] dmask:0x3 dim:SQ_RSRC_IMG_1D d16 ; encoding: [0x20,0x00,0xc8,0xe4,0x22,0x48,0x00,0x20,0x25,0x00,0x00,0x00]
+
+image_sample v[34:35], v37, s[36:43], s[64:67] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe d16
+// GFX13: image_sample v[34:35], v37, s[36:43], s[64:67] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe d16 ; encoding: [0x28,0x00,0xc8,0xe4,0x22,0x48,0x00,0x20,0x25,0x00,0x00,0x00]
+
+image_sample v[34:35], v37, s[36:43], s[64:67] dmask:0x3 dim:SQ_RSRC_IMG_1D lwe
+// GFX13: image_sample v[34:35], v37, s[36:43], s[64:67] dmask:0x3 dim:SQ_RSRC_IMG_1D lwe ; encoding: [0x00,0x00,0xc8,0xe4,0x22,0x49,0x00,0x20,0x25,0x00,0x00,0x00]
+
+// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
+image_sample v[38:39], [v40, v41], s[40:47], s[60:63] dmask:0xc dim:SQ_RSRC_IMG_CUBE unorm th:TH_LOAD_HT scope:SCOPE_DEV r128 a16 tfe lwe d16
+// GFX13: image_sample v[38:39], [v40, v41], s[40:47], s[60:63] dmask:0xc dim:SQ_RSRC_IMG_CUBE unorm th:TH_LOAD_HT scope:SCOPE_DEV r128 a16 tfe lwe d16 ; encoding: [0x7b,0x20,0x08,0xe7,0x26,0x51,0x28,0x1e,0x28,0x29,0x00,0x00]
+
+image_sample_d v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_d v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x48,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_d v64, [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_d v64, [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x08,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d v[64:65], [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_d v[64:65], [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0xc8,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d v[64:65], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_d v[64:65], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x08,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_d v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x80,0xc8,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d v[64:67], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_d v[64:67], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0xc8,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_l v64, [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_l v64, [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x49,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_sample_l v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_l v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x09,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_l v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_l v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0xc9,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_l v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_l v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0x09,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_l v[64:66], [v32, v33, v34], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_l v[64:66], [v32, v33, v34], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x00,0xc9,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_l v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_l v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0xc9,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_b v64, [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_b v64, [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0x49,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_sample_b v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_b v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0x09,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_b v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_b v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x40,0xc9,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_b v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_b v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x40,0x09,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_b v[64:66], [v32, v33, v34], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_b v[64:66], [v32, v33, v34], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x40,0xc9,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_b v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_b v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x40,0xc9,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_lz v64, v32, s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_lz v64, v32, s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x49,0xe4,0x40,0x08,0x00,0x02,0x20,0x00,0x00,0x00]
+
+image_sample_lz v64, [v32, v33], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_lz v64, [v32, v33], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x09,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_sample_lz v[64:65], [v32, v33, v34], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_lz v[64:65], [v32, v33, v34], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0xc0,0xc9,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_lz v[64:65], [v32, v33, v34], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_lz v[64:65], [v32, v33, v34], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x09,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_lz v[64:66], [v32, v33], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_lz v[64:66], [v32, v33], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0xc0,0xc9,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_sample_lz v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_lz v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0xc9,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_c v64, [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_c v64, [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x4a,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_sample_c v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_c v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x0a,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_c v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_c v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0xca,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_c v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0x0a,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c v[64:66], [v32, v33, v34], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_c v[64:66], [v32, v33, v34], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x00,0xca,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_c v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_c v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0xca,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_c_d v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x4a,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d v64, [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_c_d v64, [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x0a,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d v[64:65], [v32, v33, v34, v[35:41]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_c_d v[64:65], [v32, v33, v34, v[35:41]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0xca,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d v[64:65], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_c_d v[64:65], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x0a,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_c_d v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x80,0xca,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d v[64:67], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_c_d v[64:67], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0xca,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_l v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_c_l v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x4b,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_c_l v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_c_l v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x0b,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_l v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_c_l v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0xcb,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_l v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_c_l v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0x0b,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_l v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_c_l v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x00,0xcb,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_l v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_c_l v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0xcb,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_c_b v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0x4b,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_c_b v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_c_b v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0x0b,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_c_b v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x40,0xcb,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_c_b v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x40,0x0b,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_c_b v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x40,0xcb,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_c_b v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x40,0xcb,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_lz v64, [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_c_lz v64, [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x4b,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_sample_c_lz v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_c_lz v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x0b,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_c_lz v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_c_lz v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0xc0,0xcb,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_lz v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_c_lz v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x0b,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_lz v[64:66], [v32, v33, v34], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_c_lz v[64:66], [v32, v33, v34], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0xc0,0xcb,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_c_lz v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_c_lz v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0xcb,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_o v64, [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_o v64, [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x4c,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_sample_o v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_o v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x0c,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_o v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_o v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0xcc,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_o v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_o v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0x0c,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_o v[64:66], [v32, v33, v34], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_o v[64:66], [v32, v33, v34], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x00,0xcc,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_o v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_o v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0xcc,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_o v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_d_o v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x4c,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_o v64, [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_d_o v64, [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x0c,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_o v[64:65], [v32, v33, v34, v[35:41]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_d_o v[64:65], [v32, v33, v34, v[35:41]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0xcc,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_o v[64:65], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_d_o v[64:65], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x0c,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_o v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_d_o v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x80,0xcc,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_o v[64:67], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_d_o v[64:67], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0xcc,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_l_o v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_l_o v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x4d,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_l_o v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_l_o v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x0d,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_l_o v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_l_o v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0xcd,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_l_o v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_l_o v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0x0d,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_l_o v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_l_o v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x00,0xcd,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_l_o v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_l_o v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0xcd,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_b_o v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_b_o v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0x4d,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_b_o v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_b_o v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0x0d,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_b_o v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_b_o v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x40,0xcd,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_b_o v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_b_o v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x40,0x0d,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_b_o v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_b_o v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x40,0xcd,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_b_o v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_b_o v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x40,0xcd,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_lz_o v64, [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_lz_o v64, [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x4d,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_sample_lz_o v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_lz_o v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x0d,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_lz_o v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_lz_o v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0xc0,0xcd,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_lz_o v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_lz_o v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x0d,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_lz_o v[64:66], [v32, v33, v34], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_lz_o v[64:66], [v32, v33, v34], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0xc0,0xcd,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_lz_o v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_lz_o v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0xcd,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_o v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_c_o v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x4e,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_c_o v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_c_o v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x0e,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_o v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_c_o v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0xce,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_o v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_c_o v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0x0e,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_o v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_c_o v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x00,0xce,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_o v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_c_o v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0xce,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_o v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_c_d_o v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x4e,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_o v64, [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_c_d_o v64, [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x0e,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_o v[64:65], [v32, v33, v34, v[35:42]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_c_d_o v[64:65], [v32, v33, v34, v[35:42]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0xce,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_o v[64:65], [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_c_d_o v[64:65], [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x0e,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_o v[64:66], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_c_d_o v[64:66], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x80,0xce,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_o v[64:67], [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_c_d_o v[64:67], [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0xce,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_l_o v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_c_l_o v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x4f,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_l_o v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_c_l_o v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x0f,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_l_o v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_c_l_o v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0xcf,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_l_o v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_c_l_o v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0x0f,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_l_o v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_c_l_o v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x00,0xcf,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_l_o v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_c_l_o v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0xcf,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b_o v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_c_b_o v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0x4f,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b_o v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_c_b_o v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0x0f,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b_o v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_c_b_o v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x40,0xcf,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b_o v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_c_b_o v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x40,0x0f,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b_o v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_c_b_o v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x40,0xcf,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b_o v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_c_b_o v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x40,0xcf,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_lz_o v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_c_lz_o v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x4f,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_c_lz_o v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_c_lz_o v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x0f,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_lz_o v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_c_lz_o v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0xc0,0xcf,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_lz_o v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_c_lz_o v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x0f,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_lz_o v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_c_lz_o v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0xc0,0xcf,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_lz_o v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_c_lz_o v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0xcf,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4 v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_gather4 v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x50,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_gather4 v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_gather4 v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0x90,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4 v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_gather4 v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0x10,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4 v[64:67], v32, s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_gather4 v[64:67], v32, s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x00,0x50,0xe4,0x40,0x08,0x00,0x02,0x20,0x00,0x00,0x00]
+
+image_gather4 v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_gather4 v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x00,0x90,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_gather4 v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_gather4 v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x00,0x10,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_gather4 v[0:3], [v4, v5], s[0:7], s[100:103] dmask:0x8 dim:SQ_RSRC_IMG_2D unorm
+// GFX13: image_gather4 v[0:3], [v4, v5], s[0:7], s[100:103] dmask:0x8 dim:SQ_RSRC_IMG_2D unorm ; encoding: [0x01,0x20,0x10,0xe6,0x00,0x00,0x00,0x32,0x04,0x05,0x00,0x00]
+
+// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
+image_gather4 v[6:9], [v10, v11], s[8:15], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D r128
+// GFX13: image_gather4 v[6:9], [v10, v11], s[8:15], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D r128 ; encoding: [0x11,0x00,0x50,0xe4,0x06,0x10,0x00,0x30,0x0a,0x0b,0x00,0x00]
+
+image_gather4 v[12:15], [v16, v17], s[16:23], s[92:95] dmask:0x2 dim:SQ_RSRC_IMG_2D scope:SCOPE_CU
+// GFX13: image_gather4 v[12:15], [v16, v17], s[16:23], s[92:95] dmask:0x2 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x90,0xe4,0x0c,0x20,0x00,0x2e,0x10,0x11,0x00,0x00]
+
+image_gather4 v[12:15], [v16, v17], s[16:23], s[92:95] dmask:0x2 dim:SQ_RSRC_IMG_2D scope:SCOPE_SE
+// GFX13: image_gather4 v[12:15], [v16, v17], s[16:23], s[92:95] dmask:0x2 dim:SQ_RSRC_IMG_2D scope:SCOPE_SE ; encoding: [0x01,0x00,0x90,0xe4,0x0c,0x20,0x04,0x2e,0x10,0x11,0x00,0x00]
+
+image_gather4 v[12:15], [v16, v17], s[16:23], s[92:95] dmask:0x2 dim:SQ_RSRC_IMG_2D scope:SCOPE_DEV
+// GFX13: image_gather4 v[12:15], [v16, v17], s[16:23], s[92:95] dmask:0x2 dim:SQ_RSRC_IMG_2D scope:SCOPE_DEV ; encoding: [0x01,0x00,0x90,0xe4,0x0c,0x20,0x08,0x2e,0x10,0x11,0x00,0x00]
+
+image_gather4 v[12:15], [v16, v17], s[16:23], s[92:95] dmask:0x2 dim:SQ_RSRC_IMG_2D scope:SCOPE_SYS
+// GFX13: image_gather4 v[12:15], [v16, v17], s[16:23], s[92:95] dmask:0x2 dim:SQ_RSRC_IMG_2D scope:SCOPE_SYS ; encoding: [0x01,0x00,0x90,0xe4,0x0c,0x20,0x0c,0x2e,0x10,0x11,0x00,0x00]
+
+image_gather4 v[18:21], [v22, v23], s[24:31], s[88:91] dmask:0x4 dim:SQ_RSRC_IMG_2D th:TH_LOAD_RT
+// GFX13: image_gather4 v[18:21], [v22, v23], s[24:31], s[88:91] dmask:0x4 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x10,0xe5,0x12,0x30,0x00,0x2c,0x16,0x17,0x00,0x00]
+
+image_gather4 v[18:21], [v22, v23], s[24:31], s[88:91] dmask:0x4 dim:SQ_RSRC_IMG_2D th:TH_LOAD_NT
+// GFX13: image_gather4 v[18:21], [v22, v23], s[24:31], s[88:91] dmask:0x4 dim:SQ_RSRC_IMG_2D th:TH_LOAD_NT ; encoding: [0x01,0x00,0x10,0xe5,0x12,0x30,0x10,0x2c,0x16,0x17,0x00,0x00]
+
+image_gather4 v[18:21], [v22, v23], s[24:31], s[88:91] dmask:0x4 dim:SQ_RSRC_IMG_2D th:TH_LOAD_HT
+// GFX13: image_gather4 v[18:21], [v22, v23], s[24:31], s[88:91] dmask:0x4 dim:SQ_RSRC_IMG_2D th:TH_LOAD_HT ; encoding: [0x01,0x00,0x10,0xe5,0x12,0x30,0x20,0x2c,0x16,0x17,0x00,0x00]
+
+image_gather4 v[18:21], [v22, v23], s[24:31], s[88:91] dmask:0x4 dim:SQ_RSRC_IMG_2D th:TH_LOAD_LU
+// GFX13: image_gather4 v[18:21], [v22, v23], s[24:31], s[88:91] dmask:0x4 dim:SQ_RSRC_IMG_2D th:TH_LOAD_LU ; encoding: [0x01,0x00,0x10,0xe5,0x12,0x30,0x30,0x2c,0x16,0x17,0x00,0x00]
+
+image_gather4 v[18:21], [v22, v23], s[24:31], s[88:91] dmask:0x4 dim:SQ_RSRC_IMG_2D th:TH_LOAD_NT_RT
+// GFX13: image_gather4 v[18:21], [v22, v23], s[24:31], s[88:91] dmask:0x4 dim:SQ_RSRC_IMG_2D th:TH_LOAD_NT_RT ; encoding: [0x01,0x00,0x10,0xe5,0x12,0x30,0x40,0x2c,0x16,0x17,0x00,0x00]
+
+image_gather4 v[18:21], [v22, v23], s[24:31], s[88:91] dmask:0x4 dim:SQ_RSRC_IMG_2D th:TH_LOAD_RT_NT
+// GFX13: image_gather4 v[18:21], [v22, v23], s[24:31], s[88:91] dmask:0x4 dim:SQ_RSRC_IMG_2D th:TH_LOAD_RT_NT ; encoding: [0x01,0x00,0x10,0xe5,0x12,0x30,0x50,0x2c,0x16,0x17,0x00,0x00]
+
+image_gather4 v[18:21], [v22, v23], s[24:31], s[88:91] dmask:0x4 dim:SQ_RSRC_IMG_2D th:TH_LOAD_NT_HT
+// GFX13: image_gather4 v[18:21], [v22, v23], s[24:31], s[88:91] dmask:0x4 dim:SQ_RSRC_IMG_2D th:TH_LOAD_NT_HT ; encoding: [0x01,0x00,0x10,0xe5,0x12,0x30,0x60,0x2c,0x16,0x17,0x00,0x00]
+
+image_gather4 v[28:31], [v33, v34], s[40:47], s[80:83] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_gather4 v[28:31], [v33, v34], s[40:47], s[80:83] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x50,0xe4,0x1c,0x50,0x00,0x28,0x21,0x22,0x00,0x00]
+
+image_gather4 v[28:29], [v33, v34], s[40:47], s[80:83] dmask:0x1 dim:SQ_RSRC_IMG_2D d16
+// GFX13: image_gather4 v[28:29], [v33, v34], s[40:47], s[80:83] dmask:0x1 dim:SQ_RSRC_IMG_2D d16 ; encoding: [0x21,0x00,0x50,0xe4,0x1c,0x50,0x00,0x28,0x21,0x22,0x00,0x00]
+
+image_gather4 v[35:38], [v39, v40], s[48:55], s[76:79] dmask:0x2 dim:SQ_RSRC_IMG_2D lwe
+// GFX13: image_gather4 v[35:38], [v39, v40], s[48:55], s[76:79] dmask:0x2 dim:SQ_RSRC_IMG_2D lwe ; encoding: [0x01,0x00,0x90,0xe4,0x23,0x61,0x00,0x26,0x27,0x28,0x00,0x00]
+
+image_gather4_l v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_gather4_l v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x51,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_l v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_gather4_l v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0x91,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_l v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_gather4_l v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0x11,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_l v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_gather4_l v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x00,0x51,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_gather4_l v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_gather4_l v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x00,0x91,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_gather4_l v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_gather4_l v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x00,0x11,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_gather4_b v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_gather4_b v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0x51,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_b v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_gather4_b v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x40,0x91,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_b v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_gather4_b v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x40,0x11,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_b v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_gather4_b v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x40,0x51,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_gather4_b v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_gather4_b v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x40,0x91,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_b v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_gather4_b v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x40,0x11,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_lz v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_gather4_lz v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x51,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_gather4_lz v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_gather4_lz v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x91,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_lz v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_gather4_lz v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0x11,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_lz v[64:67], v32, s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_gather4_lz v[64:67], v32, s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0xc0,0x51,0xe4,0x40,0x08,0x00,0x02,0x20,0x00,0x00,0x00]
+
+image_gather4_lz v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_gather4_lz v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0xc0,0x91,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_gather4_lz v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_gather4_lz v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0xc0,0x11,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_gather4_c v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_gather4_c v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x52,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_c v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_gather4_c v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0x92,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_gather4_c v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0x12,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_gather4_c v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x00,0x52,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_gather4_c v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_gather4_c v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x00,0x92,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_c v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_gather4_c v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x00,0x12,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_c_lz v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_gather4_c_lz v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x53,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_c_lz v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_gather4_c_lz v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x93,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_lz v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_gather4_c_lz v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0x13,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_lz v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_gather4_c_lz v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0xc0,0x53,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_gather4_c_lz v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_gather4_c_lz v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0xc0,0x93,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_c_lz v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_gather4_c_lz v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0xc0,0x13,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_o v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_gather4_o v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x54,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_o v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_gather4_o v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0x94,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_o v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_gather4_o v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0x14,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_o v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_gather4_o v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x00,0x54,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_gather4_o v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_gather4_o v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x00,0x94,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_o v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_gather4_o v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x00,0x14,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_lz_o v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_gather4_lz_o v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x55,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_lz_o v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_gather4_lz_o v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x95,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_lz_o v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_gather4_lz_o v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0x15,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_lz_o v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_gather4_lz_o v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0xc0,0x55,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_gather4_lz_o v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_gather4_lz_o v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0xc0,0x95,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_lz_o v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_gather4_lz_o v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0xc0,0x15,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_c_lz_o v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_gather4_c_lz_o v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x57,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_lz_o v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_gather4_c_lz_o v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x97,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_lz_o v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_gather4_c_lz_o v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0x17,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_lz_o v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_gather4_c_lz_o v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0xc0,0x57,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_c_lz_o v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_gather4_c_lz_o v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0xc0,0x97,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_lz_o v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_gather4_c_lz_o v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0xc0,0x17,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_get_lod v64, v32, s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_get_lod v64, v32, s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x58,0xe4,0x40,0x08,0x00,0x32,0x20,0x00,0x00,0x00]
+
+image_get_lod v64, [v32, v33], s[4:11], s[100:103] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_get_lod v64, [v32, v33], s[4:11], s[100:103] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x18,0xe6,0x40,0x08,0x00,0x32,0x20,0x21,0x00,0x00]
+
+image_get_lod v[64:65], [v32, v33, v34], s[4:11], s[100:103] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_get_lod v[64:65], [v32, v33, v34], s[4:11], s[100:103] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0xd8,0xe4,0x40,0x08,0x00,0x32,0x20,0x21,0x22,0x00]
+
+image_get_lod v[64:65], [v32, v33, v34], s[4:11], s[100:103] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_get_lod v[64:65], [v32, v33, v34], s[4:11], s[100:103] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0x18,0xe7,0x40,0x08,0x00,0x32,0x20,0x21,0x22,0x00]
+
+image_get_lod v[64:66], [v32, v33], s[4:11], s[100:103] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_get_lod v[64:66], [v32, v33], s[4:11], s[100:103] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x00,0xd8,0xe6,0x40,0x08,0x00,0x32,0x20,0x21,0x00,0x00]
+
+image_sample_d_g16 v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_d_g16 v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x68,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_d_g16 v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_d_g16 v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x28,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_g16 v[64:65], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_d_g16 v[64:65], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0xe8,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_g16 v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_d_g16 v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x28,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_g16 v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_d_g16 v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x80,0xe8,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_g16 v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_d_g16 v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0xe8,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_g16 v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_c_d_g16 v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x6a,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_g16 v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_c_d_g16 v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x2a,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_g16 v[64:65], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_c_d_g16 v[64:65], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0xea,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_g16 v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_c_d_g16 v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x2a,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_g16 v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_c_d_g16 v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x80,0xea,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_g16 v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_c_d_g16 v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0xea,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_o_g16 v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_d_o_g16 v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x6c,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_o_g16 v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_d_o_g16 v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x2c,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_o_g16 v[64:65], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_d_o_g16 v[64:65], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0xec,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_o_g16 v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_d_o_g16 v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x2c,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_o_g16 v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_d_o_g16 v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x80,0xec,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_o_g16 v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_d_o_g16 v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0xec,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_o_g16 v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_c_d_o_g16 v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x6e,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_o_g16 v64, [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_c_d_o_g16 v64, [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x2e,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_o_g16 v[64:65], [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_c_d_o_g16 v[64:65], [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0xee,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_o_g16 v[64:65], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_c_d_o_g16 v[64:65], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x2e,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_o_g16 v[64:66], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_c_d_o_g16 v[64:66], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x80,0xee,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_o_g16 v[64:67], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_c_d_o_g16 v[64:67], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0xee,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_o_g16 v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D a16
+// GFX13: image_sample_c_d_o_g16 v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x80,0x6e,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_o_g16 v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_sample_c_d_o_g16 v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x80,0x2e,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_o_g16 v[64:65], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D a16
+// GFX13: image_sample_c_d_o_g16 v[64:65], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D a16 ; encoding: [0x42,0x80,0xee,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_o_g16 v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_sample_c_d_o_g16 v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x80,0x2e,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_o_g16 v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY a16
+// GFX13: image_sample_c_d_o_g16 v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY a16 ; encoding: [0x44,0x80,0xee,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_o_g16 v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_sample_c_d_o_g16 v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x80,0xee,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_cl v64, [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_cl v64, [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0x48,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_sample_cl v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_cl v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0x08,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_cl v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_cl v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x40,0xc8,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_cl v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_cl v[64:65], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x40,0x08,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_cl v[64:66], [v32, v33, v34], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_cl v[64:66], [v32, v33, v34], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x40,0xc8,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_cl v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_cl v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x40,0xc8,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_d_cl v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x48,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl v64, [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_d_cl v64, [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x08,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl v[64:65], [v32, v33, v34, v[35:41]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_d_cl v[64:65], [v32, v33, v34, v[35:41]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0xc0,0xc8,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl v[64:65], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_d_cl v[64:65], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x08,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_d_cl v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0xc0,0xc8,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl v[64:67], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_d_cl v[64:67], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0xc8,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_b_cl v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_b_cl v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x49,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_b_cl v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_b_cl v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x09,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_b_cl v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_b_cl v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0xc9,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_b_cl v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_b_cl v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x09,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_b_cl v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_b_cl v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x80,0xc9,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_b_cl v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_b_cl v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0xc9,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_cl v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_c_cl v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0x4a,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_c_cl v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_c_cl v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0x0a,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_cl v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_c_cl v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x40,0xca,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_cl v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_c_cl v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x40,0x0a,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_cl v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_c_cl v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x40,0xca,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_cl v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_c_cl v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x40,0xca,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_c_d_cl v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x4a,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl v64, [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_c_d_cl v64, [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x0a,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl v[64:65], [v32, v33, v34, v[35:42]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_c_d_cl v[64:65], [v32, v33, v34, v[35:42]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0xc0,0xca,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl v[64:65], [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_c_d_cl v[64:65], [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x0a,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl v[64:66], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_c_d_cl v[64:66], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0xc0,0xca,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl v[64:67], [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_c_d_cl v[64:67], [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0xca,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b_cl v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_c_b_cl v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x4b,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b_cl v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_c_b_cl v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x0b,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b_cl v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_c_b_cl v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0xcb,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b_cl v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_c_b_cl v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x0b,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b_cl v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_c_b_cl v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x80,0xcb,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b_cl v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_c_b_cl v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0xcb,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_cl_o v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_cl_o v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0x4c,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_sample_cl_o v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_cl_o v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0x0c,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_cl_o v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_cl_o v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x40,0xcc,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_cl_o v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_cl_o v[64:65], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x40,0x0c,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_cl_o v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_cl_o v[64:66], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x40,0xcc,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_cl_o v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_cl_o v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x40,0xcc,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl_o v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_d_cl_o v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x4c,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl_o v64, [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_d_cl_o v64, [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x0c,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl_o v[64:65], [v32, v33, v34, v[35:42]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_d_cl_o v[64:65], [v32, v33, v34, v[35:42]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0xc0,0xcc,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl_o v[64:65], [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_d_cl_o v[64:65], [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x0c,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl_o v[64:66], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_d_cl_o v[64:66], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0xc0,0xcc,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl_o v[64:67], [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_d_cl_o v[64:67], [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0xcc,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_b_cl_o v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_b_cl_o v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x4d,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_b_cl_o v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_b_cl_o v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x0d,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_b_cl_o v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_b_cl_o v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0xcd,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_b_cl_o v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_b_cl_o v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x0d,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_b_cl_o v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_b_cl_o v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x80,0xcd,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_b_cl_o v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_b_cl_o v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0xcd,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_cl_o v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_c_cl_o v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0x4e,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_cl_o v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_c_cl_o v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0x0e,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_cl_o v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_c_cl_o v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x40,0xce,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_cl_o v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_c_cl_o v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x40,0x0e,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_cl_o v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_c_cl_o v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x40,0xce,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_cl_o v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_c_cl_o v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x40,0xce,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl_o v64, [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_c_d_cl_o v64, [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x4e,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl_o v64, [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_c_d_cl_o v64, [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x0e,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl_o v[64:65], [v32, v33, v34, v[35:43]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_c_d_cl_o v[64:65], [v32, v33, v34, v[35:43]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0xc0,0xce,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl_o v[64:65], [v32, v33, v34, v[35:41]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_c_d_cl_o v[64:65], [v32, v33, v34, v[35:41]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x0e,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl_o v[64:66], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_c_d_cl_o v[64:66], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0xc0,0xce,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl_o v[64:67], [v32, v33, v34, v[35:41]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_c_d_cl_o v[64:67], [v32, v33, v34, v[35:41]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0xce,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b_cl_o v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_c_b_cl_o v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x4f,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b_cl_o v64, [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_c_b_cl_o v64, [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x0f,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b_cl_o v[64:65], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_c_b_cl_o v[64:65], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0xcf,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b_cl_o v[64:65], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_c_b_cl_o v[64:65], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x0f,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b_cl_o v[64:66], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_c_b_cl_o v[64:66], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0x80,0xcf,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_b_cl_o v[64:67], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_c_b_cl_o v[64:67], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0xcf,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl_g16 v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_c_d_cl_g16 v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x6a,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl_g16 v64, [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_c_d_cl_g16 v64, [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x2a,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl_g16 v[64:65], [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_c_d_cl_g16 v[64:65], [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0xc0,0xea,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl_g16 v[64:65], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_c_d_cl_g16 v[64:65], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x2a,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl_g16 v[64:66], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_c_d_cl_g16 v[64:66], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0xc0,0xea,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl_g16 v[64:67], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_c_d_cl_g16 v[64:67], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0xea,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl_o_g16 v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_d_cl_o_g16 v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x6c,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl_o_g16 v64, [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_d_cl_o_g16 v64, [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x2c,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl_o_g16 v[64:65], [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_d_cl_o_g16 v[64:65], [v32, v33, v34, v[35:40]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0xc0,0xec,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl_o_g16 v[64:65], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_d_cl_o_g16 v[64:65], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x2c,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl_o_g16 v[64:66], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_d_cl_o_g16 v[64:66], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0xc0,0xec,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl_o_g16 v[64:67], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_d_cl_o_g16 v[64:67], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0xec,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl_o_g16 v64, [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_c_d_cl_o_g16 v64, [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x6e,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl_o_g16 v64, [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_c_d_cl_o_g16 v64, [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x2e,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl_o_g16 v[64:65], [v32, v33, v34, v[35:41]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_c_d_cl_o_g16 v[64:65], [v32, v33, v34, v[35:41]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0xc0,0xee,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl_o_g16 v[64:65], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_c_d_cl_o_g16 v[64:65], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x2e,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl_o_g16 v[64:66], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_c_d_cl_o_g16 v[64:66], [v32, v33, v34, v[35:38]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0xc0,0xee,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_c_d_cl_o_g16 v[64:67], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_c_d_cl_o_g16 v[64:67], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0xee,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl_g16 v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX13: image_sample_d_cl_g16 v64, [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x68,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl_g16 v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D
+// GFX13: image_sample_d_cl_g16 v64, [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x28,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl_g16 v[64:65], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D
+// GFX13: image_sample_d_cl_g16 v[64:65], [v32, v33, v34, v[35:39]], s[4:11], s[4:7] dmask:0x3 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0xc0,0xe8,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl_g16 v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_sample_d_cl_g16 v[64:65], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xc dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0xc0,0x28,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl_g16 v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
+// GFX13: image_sample_d_cl_g16 v[64:66], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x04,0xc0,0xe8,0xe6,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_sample_d_cl_g16 v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_sample_d_cl_g16 v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0xc0,0xe8,0xe7,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_cl v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_gather4_cl v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0x50,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_cl v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_gather4_cl v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x40,0x90,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_cl v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_gather4_cl v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x40,0x10,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_cl v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_gather4_cl v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x40,0x50,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_gather4_cl v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_gather4_cl v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x40,0x90,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_gather4_cl v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_gather4_cl v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x40,0x10,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_gather4_b_cl v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_gather4_b_cl v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x51,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_b_cl v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_gather4_b_cl v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x91,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_b_cl v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_gather4_b_cl v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0x11,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_b_cl v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_gather4_b_cl v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x80,0x51,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_b_cl v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_gather4_b_cl v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x80,0x91,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_b_cl v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_gather4_b_cl v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x80,0x11,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_c_cl v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_gather4_c_cl v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0x52,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_cl v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_gather4_c_cl v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x40,0x92,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_cl v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_gather4_c_cl v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x40,0x12,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_cl v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_gather4_c_cl v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x40,0x52,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_c_cl v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_gather4_c_cl v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x40,0x92,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_c_cl v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_gather4_c_cl v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x40,0x12,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_c_l v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_gather4_c_l v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x53,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_l v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_gather4_c_l v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x00,0x93,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_l v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_gather4_c_l v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0x13,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_l v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_gather4_c_l v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x00,0x53,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_c_l v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_gather4_c_l v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x00,0x93,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_c_l v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_gather4_c_l v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x00,0x13,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_c_b v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_gather4_c_b v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0x53,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_b v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_gather4_c_b v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x40,0x93,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_b v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_gather4_c_b v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x40,0x13,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_b v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_gather4_c_b v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x40,0x53,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4_c_b v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_gather4_c_b v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x40,0x93,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_b v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_gather4_c_b v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x40,0x13,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_b_cl v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_gather4_c_b_cl v[64:67], [v32, v33, v34, v[35:36]], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x53,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_b_cl v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_gather4_c_b_cl v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x80,0x93,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_b_cl v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_gather4_c_b_cl v[64:67], [v32, v33, v34, v[35:37]], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x80,0x13,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_b_cl v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_gather4_c_b_cl v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x80,0x53,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_b_cl v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_gather4_c_b_cl v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x80,0x93,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4_c_b_cl v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_gather4_c_b_cl v[64:67], [v32, v33, v34, v35], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x80,0x13,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x23]
+
+image_gather4h v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX13: image_gather4h v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0x58,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_gather4h v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE
+// GFX13: image_gather4h v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x03,0x40,0x98,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4h v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+// GFX13: image_gather4h v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x40,0x18,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
+
+image_gather4h v[64:67], v32, s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D a16
+// GFX13: image_gather4h v[64:67], v32, s[4:11], s[4:7] dmask:0x8 dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x41,0x40,0x18,0xe6,0x40,0x08,0x00,0x02,0x20,0x00,0x00,0x00]
+
+image_gather4h v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16
+// GFX13: image_gather4h v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE a16 ; encoding: [0x43,0x40,0x98,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_gather4h v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+// GFX13: image_gather4h v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; encoding: [0x45,0x40,0x18,0xe5,0x40,0x08,0x00,0x02,0x20,0x21,0x00,0x00]
+
+image_msaa_load v[1:4], [v5, v6, v7], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA
+// GFX13: image_msaa_load v[1:4], [v5, v6, v7], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA ; encoding: [0x06,0x00,0x60,0xe4,0x01,0x10,0x00,0x00,0x05,0x06,0x07,0x00]
+
+image_msaa_load v[1:4], [v5, v6, v7], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm
+// GFX13: image_msaa_load v[1:4], [v5, v6, v7], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm ; encoding: [0x06,0x20,0x60,0xe4,0x01,0x10,0x00,0x00,0x05,0x06,0x07,0x00]
+
+image_msaa_load v[1:2], [v1, v2, v3], s[16:23] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm d16
+// GFX13: image_msaa_load v[1:2], [v1, v2, v3], s[16:23] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm d16 ; encoding: [0x26,0x20,0x60,0xe4,0x01,0x20,0x00,0x00,0x01,0x02,0x03,0x00]
+
+image_msaa_load v[1:4], [v1, v2], s[8:15] dmask:0x2 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
+// GFX13: image_msaa_load v[1:4], [v1, v2], s[8:15] dmask:0x2 dim:SQ_RSRC_IMG_2D_MSAA unorm a16 ; encoding: [0x46,0x20,0xa0,0xe4,0x01,0x10,0x00,0x00,0x01,0x02,0x00,0x00]
+
+image_msaa_load v[1:2], [v2, v1], s[8:15] dmask:0x2 dim:SQ_RSRC_IMG_2D_MSAA unorm a16 d16
+// GFX13: image_msaa_load v[1:2], [v2, v1], s[8:15] dmask:0x2 dim:SQ_RSRC_IMG_2D_MSAA unorm a16 d16 ; encoding: [0x66,0x20,0xa0,0xe4,0x01,0x10,0x00,0x00,0x02,0x01,0x00,0x00]
+
+image_msaa_load v[1:4], [v8, v6, v5, v7], s[8:15] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm
+// GFX13: image_msaa_load v[1:4], [v8, v6, v5, v7], s[8:15] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm ; encoding: [0x07,0x20,0x20,0xe5,0x01,0x10,0x00,0x00,0x08,0x06,0x05,0x07]
+
+image_msaa_load v[1:2], [v204, v11, v14, v19], s[96:103] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm d16
+// GFX13: image_msaa_load v[1:2], [v204, v11, v14, v19], s[96:103] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm d16 ; encoding: [0x27,0x20,0x20,0xe5,0x01,0xc0,0x00,0x00,0xcc,0x0b,0x0e,0x13]
+
+image_msaa_load v[1:4], [v8, v6], s[8:15] dmask:0x8 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16
+// GFX13: image_msaa_load v[1:4], [v8, v6], s[8:15] dmask:0x8 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; encoding: [0x47,0x20,0x20,0xe6,0x01,0x10,0x00,0x00,0x08,0x06,0x00,0x00]
+
+image_msaa_load v[1:2], [v5, v7], s[8:15] dmask:0x8 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 d16
+// GFX13: image_msaa_load v[1:2], [v5, v7], s[8:15] dmask:0x8 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 d16 ; encoding: [0x67,0x20,0x20,0xe6,0x01,0x10,0x00,0x00,0x05,0x07,0x00,0x00]
+
+image_msaa_load v[0:4], [v5, v7, v11, v55], s[8:15] dmask:0x8 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe
+// GFX13: image_msaa_load v[0:4], [v5, v7, v11, v55], s[8:15] dmask:0x8 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe ; encoding: [0x0f,0x20,0x20,0xe6,0x00,0x10,0x00,0x00,0x05,0x07,0x0b,0x37]
+
+image_msaa_load v[1:4], [v5, v6, v7, v8], s[8:15] dmask:0x8 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY lwe
+// GFX13: image_msaa_load v[1:4], [v5, v6, v7, v8], s[8:15] dmask:0x8 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY lwe ; encoding: [0x07,0x00,0x20,0xe6,0x01,0x11,0x00,0x00,0x05,0x06,0x07,0x08]
+
+image_msaa_load v[0:2], [v5, v7, v11, v55], s[8:15] dmask:0x8 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe d16
+// GFX13: image_msaa_load v[0:2], [v5, v7, v11, v55], s[8:15] dmask:0x8 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe d16 ; encoding: [0x2f,0x20,0x20,0xe6,0x00,0x10,0x00,0x00,0x05,0x07,0x0b,0x37]
+
+image_msaa_load v[1:4], [v5, v6, v7], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm th:TH_LOAD_NT
+// GFX13: image_msaa_load v[1:4], [v5, v6, v7], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm th:TH_LOAD_NT ; encoding: [0x06,0x20,0x60,0xe4,0x01,0x10,0x10,0x00,0x05,0x06,0x07,0x00]
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