[llvm] 4e2ad71 - [NFC] Format two AMDGPU files (#197672)
via llvm-commits
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Thu May 14 06:31:38 PDT 2026
Author: Shilei Tian
Date: 2026-05-14T13:31:33Z
New Revision: 4e2ad71ace933e5c5f860ad389d024dddecaab44
URL: https://github.com/llvm/llvm-project/commit/4e2ad71ace933e5c5f860ad389d024dddecaab44
DIFF: https://github.com/llvm/llvm-project/commit/4e2ad71ace933e5c5f860ad389d024dddecaab44.diff
LOG: [NFC] Format two AMDGPU files (#197672)
- `llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp`
- `llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp`
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index ad61d8d084c7b..6e8ad3f9f1a24 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -1507,14 +1507,22 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
static unsigned getRsrcReg(CallingConv::ID CallConv) {
switch (CallConv) {
- default: [[fallthrough]];
- case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
- case CallingConv::AMDGPU_LS: return R_00B528_SPI_SHADER_PGM_RSRC1_LS;
- case CallingConv::AMDGPU_HS: return R_00B428_SPI_SHADER_PGM_RSRC1_HS;
- case CallingConv::AMDGPU_ES: return R_00B328_SPI_SHADER_PGM_RSRC1_ES;
- case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
- case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
- case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
+ default:
+ [[fallthrough]];
+ case CallingConv::AMDGPU_CS:
+ return R_00B848_COMPUTE_PGM_RSRC1;
+ case CallingConv::AMDGPU_LS:
+ return R_00B528_SPI_SHADER_PGM_RSRC1_LS;
+ case CallingConv::AMDGPU_HS:
+ return R_00B428_SPI_SHADER_PGM_RSRC1_HS;
+ case CallingConv::AMDGPU_ES:
+ return R_00B328_SPI_SHADER_PGM_RSRC1_ES;
+ case CallingConv::AMDGPU_GS:
+ return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
+ case CallingConv::AMDGPU_VS:
+ return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
+ case CallingConv::AMDGPU_PS:
+ return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
}
}
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
index 53c21837a11dd..d6509fdd2b21a 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
@@ -237,7 +237,7 @@ unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) {
AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S,
formatted_raw_ostream &OS)
- : AMDGPUTargetStreamer(S), OS(OS) { }
+ : AMDGPUTargetStreamer(S), OS(OS) {}
// A hook for emitting stuff at the end.
// We use it for emitting the accumulated PAL metadata as directives.
@@ -276,10 +276,11 @@ void AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(AMDGPUMCKernelCodeT &Header) {
void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName,
unsigned Type) {
switch (Type) {
- default: llvm_unreachable("Invalid AMDGPU symbol type");
- case ELF::STT_AMDGPU_HSA_KERNEL:
- OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ;
- break;
+ default:
+ llvm_unreachable("Invalid AMDGPU symbol type");
+ case ELF::STT_AMDGPU_HSA_KERNEL:
+ OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n';
+ break;
}
}
@@ -337,8 +338,8 @@ bool AMDGPUTargetAsmStreamer::EmitISAVersion() {
return true;
}
-bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(
- msgpack::Document &HSAMetadataDoc, bool Strict) {
+bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc,
+ bool Strict) {
HSAMD::V3::MetadataVerifier Verifier(Strict);
if (!Verifier.verify(HSAMetadataDoc.getRoot()))
return false;
@@ -548,7 +549,8 @@ void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
case AMDGPU::AMDHSA_COV4:
case AMDGPU::AMDHSA_COV5:
if (getTargetID()->isXnackSupported())
- OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny() << '\n';
+ OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny()
+ << '\n';
break;
}
@@ -815,13 +817,13 @@ void AMDGPUTargetELFStreamer::EmitNote(
S.pushSection();
S.switchSection(
Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags));
- S.emitInt32(NameSZ); // namesz
- S.emitValue(DescSZ, 4); // descz
- S.emitInt32(NoteType); // type
- S.emitBytes(Name); // name
- S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
- EmitDesc(S); // desc
- S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
+ S.emitInt32(NameSZ); // namesz
+ S.emitValue(DescSZ, 4); // descz
+ S.emitInt32(NoteType); // type
+ S.emitBytes(Name); // name
+ S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
+ EmitDesc(S); // desc
+ S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
S.popSection();
}
@@ -1027,8 +1029,8 @@ bool AMDGPUTargetELFStreamer::EmitISAVersion() {
auto *DescBegin = Context.createTempSymbol();
auto *DescEnd = Context.createTempSymbol();
auto *DescSZ = MCBinaryExpr::createSub(
- MCSymbolRefExpr::create(DescEnd, Context),
- MCSymbolRefExpr::create(DescBegin, Context), Context);
+ MCSymbolRefExpr::create(DescEnd, Context),
+ MCSymbolRefExpr::create(DescBegin, Context), Context);
EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_ISA_NAME,
[&](MCELFStreamer &OS) {
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