[clang] [compiler-rt] [llvm] [X86] Hygon Processors Initial enablement (PR #187622)

[Xiaomeng Zhang via llvm-commits]

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+//=- X86ScheduleC864GM4.td - X86 C86-4G-M4 Scheduling --------*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the machine model for C86-4G-M4 to support instruction
+// scheduling and other instruction cost heuristics.
+//
+//===----------------------------------------------------------------------===//
+
+def C864GM4Model : SchedMachineModel {
+  let IssueWidth = 4;
+  let MicroOpBufferSize = 224;
+  // The maximum dispatch is 6 ops/cycle, and a mispredict cost is 16 cycle from
+  // the op-cache, so the loop buffer is limited to 6*16 = 96.
+  let LoopMicroOpBufferSize = 96;
+  // The common case of branch misprediction penalty is 16 cycles.
+  let MispredictPenalty = 16;
+
+  let LoadLatency = 4;
+  int VecLoadLatency = 7;
+  int StoreLatency = 1;
+  let HighLatency = 25;
+
+  let PostRAScheduler = 1;
+
+  let CompleteModel = 1;
+}
+
+let SchedModel = C864GM4Model in {
+
+//===----------------------------------------------------------------------===//
+// Integer Execution Unit
+//===----------------------------------------------------------------------===//
+
+// The C864GM4 has 4 ALUs.
+def 4GM4ALU0 : ProcResource<1>;
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zhangxiaomeng-hygon wrote:

OK, I will change it.

https://github.com/llvm/llvm-project/pull/187622