[llvm] [AArch64][GlobalISel] Fast-path common G_CONSTANT/G_BRCOND/G_FRAME_INDEX regbank mappings (PR #197383)

[Cullen Rhodes via llvm-commits]

https://github.com/c-rhodes updated https://github.com/llvm/llvm-project/pull/197383

>From 756c285a551cc02259bea3a72fc14174128dd600 Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Tue, 12 May 2026 10:54:37 +0000
Subject: [PATCH 1/2] [AArch64][GlobalISel] Fast-path common
 G_CONSTANT/G_BRCOND/G_FRAME_INDEX regbank mappings

Returning the default register-bank mapping directly for these opcodes
is a -0.17% compile-time improvement on aarch64-O0-g.

https://llvm-compile-time-tracker.com/compare.php?from=b4aa4d4dcb6f1c8a00d1d1e53d2b353c97ec98b7&to=0779891fc6bf6a01e4f14d3f359e212c6ec52c0d&stat=instructions%3Au

Assisted-by: codex
---
 .../AArch64/GISel/AArch64RegisterBankInfo.cpp | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index d65ffb1c36814..c0a34292abd73 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -969,6 +969,26 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
         // We only care about the mapping of the destination for COPY.
         /*NumOperands*/ Opc == TargetOpcode::G_BITCAST ? 2 : 1);
   }
+  case TargetOpcode::G_CONSTANT: {
+    LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
+    TypeSize Size = DstTy.getSizeInBits();
+    if (!(DstTy.isPointer() || (DstTy.isScalar() && Size >= 32 && Size <= 64)))
+      break;
+    // Scalar constants materialize in GPRs.
+    [[fallthrough]];
+  }
+  case TargetOpcode::G_BRCOND:
+  case TargetOpcode::G_FRAME_INDEX: {
+    // Operand 0 is the only banked operand and is mapped to GPR.
+    return getInstructionMapping(
+        DefaultMappingID, /*Cost=*/1,
+        getOperandsMapping(
+            {getValueMapping(
+                 PMI_FirstGPR,
+                 MRI.getType(MI.getOperand(0).getReg()).getSizeInBits()),
+             nullptr}),
+        /*NumOperands=*/2);
+  }
   default:
     break;
   }

>From 2072fa7052d521b1e68b4fae8ffd255a57ebe66b Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Wed, 13 May 2026 08:02:39 +0000
Subject: [PATCH 2/2] address comments

---
 llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index c0a34292abd73..e814316b0f2ed 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -972,7 +972,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case TargetOpcode::G_CONSTANT: {
     LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
     TypeSize Size = DstTy.getSizeInBits();
-    if (!(DstTy.isPointer() || (DstTy.isScalar() && Size >= 32 && Size <= 64)))
+    if (!DstTy.isPointer() && (!DstTy.isScalar() || Size < 32 || Size > 64))
       break;
     // Scalar constants materialize in GPRs.
     [[fallthrough]];