[llvm] [AMDGPU][True16] true16 impl for v_ashr_pk_u/i8_i32 (PR #197167)
Mariusz Sikora via llvm-commits
llvm-commits at lists.llvm.org
Wed May 13 04:02:26 PDT 2026
https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/197167
>From 869019069b3b9ca21ade023afc83a01a54538239 Mon Sep 17 00:00:00 2001
From: Guo Chen <guochen2 at amd.com>
Date: Wed, 29 Apr 2026 11:10:55 -0400
Subject: [PATCH 1/4] [AMDGPU][True16] true16 impl for v_ashr_pk_u/i8_i32
---
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 6 +
llvm/lib/Target/AMDGPU/VOP3Instructions.td | 33 ++--
llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll | 147 ++++++++++++++----
llvm/test/MC/AMDGPU/gfx1250_asm_vop3.s | 48 +++---
llvm/test/MC/AMDGPU/gfx13_asm_vop3.s | 48 +++---
llvm/test/MC/AMDGPU/gfx13_asm_vop3_dpp16.s | 40 +++--
llvm/test/MC/AMDGPU/gfx13_asm_vop3_dpp8.s | 16 +-
.../Disassembler/AMDGPU/gfx1250_dasm_vop3.txt | 36 +++--
.../AMDGPU/gfx1250_dasm_vop3_dpp16.txt | 24 ++-
.../AMDGPU/gfx1250_dasm_vop3_dpp8.txt | 12 +-
10 files changed, 276 insertions(+), 134 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 90b5f7b0b794b..9e8bee80b9f74 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -3566,6 +3566,12 @@ def getVOPDInfoFromComponentOpcodes : SearchIndex {
let Key = ["OpX", "OpY", "SubTgt", "VOPD3"];
}
+class true16HelperReg32FromSrc16<dag op, bit true16, bit ishi16 = 0> {
+ dag ret = !if(true16,!if(ishi16, (REG_SEQUENCE VGPR_32, (i16 (IMPLICIT_DEF)), lo16, op, hi16),
+ (REG_SEQUENCE VGPR_32, op, lo16, (i16 (IMPLICIT_DEF)), hi16)),
+ op);
+}
+
include "SIInstructions.td"
include "DSInstructions.td"
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index e78ecd1af9b45..0e4ff79f2ba83 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -2009,29 +2009,44 @@ let SubtargetPredicate = HasPseudoScalarTrans in {
let HasModifiers = 1 in
def ASHR_PK_I8_Profile : VOP3_Profile<VOP_I16_I32_I32_I32, VOP3_OPSEL_ONLY>;
+def ASHR_PK_I8_Profile_t16 : VOP3_Profile_True16<VOP_I16_I32_I32_I32, VOP3_OPSEL_ONLY>;
+def ASHR_PK_I8_Profile_fake16 : VOP3_Profile_Fake16<VOP_I16_I32_I32_I32, VOP3_OPSEL_ONLY>;
let SubtargetPredicate = HasAshrPkInsts, isReMaterializable = 1 in {
- defm V_ASHR_PK_I8_I32 : VOP3Inst<"v_ashr_pk_i8_i32", ASHR_PK_I8_Profile, int_amdgcn_ashr_pk_i8_i32>;
- defm V_ASHR_PK_U8_I32 : VOP3Inst<"v_ashr_pk_u8_i32", ASHR_PK_I8_Profile, int_amdgcn_ashr_pk_u8_i32>;
+ defm V_ASHR_PK_I8_I32: VOP3Inst_t16_with_profiles <"v_ashr_pk_i8_i32", ASHR_PK_I8_Profile,
+ ASHR_PK_I8_Profile_t16, ASHR_PK_I8_Profile_fake16,
+ int_amdgcn_ashr_pk_i8_i32>;
+ defm V_ASHR_PK_U8_I32: VOP3Inst_t16_with_profiles <"v_ashr_pk_u8_i32", ASHR_PK_I8_Profile,
+ ASHR_PK_I8_Profile_t16, ASHR_PK_I8_Profile_fake16,
+ int_amdgcn_ashr_pk_u8_i32>;
} // End SubtargetPredicate = HasAshrPkInsts, isReMaterializable = 1
-class AshrPkI8Pat<VOP3_Pseudo inst, int lo, int hi>: GCNPat<
+class AshrPkI8Pat<VOP3_Pseudo inst, int lo, int hi, bit true16 = 0>: GCNPat<
(i32 (or (i32 (shl (i32 (AMDGPUsmed3 (i32 (sra i32:$src1, i32:$src2)), (i32 lo), (i32 hi))), (i32 8))),
(i32 (and (i32 (AMDGPUsmed3 (i32 (sra i32:$src0, i32:$src2)), (i32 lo), (i32 hi))), (i32 255))))),
- (inst 0, VSrc_b32:$src0, 0, VSrc_b32:$src1, 0, VSrc_b32:$src2, 0 )
+ true16HelperReg32FromSrc16<(inst 0, VSrc_b32:$src0, 0, VSrc_b32:$src1, 0, VSrc_b32:$src2, 0 ), true16>.ret
>;
-class AshrPkU8Pat<VOP3_Pseudo inst, int lo, int hi>: GCNPat<
+class AshrPkU8Pat<VOP3_Pseudo inst, int lo, int hi, bit true16 = 0>: GCNPat<
(i32 (or (i32 (shl (i32 (AMDGPUsmed3 (i32 (sra i32:$src1, i32:$src2)), (i32 lo), (i32 hi))), (i32 8))),
(i32 (AMDGPUsmed3 (i32 (sra i32:$src0, i32:$src2)), (i32 lo), (i32 hi))))),
- (inst 0, VSrc_b32:$src0, 0, VSrc_b32:$src1, 0, VSrc_b32:$src2, 0 )
+ true16HelperReg32FromSrc16<(inst 0, VSrc_b32:$src0, 0, VSrc_b32:$src1, 0, VSrc_b32:$src2, 0 ), true16>.ret
>;
-let SubtargetPredicate = HasAshrPkInsts in {
+let SubtargetPredicate = HasAshrPkInsts, True16Predicate = NotHasTrue16BitInsts in {
def : AshrPkI8Pat<V_ASHR_PK_I8_I32_e64, -128, 127>;
def : AshrPkU8Pat<V_ASHR_PK_U8_I32_e64, 0, 255>;
}
+let SubtargetPredicate = HasAshrPkInsts, True16Predicate = UseFakeTrue16Insts in {
+ def : AshrPkI8Pat<V_ASHR_PK_I8_I32_fake16_e64, -128, 127>;
+ def : AshrPkU8Pat<V_ASHR_PK_U8_I32_fake16_e64, 0, 255>;
+}
+let SubtargetPredicate = HasAshrPkInsts, True16Predicate = UseRealTrue16Insts in {
+ def : AshrPkI8Pat<V_ASHR_PK_I8_I32_t16_e64, -128, 127, 1>;
+ def : AshrPkU8Pat<V_ASHR_PK_U8_I32_t16_e64, 0, 255, 1>;
+}
+
let SubtargetPredicate = isGFX13Plus in {
defm V_CVT_SCALEF32_PK32_BF6_F32 : VOP3Inst<"v_cvt_scalef32_pk32_bf6_f32", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V6I32_V32F32_F32>>;
defm V_CVT_SCALEF32_PK32_FP6_F32 : VOP3Inst<"v_cvt_scalef32_pk32_fp6_f32", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V6I32_V32F32_F32>>;
@@ -2391,8 +2406,8 @@ defm V_PERM_PK16_B4_U4 : VOP3Only_Real_Base_gfx1250_gfx13<0x23f, 0
defm V_PERM_PK16_B6_U4 : VOP3Only_Real_Base_gfx1250_gfx13<0x242, 0x349>;
defm V_PERM_PK16_B8_U4 : VOP3Only_Real_Base_gfx1250_gfx13<0x243, 0x34a>;
defm V_LSHL_ADD_U64 : VOP3Only_Realtriple_gfx1250_DPP8_gfx13<0x252>;
-defm V_ASHR_PK_I8_I32 : VOP3Only_Realtriple_gfx1250_gfx13<0x290, 0x290>;
-defm V_ASHR_PK_U8_I32 : VOP3Only_Realtriple_gfx1250_gfx13<0x291, 0x291>;
+defm V_ASHR_PK_I8_I32 : VOP3Only_Realtriple_t16_and_fake16_gfx1250_gfx13<0x290, 0x290>;
+defm V_ASHR_PK_U8_I32 : VOP3Only_Realtriple_t16_and_fake16_gfx1250_gfx13<0x291, 0x291>;
defm V_CVT_SCALE_PK8_F16_FP4 : VOP3Only_ScaleSel_Real_gfx1250_gfx13<0x29f, 0x2bd>;
defm V_CVT_SCALE_PK8_BF16_FP4 : VOP3Only_ScaleSel_Real_gfx1250_gfx13<0x2a0, 0x2ba>;
defm V_CVT_SCALE_PK8_F32_FP4 : VOP3Only_ScaleSel_Real_gfx1250_gfx13<0x2a1, 0x2c0>;
diff --git a/llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll b/llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll
index 1676859b2cc06..4d6ff1083492a 100644
--- a/llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll
@@ -1,6 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX950 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250 %s
+; RUN: llc -mtriple=amdgcn -mattr=+real-true16 -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mattr=+real-true16 -mcpu=gfx1310 < %s | FileCheck -check-prefixes=GFX1300-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1310 < %s | FileCheck -check-prefixes=GFX1300-FAKE16 %s
define amdgpu_kernel void @v_ashr_pk_i8_i32(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) #0 {
; GFX950-LABEL: v_ashr_pk_i8_i32:
; GFX950: ; %bb.0:
@@ -15,20 +18,63 @@ define amdgpu_kernel void @v_ashr_pk_i8_i32(ptr addrspace(1) %out, i32 %src0, i3
; GFX950-NEXT: global_store_short v0, v1, s[6:7]
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: v_ashr_pk_i8_i32:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
-; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_and_b32 s2, s2, 31
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_mov_b32_e32 v0, s2
-; GFX1250-NEXT: v_ashr_pk_i8_i32 v0, s0, s1, v0
-; GFX1250-NEXT: global_store_b16 v1, v0, s[6:7]
-; GFX1250-NEXT: s_endpgm
+; GFX1250-TRUE16-LABEL: v_ashr_pk_i8_i32:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-TRUE16-NEXT: s_clause 0x1
+; GFX1250-TRUE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
+; GFX1250-TRUE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: s_and_b32 s2, s2, 31
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1250-TRUE16-NEXT: v_ashr_pk_i8_i32 v0.l, s0, s1, v0
+; GFX1250-TRUE16-NEXT: global_store_b16 v1, v0, s[6:7]
+; GFX1250-TRUE16-NEXT: s_endpgm
+;
+; GFX1250-FAKE16-LABEL: v_ashr_pk_i8_i32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-FAKE16-NEXT: s_clause 0x1
+; GFX1250-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
+; GFX1250-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: s_and_b32 s2, s2, 31
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1250-FAKE16-NEXT: v_ashr_pk_i8_i32 v0, s0, s1, v0
+; GFX1250-FAKE16-NEXT: global_store_b16 v1, v0, s[6:7]
+; GFX1250-FAKE16-NEXT: s_endpgm
+;
+; GFX1300-TRUE16-LABEL: v_ashr_pk_i8_i32:
+; GFX1300-TRUE16: ; %bb.0:
+; GFX1300-TRUE16-NEXT: s_clause 0x1
+; GFX1300-TRUE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
+; GFX1300-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv
+; GFX1300-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1300-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1300-TRUE16-NEXT: s_and_b32 s2, s2, 31
+; GFX1300-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1300-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1300-TRUE16-NEXT: v_ashr_pk_i8_i32 v0.l, s0, s1, v0
+; GFX1300-TRUE16-NEXT: global_store_b16 v1, v0, s[4:5]
+; GFX1300-TRUE16-NEXT: s_endpgm
+;
+; GFX1300-FAKE16-LABEL: v_ashr_pk_i8_i32:
+; GFX1300-FAKE16: ; %bb.0:
+; GFX1300-FAKE16-NEXT: s_clause 0x1
+; GFX1300-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
+; GFX1300-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv
+; GFX1300-FAKE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1300-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1300-FAKE16-NEXT: s_and_b32 s2, s2, 31
+; GFX1300-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1300-FAKE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1300-FAKE16-NEXT: v_ashr_pk_i8_i32 v0, s0, s1, v0
+; GFX1300-FAKE16-NEXT: global_store_b16 v1, v0, s[4:5]
+; GFX1300-FAKE16-NEXT: s_endpgm
%insert.0 = insertelement <2 x i32> poison, i32 %src0, i64 0
%build_vector = insertelement <2 x i32> %insert.0, i32 %src1, i64 1
%src2.clamp = and i32 %src2, 31
@@ -57,20 +103,63 @@ define amdgpu_kernel void @v_ashr_pk_u8_i32(ptr addrspace(1) %out, i32 %src0, i3
; GFX950-NEXT: global_store_short v0, v1, s[6:7]
; GFX950-NEXT: s_endpgm
;
-; GFX1250-LABEL: v_ashr_pk_u8_i32:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
-; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_and_b32 s2, s2, 31
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_mov_b32_e32 v0, s2
-; GFX1250-NEXT: v_ashr_pk_u8_i32 v0, s0, s1, v0
-; GFX1250-NEXT: global_store_b16 v1, v0, s[6:7]
-; GFX1250-NEXT: s_endpgm
+; GFX1250-TRUE16-LABEL: v_ashr_pk_u8_i32:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-TRUE16-NEXT: s_clause 0x1
+; GFX1250-TRUE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
+; GFX1250-TRUE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: s_and_b32 s2, s2, 31
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1250-TRUE16-NEXT: v_ashr_pk_u8_i32 v0.l, s0, s1, v0
+; GFX1250-TRUE16-NEXT: global_store_b16 v1, v0, s[6:7]
+; GFX1250-TRUE16-NEXT: s_endpgm
+;
+; GFX1250-FAKE16-LABEL: v_ashr_pk_u8_i32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-FAKE16-NEXT: s_clause 0x1
+; GFX1250-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
+; GFX1250-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
+; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: s_and_b32 s2, s2, 31
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1250-FAKE16-NEXT: v_ashr_pk_u8_i32 v0, s0, s1, v0
+; GFX1250-FAKE16-NEXT: global_store_b16 v1, v0, s[6:7]
+; GFX1250-FAKE16-NEXT: s_endpgm
+;
+; GFX1300-TRUE16-LABEL: v_ashr_pk_u8_i32:
+; GFX1300-TRUE16: ; %bb.0:
+; GFX1300-TRUE16-NEXT: s_clause 0x1
+; GFX1300-TRUE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
+; GFX1300-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv
+; GFX1300-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1300-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1300-TRUE16-NEXT: s_and_b32 s2, s2, 31
+; GFX1300-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1300-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1300-TRUE16-NEXT: v_ashr_pk_u8_i32 v0.l, s0, s1, v0
+; GFX1300-TRUE16-NEXT: global_store_b16 v1, v0, s[4:5]
+; GFX1300-TRUE16-NEXT: s_endpgm
+;
+; GFX1300-FAKE16-LABEL: v_ashr_pk_u8_i32:
+; GFX1300-FAKE16: ; %bb.0:
+; GFX1300-FAKE16-NEXT: s_clause 0x1
+; GFX1300-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
+; GFX1300-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv
+; GFX1300-FAKE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1300-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1300-FAKE16-NEXT: s_and_b32 s2, s2, 31
+; GFX1300-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1300-FAKE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1300-FAKE16-NEXT: v_ashr_pk_u8_i32 v0, s0, s1, v0
+; GFX1300-FAKE16-NEXT: global_store_b16 v1, v0, s[4:5]
+; GFX1300-FAKE16-NEXT: s_endpgm
%insert.0 = insertelement <2 x i32> poison, i32 %src0, i64 0
%build_vector = insertelement <2 x i32> %insert.0, i32 %src1, i64 1
%src2.clamp = and i32 %src2, 31
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3.s
index 7b596bbb83d28..89bf957c1b6cc 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3.s
@@ -379,41 +379,41 @@ v_cvt_sr_pk_bf16_f32 v5, -src_scc, |vcc_lo|, -1 mul:4
v_cvt_sr_pk_bf16_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2
// GFX1250: v_cvt_sr_pk_bf16_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x6e,0xd7,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
-v_ashr_pk_i8_i32 v2, s4, v7, v8
-// GFX1250: v_ashr_pk_i8_i32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x0e,0x22,0x04]
+v_ashr_pk_i8_i32 v2.l, s4, v7, v8
+// GFX1250: v_ashr_pk_i8_i32 v2.l, s4, v7, v8 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x0e,0x22,0x04]
-v_ashr_pk_i8_i32 v2, v4, 0, 1
-// GFX1250: v_ashr_pk_i8_i32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x01,0x05,0x02]
+v_ashr_pk_i8_i32 v2.l, v4, 0, 1
+// GFX1250: v_ashr_pk_i8_i32 v2.l, v4, 0, 1 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x01,0x05,0x02]
-v_ashr_pk_i8_i32 v2, v4, 3, s2
-// GFX1250: v_ashr_pk_i8_i32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x07,0x09,0x00]
+v_ashr_pk_i8_i32 v2.l, v4, 3, s2
+// GFX1250: v_ashr_pk_i8_i32 v2.l, v4, 3, s2 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x07,0x09,0x00]
-v_ashr_pk_i8_i32 v2, s4, 4, v2
-// GFX1250: v_ashr_pk_i8_i32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x08,0x09,0x04]
+v_ashr_pk_i8_i32 v2.l, s4, 4, v2
+// GFX1250: v_ashr_pk_i8_i32 v2.l, s4, 4, v2 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x08,0x09,0x04]
-v_ashr_pk_i8_i32 v2, v4, v7, 12345
-// GFX1250: v_ashr_pk_i8_i32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00]
+v_ashr_pk_i8_i32 v2.l, v4, v7, 12345
+// GFX1250: v_ashr_pk_i8_i32 v2.l, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00]
-v_ashr_pk_i8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1]
-// GFX1250: v_ashr_pk_i8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x90,0xd6,0x02,0x07,0x12,0x04]
+v_ashr_pk_i8_i32 v1.h, v2, v3, v4 op_sel:[0,0,0,1]
+// GFX1250: v_ashr_pk_i8_i32 v1.h, v2, v3, v4 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x90,0xd6,0x02,0x07,0x12,0x04]
-v_ashr_pk_u8_i32 v2, s4, v7, v8
-// GFX1250: v_ashr_pk_u8_i32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x0e,0x22,0x04]
+v_ashr_pk_u8_i32 v2.l, s4, v7, v8
+// GFX1250: v_ashr_pk_u8_i32 v2.l, s4, v7, v8 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x0e,0x22,0x04]
-v_ashr_pk_u8_i32 v2, v4, 0, 1
-// GFX1250: v_ashr_pk_u8_i32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x01,0x05,0x02]
+v_ashr_pk_u8_i32 v2.l, v4, 0, 1
+// GFX1250: v_ashr_pk_u8_i32 v2.l, v4, 0, 1 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x01,0x05,0x02]
-v_ashr_pk_u8_i32 v2, v4, 3, s2
-// GFX1250: v_ashr_pk_u8_i32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x07,0x09,0x00]
+v_ashr_pk_u8_i32 v2.l, v4, 3, s2
+// GFX1250: v_ashr_pk_u8_i32 v2.l, v4, 3, s2 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x07,0x09,0x00]
-v_ashr_pk_u8_i32 v2, s4, 4, v2
-// GFX1250: v_ashr_pk_u8_i32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x08,0x09,0x04]
+v_ashr_pk_u8_i32 v2.l, s4, 4, v2
+// GFX1250: v_ashr_pk_u8_i32 v2.l, s4, 4, v2 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x08,0x09,0x04]
-v_ashr_pk_u8_i32 v2, v4, v7, 12345
-// GFX1250: v_ashr_pk_u8_i32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00]
+v_ashr_pk_u8_i32 v2.l, v4, v7, 12345
+// GFX1250: v_ashr_pk_u8_i32 v2.l, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00]
-v_ashr_pk_u8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1]
-// GFX1250: v_ashr_pk_u8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x91,0xd6,0x02,0x07,0x12,0x04]
+v_ashr_pk_u8_i32 v1.h, v2, v3, v4 op_sel:[0,0,0,1]
+// GFX1250: v_ashr_pk_u8_i32 v1.h, v2, v3, v4 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x91,0xd6,0x02,0x07,0x12,0x04]
v_cvt_pk_bf8_f16 v1.l, v2
// GFX1250: v_cvt_pk_bf8_f16 v1.l, v2 ; encoding: [0x01,0x00,0x73,0xd7,0x02,0x01,0x01,0x02]
diff --git a/llvm/test/MC/AMDGPU/gfx13_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx13_asm_vop3.s
index 601fe2e3db9d2..2d2841ba25584 100644
--- a/llvm/test/MC/AMDGPU/gfx13_asm_vop3.s
+++ b/llvm/test/MC/AMDGPU/gfx13_asm_vop3.s
@@ -532,41 +532,41 @@ v_and_or_b32 v5, src_scc, vcc_lo, -1
v_and_or_b32 v255, 0xaf123456, vcc_hi, null
// GFX13: v_and_or_b32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x71,0xd7,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
-v_ashr_pk_i8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1]
-// GFX13: v_ashr_pk_i8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x90,0xd6,0x02,0x07,0x12,0x04]
+v_ashr_pk_i8_i32 v1.h, v2, v3, v4 op_sel:[0,0,0,1]
+// GFX13: v_ashr_pk_i8_i32 v1.h, v2, v3, v4 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x90,0xd6,0x02,0x07,0x12,0x04]
-v_ashr_pk_i8_i32 v2, s4, 4, v2
-// GFX13: v_ashr_pk_i8_i32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x08,0x09,0x04]
+v_ashr_pk_i8_i32 v2.l, s4, 4, v2
+// GFX13: v_ashr_pk_i8_i32 v2.l, s4, 4, v2 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x08,0x09,0x04]
-v_ashr_pk_i8_i32 v2, s4, v7, v8
-// GFX13: v_ashr_pk_i8_i32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x0e,0x22,0x04]
+v_ashr_pk_i8_i32 v2.l, s4, v7, v8
+// GFX13: v_ashr_pk_i8_i32 v2.l, s4, v7, v8 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x0e,0x22,0x04]
-v_ashr_pk_i8_i32 v2, v4, 0, 1
-// GFX13: v_ashr_pk_i8_i32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x01,0x05,0x02]
+v_ashr_pk_i8_i32 v2.l, v4, 0, 1
+// GFX13: v_ashr_pk_i8_i32 v2.l, v4, 0, 1 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x01,0x05,0x02]
-v_ashr_pk_i8_i32 v2, v4, 3, s2
-// GFX13: v_ashr_pk_i8_i32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x07,0x09,0x00]
+v_ashr_pk_i8_i32 v2.l, v4, 3, s2
+// GFX13: v_ashr_pk_i8_i32 v2.l, v4, 3, s2 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x07,0x09,0x00]
-v_ashr_pk_i8_i32 v2, v4, v7, 12345
-// GFX13: v_ashr_pk_i8_i32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00]
+v_ashr_pk_i8_i32 v2.l, v4, v7, 12345
+// GFX13: v_ashr_pk_i8_i32 v2.l, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00]
-v_ashr_pk_u8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1]
-// GFX13: v_ashr_pk_u8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x91,0xd6,0x02,0x07,0x12,0x04]
+v_ashr_pk_u8_i32 v1.h, v2, v3, v4 op_sel:[0,0,0,1]
+// GFX13: v_ashr_pk_u8_i32 v1.h, v2, v3, v4 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x91,0xd6,0x02,0x07,0x12,0x04]
-v_ashr_pk_u8_i32 v2, s4, 4, v2
-// GFX13: v_ashr_pk_u8_i32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x08,0x09,0x04]
+v_ashr_pk_u8_i32 v2.l, s4, 4, v2
+// GFX13: v_ashr_pk_u8_i32 v2.l, s4, 4, v2 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x08,0x09,0x04]
-v_ashr_pk_u8_i32 v2, s4, v7, v8
-// GFX13: v_ashr_pk_u8_i32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x0e,0x22,0x04]
+v_ashr_pk_u8_i32 v2.l, s4, v7, v8
+// GFX13: v_ashr_pk_u8_i32 v2.l, s4, v7, v8 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x0e,0x22,0x04]
-v_ashr_pk_u8_i32 v2, v4, 0, 1
-// GFX13: v_ashr_pk_u8_i32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x01,0x05,0x02]
+v_ashr_pk_u8_i32 v2.l, v4, 0, 1
+// GFX13: v_ashr_pk_u8_i32 v2.l, v4, 0, 1 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x01,0x05,0x02]
-v_ashr_pk_u8_i32 v2, v4, 3, s2
-// GFX13: v_ashr_pk_u8_i32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x07,0x09,0x00]
+v_ashr_pk_u8_i32 v2.l, v4, 3, s2
+// GFX13: v_ashr_pk_u8_i32 v2.l, v4, 3, s2 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x07,0x09,0x00]
-v_ashr_pk_u8_i32 v2, v4, v7, 12345
-// GFX13: v_ashr_pk_u8_i32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00]
+v_ashr_pk_u8_i32 v2.l, v4, v7, 12345
+// GFX13: v_ashr_pk_u8_i32 v2.l, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00]
v_ashrrev_i16 v5.l, v1.l, v2.l
// GFX13: v_ashrrev_i16 v5.l, v1.l, v2.l ; encoding: [0x05,0x00,0x08,0xd7,0x01,0x05,0x02,0x02]
diff --git a/llvm/test/MC/AMDGPU/gfx13_asm_vop3_dpp16.s b/llvm/test/MC/AMDGPU/gfx13_asm_vop3_dpp16.s
index e8b6c03eeae7d..ae3200fb6e400 100644
--- a/llvm/test/MC/AMDGPU/gfx13_asm_vop3_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx13_asm_vop3_dpp16.s
@@ -491,29 +491,37 @@ v_and_or_b32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 boun
v_and_or_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX13: v_and_or_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x00,0x71,0xd7,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
-v_ashr_pk_i8_i32 v2, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3
-// GFX13: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3 ; encoding: [0x02,0x40,0x90,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0x53]
+v_ashr_pk_i8_i32 v2.h, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3
+// GFX13: v_ashr_pk_i8_i32_e64_dpp v2.h, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3 ; encoding: [0x02,0x40,0x90,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0x53]
+// ERR: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3
-v_ashr_pk_i8_i32 v2, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf
-// GFX13: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0xff]
+v_ashr_pk_i8_i32 v2.l, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX13: v_ashr_pk_i8_i32_e64_dpp v2.l, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0xff]
+// ERR: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf
-v_ashr_pk_i8_i32 v2, v4, v7, v8 quad_perm:[1,2,3,1]
-// GFX13: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, v8 quad_perm:[1,2,3,1] row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x79,0x00,0xff]
+v_ashr_pk_i8_i32 v2.l, v4, v7, v8 quad_perm:[1,2,3,1]
+// GFX13: v_ashr_pk_i8_i32_e64_dpp v2.l, v4, v7, v8 quad_perm:[1,2,3,1] row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x79,0x00,0xff]
+// ERR: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, v8 quad_perm:[1,2,3,1] row_mask:0xf bank_mask:0xf
-v_ashr_pk_i8_i32 v2, v4, v7, v8 row_share:3 fi:1
-// GFX13: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, v8 row_share:3 row_mask:0xf bank_mask:0xf fi:1 ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x53,0x05,0xff]
+v_ashr_pk_i8_i32 v2.l, v4, v7, v8 row_share:3 fi:1
+// GFX13: v_ashr_pk_i8_i32_e64_dpp v2.l, v4, v7, v8 row_share:3 row_mask:0xf bank_mask:0xf fi:1 ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x53,0x05,0xff]
+// ERR: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, v8 row_share:3 row_mask:0xf bank_mask:0xf fi:1
-v_ashr_pk_u8_i32 v2, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3
-// GFX13: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3 ; encoding: [0x02,0x40,0x91,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0x53]
+v_ashr_pk_u8_i32 v2.h, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3
+// GFX13: v_ashr_pk_u8_i32_e64_dpp v2.h, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3 ; encoding: [0x02,0x40,0x91,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0x53]
+// ERR: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3
-v_ashr_pk_u8_i32 v2, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf
-// GFX13: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0xff]
+v_ashr_pk_u8_i32 v2.l, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX13: v_ashr_pk_u8_i32_e64_dpp v2.l, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0xff]
+// ERR: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf
-v_ashr_pk_u8_i32 v2, v4, v7, v8 quad_perm:[1,2,3,1]
-// GFX13: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, v8 quad_perm:[1,2,3,1] row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x79,0x00,0xff]
+v_ashr_pk_u8_i32 v2.l, v4, v7, v8 quad_perm:[1,2,3,1]
+// GFX13: v_ashr_pk_u8_i32_e64_dpp v2.l, v4, v7, v8 quad_perm:[1,2,3,1] row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x79,0x00,0xff]
+// ERR: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, v8 quad_perm:[1,2,3,1] row_mask:0xf bank_mask:0xf
-v_ashr_pk_u8_i32 v2, v4, v7, v8 row_share:3 fi:1
-// GFX13: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, v8 row_share:3 row_mask:0xf bank_mask:0xf fi:1 ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x53,0x05,0xff]
+v_ashr_pk_u8_i32 v2.l, v4, v7, v8 row_share:3 fi:1
+// GFX13: v_ashr_pk_u8_i32_e64_dpp v2.l, v4, v7, v8 row_share:3 row_mask:0xf bank_mask:0xf fi:1 ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x53,0x05,0xff]
+// ERR: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, v8 row_share:3 row_mask:0xf bank_mask:0xf fi:1
v_ashrrev_i16_e64_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0]
// GFX13: v_ashrrev_i16_e64_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x08,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx13_asm_vop3_dpp8.s b/llvm/test/MC/AMDGPU/gfx13_asm_vop3_dpp8.s
index 654bdbf28f752..62466209858ff 100644
--- a/llvm/test/MC/AMDGPU/gfx13_asm_vop3_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx13_asm_vop3_dpp8.s
@@ -255,17 +255,17 @@ v_and_or_b32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
v_and_or_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX13: v_and_or_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x00,0x71,0xd7,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
-v_ashr_pk_i8_i32 v5, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1
-// GFX13: v_ashr_pk_i8_i32_e64_dpp v5, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x40,0x90,0xd6,0xea,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+v_ashr_pk_i8_i32 v5.h, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX13: v_ashr_pk_i8_i32_e64_dpp v5.h, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x40,0x90,0xd6,0xea,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
-v_ashr_pk_i8_i32 v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
-// GFX13: v_ashr_pk_i8_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x90,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+v_ashr_pk_i8_i32 v5.l, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX13: v_ashr_pk_i8_i32_e64_dpp v5.l, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x90,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
-v_ashr_pk_u8_i32 v5, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1
-// GFX13: v_ashr_pk_u8_i32_e64_dpp v5, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x40,0x91,0xd6,0xea,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+v_ashr_pk_u8_i32 v5.h, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX13: v_ashr_pk_u8_i32_e64_dpp v5.h, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x40,0x91,0xd6,0xea,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
-v_ashr_pk_u8_i32 v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
-// GFX13: v_ashr_pk_u8_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x91,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+v_ashr_pk_u8_i32 v5.l, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX13: v_ashr_pk_u8_i32_e64_dpp v5.l, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x91,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
v_ashrrev_i16_e64_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
// GFX13: v_ashrrev_i16_e64_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x08,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3.txt
index 84ed7b7d7f6bf..6233a064b7fa0 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3.txt
@@ -399,40 +399,52 @@
# GFX1250: v_cvt_sr_pk_bf16_f32 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x6e,0xd7,0x7e,0x82,0xad,0x01]
0x02,0x00,0x90,0xd6,0x04,0x08,0x09,0x04
-# GFX1250: v_ashr_pk_i8_i32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x08,0x09,0x04]
+# GFX1250-FAKE16: v_ashr_pk_i8_i32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x08,0x09,0x04]
+# GFX1250-REAL16: v_ashr_pk_i8_i32 v2.l, s4, 4, v2 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x08,0x09,0x04]
0x02,0x00,0x90,0xd6,0x04,0x0e,0x22,0x04
-# GFX1250: v_ashr_pk_i8_i32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x0e,0x22,0x04]
+# GFX1250-FAKE16: v_ashr_pk_i8_i32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x0e,0x22,0x04]
+# GFX1250-REAL16: v_ashr_pk_i8_i32 v2.l, s4, v7, v8 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x0e,0x22,0x04]
0x02,0x00,0x90,0xd6,0x04,0x01,0x05,0x02
-# GFX1250: v_ashr_pk_i8_i32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x01,0x05,0x02]
+# GFX1250-FAKE16: v_ashr_pk_i8_i32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x01,0x05,0x02]
+# GFX1250-REAL16: v_ashr_pk_i8_i32 v2.l, v4, 0, 1 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x01,0x05,0x02]
0x02,0x00,0x90,0xd6,0x04,0x07,0x09,0x00
-# GFX1250: v_ashr_pk_i8_i32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x07,0x09,0x00]
+# GFX1250-FAKE16: v_ashr_pk_i8_i32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x07,0x09,0x00]
+# GFX1250-REAL16: v_ashr_pk_i8_i32 v2.l, v4, 3, s2 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x07,0x09,0x00]
0x02,0x00,0x90,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00
-# GFX1250: v_ashr_pk_i8_i32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00]
+# GFX1250-FAKE16: v_ashr_pk_i8_i32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00]
+# GFX1250-REAL16: v_ashr_pk_i8_i32 v2.l, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00]
0x01,0x40,0x90,0xd6,0x02,0x07,0x12,0x04
-# GFX1250: v_ashr_pk_i8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x90,0xd6,0x02,0x07,0x12,0x04]
+# GFX1250-FAKE16: v_ashr_pk_i8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x90,0xd6,0x02,0x07,0x12,0x04]
+# GFX1250-REAL16: v_ashr_pk_i8_i32 v1.h, v2, v3, v4 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x90,0xd6,0x02,0x07,0x12,0x04]
0x02,0x00,0x91,0xd6,0x04,0x08,0x09,0x04
-# GFX1250: v_ashr_pk_u8_i32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x08,0x09,0x04]
+# GFX1250-FAKE16: v_ashr_pk_u8_i32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x08,0x09,0x04]
+# GFX1250-REAL16: v_ashr_pk_u8_i32 v2.l, s4, 4, v2 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x08,0x09,0x04]
0x02,0x00,0x91,0xd6,0x04,0x0e,0x22,0x04
-# GFX1250: v_ashr_pk_u8_i32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x0e,0x22,0x04]
+# GFX1250-FAKE16: v_ashr_pk_u8_i32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x0e,0x22,0x04]
+# GFX1250-REAL16: v_ashr_pk_u8_i32 v2.l, s4, v7, v8 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x0e,0x22,0x04]
0x02,0x00,0x91,0xd6,0x04,0x01,0x05,0x02
-# GFX1250: v_ashr_pk_u8_i32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x01,0x05,0x02]
+# GFX1250-FAKE16: v_ashr_pk_u8_i32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x01,0x05,0x02]
+# GFX1250-REAL16: v_ashr_pk_u8_i32 v2.l, v4, 0, 1 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x01,0x05,0x02]
0x02,0x00,0x91,0xd6,0x04,0x07,0x09,0x00
-# GFX1250: v_ashr_pk_u8_i32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x07,0x09,0x00]
+# GFX1250-FAKE16: v_ashr_pk_u8_i32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x07,0x09,0x00]
+# GFX1250-REAL16: v_ashr_pk_u8_i32 v2.l, v4, 3, s2 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x07,0x09,0x00]
0x02,0x00,0x91,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00
-# GFX1250: v_ashr_pk_u8_i32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00]
+# GFX1250-FAKE16: v_ashr_pk_u8_i32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00]
+# GFX1250-REAL16: v_ashr_pk_u8_i32 v2.l, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00]
0x01,0x40,0x91,0xd6,0x02,0x07,0x12,0x04
-# GFX1250: v_ashr_pk_u8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x91,0xd6,0x02,0x07,0x12,0x04]
+# GFX1250-FAKE16: v_ashr_pk_u8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x91,0xd6,0x02,0x07,0x12,0x04]
+# GFX1250-REAL16: v_ashr_pk_u8_i32 v1.h, v2, v3, v4 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x91,0xd6,0x02,0x07,0x12,0x04]
0x01,0x00,0x73,0xd7,0x02,0x01,0x00,0x00
# GFX1250-FAKE16: v_cvt_pk_bf8_f16 v1, v2 ; encoding: [0x01,0x00,0x73,0xd7,0x02,0x01,0x01,0x02]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_dpp16.txt
index 4b21239429cd2..e794a8bbaa55e 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_dpp16.txt
@@ -424,28 +424,36 @@
# GFX1250: v_cvt_sr_pk_bf16_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6e,0xd7,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
0x02,0x40,0x90,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0x53
-# GFX1250: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3 ; encoding: [0x02,0x40,0x90,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0x53]
+# GFX1250-FAKE16: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3 ; encoding: [0x02,0x40,0x90,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0x53]
+# GFX1250-REAL16: v_ashr_pk_i8_i32_e64_dpp v2.h, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3 ; encoding: [0x02,0x40,0x90,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0x53]
0x02,0x00,0x90,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0xff
-# GFX1250: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0xff]
+# GFX1250-FAKE16: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0xff]
+# GFX1250-REAL16: v_ashr_pk_i8_i32_e64_dpp v2.l, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0xff]
0x02,0x00,0x90,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x79,0x00,0xff
-# GFX1250: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, v8 quad_perm:[1,2,3,1] row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x79,0x00,0xff]
+# GFX1250-FAKE16: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, v8 quad_perm:[1,2,3,1] row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x79,0x00,0xff]
+# GFX1250-REAL16: v_ashr_pk_i8_i32_e64_dpp v2.l, v4, v7, v8 quad_perm:[1,2,3,1] row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x79,0x00,0xff]
0x02,0x00,0x90,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x53,0x05,0xff
-# GFX1250: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, v8 row_share:3 row_mask:0xf bank_mask:0xf fi:1 ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x53,0x05,0xff]
+# GFX1250-FAKE16: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, v8 row_share:3 row_mask:0xf bank_mask:0xf fi:1 ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x53,0x05,0xff]
+# GFX1250-REAL16: v_ashr_pk_i8_i32_e64_dpp v2.l, v4, v7, v8 row_share:3 row_mask:0xf bank_mask:0xf fi:1 ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x53,0x05,0xff]
0x02,0x40,0x91,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0x53
-# GFX1250: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3 ; encoding: [0x02,0x40,0x91,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0x53]
+# GFX1250-FAKE16: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3 ; encoding: [0x02,0x40,0x91,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0x53]
+# GFX1250-REAL16: v_ashr_pk_u8_i32_e64_dpp v2.h, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3 ; encoding: [0x02,0x40,0x91,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0x53]
0x02,0x00,0x91,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0xff
-# GFX1250: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0xff]
+# GFX1250-FAKE16: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0xff]
+# GFX1250-REAL16: v_ashr_pk_u8_i32_e64_dpp v2.l, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0xff]
0x02,0x00,0x91,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x79,0x00,0xff
-# GFX1250: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, v8 quad_perm:[1,2,3,1] row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x79,0x00,0xff]
+# GFX1250-FAKE16: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, v8 quad_perm:[1,2,3,1] row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x79,0x00,0xff]
+# GFX1250-REAL16: v_ashr_pk_u8_i32_e64_dpp v2.l, v4, v7, v8 quad_perm:[1,2,3,1] row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x79,0x00,0xff]
0x02,0x00,0x91,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x53,0x05,0xff
-# GFX1250: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, v8 row_share:3 row_mask:0xf bank_mask:0xf fi:1 ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x53,0x05,0xff]
+# GFX1250-FAKE16: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, v8 row_share:3 row_mask:0xf bank_mask:0xf fi:1 ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x53,0x05,0xff]
+# GFX1250-REAL16: v_ashr_pk_u8_i32_e64_dpp v2.l, v4, v7, v8 row_share:3 row_mask:0xf bank_mask:0xf fi:1 ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x53,0x05,0xff]
0x01,0x00,0x73,0xd7,0xfa,0x00,0x00,0x00,0x02,0x39,0x00,0xff
# GFX1250-FAKE16: v_cvt_pk_bf8_f16_e64_dpp v1, v2 quad_perm:[1,2,3,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0x73,0xd7,0xfa,0x00,0x00,0x00,0x02,0x39,0x00,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_dpp8.txt
index a14535f2b0018..6efadea7eb169 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_dpp8.txt
@@ -320,16 +320,20 @@
# GFX1250: v_cvt_sr_pk_bf16_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6e,0xd7,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
0x05,0x40,0x90,0xd6,0xea,0x04,0x0e,0x00,0x01,0x77,0x39,0x05
-# GFX1250: v_ashr_pk_i8_i32_e64_dpp v5, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x40,0x90,0xd6,0xea,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_ashr_pk_i8_i32_e64_dpp v5, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x40,0x90,0xd6,0xea,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+# GFX1250-REAL16: v_ashr_pk_i8_i32_e64_dpp v5.h, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x40,0x90,0xd6,0xea,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
0x05,0x00,0x90,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
-# GFX1250: v_ashr_pk_i8_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x90,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_ashr_pk_i8_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x90,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+# GFX1250-REAL16: v_ashr_pk_i8_i32_e64_dpp v5.l, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x90,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
0x05,0x40,0x91,0xd6,0xea,0x04,0x0e,0x00,0x01,0x77,0x39,0x05
-# GFX1250: v_ashr_pk_u8_i32_e64_dpp v5, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x40,0x91,0xd6,0xea,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_ashr_pk_u8_i32_e64_dpp v5, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x40,0x91,0xd6,0xea,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+# GFX1250-REAL16: v_ashr_pk_u8_i32_e64_dpp v5.h, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x40,0x91,0xd6,0xea,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
0x05,0x00,0x91,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
-# GFX1250: v_ashr_pk_u8_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x91,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_ashr_pk_u8_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x91,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+# GFX1250-REAL16: v_ashr_pk_u8_i32_e64_dpp v5.l, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x91,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
0x01,0x00,0x73,0xd7,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05
# GFX1250-FAKE16: v_cvt_pk_bf8_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x00,0x73,0xd7,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05]
>From 6efdea6fa0285efc3ef76afb7d670b77d2c0b359 Mon Sep 17 00:00:00 2001
From: Mariusz Sikora <mariusz.sikora at amd.com>
Date: Tue, 12 May 2026 15:42:05 -0400
Subject: [PATCH 2/4] Use OutPatFrag for true16HelperReg32FromSrc16
---
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 12 +++++++-----
llvm/lib/Target/AMDGPU/VOP3Instructions.td | 4 ++--
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 9e8bee80b9f74..b78c962b2be65 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -3566,11 +3566,13 @@ def getVOPDInfoFromComponentOpcodes : SearchIndex {
let Key = ["OpX", "OpY", "SubTgt", "VOPD3"];
}
-class true16HelperReg32FromSrc16<dag op, bit true16, bit ishi16 = 0> {
- dag ret = !if(true16,!if(ishi16, (REG_SEQUENCE VGPR_32, (i16 (IMPLICIT_DEF)), lo16, op, hi16),
- (REG_SEQUENCE VGPR_32, op, lo16, (i16 (IMPLICIT_DEF)), hi16)),
- op);
-}
+class true16HelperReg32FromSrc16<bit true16, bit ishi16 = 0> : OutPatFrag<
+ (ops node:$op),
+ !if(true16,
+ !if(ishi16,
+ (REG_SEQUENCE VGPR_32, (i16 (IMPLICIT_DEF)), lo16, $op, hi16),
+ (REG_SEQUENCE VGPR_32, $op, lo16, (i16 (IMPLICIT_DEF)), hi16)),
+ (COPY_TO_REGCLASS $op, VGPR_32))>;
include "SIInstructions.td"
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 0e4ff79f2ba83..e604d3cd466be 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -2024,13 +2024,13 @@ let SubtargetPredicate = HasAshrPkInsts, isReMaterializable = 1 in {
class AshrPkI8Pat<VOP3_Pseudo inst, int lo, int hi, bit true16 = 0>: GCNPat<
(i32 (or (i32 (shl (i32 (AMDGPUsmed3 (i32 (sra i32:$src1, i32:$src2)), (i32 lo), (i32 hi))), (i32 8))),
(i32 (and (i32 (AMDGPUsmed3 (i32 (sra i32:$src0, i32:$src2)), (i32 lo), (i32 hi))), (i32 255))))),
- true16HelperReg32FromSrc16<(inst 0, VSrc_b32:$src0, 0, VSrc_b32:$src1, 0, VSrc_b32:$src2, 0 ), true16>.ret
+ (true16HelperReg32FromSrc16<true16> (inst 0, VSrc_b32:$src0, 0, VSrc_b32:$src1, 0, VSrc_b32:$src2, 0 ))
>;
class AshrPkU8Pat<VOP3_Pseudo inst, int lo, int hi, bit true16 = 0>: GCNPat<
(i32 (or (i32 (shl (i32 (AMDGPUsmed3 (i32 (sra i32:$src1, i32:$src2)), (i32 lo), (i32 hi))), (i32 8))),
(i32 (AMDGPUsmed3 (i32 (sra i32:$src0, i32:$src2)), (i32 lo), (i32 hi))))),
- true16HelperReg32FromSrc16<(inst 0, VSrc_b32:$src0, 0, VSrc_b32:$src1, 0, VSrc_b32:$src2, 0 ), true16>.ret
+ (true16HelperReg32FromSrc16<true16> (inst 0, VSrc_b32:$src0, 0, VSrc_b32:$src1, 0, VSrc_b32:$src2, 0 ))
>;
let SubtargetPredicate = HasAshrPkInsts, True16Predicate = NotHasTrue16BitInsts in {
>From 53050a9fe7c19872b81ec19b9850c98396181b8f Mon Sep 17 00:00:00 2001
From: Mariusz Sikora <mariusz.sikora at amd.com>
Date: Wed, 13 May 2026 03:47:09 -0400
Subject: [PATCH 3/4] Split true16HelperReg32FromSrc16 into two OutPatFrags
---
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 12 ++++-----
llvm/lib/Target/AMDGPU/VOP3Instructions.td | 30 +++++++++++++---------
2 files changed, 23 insertions(+), 19 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index b78c962b2be65..35ead51a7f5d6 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -3566,13 +3566,11 @@ def getVOPDInfoFromComponentOpcodes : SearchIndex {
let Key = ["OpX", "OpY", "SubTgt", "VOPD3"];
}
-class true16HelperReg32FromSrc16<bit true16, bit ishi16 = 0> : OutPatFrag<
- (ops node:$op),
- !if(true16,
- !if(ishi16,
- (REG_SEQUENCE VGPR_32, (i16 (IMPLICIT_DEF)), lo16, $op, hi16),
- (REG_SEQUENCE VGPR_32, $op, lo16, (i16 (IMPLICIT_DEF)), hi16)),
- (COPY_TO_REGCLASS $op, VGPR_32))>;
+def true16Lo16ToReg32 : OutPatFrag<(ops node:$op),
+ (REG_SEQUENCE VGPR_32, $op, lo16, (i16 (IMPLICIT_DEF)), hi16)>;
+
+def true16Hi16ToReg32 : OutPatFrag<(ops node:$op),
+ (REG_SEQUENCE VGPR_32, (i16 (IMPLICIT_DEF)), lo16, $op, hi16)>;
include "SIInstructions.td"
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index e604d3cd466be..f6ffc085d3377 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -2021,30 +2021,36 @@ let SubtargetPredicate = HasAshrPkInsts, isReMaterializable = 1 in {
int_amdgcn_ashr_pk_u8_i32>;
} // End SubtargetPredicate = HasAshrPkInsts, isReMaterializable = 1
-class AshrPkI8Pat<VOP3_Pseudo inst, int lo, int hi, bit true16 = 0>: GCNPat<
+multiclass AshrPkI8Pat<VOP3_Pseudo inst, int lo, int hi, bit true16 = 0> {
+ defvar Inst = (inst 0, VSrc_b32:$src0, 0, VSrc_b32:$src1, 0, VSrc_b32:$src2, 0);
+
+ def : GCNPat<
(i32 (or (i32 (shl (i32 (AMDGPUsmed3 (i32 (sra i32:$src1, i32:$src2)), (i32 lo), (i32 hi))), (i32 8))),
(i32 (and (i32 (AMDGPUsmed3 (i32 (sra i32:$src0, i32:$src2)), (i32 lo), (i32 hi))), (i32 255))))),
- (true16HelperReg32FromSrc16<true16> (inst 0, VSrc_b32:$src0, 0, VSrc_b32:$src1, 0, VSrc_b32:$src2, 0 ))
->;
+ !if(true16, (true16Lo16ToReg32 Inst), Inst)>;
+}
+
+multiclass AshrPkU8Pat<VOP3_Pseudo inst, int lo, int hi, bit true16 = 0> {
+ defvar Inst = (inst 0, VSrc_b32:$src0, 0, VSrc_b32:$src1, 0, VSrc_b32:$src2, 0);
-class AshrPkU8Pat<VOP3_Pseudo inst, int lo, int hi, bit true16 = 0>: GCNPat<
+ def : GCNPat<
(i32 (or (i32 (shl (i32 (AMDGPUsmed3 (i32 (sra i32:$src1, i32:$src2)), (i32 lo), (i32 hi))), (i32 8))),
(i32 (AMDGPUsmed3 (i32 (sra i32:$src0, i32:$src2)), (i32 lo), (i32 hi))))),
- (true16HelperReg32FromSrc16<true16> (inst 0, VSrc_b32:$src0, 0, VSrc_b32:$src1, 0, VSrc_b32:$src2, 0 ))
->;
+ !if(true16, (true16Lo16ToReg32 Inst), Inst)>;
+}
let SubtargetPredicate = HasAshrPkInsts, True16Predicate = NotHasTrue16BitInsts in {
- def : AshrPkI8Pat<V_ASHR_PK_I8_I32_e64, -128, 127>;
- def : AshrPkU8Pat<V_ASHR_PK_U8_I32_e64, 0, 255>;
+ defm : AshrPkI8Pat<V_ASHR_PK_I8_I32_e64, -128, 127>;
+ defm : AshrPkU8Pat<V_ASHR_PK_U8_I32_e64, 0, 255>;
}
let SubtargetPredicate = HasAshrPkInsts, True16Predicate = UseFakeTrue16Insts in {
- def : AshrPkI8Pat<V_ASHR_PK_I8_I32_fake16_e64, -128, 127>;
- def : AshrPkU8Pat<V_ASHR_PK_U8_I32_fake16_e64, 0, 255>;
+ defm : AshrPkI8Pat<V_ASHR_PK_I8_I32_fake16_e64, -128, 127>;
+ defm : AshrPkU8Pat<V_ASHR_PK_U8_I32_fake16_e64, 0, 255>;
}
let SubtargetPredicate = HasAshrPkInsts, True16Predicate = UseRealTrue16Insts in {
- def : AshrPkI8Pat<V_ASHR_PK_I8_I32_t16_e64, -128, 127, 1>;
- def : AshrPkU8Pat<V_ASHR_PK_U8_I32_t16_e64, 0, 255, 1>;
+ defm : AshrPkI8Pat<V_ASHR_PK_I8_I32_t16_e64, -128, 127, 1>;
+ defm : AshrPkU8Pat<V_ASHR_PK_U8_I32_t16_e64, 0, 255, 1>;
}
let SubtargetPredicate = isGFX13Plus in {
>From c7ec18171c33c67c220483a2db74658757652172 Mon Sep 17 00:00:00 2001
From: Mariusz Sikora <mariusz.sikora at amd.com>
Date: Wed, 13 May 2026 06:57:06 -0400
Subject: [PATCH 4/4] Rename true16(Lo|Hi)16ToReg32 to (lo|hi)16_to_vgpr32
---
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 4 ++--
llvm/lib/Target/AMDGPU/VOP3Instructions.td | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 35ead51a7f5d6..e06ab018abed8 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -3566,10 +3566,10 @@ def getVOPDInfoFromComponentOpcodes : SearchIndex {
let Key = ["OpX", "OpY", "SubTgt", "VOPD3"];
}
-def true16Lo16ToReg32 : OutPatFrag<(ops node:$op),
+def lo16_to_vgpr32 : OutPatFrag<(ops node:$op),
(REG_SEQUENCE VGPR_32, $op, lo16, (i16 (IMPLICIT_DEF)), hi16)>;
-def true16Hi16ToReg32 : OutPatFrag<(ops node:$op),
+def hi16_to_vgpr32 : OutPatFrag<(ops node:$op),
(REG_SEQUENCE VGPR_32, (i16 (IMPLICIT_DEF)), lo16, $op, hi16)>;
include "SIInstructions.td"
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index f6ffc085d3377..3a477cad4248c 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -2027,7 +2027,7 @@ multiclass AshrPkI8Pat<VOP3_Pseudo inst, int lo, int hi, bit true16 = 0> {
def : GCNPat<
(i32 (or (i32 (shl (i32 (AMDGPUsmed3 (i32 (sra i32:$src1, i32:$src2)), (i32 lo), (i32 hi))), (i32 8))),
(i32 (and (i32 (AMDGPUsmed3 (i32 (sra i32:$src0, i32:$src2)), (i32 lo), (i32 hi))), (i32 255))))),
- !if(true16, (true16Lo16ToReg32 Inst), Inst)>;
+ !if(true16, (lo16_to_vgpr32 Inst), Inst)>;
}
multiclass AshrPkU8Pat<VOP3_Pseudo inst, int lo, int hi, bit true16 = 0> {
@@ -2036,7 +2036,7 @@ multiclass AshrPkU8Pat<VOP3_Pseudo inst, int lo, int hi, bit true16 = 0> {
def : GCNPat<
(i32 (or (i32 (shl (i32 (AMDGPUsmed3 (i32 (sra i32:$src1, i32:$src2)), (i32 lo), (i32 hi))), (i32 8))),
(i32 (AMDGPUsmed3 (i32 (sra i32:$src0, i32:$src2)), (i32 lo), (i32 hi))))),
- !if(true16, (true16Lo16ToReg32 Inst), Inst)>;
+ !if(true16, (lo16_to_vgpr32 Inst), Inst)>;
}
let SubtargetPredicate = HasAshrPkInsts, True16Predicate = NotHasTrue16BitInsts in {
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