[llvm] [AMDGPU] Remove RCP_IFLAG combine (PR #197426)
via llvm-commits
llvm-commits at lists.llvm.org
Wed May 13 04:49:58 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Piotr Sobczak (piotrAMD)
<details>
<summary>Changes</summary>
The combine was added in D48569 8 years ago with the aim of preserving flags, but the current LangRef says the status flags are not observable in the default FP environment.
The main motivation for this change is to enable scalar float reciprocal generation v_s_rcp_f32 on newer hardware. There is no v_s_rcp_iflag_f32, so the combine effectively blocks the selection.
See: pseudo-scalar-transcendental.ll.
---
Patch is 197.18 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/197426.diff
25 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (-6)
- (modified) llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll (+160-160)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-codegen.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/bypass-div.ll (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/idiv-licm.ll (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll (+6-7)
- (modified) llvm/test/CodeGen/AMDGPU/med3-knownbits.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/permute_i8.ll (+32-32)
- (modified) llvm/test/CodeGen/AMDGPU/pr155452.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll (+10-19)
- (removed) llvm/test/CodeGen/AMDGPU/rcp_iflag.ll (-46)
- (modified) llvm/test/CodeGen/AMDGPU/sdiv.ll (+33-33)
- (modified) llvm/test/CodeGen/AMDGPU/sdiv64.ll (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/sdivrem24.ll (+9-17)
- (modified) llvm/test/CodeGen/AMDGPU/srem.ll (+21-21)
- (modified) llvm/test/CodeGen/AMDGPU/srem64.ll (+20-20)
- (modified) llvm/test/CodeGen/AMDGPU/udiv.ll (+52-52)
- (modified) llvm/test/CodeGen/AMDGPU/udiv64.ll (+18-18)
- (modified) llvm/test/CodeGen/AMDGPU/udivrem.ll (+14-14)
- (modified) llvm/test/CodeGen/AMDGPU/udivrem24.ll (+40-40)
- (modified) llvm/test/CodeGen/AMDGPU/urem64.ll (+18-18)
- (modified) llvm/test/CodeGen/AMDGPU/wave32.ll (+4-4)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 6c88bc7145eda..2a587684f11c0 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -15463,12 +15463,6 @@ SDValue SITargetLowering::performRcpCombine(SDNode *N,
SDLoc(N), VT);
}
- if (VT == MVT::f32 && (N0.getOpcode() == ISD::UINT_TO_FP ||
- N0.getOpcode() == ISD::SINT_TO_FP)) {
- return DCI.DAG.getNode(AMDGPUISD::RCP_IFLAG, SDLoc(N), VT, N0,
- N->getFlags());
- }
-
// TODO: Could handle f32 + amdgcn.sqrt but probably never reaches here.
if ((VT == MVT::f16 && N0.getOpcode() == ISD::FSQRT) &&
N->getFlags().hasAllowContract() && N0->getFlags().hasAllowContract()) {
diff --git a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
index 4c10e4d459849..daf7fed3731f5 100644
--- a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
+++ b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
@@ -520,7 +520,7 @@ define amdgpu_kernel void @introduced_copy_to_sgpr(i64 %arg, i32 %arg1, i32 %arg
; GFX908-NEXT: s_sub_i32 s1, 0, s7
; GFX908-NEXT: v_cvt_f32_f16_e32 v18, s0
; GFX908-NEXT: v_mov_b32_e32 v17, 0
-; GFX908-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX908-NEXT: v_rcp_f32_e32 v0, v0
; GFX908-NEXT: v_mov_b32_e32 v1, 0
; GFX908-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX908-NEXT: v_cvt_u32_f32_e32 v0, v0
@@ -683,7 +683,7 @@ define amdgpu_kernel void @introduced_copy_to_sgpr(i64 %arg, i32 %arg1, i32 %arg
; GFX90A-NEXT: s_sub_i32 s1, 0, s7
; GFX90A-NEXT: v_mov_b32_e32 v19, 0
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], 0, 0
-; GFX90A-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX90A-NEXT: v_rcp_f32_e32 v0, v0
; GFX90A-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v0
; GFX90A-NEXT: v_cvt_f32_f16_e32 v0, s0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
index 62059cd989ba2..a2e3c9aa8acc5 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
@@ -140,7 +140,7 @@ define i32 @select_sdiv_lhs_opaque_const0_i32(i1 %cond) {
; GCN-NEXT: v_cvt_f32_u32_e32 v2, v1
; GCN-NEXT: v_sub_u32_e32 v3, vcc, 0, v1
; GCN-NEXT: s_mov_b32 s4, 0xf4240
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GCN-NEXT: v_rcp_f32_e32 v2, v2
; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v0
; GCN-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
@@ -222,7 +222,7 @@ define i32 @select_sdiv_lhs_opaque_const1_i32(i1 %cond) {
; GCN-NEXT: v_cvt_f32_u32_e32 v2, v1
; GCN-NEXT: v_sub_u32_e32 v3, vcc, 0, v1
; GCN-NEXT: s_mov_b32 s4, 0xf4240
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GCN-NEXT: v_rcp_f32_e32 v2, v2
; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v0
; GCN-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
index 018eb779fc815..1659ca62a0516 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
@@ -45,7 +45,7 @@ define amdgpu_kernel void @udiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s5
; GFX6-NEXT: s_sub_i32 s2, 0, s5
; GFX6-NEXT: s_mov_b32 s3, 0xf000
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_lo_u32 v1, s2, v0
@@ -76,7 +76,7 @@ define amdgpu_kernel void @udiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX9-NEXT: s_sub_i32 s4, 0, s3
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_readfirstlane_b32 s5, v0
@@ -142,7 +142,7 @@ define amdgpu_kernel void @urem_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s5
; GFX6-NEXT: s_sub_i32 s2, 0, s5
; GFX6-NEXT: s_mov_b32 s3, 0xf000
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_lo_u32 v1, s2, v0
@@ -170,7 +170,7 @@ define amdgpu_kernel void @urem_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX9-NEXT: s_sub_i32 s4, 0, s3
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_readfirstlane_b32 s5, v0
@@ -247,7 +247,7 @@ define amdgpu_kernel void @sdiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX6-NEXT: s_sub_i32 s2, 0, s6
; GFX6-NEXT: s_abs_i32 s7, s4
; GFX6-NEXT: s_xor_b32 s4, s4, s5
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: s_ashr_i32 s4, s4, 31
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
@@ -285,7 +285,7 @@ define amdgpu_kernel void @sdiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX9-NEXT: s_sub_i32 s5, 0, s4
; GFX9-NEXT: s_xor_b32 s3, s2, s3
; GFX9-NEXT: s_abs_i32 s2, s2
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_ashr_i32 s3, s3, 31
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
@@ -364,7 +364,7 @@ define amdgpu_kernel void @srem_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX6-NEXT: s_sub_i32 s2, 0, s5
; GFX6-NEXT: s_abs_i32 s6, s4
; GFX6-NEXT: s_ashr_i32 s4, s4, 31
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
@@ -398,7 +398,7 @@ define amdgpu_kernel void @srem_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX9-NEXT: s_sub_i32 s5, 0, s3
; GFX9-NEXT: s_ashr_i32 s4, s2, 31
; GFX9-NEXT: s_abs_i32 s2, s2
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_readfirstlane_b32 s6, v0
@@ -457,7 +457,7 @@ define amdgpu_kernel void @udiv_i16(ptr addrspace(1) %out, i16 %x, i16 %y) {
; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: v_rcp_f32_e32 v2, v0
; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
; GFX6-NEXT: v_trunc_f32_e32 v2, v2
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v2
@@ -478,7 +478,7 @@ define amdgpu_kernel void @udiv_i16(ptr addrspace(1) %out, i16 %x, i16 %y) {
; GFX9-NEXT: s_and_b32 s0, s0, 0xffff
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s0
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX9-NEXT: v_rcp_f32_e32 v2, v0
; GFX9-NEXT: v_mul_f32_e32 v2, v1, v2
; GFX9-NEXT: v_trunc_f32_e32 v2, v2
; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v2
@@ -527,7 +527,7 @@ define amdgpu_kernel void @urem_i16(ptr addrspace(1) %out, i16 %x, i16 %y) {
; GFX6-NEXT: s_and_b32 s0, s6, 0xffff
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: v_rcp_f32_e32 v2, v0
; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
; GFX6-NEXT: v_trunc_f32_e32 v2, v2
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v2
@@ -550,7 +550,7 @@ define amdgpu_kernel void @urem_i16(ptr addrspace(1) %out, i16 %x, i16 %y) {
; GFX9-NEXT: s_and_b32 s0, s2, 0xffff
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s0
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX9-NEXT: v_rcp_f32_e32 v2, v0
; GFX9-NEXT: v_mul_f32_e32 v2, v1, v2
; GFX9-NEXT: v_trunc_f32_e32 v2, v2
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v2
@@ -606,7 +606,7 @@ define amdgpu_kernel void @sdiv_i16(ptr addrspace(1) %out, i16 %x, i16 %y) {
; GFX6-NEXT: s_sext_i32_i16 s5, s6
; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s5
; GFX6-NEXT: s_xor_b32 s4, s5, s4
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: v_rcp_f32_e32 v2, v0
; GFX6-NEXT: s_ashr_i32 s4, s4, 30
; GFX6-NEXT: s_or_b32 s6, s4, 1
; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
@@ -631,7 +631,7 @@ define amdgpu_kernel void @sdiv_i16(ptr addrspace(1) %out, i16 %x, i16 %y) {
; GFX9-NEXT: s_sext_i32_i16 s2, s2
; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s2
; GFX9-NEXT: s_xor_b32 s2, s2, s3
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
+; GFX9-NEXT: v_rcp_f32_e32 v3, v0
; GFX9-NEXT: s_ashr_i32 s2, s2, 30
; GFX9-NEXT: s_or_b32 s4, s2, 1
; GFX9-NEXT: v_mul_f32_e32 v3, v2, v3
@@ -687,7 +687,7 @@ define amdgpu_kernel void @srem_i16(ptr addrspace(1) %out, i16 %x, i16 %y) {
; GFX6-NEXT: s_sext_i32_i16 s2, s6
; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s2
; GFX6-NEXT: s_xor_b32 s2, s2, s7
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: v_rcp_f32_e32 v2, v0
; GFX6-NEXT: s_ashr_i32 s2, s2, 30
; GFX6-NEXT: s_or_b32 s4, s2, 1
; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
@@ -715,7 +715,7 @@ define amdgpu_kernel void @srem_i16(ptr addrspace(1) %out, i16 %x, i16 %y) {
; GFX9-NEXT: s_sext_i32_i16 s2, s6
; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s2
; GFX9-NEXT: s_xor_b32 s2, s2, s7
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX9-NEXT: v_rcp_f32_e32 v2, v0
; GFX9-NEXT: s_ashr_i32 s2, s2, 30
; GFX9-NEXT: s_or_b32 s4, s2, 1
; GFX9-NEXT: v_mul_f32_e32 v2, v1, v2
@@ -766,7 +766,7 @@ define amdgpu_kernel void @udiv_i8(ptr addrspace(1) %out, i8 %x, i8 %y) {
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_ubyte1_e32 v0, s6
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v0
+; GFX6-NEXT: v_rcp_f32_e32 v1, v0
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, s6
; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1
; GFX6-NEXT: v_trunc_f32_e32 v1, v1
@@ -784,7 +784,7 @@ define amdgpu_kernel void @udiv_i8(ptr addrspace(1) %out, i8 %x, i8 %y) {
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_ubyte1_e32 v0, s2
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v0
+; GFX9-NEXT: v_rcp_f32_e32 v1, v0
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, s2
; GFX9-NEXT: v_mul_f32_e32 v1, v3, v1
; GFX9-NEXT: v_trunc_f32_e32 v1, v1
@@ -830,7 +830,7 @@ define amdgpu_kernel void @urem_i8(ptr addrspace(1) %out, i8 %x, i8 %y) {
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_ubyte1_e32 v0, s6
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v0
+; GFX6-NEXT: v_rcp_f32_e32 v1, v0
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, s6
; GFX6-NEXT: s_lshr_b32 s2, s6, 8
; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1
@@ -851,7 +851,7 @@ define amdgpu_kernel void @urem_i8(ptr addrspace(1) %out, i8 %x, i8 %y) {
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_ubyte1_e32 v0, s2
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v0
+; GFX9-NEXT: v_rcp_f32_e32 v1, v0
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v2, s2
; GFX9-NEXT: s_lshr_b32 s3, s2, 8
; GFX9-NEXT: v_mul_f32_e32 v1, v2, v1
@@ -908,7 +908,7 @@ define amdgpu_kernel void @sdiv_i8(ptr addrspace(1) %out, i8 %x, i8 %y) {
; GFX6-NEXT: s_sext_i32_i8 s5, s6
; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s5
; GFX6-NEXT: s_xor_b32 s4, s5, s4
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: v_rcp_f32_e32 v2, v0
; GFX6-NEXT: s_ashr_i32 s4, s4, 30
; GFX6-NEXT: s_or_b32 s6, s4, 1
; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
@@ -933,7 +933,7 @@ define amdgpu_kernel void @sdiv_i8(ptr addrspace(1) %out, i8 %x, i8 %y) {
; GFX9-NEXT: s_sext_i32_i8 s2, s2
; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s2
; GFX9-NEXT: s_xor_b32 s2, s2, s3
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
+; GFX9-NEXT: v_rcp_f32_e32 v3, v0
; GFX9-NEXT: s_ashr_i32 s2, s2, 30
; GFX9-NEXT: s_or_b32 s4, s2, 1
; GFX9-NEXT: v_mul_f32_e32 v3, v2, v3
@@ -989,7 +989,7 @@ define amdgpu_kernel void @srem_i8(ptr addrspace(1) %out, i8 %x, i8 %y) {
; GFX6-NEXT: s_sext_i32_i8 s3, s6
; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s3
; GFX6-NEXT: s_xor_b32 s2, s3, s2
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: v_rcp_f32_e32 v2, v0
; GFX6-NEXT: s_ashr_i32 s2, s2, 30
; GFX6-NEXT: s_lshr_b32 s4, s6, 8
; GFX6-NEXT: s_or_b32 s5, s2, 1
@@ -1018,7 +1018,7 @@ define amdgpu_kernel void @srem_i8(ptr addrspace(1) %out, i8 %x, i8 %y) {
; GFX9-NEXT: s_sext_i32_i8 s3, s6
; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s3
; GFX9-NEXT: s_xor_b32 s2, s3, s2
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX9-NEXT: v_rcp_f32_e32 v2, v0
; GFX9-NEXT: s_ashr_i32 s2, s2, 30
; GFX9-NEXT: s_lshr_b32 s4, s6, 8
; GFX9-NEXT: s_or_b32 s5, s2, 1
@@ -1184,13 +1184,13 @@ define amdgpu_kernel void @udiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; GFX6-NEXT: s_sub_i32 s0, 0, s12
; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s13
; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s14
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s15
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v4
+; GFX6-NEXT: v_rcp_f32_e32 v2, v2
+; GFX6-NEXT: v_rcp_f32_e32 v4, v4
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v6
+; GFX6-NEXT: v_rcp_f32_e32 v6, v6
; GFX6-NEXT: v_mul_lo_u32 v1, s0, v0
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
@@ -1281,8 +1281,8 @@ define amdgpu_kernel void @udiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s13
; GFX9-NEXT: s_sub_i32 s2, 0, s12
; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s14
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
+; GFX9-NEXT: v_rcp_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
@@ -1307,7 +1307,7 @@ define amdgpu_kernel void @udiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; GFX9-NEXT: s_mul_i32 s3, s3, s4
; GFX9-NEXT: s_mul_hi_u32 s3, s4, s3
; GFX9-NEXT: s_add_i32 s4, s4, s3
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v2
+; GFX9-NEXT: v_rcp_f32_e32 v0, v2
; GFX9-NEXT: s_mul_hi_u32 s3, s9, s4
; GFX9-NEXT: s_mul_i32 s4, s3, s13
; GFX9-NEXT: s_sub_i32 s4, s9, s4
@@ -1327,7 +1327,7 @@ define amdgpu_kernel void @udiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; GFX9-NEXT: s_mul_i32 s4, s4, s5
; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4
; GFX9-NEXT: s_add_i32 s5, s5, s4
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_mul_hi_u32 s4, s10, s5
; GFX9-NEXT: s_mul_i32 s5, s4, s14
; GFX9-NEXT: s_sub_i32 s5, s10, s5
@@ -1502,8 +1502,8 @@ define amdgpu_kernel void @urem_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s12
; GFX6-NEXT: s_sub_i32 s0, 0, s12
; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s13
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT: v_rcp_f32_e32 v0, v0
+; GFX6-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_lo_u32 v1, s0, v0
@@ -1524,7 +1524,7 @@ define amdgpu_kernel void @urem_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; GFX6-NEXT: s_cselect_b32 s6, s1, s0
; GFX6-NEXT: s_sub_i32 s0, 0, s13
; GFX6-NEXT: v_mul_lo_u32 v0, s0, v1
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-NEXT: v_mul_hi_u32 v0, v1, v0
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s9, v0
@@ -1542,7 +1542,7 @@ define amdgpu_kernel void @urem_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; GFX6-NEXT: s_cselect_b32 s7, s1, s0
; GFX6-NEXT: s_sub_i32 s0, 0, s14
; GFX6-NEXT: v_mul_lo_u32 v0, s0, v1
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-NEXT: v_mul_hi_u32 v0, v1, v0
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s10, v0
@@ -1590,9 +1590,9 @@ define amdgpu_kernel void @urem_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s13
; GFX9-NEXT: s_sub_i32 s2, 0, s12
; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s14
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
+; GFX9-NEXT: v_rcp_f32_e32 v1, v1
+; GFX9-NEXT: v_rcp_f32_e32 v2, v2
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
@@ -1632,7 +1632,7 @@ define amdgpu_kernel void @urem_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; GFX9-NEXT: s_mul_i32 s4, s4, s5
; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4
; GFX9-NEXT: s_add_i32 s5, s5, s4
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_mul_hi_u32 s4, s10, s5
; GFX9-NEXT: s_mul_i32 s4, s4, s14
; GFX9-NEXT: s_sub_i32 s4, s10, s4
@@ -1849,7 +1849,7 @@ define amdgpu_kernel void @sdiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s0
; GFX6-NEXT: s_sub_i32 s1, 0, s0
; GFX6-NEXT: s_xor_b32 s2, s8, s12
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_lo_u32 v1, s1, v0
@@ -1873,7 +1873,7 @@ define amdgpu_kernel void @sdiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; GFX6-NEXT: s_sub_i32 s3, 0, s2
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: s_xor_b32 s6, s9, s13
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v0
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
@@ -1900,7 +1900,7 @@ define amdgpu_kernel void @sdiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; GFX6-NEXT: s_sub_i32 s7, 0, s6
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v2
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v4
+; GFX6-NEXT: v_rcp_f32_e32 v4, v4
; GFX6-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX6-NEXT: v_mul_lo_u32 v5, s7, v4
@@ -1925,7 +1925,7 @@ define amdgpu_kernel void @sdiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; GFX6-NEXT: s_sub_i32 s0, 0, s12
; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v4
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v6
+; GFX6-NEXT: v_rcp_f32_e32 v1, v6
; GFX6-NEXT: s_abs_i32 s1, s11
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0
; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
@@ -1970,7 +1970,7 @@ define amdgpu_kernel void @sdiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; GFX9-NEXT: s_sub_i32 s3, 0, s0
; GFX9-NEXT: s_abs_i32 s2, s8
; GFX9-NEXT: s_xor_b32 s1, s8, s12
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_ashr_i32 s1, s1, 31
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/197426
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