[llvm] [CodeGen] Debug insns must not affect liveness analysis (PR #193104)
via llvm-commits
llvm-commits at lists.llvm.org
Wed May 13 05:01:12 PDT 2026
https://github.com/LU-JOHN updated https://github.com/llvm/llvm-project/pull/193104
>From e63b2e3f90f7d0f97cc007227775033a5c396843 Mon Sep 17 00:00:00 2001
From: John Lu <John.Lu at amd.com>
Date: Mon, 20 Apr 2026 17:51:44 -0500
Subject: [PATCH 1/8] Debug insns must not affect DCE
Signed-off-by: John Lu <John.Lu at amd.com>
---
.../CodeGen/DeadMachineInstructionElim.cpp | 3 +++
...debug-independence-dead-mi-elimination.mir | 25 +++++++++++++++++++
2 files changed, 28 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir
diff --git a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
index 2c58b014d2399..0970422b6818a 100644
--- a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
+++ b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
@@ -105,6 +105,9 @@ bool DeadMachineInstructionElimImpl::eliminateDeadMI(
// Now scan the instructions and delete dead ones, tracking physreg
// liveness as we go.
for (MachineInstr &MI : make_early_inc_range(reverse(*MBB))) {
+ // Do not let debug instructions affect liveness calculations.
+ if (MI.isDebugInstr())
+ continue;
// If the instruction is dead, delete it!
if (MI.isDead(*MRI, &LivePhysRegs)) {
if (MI.isPHI()) {
diff --git a/llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir b/llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir
new file mode 100644
index 0000000000000..b47a39e646252
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir
@@ -0,0 +1,25 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass dead-mi-elimination -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass dead-mi-elimination -o - %s -debugify-and-strip-all-safe | FileCheck %s
+
+# Ensure that references in debug instructions to register results in dead
+# instructions does not prevent DCE.
+
+---
+name: func
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; GCN-LABEL: name: func
+ ; GCN: liveins: $vgpr0
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: SI_RETURN implicit $vgpr0
+ ; CHECK-LABEL: name: func
+ ; CHECK: liveins: $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: SI_RETURN implicit $vgpr0
+ $sgpr0 = S_MOV_B32 0
+ SI_RETURN implicit $vgpr0
+...
+
>From cbd955048ebdd40bad0aa1ca88056f62007e06f4 Mon Sep 17 00:00:00 2001
From: John Lu <John.Lu at amd.com>
Date: Tue, 21 Apr 2026 15:42:16 -0500
Subject: [PATCH 2/8] Skip debug insns in stepBackward
Signed-off-by: John Lu <John.Lu at amd.com>
---
llvm/lib/CodeGen/DeadMachineInstructionElim.cpp | 3 ---
llvm/lib/CodeGen/LiveRegUnits.cpp | 4 ++++
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
index 0970422b6818a..2c58b014d2399 100644
--- a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
+++ b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
@@ -105,9 +105,6 @@ bool DeadMachineInstructionElimImpl::eliminateDeadMI(
// Now scan the instructions and delete dead ones, tracking physreg
// liveness as we go.
for (MachineInstr &MI : make_early_inc_range(reverse(*MBB))) {
- // Do not let debug instructions affect liveness calculations.
- if (MI.isDebugInstr())
- continue;
// If the instruction is dead, delete it!
if (MI.isDead(*MRI, &LivePhysRegs)) {
if (MI.isPHI()) {
diff --git a/llvm/lib/CodeGen/LiveRegUnits.cpp b/llvm/lib/CodeGen/LiveRegUnits.cpp
index 348ccd85f4c45..c04c1404c29a5 100644
--- a/llvm/lib/CodeGen/LiveRegUnits.cpp
+++ b/llvm/lib/CodeGen/LiveRegUnits.cpp
@@ -42,6 +42,10 @@ void LiveRegUnits::addRegsInMask(const uint32_t *RegMask) {
}
void LiveRegUnits::stepBackward(const MachineInstr &MI) {
+ // Do not let debug instructions affect liveness calculations.
+ if (MI.isDebugInstr())
+ return;
+
// Remove defined registers and regmask kills from the set.
for (const MachineOperand &MOP : MI.operands()) {
if (MOP.isReg()) {
>From f8ddc8e58d96f21ecd7342e304d4c3044baef987 Mon Sep 17 00:00:00 2001
From: John Lu <John.Lu at amd.com>
Date: Tue, 21 Apr 2026 15:45:28 -0500
Subject: [PATCH 3/8] Fix grammar
Signed-off-by: John Lu <John.Lu at amd.com>
---
.../CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir b/llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir
index b47a39e646252..c1844406a8917 100644
--- a/llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir
+++ b/llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir
@@ -3,7 +3,7 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass dead-mi-elimination -o - %s -debugify-and-strip-all-safe | FileCheck %s
# Ensure that references in debug instructions to register results in dead
-# instructions does not prevent DCE.
+# instructions do not prevent DCE.
---
name: func
>From c4340a1f890ec7b06a622a837ec63fe9df3e46ab Mon Sep 17 00:00:00 2001
From: John Lu <John.Lu at amd.com>
Date: Wed, 22 Apr 2026 08:40:35 -0500
Subject: [PATCH 4/8] Address feedback
Signed-off-by: John Lu <John.Lu at amd.com>
---
.../CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir b/llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir
index c1844406a8917..a35eb170ea937 100644
--- a/llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir
+++ b/llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass dead-mi-elimination -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass dead-mi-elimination -o - %s -debugify-and-strip-all-safe | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=dead-mi-elimination -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=dead-mi-elimination -o - %s -debugify-and-strip-all-safe | FileCheck %s
# Ensure that references in debug instructions to register results in dead
# instructions do not prevent DCE.
>From 68051a599a6c4a60e45bef65a9cc0472b4e67037 Mon Sep 17 00:00:00 2001
From: John Lu <John.Lu at amd.com>
Date: Fri, 8 May 2026 16:06:24 -0500
Subject: [PATCH 5/8] More testing of debug-independence in LiveRegUnits
Signed-off-by: John Lu <John.Lu at amd.com>
---
llvm/test/CodeGen/AArch64/machine-outliner-calls.mir | 1 +
llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir | 1 +
llvm/test/CodeGen/ARM/flag-crash.ll | 1 +
llvm/test/CodeGen/Thumb2/ldr-str-imm12.ll | 1 +
llvm/test/CodeGen/WebAssembly/simd-arith.ll | 1 +
5 files changed, 5 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-calls.mir b/llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
index 700a5b228122f..ea995b002e976 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=aarch64--- -run-pass=prologepilog -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64--- -run-pass=prologepilog -run-pass=machine-outliner -verify-machineinstrs %s -o - -debugify-and-strip-all-safe | FileCheck %s
# RUN: llc -mtriple=aarch64-pc-windows-msvc -run-pass=prologepilog -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=WINDOWS
--- |
define void @baz() #0 {
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
index 79486d56c55ca..c7dcfe1e5754a 100644
--- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=MUBUFW64,GFX7 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=prologepilog -debugify-and-strip-all-safe %s -o - | FileCheck -check-prefixes=MUBUFW64,GFX7 %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=MUBUFW64,GFX8 %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=MUBUFW64,GFX900 %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=MUBUFW64,GFX90A %s
diff --git a/llvm/test/CodeGen/ARM/flag-crash.ll b/llvm/test/CodeGen/ARM/flag-crash.ll
index 83a6b2470c51a..056f097fd17f8 100644
--- a/llvm/test/CodeGen/ARM/flag-crash.ll
+++ b/llvm/test/CodeGen/ARM/flag-crash.ll
@@ -1,4 +1,5 @@
; RUN: llc < %s -O3 -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 -relocation-model=pic
+; RUN: llc < %s -O3 -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 -relocation-model=pic -debugify-and-strip-all-safe
; PR7484
%struct.gs_matrix = type { float, i32, float, i32, float, i32, float, i32, float, i32, float, i32 }
diff --git a/llvm/test/CodeGen/Thumb2/ldr-str-imm12.ll b/llvm/test/CodeGen/Thumb2/ldr-str-imm12.ll
index 1d177b0a4ebbf..ce039cb1d5452 100644
--- a/llvm/test/CodeGen/Thumb2/ldr-str-imm12.ll
+++ b/llvm/test/CodeGen/Thumb2/ldr-str-imm12.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-atomic-cfg-tidy=0 -mcpu=cortex-a8 -relocation-model=pic -frame-pointer=all | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-atomic-cfg-tidy=0 -mcpu=cortex-a8 -relocation-model=pic -frame-pointer=all -debugify-and-strip-all-safe | FileCheck %s
; rdar://7352504
%0 = type { i16, i8, i8 }
diff --git a/llvm/test/CodeGen/WebAssembly/simd-arith.ll b/llvm/test/CodeGen/WebAssembly/simd-arith.ll
index cb06ee84ec99c..5fcbd2bee5861 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-arith.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-arith.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefix=SIMD128
+; RUN: llc < %s -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -debugify-and-strip-all-safe | FileCheck %s --check-prefix=SIMD128
; RUN: llc < %s -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel | FileCheck %s --check-prefix=SIMD128-FAST
; RUN: llc < %s -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefix=NO-SIMD128
; RUN: llc < %s -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -fast-isel | FileCheck %s --check-prefix=NO-SIMD128-FAST
>From 2de2b64663087139b876bd88f7c2ebefa3a718a5 Mon Sep 17 00:00:00 2001
From: John Lu <John.Lu at amd.com>
Date: Tue, 12 May 2026 08:48:37 -0500
Subject: [PATCH 6/8] Do not pass debug insns to stepBackward
Signed-off-by: John Lu <John.Lu at amd.com>
---
llvm/include/llvm/CodeGen/MachineOutliner.h | 3 ++-
llvm/lib/CodeGen/DeadMachineInstructionElim.cpp | 3 ++-
llvm/lib/CodeGen/LiveRegUnits.cpp | 5 ++---
llvm/lib/CodeGen/RegisterScavenging.cpp | 3 ++-
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 6 ++++--
llvm/lib/Target/SystemZ/SystemZShortenInst.cpp | 4 ++--
llvm/lib/Target/X86/X86FixupBWInsts.cpp | 3 ++-
7 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineOutliner.h b/llvm/include/llvm/CodeGen/MachineOutliner.h
index 66cab3d652104..2f38017f10274 100644
--- a/llvm/include/llvm/CodeGen/MachineOutliner.h
+++ b/llvm/include/llvm/CodeGen/MachineOutliner.h
@@ -89,7 +89,8 @@ struct Candidate {
// outlining candidate.
for (auto &MI : make_range(MBB->rbegin(),
(MachineBasicBlock::reverse_iterator)begin()))
- FromEndOfBlockToStartOfSeq.stepBackward(MI);
+ if (!MI.isDebugInstr())
+ FromEndOfBlockToStartOfSeq.stepBackward(MI);
}
/// Populate InSeq with liveness information.
diff --git a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
index 2c58b014d2399..938adc97db5ef 100644
--- a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
+++ b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
@@ -120,7 +120,8 @@ bool DeadMachineInstructionElimImpl::eliminateDeadMI(
++NumDeletes;
continue;
}
- LivePhysRegs.stepBackward(MI);
+ if (!MI.isDebugInstr())
+ LivePhysRegs.stepBackward(MI);
}
}
LivePhysRegs.clear();
diff --git a/llvm/lib/CodeGen/LiveRegUnits.cpp b/llvm/lib/CodeGen/LiveRegUnits.cpp
index c04c1404c29a5..6ff4ef1c95e41 100644
--- a/llvm/lib/CodeGen/LiveRegUnits.cpp
+++ b/llvm/lib/CodeGen/LiveRegUnits.cpp
@@ -42,9 +42,8 @@ void LiveRegUnits::addRegsInMask(const uint32_t *RegMask) {
}
void LiveRegUnits::stepBackward(const MachineInstr &MI) {
- // Do not let debug instructions affect liveness calculations.
- if (MI.isDebugInstr())
- return;
+ assert(!MI.isDebugInstr() &&
+ "Debug instructions must not affect liveness calculation");
// Remove defined registers and regmask kills from the set.
for (const MachineOperand &MOP : MI.operands()) {
diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp
index bcac08ba322a8..e7b8258cefb2b 100644
--- a/llvm/lib/CodeGen/RegisterScavenging.cpp
+++ b/llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -80,7 +80,8 @@ void RegScavenger::enterBasicBlockEnd(MachineBasicBlock &MBB) {
void RegScavenger::backward() {
const MachineInstr &MI = *--MBBI;
- LiveUnits.stepBackward(MI);
+ if (!MI.isDebugInstr())
+ LiveUnits.stepBackward(MI);
// Expire scavenge spill frameindex uses.
for (ScavengedInfo &I : Scavenged) {
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index c0a389f9b2d93..c7c9635031de1 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -10613,7 +10613,8 @@ AArch64InstrInfo::getOutlinableRanges(MachineBasicBlock &MBB,
// SKIP: <unsafe use>
auto FirstPossibleEndPt = MBB.instr_rbegin();
for (; FirstPossibleEndPt != MBB.instr_rend(); ++FirstPossibleEndPt) {
- LRU.stepBackward(*FirstPossibleEndPt);
+ if (!FirstPossibleEndPt->isDebugInstr())
+ LRU.stepBackward(*FirstPossibleEndPt);
// Update flags that impact how we outline across the entire block,
// regardless of safety.
UpdateWholeMBBFlags(*FirstPossibleEndPt);
@@ -10629,7 +10630,8 @@ AArch64InstrInfo::getOutlinableRanges(MachineBasicBlock &MBB,
// are dead (if there is any such point). Begin partitioning the MBB into
// ranges.
for (auto &MI : make_range(FirstPossibleEndPt, MBB.instr_rend())) {
- LRU.stepBackward(MI);
+ if (!MI.isDebugInstr())
+ LRU.stepBackward(MI);
UpdateWholeMBBFlags(MI);
if (!AreAllUnsafeRegsDead()) {
SaveRangeIfNonEmpty();
diff --git a/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp b/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
index 96a41487c87e3..991b2e45f1297 100644
--- a/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
@@ -373,8 +373,8 @@ bool SystemZShortenInst::processBlock(MachineBasicBlock &MBB) {
break;
}
}
-
- LiveRegs.stepBackward(MI);
+ if (!MI.isDebugInstr())
+ LiveRegs.stepBackward(MI);
}
return Changed;
diff --git a/llvm/lib/Target/X86/X86FixupBWInsts.cpp b/llvm/lib/Target/X86/X86FixupBWInsts.cpp
index ffe3510af61ac..18819efd35e27 100644
--- a/llvm/lib/Target/X86/X86FixupBWInsts.cpp
+++ b/llvm/lib/Target/X86/X86FixupBWInsts.cpp
@@ -459,7 +459,8 @@ void X86FixupBWInstImpl::processBasicBlock(MachineFunction &MF,
MIReplacements.push_back(std::make_pair(&MI, NewMI));
// We're done with this instruction, update liveness for the next one.
- LiveUnits.stepBackward(MI);
+ if (!MI.isDebugInstr())
+ LiveUnits.stepBackward(MI);
}
while (!MIReplacements.empty()) {
>From bf664af8999c0cebe945899b583f058d34ecc93e Mon Sep 17 00:00:00 2001
From: John Lu <John.Lu at amd.com>
Date: Tue, 12 May 2026 18:28:25 -0500
Subject: [PATCH 7/8] Change another call
Signed-off-by: John Lu <John.Lu at amd.com>
---
llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp b/llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp
index 98d531c9982a0..8888bf792b279 100644
--- a/llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp
+++ b/llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp
@@ -187,7 +187,8 @@ bool RemoveLoadsIntoFakeUses::run(MachineFunction &MF) {
RegFakeUses.erase(&FakeUse);
}
}
- LivePhysRegs.stepBackward(MI);
+ if (!MI.isDebugInstr())
+ LivePhysRegs.stepBackward(MI);
}
}
>From ca59e7d514275646e0083ef3671ba21b9a0bfbab Mon Sep 17 00:00:00 2001
From: John Lu <John.Lu at amd.com>
Date: Wed, 13 May 2026 07:00:53 -0500
Subject: [PATCH 8/8] Skip whole loop
Signed-off-by: John Lu <John.Lu at amd.com>
---
llvm/lib/CodeGen/DeadMachineInstructionElim.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
index 938adc97db5ef..67f924816e607 100644
--- a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
+++ b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
@@ -105,6 +105,8 @@ bool DeadMachineInstructionElimImpl::eliminateDeadMI(
// Now scan the instructions and delete dead ones, tracking physreg
// liveness as we go.
for (MachineInstr &MI : make_early_inc_range(reverse(*MBB))) {
+ if (MI.isDebugInstr())
+ continue;
// If the instruction is dead, delete it!
if (MI.isDead(*MRI, &LivePhysRegs)) {
if (MI.isPHI()) {
@@ -120,8 +122,7 @@ bool DeadMachineInstructionElimImpl::eliminateDeadMI(
++NumDeletes;
continue;
}
- if (!MI.isDebugInstr())
- LivePhysRegs.stepBackward(MI);
+ LivePhysRegs.stepBackward(MI);
}
}
LivePhysRegs.clear();
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