[llvm] [RISCV][P-ext] Support pabd(u).db/h. (PR #197332)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/197332

None

>From d9224ec4ed88021f0b6a8d72fb4644bb128f1a5a Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 12 May 2026 17:03:19 -0700
Subject: [PATCH] [RISCV][P-ext] Support pabd(u).db/h.

---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp |  2 ++
 llvm/lib/Target/RISCV/RISCVInstrInfoP.td    | 10 +++++++
 llvm/test/CodeGen/RISCV/rvp-simd-64.ll      | 30 +++++----------------
 3 files changed, 18 insertions(+), 24 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ac1ef084d1d24..650efc96c78d5 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -629,6 +629,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
       setOperationAction({ISD::AVGFLOORS, ISD::AVGFLOORU}, P64VecVTs, Legal);
       setOperationAction({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX},
                          P64VecVTs, Legal);
+      setOperationAction({ISD::ABS, ISD::ABDS, ISD::ABDU},
+                         {MVT::v4i16, MVT::v8i8}, Legal);
       setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Legal);
       setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal);
       setOperationAction(ISD::CONCAT_VECTORS, {MVT::v4i16, MVT::v8i8}, Legal);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 3f5508f5df4e8..fbdc7db8300d6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -2258,6 +2258,16 @@ let Predicates = [HasStdExtP, IsRV32] in {
   def : PatGprPairGprPair<riscv_asub, PASUB_DW, v2i32>;
   def : PatGprPairGprPair<riscv_asubu, PASUBU_DW, v2i32>;
 
+  // 8-bit absolute difference patterns
+  def : Pat<(v8i8 (abs GPRPair:$rs1)), (PABD_DB GPRPair:$rs1, (v8i8 X0_Pair))>;
+  def : PatGprPairGprPair<abds, PABD_DB, v8i8>;
+  def : PatGprPairGprPair<abdu, PABDU_DB, v8i8>;
+
+  // 16-bit absolute difference patterns
+  def : Pat<(v4i16 (abs GPRPair:$rs1)), (PABD_DH GPRPair:$rs1, (v4i16 X0_Pair))>;
+  def : PatGprPairGprPair<abds, PABD_DH, v4i16>;
+  def : PatGprPairGprPair<abdu, PABDU_DH, v4i16>;
+
   // [s|u]min/[s|u]max patterns
   def : PatGprPairGprPair<smin, PMIN_DB, v8i8>;
   def : PatGprPairGprPair<umin, PMINU_DB, v8i8>;
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
index 6c6ee5ebcf6a8..79d390f3b3867 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
@@ -1040,12 +1040,7 @@ define <2 x i32> @test_pabs_w(<2 x i32> %a) {
 define <4 x i16> @test_pabs_h(<4 x i16> %a) {
 ; RV32-LABEL: test_pabs_h:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    lui a2, %hi(.LCPI38_0)
-; RV32-NEXT:    lw a4, %lo(.LCPI38_0)(a2)
-; RV32-NEXT:    addi a2, a2, %lo(.LCPI38_0)
-; RV32-NEXT:    lw a5, 4(a2)
-; RV32-NEXT:    psub.dh a2, a4, a0
-; RV32-NEXT:    pmax.dh a0, a0, a2
+; RV32-NEXT:    pabs.dh a0, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_pabs_h:
@@ -1059,12 +1054,7 @@ define <4 x i16> @test_pabs_h(<4 x i16> %a) {
 define <8 x i8> @test_pabs_b(<8 x i8> %a) {
 ; RV32-LABEL: test_pabs_b:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    lui a2, %hi(.LCPI39_0)
-; RV32-NEXT:    lw a4, %lo(.LCPI39_0)(a2)
-; RV32-NEXT:    addi a2, a2, %lo(.LCPI39_0)
-; RV32-NEXT:    lw a5, 4(a2)
-; RV32-NEXT:    psub.db a2, a4, a0
-; RV32-NEXT:    pmax.db a0, a0, a2
+; RV32-NEXT:    pabs.db a0, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_pabs_b:
@@ -1124,9 +1114,7 @@ define <2 x i32> @test_pdifu_w(<2 x i32> %a, <2 x i32> %b) {
 define <4 x i16> @test_pdif_h(<4 x i16> %a, <4 x i16> %b) {
 ; RV32-LABEL: test_pdif_h:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    pmin.dh a4, a0, a2
-; RV32-NEXT:    pmax.dh a0, a0, a2
-; RV32-NEXT:    psub.dh a0, a0, a4
+; RV32-NEXT:    pabd.dh a0, a0, a2
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_pdif_h:
@@ -1144,9 +1132,7 @@ define <4 x i16> @test_pdif_h(<4 x i16> %a, <4 x i16> %b) {
 define <4 x i16> @test_pdifu_h(<4 x i16> %a, <4 x i16> %b) {
 ; RV32-LABEL: test_pdifu_h:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    pminu.dh a4, a0, a2
-; RV32-NEXT:    pmaxu.dh a0, a0, a2
-; RV32-NEXT:    psub.dh a0, a0, a4
+; RV32-NEXT:    pabdu.dh a0, a0, a2
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_pdifu_h:
@@ -1163,9 +1149,7 @@ define <4 x i16> @test_pdifu_h(<4 x i16> %a, <4 x i16> %b) {
 define <8 x i8> @test_pdif_b(<8 x i8> %a, <8 x i8> %b) {
 ; RV32-LABEL: test_pdif_b:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    pmin.db a4, a0, a2
-; RV32-NEXT:    pmax.db a0, a0, a2
-; RV32-NEXT:    psub.db a0, a0, a4
+; RV32-NEXT:    pabd.db a0, a0, a2
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_pdif_b:
@@ -1182,9 +1166,7 @@ define <8 x i8> @test_pdif_b(<8 x i8> %a, <8 x i8> %b) {
 define <8 x i8> @test_pdifu_b(<8 x i8> %a, <8 x i8> %b) {
 ; RV32-LABEL: test_pdifu_b:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    pminu.db a4, a0, a2
-; RV32-NEXT:    pmaxu.db a0, a0, a2
-; RV32-NEXT:    psub.db a0, a0, a4
+; RV32-NEXT:    pabdu.db a0, a0, a2
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_pdifu_b: