[llvm] 8bddd0f - [DAG] visitBITCAST - fold (conv (scalar_to_vector(load x))) -> (load (conv*)x) (#196978)

[via llvm-commits]

Author: Simon Pilgrim
Date: 2026-05-12T15:05:50Z
New Revision: 8bddd0f35f6b3d009a3e28160eb0e97a4ff5b5b5

URL: https://github.com/llvm/llvm-project/commit/8bddd0f35f6b3d009a3e28160eb0e97a4ff5b5b5
DIFF: https://github.com/llvm/llvm-project/commit/8bddd0f35f6b3d009a3e28160eb0e97a4ff5b5b5.diff

LOG: [DAG] visitBITCAST - fold (conv (scalar_to_vector(load x))) -> (load (conv*)x) (#196978)

Legalization can leave superfluous scalar_to_vector nodes with the
scalar bitwidth matching the vector bitwidth - peek through these when
attempting to bitcast folds

Only one match in trunk at the moment, but there are some additional
folds encountered in #149798

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/test/CodeGen/AArch64/neon-dotreduce.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 4d441b844ebdc..707043736ed3c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -17633,6 +17633,11 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {
   // fold (conv (freeze (load x))) -> (freeze (load (conv*)x))
   // If the resultant load doesn't need a higher alignment than the original!
   auto CastLoad = [this, &VT](SDValue N0, const SDLoc &DL) {
+    // Peek through scalar_to_vector if the scalar is same size as VT - often a
+    // leftover from legalization.
+    if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && N0.hasOneUse() &&
+        N0.getOperand(0).getValueSizeInBits() == VT.getSizeInBits())
+      N0 = N0.getOperand(0);
     if (N0.getOpcode() == ISD::AssertNoFPClass)
       N0 = N0.getOperand(0);
     if (!ISD::isNormalLoad(N0.getNode()) || !N0.hasOneUse())

diff  --git a/llvm/test/CodeGen/AArch64/neon-dotreduce.ll b/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
index 8854d8ab80798..ff9c75cfd0c5e 100644
--- a/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+++ b/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
@@ -445,9 +445,8 @@ entry:
 define i32 @test_udot_v5i8_nomla(ptr nocapture readonly %a1) {
 ; CHECK-SD-LABEL: test_udot_v5i8_nomla:
 ; CHECK-SD:       // %bb.0: // %entry
-; CHECK-SD-NEXT:    ldr x8, [x0]
+; CHECK-SD-NEXT:    ldr d0, [x0]
 ; CHECK-SD-NEXT:    movi v1.2d, #0000000000000000
-; CHECK-SD-NEXT:    fmov d0, x8
 ; CHECK-SD-NEXT:    ushll v0.8h, v0.8b, #0
 ; CHECK-SD-NEXT:    ushll2 v2.4s, v0.8h, #0
 ; CHECK-SD-NEXT:    mov v1.s[0], v2.s[0]