[llvm] c583e32 - [RISCV] Rename dota4 to dot4a (#196921)
via llvm-commits
llvm-commits at lists.llvm.org
Mon May 11 21:01:41 PDT 2026
Author: Pengcheng Wang
Date: 2026-05-12T12:01:35+08:00
New Revision: c583e3280ac3f9cd715f9c1d76c492cfd6c69bc2
URL: https://github.com/llvm/llvm-project/commit/c583e3280ac3f9cd715f9c1d76c492cfd6c69bc2
DIFF: https://github.com/llvm/llvm-project/commit/c583e3280ac3f9cd715f9c1d76c492cfd6c69bc2.diff
LOG: [RISCV] Rename dota4 to dot4a (#196921)
I don't know how this slipped our eyes...
Added:
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
llvm/test/CodeGen/RISCV/rvv/vdot4a.ll
llvm/test/CodeGen/RISCV/rvv/vdot4asu.ll
llvm/test/CodeGen/RISCV/rvv/vdot4au.ll
llvm/test/CodeGen/RISCV/rvv/vdot4aus.ll
Modified:
clang/include/clang/Basic/riscv_vector.td
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoZvdot4a8i.td
llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
llvm/test/CodeGen/RISCV/rvv/commutable-zvdot4a8i.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvdot4a8i.ll
llvm/test/CodeGen/RISCV/rvv/zvdot4a8i-sdnode.ll
llvm/test/MC/RISCV/rvv/zvdot4a8i-invalid.s
llvm/test/MC/RISCV/rvv/zvdot4a8i.s
llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
Removed:
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4u_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4u_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4us_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4u_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4u_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4us_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4u_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4u_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4us_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4u_vv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4u_vx.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4us_vx.c
llvm/test/CodeGen/RISCV/rvv/vdota4.ll
llvm/test/CodeGen/RISCV/rvv/vdota4su.ll
llvm/test/CodeGen/RISCV/rvv/vdota4u.ll
llvm/test/CodeGen/RISCV/rvv/vdota4us.ll
################################################################################
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 06b13dd5725f8..386290f8b4ba1 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2116,7 +2116,7 @@ let UnMaskedPolicyScheme = HasPolicyOperand, HasMasked = false in {
}
// Zvdot4a8i
-multiclass RVVVDOTA4QBuiltinSet<list<list<string>> suffixes_prototypes> {
+multiclass RVVVDOT4AQBuiltinSet<list<list<string>> suffixes_prototypes> {
let UnMaskedPolicyScheme = HasPolicyOperand,
HasMaskedOffOperand = false,
OverloadedName = NAME,
@@ -2128,16 +2128,16 @@ multiclass RVVVDOTA4QBuiltinSet<list<list<string>> suffixes_prototypes> {
// Only SEW=32 is defined for zvdot4a8i so far, and since inputs are in fact
// four 8-bit integer bundles, we use unsigned type to represent all of them
let RequiredFeatures = ["zvdot4a8i"] in {
- defm vdota4
- : RVVVDOTA4QBuiltinSet<[["vv", "v", "vvUvUv"],
+ defm vdot4a
+ : RVVVDOT4AQBuiltinSet<[["vv", "v", "vvUvUv"],
["vx", "v", "vvUvUe"]]>;
- defm vdota4u
- : RVVVDOTA4QBuiltinSet<[["vv", "Uv", "UvUvUvUv"],
+ defm vdot4au
+ : RVVVDOT4AQBuiltinSet<[["vv", "Uv", "UvUvUvUv"],
["vx", "Uv", "UvUvUvUe"]]>;
- defm vdota4su
- : RVVVDOTA4QBuiltinSet<[["vv", "v", "vvUvUv"],
+ defm vdot4asu
+ : RVVVDOT4AQBuiltinSet<[["vv", "v", "vvUvUv"],
["vx", "v", "vvUvUe"]]>;
- defm vdota4us : RVVVDOTA4QBuiltinSet<[["vx", "v", "vvUvUe"]]>;
+ defm vdot4aus : RVVVDOT4AQBuiltinSet<[["vx", "v", "vvUvUe"]]>;
}
// Zvzip
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
similarity index 74%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
index 22f9053ce4a18..d5c1a241dbd60 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
@@ -6,112 +6,112 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vv_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1,
+vint32mf2_t test_vdot4a_vv_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4_vv_i32mf2(vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32mf2(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vv_i32m1(vint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1,
+vint32m1_t test_vdot4a_vv_i32m1(vint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
- return __riscv_vdota4_vv_i32m1(vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m1(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vv_i32m2(vint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1,
+vint32m2_t test_vdot4a_vv_i32m2(vint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1,
size_t vl) {
- return __riscv_vdota4_vv_i32m2(vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m2(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vv_i32m4(vint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1,
+vint32m4_t test_vdot4a_vv_i32m4(vint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1,
size_t vl) {
- return __riscv_vdota4_vv_i32m4(vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m4(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vv_i32m8(vint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1,
+vint32m8_t test_vdot4a_vv_i32m8(vint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1,
size_t vl) {
- return __riscv_vdota4_vv_i32m8(vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m8(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vuint32mf2_t vs2,
+vint32mf2_t test_vdot4a_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vuint32mf2_t vs2,
vuint32mf2_t vs1, size_t vl) {
- return __riscv_vdota4_vv_i32mf2_m(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32mf2_m(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4a_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4_vv_i32m1_m(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m1_m(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4a_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4_vv_i32m2_m(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m2_m(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4a_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4_vv_i32m4_m(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m4_m(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4a_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4_vv_i32m8_m(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m8_m(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
similarity index 73%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
index 2045577d58ca1..be62f7fb1c644 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
@@ -6,112 +6,112 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vx_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2, uint32_t rs1,
+vint32mf2_t test_vdot4a_vx_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4_vx_i32mf2(vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32mf2(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vx_i32m1(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
+vint32m1_t test_vdot4a_vx_i32m1(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4_vx_i32m1(vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m1(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vx_i32m2(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
+vint32m2_t test_vdot4a_vx_i32m2(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4_vx_i32m2(vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m2(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vx_i32m4(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
+vint32m4_t test_vdot4a_vx_i32m4(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4_vx_i32m4(vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m4(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vx_i32m8(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
+vint32m8_t test_vdot4a_vx_i32m8(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4_vx_i32m8(vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m8(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vuint32mf2_t vs2,
+vint32mf2_t test_vdot4a_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vuint32mf2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32mf2_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32mf2_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4a_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32m1_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m1_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4a_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32m2_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m2_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4a_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32m4_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m4_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4a_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32m8_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m8_m(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
similarity index 74%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vv.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
index 21290663366ba..e710753329a86 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
@@ -6,113 +6,113 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vv_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2,
+vint32mf2_t test_vdot4asu_vv_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2,
vuint32mf2_t vs1, size_t vl) {
- return __riscv_vdota4su_vv_i32mf2(vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32mf2(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vv_i32m1(vint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1,
+vint32m1_t test_vdot4asu_vv_i32m1(vint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
- return __riscv_vdota4su_vv_i32m1(vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m1(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vv_i32m2(vint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1,
+vint32m2_t test_vdot4asu_vv_i32m2(vint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1,
size_t vl) {
- return __riscv_vdota4su_vv_i32m2(vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m2(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vv_i32m4(vint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1,
+vint32m4_t test_vdot4asu_vv_i32m4(vint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1,
size_t vl) {
- return __riscv_vdota4su_vv_i32m4(vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m4(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vv_i32m8(vint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1,
+vint32m8_t test_vdot4asu_vv_i32m8(vint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1,
size_t vl) {
- return __riscv_vdota4su_vv_i32m8(vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m8(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4asu_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4su_vv_i32mf2_m(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32mf2_m(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4asu_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4su_vv_i32m1_m(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m1_m(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4asu_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4su_vv_i32m2_m(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m2_m(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4asu_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4su_vv_i32m4_m(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m4_m(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4asu_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4su_vv_i32m8_m(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m8_m(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
similarity index 73%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
index fd0095f9eec4a..3f1eb899817d6 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
@@ -6,112 +6,112 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vx_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2, uint32_t rs1,
+vint32mf2_t test_vdot4asu_vx_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su_vx_i32mf2(vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32mf2(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vx_i32m1(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
+vint32m1_t test_vdot4asu_vx_i32m1(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su_vx_i32m1(vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m1(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vx_i32m2(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
+vint32m2_t test_vdot4asu_vx_i32m2(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su_vx_i32m2(vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m2(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vx_i32m4(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
+vint32m4_t test_vdot4asu_vx_i32m4(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su_vx_i32m4(vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m4(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vx_i32m8(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
+vint32m8_t test_vdot4asu_vx_i32m8(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su_vx_i32m8(vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m8(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4asu_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_vx_i32mf2_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32mf2_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4asu_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_vx_i32m1_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m1_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4asu_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_vx_i32m2_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m2_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4asu_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_vx_i32m4_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m4_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4asu_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_vx_i32m8_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m8_m(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4u_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
similarity index 74%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4u_vv.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
index e203e30252426..e91e9ded51131 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4u_vv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
@@ -6,113 +6,113 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vv_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2,
+vuint32mf2_t test_vdot4au_vv_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2,
vuint32mf2_t vs1, size_t vl) {
- return __riscv_vdota4u_vv_u32mf2(vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32mf2(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vv_u32m1(vuint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1,
+vuint32m1_t test_vdot4au_vv_u32m1(vuint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
- return __riscv_vdota4u_vv_u32m1(vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m1(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vv_u32m2(vuint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1,
+vuint32m2_t test_vdot4au_vv_u32m2(vuint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1,
size_t vl) {
- return __riscv_vdota4u_vv_u32m2(vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m2(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vv_u32m4(vuint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1,
+vuint32m4_t test_vdot4au_vv_u32m4(vuint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1,
size_t vl) {
- return __riscv_vdota4u_vv_u32m4(vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m4(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1,
+vuint32m8_t test_vdot4au_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1,
size_t vl) {
- return __riscv_vdota4u_vv_u32m8(vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m8(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vv_u32mf2_m(vbool64_t vm, vuint32mf2_t vd,
+vuint32mf2_t test_vdot4au_vv_u32mf2_m(vbool64_t vm, vuint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4u_vv_u32mf2_m(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32mf2_m(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vv_u32m1_m(vbool32_t vm, vuint32m1_t vd, vuint32m1_t vs2,
+vuint32m1_t test_vdot4au_vv_u32m1_m(vbool32_t vm, vuint32m1_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4u_vv_u32m1_m(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m1_m(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vv_u32m2_m(vbool16_t vm, vuint32m2_t vd, vuint32m2_t vs2,
+vuint32m2_t test_vdot4au_vv_u32m2_m(vbool16_t vm, vuint32m2_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4u_vv_u32m2_m(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m2_m(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vv_u32m4_m(vbool8_t vm, vuint32m4_t vd, vuint32m4_t vs2,
+vuint32m4_t test_vdot4au_vv_u32m4_m(vbool8_t vm, vuint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4u_vv_u32m4_m(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m4_m(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vv_u32m8_m(vbool4_t vm, vuint32m8_t vd, vuint32m8_t vs2,
+vuint32m8_t test_vdot4au_vv_u32m8_m(vbool4_t vm, vuint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4u_vv_u32m8_m(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m8_m(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4u_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
similarity index 73%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4u_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
index 44ec0e6ba7edb..d9cc4670f8349 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4u_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
@@ -6,112 +6,112 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vx_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2,
+vuint32mf2_t test_vdot4au_vx_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32mf2(vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32mf2(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vx_u32m1(vuint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
+vuint32m1_t test_vdot4au_vx_u32m1(vuint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4u_vx_u32m1(vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m1(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vx_u32m2(vuint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
+vuint32m2_t test_vdot4au_vx_u32m2(vuint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4u_vx_u32m2(vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m2(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vx_u32m4(vuint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
+vuint32m4_t test_vdot4au_vx_u32m4(vuint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4u_vx_u32m4(vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m4(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vx_u32m8(vuint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
+vuint32m8_t test_vdot4au_vx_u32m8(vuint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4u_vx_u32m8(vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m8(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vx_u32mf2_m(vbool64_t vm, vuint32mf2_t vd,
+vuint32mf2_t test_vdot4au_vx_u32mf2_m(vbool64_t vm, vuint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32mf2_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32mf2_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vx_u32m1_m(vbool32_t vm, vuint32m1_t vd, vuint32m1_t vs2,
+vuint32m1_t test_vdot4au_vx_u32m1_m(vbool32_t vm, vuint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32m1_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m1_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vx_u32m2_m(vbool16_t vm, vuint32m2_t vd, vuint32m2_t vs2,
+vuint32m2_t test_vdot4au_vx_u32m2_m(vbool16_t vm, vuint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32m2_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m2_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vx_u32m4_m(vbool8_t vm, vuint32m4_t vd, vuint32m4_t vs2,
+vuint32m4_t test_vdot4au_vx_u32m4_m(vbool8_t vm, vuint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32m4_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m4_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vx_u32m8_m(vbool4_t vm, vuint32m8_t vd, vuint32m8_t vs2,
+vuint32m8_t test_vdot4au_vx_u32m8_m(vbool4_t vm, vuint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32m8_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m8_m(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4us_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
similarity index 73%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4us_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
index 064ff0c459ccf..c7792c32b5347 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4us_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
@@ -6,112 +6,112 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4us_vx_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2,
+vint32mf2_t test_vdot4aus_vx_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_vx_i32mf2(vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32mf2(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4us_vx_i32m1(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
+vint32m1_t test_vdot4aus_vx_i32m1(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us_vx_i32m1(vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m1(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4us_vx_i32m2(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
+vint32m2_t test_vdot4aus_vx_i32m2(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us_vx_i32m2(vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m2(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4us_vx_i32m4(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
+vint32m4_t test_vdot4aus_vx_i32m4(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us_vx_i32m4(vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m4(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4us_vx_i32m8(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
+vint32m8_t test_vdot4aus_vx_i32m8(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us_vx_i32m8(vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m8(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4us_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4aus_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_vx_i32mf2_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32mf2_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4us_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4aus_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_vx_i32m1_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m1_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4us_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4aus_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_vx_i32m2_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m2_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4us_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4aus_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_vx_i32m4_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m4_m(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4us_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4aus_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_vx_i32m8_m(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m8_m(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
similarity index 75%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4_vv.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
index b3b41292c127d..c733e71512509 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4_vv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
@@ -6,112 +6,112 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vv_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1,
+vint32mf2_t test_vdot4a_vv_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4(vd, vs2, vs1, vl);
+ return __riscv_vdot4a(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vv_i32m1(vint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1,
+vint32m1_t test_vdot4a_vv_i32m1(vint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
- return __riscv_vdota4(vd, vs2, vs1, vl);
+ return __riscv_vdot4a(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vv_i32m2(vint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1,
+vint32m2_t test_vdot4a_vv_i32m2(vint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1,
size_t vl) {
- return __riscv_vdota4(vd, vs2, vs1, vl);
+ return __riscv_vdot4a(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vv_i32m4(vint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1,
+vint32m4_t test_vdot4a_vv_i32m4(vint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1,
size_t vl) {
- return __riscv_vdota4(vd, vs2, vs1, vl);
+ return __riscv_vdot4a(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vv_i32m8(vint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1,
+vint32m8_t test_vdot4a_vv_i32m8(vint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1,
size_t vl) {
- return __riscv_vdota4(vd, vs2, vs1, vl);
+ return __riscv_vdot4a(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vuint32mf2_t vs2,
+vint32mf2_t test_vdot4a_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vuint32mf2_t vs2,
vuint32mf2_t vs1, size_t vl) {
- return __riscv_vdota4(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4a_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4a_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4a_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4a_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
similarity index 74%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
index a050941275d1a..c197e75cd422d 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
@@ -6,112 +6,112 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vx_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2, uint32_t rs1,
+vint32mf2_t test_vdot4a_vx_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4(vd, vs2, rs1, vl);
+ return __riscv_vdot4a(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vx_i32m1(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
+vint32m1_t test_vdot4a_vx_i32m1(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4(vd, vs2, rs1, vl);
+ return __riscv_vdot4a(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vx_i32m2(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
+vint32m2_t test_vdot4a_vx_i32m2(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4(vd, vs2, rs1, vl);
+ return __riscv_vdot4a(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vx_i32m4(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
+vint32m4_t test_vdot4a_vx_i32m4(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4(vd, vs2, rs1, vl);
+ return __riscv_vdot4a(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vx_i32m8(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
+vint32m8_t test_vdot4a_vx_i32m8(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4(vd, vs2, rs1, vl);
+ return __riscv_vdot4a(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vuint32mf2_t vs2,
+vint32mf2_t test_vdot4a_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vuint32mf2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4a_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4a_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4a_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4a_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
similarity index 75%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vv.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
index 095c7254df378..e6f15424ce213 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
@@ -6,113 +6,113 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vv_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2,
+vint32mf2_t test_vdot4asu_vv_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2,
vuint32mf2_t vs1, size_t vl) {
- return __riscv_vdota4su(vd, vs2, vs1, vl);
+ return __riscv_vdot4asu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vv_i32m1(vint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1,
+vint32m1_t test_vdot4asu_vv_i32m1(vint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
- return __riscv_vdota4su(vd, vs2, vs1, vl);
+ return __riscv_vdot4asu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vv_i32m2(vint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1,
+vint32m2_t test_vdot4asu_vv_i32m2(vint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1,
size_t vl) {
- return __riscv_vdota4su(vd, vs2, vs1, vl);
+ return __riscv_vdot4asu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vv_i32m4(vint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1,
+vint32m4_t test_vdot4asu_vv_i32m4(vint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1,
size_t vl) {
- return __riscv_vdota4su(vd, vs2, vs1, vl);
+ return __riscv_vdot4asu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vv_i32m8(vint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1,
+vint32m8_t test_vdot4asu_vv_i32m8(vint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1,
size_t vl) {
- return __riscv_vdota4su(vd, vs2, vs1, vl);
+ return __riscv_vdot4asu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4asu_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4su(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4asu_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4su(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4asu_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4su(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4asu_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4su(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4asu_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4su(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
similarity index 74%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
index a96cd01b3737e..93fb2741dac2a 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
@@ -6,112 +6,112 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vx_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2, uint32_t rs1,
+vint32mf2_t test_vdot4asu_vx_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su(vd, vs2, rs1, vl);
+ return __riscv_vdot4asu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vx_i32m1(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
+vint32m1_t test_vdot4asu_vx_i32m1(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su(vd, vs2, rs1, vl);
+ return __riscv_vdot4asu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vx_i32m2(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
+vint32m2_t test_vdot4asu_vx_i32m2(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su(vd, vs2, rs1, vl);
+ return __riscv_vdot4asu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vx_i32m4(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
+vint32m4_t test_vdot4asu_vx_i32m4(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su(vd, vs2, rs1, vl);
+ return __riscv_vdot4asu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vx_i32m8(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
+vint32m8_t test_vdot4asu_vx_i32m8(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su(vd, vs2, rs1, vl);
+ return __riscv_vdot4asu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4asu_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4su(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4asu_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4asu_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4asu_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4asu_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4u_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
similarity index 75%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4u_vv.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
index ccaa68c5bb298..c3fe9aa77ee9c 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4u_vv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
@@ -6,113 +6,113 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vv_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2,
+vuint32mf2_t test_vdot4au_vv_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2,
vuint32mf2_t vs1, size_t vl) {
- return __riscv_vdota4u(vd, vs2, vs1, vl);
+ return __riscv_vdot4au(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vv_u32m1(vuint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1,
+vuint32m1_t test_vdot4au_vv_u32m1(vuint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
- return __riscv_vdota4u(vd, vs2, vs1, vl);
+ return __riscv_vdot4au(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vv_u32m2(vuint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1,
+vuint32m2_t test_vdot4au_vv_u32m2(vuint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1,
size_t vl) {
- return __riscv_vdota4u(vd, vs2, vs1, vl);
+ return __riscv_vdot4au(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vv_u32m4(vuint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1,
+vuint32m4_t test_vdot4au_vv_u32m4(vuint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1,
size_t vl) {
- return __riscv_vdota4u(vd, vs2, vs1, vl);
+ return __riscv_vdot4au(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1,
+vuint32m8_t test_vdot4au_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1,
size_t vl) {
- return __riscv_vdota4u(vd, vs2, vs1, vl);
+ return __riscv_vdot4au(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vv_u32mf2_m(vbool64_t vm, vuint32mf2_t vd,
+vuint32mf2_t test_vdot4au_vv_u32mf2_m(vbool64_t vm, vuint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4u(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vv_u32m1_m(vbool32_t vm, vuint32m1_t vd, vuint32m1_t vs2,
+vuint32m1_t test_vdot4au_vv_u32m1_m(vbool32_t vm, vuint32m1_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4u(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vv_u32m2_m(vbool16_t vm, vuint32m2_t vd, vuint32m2_t vs2,
+vuint32m2_t test_vdot4au_vv_u32m2_m(vbool16_t vm, vuint32m2_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4u(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vv_u32m4_m(vbool8_t vm, vuint32m4_t vd, vuint32m4_t vs2,
+vuint32m4_t test_vdot4au_vv_u32m4_m(vbool8_t vm, vuint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4u(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vv_u32m8_m(vbool4_t vm, vuint32m8_t vd, vuint32m8_t vs2,
+vuint32m8_t test_vdot4au_vv_u32m8_m(vbool4_t vm, vuint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4u(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4u_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
similarity index 74%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4u_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
index a6ba47aec9c29..643002fa4e067 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4u_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
@@ -6,112 +6,112 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vx_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2,
+vuint32mf2_t test_vdot4au_vx_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u(vd, vs2, rs1, vl);
+ return __riscv_vdot4au(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vx_u32m1(vuint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
+vuint32m1_t test_vdot4au_vx_u32m1(vuint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4u(vd, vs2, rs1, vl);
+ return __riscv_vdot4au(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vx_u32m2(vuint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
+vuint32m2_t test_vdot4au_vx_u32m2(vuint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4u(vd, vs2, rs1, vl);
+ return __riscv_vdot4au(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vx_u32m4(vuint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
+vuint32m4_t test_vdot4au_vx_u32m4(vuint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4u(vd, vs2, rs1, vl);
+ return __riscv_vdot4au(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vx_u32m8(vuint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
+vuint32m8_t test_vdot4au_vx_u32m8(vuint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4u(vd, vs2, rs1, vl);
+ return __riscv_vdot4au(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vx_u32mf2_m(vbool64_t vm, vuint32mf2_t vd,
+vuint32mf2_t test_vdot4au_vx_u32mf2_m(vbool64_t vm, vuint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vx_u32m1_m(vbool32_t vm, vuint32m1_t vd, vuint32m1_t vs2,
+vuint32m1_t test_vdot4au_vx_u32m1_m(vbool32_t vm, vuint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vx_u32m2_m(vbool16_t vm, vuint32m2_t vd, vuint32m2_t vs2,
+vuint32m2_t test_vdot4au_vx_u32m2_m(vbool16_t vm, vuint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vx_u32m4_m(vbool8_t vm, vuint32m4_t vd, vuint32m4_t vs2,
+vuint32m4_t test_vdot4au_vx_u32m4_m(vbool8_t vm, vuint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vx_u32m8_m(vbool4_t vm, vuint32m8_t vd, vuint32m8_t vs2,
+vuint32m8_t test_vdot4au_vx_u32m8_m(vbool4_t vm, vuint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4us_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
similarity index 74%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4us_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
index 4c87bc2372a69..067a4bea18212 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4us_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
@@ -6,112 +6,112 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4us_vx_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2,
+vint32mf2_t test_vdot4aus_vx_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us(vd, vs2, rs1, vl);
+ return __riscv_vdot4aus(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4us_vx_i32m1(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
+vint32m1_t test_vdot4aus_vx_i32m1(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us(vd, vs2, rs1, vl);
+ return __riscv_vdot4aus(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4us_vx_i32m2(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
+vint32m2_t test_vdot4aus_vx_i32m2(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us(vd, vs2, rs1, vl);
+ return __riscv_vdot4aus(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4us_vx_i32m4(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
+vint32m4_t test_vdot4aus_vx_i32m4(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us(vd, vs2, rs1, vl);
+ return __riscv_vdot4aus(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4us_vx_i32m8(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
+vint32m8_t test_vdot4aus_vx_i32m8(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us(vd, vs2, rs1, vl);
+ return __riscv_vdot4aus(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_m(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4us_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4aus_vx_i32mf2_m(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4us(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_m(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4us_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4aus_vx_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_m(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4us_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4aus_vx_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4_m(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4us_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4aus_vx_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8_m(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8_m(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4us_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4aus_vx_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
similarity index 74%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4_vv.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
index 753087c6ca811..4bdb1179fa373 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4_vv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
@@ -6,224 +6,224 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vv_i32mf2_tu(vint32mf2_t vd, vuint32mf2_t vs2,
+vint32mf2_t test_vdot4a_vv_i32mf2_tu(vint32mf2_t vd, vuint32mf2_t vs2,
vuint32mf2_t vs1, size_t vl) {
- return __riscv_vdota4_vv_i32mf2_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32mf2_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vv_i32m1_tu(vint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1,
+vint32m1_t test_vdot4a_vv_i32m1_tu(vint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
- return __riscv_vdota4_vv_i32m1_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m1_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vv_i32m2_tu(vint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1,
+vint32m2_t test_vdot4a_vv_i32m2_tu(vint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1,
size_t vl) {
- return __riscv_vdota4_vv_i32m2_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m2_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vv_i32m4_tu(vint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1,
+vint32m4_t test_vdot4a_vv_i32m4_tu(vint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1,
size_t vl) {
- return __riscv_vdota4_vv_i32m4_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m4_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vv_i32m8_tu(vint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1,
+vint32m8_t test_vdot4a_vv_i32m8_tu(vint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1,
size_t vl) {
- return __riscv_vdota4_vv_i32m8_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m8_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vv_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4a_vv_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4_vv_i32mf2_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32mf2_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vv_i32m1_tum(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4a_vv_i32m1_tum(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4_vv_i32m1_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m1_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vv_i32m2_tum(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4a_vv_i32m2_tum(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4_vv_i32m2_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m2_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vv_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4a_vv_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4_vv_i32m4_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m4_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vv_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4a_vv_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4_vv_i32m8_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m8_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vv_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4a_vv_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4_vv_i32mf2_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32mf2_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vv_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4a_vv_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4_vv_i32m1_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m1_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vv_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4a_vv_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4_vv_i32m2_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m2_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vv_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4a_vv_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4_vv_i32m4_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m4_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vv_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4a_vv_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4_vv_i32m8_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m8_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vv_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4a_vv_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) {
- return __riscv_vdota4_vv_i32mf2_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32mf2_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vv_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4a_vv_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4_vv_i32m1_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m1_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vv_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4a_vv_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4_vv_i32m2_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m2_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vv_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4a_vv_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4_vv_i32m4_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m4_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vv_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4a_vv_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4_vv_i32m8_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_vv_i32m8_mu(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
similarity index 73%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
index 3d9e954e1d067..fabf45616d570 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
@@ -6,222 +6,222 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vx_i32mf2_tu(vint32mf2_t vd, vuint32mf2_t vs2,
+vint32mf2_t test_vdot4a_vx_i32mf2_tu(vint32mf2_t vd, vuint32mf2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32mf2_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32mf2_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vx_i32m1_tu(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
+vint32m1_t test_vdot4a_vx_i32m1_tu(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4_vx_i32m1_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m1_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vx_i32m2_tu(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
+vint32m2_t test_vdot4a_vx_i32m2_tu(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4_vx_i32m2_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m2_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vx_i32m4_tu(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
+vint32m4_t test_vdot4a_vx_i32m4_tu(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4_vx_i32m4_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m4_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vx_i32m8_tu(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
+vint32m8_t test_vdot4a_vx_i32m8_tu(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4_vx_i32m8_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m8_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4a_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32mf2_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32mf2_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4a_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32m1_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m1_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4a_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32m2_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m2_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4a_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32m4_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m4_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4a_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32m8_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m8_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4a_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32mf2_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32mf2_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4a_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32m1_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m1_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4a_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32m2_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m2_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4a_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32m4_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m4_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4a_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32m8_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m8_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4a_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32mf2_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32mf2_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4a_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32m1_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m1_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4a_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32m2_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m2_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4a_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32m4_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m4_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4a_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_vx_i32m8_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_vx_i32m8_mu(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
similarity index 74%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vv.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
index 9d643edf7b7ed..36e3185d032bc 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
@@ -6,227 +6,227 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vv_i32mf2_tu(vint32mf2_t vd, vuint32mf2_t vs2,
+vint32mf2_t test_vdot4asu_vv_i32mf2_tu(vint32mf2_t vd, vuint32mf2_t vs2,
vuint32mf2_t vs1, size_t vl) {
- return __riscv_vdota4su_vv_i32mf2_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32mf2_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vv_i32m1_tu(vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4asu_vv_i32m1_tu(vint32m1_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4su_vv_i32m1_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m1_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vv_i32m2_tu(vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4asu_vv_i32m2_tu(vint32m2_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4su_vv_i32m2_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m2_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vv_i32m4_tu(vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4asu_vv_i32m4_tu(vint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4su_vv_i32m4_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m4_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vv_i32m8_tu(vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4asu_vv_i32m8_tu(vint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4su_vv_i32m8_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m8_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vv_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4asu_vv_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4su_vv_i32mf2_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32mf2_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vv_i32m1_tum(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4asu_vv_i32m1_tum(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4su_vv_i32m1_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m1_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vv_i32m2_tum(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4asu_vv_i32m2_tum(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4su_vv_i32m2_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m2_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vv_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4asu_vv_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4su_vv_i32m4_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m4_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vv_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4asu_vv_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4su_vv_i32m8_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m8_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vv_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4asu_vv_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4su_vv_i32mf2_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32mf2_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vv_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
+vint32m1_t test_vdot4asu_vv_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
- return __riscv_vdota4su_vv_i32m1_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m1_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vv_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
+vint32m2_t test_vdot4asu_vv_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
vuint32m2_t vs2, vuint32m2_t vs1,
size_t vl) {
- return __riscv_vdota4su_vv_i32m2_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m2_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vv_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4asu_vv_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4su_vv_i32m4_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m4_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vv_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4asu_vv_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4su_vv_i32m8_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m8_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vv_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4asu_vv_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4su_vv_i32mf2_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32mf2_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vv_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4asu_vv_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4su_vv_i32m1_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m1_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vv_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4asu_vv_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4su_vv_i32m2_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m2_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vv_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4asu_vv_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4su_vv_i32m4_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m4_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vv_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4asu_vv_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4su_vv_i32m8_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_vv_i32m8_mu(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
similarity index 73%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
index 74f5cfc73cab7..e437161ff1207 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
@@ -6,224 +6,224 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vx_i32mf2_tu(vint32mf2_t vd, vuint32mf2_t vs2,
+vint32mf2_t test_vdot4asu_vx_i32mf2_tu(vint32mf2_t vd, vuint32mf2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_vx_i32mf2_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32mf2_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vx_i32m1_tu(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
+vint32m1_t test_vdot4asu_vx_i32m1_tu(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su_vx_i32m1_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m1_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vx_i32m2_tu(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
+vint32m2_t test_vdot4asu_vx_i32m2_tu(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su_vx_i32m2_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m2_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vx_i32m4_tu(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
+vint32m4_t test_vdot4asu_vx_i32m4_tu(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su_vx_i32m4_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m4_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vx_i32m8_tu(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
+vint32m8_t test_vdot4asu_vx_i32m8_tu(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su_vx_i32m8_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m8_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4asu_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su_vx_i32mf2_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32mf2_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4asu_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_vx_i32m1_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m1_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4asu_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_vx_i32m2_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m2_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4asu_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_vx_i32m4_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m4_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4asu_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_vx_i32m8_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m8_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4asu_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su_vx_i32mf2_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32mf2_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
+vint32m1_t test_vdot4asu_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
vuint32m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_vx_i32m1_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m1_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
+vint32m2_t test_vdot4asu_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
vuint32m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_vx_i32m2_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m2_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4asu_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_vx_i32m4_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m4_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4asu_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_vx_i32m8_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m8_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4asu_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_vx_i32mf2_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32mf2_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4asu_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_vx_i32m1_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m1_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4asu_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_vx_i32m2_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m2_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4asu_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_vx_i32m4_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m4_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4asu_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_vx_i32m8_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_vx_i32m8_mu(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4u_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
similarity index 74%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4u_vv.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
index 59177c74ba70d..d018c57305618 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4u_vv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
@@ -6,233 +6,233 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vv_u32mf2_tu(vuint32mf2_t vd, vuint32mf2_t vs2,
+vuint32mf2_t test_vdot4au_vv_u32mf2_tu(vuint32mf2_t vd, vuint32mf2_t vs2,
vuint32mf2_t vs1, size_t vl) {
- return __riscv_vdota4u_vv_u32mf2_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32mf2_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vv_u32m1_tu(vuint32m1_t vd, vuint32m1_t vs2,
+vuint32m1_t test_vdot4au_vv_u32m1_tu(vuint32m1_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4u_vv_u32m1_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m1_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vv_u32m2_tu(vuint32m2_t vd, vuint32m2_t vs2,
+vuint32m2_t test_vdot4au_vv_u32m2_tu(vuint32m2_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4u_vv_u32m2_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m2_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vv_u32m4_tu(vuint32m4_t vd, vuint32m4_t vs2,
+vuint32m4_t test_vdot4au_vv_u32m4_tu(vuint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4u_vv_u32m4_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m4_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2,
+vuint32m8_t test_vdot4au_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4u_vv_u32m8_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m8_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vv_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,
+vuint32mf2_t test_vdot4au_vv_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4u_vv_u32mf2_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32mf2_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vv_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
+vuint32m1_t test_vdot4au_vv_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
- return __riscv_vdota4u_vv_u32m1_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m1_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vv_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
+vuint32m2_t test_vdot4au_vv_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
vuint32m2_t vs2, vuint32m2_t vs1,
size_t vl) {
- return __riscv_vdota4u_vv_u32m2_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m2_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vv_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
+vuint32m4_t test_vdot4au_vv_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
vuint32m4_t vs2, vuint32m4_t vs1,
size_t vl) {
- return __riscv_vdota4u_vv_u32m4_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m4_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vv_u32m8_tum(vbool4_t vm, vuint32m8_t vd,
+vuint32m8_t test_vdot4au_vv_u32m8_tum(vbool4_t vm, vuint32m8_t vd,
vuint32m8_t vs2, vuint32m8_t vs1,
size_t vl) {
- return __riscv_vdota4u_vv_u32m8_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m8_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vv_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,
+vuint32mf2_t test_vdot4au_vv_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4u_vv_u32mf2_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32mf2_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vv_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
+vuint32m1_t test_vdot4au_vv_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
- return __riscv_vdota4u_vv_u32m1_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m1_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vv_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
+vuint32m2_t test_vdot4au_vv_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
vuint32m2_t vs2, vuint32m2_t vs1,
size_t vl) {
- return __riscv_vdota4u_vv_u32m2_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m2_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vv_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
+vuint32m4_t test_vdot4au_vv_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
vuint32m4_t vs2, vuint32m4_t vs1,
size_t vl) {
- return __riscv_vdota4u_vv_u32m4_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m4_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vv_u32m8_tumu(vbool4_t vm, vuint32m8_t vd,
+vuint32m8_t test_vdot4au_vv_u32m8_tumu(vbool4_t vm, vuint32m8_t vd,
vuint32m8_t vs2, vuint32m8_t vs1,
size_t vl) {
- return __riscv_vdota4u_vv_u32m8_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m8_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vv_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,
+vuint32mf2_t test_vdot4au_vv_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4u_vv_u32mf2_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32mf2_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vv_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
+vuint32m1_t test_vdot4au_vv_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4u_vv_u32m1_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m1_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vv_u32m2_mu(vbool16_t vm, vuint32m2_t vd,
+vuint32m2_t test_vdot4au_vv_u32m2_mu(vbool16_t vm, vuint32m2_t vd,
vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4u_vv_u32m2_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m2_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vv_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint32m4_t vs2,
+vuint32m4_t test_vdot4au_vv_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4u_vv_u32m4_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m4_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vv_u32m8_mu(vbool4_t vm, vuint32m8_t vd, vuint32m8_t vs2,
+vuint32m8_t test_vdot4au_vv_u32m8_mu(vbool4_t vm, vuint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4u_vv_u32m8_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_vv_u32m8_mu(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4u_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
similarity index 73%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4u_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
index 9068dcb39218d..d33ab1b6585b5 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4u_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
@@ -6,225 +6,225 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vx_u32mf2_tu(vuint32mf2_t vd, vuint32mf2_t vs2,
+vuint32mf2_t test_vdot4au_vx_u32mf2_tu(vuint32mf2_t vd, vuint32mf2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32mf2_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32mf2_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vx_u32m1_tu(vuint32m1_t vd, vuint32m1_t vs2,
+vuint32m1_t test_vdot4au_vx_u32m1_tu(vuint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32m1_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m1_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vx_u32m2_tu(vuint32m2_t vd, vuint32m2_t vs2,
+vuint32m2_t test_vdot4au_vx_u32m2_tu(vuint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32m2_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m2_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vx_u32m4_tu(vuint32m4_t vd, vuint32m4_t vs2,
+vuint32m4_t test_vdot4au_vx_u32m4_tu(vuint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32m4_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m4_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vx_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2,
+vuint32m8_t test_vdot4au_vx_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32m8_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m8_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vx_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,
+vuint32mf2_t test_vdot4au_vx_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4u_vx_u32mf2_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32mf2_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vx_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
+vuint32m1_t test_vdot4au_vx_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
vuint32m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32m1_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m1_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vx_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
+vuint32m2_t test_vdot4au_vx_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
vuint32m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32m2_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m2_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vx_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
+vuint32m4_t test_vdot4au_vx_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
vuint32m4_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32m4_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m4_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vx_u32m8_tum(vbool4_t vm, vuint32m8_t vd,
+vuint32m8_t test_vdot4au_vx_u32m8_tum(vbool4_t vm, vuint32m8_t vd,
vuint32m8_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32m8_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m8_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vx_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,
+vuint32mf2_t test_vdot4au_vx_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4u_vx_u32mf2_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32mf2_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vx_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
+vuint32m1_t test_vdot4au_vx_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
vuint32m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32m1_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m1_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vx_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
+vuint32m2_t test_vdot4au_vx_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
vuint32m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32m2_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m2_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vx_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
+vuint32m4_t test_vdot4au_vx_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
vuint32m4_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32m4_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m4_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vx_u32m8_tumu(vbool4_t vm, vuint32m8_t vd,
+vuint32m8_t test_vdot4au_vx_u32m8_tumu(vbool4_t vm, vuint32m8_t vd,
vuint32m8_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32m8_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m8_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vx_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,
+vuint32mf2_t test_vdot4au_vx_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4u_vx_u32mf2_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32mf2_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vx_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
+vuint32m1_t test_vdot4au_vx_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
vuint32m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32m1_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m1_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vx_u32m2_mu(vbool16_t vm, vuint32m2_t vd,
+vuint32m2_t test_vdot4au_vx_u32m2_mu(vbool16_t vm, vuint32m2_t vd,
vuint32m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32m2_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m2_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vx_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint32m4_t vs2,
+vuint32m4_t test_vdot4au_vx_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32m4_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m4_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vx_u32m8_mu(vbool4_t vm, vuint32m8_t vd, vuint32m8_t vs2,
+vuint32m8_t test_vdot4au_vx_u32m8_mu(vbool4_t vm, vuint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_vx_u32m8_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_vx_u32m8_mu(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4us_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
similarity index 73%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4us_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
index 01da3b8e04d67..56c58cb790352 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4us_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
@@ -6,225 +6,225 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4us_vx_i32mf2_tu(vint32mf2_t vd, vuint32mf2_t vs2,
+vint32mf2_t test_vdot4aus_vx_i32mf2_tu(vint32mf2_t vd, vuint32mf2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_vx_i32mf2_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32mf2_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4us_vx_i32m1_tu(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
+vint32m1_t test_vdot4aus_vx_i32m1_tu(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us_vx_i32m1_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m1_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4us_vx_i32m2_tu(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
+vint32m2_t test_vdot4aus_vx_i32m2_tu(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us_vx_i32m2_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m2_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4us_vx_i32m4_tu(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
+vint32m4_t test_vdot4aus_vx_i32m4_tu(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us_vx_i32m4_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m4_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4us_vx_i32m8_tu(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
+vint32m8_t test_vdot4aus_vx_i32m8_tu(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us_vx_i32m8_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m8_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4us_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4aus_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us_vx_i32mf2_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32mf2_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4us_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd,
+vint32m1_t test_vdot4aus_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd,
vuint32m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_vx_i32m1_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m1_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4us_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd,
+vint32m2_t test_vdot4aus_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd,
vuint32m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_vx_i32m2_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m2_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4us_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4aus_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_vx_i32m4_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m4_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4us_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4aus_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_vx_i32m8_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m8_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4us_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4aus_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us_vx_i32mf2_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32mf2_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4us_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
+vint32m1_t test_vdot4aus_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
vuint32m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_vx_i32m1_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m1_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4us_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
+vint32m2_t test_vdot4aus_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
vuint32m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_vx_i32m2_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m2_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4us_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd,
+vint32m4_t test_vdot4aus_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd,
vuint32m4_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_vx_i32m4_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m4_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4us_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd,
+vint32m8_t test_vdot4aus_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd,
vuint32m8_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_vx_i32m8_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m8_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4us_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4aus_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us_vx_i32mf2_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32mf2_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4us_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4aus_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_vx_i32m1_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m1_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4us_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4aus_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_vx_i32m2_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m2_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4us_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4aus_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_vx_i32m4_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m4_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4us_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4aus_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_vx_i32m8_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_vx_i32m8_mu(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
similarity index 75%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4_vv.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
index fa14df5d58c95..06e15986b5f9d 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4_vv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
@@ -6,224 +6,224 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vv_i32mf2_tu(vint32mf2_t vd, vuint32mf2_t vs2,
+vint32mf2_t test_vdot4a_vv_i32mf2_tu(vint32mf2_t vd, vuint32mf2_t vs2,
vuint32mf2_t vs1, size_t vl) {
- return __riscv_vdota4_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4a_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vv_i32m1_tu(vint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1,
+vint32m1_t test_vdot4a_vv_i32m1_tu(vint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
- return __riscv_vdota4_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4a_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vv_i32m2_tu(vint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1,
+vint32m2_t test_vdot4a_vv_i32m2_tu(vint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1,
size_t vl) {
- return __riscv_vdota4_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4a_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vv_i32m4_tu(vint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1,
+vint32m4_t test_vdot4a_vv_i32m4_tu(vint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1,
size_t vl) {
- return __riscv_vdota4_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4a_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vv_i32m8_tu(vint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1,
+vint32m8_t test_vdot4a_vv_i32m8_tu(vint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1,
size_t vl) {
- return __riscv_vdota4_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4a_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vv_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4a_vv_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vv_i32m1_tum(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4a_vv_i32m1_tum(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vv_i32m2_tum(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4a_vv_i32m2_tum(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vv_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4a_vv_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vv_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4a_vv_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vv_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4a_vv_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vv_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4a_vv_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vv_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4a_vv_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vv_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4a_vv_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vv_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4a_vv_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vv_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4a_vv_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) {
- return __riscv_vdota4_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vv_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4a_vv_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vv_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4a_vv_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vv_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4a_vv_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vv_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4a_vv_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4a_mu(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
similarity index 74%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
index b78992c17e909..bde5c14377a60 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
@@ -6,222 +6,222 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vx_i32mf2_tu(vint32mf2_t vd, vuint32mf2_t vs2,
+vint32mf2_t test_vdot4a_vx_i32mf2_tu(vint32mf2_t vd, vuint32mf2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4a_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vx_i32m1_tu(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
+vint32m1_t test_vdot4a_vx_i32m1_tu(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4a_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vx_i32m2_tu(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
+vint32m2_t test_vdot4a_vx_i32m2_tu(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4a_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vx_i32m4_tu(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
+vint32m4_t test_vdot4a_vx_i32m4_tu(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4a_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vx_i32m8_tu(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
+vint32m8_t test_vdot4a_vx_i32m8_tu(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4a_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4a_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4a_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4a_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4a_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4a_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4a_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4a_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4a_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4a_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4a_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4a_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4a_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4a_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4a_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4a_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4a_mu(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
similarity index 75%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vv.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
index effe5a58c0efa..af485557b88b4 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
@@ -6,227 +6,227 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vv_i32mf2_tu(vint32mf2_t vd, vuint32mf2_t vs2,
+vint32mf2_t test_vdot4asu_vv_i32mf2_tu(vint32mf2_t vd, vuint32mf2_t vs2,
vuint32mf2_t vs1, size_t vl) {
- return __riscv_vdota4su_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vv_i32m1_tu(vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4asu_vv_i32m1_tu(vint32m1_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4su_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vv_i32m2_tu(vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4asu_vv_i32m2_tu(vint32m2_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4su_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vv_i32m4_tu(vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4asu_vv_i32m4_tu(vint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4su_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vv_i32m8_tu(vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4asu_vv_i32m8_tu(vint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4su_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vv_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4asu_vv_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4su_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vv_i32m1_tum(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4asu_vv_i32m1_tum(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4su_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vv_i32m2_tum(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4asu_vv_i32m2_tum(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4su_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vv_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4asu_vv_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4su_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vv_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4asu_vv_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4su_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vv_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4asu_vv_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4su_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vv_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
+vint32m1_t test_vdot4asu_vv_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
- return __riscv_vdota4su_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vv_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
+vint32m2_t test_vdot4asu_vv_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
vuint32m2_t vs2, vuint32m2_t vs1,
size_t vl) {
- return __riscv_vdota4su_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vv_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4asu_vv_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4su_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vv_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4asu_vv_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4su_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vv_i32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vv_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4asu_vv_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4su_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vv_i32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vv_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4asu_vv_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4su_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vv_i32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vv_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4asu_vv_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4su_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vv_i32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vv_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4asu_vv_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4su_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vv_i32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vv_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4asu_vv_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4su_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4asu_mu(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
similarity index 74%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
index 6cb2462283e9e..2323083af8c7f 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
@@ -6,224 +6,224 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vx_i32mf2_tu(vint32mf2_t vd, vuint32mf2_t vs2,
+vint32mf2_t test_vdot4asu_vx_i32mf2_tu(vint32mf2_t vd, vuint32mf2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vx_i32m1_tu(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
+vint32m1_t test_vdot4asu_vx_i32m1_tu(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vx_i32m2_tu(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
+vint32m2_t test_vdot4asu_vx_i32m2_tu(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vx_i32m4_tu(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
+vint32m4_t test_vdot4asu_vx_i32m4_tu(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vx_i32m8_tu(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
+vint32m8_t test_vdot4asu_vx_i32m8_tu(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4asu_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4asu_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4asu_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4asu_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4asu_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4asu_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4su_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
+vint32m1_t test_vdot4asu_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
vuint32m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
+vint32m2_t test_vdot4asu_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
vuint32m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4asu_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4asu_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4su_vx_i32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4su_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4asu_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4su_vx_i32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4su_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4asu_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4su_vx_i32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4su_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4asu_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4su_vx_i32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4su_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4asu_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4su_vx_i32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4su_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4asu_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4su_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4asu_mu(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4u_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
similarity index 75%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4u_vv.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
index 26f9131e61ce7..5f9b75210a740 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4u_vv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
@@ -6,233 +6,233 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vv_u32mf2_tu(vuint32mf2_t vd, vuint32mf2_t vs2,
+vuint32mf2_t test_vdot4au_vv_u32mf2_tu(vuint32mf2_t vd, vuint32mf2_t vs2,
vuint32mf2_t vs1, size_t vl) {
- return __riscv_vdota4u_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4au_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vv_u32m1_tu(vuint32m1_t vd, vuint32m1_t vs2,
+vuint32m1_t test_vdot4au_vv_u32m1_tu(vuint32m1_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4u_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4au_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vv_u32m2_tu(vuint32m2_t vd, vuint32m2_t vs2,
+vuint32m2_t test_vdot4au_vv_u32m2_tu(vuint32m2_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4u_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4au_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vv_u32m4_tu(vuint32m4_t vd, vuint32m4_t vs2,
+vuint32m4_t test_vdot4au_vv_u32m4_tu(vuint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4u_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4au_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2,
+vuint32m8_t test_vdot4au_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4u_tu(vd, vs2, vs1, vl);
+ return __riscv_vdot4au_tu(vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vv_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,
+vuint32mf2_t test_vdot4au_vv_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4u_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vv_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
+vuint32m1_t test_vdot4au_vv_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
- return __riscv_vdota4u_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vv_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
+vuint32m2_t test_vdot4au_vv_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
vuint32m2_t vs2, vuint32m2_t vs1,
size_t vl) {
- return __riscv_vdota4u_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vv_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
+vuint32m4_t test_vdot4au_vv_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
vuint32m4_t vs2, vuint32m4_t vs1,
size_t vl) {
- return __riscv_vdota4u_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vv_u32m8_tum(vbool4_t vm, vuint32m8_t vd,
+vuint32m8_t test_vdot4au_vv_u32m8_tum(vbool4_t vm, vuint32m8_t vd,
vuint32m8_t vs2, vuint32m8_t vs1,
size_t vl) {
- return __riscv_vdota4u_tum(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_tum(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vv_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,
+vuint32mf2_t test_vdot4au_vv_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4u_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vv_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
+vuint32m1_t test_vdot4au_vv_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
- return __riscv_vdota4u_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vv_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
+vuint32m2_t test_vdot4au_vv_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
vuint32m2_t vs2, vuint32m2_t vs1,
size_t vl) {
- return __riscv_vdota4u_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vv_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
+vuint32m4_t test_vdot4au_vv_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
vuint32m4_t vs2, vuint32m4_t vs1,
size_t vl) {
- return __riscv_vdota4u_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vv_u32m8_tumu(vbool4_t vm, vuint32m8_t vd,
+vuint32m8_t test_vdot4au_vv_u32m8_tumu(vbool4_t vm, vuint32m8_t vd,
vuint32m8_t vs2, vuint32m8_t vs1,
size_t vl) {
- return __riscv_vdota4u_tumu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_tumu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vv_u32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vv_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,
+vuint32mf2_t test_vdot4au_vv_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
- return __riscv_vdota4u_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vv_u32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vv_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
+vuint32m1_t test_vdot4au_vv_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) {
- return __riscv_vdota4u_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vv_u32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vv_u32m2_mu(vbool16_t vm, vuint32m2_t vd,
+vuint32m2_t test_vdot4au_vv_u32m2_mu(vbool16_t vm, vuint32m2_t vd,
vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) {
- return __riscv_vdota4u_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vv_u32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vv_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint32m4_t vs2,
+vuint32m4_t test_vdot4au_vv_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
- return __riscv_vdota4u_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_mu(vm, vd, vs2, vs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vv_u32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vv_u32m8_mu(vbool4_t vm, vuint32m8_t vd, vuint32m8_t vs2,
+vuint32m8_t test_vdot4au_vv_u32m8_mu(vbool4_t vm, vuint32m8_t vd, vuint32m8_t vs2,
vuint32m8_t vs1, size_t vl) {
- return __riscv_vdota4u_mu(vm, vd, vs2, vs1, vl);
+ return __riscv_vdot4au_mu(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4u_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
similarity index 74%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4u_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
index 2ecc45e61c476..2895be49178ed 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4u_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
@@ -6,225 +6,225 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vx_u32mf2_tu(vuint32mf2_t vd, vuint32mf2_t vs2,
+vuint32mf2_t test_vdot4au_vx_u32mf2_tu(vuint32mf2_t vd, vuint32mf2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4au_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vx_u32m1_tu(vuint32m1_t vd, vuint32m1_t vs2,
+vuint32m1_t test_vdot4au_vx_u32m1_tu(vuint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4au_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vx_u32m2_tu(vuint32m2_t vd, vuint32m2_t vs2,
+vuint32m2_t test_vdot4au_vx_u32m2_tu(vuint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4au_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vx_u32m4_tu(vuint32m4_t vd, vuint32m4_t vs2,
+vuint32m4_t test_vdot4au_vx_u32m4_tu(vuint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4au_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vx_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2,
+vuint32m8_t test_vdot4au_vx_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4au_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vx_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,
+vuint32mf2_t test_vdot4au_vx_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4u_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vx_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
+vuint32m1_t test_vdot4au_vx_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
vuint32m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vx_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
+vuint32m2_t test_vdot4au_vx_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
vuint32m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vx_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
+vuint32m4_t test_vdot4au_vx_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
vuint32m4_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vx_u32m8_tum(vbool4_t vm, vuint32m8_t vd,
+vuint32m8_t test_vdot4au_vx_u32m8_tum(vbool4_t vm, vuint32m8_t vd,
vuint32m8_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vx_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,
+vuint32mf2_t test_vdot4au_vx_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4u_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vx_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
+vuint32m1_t test_vdot4au_vx_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
vuint32m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vx_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
+vuint32m2_t test_vdot4au_vx_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
vuint32m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vx_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
+vuint32m4_t test_vdot4au_vx_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
vuint32m4_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vx_u32m8_tumu(vbool4_t vm, vuint32m8_t vd,
+vuint32m8_t test_vdot4au_vx_u32m8_tumu(vbool4_t vm, vuint32m8_t vd,
vuint32m8_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4u_vx_u32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vuint32mf2_t test_vdota4u_vx_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,
+vuint32mf2_t test_vdot4au_vx_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4u_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4u_vx_u32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vdota4u_vx_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
+vuint32m1_t test_vdot4au_vx_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
vuint32m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4u_vx_u32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vdota4u_vx_u32m2_mu(vbool16_t vm, vuint32m2_t vd,
+vuint32m2_t test_vdot4au_vx_u32m2_mu(vbool16_t vm, vuint32m2_t vd,
vuint32m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4u_vx_u32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4au.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vdota4u_vx_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint32m4_t vs2,
+vuint32m4_t test_vdot4au_vx_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4u_vx_u32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4au.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vdota4u_vx_u32m8_mu(vbool4_t vm, vuint32m8_t vd, vuint32m8_t vs2,
+vuint32m8_t test_vdot4au_vx_u32m8_mu(vbool4_t vm, vuint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4u_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4au_mu(vm, vd, vs2, rs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4us_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
similarity index 74%
rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4us_vx.c
rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
index 380962ff3499d..d3cb25269d7c5 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4us_vx.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
@@ -6,225 +6,225 @@
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tu(
// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4us_vx_i32mf2_tu(vint32mf2_t vd, vuint32mf2_t vs2,
+vint32mf2_t test_vdot4aus_vx_i32mf2_tu(vint32mf2_t vd, vuint32mf2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tu(
// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4us_vx_i32m1_tu(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
+vint32m1_t test_vdot4aus_vx_i32m1_tu(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tu(
// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4us_vx_i32m2_tu(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
+vint32m2_t test_vdot4aus_vx_i32m2_tu(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4_tu(
// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4us_vx_i32m4_tu(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
+vint32m4_t test_vdot4aus_vx_i32m4_tu(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8_tu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8_tu(
// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4us_vx_i32m8_tu(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
+vint32m8_t test_vdot4aus_vx_i32m8_tu(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us_tu(vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_tu(vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tum(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4us_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4aus_vx_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tum(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4us_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd,
+vint32m1_t test_vdot4aus_vx_i32m1_tum(vbool32_t vm, vint32m1_t vd,
vuint32m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tum(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4us_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd,
+vint32m2_t test_vdot4aus_vx_i32m2_tum(vbool16_t vm, vint32m2_t vd,
vuint32m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4_tum(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4us_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4aus_vx_i32m4_tum(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8_tum(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8_tum(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4us_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4aus_vx_i32m8_tum(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_tum(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_tum(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tumu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4us_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4aus_vx_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tumu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4us_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
+vint32m1_t test_vdot4aus_vx_i32m1_tumu(vbool32_t vm, vint32m1_t vd,
vuint32m1_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tumu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4us_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
+vint32m2_t test_vdot4aus_vx_i32m2_tumu(vbool16_t vm, vint32m2_t vd,
vuint32m2_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4_tumu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4us_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd,
+vint32m4_t test_vdot4aus_vx_i32m4_tumu(vbool8_t vm, vint32m4_t vd,
vuint32m4_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8_tumu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8_tumu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4us_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd,
+vint32m8_t test_vdot4aus_vx_i32m8_tumu(vbool4_t vm, vint32m8_t vd,
vuint32m8_t vs2, uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_tumu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_tumu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4us_vx_i32mf2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_mu(
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4us.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
-vint32mf2_t test_vdota4us_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
+vint32mf2_t test_vdot4aus_vx_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
vuint32mf2_t vs2, uint32_t rs1,
size_t vl) {
- return __riscv_vdota4us_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4us_vx_i32m1_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_mu(
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4us.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vdota4us_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
+vint32m1_t test_vdot4aus_vx_i32m1_mu(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4us_vx_i32m2_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_mu(
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4us.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vdota4us_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
+vint32m2_t test_vdot4aus_vx_i32m2_mu(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4us_vx_i32m4_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4_mu(
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4us.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vdota4us_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
+vint32m4_t test_vdot4aus_vx_i32m4_mu(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_mu(vm, vd, vs2, rs1, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4us_vx_i32m8_mu(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8_mu(
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4us.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vdota4us_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
+vint32m8_t test_vdot4aus_vx_i32m8_mu(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2,
uint32_t rs1, size_t vl) {
- return __riscv_vdota4us_mu(vm, vd, vs2, rs1, vl);
+ return __riscv_vdot4aus_mu(vm, vd, vs2, rs1, vl);
}
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index caf8fa6f9be81..f53f752c25c30 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -2003,7 +2003,7 @@ let TargetPrefix = "riscv" in {
// We use llvm_anyvector_ty and llvm_anyint_ty for future extensibility
// purpose but only EEW=32 is defined for now
// Input: (vector_in, vector_in, vector_in/scalar_in, vl, policy)
- class RISCVVDOTA4UnMasked<bit HasVV>
+ class RISCVVDOT4AUnMasked<bit HasVV>
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>,
!if(HasVV, llvm_any_ty, llvm_anyint_ty),
@@ -2014,7 +2014,7 @@ let TargetPrefix = "riscv" in {
let VLOperand = 3;
}
// Input: (vector_in, vector_in, vector_in/scalar_in, mask, vl, policy)
- class RISCVVDOTA4Masked<bit HasVV>
+ class RISCVVDOT4AMasked<bit HasVV>
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>,
!if(HasVV, llvm_any_ty, llvm_anyint_ty),
@@ -2026,15 +2026,15 @@ let TargetPrefix = "riscv" in {
let VLOperand = 4;
}
- multiclass RISCVVDOTA4<bit HasVV = 1> {
- def "int_riscv_" # NAME : RISCVVDOTA4UnMasked<HasVV=HasVV>;
- def "int_riscv_" # NAME # "_mask" : RISCVVDOTA4Masked<HasVV=HasVV>;
+ multiclass RISCVVDOT4A<bit HasVV = 1> {
+ def "int_riscv_" # NAME : RISCVVDOT4AUnMasked<HasVV=HasVV>;
+ def "int_riscv_" # NAME # "_mask" : RISCVVDOT4AMasked<HasVV=HasVV>;
}
- defm vdota4 : RISCVVDOTA4;
- defm vdota4u : RISCVVDOTA4;
- defm vdota4su : RISCVVDOTA4;
- defm vdota4us : RISCVVDOTA4<HasVV=0>;
+ defm vdot4a : RISCVVDOT4A;
+ defm vdot4au : RISCVVDOT4A;
+ defm vdot4asu : RISCVVDOT4A;
+ defm vdot4aus : RISCVVDOT4A<HasVV=0>;
} // TargetPrefix = "riscv"
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 93e820b4713ec..b3258898452f9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -9182,7 +9182,7 @@ SDValue RISCVTargetLowering::lowerADJUST_TRAMPOLINE(SDValue Op,
SDValue RISCVTargetLowering::lowerPARTIAL_REDUCE_MLA(SDValue Op,
SelectionDAG &DAG) const {
- // Currently, only the vdota4 and vdota4u case (from zvdot4a8i) should be
+ // Currently, only the vdot4a and vdot4au case (from zvdot4a8i) should be
// legal.
// TODO: There are many other sub-cases we could potentially lower, are
// any of them worthwhile? Ex: via vredsum, vwredsum, vwwmaccu, etc..
@@ -9215,13 +9215,13 @@ SDValue RISCVTargetLowering::lowerPARTIAL_REDUCE_MLA(SDValue Op,
unsigned Opc;
switch (Op.getOpcode()) {
case ISD::PARTIAL_REDUCE_SMLA:
- Opc = RISCVISD::VDOTA4_VL;
+ Opc = RISCVISD::VDOT4A_VL;
break;
case ISD::PARTIAL_REDUCE_UMLA:
- Opc = RISCVISD::VDOTA4U_VL;
+ Opc = RISCVISD::VDOT4AU_VL;
break;
case ISD::PARTIAL_REDUCE_SUMLA:
- Opc = RISCVISD::VDOTA4SU_VL;
+ Opc = RISCVISD::VDOT4ASU_VL;
break;
default:
llvm_unreachable("Unexpected opcode");
@@ -19984,7 +19984,7 @@ static SDValue getZeroPaddedAdd(const SDLoc &DL, SDValue A, SDValue B,
return DAG.getInsertSubvector(DL, B, Res, 0);
}
-static SDValue foldReduceOperandViaVDOTA4(SDValue InVec, const SDLoc &DL,
+static SDValue foldReduceOperandViaVDOT4A(SDValue InVec, const SDLoc &DL,
SelectionDAG &DAG,
const RISCVSubtarget &Subtarget,
const RISCVTargetLowering &TLI) {
@@ -20000,8 +20000,8 @@ static SDValue foldReduceOperandViaVDOTA4(SDValue InVec, const SDLoc &DL,
// form).
SDValue A, B;
if (sd_match(InVec, m_AddLike(m_Value(A), m_Value(B)))) {
- SDValue AOpt = foldReduceOperandViaVDOTA4(A, DL, DAG, Subtarget, TLI);
- SDValue BOpt = foldReduceOperandViaVDOTA4(B, DL, DAG, Subtarget, TLI);
+ SDValue AOpt = foldReduceOperandViaVDOT4A(A, DL, DAG, Subtarget, TLI);
+ SDValue BOpt = foldReduceOperandViaVDOT4A(B, DL, DAG, Subtarget, TLI);
if (AOpt || BOpt) {
if (AOpt)
A = AOpt;
@@ -20079,7 +20079,7 @@ static SDValue performVECREDUCECombine(SDNode *N, SelectionDAG &DAG,
SDLoc DL(N);
EVT VT = N->getValueType(0);
SDValue InVec = N->getOperand(0);
- if (SDValue V = foldReduceOperandViaVDOTA4(InVec, DL, DAG, Subtarget, TLI))
+ if (SDValue V = foldReduceOperandViaVDOT4A(InVec, DL, DAG, Subtarget, TLI))
return DAG.getNode(ISD::VECREDUCE_ADD, DL, VT, V);
return SDValue();
}
@@ -20407,7 +20407,7 @@ static SDValue combineToVWMACC(SDNode *N, SelectionDAG &DAG,
return DAG.getNode(Opc, DL, VT, Ops);
}
-static SDValue combineVdota4Accum(SDNode *N, SelectionDAG &DAG,
+static SDValue combineVdot4aAccum(SDNode *N, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
assert(N->getOpcode() == RISCVISD::ADD_VL || N->getOpcode() == ISD::ADD);
@@ -20424,21 +20424,21 @@ static SDValue combineVdota4Accum(SDNode *N, SelectionDAG &DAG,
return SDValue();
}
- auto IsVdota4Opc = [](unsigned Opc) {
+ auto IsVdot4aOpc = [](unsigned Opc) {
switch (Opc) {
- case RISCVISD::VDOTA4_VL:
- case RISCVISD::VDOTA4U_VL:
- case RISCVISD::VDOTA4SU_VL:
+ case RISCVISD::VDOT4A_VL:
+ case RISCVISD::VDOT4AU_VL:
+ case RISCVISD::VDOT4ASU_VL:
return true;
default:
return false;
}
};
- if (!IsVdota4Opc(DotOp.getOpcode()))
+ if (!IsVdot4aOpc(DotOp.getOpcode()))
std::swap(Addend, DotOp);
- if (!IsVdota4Opc(DotOp.getOpcode()))
+ if (!IsVdot4aOpc(DotOp.getOpcode()))
return SDValue();
auto [AddMask, AddVL] = [](SDNode *N, SelectionDAG &DAG,
@@ -21274,7 +21274,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return V;
if (SDValue V = combineToVWMACC(N, DAG, Subtarget))
return V;
- if (SDValue V = combineVdota4Accum(N, DAG, Subtarget))
+ if (SDValue V = combineVdot4aAccum(N, DAG, Subtarget))
return V;
return performADDCombine(N, DCI, Subtarget);
}
@@ -21848,7 +21848,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return V;
if (SDValue V = combineOp_VLToVWOp_VL(N, DCI, Subtarget))
return V;
- if (SDValue V = combineVdota4Accum(N, DAG, Subtarget))
+ if (SDValue V = combineVdot4aAccum(N, DAG, Subtarget))
return V;
return combineToVWMACC(N, DAG, Subtarget);
case RISCVISD::VWADDU_VL:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 93512842712df..f2cfee8477883 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -4193,16 +4193,16 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
case CASE_RVV_OPCODE(VAADD_VV):
case CASE_RVV_OPCODE(VAADDU_VV):
case CASE_RVV_OPCODE(VSMUL_VV):
- case CASE_RVV_OPCODE_LMUL(VDOTA4_VV, MF2):
- case CASE_RVV_OPCODE_LMUL(VDOTA4_VV, M1):
- case CASE_RVV_OPCODE_LMUL(VDOTA4_VV, M2):
- case CASE_RVV_OPCODE_LMUL(VDOTA4_VV, M4):
- case CASE_RVV_OPCODE_LMUL(VDOTA4_VV, M8):
- case CASE_RVV_OPCODE_LMUL(VDOTA4U_VV, MF2):
- case CASE_RVV_OPCODE_LMUL(VDOTA4U_VV, M1):
- case CASE_RVV_OPCODE_LMUL(VDOTA4U_VV, M2):
- case CASE_RVV_OPCODE_LMUL(VDOTA4U_VV, M4):
- case CASE_RVV_OPCODE_LMUL(VDOTA4U_VV, M8):
+ case CASE_RVV_OPCODE_LMUL(VDOT4A_VV, MF2):
+ case CASE_RVV_OPCODE_LMUL(VDOT4A_VV, M1):
+ case CASE_RVV_OPCODE_LMUL(VDOT4A_VV, M2):
+ case CASE_RVV_OPCODE_LMUL(VDOT4A_VV, M4):
+ case CASE_RVV_OPCODE_LMUL(VDOT4A_VV, M8):
+ case CASE_RVV_OPCODE_LMUL(VDOT4AU_VV, MF2):
+ case CASE_RVV_OPCODE_LMUL(VDOT4AU_VV, M1):
+ case CASE_RVV_OPCODE_LMUL(VDOT4AU_VV, M2):
+ case CASE_RVV_OPCODE_LMUL(VDOT4AU_VV, M4):
+ case CASE_RVV_OPCODE_LMUL(VDOT4AU_VV, M8):
// Operands 2 and 3 are commutable.
return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
case CASE_VFMA_SPLATS(FMADD):
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvdot4a8i.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvdot4a8i.td
index d8c60dc9a584c..35a98ad7eb15a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvdot4a8i.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvdot4a8i.td
@@ -17,7 +17,7 @@
// Instructions
//===----------------------------------------------------------------------===//
-class VDOTA4VV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+class VDOT4AVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
: RVInstVV<funct6, opv, (outs VR:$vd_wb),
(ins VR:$vd, VR:$vs2, VR:$vs1, VMaskOp:$vm),
opcodestr, "$vd, $vs2, $vs1$vm"> {
@@ -27,7 +27,7 @@ class VDOTA4VV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
let Constraints = "$vd = $vd_wb";
}
-class VDOTA4VX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+class VDOT4AVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
: RVInstVX<funct6, opv, (outs VR:$vd_wb),
(ins VR:$vd, VR:$vs2, GPR:$rs1, VMaskOp:$vm),
opcodestr, "$vd, $vs2, $rs1$vm"> {
@@ -38,13 +38,13 @@ class VDOTA4VX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
}
let Predicates = [HasStdExtZvdot4a8i] in {
- def VDOTA4_VV : VDOTA4VV<0b101100, OPMVV, "vdota4.vv">;
- def VDOTA4_VX : VDOTA4VX<0b101100, OPMVX, "vdota4.vx">;
- def VDOTA4U_VV : VDOTA4VV<0b101000, OPMVV, "vdota4u.vv">;
- def VDOTA4U_VX : VDOTA4VX<0b101000, OPMVX, "vdota4u.vx">;
- def VDOTA4SU_VV : VDOTA4VV<0b101010, OPMVV, "vdota4su.vv">;
- def VDOTA4SU_VX : VDOTA4VX<0b101010, OPMVX, "vdota4su.vx">;
- def VDOTA4US_VX : VDOTA4VX<0b101110, OPMVX, "vdota4us.vx">;
+ def VDOT4A_VV : VDOT4AVV<0b101100, OPMVV, "vdot4a.vv">;
+ def VDOT4A_VX : VDOT4AVX<0b101100, OPMVX, "vdot4a.vx">;
+ def VDOT4AU_VV : VDOT4AVV<0b101000, OPMVV, "vdot4au.vv">;
+ def VDOT4AU_VX : VDOT4AVX<0b101000, OPMVX, "vdot4au.vx">;
+ def VDOT4ASU_VV : VDOT4AVV<0b101010, OPMVV, "vdot4asu.vv">;
+ def VDOT4ASU_VX : VDOT4AVX<0b101010, OPMVX, "vdot4asu.vx">;
+ def VDOT4AUS_VX : VDOT4AVX<0b101110, OPMVX, "vdot4aus.vx">;
} // Predicates = [HasStdExtZvdot4a8i]
//===----------------------------------------------------------------------===//
@@ -52,16 +52,16 @@ let Predicates = [HasStdExtZvdot4a8i] in {
//===----------------------------------------------------------------------===//
let HasPassthruOp = true, HasMaskOp = true in {
- def riscv_vdota4_vl : RVSDNode<"VDOTA4_VL", SDT_RISCVIntBinOp_VL>;
- def riscv_vdota4u_vl : RVSDNode<"VDOTA4U_VL", SDT_RISCVIntBinOp_VL>;
- def riscv_vdota4su_vl : RVSDNode<"VDOTA4SU_VL", SDT_RISCVIntBinOp_VL>;
+ def riscv_vdot4a_vl : RVSDNode<"VDOT4A_VL", SDT_RISCVIntBinOp_VL>;
+ def riscv_vdot4au_vl : RVSDNode<"VDOT4AU_VL", SDT_RISCVIntBinOp_VL>;
+ def riscv_vdot4asu_vl : RVSDNode<"VDOT4ASU_VL", SDT_RISCVIntBinOp_VL>;
} // let HasPassthruOp = true, HasMaskOp = true
//===----------------------------------------------------------------------===//
// Pseudo Instructions for CodeGen
//===----------------------------------------------------------------------===//
-multiclass VPseudoVDOTA4_VV_VX<bit Commutable = 0> {
+multiclass VPseudoVDOT4A_VV_VX<bit Commutable = 0> {
foreach m = MxSet<32>.m in {
defm "" : VPseudoBinaryV_VV<m, Commutable=Commutable>,
SchedBinary<"WriteVIMulAddV", "ReadVIMulAddV", "ReadVIMulAddV", m.MX,
@@ -74,12 +74,12 @@ multiclass VPseudoVDOTA4_VV_VX<bit Commutable = 0> {
let Predicates = [HasStdExtZvdot4a8i], mayLoad = 0, mayStore = 0,
hasSideEffects = 0 in {
- defm PseudoVDOTA4 : VPseudoVDOTA4_VV_VX<Commutable=1>;
- defm PseudoVDOTA4U : VPseudoVDOTA4_VV_VX<Commutable=1>;
- defm PseudoVDOTA4SU : VPseudoVDOTA4_VV_VX;
- // VDOTA4US does not have a VV variant
+ defm PseudoVDOT4A : VPseudoVDOT4A_VV_VX<Commutable=1>;
+ defm PseudoVDOT4AU : VPseudoVDOT4A_VV_VX<Commutable=1>;
+ defm PseudoVDOT4ASU : VPseudoVDOT4A_VV_VX;
+ // VDOT4AUS does not have a VV variant
foreach m = MxListVF4 in {
- defm "PseudoVDOTA4US_VX" : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, GPR, m>;
+ defm "PseudoVDOT4AUS_VX" : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, GPR, m>;
}
}
@@ -88,11 +88,11 @@ let Predicates = [HasStdExtZvdot4a8i], mayLoad = 0, mayStore = 0,
//===----------------------------------------------------------------------===//
defvar AllE32Vectors = [VI32MF2, VI32M1, VI32M2, VI32M4, VI32M8];
-defm : VPatBinaryVL_VV_VX<riscv_vdota4_vl, "PseudoVDOTA4", AllE32Vectors, ExtraPreds=[HasStdExtZvdot4a8i]>;
-defm : VPatBinaryVL_VV_VX<riscv_vdota4u_vl, "PseudoVDOTA4U", AllE32Vectors, ExtraPreds=[HasStdExtZvdot4a8i]>;
-defm : VPatBinaryVL_VV_VX<riscv_vdota4su_vl, "PseudoVDOTA4SU", AllE32Vectors, ExtraPreds=[HasStdExtZvdot4a8i]>;
+defm : VPatBinaryVL_VV_VX<riscv_vdot4a_vl, "PseudoVDOT4A", AllE32Vectors, ExtraPreds=[HasStdExtZvdot4a8i]>;
+defm : VPatBinaryVL_VV_VX<riscv_vdot4au_vl, "PseudoVDOT4AU", AllE32Vectors, ExtraPreds=[HasStdExtZvdot4a8i]>;
+defm : VPatBinaryVL_VV_VX<riscv_vdot4asu_vl, "PseudoVDOT4ASU", AllE32Vectors, ExtraPreds=[HasStdExtZvdot4a8i]>;
-// These VPat definitions are for vdota4 because they have a
diff erent operand
+// These VPat definitions are for vdot4a because they have a
diff erent operand
// order with other ternary instructions (i.e. vop.vx vd, vs2, rs1)
multiclass VPatTernaryV_VX_AAAX<string intrinsic, string instruction,
list<VTypeInfo> vtilist,
@@ -126,7 +126,7 @@ multiclass VPatTernaryV_VV_VX_AAAX<string intrinsic, string instruction,
: VPatTernaryV_VV_AAAX<intrinsic, instruction, vtilist, ExtraPreds>,
VPatTernaryV_VX_AAAX<intrinsic, instruction, vtilist, ExtraPreds>;
-defm : VPatTernaryV_VV_VX_AAAX<"int_riscv_vdota4", "PseudoVDOTA4", AllE32Vectors, [HasStdExtZvdot4a8i]>;
-defm : VPatTernaryV_VV_VX_AAAX<"int_riscv_vdota4u", "PseudoVDOTA4U", AllE32Vectors, [HasStdExtZvdot4a8i]>;
-defm : VPatTernaryV_VV_VX_AAAX<"int_riscv_vdota4su", "PseudoVDOTA4SU", AllE32Vectors, [HasStdExtZvdot4a8i]>;
-defm : VPatTernaryV_VX_AAAX<"int_riscv_vdota4us", "PseudoVDOTA4US", AllE32Vectors, [HasStdExtZvdot4a8i]>;
+defm : VPatTernaryV_VV_VX_AAAX<"int_riscv_vdot4a", "PseudoVDOT4A", AllE32Vectors, [HasStdExtZvdot4a8i]>;
+defm : VPatTernaryV_VV_VX_AAAX<"int_riscv_vdot4au", "PseudoVDOT4AU", AllE32Vectors, [HasStdExtZvdot4a8i]>;
+defm : VPatTernaryV_VV_VX_AAAX<"int_riscv_vdot4asu", "PseudoVDOT4ASU", AllE32Vectors, [HasStdExtZvdot4a8i]>;
+defm : VPatTernaryV_VX_AAAX<"int_riscv_vdot4aus", "PseudoVDOT4AUS", AllE32Vectors, [HasStdExtZvdot4a8i]>;
diff --git a/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp b/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp
index 2315a7802f7c5..fbb102caecdc6 100644
--- a/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp
@@ -35,9 +35,9 @@ void RISCVSelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
assert(N->getOperand(2).getOpcode() == ISD::TargetConstant &&
"Expected index to be a target constant!");
break;
- case RISCVISD::VDOTA4_VL:
- case RISCVISD::VDOTA4U_VL:
- case RISCVISD::VDOTA4SU_VL: {
+ case RISCVISD::VDOT4A_VL:
+ case RISCVISD::VDOT4AU_VL:
+ case RISCVISD::VDOT4ASU_VL: {
EVT VT = N->getValueType(0);
assert(VT.isScalableVector() && VT.getVectorElementType() == MVT::i32 &&
"Expected result to be an i32 scalable vector");
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index ca82f3e1a147b..3d2a70a826dd1 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -358,9 +358,9 @@ InstructionCost RISCVTTIImpl::getPartialReductionCost(
Type *Tp = VectorType::get(AccumType, VF.divideCoefficientBy(4));
std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Tp);
- // Note: Asuming all vdota4* variants are equal cost
+ // Note: Asuming all vdot4a* variants are equal cost
return LT.first *
- getRISCVInstructionCost(RISCV::VDOTA4_VV, LT.second, CostKind);
+ getRISCVInstructionCost(RISCV::VDOT4A_VV, LT.second, CostKind);
}
bool RISCVTTIImpl::shouldExpandReduction(const IntrinsicInst *II) const {
diff --git a/llvm/test/CodeGen/RISCV/rvv/commutable-zvdot4a8i.ll b/llvm/test/CodeGen/RISCV/rvv/commutable-zvdot4a8i.ll
index e5b3324651fce..771246a304ce2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/commutable-zvdot4a8i.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/commutable-zvdot4a8i.ll
@@ -4,22 +4,22 @@
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+experimental-zvdot4a8i \
; RUN: -verify-machineinstrs | FileCheck %s
-; vdota4.vv - commutable
-define <vscale x 2 x i32> @commutable_vdota4_vv(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
-; CHECK-LABEL: commutable_vdota4_vv:
+; vdot4a.vv - commutable
+define <vscale x 2 x i32> @commutable_vdot4a_vv(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
+; CHECK-LABEL: commutable_vdot4a_vv:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vdota4.vv v8, v8, v9
+; CHECK-NEXT: vdot4a.vv v8, v8, v9
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv2i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32(
<vscale x 2 x i32> poison,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
iXLen %2, iXLen 1)
- %b = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv2i32(
+ %b = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32(
<vscale x 2 x i32> poison,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %0,
@@ -28,21 +28,21 @@ entry:
ret <vscale x 2 x i32> %ret
}
-define <vscale x 2 x i32> @commutable_vdota4_vv_masked(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %mask, iXLen %2) {
-; CHECK-LABEL: commutable_vdota4_vv_masked:
+define <vscale x 2 x i32> @commutable_vdot4a_vv_masked(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %mask, iXLen %2) {
+; CHECK-LABEL: commutable_vdot4a_vv_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vdota4.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vdot4a.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: ret
- %a = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv2i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> poison,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i1> %mask,
iXLen %2, iXLen 1)
- %b = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv2i32(
+ %b = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> poison,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %0,
@@ -52,22 +52,22 @@ define <vscale x 2 x i32> @commutable_vdota4_vv_masked(<vscale x 2 x i32> %0, <v
ret <vscale x 2 x i32> %ret
}
-; vdota4u.vv - commutable
-define <vscale x 2 x i32> @commutable_vdota4u_vv(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
-; CHECK-LABEL: commutable_vdota4u_vv:
+; vdot4au.vv - commutable
+define <vscale x 2 x i32> @commutable_vdot4au_vv(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
+; CHECK-LABEL: commutable_vdot4au_vv:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vdota4u.vv v8, v8, v9
+; CHECK-NEXT: vdot4au.vv v8, v8, v9
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.nxv2i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32(
<vscale x 2 x i32> poison,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
iXLen %2, iXLen 1)
- %b = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.nxv2i32(
+ %b = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32(
<vscale x 2 x i32> poison,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %0,
@@ -76,21 +76,21 @@ entry:
ret <vscale x 2 x i32> %ret
}
-define <vscale x 2 x i32> @commutable_vdota4u_vv_masked(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %mask, iXLen %2) {
-; CHECK-LABEL: commutable_vdota4u_vv_masked:
+define <vscale x 2 x i32> @commutable_vdot4au_vv_masked(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %mask, iXLen %2) {
+; CHECK-LABEL: commutable_vdot4au_vv_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vdota4u.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vdot4au.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: ret
- %a = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv2i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> poison,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i1> %mask,
iXLen %2, iXLen 1)
- %b = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv2i32(
+ %b = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> poison,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %0,
@@ -100,23 +100,23 @@ define <vscale x 2 x i32> @commutable_vdota4u_vv_masked(<vscale x 2 x i32> %0, <
ret <vscale x 2 x i32> %ret
}
-; vdota4su.vv - NOT commutable (signed x unsigned, operand order matters)
-define <vscale x 2 x i32> @commutable_vdota4su_vv(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
-; CHECK-LABEL: commutable_vdota4su_vv:
+; vdot4asu.vv - NOT commutable (signed x unsigned, operand order matters)
+define <vscale x 2 x i32> @commutable_vdot4asu_vv(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
+; CHECK-LABEL: commutable_vdot4asu_vv:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vdota4su.vv v10, v8, v9
-; CHECK-NEXT: vdota4su.vv v8, v9, v8
+; CHECK-NEXT: vdot4asu.vv v10, v8, v9
+; CHECK-NEXT: vdot4asu.vv v8, v9, v8
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vadd.vv v8, v10, v8
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.nxv2i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32(
<vscale x 2 x i32> poison,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
iXLen %2, iXLen 1)
- %b = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.nxv2i32(
+ %b = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32(
<vscale x 2 x i32> poison,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %0,
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvdot4a8i.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvdot4a8i.ll
index f1211adcd2c09..2482ccbdde9ac 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvdot4a8i.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvdot4a8i.ll
@@ -4,8 +4,8 @@
; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvdot4a8i -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,DOT,DOT32
; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvdot4a8i -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,DOT,DOT64
-define i32 @vdota4_vv(<16 x i8> %a, <16 x i8> %b) {
-; NODOT-LABEL: vdota4_vv:
+define i32 @vdot4a_vv(<16 x i8> %a, <16 x i8> %b) {
+; NODOT-LABEL: vdot4a_vv:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v12, v8
@@ -17,11 +17,11 @@ define i32 @vdota4_vv(<16 x i8> %a, <16 x i8> %b) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4_vv:
+; DOT-LABEL: vdot4a_vv:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vdota4.vv v10, v8, v9
+; DOT-NEXT: vdot4a.vv v10, v8, v9
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -34,8 +34,8 @@ entry:
ret i32 %res
}
-define i32 @vdota4_vx_constant(<16 x i8> %a) {
-; CHECK-LABEL: vdota4_vx_constant:
+define i32 @vdot4a_vx_constant(<16 x i8> %a) {
+; CHECK-LABEL: vdot4a_vx_constant:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsext.vf2 v12, v8
@@ -53,8 +53,8 @@ entry:
ret i32 %res
}
-define i32 @vdota4_vx_constant_swapped(<16 x i8> %a) {
-; CHECK-LABEL: vdota4_vx_constant_swapped:
+define i32 @vdot4a_vx_constant_swapped(<16 x i8> %a) {
+; CHECK-LABEL: vdot4a_vx_constant_swapped:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsext.vf2 v12, v8
@@ -72,8 +72,8 @@ entry:
ret i32 %res
}
-define i32 @vdota4u_vv(<16 x i8> %a, <16 x i8> %b) {
-; NODOT-LABEL: vdota4u_vv:
+define i32 @vdot4au_vv(<16 x i8> %a, <16 x i8> %b) {
+; NODOT-LABEL: vdot4au_vv:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; NODOT-NEXT: vwmulu.vv v10, v8, v9
@@ -85,11 +85,11 @@ define i32 @vdota4u_vv(<16 x i8> %a, <16 x i8> %b) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4u_vv:
+; DOT-LABEL: vdot4au_vv:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vdota4u.vv v10, v8, v9
+; DOT-NEXT: vdot4au.vv v10, v8, v9
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -102,8 +102,8 @@ entry:
ret i32 %res
}
-define i32 @vdota4u_vx_constant(<16 x i8> %a) {
-; CHECK-LABEL: vdota4u_vx_constant:
+define i32 @vdot4au_vx_constant(<16 x i8> %a) {
+; CHECK-LABEL: vdot4au_vx_constant:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v12, v8
@@ -121,8 +121,8 @@ entry:
ret i32 %res
}
-define i32 @vdota4su_vv(<16 x i8> %a, <16 x i8> %b) {
-; NODOT-LABEL: vdota4su_vv:
+define i32 @vdot4asu_vv(<16 x i8> %a, <16 x i8> %b) {
+; NODOT-LABEL: vdot4asu_vv:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v12, v8
@@ -134,11 +134,11 @@ define i32 @vdota4su_vv(<16 x i8> %a, <16 x i8> %b) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4su_vv:
+; DOT-LABEL: vdot4asu_vv:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vdota4su.vv v10, v8, v9
+; DOT-NEXT: vdot4asu.vv v10, v8, v9
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -151,8 +151,8 @@ entry:
ret i32 %res
}
-define i32 @vdota4su_vv_swapped(<16 x i8> %a, <16 x i8> %b) {
-; NODOT-LABEL: vdota4su_vv_swapped:
+define i32 @vdot4asu_vv_swapped(<16 x i8> %a, <16 x i8> %b) {
+; NODOT-LABEL: vdot4asu_vv_swapped:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v12, v8
@@ -164,11 +164,11 @@ define i32 @vdota4su_vv_swapped(<16 x i8> %a, <16 x i8> %b) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4su_vv_swapped:
+; DOT-LABEL: vdot4asu_vv_swapped:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vdota4su.vv v10, v8, v9
+; DOT-NEXT: vdot4asu.vv v10, v8, v9
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -236,7 +236,7 @@ define i32 @reduce_of_sext(<16 x i8> %a) {
; DOT-NEXT: vmv.v.i v9, 1
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vdota4.vv v10, v8, v9
+; DOT-NEXT: vdot4a.vv v10, v8, v9
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -263,7 +263,7 @@ define i32 @reduce_of_zext(<16 x i8> %a) {
; DOT-NEXT: vmv.v.i v9, 1
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vdota4u.vv v10, v8, v9
+; DOT-NEXT: vdot4au.vv v10, v8, v9
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -274,8 +274,8 @@ entry:
ret i32 %res
}
-define i32 @vdota4_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
-; NODOT-LABEL: vdota4_vv_accum:
+define i32 @vdot4a_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
+; NODOT-LABEL: vdot4a_vv_accum:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v10, v8
@@ -287,11 +287,11 @@ define i32 @vdota4_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4_vv_accum:
+; DOT-LABEL: vdot4a_vv_accum:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv1r.v v16, v12
-; DOT-NEXT: vdota4.vv v16, v8, v9
+; DOT-NEXT: vdot4a.vv v16, v8, v9
; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma
; DOT-NEXT: vmv.v.v v12, v16
; DOT-NEXT: vmv.s.x v8, zero
@@ -308,8 +308,8 @@ entry:
ret i32 %sum
}
-define i32 @vdota4u_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
-; NODOT-LABEL: vdota4u_vv_accum:
+define i32 @vdot4au_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
+; NODOT-LABEL: vdot4au_vv_accum:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; NODOT-NEXT: vwmulu.vv v10, v8, v9
@@ -321,11 +321,11 @@ define i32 @vdota4u_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4u_vv_accum:
+; DOT-LABEL: vdot4au_vv_accum:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv1r.v v16, v12
-; DOT-NEXT: vdota4u.vv v16, v8, v9
+; DOT-NEXT: vdot4au.vv v16, v8, v9
; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma
; DOT-NEXT: vmv.v.v v12, v16
; DOT-NEXT: vmv.s.x v8, zero
@@ -342,8 +342,8 @@ entry:
ret i32 %sum
}
-define i32 @vdota4su_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
-; NODOT-LABEL: vdota4su_vv_accum:
+define i32 @vdot4asu_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
+; NODOT-LABEL: vdot4asu_vv_accum:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v10, v8
@@ -355,11 +355,11 @@ define i32 @vdota4su_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4su_vv_accum:
+; DOT-LABEL: vdot4asu_vv_accum:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv1r.v v16, v12
-; DOT-NEXT: vdota4su.vv v16, v8, v9
+; DOT-NEXT: vdot4asu.vv v16, v8, v9
; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma
; DOT-NEXT: vmv.v.v v12, v16
; DOT-NEXT: vmv.s.x v8, zero
@@ -376,8 +376,8 @@ entry:
ret i32 %sum
}
-define i32 @vdota4_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
-; NODOT-LABEL: vdota4_vv_scalar_add:
+define i32 @vdot4a_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
+; NODOT-LABEL: vdot4a_vv_scalar_add:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v12, v8
@@ -389,11 +389,11 @@ define i32 @vdota4_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4_vv_scalar_add:
+; DOT-LABEL: vdot4a_vv_scalar_add:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vdota4.vv v10, v8, v9
+; DOT-NEXT: vdot4a.vv v10, v8, v9
; DOT-NEXT: vmv.s.x v8, a0
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -407,8 +407,8 @@ entry:
ret i32 %add
}
-define i32 @vdota4u_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
-; NODOT-LABEL: vdota4u_vv_scalar_add:
+define i32 @vdot4au_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
+; NODOT-LABEL: vdot4au_vv_scalar_add:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; NODOT-NEXT: vwmulu.vv v10, v8, v9
@@ -420,11 +420,11 @@ define i32 @vdota4u_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4u_vv_scalar_add:
+; DOT-LABEL: vdot4au_vv_scalar_add:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vdota4u.vv v10, v8, v9
+; DOT-NEXT: vdot4au.vv v10, v8, v9
; DOT-NEXT: vmv.s.x v8, a0
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -438,8 +438,8 @@ entry:
ret i32 %add
}
-define i32 @vdota4su_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
-; NODOT-LABEL: vdota4su_vv_scalar_add:
+define i32 @vdot4asu_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
+; NODOT-LABEL: vdot4asu_vv_scalar_add:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v12, v8
@@ -451,11 +451,11 @@ define i32 @vdota4su_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4su_vv_scalar_add:
+; DOT-LABEL: vdot4asu_vv_scalar_add:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vdota4su.vv v10, v8, v9
+; DOT-NEXT: vdot4asu.vv v10, v8, v9
; DOT-NEXT: vmv.s.x v8, a0
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -469,8 +469,8 @@ entry:
ret i32 %add
}
-define i32 @vdota4_vv_split(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
-; NODOT-LABEL: vdota4_vv_split:
+define i32 @vdot4a_vv_split(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
+; NODOT-LABEL: vdot4a_vv_split:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v12, v8
@@ -485,12 +485,12 @@ define i32 @vdota4_vv_split(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8>
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4_vv_split:
+; DOT-LABEL: vdot4a_vv_split:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vdota4.vv v12, v8, v9
-; DOT-NEXT: vdota4.vv v12, v10, v11
+; DOT-NEXT: vdot4a.vv v12, v8, v9
+; DOT-NEXT: vdot4a.vv v12, v10, v11
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -507,8 +507,8 @@ entry:
ret i32 %sum
}
-define <1 x i32> @vdota4_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b) {
-; NODOT-LABEL: vdota4_vv_partial_reduce_v1i32_v4i8:
+define <1 x i32> @vdot4a_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b) {
+; NODOT-LABEL: vdot4a_vv_partial_reduce_v1i32_v4i8:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; NODOT-NEXT: vsext.vf2 v10, v8
@@ -526,11 +526,11 @@ define <1 x i32> @vdota4_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b)
; NODOT-NEXT: vadd.vv v8, v9, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4_vv_partial_reduce_v1i32_v4i8:
+; DOT-LABEL: vdot4a_vv_partial_reduce_v1i32_v4i8:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; DOT-NEXT: vmv.s.x v10, zero
-; DOT-NEXT: vdota4.vv v10, v8, v9
+; DOT-NEXT: vdot4a.vv v10, v8, v9
; DOT-NEXT: vmv1r.v v8, v10
; DOT-NEXT: ret
entry:
@@ -541,8 +541,8 @@ entry:
ret <1 x i32> %res
}
-define <1 x i32> @vdota4u_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b) {
-; NODOT-LABEL: vdota4u_vv_partial_reduce_v1i32_v4i8:
+define <1 x i32> @vdot4au_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b) {
+; NODOT-LABEL: vdot4au_vv_partial_reduce_v1i32_v4i8:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; NODOT-NEXT: vwmulu.vv v10, v8, v9
@@ -559,11 +559,11 @@ define <1 x i32> @vdota4u_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b)
; NODOT-NEXT: vadd.vv v8, v8, v9
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4u_vv_partial_reduce_v1i32_v4i8:
+; DOT-LABEL: vdot4au_vv_partial_reduce_v1i32_v4i8:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; DOT-NEXT: vmv.s.x v10, zero
-; DOT-NEXT: vdota4u.vv v10, v8, v9
+; DOT-NEXT: vdot4au.vv v10, v8, v9
; DOT-NEXT: vmv1r.v v8, v10
; DOT-NEXT: ret
entry:
@@ -574,8 +574,8 @@ entry:
ret <1 x i32> %res
}
-define <1 x i32> @vdota4u_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
-; NODOT-LABEL: vdota4u_vx_partial_reduce:
+define <1 x i32> @vdot4au_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
+; NODOT-LABEL: vdot4au_vx_partial_reduce:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; NODOT-NEXT: vzext.vf4 v9, v8
@@ -591,7 +591,7 @@ define <1 x i32> @vdota4u_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
; NODOT-NEXT: vadd.vv v8, v8, v9
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4u_vx_partial_reduce:
+; DOT-LABEL: vdot4au_vx_partial_reduce:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; DOT-NEXT: vmv.s.x v9, zero
@@ -599,7 +599,7 @@ define <1 x i32> @vdota4u_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
; DOT-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; DOT-NEXT: vmv.v.x v10, a0
; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; DOT-NEXT: vdota4u.vv v9, v8, v10
+; DOT-NEXT: vdot4au.vv v9, v8, v10
; DOT-NEXT: vmv1r.v v8, v9
; DOT-NEXT: ret
entry:
@@ -609,8 +609,8 @@ entry:
ret <1 x i32> %res
}
-define <1 x i32> @vdota4_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
-; NODOT-LABEL: vdota4_vx_partial_reduce:
+define <1 x i32> @vdot4a_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
+; NODOT-LABEL: vdot4a_vx_partial_reduce:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; NODOT-NEXT: vsext.vf4 v9, v8
@@ -627,7 +627,7 @@ define <1 x i32> @vdota4_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
; NODOT-NEXT: vadd.vv v8, v8, v9
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4_vx_partial_reduce:
+; DOT-LABEL: vdot4a_vx_partial_reduce:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; DOT-NEXT: vmv.s.x v9, zero
@@ -635,7 +635,7 @@ define <1 x i32> @vdota4_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
; DOT-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; DOT-NEXT: vmv.v.x v10, a0
; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; DOT-NEXT: vdota4.vv v9, v8, v10
+; DOT-NEXT: vdot4a.vv v9, v8, v10
; DOT-NEXT: vmv1r.v v8, v9
; DOT-NEXT: ret
entry:
@@ -645,8 +645,8 @@ entry:
ret <1 x i32> %res
}
-define <1 x i32> @vdota4su_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b) {
-; NODOT-LABEL: vdota4su_vv_partial_reduce_v1i32_v4i8:
+define <1 x i32> @vdot4asu_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b) {
+; NODOT-LABEL: vdot4asu_vv_partial_reduce_v1i32_v4i8:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; NODOT-NEXT: vsext.vf2 v10, v8
@@ -664,11 +664,11 @@ define <1 x i32> @vdota4su_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b
; NODOT-NEXT: vadd.vv v8, v9, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4su_vv_partial_reduce_v1i32_v4i8:
+; DOT-LABEL: vdot4asu_vv_partial_reduce_v1i32_v4i8:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; DOT-NEXT: vmv.s.x v10, zero
-; DOT-NEXT: vdota4su.vv v10, v8, v9
+; DOT-NEXT: vdot4asu.vv v10, v8, v9
; DOT-NEXT: vmv1r.v v8, v10
; DOT-NEXT: ret
entry:
@@ -679,8 +679,8 @@ entry:
ret <1 x i32> %res
}
-define <1 x i32> @vdota4su_vv_partial_reduce_swapped(<4 x i8> %a, <4 x i8> %b) {
-; NODOT-LABEL: vdota4su_vv_partial_reduce_swapped:
+define <1 x i32> @vdot4asu_vv_partial_reduce_swapped(<4 x i8> %a, <4 x i8> %b) {
+; NODOT-LABEL: vdot4asu_vv_partial_reduce_swapped:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; NODOT-NEXT: vsext.vf2 v10, v8
@@ -698,11 +698,11 @@ define <1 x i32> @vdota4su_vv_partial_reduce_swapped(<4 x i8> %a, <4 x i8> %b) {
; NODOT-NEXT: vadd.vv v8, v9, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4su_vv_partial_reduce_swapped:
+; DOT-LABEL: vdot4asu_vv_partial_reduce_swapped:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; DOT-NEXT: vmv.s.x v10, zero
-; DOT-NEXT: vdota4su.vv v10, v8, v9
+; DOT-NEXT: vdot4asu.vv v10, v8, v9
; DOT-NEXT: vmv1r.v v8, v10
; DOT-NEXT: ret
entry:
@@ -713,8 +713,8 @@ entry:
ret <1 x i32> %res
}
-define <1 x i32> @vdota4su_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
-; CHECK-LABEL: vdota4su_vx_partial_reduce:
+define <1 x i32> @vdot4asu_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
+; CHECK-LABEL: vdot4asu_vx_partial_reduce:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vsext.vf4 v9, v8
@@ -737,8 +737,8 @@ entry:
}
-define <2 x i32> @vdota4_vv_partial_reduce_v2i32_v8i8(<8 x i8> %a, <8 x i8> %b) {
-; NODOT-LABEL: vdota4_vv_partial_reduce_v2i32_v8i8:
+define <2 x i32> @vdot4a_vv_partial_reduce_v2i32_v8i8(<8 x i8> %a, <8 x i8> %b) {
+; NODOT-LABEL: vdot4a_vv_partial_reduce_v2i32_v8i8:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; NODOT-NEXT: vsext.vf2 v10, v8
@@ -757,11 +757,11 @@ define <2 x i32> @vdota4_vv_partial_reduce_v2i32_v8i8(<8 x i8> %a, <8 x i8> %b)
; NODOT-NEXT: vadd.vv v8, v8, v12
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4_vv_partial_reduce_v2i32_v8i8:
+; DOT-LABEL: vdot4a_vv_partial_reduce_v2i32_v8i8:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vdota4.vv v10, v8, v9
+; DOT-NEXT: vdot4a.vv v10, v8, v9
; DOT-NEXT: vmv1r.v v8, v10
; DOT-NEXT: ret
entry:
@@ -772,8 +772,8 @@ entry:
ret <2 x i32> %res
}
-define <2 x i32> @vdota4_vv_partial_reduce_v2i32_v64i8(<64 x i8> %a, <64 x i8> %b) {
-; CHECK-LABEL: vdota4_vv_partial_reduce_v2i32_v64i8:
+define <2 x i32> @vdot4a_vv_partial_reduce_v2i32_v64i8(<64 x i8> %a, <64 x i8> %b) {
+; CHECK-LABEL: vdot4a_vv_partial_reduce_v2i32_v64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
@@ -949,8 +949,8 @@ entry:
ret <2 x i32> %res
}
-define <4 x i32> @vdota4_vv_partial_reduce_v4i32_v16i8(<16 x i8> %a, <16 x i8> %b) {
-; NODOT-LABEL: vdota4_vv_partial_reduce_v4i32_v16i8:
+define <4 x i32> @vdot4a_vv_partial_reduce_v4i32_v16i8(<16 x i8> %a, <16 x i8> %b) {
+; NODOT-LABEL: vdot4a_vv_partial_reduce_v4i32_v16i8:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v12, v8
@@ -969,11 +969,11 @@ define <4 x i32> @vdota4_vv_partial_reduce_v4i32_v16i8(<16 x i8> %a, <16 x i8> %
; NODOT-NEXT: vadd.vv v8, v8, v16
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4_vv_partial_reduce_v4i32_v16i8:
+; DOT-LABEL: vdot4a_vv_partial_reduce_v4i32_v16i8:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vdota4.vv v10, v8, v9
+; DOT-NEXT: vdot4a.vv v10, v8, v9
; DOT-NEXT: vmv.v.v v8, v10
; DOT-NEXT: ret
entry:
@@ -984,8 +984,8 @@ entry:
ret <4 x i32> %res
}
-define <16 x i32> @vdota4_vv_partial_reduce_v16i32_v64i8(<64 x i8> %a, <64 x i8> %b) {
-; NODOT-LABEL: vdota4_vv_partial_reduce_v16i32_v64i8:
+define <16 x i32> @vdot4a_vv_partial_reduce_v16i32_v64i8(<64 x i8> %a, <64 x i8> %b) {
+; NODOT-LABEL: vdot4a_vv_partial_reduce_v16i32_v64i8:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: li a0, 32
; NODOT-NEXT: vsetvli zero, a0, e16, m4, ta, ma
@@ -1012,11 +1012,11 @@ define <16 x i32> @vdota4_vv_partial_reduce_v16i32_v64i8(<64 x i8> %a, <64 x i8>
; NODOT-NEXT: vadd.vv v8, v8, v24
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4_vv_partial_reduce_v16i32_v64i8:
+; DOT-LABEL: vdot4a_vv_partial_reduce_v16i32_v64i8:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; DOT-NEXT: vmv.v.i v16, 0
-; DOT-NEXT: vdota4.vv v16, v8, v12
+; DOT-NEXT: vdot4a.vv v16, v8, v12
; DOT-NEXT: vmv.v.v v8, v16
; DOT-NEXT: ret
entry:
@@ -1027,8 +1027,8 @@ entry:
ret <16 x i32> %res
}
-define <4 x i32> @vdota4_vv_partial_reduce_m1_accum(<16 x i8> %a, <16 x i8> %b, <4 x i32> %accum) {
-; NODOT-LABEL: vdota4_vv_partial_reduce_m1_accum:
+define <4 x i32> @vdot4a_vv_partial_reduce_m1_accum(<16 x i8> %a, <16 x i8> %b, <4 x i32> %accum) {
+; NODOT-LABEL: vdot4a_vv_partial_reduce_m1_accum:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v16, v8
@@ -1049,10 +1049,10 @@ define <4 x i32> @vdota4_vv_partial_reduce_m1_accum(<16 x i8> %a, <16 x i8> %b,
; NODOT-NEXT: vadd.vv v8, v8, v16
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4_vv_partial_reduce_m1_accum:
+; DOT-LABEL: vdot4a_vv_partial_reduce_m1_accum:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; DOT-NEXT: vdota4.vv v10, v8, v9
+; DOT-NEXT: vdot4a.vv v10, v8, v9
; DOT-NEXT: vmv.v.v v8, v10
; DOT-NEXT: ret
entry:
@@ -1063,8 +1063,8 @@ entry:
ret <4 x i32> %res
}
-define <16 x i32> @vdota4_vv_partial_reduce3(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-LABEL: vdota4_vv_partial_reduce3:
+define <16 x i32> @vdot4a_vv_partial_reduce3(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: vdot4a_vv_partial_reduce3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsext.vf2 v12, v8
@@ -1080,8 +1080,8 @@ entry:
}
; Test legalization - type split
-define <64 x i32> @vdota4su_vv_partial_v64i32_v256i8(<256 x i8> %a, <256 x i8> %b) {
-; NODOT-LABEL: vdota4su_vv_partial_v64i32_v256i8:
+define <64 x i32> @vdot4asu_vv_partial_v64i32_v256i8(<256 x i8> %a, <256 x i8> %b) {
+; NODOT-LABEL: vdot4asu_vv_partial_v64i32_v256i8:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: addi sp, sp, -16
; NODOT-NEXT: .cfi_def_cfa_offset 16
@@ -1298,7 +1298,7 @@ define <64 x i32> @vdota4su_vv_partial_v64i32_v256i8(<256 x i8> %a, <256 x i8> %
; NODOT-NEXT: .cfi_def_cfa_offset 0
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4su_vv_partial_v64i32_v256i8:
+; DOT-LABEL: vdot4asu_vv_partial_v64i32_v256i8:
; DOT: # %bb.0: # %entry
; DOT-NEXT: addi sp, sp, -16
; DOT-NEXT: .cfi_def_cfa_offset 16
@@ -1345,7 +1345,7 @@ define <64 x i32> @vdota4su_vv_partial_v64i32_v256i8(<256 x i8> %a, <256 x i8> %
; DOT-NEXT: add a0, sp, a0
; DOT-NEXT: addi a0, a0, 16
; DOT-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; DOT-NEXT: vdota4su.vv v0, v16, v8
+; DOT-NEXT: vdot4asu.vv v0, v16, v8
; DOT-NEXT: csrr a0, vlenb
; DOT-NEXT: slli a0, a0, 3
; DOT-NEXT: mv a1, a0
@@ -1356,7 +1356,7 @@ define <64 x i32> @vdota4su_vv_partial_v64i32_v256i8(<256 x i8> %a, <256 x i8> %
; DOT-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; DOT-NEXT: addi a0, sp, 16
; DOT-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; DOT-NEXT: vdota4su.vv v24, v16, v8
+; DOT-NEXT: vdot4asu.vv v24, v16, v8
; DOT-NEXT: vmv.v.v v8, v0
; DOT-NEXT: vmv.v.v v16, v24
; DOT-NEXT: csrr a0, vlenb
@@ -1375,8 +1375,8 @@ entry:
}
; Test legalization - integer promote
-define <4 x i31> @vdota4su_vv_partial_v4i31_v16i7(<16 x i7> %a, <16 x i7> %b) {
-; NODOT-LABEL: vdota4su_vv_partial_v4i31_v16i7:
+define <4 x i31> @vdot4asu_vv_partial_v4i31_v16i7(<16 x i7> %a, <16 x i7> %b) {
+; NODOT-LABEL: vdot4asu_vv_partial_v4i31_v16i7:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; NODOT-NEXT: vzext.vf4 v12, v8
@@ -1404,7 +1404,7 @@ define <4 x i31> @vdota4su_vv_partial_v4i31_v16i7(<16 x i7> %a, <16 x i7> %b) {
; NODOT-NEXT: vadd.vv v8, v8, v16
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4su_vv_partial_v4i31_v16i7:
+; DOT-LABEL: vdot4asu_vv_partial_v4i31_v16i7:
; DOT: # %bb.0: # %entry
; DOT-NEXT: li a0, 127
; DOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma
@@ -1413,7 +1413,7 @@ define <4 x i31> @vdota4su_vv_partial_v4i31_v16i7(<16 x i7> %a, <16 x i7> %b) {
; DOT-NEXT: vsra.vi v10, v8, 1
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v8, 0
-; DOT-NEXT: vdota4su.vv v8, v10, v9
+; DOT-NEXT: vdot4asu.vv v8, v10, v9
; DOT-NEXT: ret
entry:
%a.ext = sext <16 x i7> %a to <16 x i31>
@@ -1425,8 +1425,8 @@ entry:
; Test legalization - expand
-define <1 x i32> @vdota4su_vv_partial_v1i32_v2i8(<2 x i8> %a, <2 x i8> %b) {
-; CHECK-LABEL: vdota4su_vv_partial_v1i32_v2i8:
+define <1 x i32> @vdot4asu_vv_partial_v1i32_v2i8(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: vdot4asu_vv_partial_v1i32_v2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vsext.vf2 v10, v8
@@ -1446,10 +1446,10 @@ entry:
}
; TODO: This isn't legal, but we could split it into two halves, and use
-; a pair of slides + two vdota4su_vv here. Or alternatively, the mul
+; a pair of slides + two vdot4asu_vv here. Or alternatively, the mul
; sequence + one vredsum, or a vadd reduce tree.
-define <1 x i32> @vdota4su_vv_partial_v1i32_v8i8(<8 x i8> %a, <8 x i8> %b) {
-; CHECK-LABEL: vdota4su_vv_partial_v1i32_v8i8:
+define <1 x i32> @vdot4asu_vv_partial_v1i32_v8i8(<8 x i8> %a, <8 x i8> %b) {
+; CHECK-LABEL: vdot4asu_vv_partial_v1i32_v8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vsext.vf2 v10, v8
@@ -1511,7 +1511,7 @@ define <4 x i32> @partial_of_sext(<16 x i8> %a) {
; DOT-NEXT: vmv.v.i v10, 1
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v9, 0
-; DOT-NEXT: vdota4.vv v9, v8, v10
+; DOT-NEXT: vdot4a.vv v9, v8, v10
; DOT-NEXT: vmv.v.v v8, v9
; DOT-NEXT: ret
entry:
@@ -1544,7 +1544,7 @@ define <4 x i32> @partial_of_zext(<16 x i8> %a) {
; DOT-NEXT: vmv.v.i v10, 1
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v9, 0
-; DOT-NEXT: vdota4u.vv v9, v8, v10
+; DOT-NEXT: vdot4au.vv v9, v8, v10
; DOT-NEXT: vmv.v.v v8, v9
; DOT-NEXT: ret
entry:
@@ -1553,8 +1553,8 @@ entry:
ret <4 x i32> %res
}
-define i32 @vdota4_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
-; NODOT-LABEL: vdota4_vv_accum_disjoint_or:
+define i32 @vdot4a_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
+; NODOT-LABEL: vdot4a_vv_accum_disjoint_or:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v16, v8
@@ -1567,11 +1567,11 @@ define i32 @vdota4_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4_vv_accum_disjoint_or:
+; DOT-LABEL: vdot4a_vv_accum_disjoint_or:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv1r.v v16, v12
-; DOT-NEXT: vdota4.vv v16, v8, v9
+; DOT-NEXT: vdot4a.vv v16, v8, v9
; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma
; DOT-NEXT: vmv.v.v v12, v16
; DOT-NEXT: vmv.s.x v8, zero
@@ -1588,8 +1588,8 @@ entry:
ret i32 %sum
}
-define i32 @vdota4_vv_accum_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
-; CHECK-LABEL: vdota4_vv_accum_or:
+define i32 @vdot4a_vv_accum_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
+; CHECK-LABEL: vdot4a_vv_accum_or:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsext.vf2 v16, v8
@@ -1610,8 +1610,8 @@ entry:
ret i32 %sum
}
-define i32 @vdota4u_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
-; NODOT-LABEL: vdota4u_vv_accum_disjoint_or:
+define i32 @vdot4au_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
+; NODOT-LABEL: vdot4au_vv_accum_disjoint_or:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; NODOT-NEXT: vwmulu.vv v10, v8, v9
@@ -1623,11 +1623,11 @@ define i32 @vdota4u_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32>
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4u_vv_accum_disjoint_or:
+; DOT-LABEL: vdot4au_vv_accum_disjoint_or:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv1r.v v16, v12
-; DOT-NEXT: vdota4u.vv v16, v8, v9
+; DOT-NEXT: vdot4au.vv v16, v8, v9
; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma
; DOT-NEXT: vmv.v.v v12, v16
; DOT-NEXT: vmv.s.x v8, zero
@@ -1644,8 +1644,8 @@ entry:
ret i32 %sum
}
-define i32 @vdota4su_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
-; NODOT-LABEL: vdota4su_vv_accum_disjoint_or:
+define i32 @vdot4asu_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
+; NODOT-LABEL: vdot4asu_vv_accum_disjoint_or:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v16, v8
@@ -1658,11 +1658,11 @@ define i32 @vdota4su_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32>
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4su_vv_accum_disjoint_or:
+; DOT-LABEL: vdot4asu_vv_accum_disjoint_or:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv1r.v v16, v12
-; DOT-NEXT: vdota4su.vv v16, v8, v9
+; DOT-NEXT: vdot4asu.vv v16, v8, v9
; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma
; DOT-NEXT: vmv.v.v v12, v16
; DOT-NEXT: vmv.s.x v8, zero
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdota4.ll b/llvm/test/CodeGen/RISCV/rvv/vdot4a.ll
similarity index 62%
rename from llvm/test/CodeGen/RISCV/rvv/vdota4.ll
rename to llvm/test/CodeGen/RISCV/rvv/vdot4a.ll
index c28520b81d014..591b80d5cdb6d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdota4.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdot4a.ll
@@ -4,14 +4,14 @@
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+experimental-zvdot4a8i \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-define <vscale x 1 x i32> @intrinsic_vdota4_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4_vv_nxv1i32_nxv1i32:
+define <vscale x 1 x i32> @intrinsic_vdot4a_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4a_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
-; CHECK-NEXT: vdota4.vv v8, v9, v10
+; CHECK-NEXT: vdot4a.vv v8, v9, v10
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.nxv1i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
@@ -20,14 +20,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vdota4_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4_vv_nxv2i32_nxv2i32:
+define <vscale x 2 x i32> @intrinsic_vdot4a_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4a_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
-; CHECK-NEXT: vdota4.vv v8, v9, v10
+; CHECK-NEXT: vdot4a.vv v8, v9, v10
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv2i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
@@ -36,14 +36,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vdota4_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4_vv_nxv4i32_nxv4i32:
+define <vscale x 4 x i32> @intrinsic_vdot4a_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4a_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
-; CHECK-NEXT: vdota4.vv v8, v10, v12
+; CHECK-NEXT: vdot4a.vv v8, v10, v12
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.nxv4i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
@@ -52,14 +52,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vdota4_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4_vv_nxv8i32_nxv8i32:
+define <vscale x 8 x i32> @intrinsic_vdot4a_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4a_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
-; CHECK-NEXT: vdota4.vv v8, v12, v16
+; CHECK-NEXT: vdot4a.vv v8, v12, v16
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.nxv8i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
@@ -68,15 +68,15 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vdota4_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4_vv_nxv16i32_nxv16i32:
+define <vscale x 16 x i32> @intrinsic_vdot4a_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4a_vv_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
-; CHECK-NEXT: vdota4.vv v8, v16, v24
+; CHECK-NEXT: vdot4a.vv v8, v16, v24
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.nxv16i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
@@ -85,14 +85,14 @@ entry:
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i32> @intrinsic_vdota4_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4_mask_vv_nxv1i32_nxv1i32:
+define <vscale x 1 x i32> @intrinsic_vdot4a_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4a_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
-; CHECK-NEXT: vdota4.vv v8, v9, v10, v0.t
+; CHECK-NEXT: vdot4a.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv1i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
@@ -102,14 +102,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vdota4_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4_mask_vv_nxv2i32_nxv2i32:
+define <vscale x 2 x i32> @intrinsic_vdot4a_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4a_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
-; CHECK-NEXT: vdota4.vv v8, v9, v10, v0.t
+; CHECK-NEXT: vdot4a.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv2i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
@@ -119,14 +119,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vdota4_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4_mask_vv_nxv4i32_nxv4i32:
+define <vscale x 4 x i32> @intrinsic_vdot4a_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4a_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
-; CHECK-NEXT: vdota4.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vdot4a.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv4i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
@@ -136,14 +136,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vdota4_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4_mask_vv_nxv8i32_nxv8i32:
+define <vscale x 8 x i32> @intrinsic_vdot4a_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4a_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
-; CHECK-NEXT: vdota4.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vdot4a.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv8i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdot4a.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
@@ -153,15 +153,15 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vdota4_mask_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4_mask_vv_nxv16i32_nxv16i32:
+define <vscale x 16 x i32> @intrinsic_vdot4a_mask_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4a_mask_vv_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
-; CHECK-NEXT: vdota4.vv v8, v16, v24, v0.t
+; CHECK-NEXT: vdot4a.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv16i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdot4a.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
@@ -171,14 +171,14 @@ entry:
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i32> @intrinsic_vdota4_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4_vx_nxv1i32_i32:
+define <vscale x 1 x i32> @intrinsic_vdot4a_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4a_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma
-; CHECK-NEXT: vdota4.vx v8, v9, a0
+; CHECK-NEXT: vdot4a.vx v8, v9, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i32 %2,
@@ -187,14 +187,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vdota4_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4_vx_nxv2i32_i32:
+define <vscale x 2 x i32> @intrinsic_vdot4a_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4a_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma
-; CHECK-NEXT: vdota4.vx v8, v9, a0
+; CHECK-NEXT: vdot4a.vx v8, v9, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i32 %2,
@@ -203,14 +203,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vdota4_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4_vx_nxv4i32_i32:
+define <vscale x 4 x i32> @intrinsic_vdot4a_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4a_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma
-; CHECK-NEXT: vdota4.vx v8, v10, a0
+; CHECK-NEXT: vdot4a.vx v8, v10, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i32 %2,
@@ -219,14 +219,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vdota4_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4_vx_nxv8i32_i32:
+define <vscale x 8 x i32> @intrinsic_vdot4a_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4a_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma
-; CHECK-NEXT: vdota4.vx v8, v12, a0
+; CHECK-NEXT: vdot4a.vx v8, v12, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i32 %2,
@@ -235,14 +235,14 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vdota4_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4_vx_nxv16i32_i32:
+define <vscale x 16 x i32> @intrinsic_vdot4a_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4a_vx_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
-; CHECK-NEXT: vdota4.vx v8, v16, a0
+; CHECK-NEXT: vdot4a.vx v8, v16, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i32 %2,
@@ -251,14 +251,14 @@ entry:
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i32> @intrinsic_vdota4_mask_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4_mask_vx_nxv1i32_i32:
+define <vscale x 1 x i32> @intrinsic_vdot4a_mask_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4a_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vdota4.vx v8, v9, a0, v0.t
+; CHECK-NEXT: vdot4a.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i32 %2,
@@ -268,14 +268,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vdota4_mask_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4_mask_vx_nxv2i32_i32:
+define <vscale x 2 x i32> @intrinsic_vdot4a_mask_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4a_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vdota4.vx v8, v9, a0, v0.t
+; CHECK-NEXT: vdot4a.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i32 %2,
@@ -285,14 +285,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vdota4_mask_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4_mask_vx_nxv4i32_i32:
+define <vscale x 4 x i32> @intrinsic_vdot4a_mask_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4a_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
-; CHECK-NEXT: vdota4.vx v8, v10, a0, v0.t
+; CHECK-NEXT: vdot4a.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i32 %2,
@@ -302,14 +302,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vdota4_mask_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4_mask_vx_nxv8i32_i32:
+define <vscale x 8 x i32> @intrinsic_vdot4a_mask_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4a_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
-; CHECK-NEXT: vdota4.vx v8, v12, a0, v0.t
+; CHECK-NEXT: vdot4a.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdot4a.mask.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i32 %2,
@@ -319,14 +319,14 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vdota4_mask_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4_mask_vx_nxv16i32_i32:
+define <vscale x 16 x i32> @intrinsic_vdot4a_mask_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4a_mask_vx_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
-; CHECK-NEXT: vdota4.vx v8, v16, a0, v0.t
+; CHECK-NEXT: vdot4a.vx v8, v16, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdot4a.mask.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i32 %2,
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdota4su.ll b/llvm/test/CodeGen/RISCV/rvv/vdot4asu.ll
similarity index 62%
rename from llvm/test/CodeGen/RISCV/rvv/vdota4su.ll
rename to llvm/test/CodeGen/RISCV/rvv/vdot4asu.ll
index a33b5ce5fa3d2..07d10f0135f18 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdota4su.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdot4asu.ll
@@ -4,14 +4,14 @@
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+experimental-zvdot4a8i \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-define <vscale x 1 x i32> @intrinsic_vdota4su_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4su_vv_nxv1i32_nxv1i32:
+define <vscale x 1 x i32> @intrinsic_vdot4asu_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4asu_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
-; CHECK-NEXT: vdota4su.vv v8, v9, v10
+; CHECK-NEXT: vdot4asu.vv v8, v9, v10
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vdota4su.nxv1i32.nxv1i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
@@ -20,14 +20,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vdota4su_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4su_vv_nxv2i32_nxv2i32:
+define <vscale x 2 x i32> @intrinsic_vdot4asu_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4asu_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
-; CHECK-NEXT: vdota4su.vv v8, v9, v10
+; CHECK-NEXT: vdot4asu.vv v8, v9, v10
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.nxv2i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
@@ -36,14 +36,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vdota4su_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4su_vv_nxv4i32_nxv4i32:
+define <vscale x 4 x i32> @intrinsic_vdot4asu_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4asu_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
-; CHECK-NEXT: vdota4su.vv v8, v10, v12
+; CHECK-NEXT: vdot4asu.vv v8, v10, v12
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vdota4su.nxv4i32.nxv4i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
@@ -52,14 +52,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vdota4su_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4su_vv_nxv8i32_nxv8i32:
+define <vscale x 8 x i32> @intrinsic_vdot4asu_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4asu_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
-; CHECK-NEXT: vdota4su.vv v8, v12, v16
+; CHECK-NEXT: vdot4asu.vv v8, v12, v16
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vdota4su.nxv8i32.nxv8i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
@@ -68,15 +68,15 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vdota4su_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4su_vv_nxv16i32_nxv16i32:
+define <vscale x 16 x i32> @intrinsic_vdot4asu_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4asu_vv_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
-; CHECK-NEXT: vdota4su.vv v8, v16, v24
+; CHECK-NEXT: vdot4asu.vv v8, v16, v24
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vdota4su.nxv16i32.nxv16i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
@@ -85,14 +85,14 @@ entry:
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i32> @intrinsic_vdota4su_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4su_mask_vv_nxv1i32_nxv1i32:
+define <vscale x 1 x i32> @intrinsic_vdot4asu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4asu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
-; CHECK-NEXT: vdota4su.vv v8, v9, v10, v0.t
+; CHECK-NEXT: vdot4asu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.nxv1i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
@@ -102,14 +102,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vdota4su_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4su_mask_vv_nxv2i32_nxv2i32:
+define <vscale x 2 x i32> @intrinsic_vdot4asu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4asu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
-; CHECK-NEXT: vdota4su.vv v8, v9, v10, v0.t
+; CHECK-NEXT: vdot4asu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.nxv2i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
@@ -119,14 +119,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vdota4su_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4su_mask_vv_nxv4i32_nxv4i32:
+define <vscale x 4 x i32> @intrinsic_vdot4asu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4asu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
-; CHECK-NEXT: vdota4su.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vdot4asu.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.nxv4i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
@@ -136,14 +136,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vdota4su_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4su_mask_vv_nxv8i32_nxv8i32:
+define <vscale x 8 x i32> @intrinsic_vdot4asu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4asu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
-; CHECK-NEXT: vdota4su.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vdot4asu.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.nxv8i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
@@ -153,15 +153,15 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vdota4su_mask_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4su_mask_vv_nxv16i32_nxv16i32:
+define <vscale x 16 x i32> @intrinsic_vdot4asu_mask_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4asu_mask_vv_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
-; CHECK-NEXT: vdota4su.vv v8, v16, v24, v0.t
+; CHECK-NEXT: vdot4asu.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.nxv16i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
@@ -171,14 +171,14 @@ entry:
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i32> @intrinsic_vdota4su_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4su_vx_nxv1i32_i32:
+define <vscale x 1 x i32> @intrinsic_vdot4asu_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4asu_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma
-; CHECK-NEXT: vdota4su.vx v8, v9, a0
+; CHECK-NEXT: vdot4asu.vx v8, v9, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vdota4su.nxv1i32.i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i32 %2,
@@ -187,14 +187,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vdota4su_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4su_vx_nxv2i32_i32:
+define <vscale x 2 x i32> @intrinsic_vdot4asu_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4asu_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma
-; CHECK-NEXT: vdota4su.vx v8, v9, a0
+; CHECK-NEXT: vdot4asu.vx v8, v9, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vdota4su.nxv2i32.i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i32 %2,
@@ -203,14 +203,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vdota4su_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4su_vx_nxv4i32_i32:
+define <vscale x 4 x i32> @intrinsic_vdot4asu_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4asu_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma
-; CHECK-NEXT: vdota4su.vx v8, v10, a0
+; CHECK-NEXT: vdot4asu.vx v8, v10, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vdota4su.nxv4i32.i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i32 %2,
@@ -219,14 +219,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vdota4su_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4su_vx_nxv8i32_i32:
+define <vscale x 8 x i32> @intrinsic_vdot4asu_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4asu_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma
-; CHECK-NEXT: vdota4su.vx v8, v12, a0
+; CHECK-NEXT: vdot4asu.vx v8, v12, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vdota4su.nxv8i32.i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i32 %2,
@@ -235,14 +235,14 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vdota4su_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4su_vx_nxv16i32_i32:
+define <vscale x 16 x i32> @intrinsic_vdot4asu_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4asu_vx_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
-; CHECK-NEXT: vdota4su.vx v8, v16, a0
+; CHECK-NEXT: vdot4asu.vx v8, v16, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vdota4su.nxv16i32.i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i32 %2,
@@ -251,14 +251,14 @@ entry:
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i32> @intrinsic_vdota4su_mask_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4su_mask_vx_nxv1i32_i32:
+define <vscale x 1 x i32> @intrinsic_vdot4asu_mask_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4asu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vdota4su.vx v8, v9, a0, v0.t
+; CHECK-NEXT: vdot4asu.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vdota4su.mask.nxv1i32.i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i32 %2,
@@ -268,14 +268,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vdota4su_mask_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4su_mask_vx_nxv2i32_i32:
+define <vscale x 2 x i32> @intrinsic_vdot4asu_mask_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4asu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vdota4su.vx v8, v9, a0, v0.t
+; CHECK-NEXT: vdot4asu.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vdota4su.mask.nxv2i32.i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i32 %2,
@@ -285,14 +285,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vdota4su_mask_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4su_mask_vx_nxv4i32_i32:
+define <vscale x 4 x i32> @intrinsic_vdot4asu_mask_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4asu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
-; CHECK-NEXT: vdota4su.vx v8, v10, a0, v0.t
+; CHECK-NEXT: vdot4asu.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vdota4su.mask.nxv4i32.i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i32 %2,
@@ -302,14 +302,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vdota4su_mask_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4su_mask_vx_nxv8i32_i32:
+define <vscale x 8 x i32> @intrinsic_vdot4asu_mask_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4asu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
-; CHECK-NEXT: vdota4su.vx v8, v12, a0, v0.t
+; CHECK-NEXT: vdot4asu.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vdota4su.mask.nxv8i32.i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.mask.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i32 %2,
@@ -319,14 +319,14 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vdota4su_mask_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4su_mask_vx_nxv16i32_i32:
+define <vscale x 16 x i32> @intrinsic_vdot4asu_mask_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4asu_mask_vx_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
-; CHECK-NEXT: vdota4su.vx v8, v16, a0, v0.t
+; CHECK-NEXT: vdot4asu.vx v8, v16, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vdota4su.mask.nxv16i32.i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.mask.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i32 %2,
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdota4u.ll b/llvm/test/CodeGen/RISCV/rvv/vdot4au.ll
similarity index 62%
rename from llvm/test/CodeGen/RISCV/rvv/vdota4u.ll
rename to llvm/test/CodeGen/RISCV/rvv/vdot4au.ll
index f26027eef1807..7b04ca7c0cbd2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdota4u.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdot4au.ll
@@ -4,14 +4,14 @@
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+experimental-zvdot4a8i \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-define <vscale x 1 x i32> @intrinsic_vdota4u_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4u_vv_nxv1i32_nxv1i32:
+define <vscale x 1 x i32> @intrinsic_vdot4au_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4au_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
-; CHECK-NEXT: vdota4u.vv v8, v9, v10
+; CHECK-NEXT: vdot4au.vv v8, v9, v10
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vdota4u.nxv1i32.nxv1i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
@@ -20,14 +20,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vdota4u_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4u_vv_nxv2i32_nxv2i32:
+define <vscale x 2 x i32> @intrinsic_vdot4au_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4au_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
-; CHECK-NEXT: vdota4u.vv v8, v9, v10
+; CHECK-NEXT: vdot4au.vv v8, v9, v10
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.nxv2i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
@@ -36,14 +36,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vdota4u_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4u_vv_nxv4i32_nxv4i32:
+define <vscale x 4 x i32> @intrinsic_vdot4au_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4au_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
-; CHECK-NEXT: vdota4u.vv v8, v10, v12
+; CHECK-NEXT: vdot4au.vv v8, v10, v12
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vdota4u.nxv4i32.nxv4i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
@@ -52,14 +52,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vdota4u_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4u_vv_nxv8i32_nxv8i32:
+define <vscale x 8 x i32> @intrinsic_vdot4au_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4au_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
-; CHECK-NEXT: vdota4u.vv v8, v12, v16
+; CHECK-NEXT: vdot4au.vv v8, v12, v16
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vdota4u.nxv8i32.nxv8i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
@@ -68,15 +68,15 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vdota4u_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4u_vv_nxv16i32_nxv16i32:
+define <vscale x 16 x i32> @intrinsic_vdot4au_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4au_vv_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
-; CHECK-NEXT: vdota4u.vv v8, v16, v24
+; CHECK-NEXT: vdot4au.vv v8, v16, v24
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vdota4u.nxv16i32.nxv16i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
@@ -85,14 +85,14 @@ entry:
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i32> @intrinsic_vdota4u_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4u_mask_vv_nxv1i32_nxv1i32:
+define <vscale x 1 x i32> @intrinsic_vdot4au_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4au_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
-; CHECK-NEXT: vdota4u.vv v8, v9, v10, v0.t
+; CHECK-NEXT: vdot4au.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.nxv1i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
@@ -102,14 +102,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vdota4u_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4u_mask_vv_nxv2i32_nxv2i32:
+define <vscale x 2 x i32> @intrinsic_vdot4au_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4au_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
-; CHECK-NEXT: vdota4u.vv v8, v9, v10, v0.t
+; CHECK-NEXT: vdot4au.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.nxv2i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
@@ -119,14 +119,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vdota4u_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4u_mask_vv_nxv4i32_nxv4i32:
+define <vscale x 4 x i32> @intrinsic_vdot4au_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4au_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
-; CHECK-NEXT: vdota4u.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vdot4au.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.nxv4i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
@@ -136,14 +136,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vdota4u_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4u_mask_vv_nxv8i32_nxv8i32:
+define <vscale x 8 x i32> @intrinsic_vdot4au_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4au_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
-; CHECK-NEXT: vdota4u.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vdot4au.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.nxv8i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdot4au.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
@@ -153,15 +153,15 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vdota4u_mask_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4u_mask_vv_nxv16i32_nxv16i32:
+define <vscale x 16 x i32> @intrinsic_vdot4au_mask_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4au_mask_vv_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
-; CHECK-NEXT: vdota4u.vv v8, v16, v24, v0.t
+; CHECK-NEXT: vdot4au.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.nxv16i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdot4au.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
@@ -171,14 +171,14 @@ entry:
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i32> @intrinsic_vdota4u_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4u_vx_nxv1i32_i32:
+define <vscale x 1 x i32> @intrinsic_vdot4au_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4au_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma
-; CHECK-NEXT: vdota4u.vx v8, v9, a0
+; CHECK-NEXT: vdot4au.vx v8, v9, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vdota4u.nxv1i32.i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i32 %2,
@@ -187,14 +187,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vdota4u_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4u_vx_nxv2i32_i32:
+define <vscale x 2 x i32> @intrinsic_vdot4au_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4au_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma
-; CHECK-NEXT: vdota4u.vx v8, v9, a0
+; CHECK-NEXT: vdot4au.vx v8, v9, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vdota4u.nxv2i32.i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i32 %2,
@@ -203,14 +203,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vdota4u_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4u_vx_nxv4i32_i32:
+define <vscale x 4 x i32> @intrinsic_vdot4au_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4au_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma
-; CHECK-NEXT: vdota4u.vx v8, v10, a0
+; CHECK-NEXT: vdot4au.vx v8, v10, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vdota4u.nxv4i32.i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i32 %2,
@@ -219,14 +219,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vdota4u_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4u_vx_nxv8i32_i32:
+define <vscale x 8 x i32> @intrinsic_vdot4au_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4au_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma
-; CHECK-NEXT: vdota4u.vx v8, v12, a0
+; CHECK-NEXT: vdot4au.vx v8, v12, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vdota4u.nxv8i32.i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i32 %2,
@@ -235,14 +235,14 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vdota4u_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4u_vx_nxv16i32_i32:
+define <vscale x 16 x i32> @intrinsic_vdot4au_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4au_vx_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
-; CHECK-NEXT: vdota4u.vx v8, v16, a0
+; CHECK-NEXT: vdot4au.vx v8, v16, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vdota4u.nxv16i32.i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i32 %2,
@@ -251,14 +251,14 @@ entry:
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i32> @intrinsic_vdota4u_mask_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4u_mask_vx_nxv1i32_i32:
+define <vscale x 1 x i32> @intrinsic_vdot4au_mask_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4au_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vdota4u.vx v8, v9, a0, v0.t
+; CHECK-NEXT: vdot4au.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vdota4u.mask.nxv1i32.i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i32 %2,
@@ -268,14 +268,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vdota4u_mask_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4u_mask_vx_nxv2i32_i32:
+define <vscale x 2 x i32> @intrinsic_vdot4au_mask_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4au_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vdota4u.vx v8, v9, a0, v0.t
+; CHECK-NEXT: vdot4au.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vdota4u.mask.nxv2i32.i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i32 %2,
@@ -285,14 +285,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vdota4u_mask_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4u_mask_vx_nxv4i32_i32:
+define <vscale x 4 x i32> @intrinsic_vdot4au_mask_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4au_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
-; CHECK-NEXT: vdota4u.vx v8, v10, a0, v0.t
+; CHECK-NEXT: vdot4au.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vdota4u.mask.nxv4i32.i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i32 %2,
@@ -302,14 +302,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vdota4u_mask_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4u_mask_vx_nxv8i32_i32:
+define <vscale x 8 x i32> @intrinsic_vdot4au_mask_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4au_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
-; CHECK-NEXT: vdota4u.vx v8, v12, a0, v0.t
+; CHECK-NEXT: vdot4au.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vdota4u.mask.nxv8i32.i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdot4au.mask.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i32 %2,
@@ -319,14 +319,14 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vdota4u_mask_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4u_mask_vx_nxv16i32_i32:
+define <vscale x 16 x i32> @intrinsic_vdot4au_mask_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4au_mask_vx_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
-; CHECK-NEXT: vdota4u.vx v8, v16, a0, v0.t
+; CHECK-NEXT: vdot4au.vx v8, v16, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vdota4u.mask.nxv16i32.i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdot4au.mask.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i32 %2,
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdota4us.ll b/llvm/test/CodeGen/RISCV/rvv/vdot4aus.ll
similarity index 62%
rename from llvm/test/CodeGen/RISCV/rvv/vdota4us.ll
rename to llvm/test/CodeGen/RISCV/rvv/vdot4aus.ll
index 5b84572a790de..b52219490adda 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdota4us.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdot4aus.ll
@@ -4,14 +4,14 @@
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+experimental-zvdot4a8i \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-define <vscale x 1 x i32> @intrinsic_vdota4us_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4us_vx_nxv1i32_i32:
+define <vscale x 1 x i32> @intrinsic_vdot4aus_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4aus_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma
-; CHECK-NEXT: vdota4us.vx v8, v9, a0
+; CHECK-NEXT: vdot4aus.vx v8, v9, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vdota4us.nxv1i32.i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i32 %2,
@@ -20,14 +20,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vdota4us_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4us_vx_nxv2i32_i32:
+define <vscale x 2 x i32> @intrinsic_vdot4aus_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4aus_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma
-; CHECK-NEXT: vdota4us.vx v8, v9, a0
+; CHECK-NEXT: vdot4aus.vx v8, v9, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vdota4us.nxv2i32.i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i32 %2,
@@ -36,14 +36,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vdota4us_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4us_vx_nxv4i32_i32:
+define <vscale x 4 x i32> @intrinsic_vdot4aus_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4aus_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma
-; CHECK-NEXT: vdota4us.vx v8, v10, a0
+; CHECK-NEXT: vdot4aus.vx v8, v10, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vdota4us.nxv4i32.i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i32 %2,
@@ -52,14 +52,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vdota4us_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4us_vx_nxv8i32_i32:
+define <vscale x 8 x i32> @intrinsic_vdot4aus_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4aus_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma
-; CHECK-NEXT: vdota4us.vx v8, v12, a0
+; CHECK-NEXT: vdot4aus.vx v8, v12, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vdota4us.nxv8i32.i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i32 %2,
@@ -68,14 +68,14 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vdota4us_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4us_vx_nxv16i32_i32:
+define <vscale x 16 x i32> @intrinsic_vdot4aus_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4aus_vx_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
-; CHECK-NEXT: vdota4us.vx v8, v16, a0
+; CHECK-NEXT: vdot4aus.vx v8, v16, a0
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vdota4us.nxv16i32.i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i32 %2,
@@ -84,14 +84,14 @@ entry:
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i32> @intrinsic_vdota4us_mask_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4us_mask_vx_nxv1i32_i32:
+define <vscale x 1 x i32> @intrinsic_vdot4aus_mask_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4aus_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vdota4us.vx v8, v9, a0, v0.t
+; CHECK-NEXT: vdot4aus.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vdota4us.mask.nxv1i32.i32(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i32 %2,
@@ -101,14 +101,14 @@ entry:
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vdota4us_mask_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4us_mask_vx_nxv2i32_i32:
+define <vscale x 2 x i32> @intrinsic_vdot4aus_mask_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4aus_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vdota4us.vx v8, v9, a0, v0.t
+; CHECK-NEXT: vdot4aus.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vdota4us.mask.nxv2i32.i32(
+ %a = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i32 %2,
@@ -118,14 +118,14 @@ entry:
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vdota4us_mask_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4us_mask_vx_nxv4i32_i32:
+define <vscale x 4 x i32> @intrinsic_vdot4aus_mask_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4aus_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
-; CHECK-NEXT: vdota4us.vx v8, v10, a0, v0.t
+; CHECK-NEXT: vdot4aus.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vdota4us.mask.nxv4i32.i32(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i32 %2,
@@ -135,14 +135,14 @@ entry:
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vdota4us_mask_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4us_mask_vx_nxv8i32_i32:
+define <vscale x 8 x i32> @intrinsic_vdot4aus_mask_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4aus_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
-; CHECK-NEXT: vdota4us.vx v8, v12, a0, v0.t
+; CHECK-NEXT: vdot4aus.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vdota4us.mask.nxv8i32.i32(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.mask.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i32 %2,
@@ -152,14 +152,14 @@ entry:
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vdota4us_mask_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
-; CHECK-LABEL: intrinsic_vdota4us_mask_vx_nxv16i32_i32:
+define <vscale x 16 x i32> @intrinsic_vdot4aus_mask_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vdot4aus_mask_vx_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
-; CHECK-NEXT: vdota4us.vx v8, v16, a0, v0.t
+; CHECK-NEXT: vdot4aus.vx v8, v16, a0, v0.t
; CHECK-NEXT: ret
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vdota4us.mask.nxv16i32.i32(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.mask.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i32 %2,
diff --git a/llvm/test/CodeGen/RISCV/rvv/zvdot4a8i-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/zvdot4a8i-sdnode.ll
index 7a54cee626e4b..f12078dae5e1f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/zvdot4a8i-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/zvdot4a8i-sdnode.ll
@@ -4,8 +4,8 @@
; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvdot4a8i -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,DOT,DOT32
; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvdot4a8i -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,DOT,DOT64
-define i32 @vdota4_vv(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
-; NODOT-LABEL: vdota4_vv:
+define i32 @vdot4a_vv(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; NODOT-LABEL: vdot4a_vv:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; NODOT-NEXT: vsext.vf2 v16, v8
@@ -17,11 +17,11 @@ define i32 @vdota4_vv(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4_vv:
+; DOT-LABEL: vdot4a_vv:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vdota4.vv v12, v8, v10
+; DOT-NEXT: vdot4a.vv v12, v8, v10
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -34,8 +34,8 @@ entry:
ret i32 %res
}
-define i32 @vdota4_vx_constant(<vscale x 16 x i8> %a) {
-; CHECK-LABEL: vdota4_vx_constant:
+define i32 @vdot4a_vx_constant(<vscale x 16 x i8> %a) {
+; CHECK-LABEL: vdot4a_vx_constant:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vsext.vf2 v16, v8
@@ -53,8 +53,8 @@ entry:
ret i32 %res
}
-define i32 @vdota4_vx_constant_swapped(<vscale x 16 x i8> %a) {
-; CHECK-LABEL: vdota4_vx_constant_swapped:
+define i32 @vdot4a_vx_constant_swapped(<vscale x 16 x i8> %a) {
+; CHECK-LABEL: vdot4a_vx_constant_swapped:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vsext.vf2 v16, v8
@@ -72,8 +72,8 @@ entry:
ret i32 %res
}
-define i32 @vdota4u_vv(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
-; NODOT-LABEL: vdota4u_vv:
+define i32 @vdot4au_vv(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; NODOT-LABEL: vdot4au_vv:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; NODOT-NEXT: vwmulu.vv v12, v8, v10
@@ -85,11 +85,11 @@ define i32 @vdota4u_vv(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4u_vv:
+; DOT-LABEL: vdot4au_vv:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vdota4u.vv v12, v8, v10
+; DOT-NEXT: vdot4au.vv v12, v8, v10
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -102,8 +102,8 @@ entry:
ret i32 %res
}
-define i32 @vdota4u_vx_constant(<vscale x 16 x i8> %a) {
-; CHECK-LABEL: vdota4u_vx_constant:
+define i32 @vdot4au_vx_constant(<vscale x 16 x i8> %a) {
+; CHECK-LABEL: vdot4au_vx_constant:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vzext.vf2 v16, v8
@@ -121,8 +121,8 @@ entry:
ret i32 %res
}
-define i32 @vdota4su_vv(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
-; NODOT-LABEL: vdota4su_vv:
+define i32 @vdot4asu_vv(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; NODOT-LABEL: vdot4asu_vv:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; NODOT-NEXT: vsext.vf2 v16, v8
@@ -134,11 +134,11 @@ define i32 @vdota4su_vv(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4su_vv:
+; DOT-LABEL: vdot4asu_vv:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vdota4su.vv v12, v8, v10
+; DOT-NEXT: vdot4asu.vv v12, v8, v10
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -151,8 +151,8 @@ entry:
ret i32 %res
}
-define i32 @vdota4su_vv_swapped(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
-; NODOT-LABEL: vdota4su_vv_swapped:
+define i32 @vdot4asu_vv_swapped(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; NODOT-LABEL: vdot4asu_vv_swapped:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; NODOT-NEXT: vsext.vf2 v16, v8
@@ -164,11 +164,11 @@ define i32 @vdota4su_vv_swapped(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4su_vv_swapped:
+; DOT-LABEL: vdot4asu_vv_swapped:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vdota4su.vv v12, v8, v10
+; DOT-NEXT: vdot4asu.vv v12, v8, v10
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -236,7 +236,7 @@ define i32 @reduce_of_sext(<vscale x 16 x i8> %a) {
; DOT-NEXT: vmv.v.i v10, 1
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vdota4.vv v12, v8, v10
+; DOT-NEXT: vdot4a.vv v12, v8, v10
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -263,7 +263,7 @@ define i32 @reduce_of_zext(<vscale x 16 x i8> %a) {
; DOT-NEXT: vmv.v.i v10, 1
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vdota4u.vv v12, v8, v10
+; DOT-NEXT: vdot4au.vv v12, v8, v10
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -274,8 +274,8 @@ entry:
ret i32 %res
}
-define i32 @vdota4_vv_accum(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i32> %x) {
-; NODOT-LABEL: vdota4_vv_accum:
+define i32 @vdot4a_vv_accum(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i32> %x) {
+; NODOT-LABEL: vdot4a_vv_accum:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; NODOT-NEXT: vsext.vf2 v12, v8
@@ -287,11 +287,11 @@ define i32 @vdota4_vv_accum(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscal
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4_vv_accum:
+; DOT-LABEL: vdot4a_vv_accum:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.s.x v12, zero
-; DOT-NEXT: vdota4.vv v16, v8, v10
+; DOT-NEXT: vdot4a.vv v16, v8, v10
; DOT-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; DOT-NEXT: vredsum.vs v8, v16, v12
; DOT-NEXT: vmv.x.s a0, v8
@@ -305,8 +305,8 @@ entry:
ret i32 %sum
}
-define i32 @vdota4u_vv_accum(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i32> %x) {
-; NODOT-LABEL: vdota4u_vv_accum:
+define i32 @vdot4au_vv_accum(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i32> %x) {
+; NODOT-LABEL: vdot4au_vv_accum:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; NODOT-NEXT: vwmulu.vv v12, v8, v10
@@ -318,11 +318,11 @@ define i32 @vdota4u_vv_accum(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vsca
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4u_vv_accum:
+; DOT-LABEL: vdot4au_vv_accum:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.s.x v12, zero
-; DOT-NEXT: vdota4u.vv v16, v8, v10
+; DOT-NEXT: vdot4au.vv v16, v8, v10
; DOT-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; DOT-NEXT: vredsum.vs v8, v16, v12
; DOT-NEXT: vmv.x.s a0, v8
@@ -336,8 +336,8 @@ entry:
ret i32 %sum
}
-define i32 @vdota4su_vv_accum(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i32> %x) {
-; NODOT-LABEL: vdota4su_vv_accum:
+define i32 @vdot4asu_vv_accum(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i32> %x) {
+; NODOT-LABEL: vdot4asu_vv_accum:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; NODOT-NEXT: vsext.vf2 v12, v8
@@ -349,11 +349,11 @@ define i32 @vdota4su_vv_accum(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vsc
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4su_vv_accum:
+; DOT-LABEL: vdot4asu_vv_accum:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.s.x v12, zero
-; DOT-NEXT: vdota4su.vv v16, v8, v10
+; DOT-NEXT: vdot4asu.vv v16, v8, v10
; DOT-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; DOT-NEXT: vredsum.vs v8, v16, v12
; DOT-NEXT: vmv.x.s a0, v8
@@ -367,8 +367,8 @@ entry:
ret i32 %sum
}
-define i32 @vdota4_vv_scalar_add(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 %x) {
-; NODOT-LABEL: vdota4_vv_scalar_add:
+define i32 @vdot4a_vv_scalar_add(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 %x) {
+; NODOT-LABEL: vdot4a_vv_scalar_add:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; NODOT-NEXT: vsext.vf2 v16, v8
@@ -380,11 +380,11 @@ define i32 @vdota4_vv_scalar_add(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4_vv_scalar_add:
+; DOT-LABEL: vdot4a_vv_scalar_add:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vdota4.vv v12, v8, v10
+; DOT-NEXT: vdot4a.vv v12, v8, v10
; DOT-NEXT: vmv.s.x v8, a0
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -398,8 +398,8 @@ entry:
ret i32 %add
}
-define i32 @vdota4u_vv_scalar_add(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 %x) {
-; NODOT-LABEL: vdota4u_vv_scalar_add:
+define i32 @vdot4au_vv_scalar_add(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 %x) {
+; NODOT-LABEL: vdot4au_vv_scalar_add:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; NODOT-NEXT: vwmulu.vv v12, v8, v10
@@ -411,11 +411,11 @@ define i32 @vdota4u_vv_scalar_add(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b,
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4u_vv_scalar_add:
+; DOT-LABEL: vdot4au_vv_scalar_add:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vdota4u.vv v12, v8, v10
+; DOT-NEXT: vdot4au.vv v12, v8, v10
; DOT-NEXT: vmv.s.x v8, a0
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -429,8 +429,8 @@ entry:
ret i32 %add
}
-define i32 @vdota4su_vv_scalar_add(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 %x) {
-; NODOT-LABEL: vdota4su_vv_scalar_add:
+define i32 @vdot4asu_vv_scalar_add(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 %x) {
+; NODOT-LABEL: vdot4asu_vv_scalar_add:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; NODOT-NEXT: vsext.vf2 v16, v8
@@ -442,11 +442,11 @@ define i32 @vdota4su_vv_scalar_add(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b,
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4su_vv_scalar_add:
+; DOT-LABEL: vdot4asu_vv_scalar_add:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vdota4su.vv v12, v8, v10
+; DOT-NEXT: vdot4asu.vv v12, v8, v10
; DOT-NEXT: vmv.s.x v8, a0
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -460,8 +460,8 @@ entry:
ret i32 %add
}
-define i32 @vdota4_vv_split(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d) {
-; NODOT-LABEL: vdota4_vv_split:
+define i32 @vdot4a_vv_split(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d) {
+; NODOT-LABEL: vdot4a_vv_split:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; NODOT-NEXT: vsext.vf2 v16, v8
@@ -476,12 +476,12 @@ define i32 @vdota4_vv_split(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscal
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: vdota4_vv_split:
+; DOT-LABEL: vdot4a_vv_split:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v16, 0
-; DOT-NEXT: vdota4.vv v16, v8, v10
-; DOT-NEXT: vdota4.vv v16, v12, v14
+; DOT-NEXT: vdot4a.vv v16, v8, v10
+; DOT-NEXT: vdot4a.vv v16, v12, v14
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v16, v8
; DOT-NEXT: vmv.x.s a0, v8
@@ -521,7 +521,7 @@ define <vscale x 1 x i32> @partial_reduce_nf2(<vscale x 4 x i8> %a, <vscale x 4
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vdota4.vv v10, v8, v9
+; DOT-NEXT: vdot4a.vv v10, v8, v9
; DOT-NEXT: vmv1r.v v8, v10
; DOT-NEXT: ret
entry:
@@ -549,7 +549,7 @@ define <vscale x 2 x i32> @partial_reduce_m1(<vscale x 8 x i8> %a, <vscale x 8 x
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vdota4.vv v10, v8, v9
+; DOT-NEXT: vdot4a.vv v10, v8, v9
; DOT-NEXT: vmv.v.v v8, v10
; DOT-NEXT: ret
entry:
@@ -577,7 +577,7 @@ define <vscale x 4 x i32> @partial_reduce_m2(<vscale x 16 x i8> %a, <vscale x 16
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 0
-; DOT-NEXT: vdota4.vv v12, v8, v10
+; DOT-NEXT: vdot4a.vv v12, v8, v10
; DOT-NEXT: vmv.v.v v8, v12
; DOT-NEXT: ret
entry:
@@ -608,7 +608,7 @@ define <vscale x 8 x i32> @partial_reduce_m4(<vscale x 32 x i8> %a, <vscale x 32
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; DOT-NEXT: vmv.v.i v16, 0
-; DOT-NEXT: vdota4.vv v16, v8, v12
+; DOT-NEXT: vdot4a.vv v16, v8, v12
; DOT-NEXT: vmv.v.v v8, v16
; DOT-NEXT: ret
entry:
@@ -657,7 +657,7 @@ define <vscale x 16 x i32> @partial_reduce_m8(<vscale x 64 x i8> %a, <vscale x 6
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; DOT-NEXT: vmv.v.i v24, 0
-; DOT-NEXT: vdota4.vv v24, v8, v16
+; DOT-NEXT: vdot4a.vv v24, v8, v16
; DOT-NEXT: vmv.v.v v8, v24
; DOT-NEXT: ret
entry:
@@ -803,7 +803,7 @@ define <vscale x 32 x i32> @partial_reduce_m16(<vscale x 128 x i8> %a, <vscale x
; DOT-NEXT: add a0, sp, a0
; DOT-NEXT: addi a0, a0, 16
; DOT-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; DOT-NEXT: vdota4.vv v0, v16, v8
+; DOT-NEXT: vdot4a.vv v0, v16, v8
; DOT-NEXT: csrr a0, vlenb
; DOT-NEXT: slli a0, a0, 4
; DOT-NEXT: add a0, sp, a0
@@ -811,7 +811,7 @@ define <vscale x 32 x i32> @partial_reduce_m16(<vscale x 128 x i8> %a, <vscale x
; DOT-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; DOT-NEXT: addi a0, sp, 16
; DOT-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; DOT-NEXT: vdota4.vv v24, v8, v16
+; DOT-NEXT: vdot4a.vv v24, v8, v16
; DOT-NEXT: vmv.v.v v8, v0
; DOT-NEXT: vmv.v.v v16, v24
; DOT-NEXT: csrr a0, vlenb
@@ -849,7 +849,7 @@ define <vscale x 4 x i32> @partial_reduce_accum(<vscale x 16 x i8> %a, <vscale x
; DOT-LABEL: partial_reduce_accum:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; DOT-NEXT: vdota4.vv v12, v8, v10
+; DOT-NEXT: vdot4a.vv v12, v8, v10
; DOT-NEXT: vmv.v.v v8, v12
; DOT-NEXT: ret
entry:
@@ -876,8 +876,8 @@ entry:
ret <vscale x 16 x i32> %res
}
-define <vscale x 1 x i32> @partial_reduce_vdota4u(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) {
-; NODOT-LABEL: partial_reduce_vdota4u:
+define <vscale x 1 x i32> @partial_reduce_vdot4au(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) {
+; NODOT-LABEL: partial_reduce_vdot4au:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; NODOT-NEXT: vwmulu.vv v10, v8, v9
@@ -894,11 +894,11 @@ define <vscale x 1 x i32> @partial_reduce_vdota4u(<vscale x 4 x i8> %a, <vscale
; NODOT-NEXT: vadd.vv v8, v9, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: partial_reduce_vdota4u:
+; DOT-LABEL: partial_reduce_vdot4au:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vdota4u.vv v10, v8, v9
+; DOT-NEXT: vdot4au.vv v10, v8, v9
; DOT-NEXT: vmv1r.v v8, v10
; DOT-NEXT: ret
entry:
@@ -909,8 +909,8 @@ entry:
ret <vscale x 1 x i32> %res
}
-define <vscale x 1 x i32> @partial_reduce_vdota4su(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) {
-; NODOT-LABEL: partial_reduce_vdota4su:
+define <vscale x 1 x i32> @partial_reduce_vdot4asu(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) {
+; NODOT-LABEL: partial_reduce_vdot4asu:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; NODOT-NEXT: vsext.vf2 v10, v8
@@ -927,11 +927,11 @@ define <vscale x 1 x i32> @partial_reduce_vdota4su(<vscale x 4 x i8> %a, <vscale
; NODOT-NEXT: vadd.vv v8, v9, v8
; NODOT-NEXT: ret
;
-; DOT-LABEL: partial_reduce_vdota4su:
+; DOT-LABEL: partial_reduce_vdot4asu:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vdota4su.vv v10, v8, v9
+; DOT-NEXT: vdot4asu.vv v10, v8, v9
; DOT-NEXT: vmv1r.v v8, v10
; DOT-NEXT: ret
entry:
@@ -960,7 +960,7 @@ define <vscale x 4 x i32> @partial_of_sext(<vscale x 16 x i8> %a) {
; DOT-NEXT: vmv.v.i v12, 1
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vdota4.vv v10, v8, v12
+; DOT-NEXT: vdot4a.vv v10, v8, v12
; DOT-NEXT: vmv.v.v v8, v10
; DOT-NEXT: ret
entry:
@@ -986,7 +986,7 @@ define <vscale x 4 x i32> @partial_of_zext(<vscale x 16 x i8> %a) {
; DOT-NEXT: vmv.v.i v12, 1
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
-; DOT-NEXT: vdota4u.vv v10, v8, v12
+; DOT-NEXT: vdot4au.vv v10, v8, v12
; DOT-NEXT: vmv.v.v v8, v10
; DOT-NEXT: ret
entry:
@@ -1018,7 +1018,7 @@ define <vscale x 2 x i32> @partial_reduce_select(<vscale x 8 x i8> %a, <vscale x
; DOT-NEXT: vmerge.vvm v10, v10, v9, v0
; DOT-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v9, 0
-; DOT-NEXT: vdota4.vv v9, v8, v10
+; DOT-NEXT: vdot4a.vv v9, v8, v10
; DOT-NEXT: vmv.v.v v8, v9
; DOT-NEXT: ret
entry:
diff --git a/llvm/test/MC/RISCV/rvv/zvdot4a8i-invalid.s b/llvm/test/MC/RISCV/rvv/zvdot4a8i-invalid.s
index bca90029286e2..b2d90550ecffd 100644
--- a/llvm/test/MC/RISCV/rvv/zvdot4a8i-invalid.s
+++ b/llvm/test/MC/RISCV/rvv/zvdot4a8i-invalid.s
@@ -1,10 +1,10 @@
# RUN: not llvm-mc -triple=riscv64 --mattr=+experimental-zvdot4a8i %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-vdota4.vv v0, v2, v4, v0.t
+vdot4a.vv v0, v2, v4, v0.t
# CHECK-ERROR: the destination vector register group cannot overlap the mask register
-# CHECK-ERROR-LABEL: vdota4.vv v0, v2, v4, v0.t
+# CHECK-ERROR-LABEL: vdot4a.vv v0, v2, v4, v0.t
-vdota4.vx v0, v2, a0, v0.t
+vdot4a.vx v0, v2, a0, v0.t
# CHECK-ERROR: the destination vector register group cannot overlap the mask register
-# CHECK-ERROR-LABEL: vdota4.vx v0, v2, a0, v0.t
+# CHECK-ERROR-LABEL: vdot4a.vx v0, v2, a0, v0.t
diff --git a/llvm/test/MC/RISCV/rvv/zvdot4a8i.s b/llvm/test/MC/RISCV/rvv/zvdot4a8i.s
index 8797f621b360f..fe217bb6d72f6 100644
--- a/llvm/test/MC/RISCV/rvv/zvdot4a8i.s
+++ b/llvm/test/MC/RISCV/rvv/zvdot4a8i.s
@@ -6,72 +6,72 @@
# RUN: | llvm-objdump -d --mattr=+experimental-zvdot4a8i - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-vdota4.vv v8, v4, v20, v0.t
-# CHECK-INST: vdota4.vv v8, v4, v20, v0.t
+vdot4a.vv v8, v4, v20, v0.t
+# CHECK-INST: vdot4a.vv v8, v4, v20, v0.t
# CHECK-ENCODING: [0x57,0x24,0x4a,0xb0]
# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers){{$}}
-vdota4.vv v8, v4, v20
-# CHECK-INST: vdota4.vv v8, v4, v20
+vdot4a.vv v8, v4, v20
+# CHECK-INST: vdot4a.vv v8, v4, v20
# CHECK-ENCODING: [0x57,0x24,0x4a,0xb2]
# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers){{$}}
-vdota4u.vv v8, v4, v20, v0.t
-# CHECK-INST: vdota4u.vv v8, v4, v20, v0.t
+vdot4au.vv v8, v4, v20, v0.t
+# CHECK-INST: vdot4au.vv v8, v4, v20, v0.t
# CHECK-ENCODING: [0x57,0x24,0x4a,0xa0]
# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers){{$}}
-vdota4u.vv v8, v4, v20
-# CHECK-INST: vdota4u.vv v8, v4, v20
+vdot4au.vv v8, v4, v20
+# CHECK-INST: vdot4au.vv v8, v4, v20
# CHECK-ENCODING: [0x57,0x24,0x4a,0xa2]
# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers){{$}}
-vdota4su.vv v8, v4, v20, v0.t
-# CHECK-INST: vdota4su.vv v8, v4, v20, v0.t
+vdot4asu.vv v8, v4, v20, v0.t
+# CHECK-INST: vdot4asu.vv v8, v4, v20, v0.t
# CHECK-ENCODING: [0x57,0x24,0x4a,0xa8]
# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers){{$}}
-vdota4su.vv v8, v4, v20
-# CHECK-INST: vdota4su.vv v8, v4, v20
+vdot4asu.vv v8, v4, v20
+# CHECK-INST: vdot4asu.vv v8, v4, v20
# CHECK-ENCODING: [0x57,0x24,0x4a,0xaa]
# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers){{$}}
-vdota4.vx v8, v4, s4, v0.t
-# CHECK-INST: vdota4.vx v8, v4, s4, v0.t
+vdot4a.vx v8, v4, s4, v0.t
+# CHECK-INST: vdot4a.vx v8, v4, s4, v0.t
# CHECK-ENCODING: [0x57,0x64,0x4a,0xb0]
# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers){{$}}
-vdota4.vx v8, v4, s4
-# CHECK-INST: vdota4.vx v8, v4, s4
+vdot4a.vx v8, v4, s4
+# CHECK-INST: vdot4a.vx v8, v4, s4
# CHECK-ENCODING: [0x57,0x64,0x4a,0xb2]
# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers){{$}}
-vdota4u.vx v8, v4, s4, v0.t
-# CHECK-INST: vdota4u.vx v8, v4, s4, v0.t
+vdot4au.vx v8, v4, s4, v0.t
+# CHECK-INST: vdot4au.vx v8, v4, s4, v0.t
# CHECK-ENCODING: [0x57,0x64,0x4a,0xa0]
# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers){{$}}
-vdota4u.vx v8, v4, s4
-# CHECK-INST: vdota4u.vx v8, v4, s4
+vdot4au.vx v8, v4, s4
+# CHECK-INST: vdot4au.vx v8, v4, s4
# CHECK-ENCODING: [0x57,0x64,0x4a,0xa2]
# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers){{$}}
-vdota4su.vx v8, v4, s4, v0.t
-# CHECK-INST: vdota4su.vx v8, v4, s4, v0.t
+vdot4asu.vx v8, v4, s4, v0.t
+# CHECK-INST: vdot4asu.vx v8, v4, s4, v0.t
# CHECK-ENCODING: [0x57,0x64,0x4a,0xa8]
# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers){{$}}
-vdota4su.vx v8, v4, s4
-# CHECK-INST: vdota4su.vx v8, v4, s4
+vdot4asu.vx v8, v4, s4
+# CHECK-INST: vdot4asu.vx v8, v4, s4
# CHECK-ENCODING: [0x57,0x64,0x4a,0xaa]
# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers){{$}}
-vdota4us.vx v8, v4, s4, v0.t
-# CHECK-INST: vdota4us.vx v8, v4, s4, v0.t
+vdot4aus.vx v8, v4, s4, v0.t
+# CHECK-INST: vdot4aus.vx v8, v4, s4, v0.t
# CHECK-ENCODING: [0x57,0x64,0x4a,0xb8]
# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers){{$}}
-vdota4us.vx v8, v4, s4
-# CHECK-INST: vdota4us.vx v8, v4, s4
+vdot4aus.vx v8, v4, s4
+# CHECK-INST: vdot4aus.vx v8, v4, s4
# CHECK-ENCODING: [0x57,0x64,0x4a,0xba]
# CHECK-ERROR: instruction requires the following: 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers){{$}}
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll b/llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
index 49144f4ad048c..2c820e8af6ff6 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
@@ -9,8 +9,8 @@
target triple = "riscv64-none-unknown-elf"
-define i32 @vdota4(ptr %a, ptr %b) #0 {
-; V-LABEL: define i32 @vdota4(
+define i32 @vdot4a(ptr %a, ptr %b) #0 {
+; V-LABEL: define i32 @vdot4a(
; V-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
; V-NEXT: entry:
; V-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
@@ -43,7 +43,7 @@ define i32 @vdota4(ptr %a, ptr %b) #0 {
; V-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
; V: scalar.ph:
;
-; ZVDOT4A8I-LABEL: define i32 @vdota4(
+; ZVDOT4A8I-LABEL: define i32 @vdot4a(
; ZVDOT4A8I-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
; ZVDOT4A8I-NEXT: entry:
; ZVDOT4A8I-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
@@ -76,7 +76,7 @@ define i32 @vdota4(ptr %a, ptr %b) #0 {
; ZVDOT4A8I-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
; ZVDOT4A8I: scalar.ph:
;
-; FIXED-V-LABEL: define i32 @vdota4(
+; FIXED-V-LABEL: define i32 @vdot4a(
; FIXED-V-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
; FIXED-V-NEXT: entry:
; FIXED-V-NEXT: br label [[VECTOR_PH:%.*]]
@@ -112,7 +112,7 @@ define i32 @vdota4(ptr %a, ptr %b) #0 {
; FIXED-V: for.exit:
; FIXED-V-NEXT: ret i32 [[TMP15]]
;
-; FIXED-ZVDOT4A8I-LABEL: define i32 @vdota4(
+; FIXED-ZVDOT4A8I-LABEL: define i32 @vdot4a(
; FIXED-ZVDOT4A8I-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
; FIXED-ZVDOT4A8I-NEXT: entry:
; FIXED-ZVDOT4A8I-NEXT: br label [[VECTOR_PH:%.*]]
@@ -148,7 +148,7 @@ define i32 @vdota4(ptr %a, ptr %b) #0 {
; FIXED-ZVDOT4A8I: for.exit:
; FIXED-ZVDOT4A8I-NEXT: ret i32 [[TMP13]]
;
-; TAILFOLD-LABEL: define i32 @vdota4(
+; TAILFOLD-LABEL: define i32 @vdot4a(
; TAILFOLD-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
; TAILFOLD-NEXT: entry:
; TAILFOLD-NEXT: br label [[VECTOR_PH:%.*]]
@@ -202,8 +202,8 @@ for.exit:
}
-define i32 @vdota4u(ptr %a, ptr %b) #0 {
-; V-LABEL: define i32 @vdota4u(
+define i32 @vdot4au(ptr %a, ptr %b) #0 {
+; V-LABEL: define i32 @vdot4au(
; V-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; V-NEXT: entry:
; V-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
@@ -236,7 +236,7 @@ define i32 @vdota4u(ptr %a, ptr %b) #0 {
; V-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
; V: scalar.ph:
;
-; ZVDOT4A8I-LABEL: define i32 @vdota4u(
+; ZVDOT4A8I-LABEL: define i32 @vdot4au(
; ZVDOT4A8I-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; ZVDOT4A8I-NEXT: entry:
; ZVDOT4A8I-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
@@ -269,7 +269,7 @@ define i32 @vdota4u(ptr %a, ptr %b) #0 {
; ZVDOT4A8I-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
; ZVDOT4A8I: scalar.ph:
;
-; FIXED-V-LABEL: define i32 @vdota4u(
+; FIXED-V-LABEL: define i32 @vdot4au(
; FIXED-V-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; FIXED-V-NEXT: entry:
; FIXED-V-NEXT: br label [[VECTOR_PH:%.*]]
@@ -305,7 +305,7 @@ define i32 @vdota4u(ptr %a, ptr %b) #0 {
; FIXED-V: for.exit:
; FIXED-V-NEXT: ret i32 [[TMP15]]
;
-; FIXED-ZVDOT4A8I-LABEL: define i32 @vdota4u(
+; FIXED-ZVDOT4A8I-LABEL: define i32 @vdot4au(
; FIXED-ZVDOT4A8I-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; FIXED-ZVDOT4A8I-NEXT: entry:
; FIXED-ZVDOT4A8I-NEXT: br label [[VECTOR_PH:%.*]]
@@ -341,7 +341,7 @@ define i32 @vdota4u(ptr %a, ptr %b) #0 {
; FIXED-ZVDOT4A8I: for.exit:
; FIXED-ZVDOT4A8I-NEXT: ret i32 [[TMP13]]
;
-; TAILFOLD-LABEL: define i32 @vdota4u(
+; TAILFOLD-LABEL: define i32 @vdot4au(
; TAILFOLD-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; TAILFOLD-NEXT: entry:
; TAILFOLD-NEXT: br label [[VECTOR_PH:%.*]]
@@ -395,8 +395,8 @@ for.exit:
}
-define i32 @vdota4su(ptr %a, ptr %b) #0 {
-; V-LABEL: define i32 @vdota4su(
+define i32 @vdot4asu(ptr %a, ptr %b) #0 {
+; V-LABEL: define i32 @vdot4asu(
; V-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; V-NEXT: entry:
; V-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
@@ -429,7 +429,7 @@ define i32 @vdota4su(ptr %a, ptr %b) #0 {
; V-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
; V: scalar.ph:
;
-; ZVDOT4A8I-LABEL: define i32 @vdota4su(
+; ZVDOT4A8I-LABEL: define i32 @vdot4asu(
; ZVDOT4A8I-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; ZVDOT4A8I-NEXT: entry:
; ZVDOT4A8I-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
@@ -462,7 +462,7 @@ define i32 @vdota4su(ptr %a, ptr %b) #0 {
; ZVDOT4A8I-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
; ZVDOT4A8I: scalar.ph:
;
-; FIXED-V-LABEL: define i32 @vdota4su(
+; FIXED-V-LABEL: define i32 @vdot4asu(
; FIXED-V-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; FIXED-V-NEXT: entry:
; FIXED-V-NEXT: br label [[VECTOR_PH:%.*]]
@@ -498,7 +498,7 @@ define i32 @vdota4su(ptr %a, ptr %b) #0 {
; FIXED-V: for.exit:
; FIXED-V-NEXT: ret i32 [[TMP15]]
;
-; FIXED-ZVDOT4A8I-LABEL: define i32 @vdota4su(
+; FIXED-ZVDOT4A8I-LABEL: define i32 @vdot4asu(
; FIXED-ZVDOT4A8I-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; FIXED-ZVDOT4A8I-NEXT: entry:
; FIXED-ZVDOT4A8I-NEXT: br label [[VECTOR_PH:%.*]]
@@ -534,7 +534,7 @@ define i32 @vdota4su(ptr %a, ptr %b) #0 {
; FIXED-ZVDOT4A8I: for.exit:
; FIXED-ZVDOT4A8I-NEXT: ret i32 [[TMP13]]
;
-; TAILFOLD-LABEL: define i32 @vdota4su(
+; TAILFOLD-LABEL: define i32 @vdot4asu(
; TAILFOLD-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; TAILFOLD-NEXT: entry:
; TAILFOLD-NEXT: br label [[VECTOR_PH:%.*]]
@@ -587,8 +587,8 @@ for.exit:
ret i32 %add
}
-define i32 @vdota4su2(ptr %a, ptr %b) #0 {
-; V-LABEL: define i32 @vdota4su2(
+define i32 @vdot4asu2(ptr %a, ptr %b) #0 {
+; V-LABEL: define i32 @vdot4asu2(
; V-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; V-NEXT: entry:
; V-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
@@ -621,7 +621,7 @@ define i32 @vdota4su2(ptr %a, ptr %b) #0 {
; V-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
; V: scalar.ph:
;
-; ZVDOT4A8I-LABEL: define i32 @vdota4su2(
+; ZVDOT4A8I-LABEL: define i32 @vdot4asu2(
; ZVDOT4A8I-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; ZVDOT4A8I-NEXT: entry:
; ZVDOT4A8I-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
@@ -654,7 +654,7 @@ define i32 @vdota4su2(ptr %a, ptr %b) #0 {
; ZVDOT4A8I-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
; ZVDOT4A8I: scalar.ph:
;
-; FIXED-V-LABEL: define i32 @vdota4su2(
+; FIXED-V-LABEL: define i32 @vdot4asu2(
; FIXED-V-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; FIXED-V-NEXT: entry:
; FIXED-V-NEXT: br label [[VECTOR_PH:%.*]]
@@ -690,7 +690,7 @@ define i32 @vdota4su2(ptr %a, ptr %b) #0 {
; FIXED-V: for.exit:
; FIXED-V-NEXT: ret i32 [[TMP15]]
;
-; FIXED-ZVDOT4A8I-LABEL: define i32 @vdota4su2(
+; FIXED-ZVDOT4A8I-LABEL: define i32 @vdot4asu2(
; FIXED-ZVDOT4A8I-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; FIXED-ZVDOT4A8I-NEXT: entry:
; FIXED-ZVDOT4A8I-NEXT: br label [[VECTOR_PH:%.*]]
@@ -726,7 +726,7 @@ define i32 @vdota4su2(ptr %a, ptr %b) #0 {
; FIXED-ZVDOT4A8I: for.exit:
; FIXED-ZVDOT4A8I-NEXT: ret i32 [[TMP13]]
;
-; TAILFOLD-LABEL: define i32 @vdota4su2(
+; TAILFOLD-LABEL: define i32 @vdot4asu2(
; TAILFOLD-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; TAILFOLD-NEXT: entry:
; TAILFOLD-NEXT: br label [[VECTOR_PH:%.*]]
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