[llvm] b4f7c93 - [AArch64][Isel] For fixed length vectors use sve for bitreverse when available (#196025)
via llvm-commits
llvm-commits at lists.llvm.org
Mon May 11 19:50:01 PDT 2026
Author: Yashwant Singh
Date: 2026-05-12T08:19:56+05:30
New Revision: b4f7c93e7d1325f1c1f00b47c10d2923e8259369
URL: https://github.com/llvm/llvm-project/commit/b4f7c93e7d1325f1c1f00b47c10d2923e8259369
DIFF: https://github.com/llvm/llvm-project/commit/b4f7c93e7d1325f1c1f00b47c10d2923e8259369.diff
LOG: [AArch64][Isel] For fixed length vectors use sve for bitreverse when available (#196025)
Lowering bitreverse via the SVE path seems to be giving significant
performance improvements for fixed width vectors
Speedups after the patch
uint8x8_t 1.01x
uint16x4_t 2.02x
uint32x2_t 2.01x
uint64x1_t 2.02x
uint8x16_t 1.00x
uint16x8_t 2.03x
uint32x4_t 2.03x
uint64x2_t 2.02x
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/bitreverse.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 8608bfe0a8205..d8ba83dd1d584 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1932,6 +1932,10 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::MULHU, VT, Custom);
}
+ for (auto VT : {MVT::v4i16, MVT::v8i16, MVT::v2i32, MVT::v4i32, MVT::v1i64,
+ MVT::v2i64})
+ setOperationAction(ISD::BITREVERSE, VT, Custom);
+
// NEON doesn't support 64-bit vector integer muls, but SVE does.
setOperationAction(ISD::MUL, MVT::v1i64, Custom);
setOperationAction(ISD::MUL, MVT::v2i64, Custom);
@@ -1970,7 +1974,6 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FP_ROUND, VT, Custom);
// These operations are not supported on NEON but SVE can do them.
- setOperationAction(ISD::BITREVERSE, MVT::v1i64, Custom);
setOperationAction(ISD::CTLZ, MVT::v1i64, Custom);
setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
@@ -1988,9 +1991,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::VECREDUCE_UMIN, MVT::v2i64, Custom);
// Int operations with no NEON support.
- for (auto VT : {MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16,
- MVT::v2i32, MVT::v4i32, MVT::v2i64}) {
- setOperationAction(ISD::BITREVERSE, VT, Custom);
+ for (auto VT : {MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16, MVT::v2i32,
+ MVT::v4i32, MVT::v2i64}) {
setOperationAction(ISD::CTTZ, VT, Custom);
setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
@@ -11825,9 +11827,7 @@ SDValue AArch64TargetLowering::LowerBitreverse(SDValue Op,
SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
- if (VT.isScalableVector() ||
- useSVEForFixedLengthVectorVT(
- VT, /*OverrideNEON=*/Subtarget->useSVEForFixedLengthVectors()))
+ if (Subtarget->isSVEorStreamingSVEAvailable())
return LowerToPredicatedOp(Op, DAG, AArch64ISD::BITREVERSE_MERGE_PASSTHRU);
SDLoc DL(Op);
diff --git a/llvm/test/CodeGen/AArch64/bitreverse.ll b/llvm/test/CodeGen/AArch64/bitreverse.ll
index 61f67328be38e..d3ea6916f0832 100644
--- a/llvm/test/CodeGen/AArch64/bitreverse.ll
+++ b/llvm/test/CodeGen/AArch64/bitreverse.ll
@@ -1,5 +1,6 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s --check-prefixes=CHECK,SDAG
+; RUN: llc -mtriple=aarch64 -mattr=+sve %s -o - | FileCheck %s --check-prefixes=CHECK,SVE
; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=1 %s -o - | FileCheck %s --check-prefixes=CHECK,GISEL
; These tests just check that the plumbing is in place for @llvm.bitreverse.
@@ -14,6 +15,14 @@ define <2 x i16> @f(<2 x i16> %a) {
; SDAG-NEXT: ushr v0.2s, v0.2s, #16
; SDAG-NEXT: ret
;
+; SVE-LABEL: f:
+; SVE: // %bb.0:
+; SVE-NEXT: ptrue p0.s, vl2
+; SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT: rbit z0.s, p0/m, z0.s
+; SVE-NEXT: ushr v0.2s, v0.2s, #16
+; SVE-NEXT: ret
+;
; GISEL-LABEL: f:
; GISEL: // %bb.0:
; GISEL-NEXT: uzp1 v0.4h, v0.4h, v0.4h
@@ -152,6 +161,14 @@ define <4 x i8> @g_vec_4x8(<4 x i8> %a) {
; SDAG-NEXT: ushr v0.4h, v0.4h, #8
; SDAG-NEXT: ret
;
+; SVE-LABEL: g_vec_4x8:
+; SVE: // %bb.0:
+; SVE-NEXT: ptrue p0.h, vl4
+; SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT: rbit z0.h, p0/m, z0.h
+; SVE-NEXT: ushr v0.4h, v0.4h, #8
+; SVE-NEXT: ret
+;
; GISEL-LABEL: g_vec_4x8:
; GISEL: // %bb.0:
; GISEL-NEXT: uzp1 v0.8b, v0.8b, v0.8b
@@ -176,11 +193,25 @@ define <9 x i8> @g_vec_9x8(<9 x i8> %a) {
declare <4 x i16> @llvm.bitreverse.v4i16(<4 x i16>) readnone
define <4 x i16> @g_vec_4x16(<4 x i16> %a) {
-; CHECK-LABEL: g_vec_4x16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: rev16 v0.8b, v0.8b
-; CHECK-NEXT: rbit v0.8b, v0.8b
-; CHECK-NEXT: ret
+; SDAG-LABEL: g_vec_4x16:
+; SDAG: // %bb.0:
+; SDAG-NEXT: rev16 v0.8b, v0.8b
+; SDAG-NEXT: rbit v0.8b, v0.8b
+; SDAG-NEXT: ret
+;
+; SVE-LABEL: g_vec_4x16:
+; SVE: // %bb.0:
+; SVE-NEXT: ptrue p0.h, vl4
+; SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT: rbit z0.h, p0/m, z0.h
+; SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT: ret
+;
+; GISEL-LABEL: g_vec_4x16:
+; GISEL: // %bb.0:
+; GISEL-NEXT: rev16 v0.8b, v0.8b
+; GISEL-NEXT: rbit v0.8b, v0.8b
+; GISEL-NEXT: ret
%b = call <4 x i16> @llvm.bitreverse.v4i16(<4 x i16> %a)
ret <4 x i16> %b
}
@@ -188,11 +219,25 @@ define <4 x i16> @g_vec_4x16(<4 x i16> %a) {
declare <8 x i16> @llvm.bitreverse.v8i16(<8 x i16>) readnone
define <8 x i16> @g_vec_8x16(<8 x i16> %a) {
-; CHECK-LABEL: g_vec_8x16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: rev16 v0.16b, v0.16b
-; CHECK-NEXT: rbit v0.16b, v0.16b
-; CHECK-NEXT: ret
+; SDAG-LABEL: g_vec_8x16:
+; SDAG: // %bb.0:
+; SDAG-NEXT: rev16 v0.16b, v0.16b
+; SDAG-NEXT: rbit v0.16b, v0.16b
+; SDAG-NEXT: ret
+;
+; SVE-LABEL: g_vec_8x16:
+; SVE: // %bb.0:
+; SVE-NEXT: ptrue p0.h, vl8
+; SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; SVE-NEXT: rbit z0.h, p0/m, z0.h
+; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
+; SVE-NEXT: ret
+;
+; GISEL-LABEL: g_vec_8x16:
+; GISEL: // %bb.0:
+; GISEL-NEXT: rev16 v0.16b, v0.16b
+; GISEL-NEXT: rbit v0.16b, v0.16b
+; GISEL-NEXT: ret
%b = call <8 x i16> @llvm.bitreverse.v8i16(<8 x i16> %a)
ret <8 x i16> %b
}
@@ -200,13 +245,32 @@ define <8 x i16> @g_vec_8x16(<8 x i16> %a) {
declare <16 x i16> @llvm.bitreverse.v16i16(<16 x i16>) readnone
define <16 x i16> @g_vec_16x16(<16 x i16> %a) {
-; CHECK-LABEL: g_vec_16x16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: rev16 v0.16b, v0.16b
-; CHECK-NEXT: rev16 v1.16b, v1.16b
-; CHECK-NEXT: rbit v0.16b, v0.16b
-; CHECK-NEXT: rbit v1.16b, v1.16b
-; CHECK-NEXT: ret
+; SDAG-LABEL: g_vec_16x16:
+; SDAG: // %bb.0:
+; SDAG-NEXT: rev16 v0.16b, v0.16b
+; SDAG-NEXT: rev16 v1.16b, v1.16b
+; SDAG-NEXT: rbit v0.16b, v0.16b
+; SDAG-NEXT: rbit v1.16b, v1.16b
+; SDAG-NEXT: ret
+;
+; SVE-LABEL: g_vec_16x16:
+; SVE: // %bb.0:
+; SVE-NEXT: ptrue p0.h, vl8
+; SVE-NEXT: // kill: def $q1 killed $q1 def $z1
+; SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; SVE-NEXT: rbit z0.h, p0/m, z0.h
+; SVE-NEXT: rbit z1.h, p0/m, z1.h
+; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
+; SVE-NEXT: // kill: def $q1 killed $q1 killed $z1
+; SVE-NEXT: ret
+;
+; GISEL-LABEL: g_vec_16x16:
+; GISEL: // %bb.0:
+; GISEL-NEXT: rev16 v0.16b, v0.16b
+; GISEL-NEXT: rev16 v1.16b, v1.16b
+; GISEL-NEXT: rbit v0.16b, v0.16b
+; GISEL-NEXT: rbit v1.16b, v1.16b
+; GISEL-NEXT: ret
%b = call <16 x i16> @llvm.bitreverse.v16i16(<16 x i16> %a)
ret <16 x i16> %b
}
@@ -214,11 +278,25 @@ define <16 x i16> @g_vec_16x16(<16 x i16> %a) {
declare <2 x i32> @llvm.bitreverse.v2i32(<2 x i32>) readnone
define <2 x i32> @g_vec_2x32(<2 x i32> %a) {
-; CHECK-LABEL: g_vec_2x32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: rev32 v0.8b, v0.8b
-; CHECK-NEXT: rbit v0.8b, v0.8b
-; CHECK-NEXT: ret
+; SDAG-LABEL: g_vec_2x32:
+; SDAG: // %bb.0:
+; SDAG-NEXT: rev32 v0.8b, v0.8b
+; SDAG-NEXT: rbit v0.8b, v0.8b
+; SDAG-NEXT: ret
+;
+; SVE-LABEL: g_vec_2x32:
+; SVE: // %bb.0:
+; SVE-NEXT: ptrue p0.s, vl2
+; SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT: rbit z0.s, p0/m, z0.s
+; SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT: ret
+;
+; GISEL-LABEL: g_vec_2x32:
+; GISEL: // %bb.0:
+; GISEL-NEXT: rev32 v0.8b, v0.8b
+; GISEL-NEXT: rbit v0.8b, v0.8b
+; GISEL-NEXT: ret
%b = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %a)
ret <2 x i32> %b
}
@@ -226,11 +304,25 @@ define <2 x i32> @g_vec_2x32(<2 x i32> %a) {
declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>) readnone
define <4 x i32> @g_vec_4x32(<4 x i32> %a) {
-; CHECK-LABEL: g_vec_4x32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: rev32 v0.16b, v0.16b
-; CHECK-NEXT: rbit v0.16b, v0.16b
-; CHECK-NEXT: ret
+; SDAG-LABEL: g_vec_4x32:
+; SDAG: // %bb.0:
+; SDAG-NEXT: rev32 v0.16b, v0.16b
+; SDAG-NEXT: rbit v0.16b, v0.16b
+; SDAG-NEXT: ret
+;
+; SVE-LABEL: g_vec_4x32:
+; SVE: // %bb.0:
+; SVE-NEXT: ptrue p0.s, vl4
+; SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; SVE-NEXT: rbit z0.s, p0/m, z0.s
+; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
+; SVE-NEXT: ret
+;
+; GISEL-LABEL: g_vec_4x32:
+; GISEL: // %bb.0:
+; GISEL-NEXT: rev32 v0.16b, v0.16b
+; GISEL-NEXT: rbit v0.16b, v0.16b
+; GISEL-NEXT: ret
%b = call <4 x i32> @llvm.bitreverse.v4i32(<4 x i32> %a)
ret <4 x i32> %b
}
@@ -238,13 +330,32 @@ define <4 x i32> @g_vec_4x32(<4 x i32> %a) {
declare <8 x i32> @llvm.bitreverse.v8i32(<8 x i32>) readnone
define <8 x i32> @g_vec_8x32(<8 x i32> %a) {
-; CHECK-LABEL: g_vec_8x32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: rev32 v0.16b, v0.16b
-; CHECK-NEXT: rev32 v1.16b, v1.16b
-; CHECK-NEXT: rbit v0.16b, v0.16b
-; CHECK-NEXT: rbit v1.16b, v1.16b
-; CHECK-NEXT: ret
+; SDAG-LABEL: g_vec_8x32:
+; SDAG: // %bb.0:
+; SDAG-NEXT: rev32 v0.16b, v0.16b
+; SDAG-NEXT: rev32 v1.16b, v1.16b
+; SDAG-NEXT: rbit v0.16b, v0.16b
+; SDAG-NEXT: rbit v1.16b, v1.16b
+; SDAG-NEXT: ret
+;
+; SVE-LABEL: g_vec_8x32:
+; SVE: // %bb.0:
+; SVE-NEXT: ptrue p0.s, vl4
+; SVE-NEXT: // kill: def $q1 killed $q1 def $z1
+; SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; SVE-NEXT: rbit z0.s, p0/m, z0.s
+; SVE-NEXT: rbit z1.s, p0/m, z1.s
+; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
+; SVE-NEXT: // kill: def $q1 killed $q1 killed $z1
+; SVE-NEXT: ret
+;
+; GISEL-LABEL: g_vec_8x32:
+; GISEL: // %bb.0:
+; GISEL-NEXT: rev32 v0.16b, v0.16b
+; GISEL-NEXT: rev32 v1.16b, v1.16b
+; GISEL-NEXT: rbit v0.16b, v0.16b
+; GISEL-NEXT: rbit v1.16b, v1.16b
+; GISEL-NEXT: ret
%b = call <8 x i32> @llvm.bitreverse.v8i32(<8 x i32> %a)
ret <8 x i32> %b
}
@@ -258,6 +369,14 @@ define <1 x i64> @g_vec_1x64(<1 x i64> %a) {
; SDAG-NEXT: rbit v0.8b, v0.8b
; SDAG-NEXT: ret
;
+; SVE-LABEL: g_vec_1x64:
+; SVE: // %bb.0:
+; SVE-NEXT: ptrue p0.d, vl1
+; SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT: rbit z0.d, p0/m, z0.d
+; SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT: ret
+;
; GISEL-LABEL: g_vec_1x64:
; GISEL: // %bb.0:
; GISEL-NEXT: fmov x8, d0
@@ -271,11 +390,25 @@ define <1 x i64> @g_vec_1x64(<1 x i64> %a) {
declare <2 x i64> @llvm.bitreverse.v2i64(<2 x i64>) readnone
define <2 x i64> @g_vec_2x64(<2 x i64> %a) {
-; CHECK-LABEL: g_vec_2x64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: rev64 v0.16b, v0.16b
-; CHECK-NEXT: rbit v0.16b, v0.16b
-; CHECK-NEXT: ret
+; SDAG-LABEL: g_vec_2x64:
+; SDAG: // %bb.0:
+; SDAG-NEXT: rev64 v0.16b, v0.16b
+; SDAG-NEXT: rbit v0.16b, v0.16b
+; SDAG-NEXT: ret
+;
+; SVE-LABEL: g_vec_2x64:
+; SVE: // %bb.0:
+; SVE-NEXT: ptrue p0.d, vl2
+; SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; SVE-NEXT: rbit z0.d, p0/m, z0.d
+; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
+; SVE-NEXT: ret
+;
+; GISEL-LABEL: g_vec_2x64:
+; GISEL: // %bb.0:
+; GISEL-NEXT: rev64 v0.16b, v0.16b
+; GISEL-NEXT: rbit v0.16b, v0.16b
+; GISEL-NEXT: ret
%b = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %a)
ret <2 x i64> %b
}
@@ -283,13 +416,32 @@ define <2 x i64> @g_vec_2x64(<2 x i64> %a) {
declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>) readnone
define <4 x i64> @g_vec_4x64(<4 x i64> %a) {
-; CHECK-LABEL: g_vec_4x64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: rev64 v0.16b, v0.16b
-; CHECK-NEXT: rev64 v1.16b, v1.16b
-; CHECK-NEXT: rbit v0.16b, v0.16b
-; CHECK-NEXT: rbit v1.16b, v1.16b
-; CHECK-NEXT: ret
+; SDAG-LABEL: g_vec_4x64:
+; SDAG: // %bb.0:
+; SDAG-NEXT: rev64 v0.16b, v0.16b
+; SDAG-NEXT: rev64 v1.16b, v1.16b
+; SDAG-NEXT: rbit v0.16b, v0.16b
+; SDAG-NEXT: rbit v1.16b, v1.16b
+; SDAG-NEXT: ret
+;
+; SVE-LABEL: g_vec_4x64:
+; SVE: // %bb.0:
+; SVE-NEXT: ptrue p0.d, vl2
+; SVE-NEXT: // kill: def $q1 killed $q1 def $z1
+; SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; SVE-NEXT: rbit z0.d, p0/m, z0.d
+; SVE-NEXT: rbit z1.d, p0/m, z1.d
+; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
+; SVE-NEXT: // kill: def $q1 killed $q1 killed $z1
+; SVE-NEXT: ret
+;
+; GISEL-LABEL: g_vec_4x64:
+; GISEL: // %bb.0:
+; GISEL-NEXT: rev64 v0.16b, v0.16b
+; GISEL-NEXT: rev64 v1.16b, v1.16b
+; GISEL-NEXT: rbit v0.16b, v0.16b
+; GISEL-NEXT: rbit v1.16b, v1.16b
+; GISEL-NEXT: ret
%b = call <4 x i64> @llvm.bitreverse.v4i64(<4 x i64> %a)
ret <4 x i64> %b
}
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll
index b62b850434469..2de1976322db0 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll
@@ -740,9 +740,7 @@ define void @ctpop_v32i64(ptr %a) vscale_range(16,0) #0 {
define <8 x i8> @cttz_v8i8(<8 x i8> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: cttz_v8i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.b, vl8
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT: rbit z0.b, p0/m, z0.b
+; CHECK-NEXT: rbit v0.8b, v0.8b
; CHECK-NEXT: clz v0.8b, v0.8b
; CHECK-NEXT: ret
%res = call <8 x i8> @llvm.cttz.v8i8(<8 x i8> %op)
@@ -752,9 +750,7 @@ define <8 x i8> @cttz_v8i8(<8 x i8> %op) vscale_range(2,0) #0 {
define <16 x i8> @cttz_v16i8(<16 x i8> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: cttz_v16i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.b, vl16
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT: rbit z0.b, p0/m, z0.b
+; CHECK-NEXT: rbit v0.16b, v0.16b
; CHECK-NEXT: clz v0.16b, v0.16b
; CHECK-NEXT: ret
%res = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %op)
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll
index 82d350f6e28f8..7cf981d63f674 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll
@@ -12,10 +12,7 @@ target triple = "aarch64-unknown-linux-gnu"
define <8 x i8> @bitreverse_v8i8(<8 x i8> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: bitreverse_v8i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.b, vl8
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT: rbit z0.b, p0/m, z0.b
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT: rbit v0.8b, v0.8b
; CHECK-NEXT: ret
%res = call <8 x i8> @llvm.bitreverse.v8i8(<8 x i8> %op)
ret <8 x i8> %res
@@ -24,10 +21,7 @@ define <8 x i8> @bitreverse_v8i8(<8 x i8> %op) vscale_range(2,0) #0 {
define <16 x i8> @bitreverse_v16i8(<16 x i8> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: bitreverse_v16i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.b, vl16
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT: rbit z0.b, p0/m, z0.b
-; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: rbit v0.16b, v0.16b
; CHECK-NEXT: ret
%res = call <16 x i8> @llvm.bitreverse.v16i8(<16 x i8> %op)
ret <16 x i8> %res
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