[llvm] [AArch64] Add a regression test for Apple tuning features (PR #196792)

[Tomer Shafir via llvm-commits]

https://github.com/tomershafir updated https://github.com/llvm/llvm-project/pull/196792

>From 44dcb7cf59aca1d31047f79642b90c350cf90bd2 Mon Sep 17 00:00:00 2001
From: tomershafir <tomer.shafir8 at gmail.com>
Date: Mon, 11 May 2026 15:25:15 +0300
Subject: [PATCH] [AArch64] Add a regression test for Apple tuning features

This patch adds a TableGen regression test that directly checks complete featrure lists per generation for Apple CPUs, to guard against changes that can break the <CPU,features> association if we lack indirect coverage.

A followup patch should introduce generational delta encoding for Apple tuning features that this test should help verify.
---
 .../TableGen/aarch64-apple-tuning-features.td | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 llvm/test/TableGen/aarch64-apple-tuning-features.td

diff --git a/llvm/test/TableGen/aarch64-apple-tuning-features.td b/llvm/test/TableGen/aarch64-apple-tuning-features.td
new file mode 100644
index 0000000000000..d0f3142dbe863
--- /dev/null
+++ b/llvm/test/TableGen/aarch64-apple-tuning-features.td
@@ -0,0 +1,28 @@
+// RUN: llvm-tblgen -print-records %p/../../lib/Target/AArch64/AArch64.td -I %p/../../lib/Target/AArch64 -I %p/../../include | FileCheck %s
+
+// Verify the resolved tuning feature lists for Apple CPUs.
+// Each generation inherits from the previous and applies add/remove deltas.
+// When adding a tuning feature to an Apple core, update the expected list below.
+
+// CHECK-LABEL: def TuneAppleA10 {
+// CHECK: list<SubtargetFeature> Implies = [FeatureAlternateSExtLoadCVTF32Pattern, FeatureArithmeticBccFusion, FeatureArithmeticCbzFusion, FeatureDisableLatencySchedHeuristic, FeatureFuseAES, FeatureFuseCryptoEOR, FeatureStorePairSuppress, FeatureZCRegMoveGPR64, FeatureZCRegMoveFPR128, FeatureZCZeroingGPR32, FeatureZCZeroingGPR64, FeatureNoZCZeroingFPR64, FeatureZCZeroingFPR128];
+// CHECK-LABEL: def TuneAppleA11 {
+// CHECK: list<SubtargetFeature> Implies = [FeatureAlternateSExtLoadCVTF32Pattern, FeatureArithmeticBccFusion, FeatureArithmeticCbzFusion, FeatureDisableLatencySchedHeuristic, FeatureFuseAES, FeatureFuseCryptoEOR, FeatureStorePairSuppress, FeatureZCRegMoveGPR64, FeatureZCRegMoveFPR128, FeatureZCZeroingGPR32, FeatureZCZeroingGPR64, FeatureNoZCZeroingFPR64, FeatureZCZeroingFPR128];
+// CHECK-LABEL: def TuneAppleA12 {
+// CHECK: list<SubtargetFeature> Implies = [FeatureAlternateSExtLoadCVTF32Pattern, FeatureArithmeticBccFusion, FeatureArithmeticCbzFusion, FeatureDisableLatencySchedHeuristic, FeatureFuseAES, FeatureFuseCryptoEOR, FeatureStorePairSuppress, FeatureZCRegMoveGPR64, FeatureZCRegMoveFPR128, FeatureZCZeroingGPR32, FeatureZCZeroingGPR64, FeatureNoZCZeroingFPR64, FeatureZCZeroingFPR128];
+// CHECK-LABEL: def TuneAppleA13 {
+// CHECK: list<SubtargetFeature> Implies = [FeatureAlternateSExtLoadCVTF32Pattern, FeatureArithmeticBccFusion, FeatureArithmeticCbzFusion, FeatureDisableLatencySchedHeuristic, FeatureFuseAES, FeatureFuseCryptoEOR, FeatureStorePairSuppress, FeatureZCRegMoveGPR64, FeatureZCRegMoveFPR128, FeatureZCZeroingGPR32, FeatureZCZeroingGPR64, FeatureNoZCZeroingFPR64, FeatureZCZeroingFPR128];
+// CHECK-LABEL: def TuneAppleA14 {
+// CHECK: list<SubtargetFeature> Implies = [FeatureAggressiveFMA, FeatureAlignCmpCSelPairs, FeatureAlternateSExtLoadCVTF32Pattern, FeatureArithmeticBccFusion, FeatureArithmeticCbzFusion, FeatureDisableLatencySchedHeuristic, FeatureFastLD1Single, FeatureFuseAddress, FeatureFuseAES, FeatureFuseArithmeticLogic, FeatureFuseCmpCSel, FeatureFuseCryptoEOR, FeatureFuseLiterals, FeatureStorePairSuppress, FeatureZCRegMoveGPR64, FeatureZCRegMoveFPR128, FeatureZCZeroingGPR32, FeatureZCZeroingGPR64, FeatureNoZCZeroingFPR64, FeatureZCZeroingFPR128, FeatureMaxInterleaveFactor4];
+// CHECK-LABEL: def TuneAppleA15 {
+// CHECK: list<SubtargetFeature> Implies = [FeatureAlternateSExtLoadCVTF32Pattern, FeatureAlignCmpCSelPairs, FeatureArithmeticBccFusion, FeatureArithmeticCbzFusion, FeatureDisableLatencySchedHeuristic, FeatureFastLD1Single, FeatureFuseAddress, FeatureFuseAdrpAdd, FeatureFuseAES, FeatureFuseArithmeticLogic, FeatureFuseCmpCSel, FeatureFuseCryptoEOR, FeatureFuseLiterals, FeatureStorePairSuppress, FeatureZCRegMoveGPR64, FeatureZCRegMoveFPR128, FeatureZCZeroingGPR32, FeatureZCZeroingGPR64, FeatureNoZCZeroingFPR64, FeatureZCZeroingFPR128, FeatureMaxInterleaveFactor4];
+// CHECK-LABEL: def TuneAppleA16 {
+// CHECK: list<SubtargetFeature> Implies = [FeatureAlternateSExtLoadCVTF32Pattern, FeatureAlignCmpCSelPairs, FeatureArithmeticBccFusion, FeatureArithmeticCbzFusion, FeatureDisableLatencySchedHeuristic, FeatureFastLD1Single, FeatureFuseAddress, FeatureFuseAdrpAdd, FeatureFuseAES, FeatureFuseArithmeticLogic, FeatureFuseCmpCSel, FeatureFuseFCmpFCSel, FeatureFuseCryptoEOR, FeatureFuseLiterals, FeatureStorePairSuppress, FeatureZCRegMoveGPR64, FeatureZCRegMoveFPR128, FeatureZCZeroingGPR32, FeatureZCZeroingGPR64, FeatureNoZCZeroingFPR64, FeatureZCZeroingFPR128, FeatureMaxInterleaveFactor4];
+// CHECK-LABEL: def TuneAppleA17 {
+// CHECK: list<SubtargetFeature> Implies = [FeatureAlternateSExtLoadCVTF32Pattern, FeatureAlignCmpCSelPairs, FeatureArithmeticBccFusion, FeatureArithmeticCbzFusion, FeatureDisableLatencySchedHeuristic, FeatureFastLD1Single, FeatureFuseAddress, FeatureFuseAdrpAdd, FeatureFuseAES, FeatureFuseArithmeticLogic, FeatureFuseCmpCSel, FeatureFuseFCmpFCSel, FeatureFuseCryptoEOR, FeatureFuseLiterals, FeatureStorePairSuppress, FeatureZCRegMoveGPR64, FeatureZCRegMoveFPR128, FeatureZCZeroingGPR32, FeatureZCZeroingGPR64, FeatureNoZCZeroingFPR64, FeatureZCZeroingFPR128, FeatureMaxInterleaveFactor4];
+// CHECK-LABEL: def TuneAppleA7 {
+// CHECK: list<SubtargetFeature> Implies = [FeatureAlternateSExtLoadCVTF32Pattern, FeatureArithmeticBccFusion, FeatureArithmeticCbzFusion, FeatureDisableLatencySchedHeuristic, FeatureFuseAES, FeatureFuseCryptoEOR, FeatureStorePairSuppress, FeatureZCRegMoveGPR64, FeatureZCRegMoveFPR128, FeatureZCZeroingGPR32, FeatureZCZeroingGPR64, FeatureNoZCZeroingFPR64, FeatureZCZeroingFPR128, FeatureZCZeroingFPWorkaround];
+// CHECK-LABEL: def TuneAppleM4 {
+// CHECK: list<SubtargetFeature> Implies = [FeatureAlternateSExtLoadCVTF32Pattern, FeatureAlignCmpCSelPairs, FeatureArithmeticBccFusion, FeatureArithmeticCbzFusion, FeatureDisableLatencySchedHeuristic, FeatureFastLD1Single, FeatureFuseAddress, FeatureFuseAdrpAdd, FeatureFuseAES, FeatureFuseArithmeticLogic, FeatureFuseCmpCSel, FeatureFuseFCmpFCSel, FeatureFuseCryptoEOR, FeatureFuseLiterals, FeatureZCRegMoveGPR64, FeatureZCRegMoveFPR128, FeatureZCZeroingGPR32, FeatureZCZeroingGPR64, FeatureNoZCZeroingFPR64, FeatureZCZeroingFPR128, FeatureMaxInterleaveFactor4];
+// CHECK-LABEL: def TuneAppleM5 {
+// CHECK: list<SubtargetFeature> Implies = [FeatureAlternateSExtLoadCVTF32Pattern, FeatureAlignCmpCSelPairs, FeatureArithmeticBccFusion, FeatureArithmeticCbzFusion, FeatureDisableLatencySchedHeuristic, FeatureFastLD1Single, FeatureFuseAddress, FeatureFuseAdrpAdd, FeatureFuseAES, FeatureFuseArithmeticLogic, FeatureFuseCmpCSel, FeatureFuseFCmpFCSel, FeatureFuseCryptoEOR, FeatureFuseLiterals, FeatureZCRegMoveGPR64, FeatureZCRegMoveFPR128, FeatureZCZeroingGPR32, FeatureZCZeroingGPR64, FeatureNoZCZeroingFPR64, FeatureZCZeroingFPR128, FeatureMaxInterleaveFactor4];