[llvm] [ARM] Have the subtraction of a large number be turned into the addition of its negative in TableGen (PR #196866)
via llvm-commits
llvm-commits at lists.llvm.org
Sun May 10 19:44:21 PDT 2026
https://github.com/LumioseSil created https://github.com/llvm/llvm-project/pull/196866
They were only modified at the asm printing level, but actually changing the representation in isel is important.
>From d6f6f76e8624c5929f655b7c0a64aa40b5dcf471 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sun, 10 May 2026 22:43:25 -0400
Subject: [PATCH] [ARM] Have the subtraction of a large number be turned into
the addition of its negative in TableGen
They were only modified at the asm printing level, but actually changing the representation in isel is important.
---
llvm/lib/Target/ARM/ARMInstrInfo.td | 7 +
llvm/lib/Target/ARM/ARMInstrThumb.td | 19 +
llvm/lib/Target/ARM/ARMInstrThumb2.td | 6 +
llvm/test/CodeGen/ARM/fpclamptosat_vec.ll | 903 +++++++++++-----------
4 files changed, 479 insertions(+), 456 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index c74c84a2602b1..1f3d56bf99f4e 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -4034,6 +4034,10 @@ def : ARMPat<(add GPR:$src, mod_imm_neg:$imm),
(SUBri GPR:$src, mod_imm_neg:$imm)>;
def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm),
(SUBSri GPR:$src, mod_imm_neg:$imm)>;
+def : ARMPat<(sub GPR:$src, mod_imm_neg:$imm),
+ (ADDri GPR:$src, mod_imm_neg:$imm)>;
+def : ARMPat<(ARMsubc GPR:$src, mod_imm_neg:$imm),
+ (ADDSri GPR:$src, mod_imm_neg:$imm)>;
def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
(SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
@@ -4041,6 +4045,9 @@ def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
(SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
Requires<[IsARM, HasV6T2]>;
+def : ARMPat<(ARMsubc GPR:$src, imm0_65535_neg:$imm),
+ (ADDSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
+ Requires<[IsARM, HasV6T2]>;
// The with-carry-in form matches bitwise not instead of the negation.
// Effectively, the inverse interpretation of the carry flag already accounts
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index 1e2e3c30a78f7..72a5de3442b7e 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -1068,6 +1068,14 @@ def : T1Pat<(or AddLikeOrOp:$Rn, imm8_255:$imm), (tADDi8 $Rn, imm8_255:$imm)>;
def : T1Pat<(or AddLikeOrOp:$Rn, tGPR:$Rm), (tADDrr $Rn, $Rm)>;
+// Match (sub r, -k) at isel as tADD* (Thumb2 does the same with T2Pat). tSUBi3/i8
+// already match (add r, -k); these patterns cover the inverse DAG shape.
+let AddedComplexity = 1 in {
+def : T1Pat<(sub tGPR:$src, mod_imm1_7_neg:$imm),
+ (tADDi3 tGPR:$src, mod_imm1_7_neg:$imm)>;
+def : T1Pat<(sub tGPR:$src, mod_imm8_255_neg:$imm),
+ (tADDi8 tGPR:$src, mod_imm8_255_neg:$imm)>;
+}
def : tInstAlias <"add${s}${p} $Rdn, $Rm",
(tADDrr tGPR:$Rdn,s_cc_out:$s, tGPR:$Rdn, tGPR:$Rm, pred:$p)>;
@@ -1406,6 +1414,17 @@ let hasPostISelHook = 1, Defs = [CPSR] in {
Sched<[WriteALU]>;
}
+let AddedComplexity = 1 in {
+def : T1Pat<(ARMaddc tGPR:$src, mod_imm1_7_neg:$imm),
+ (tSUBSi3 tGPR:$src, mod_imm1_7_neg:$imm)>;
+def : T1Pat<(ARMaddc tGPR:$src, mod_imm8_255_neg:$imm),
+ (tSUBSi8 tGPR:$src, mod_imm8_255_neg:$imm)>;
+def : T1Pat<(ARMsubc tGPR:$src, mod_imm1_7_neg:$imm),
+ (tADDSi3 tGPR:$src, mod_imm1_7_neg:$imm)>;
+def : T1Pat<(ARMsubc tGPR:$src, mod_imm8_255_neg:$imm),
+ (tADDSi8 tGPR:$src, mod_imm8_255_neg:$imm)>;
+}
+
// Sign-extend byte
def tSXTB : // A8.6.222
T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index e79adb370798e..9886e1c7639dc 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -2528,6 +2528,12 @@ def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
(t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
def : T2Pat<(ARMaddc rGPR:$src, imm0_65535_neg:$imm),
(t2SUBSrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
+def : T2Pat<(ARMsubc rGPR:$src, imm1_255_neg:$imm),
+ (t2ADDSri rGPR:$src, imm1_255_neg:$imm)>;
+def : T2Pat<(ARMsubc rGPR:$src, t2_so_imm_neg:$imm),
+ (t2ADDSri rGPR:$src, t2_so_imm_neg:$imm)>;
+def : T2Pat<(ARMsubc rGPR:$src, imm0_65535_neg:$imm),
+ (t2ADDSrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
// The with-carry-in form matches bitwise not instead of the negation.
// Effectively, the inverse interpretation of the carry flag already accounts
// for part of the negation.
diff --git a/llvm/test/CodeGen/ARM/fpclamptosat_vec.ll b/llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
index 40b360e9158ff..764ac9e6909f8 100644
--- a/llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
+++ b/llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
@@ -19,28 +19,27 @@ define <2 x i32> @stest_f64i32(<2 x double> %x) {
; CHECK-NEXT: vmov r0, r1, d8
; CHECK-NEXT: vmov.32 d9[0], r4
; CHECK-NEXT: bl __aeabi_d2lz
+; CHECK-NEXT: adds r3, r4, #-2147483647
; CHECK-NEXT: vmov.32 d8[0], r0
-; CHECK-NEXT: mvn r3, #-2147483648
-; CHECK-NEXT: subs r4, r4, r3
+; CHECK-NEXT: sbcs r3, r5, #0
; CHECK-NEXT: adr r2, .LCPI0_0
+; CHECK-NEXT: mov r3, #0
; CHECK-NEXT: vmov.32 d9[1], r5
-; CHECK-NEXT: sbcs r5, r5, #0
-; CHECK-NEXT: mov r5, #0
-; CHECK-NEXT: mvn r12, #0
-; CHECK-NEXT: movwlt r5, #1
-; CHECK-NEXT: cmp r5, #0
-; CHECK-NEXT: mvnne r5, #0
-; CHECK-NEXT: subs r0, r0, r3
+; CHECK-NEXT: movwlt r3, #1
+; CHECK-NEXT: cmp r3, #0
+; CHECK-NEXT: mvnne r3, #0
+; CHECK-NEXT: adds r0, r0, #-2147483647
; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: vmov.32 d8[1], r1
; CHECK-NEXT: mov r0, #0
-; CHECK-NEXT: adr r4, .LCPI0_1
+; CHECK-NEXT: mvn r12, #0
; CHECK-NEXT: movwlt r0, #1
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: vdup.32 d19, r5
+; CHECK-NEXT: vdup.32 d19, r3
; CHECK-NEXT: mvnne r0, #0
; CHECK-NEXT: vld1.64 {d16, d17}, [r2:128]
; CHECK-NEXT: mov r2, #0
+; CHECK-NEXT: adr r4, .LCPI0_1
; CHECK-NEXT: vdup.32 d18, r0
; CHECK-NEXT: vbit q8, q4, q9
; CHECK-NEXT: vld1.64 {d18, d19}, [r4:128]
@@ -100,22 +99,21 @@ define <2 x i32> @utest_f64i32(<2 x double> %x) {
; CHECK-NEXT: vmov r0, r1, d8
; CHECK-NEXT: vmov.32 d9[0], r4
; CHECK-NEXT: bl __aeabi_d2ulz
+; CHECK-NEXT: adds r3, r4, #1
; CHECK-NEXT: vmov.32 d8[0], r0
-; CHECK-NEXT: mvn r3, #0
-; CHECK-NEXT: subs r4, r4, r3
+; CHECK-NEXT: sbcs r3, r5, #0
; CHECK-NEXT: mov r2, #0
+; CHECK-NEXT: mov r3, #0
; CHECK-NEXT: vmov.32 d9[1], r5
-; CHECK-NEXT: sbcs r5, r5, #0
-; CHECK-NEXT: mov r5, #0
-; CHECK-NEXT: movwlo r5, #1
-; CHECK-NEXT: cmp r5, #0
-; CHECK-NEXT: mvnne r5, #0
-; CHECK-NEXT: subs r0, r0, r3
+; CHECK-NEXT: movwlo r3, #1
+; CHECK-NEXT: cmp r3, #0
+; CHECK-NEXT: mvnne r3, #0
+; CHECK-NEXT: adds r0, r0, #1
; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: vmov.32 d8[1], r1
; CHECK-NEXT: movwlo r2, #1
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: vdup.32 d17, r5
+; CHECK-NEXT: vdup.32 d17, r3
; CHECK-NEXT: mvnne r2, #0
; CHECK-NEXT: vdup.32 d16, r2
; CHECK-NEXT: vand q9, q4, q8
@@ -146,24 +144,23 @@ define <2 x i32> @ustest_f64i32(<2 x double> %x) {
; CHECK-NEXT: vmov r0, r1, d8
; CHECK-NEXT: vmov.32 d9[0], r4
; CHECK-NEXT: bl __aeabi_d2lz
+; CHECK-NEXT: adds r3, r4, #1
; CHECK-NEXT: vmov.32 d8[0], r0
-; CHECK-NEXT: mvn r3, #0
-; CHECK-NEXT: subs r4, r4, r3
+; CHECK-NEXT: sbcs r3, r5, #0
; CHECK-NEXT: vmov.i64 q9, #0xffffffff
+; CHECK-NEXT: mov r3, #0
; CHECK-NEXT: vmov.32 d9[1], r5
-; CHECK-NEXT: sbcs r5, r5, #0
-; CHECK-NEXT: mov r5, #0
-; CHECK-NEXT: mov r2, #0
-; CHECK-NEXT: movwlt r5, #1
-; CHECK-NEXT: cmp r5, #0
-; CHECK-NEXT: mvnne r5, #0
-; CHECK-NEXT: subs r0, r0, r3
+; CHECK-NEXT: movwlt r3, #1
+; CHECK-NEXT: cmp r3, #0
+; CHECK-NEXT: mvnne r3, #0
+; CHECK-NEXT: adds r0, r0, #1
; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: vmov.32 d8[1], r1
; CHECK-NEXT: mov r0, #0
+; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: movwlt r0, #1
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: vdup.32 d17, r5
+; CHECK-NEXT: vdup.32 d17, r3
; CHECK-NEXT: mvnne r0, #0
; CHECK-NEXT: vdup.32 d16, r0
; CHECK-NEXT: vbsl q8, q4, q9
@@ -208,79 +205,80 @@ define <4 x i32> @stest_f32i32(<4 x float> %x) {
; CHECK-NEXT: vorr q4, q0, q0
; CHECK-NEXT: vmov r0, s19
; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: mov r6, r0
+; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: vmov r0, s18
-; CHECK-NEXT: mov r7, r1
-; CHECK-NEXT: adr r1, .LCPI3_0
-; CHECK-NEXT: vld1.64 {d10, d11}, [r1:128]
-; CHECK-NEXT: vmov r5, s17
-; CHECK-NEXT: mov r4, #0
-; CHECK-NEXT: mvn r9, #-2147483648
-; CHECK-NEXT: vmov.32 d13[0], r6
+; CHECK-NEXT: mov r6, r1
+; CHECK-NEXT: vmov.32 d13[0], r5
; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: subs r2, r6, r9
-; CHECK-NEXT: vmov.32 d12[0], r0
-; CHECK-NEXT: sbcs r2, r7, #0
-; CHECK-NEXT: vmov r8, s16
-; CHECK-NEXT: mov r2, #0
-; CHECK-NEXT: vmov.32 d13[1], r7
-; CHECK-NEXT: movwlt r2, #1
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: mvnne r2, #0
-; CHECK-NEXT: subs r0, r0, r9
-; CHECK-NEXT: sbcs r0, r1, #0
-; CHECK-NEXT: vdup.32 d17, r2
-; CHECK-NEXT: mov r0, #0
+; CHECK-NEXT: mov r2, r0
+; CHECK-NEXT: vmov r0, s17
+; CHECK-NEXT: adr r3, .LCPI3_0
+; CHECK-NEXT: vmov.32 d12[0], r2
+; CHECK-NEXT: vmov r4, s16
+; CHECK-NEXT: mov r7, #0
+; CHECK-NEXT: vld1.64 {d10, d11}, [r3:128]
+; CHECK-NEXT: adds r3, r5, #-2147483647
+; CHECK-NEXT: sbcs r3, r6, #0
+; CHECK-NEXT: mov r3, #0
+; CHECK-NEXT: vmov.32 d13[1], r6
+; CHECK-NEXT: movwlt r3, #1
+; CHECK-NEXT: cmp r3, #0
+; CHECK-NEXT: mvnne r3, #0
+; CHECK-NEXT: adds r2, r2, #-2147483647
; CHECK-NEXT: vmov.32 d12[1], r1
-; CHECK-NEXT: movwlt r0, #1
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: mvnne r0, #0
-; CHECK-NEXT: vdup.32 d16, r0
-; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: sbcs r1, r1, #0
+; CHECK-NEXT: mov r1, #0
+; CHECK-NEXT: movwlt r1, #1
+; CHECK-NEXT: cmp r1, #0
+; CHECK-NEXT: vdup.32 d17, r3
+; CHECK-NEXT: mvnne r1, #0
+; CHECK-NEXT: vdup.32 d16, r1
; CHECK-NEXT: vorr q4, q8, q8
; CHECK-NEXT: vbsl q4, q6, q5
+; CHECK-NEXT: vmov r9, r8, d8
; CHECK-NEXT: bl __aeabi_f2lz
+; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: vmov.32 d13[0], r0
-; CHECK-NEXT: subs r0, r0, r9
-; CHECK-NEXT: sbcs r0, r1, #0
-; CHECK-NEXT: mov r6, #0
-; CHECK-NEXT: movwlt r6, #1
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: mov r0, r8
-; CHECK-NEXT: vmov r11, r10, d8
-; CHECK-NEXT: vmov.32 d13[1], r1
-; CHECK-NEXT: mvnne r6, #0
-; CHECK-NEXT: vmov r5, r7, d9
+; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: mov r6, r1
+; CHECK-NEXT: vmov r11, r10, d9
; CHECK-NEXT: bl __aeabi_f2lz
+; CHECK-NEXT: adds r2, r5, #-2147483647
; CHECK-NEXT: vmov.32 d12[0], r0
-; CHECK-NEXT: subs r0, r0, r9
+; CHECK-NEXT: sbcs r2, r6, #0
+; CHECK-NEXT: mov r2, #0
+; CHECK-NEXT: vmov.32 d13[1], r6
+; CHECK-NEXT: movwlt r2, #1
+; CHECK-NEXT: cmp r2, #0
+; CHECK-NEXT: mvnne r2, #0
+; CHECK-NEXT: adds r0, r0, #-2147483647
; CHECK-NEXT: sbcs r0, r1, #0
+; CHECK-NEXT: vmov.32 d12[1], r1
; CHECK-NEXT: mov r0, #0
-; CHECK-NEXT: vdup.32 d17, r6
+; CHECK-NEXT: adr r1, .LCPI3_1
; CHECK-NEXT: movwlt r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mvnne r0, #0
-; CHECK-NEXT: vmov.32 d12[1], r1
-; CHECK-NEXT: adr r1, .LCPI3_1
-; CHECK-NEXT: rsbs r3, r11, #-2147483648
+; CHECK-NEXT: vdup.32 d17, r2
; CHECK-NEXT: vdup.32 d16, r0
-; CHECK-NEXT: mvn r0, #0
+; CHECK-NEXT: rsbs r3, r9, #-2147483648
; CHECK-NEXT: vbsl q8, q6, q5
; CHECK-NEXT: vld1.64 {d18, d19}, [r1:128]
-; CHECK-NEXT: sbcs r3, r0, r10
+; CHECK-NEXT: mvn r0, #0
+; CHECK-NEXT: sbcs r3, r0, r8
; CHECK-NEXT: mov r3, #0
; CHECK-NEXT: vmov r1, r2, d17
; CHECK-NEXT: movwlt r3, #1
+; CHECK-NEXT: vmov r5, r4, d16
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: mvnne r3, #0
-; CHECK-NEXT: rsbs r6, r5, #-2147483648
-; CHECK-NEXT: vmov r6, r5, d16
-; CHECK-NEXT: sbcs r7, r0, r7
-; CHECK-NEXT: mov r7, #0
-; CHECK-NEXT: movwlt r7, #1
-; CHECK-NEXT: cmp r7, #0
-; CHECK-NEXT: mvnne r7, #0
-; CHECK-NEXT: vdup.32 d23, r7
+; CHECK-NEXT: rsbs r6, r11, #-2147483648
+; CHECK-NEXT: sbcs r6, r0, r10
+; CHECK-NEXT: mov r6, #0
+; CHECK-NEXT: movwlt r6, #1
+; CHECK-NEXT: cmp r6, #0
+; CHECK-NEXT: mvnne r6, #0
+; CHECK-NEXT: vdup.32 d23, r6
; CHECK-NEXT: vdup.32 d22, r3
; CHECK-NEXT: vbsl q11, q4, q9
; CHECK-NEXT: vmovn.i64 d1, q11
@@ -290,13 +288,13 @@ define <4 x i32> @stest_f32i32(<4 x float> %x) {
; CHECK-NEXT: movwlt r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: mvnne r1, #0
-; CHECK-NEXT: rsbs r2, r6, #-2147483648
-; CHECK-NEXT: sbcs r0, r0, r5
+; CHECK-NEXT: rsbs r2, r5, #-2147483648
+; CHECK-NEXT: sbcs r0, r0, r4
; CHECK-NEXT: vdup.32 d21, r1
-; CHECK-NEXT: movwlt r4, #1
-; CHECK-NEXT: cmp r4, #0
-; CHECK-NEXT: mvnne r4, #0
-; CHECK-NEXT: vdup.32 d20, r4
+; CHECK-NEXT: movwlt r7, #1
+; CHECK-NEXT: cmp r7, #0
+; CHECK-NEXT: mvnne r7, #0
+; CHECK-NEXT: vdup.32 d20, r7
; CHECK-NEXT: vbif q8, q9, q10
; CHECK-NEXT: vmovn.i64 d0, q8
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
@@ -352,38 +350,37 @@ define <4 x i32> @utest_f32i32(<4 x float> %x) {
; CHECK-NEXT: mov r5, r1
; CHECK-NEXT: bl __aeabi_f2ulz
; CHECK-NEXT: vmov.32 d8[0], r0
-; CHECK-NEXT: mvn r3, #0
-; CHECK-NEXT: subs r0, r0, r3
-; CHECK-NEXT: mov r2, #0
+; CHECK-NEXT: adds r0, r0, #1
; CHECK-NEXT: sbcs r0, r1, #0
-; CHECK-NEXT: vmov.32 d9[1], r9
+; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: mov r0, #0
+; CHECK-NEXT: vmov.32 d9[1], r9
; CHECK-NEXT: movwlo r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vmov.32 d8[1], r1
; CHECK-NEXT: mvnne r0, #0
-; CHECK-NEXT: subs r1, r8, r3
+; CHECK-NEXT: adds r1, r8, #1
; CHECK-NEXT: sbcs r1, r9, #0
; CHECK-NEXT: vmov.32 d11[1], r5
; CHECK-NEXT: mov r1, #0
; CHECK-NEXT: movwlo r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: mvnne r1, #0
-; CHECK-NEXT: subs r6, r4, r3
-; CHECK-NEXT: sbcs r6, r5, #0
-; CHECK-NEXT: vdup.32 d19, r1
-; CHECK-NEXT: mov r6, #0
-; CHECK-NEXT: vdup.32 d18, r0
-; CHECK-NEXT: movwlo r6, #1
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: mvnne r6, #0
-; CHECK-NEXT: subs r3, r10, r3
-; CHECK-NEXT: sbcs r3, r7, #0
+; CHECK-NEXT: adds r3, r4, #1
+; CHECK-NEXT: sbcs r3, r5, #0
; CHECK-NEXT: vmov.32 d10[1], r7
+; CHECK-NEXT: mov r3, #0
+; CHECK-NEXT: movwlo r3, #1
+; CHECK-NEXT: cmp r3, #0
+; CHECK-NEXT: mvnne r3, #0
+; CHECK-NEXT: adds r6, r10, #1
+; CHECK-NEXT: sbcs r7, r7, #0
+; CHECK-NEXT: vdup.32 d19, r1
; CHECK-NEXT: movwlo r2, #1
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: vdup.32 d17, r6
+; CHECK-NEXT: vdup.32 d18, r0
; CHECK-NEXT: mvnne r2, #0
+; CHECK-NEXT: vdup.32 d17, r3
; CHECK-NEXT: vand q10, q4, q9
; CHECK-NEXT: vdup.32 d16, r2
; CHECK-NEXT: vand q11, q5, q8
@@ -404,51 +401,50 @@ entry:
define <4 x i32> @ustest_f32i32(<4 x float> %x) {
; CHECK-LABEL: ustest_f32i32:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vorr q4, q0, q0
-; CHECK-NEXT: vmov r0, s18
-; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: vmov r0, s19
-; CHECK-NEXT: mov r6, r1
; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: mov r2, r0
-; CHECK-NEXT: vmov r0, s17
-; CHECK-NEXT: vmov.32 d17[0], r2
-; CHECK-NEXT: mvn r4, #0
-; CHECK-NEXT: subs r2, r2, r4
+; CHECK-NEXT: mov r6, r0
+; CHECK-NEXT: vmov r0, s18
+; CHECK-NEXT: mov r7, r1
+; CHECK-NEXT: vmov r5, s17
+; CHECK-NEXT: vmov.32 d13[0], r6
; CHECK-NEXT: vmov r8, s16
-; CHECK-NEXT: vmov.32 d16[0], r5
+; CHECK-NEXT: bl __aeabi_f2lz
+; CHECK-NEXT: adds r2, r6, #1
+; CHECK-NEXT: vmov.32 d12[0], r0
+; CHECK-NEXT: sbcs r2, r7, #0
; CHECK-NEXT: vmov.i64 q5, #0xffffffff
-; CHECK-NEXT: mov r7, #0
-; CHECK-NEXT: vmov.32 d17[1], r1
-; CHECK-NEXT: sbcs r1, r1, #0
-; CHECK-NEXT: mov r1, #0
-; CHECK-NEXT: movwlt r1, #1
-; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: mvnne r1, #0
-; CHECK-NEXT: subs r2, r5, r4
-; CHECK-NEXT: sbcs r2, r6, #0
-; CHECK-NEXT: vdup.32 d19, r1
; CHECK-NEXT: mov r2, #0
-; CHECK-NEXT: vmov.32 d16[1], r6
+; CHECK-NEXT: vmov.32 d13[1], r7
; CHECK-NEXT: movwlt r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: mvnne r2, #0
-; CHECK-NEXT: vdup.32 d18, r2
-; CHECK-NEXT: vorr q4, q9, q9
-; CHECK-NEXT: vbsl q4, q8, q5
-; CHECK-NEXT: vmov r10, r9, d8
+; CHECK-NEXT: adds r0, r0, #1
+; CHECK-NEXT: sbcs r0, r1, #0
+; CHECK-NEXT: vdup.32 d17, r2
+; CHECK-NEXT: mov r0, #0
+; CHECK-NEXT: vmov.32 d12[1], r1
+; CHECK-NEXT: movwlt r0, #1
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mvnne r0, #0
+; CHECK-NEXT: mov r4, #0
+; CHECK-NEXT: vdup.32 d16, r0
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: vorr q4, q8, q8
+; CHECK-NEXT: vbsl q4, q6, q5
+; CHECK-NEXT: vmov r7, r9, d8
; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: vmov.32 d13[0], r0
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r6, r1
; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: subs r2, r5, r4
+; CHECK-NEXT: adds r2, r5, #1
; CHECK-NEXT: vmov.32 d12[0], r0
; CHECK-NEXT: sbcs r2, r6, #0
; CHECK-NEXT: mov r2, #0
@@ -456,7 +452,7 @@ define <4 x i32> @ustest_f32i32(<4 x float> %x) {
; CHECK-NEXT: movwlt r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: mvnne r2, #0
-; CHECK-NEXT: subs r0, r0, r4
+; CHECK-NEXT: adds r0, r0, #1
; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: vmov.32 d12[1], r1
; CHECK-NEXT: mov r0, #0
@@ -467,14 +463,14 @@ define <4 x i32> @ustest_f32i32(<4 x float> %x) {
; CHECK-NEXT: vdup.32 d16, r0
; CHECK-NEXT: vmov r0, r1, d9
; CHECK-NEXT: vbsl q8, q6, q5
-; CHECK-NEXT: rsbs r6, r10, #0
-; CHECK-NEXT: rscs r6, r9, #0
-; CHECK-NEXT: mov r6, #0
+; CHECK-NEXT: rsbs r7, r7, #0
+; CHECK-NEXT: rscs r7, r9, #0
+; CHECK-NEXT: mov r7, #0
; CHECK-NEXT: vmov r2, r3, d17
-; CHECK-NEXT: movwlt r6, #1
-; CHECK-NEXT: vmov r5, r4, d16
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: mvnne r6, #0
+; CHECK-NEXT: movwlt r7, #1
+; CHECK-NEXT: vmov r6, r5, d16
+; CHECK-NEXT: cmp r7, #0
+; CHECK-NEXT: mvnne r7, #0
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: rscs r0, r1, #0
; CHECK-NEXT: mov r0, #0
@@ -485,23 +481,23 @@ define <4 x i32> @ustest_f32i32(<4 x float> %x) {
; CHECK-NEXT: rscs r1, r3, #0
; CHECK-NEXT: vdup.32 d21, r0
; CHECK-NEXT: mov r1, #0
-; CHECK-NEXT: vdup.32 d20, r6
+; CHECK-NEXT: vdup.32 d20, r7
; CHECK-NEXT: movwlt r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: mvnne r1, #0
-; CHECK-NEXT: rsbs r2, r5, #0
-; CHECK-NEXT: rscs r2, r4, #0
+; CHECK-NEXT: rsbs r2, r6, #0
+; CHECK-NEXT: rscs r2, r5, #0
; CHECK-NEXT: vdup.32 d19, r1
-; CHECK-NEXT: movwlt r7, #1
-; CHECK-NEXT: cmp r7, #0
-; CHECK-NEXT: mvnne r7, #0
+; CHECK-NEXT: movwlt r4, #1
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: mvnne r4, #0
; CHECK-NEXT: vand q10, q10, q4
-; CHECK-NEXT: vdup.32 d18, r7
+; CHECK-NEXT: vdup.32 d18, r4
; CHECK-NEXT: vand q8, q9, q8
; CHECK-NEXT: vmovn.i64 d1, q10
; CHECK-NEXT: vmovn.i64 d0, q8
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
entry:
%conv = fptosi <4 x float> %x to <4 x i64>
%0 = icmp slt <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
@@ -515,95 +511,94 @@ entry:
define <4 x i32> @stest_f16i32(<4 x half> %x) {
; CHECK-NEON-LABEL: stest_f16i32:
; CHECK-NEON: @ %bb.0: @ %entry
-; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEON-NEXT: .pad #4
-; CHECK-NEON-NEXT: sub sp, sp, #4
-; CHECK-NEON-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEON-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEON-NEXT: vmov r0, s2
-; CHECK-NEON-NEXT: vmov.f32 s16, s3
+; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEON-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
+; CHECK-NEON-NEXT: vpush {d8, d9, d10, d11, d12, d13}
+; CHECK-NEON-NEXT: vmov r0, s3
+; CHECK-NEON-NEXT: vmov.f32 s16, s2
; CHECK-NEON-NEXT: vmov.f32 s18, s1
; CHECK-NEON-NEXT: vmov.f32 s20, s0
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2lz
; CHECK-NEON-NEXT: mov r6, r0
; CHECK-NEON-NEXT: vmov r0, s16
-; CHECK-NEON-NEXT: mov r5, r1
+; CHECK-NEON-NEXT: vmov r4, s18
+; CHECK-NEON-NEXT: mov r7, r1
+; CHECK-NEON-NEXT: vmov.32 d9[0], r6
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2lz
-; CHECK-NEON-NEXT: vmov r2, s18
-; CHECK-NEON-NEXT: adr r3, .LCPI6_0
-; CHECK-NEON-NEXT: vld1.64 {d8, d9}, [r3:128]
-; CHECK-NEON-NEXT: mvn r9, #-2147483648
-; CHECK-NEON-NEXT: subs r3, r6, r9
-; CHECK-NEON-NEXT: mov r4, #0
-; CHECK-NEON-NEXT: sbcs r3, r5, #0
-; CHECK-NEON-NEXT: vmov.32 d15[0], r0
-; CHECK-NEON-NEXT: movwlt r4, #1
-; CHECK-NEON-NEXT: cmp r4, #0
-; CHECK-NEON-NEXT: mvnne r4, #0
-; CHECK-NEON-NEXT: subs r0, r0, r9
+; CHECK-NEON-NEXT: adr r2, .LCPI6_0
+; CHECK-NEON-NEXT: vmov r8, s20
+; CHECK-NEON-NEXT: vld1.64 {d10, d11}, [r2:128]
+; CHECK-NEON-NEXT: adds r2, r6, #-2147483647
+; CHECK-NEON-NEXT: sbcs r2, r7, #0
+; CHECK-NEON-NEXT: mov r5, #0
+; CHECK-NEON-NEXT: mov r2, #0
+; CHECK-NEON-NEXT: vmov.32 d8[0], r0
+; CHECK-NEON-NEXT: movwlt r2, #1
+; CHECK-NEON-NEXT: cmp r2, #0
+; CHECK-NEON-NEXT: mvnne r2, #0
+; CHECK-NEON-NEXT: adds r0, r0, #-2147483647
; CHECK-NEON-NEXT: sbcs r0, r1, #0
-; CHECK-NEON-NEXT: vmov.32 d14[0], r6
+; CHECK-NEON-NEXT: vmov.32 d9[1], r7
; CHECK-NEON-NEXT: mov r0, #0
-; CHECK-NEON-NEXT: vmov r8, s20
; CHECK-NEON-NEXT: movwlt r0, #1
; CHECK-NEON-NEXT: cmp r0, #0
+; CHECK-NEON-NEXT: vmov.32 d8[1], r1
; CHECK-NEON-NEXT: mvnne r0, #0
-; CHECK-NEON-NEXT: vmov.32 d15[1], r1
-; CHECK-NEON-NEXT: mov r7, #0
-; CHECK-NEON-NEXT: vdup.32 d11, r0
-; CHECK-NEON-NEXT: vmov.32 d14[1], r5
-; CHECK-NEON-NEXT: mov r0, r2
+; CHECK-NEON-NEXT: vdup.32 d17, r2
+; CHECK-NEON-NEXT: vdup.32 d16, r0
+; CHECK-NEON-NEXT: mov r0, r4
+; CHECK-NEON-NEXT: vbif q4, q5, q8
+; CHECK-NEON-NEXT: vmov r10, r9, d8
; CHECK-NEON-NEXT: bl __aeabi_h2f
-; CHECK-NEON-NEXT: vdup.32 d10, r4
; CHECK-NEON-NEXT: bl __aeabi_f2lz
+; CHECK-NEON-NEXT: mov r4, r0
; CHECK-NEON-NEXT: vmov.32 d13[0], r0
-; CHECK-NEON-NEXT: subs r0, r0, r9
-; CHECK-NEON-NEXT: vbsl q5, q7, q4
-; CHECK-NEON-NEXT: sbcs r0, r1, #0
-; CHECK-NEON-NEXT: mov r6, #0
; CHECK-NEON-NEXT: mov r0, r8
-; CHECK-NEON-NEXT: movwlt r6, #1
-; CHECK-NEON-NEXT: cmp r6, #0
-; CHECK-NEON-NEXT: vmov r11, r10, d10
-; CHECK-NEON-NEXT: vmov.32 d13[1], r1
-; CHECK-NEON-NEXT: mvnne r6, #0
-; CHECK-NEON-NEXT: vmov r5, r4, d11
+; CHECK-NEON-NEXT: mov r6, r1
; CHECK-NEON-NEXT: bl __aeabi_h2f
+; CHECK-NEON-NEXT: vmov r7, r8, d9
; CHECK-NEON-NEXT: bl __aeabi_f2lz
+; CHECK-NEON-NEXT: adds r2, r4, #-2147483647
; CHECK-NEON-NEXT: vmov.32 d12[0], r0
-; CHECK-NEON-NEXT: subs r0, r0, r9
+; CHECK-NEON-NEXT: sbcs r2, r6, #0
+; CHECK-NEON-NEXT: mov r2, #0
+; CHECK-NEON-NEXT: vmov.32 d13[1], r6
+; CHECK-NEON-NEXT: movwlt r2, #1
+; CHECK-NEON-NEXT: cmp r2, #0
+; CHECK-NEON-NEXT: mvnne r2, #0
+; CHECK-NEON-NEXT: adds r0, r0, #-2147483647
; CHECK-NEON-NEXT: sbcs r0, r1, #0
+; CHECK-NEON-NEXT: vmov.32 d12[1], r1
; CHECK-NEON-NEXT: mov r0, #0
-; CHECK-NEON-NEXT: vdup.32 d17, r6
+; CHECK-NEON-NEXT: adr r1, .LCPI6_1
; CHECK-NEON-NEXT: movwlt r0, #1
; CHECK-NEON-NEXT: cmp r0, #0
; CHECK-NEON-NEXT: mvnne r0, #0
-; CHECK-NEON-NEXT: vmov.32 d12[1], r1
-; CHECK-NEON-NEXT: adr r1, .LCPI6_1
-; CHECK-NEON-NEXT: rsbs r3, r11, #-2147483648
+; CHECK-NEON-NEXT: vdup.32 d17, r2
; CHECK-NEON-NEXT: vdup.32 d16, r0
-; CHECK-NEON-NEXT: mvn r0, #0
-; CHECK-NEON-NEXT: vbsl q8, q6, q4
+; CHECK-NEON-NEXT: rsbs r3, r10, #-2147483648
+; CHECK-NEON-NEXT: vbsl q8, q6, q5
; CHECK-NEON-NEXT: vld1.64 {d18, d19}, [r1:128]
-; CHECK-NEON-NEXT: sbcs r3, r0, r10
+; CHECK-NEON-NEXT: mvn r0, #0
+; CHECK-NEON-NEXT: sbcs r3, r0, r9
; CHECK-NEON-NEXT: mov r3, #0
; CHECK-NEON-NEXT: vmov r1, r2, d17
; CHECK-NEON-NEXT: movwlt r3, #1
+; CHECK-NEON-NEXT: vmov r6, r4, d16
; CHECK-NEON-NEXT: cmp r3, #0
; CHECK-NEON-NEXT: mvnne r3, #0
-; CHECK-NEON-NEXT: rsbs r6, r5, #-2147483648
-; CHECK-NEON-NEXT: sbcs r6, r0, r4
-; CHECK-NEON-NEXT: vmov r5, r4, d16
-; CHECK-NEON-NEXT: mov r6, #0
-; CHECK-NEON-NEXT: movwlt r6, #1
-; CHECK-NEON-NEXT: cmp r6, #0
-; CHECK-NEON-NEXT: mvnne r6, #0
-; CHECK-NEON-NEXT: vdup.32 d23, r6
+; CHECK-NEON-NEXT: rsbs r7, r7, #-2147483648
+; CHECK-NEON-NEXT: sbcs r7, r0, r8
+; CHECK-NEON-NEXT: mov r7, #0
+; CHECK-NEON-NEXT: movwlt r7, #1
+; CHECK-NEON-NEXT: cmp r7, #0
+; CHECK-NEON-NEXT: mvnne r7, #0
+; CHECK-NEON-NEXT: vdup.32 d23, r7
; CHECK-NEON-NEXT: vdup.32 d22, r3
-; CHECK-NEON-NEXT: vbsl q11, q5, q9
+; CHECK-NEON-NEXT: vbsl q11, q4, q9
; CHECK-NEON-NEXT: vmovn.i64 d1, q11
; CHECK-NEON-NEXT: rsbs r1, r1, #-2147483648
; CHECK-NEON-NEXT: sbcs r1, r0, r2
@@ -611,18 +606,17 @@ define <4 x i32> @stest_f16i32(<4 x half> %x) {
; CHECK-NEON-NEXT: movwlt r1, #1
; CHECK-NEON-NEXT: cmp r1, #0
; CHECK-NEON-NEXT: mvnne r1, #0
-; CHECK-NEON-NEXT: rsbs r2, r5, #-2147483648
+; CHECK-NEON-NEXT: rsbs r2, r6, #-2147483648
; CHECK-NEON-NEXT: sbcs r0, r0, r4
; CHECK-NEON-NEXT: vdup.32 d21, r1
-; CHECK-NEON-NEXT: movwlt r7, #1
-; CHECK-NEON-NEXT: cmp r7, #0
-; CHECK-NEON-NEXT: mvnne r7, #0
-; CHECK-NEON-NEXT: vdup.32 d20, r7
+; CHECK-NEON-NEXT: movwlt r5, #1
+; CHECK-NEON-NEXT: cmp r5, #0
+; CHECK-NEON-NEXT: mvnne r5, #0
+; CHECK-NEON-NEXT: vdup.32 d20, r5
; CHECK-NEON-NEXT: vbif q8, q9, q10
; CHECK-NEON-NEXT: vmovn.i64 d0, q8
-; CHECK-NEON-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEON-NEXT: add sp, sp, #4
-; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+; CHECK-NEON-NEXT: vpop {d8, d9, d10, d11, d12, d13}
+; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
; CHECK-NEON-NEXT: .p2align 4
; CHECK-NEON-NEXT: @ %bb.1:
; CHECK-NEON-NEXT: .LCPI6_0:
@@ -644,83 +638,84 @@ define <4 x i32> @stest_f16i32(<4 x half> %x) {
; CHECK-FP16-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-FP16-NEXT: vmov.u16 r0, d0[3]
; CHECK-FP16-NEXT: vorr d8, d0, d0
-; CHECK-FP16-NEXT: vmov.u16 r8, d0[0]
-; CHECK-FP16-NEXT: vmov.u16 r9, d0[1]
+; CHECK-FP16-NEXT: vmov.u16 r7, d0[1]
; CHECK-FP16-NEXT: vmov s0, r0
; CHECK-FP16-NEXT: bl __fixhfdi
; CHECK-FP16-NEXT: mov r4, r0
; CHECK-FP16-NEXT: vmov.u16 r0, d8[2]
; CHECK-FP16-NEXT: mov r5, r1
-; CHECK-FP16-NEXT: vmov.32 d9[0], r4
+; CHECK-FP16-NEXT: vmov.32 d11[0], r4
; CHECK-FP16-NEXT: vmov s0, r0
; CHECK-FP16-NEXT: bl __fixhfdi
; CHECK-FP16-NEXT: adr r2, .LCPI6_0
-; CHECK-FP16-NEXT: mvn r10, #-2147483648
-; CHECK-FP16-NEXT: vld1.64 {d10, d11}, [r2:128]
-; CHECK-FP16-NEXT: subs r2, r4, r10
+; CHECK-FP16-NEXT: vmov.32 d10[0], r0
+; CHECK-FP16-NEXT: vmov s0, r7
+; CHECK-FP16-NEXT: mov r6, #0
+; CHECK-FP16-NEXT: vld1.64 {d12, d13}, [r2:128]
+; CHECK-FP16-NEXT: adds r2, r4, #-2147483647
; CHECK-FP16-NEXT: sbcs r2, r5, #0
-; CHECK-FP16-NEXT: vmov s0, r9
; CHECK-FP16-NEXT: mov r2, #0
-; CHECK-FP16-NEXT: vmov.32 d8[0], r0
+; CHECK-FP16-NEXT: vmov.32 d11[1], r5
; CHECK-FP16-NEXT: movwlt r2, #1
; CHECK-FP16-NEXT: cmp r2, #0
; CHECK-FP16-NEXT: mvnne r2, #0
-; CHECK-FP16-NEXT: subs r0, r0, r10
+; CHECK-FP16-NEXT: adds r0, r0, #-2147483647
; CHECK-FP16-NEXT: sbcs r0, r1, #0
-; CHECK-FP16-NEXT: vmov.32 d9[1], r5
+; CHECK-FP16-NEXT: vmov.32 d10[1], r1
; CHECK-FP16-NEXT: mov r0, #0
-; CHECK-FP16-NEXT: mov r6, #0
; CHECK-FP16-NEXT: movwlt r0, #1
; CHECK-FP16-NEXT: cmp r0, #0
-; CHECK-FP16-NEXT: vmov.32 d8[1], r1
-; CHECK-FP16-NEXT: mvnne r0, #0
; CHECK-FP16-NEXT: vdup.32 d17, r2
+; CHECK-FP16-NEXT: mvnne r0, #0
; CHECK-FP16-NEXT: vdup.32 d16, r0
-; CHECK-FP16-NEXT: vbif q4, q5, q8
+; CHECK-FP16-NEXT: vbif q5, q6, q8
+; CHECK-FP16-NEXT: vmov r9, r8, d10
; CHECK-FP16-NEXT: bl __fixhfdi
-; CHECK-FP16-NEXT: vmov.32 d13[0], r0
-; CHECK-FP16-NEXT: subs r0, r0, r10
-; CHECK-FP16-NEXT: vmov s0, r8
-; CHECK-FP16-NEXT: sbcs r0, r1, #0
-; CHECK-FP16-NEXT: mov r7, #0
-; CHECK-FP16-NEXT: vmov r9, r8, d8
-; CHECK-FP16-NEXT: movwlt r7, #1
-; CHECK-FP16-NEXT: cmp r7, #0
-; CHECK-FP16-NEXT: vmov.32 d13[1], r1
-; CHECK-FP16-NEXT: vmov r5, r4, d9
-; CHECK-FP16-NEXT: mvnne r7, #0
+; CHECK-FP16-NEXT: mov r4, r0
+; CHECK-FP16-NEXT: vmov.u16 r0, d8[0]
+; CHECK-FP16-NEXT: mov r5, r1
+; CHECK-FP16-NEXT: vmov.32 d9[0], r4
+; CHECK-FP16-NEXT: vmov r7, r10, d11
+; CHECK-FP16-NEXT: vmov s0, r0
; CHECK-FP16-NEXT: bl __fixhfdi
-; CHECK-FP16-NEXT: vmov.32 d12[0], r0
-; CHECK-FP16-NEXT: subs r0, r0, r10
+; CHECK-FP16-NEXT: adds r2, r4, #-2147483647
+; CHECK-FP16-NEXT: vmov.32 d8[0], r0
+; CHECK-FP16-NEXT: sbcs r2, r5, #0
+; CHECK-FP16-NEXT: mov r2, #0
+; CHECK-FP16-NEXT: vmov.32 d9[1], r5
+; CHECK-FP16-NEXT: movwlt r2, #1
+; CHECK-FP16-NEXT: cmp r2, #0
+; CHECK-FP16-NEXT: mvnne r2, #0
+; CHECK-FP16-NEXT: adds r0, r0, #-2147483647
; CHECK-FP16-NEXT: sbcs r0, r1, #0
+; CHECK-FP16-NEXT: vmov.32 d8[1], r1
; CHECK-FP16-NEXT: mov r0, #0
-; CHECK-FP16-NEXT: vdup.32 d17, r7
+; CHECK-FP16-NEXT: adr r1, .LCPI6_1
; CHECK-FP16-NEXT: movwlt r0, #1
; CHECK-FP16-NEXT: cmp r0, #0
; CHECK-FP16-NEXT: mvnne r0, #0
-; CHECK-FP16-NEXT: vmov.32 d12[1], r1
-; CHECK-FP16-NEXT: adr r1, .LCPI6_1
-; CHECK-FP16-NEXT: rsbs r3, r9, #-2147483648
+; CHECK-FP16-NEXT: vdup.32 d17, r2
; CHECK-FP16-NEXT: vdup.32 d16, r0
-; CHECK-FP16-NEXT: mvn r0, #0
-; CHECK-FP16-NEXT: vbsl q8, q6, q5
+; CHECK-FP16-NEXT: rsbs r3, r9, #-2147483648
+; CHECK-FP16-NEXT: vbsl q8, q4, q6
; CHECK-FP16-NEXT: vld1.64 {d18, d19}, [r1:128]
+; CHECK-FP16-NEXT: mvn r0, #0
; CHECK-FP16-NEXT: sbcs r3, r0, r8
; CHECK-FP16-NEXT: mov r3, #0
; CHECK-FP16-NEXT: vmov r1, r2, d17
; CHECK-FP16-NEXT: movwlt r3, #1
+; CHECK-FP16-NEXT: vmov r5, r4, d16
; CHECK-FP16-NEXT: cmp r3, #0
; CHECK-FP16-NEXT: mvnne r3, #0
-; CHECK-FP16-NEXT: rsbs r7, r5, #-2147483648
-; CHECK-FP16-NEXT: sbcs r7, r0, r4
-; CHECK-FP16-NEXT: vmov r5, r4, d16
+; CHECK-FP16-NEXT: rsbs r7, r7, #-2147483648
+; CHECK-FP16-NEXT: sbcs r7, r0, r10
; CHECK-FP16-NEXT: mov r7, #0
; CHECK-FP16-NEXT: movwlt r7, #1
; CHECK-FP16-NEXT: cmp r7, #0
; CHECK-FP16-NEXT: mvnne r7, #0
; CHECK-FP16-NEXT: vdup.32 d23, r7
; CHECK-FP16-NEXT: vdup.32 d22, r3
-; CHECK-FP16-NEXT: vbsl q11, q4, q9
+; CHECK-FP16-NEXT: vbsl q11, q5, q9
; CHECK-FP16-NEXT: vmovn.i64 d1, q11
; CHECK-FP16-NEXT: rsbs r1, r1, #-2147483648
; CHECK-FP16-NEXT: sbcs r1, r0, r2
@@ -795,38 +790,37 @@ define <4 x i32> @utest_f16i32(<4 x half> %x) {
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2ulz
; CHECK-NEON-NEXT: vmov.32 d8[0], r0
-; CHECK-NEON-NEXT: mvn r3, #0
-; CHECK-NEON-NEXT: subs r0, r0, r3
-; CHECK-NEON-NEXT: mov r2, #0
+; CHECK-NEON-NEXT: adds r0, r0, #1
; CHECK-NEON-NEXT: sbcs r0, r1, #0
-; CHECK-NEON-NEXT: vmov.32 d9[1], r9
+; CHECK-NEON-NEXT: mov r2, #0
; CHECK-NEON-NEXT: mov r0, #0
+; CHECK-NEON-NEXT: vmov.32 d9[1], r9
; CHECK-NEON-NEXT: movwlo r0, #1
; CHECK-NEON-NEXT: cmp r0, #0
; CHECK-NEON-NEXT: vmov.32 d8[1], r1
; CHECK-NEON-NEXT: mvnne r0, #0
-; CHECK-NEON-NEXT: subs r1, r8, r3
+; CHECK-NEON-NEXT: adds r1, r8, #1
; CHECK-NEON-NEXT: sbcs r1, r9, #0
; CHECK-NEON-NEXT: vmov.32 d11[1], r5
; CHECK-NEON-NEXT: mov r1, #0
; CHECK-NEON-NEXT: movwlo r1, #1
; CHECK-NEON-NEXT: cmp r1, #0
; CHECK-NEON-NEXT: mvnne r1, #0
-; CHECK-NEON-NEXT: subs r6, r4, r3
-; CHECK-NEON-NEXT: sbcs r6, r5, #0
-; CHECK-NEON-NEXT: vdup.32 d19, r1
-; CHECK-NEON-NEXT: mov r6, #0
-; CHECK-NEON-NEXT: vdup.32 d18, r0
-; CHECK-NEON-NEXT: movwlo r6, #1
-; CHECK-NEON-NEXT: cmp r6, #0
-; CHECK-NEON-NEXT: mvnne r6, #0
-; CHECK-NEON-NEXT: subs r3, r10, r3
-; CHECK-NEON-NEXT: sbcs r3, r7, #0
+; CHECK-NEON-NEXT: adds r3, r4, #1
+; CHECK-NEON-NEXT: sbcs r3, r5, #0
; CHECK-NEON-NEXT: vmov.32 d10[1], r7
+; CHECK-NEON-NEXT: mov r3, #0
+; CHECK-NEON-NEXT: movwlo r3, #1
+; CHECK-NEON-NEXT: cmp r3, #0
+; CHECK-NEON-NEXT: mvnne r3, #0
+; CHECK-NEON-NEXT: adds r6, r10, #1
+; CHECK-NEON-NEXT: sbcs r7, r7, #0
+; CHECK-NEON-NEXT: vdup.32 d19, r1
; CHECK-NEON-NEXT: movwlo r2, #1
; CHECK-NEON-NEXT: cmp r2, #0
-; CHECK-NEON-NEXT: vdup.32 d17, r6
+; CHECK-NEON-NEXT: vdup.32 d18, r0
; CHECK-NEON-NEXT: mvnne r2, #0
+; CHECK-NEON-NEXT: vdup.32 d17, r3
; CHECK-NEON-NEXT: vand q10, q4, q9
; CHECK-NEON-NEXT: vdup.32 d16, r2
; CHECK-NEON-NEXT: vand q11, q5, q8
@@ -868,37 +862,36 @@ define <4 x i32> @utest_f16i32(<4 x half> %x) {
; CHECK-FP16-NEXT: vmov s0, r0
; CHECK-FP16-NEXT: bl __fixunshfdi
; CHECK-FP16-NEXT: vmov.32 d10[0], r0
-; CHECK-FP16-NEXT: mvn r3, #0
-; CHECK-FP16-NEXT: subs r0, r0, r3
-; CHECK-FP16-NEXT: mov r2, #0
+; CHECK-FP16-NEXT: adds r0, r0, #1
; CHECK-FP16-NEXT: sbcs r0, r1, #0
-; CHECK-FP16-NEXT: vmov.32 d11[1], r7
+; CHECK-FP16-NEXT: mov r2, #0
; CHECK-FP16-NEXT: mov r0, #0
+; CHECK-FP16-NEXT: vmov.32 d11[1], r7
; CHECK-FP16-NEXT: movwlo r0, #1
; CHECK-FP16-NEXT: cmp r0, #0
; CHECK-FP16-NEXT: vmov.32 d10[1], r1
; CHECK-FP16-NEXT: mvnne r0, #0
-; CHECK-FP16-NEXT: subs r1, r6, r3
+; CHECK-FP16-NEXT: adds r1, r6, #1
; CHECK-FP16-NEXT: sbcs r1, r7, #0
; CHECK-FP16-NEXT: vmov.32 d13[1], r5
; CHECK-FP16-NEXT: mov r1, #0
; CHECK-FP16-NEXT: movwlo r1, #1
; CHECK-FP16-NEXT: cmp r1, #0
; CHECK-FP16-NEXT: mvnne r1, #0
-; CHECK-FP16-NEXT: subs r7, r4, r3
-; CHECK-FP16-NEXT: sbcs r7, r5, #0
+; CHECK-FP16-NEXT: adds r3, r4, #1
+; CHECK-FP16-NEXT: sbcs r3, r5, #0
; CHECK-FP16-NEXT: vdup.32 d19, r1
-; CHECK-FP16-NEXT: mov r7, #0
+; CHECK-FP16-NEXT: mov r3, #0
; CHECK-FP16-NEXT: vdup.32 d18, r0
-; CHECK-FP16-NEXT: movwlo r7, #1
-; CHECK-FP16-NEXT: cmp r7, #0
-; CHECK-FP16-NEXT: mvnne r7, #0
-; CHECK-FP16-NEXT: subs r3, r8, r3
-; CHECK-FP16-NEXT: sbcs r3, r9, #0
+; CHECK-FP16-NEXT: movwlo r3, #1
+; CHECK-FP16-NEXT: cmp r3, #0
+; CHECK-FP16-NEXT: mvnne r3, #0
+; CHECK-FP16-NEXT: adds r7, r8, #1
+; CHECK-FP16-NEXT: sbcs r7, r9, #0
; CHECK-FP16-NEXT: vmov.32 d12[1], r9
; CHECK-FP16-NEXT: movwlo r2, #1
; CHECK-FP16-NEXT: cmp r2, #0
-; CHECK-FP16-NEXT: vdup.32 d17, r7
+; CHECK-FP16-NEXT: vdup.32 d17, r3
; CHECK-FP16-NEXT: mvnne r2, #0
; CHECK-FP16-NEXT: vand q10, q5, q9
; CHECK-FP16-NEXT: vdup.32 d16, r2
@@ -921,57 +914,55 @@ entry:
define <4 x i32> @ustest_f16i32(<4 x half> %x) {
; CHECK-NEON-LABEL: ustest_f16i32:
; CHECK-NEON: @ %bb.0: @ %entry
-; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
; CHECK-NEON-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEON-NEXT: vpush {d8, d9, d10, d11, d12, d13}
-; CHECK-NEON-NEXT: vmov r0, s2
-; CHECK-NEON-NEXT: vmov.f32 s16, s3
+; CHECK-NEON-NEXT: vmov r0, s3
+; CHECK-NEON-NEXT: vmov.f32 s16, s2
; CHECK-NEON-NEXT: vmov.f32 s18, s1
; CHECK-NEON-NEXT: vmov.f32 s20, s0
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2lz
-; CHECK-NEON-NEXT: mov r5, r0
+; CHECK-NEON-NEXT: mov r6, r0
; CHECK-NEON-NEXT: vmov r0, s16
-; CHECK-NEON-NEXT: mov r6, r1
+; CHECK-NEON-NEXT: mov r7, r1
; CHECK-NEON-NEXT: bl __aeabi_h2f
+; CHECK-NEON-NEXT: vmov r5, s18
+; CHECK-NEON-NEXT: vmov.32 d9[0], r6
+; CHECK-NEON-NEXT: vmov r8, s20
; CHECK-NEON-NEXT: bl __aeabi_f2lz
-; CHECK-NEON-NEXT: mov r2, r0
-; CHECK-NEON-NEXT: vmov r0, s18
-; CHECK-NEON-NEXT: vmov.32 d17[0], r2
-; CHECK-NEON-NEXT: mvn r8, #0
-; CHECK-NEON-NEXT: subs r2, r2, r8
-; CHECK-NEON-NEXT: vmov r4, s20
-; CHECK-NEON-NEXT: vmov.32 d16[0], r5
+; CHECK-NEON-NEXT: adds r2, r6, #1
+; CHECK-NEON-NEXT: vmov.32 d8[0], r0
+; CHECK-NEON-NEXT: sbcs r2, r7, #0
; CHECK-NEON-NEXT: vmov.i64 q5, #0xffffffff
-; CHECK-NEON-NEXT: mov r7, #0
-; CHECK-NEON-NEXT: vmov.32 d17[1], r1
-; CHECK-NEON-NEXT: sbcs r1, r1, #0
-; CHECK-NEON-NEXT: mov r1, #0
-; CHECK-NEON-NEXT: movwlt r1, #1
-; CHECK-NEON-NEXT: cmp r1, #0
-; CHECK-NEON-NEXT: mvnne r1, #0
-; CHECK-NEON-NEXT: subs r2, r5, r8
-; CHECK-NEON-NEXT: sbcs r2, r6, #0
-; CHECK-NEON-NEXT: vdup.32 d19, r1
; CHECK-NEON-NEXT: mov r2, #0
-; CHECK-NEON-NEXT: vmov.32 d16[1], r6
+; CHECK-NEON-NEXT: vmov.32 d9[1], r7
; CHECK-NEON-NEXT: movwlt r2, #1
; CHECK-NEON-NEXT: cmp r2, #0
; CHECK-NEON-NEXT: mvnne r2, #0
-; CHECK-NEON-NEXT: vdup.32 d18, r2
-; CHECK-NEON-NEXT: vorr q4, q9, q9
-; CHECK-NEON-NEXT: vbsl q4, q8, q5
-; CHECK-NEON-NEXT: vmov r10, r9, d8
+; CHECK-NEON-NEXT: adds r0, r0, #1
+; CHECK-NEON-NEXT: sbcs r0, r1, #0
+; CHECK-NEON-NEXT: vmov.32 d8[1], r1
+; CHECK-NEON-NEXT: mov r0, #0
+; CHECK-NEON-NEXT: mov r4, #0
+; CHECK-NEON-NEXT: movwlt r0, #1
+; CHECK-NEON-NEXT: cmp r0, #0
+; CHECK-NEON-NEXT: vdup.32 d17, r2
+; CHECK-NEON-NEXT: mvnne r0, #0
+; CHECK-NEON-NEXT: vdup.32 d16, r0
+; CHECK-NEON-NEXT: mov r0, r5
+; CHECK-NEON-NEXT: vbif q4, q5, q8
+; CHECK-NEON-NEXT: vmov r7, r9, d8
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2lz
; CHECK-NEON-NEXT: mov r5, r0
; CHECK-NEON-NEXT: vmov.32 d13[0], r0
-; CHECK-NEON-NEXT: mov r0, r4
+; CHECK-NEON-NEXT: mov r0, r8
; CHECK-NEON-NEXT: mov r6, r1
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2lz
-; CHECK-NEON-NEXT: subs r2, r5, r8
+; CHECK-NEON-NEXT: adds r2, r5, #1
; CHECK-NEON-NEXT: vmov.32 d12[0], r0
; CHECK-NEON-NEXT: sbcs r2, r6, #0
; CHECK-NEON-NEXT: mov r2, #0
@@ -979,7 +970,7 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) {
; CHECK-NEON-NEXT: movwlt r2, #1
; CHECK-NEON-NEXT: cmp r2, #0
; CHECK-NEON-NEXT: mvnne r2, #0
-; CHECK-NEON-NEXT: subs r0, r0, r8
+; CHECK-NEON-NEXT: adds r0, r0, #1
; CHECK-NEON-NEXT: sbcs r0, r1, #0
; CHECK-NEON-NEXT: vmov.32 d12[1], r1
; CHECK-NEON-NEXT: mov r0, #0
@@ -990,14 +981,14 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) {
; CHECK-NEON-NEXT: vdup.32 d16, r0
; CHECK-NEON-NEXT: vmov r0, r1, d9
; CHECK-NEON-NEXT: vbsl q8, q6, q5
-; CHECK-NEON-NEXT: rsbs r6, r10, #0
-; CHECK-NEON-NEXT: rscs r6, r9, #0
-; CHECK-NEON-NEXT: mov r6, #0
+; CHECK-NEON-NEXT: rsbs r7, r7, #0
+; CHECK-NEON-NEXT: rscs r7, r9, #0
+; CHECK-NEON-NEXT: mov r7, #0
; CHECK-NEON-NEXT: vmov r2, r3, d17
-; CHECK-NEON-NEXT: movwlt r6, #1
-; CHECK-NEON-NEXT: vmov r5, r4, d16
-; CHECK-NEON-NEXT: cmp r6, #0
-; CHECK-NEON-NEXT: mvnne r6, #0
+; CHECK-NEON-NEXT: movwlt r7, #1
+; CHECK-NEON-NEXT: vmov r6, r5, d16
+; CHECK-NEON-NEXT: cmp r7, #0
+; CHECK-NEON-NEXT: mvnne r7, #0
; CHECK-NEON-NEXT: rsbs r0, r0, #0
; CHECK-NEON-NEXT: rscs r0, r1, #0
; CHECK-NEON-NEXT: mov r0, #0
@@ -1008,33 +999,33 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) {
; CHECK-NEON-NEXT: rscs r1, r3, #0
; CHECK-NEON-NEXT: vdup.32 d21, r0
; CHECK-NEON-NEXT: mov r1, #0
-; CHECK-NEON-NEXT: vdup.32 d20, r6
+; CHECK-NEON-NEXT: vdup.32 d20, r7
; CHECK-NEON-NEXT: movwlt r1, #1
; CHECK-NEON-NEXT: cmp r1, #0
; CHECK-NEON-NEXT: mvnne r1, #0
-; CHECK-NEON-NEXT: rsbs r2, r5, #0
-; CHECK-NEON-NEXT: rscs r2, r4, #0
+; CHECK-NEON-NEXT: rsbs r2, r6, #0
+; CHECK-NEON-NEXT: rscs r2, r5, #0
; CHECK-NEON-NEXT: vdup.32 d19, r1
-; CHECK-NEON-NEXT: movwlt r7, #1
-; CHECK-NEON-NEXT: cmp r7, #0
-; CHECK-NEON-NEXT: mvnne r7, #0
+; CHECK-NEON-NEXT: movwlt r4, #1
+; CHECK-NEON-NEXT: cmp r4, #0
+; CHECK-NEON-NEXT: mvnne r4, #0
; CHECK-NEON-NEXT: vand q10, q10, q4
-; CHECK-NEON-NEXT: vdup.32 d18, r7
+; CHECK-NEON-NEXT: vdup.32 d18, r4
; CHECK-NEON-NEXT: vand q8, q9, q8
; CHECK-NEON-NEXT: vmovn.i64 d1, q10
; CHECK-NEON-NEXT: vmovn.i64 d0, q8
; CHECK-NEON-NEXT: vpop {d8, d9, d10, d11, d12, d13}
-; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
+; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
;
; CHECK-FP16-LABEL: ustest_f16i32:
; CHECK-FP16: @ %bb.0: @ %entry
-; CHECK-FP16-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-FP16-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-FP16-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-FP16-NEXT: push {r4, r5, r6, r7, r8, lr}
; CHECK-FP16-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-FP16-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-FP16-NEXT: vmov.u16 r0, d0[3]
; CHECK-FP16-NEXT: vorr d8, d0, d0
-; CHECK-FP16-NEXT: vmov.u16 r8, d0[1]
+; CHECK-FP16-NEXT: vmov.u16 r7, d0[1]
; CHECK-FP16-NEXT: vmov s0, r0
; CHECK-FP16-NEXT: bl __fixhfdi
; CHECK-FP16-NEXT: mov r4, r0
@@ -1043,29 +1034,28 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) {
; CHECK-FP16-NEXT: vmov.32 d11[0], r4
; CHECK-FP16-NEXT: vmov s0, r0
; CHECK-FP16-NEXT: bl __fixhfdi
-; CHECK-FP16-NEXT: mvn r7, #0
-; CHECK-FP16-NEXT: subs r2, r4, r7
-; CHECK-FP16-NEXT: sbcs r2, r5, #0
+; CHECK-FP16-NEXT: adds r2, r4, #1
; CHECK-FP16-NEXT: vmov.32 d10[0], r0
-; CHECK-FP16-NEXT: mov r2, #0
+; CHECK-FP16-NEXT: sbcs r2, r5, #0
; CHECK-FP16-NEXT: vmov.i64 q6, #0xffffffff
+; CHECK-FP16-NEXT: mov r2, #0
+; CHECK-FP16-NEXT: vmov.32 d11[1], r5
; CHECK-FP16-NEXT: movwlt r2, #1
; CHECK-FP16-NEXT: cmp r2, #0
; CHECK-FP16-NEXT: mvnne r2, #0
-; CHECK-FP16-NEXT: subs r0, r0, r7
+; CHECK-FP16-NEXT: adds r0, r0, #1
; CHECK-FP16-NEXT: sbcs r0, r1, #0
-; CHECK-FP16-NEXT: vmov.32 d11[1], r5
+; CHECK-FP16-NEXT: vmov.32 d10[1], r1
; CHECK-FP16-NEXT: mov r0, #0
-; CHECK-FP16-NEXT: vmov s0, r8
+; CHECK-FP16-NEXT: vmov s0, r7
; CHECK-FP16-NEXT: movwlt r0, #1
; CHECK-FP16-NEXT: cmp r0, #0
-; CHECK-FP16-NEXT: vmov.32 d10[1], r1
-; CHECK-FP16-NEXT: mvnne r0, #0
-; CHECK-FP16-NEXT: mov r6, #0
; CHECK-FP16-NEXT: vdup.32 d17, r2
+; CHECK-FP16-NEXT: mvnne r0, #0
; CHECK-FP16-NEXT: vdup.32 d16, r0
+; CHECK-FP16-NEXT: mov r6, #0
; CHECK-FP16-NEXT: vbif q5, q6, q8
-; CHECK-FP16-NEXT: vmov r9, r8, d10
+; CHECK-FP16-NEXT: vmov r7, r8, d10
; CHECK-FP16-NEXT: bl __fixhfdi
; CHECK-FP16-NEXT: mov r4, r0
; CHECK-FP16-NEXT: vmov.u16 r0, d8[0]
@@ -1073,7 +1063,7 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) {
; CHECK-FP16-NEXT: vmov.32 d9[0], r4
; CHECK-FP16-NEXT: vmov s0, r0
; CHECK-FP16-NEXT: bl __fixhfdi
-; CHECK-FP16-NEXT: subs r2, r4, r7
+; CHECK-FP16-NEXT: adds r2, r4, #1
; CHECK-FP16-NEXT: vmov.32 d8[0], r0
; CHECK-FP16-NEXT: sbcs r2, r5, #0
; CHECK-FP16-NEXT: mov r2, #0
@@ -1081,7 +1071,7 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) {
; CHECK-FP16-NEXT: movwlt r2, #1
; CHECK-FP16-NEXT: cmp r2, #0
; CHECK-FP16-NEXT: mvnne r2, #0
-; CHECK-FP16-NEXT: subs r0, r0, r7
+; CHECK-FP16-NEXT: adds r0, r0, #1
; CHECK-FP16-NEXT: sbcs r0, r1, #0
; CHECK-FP16-NEXT: vmov.32 d8[1], r1
; CHECK-FP16-NEXT: mov r0, #0
@@ -1092,7 +1082,7 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) {
; CHECK-FP16-NEXT: vdup.32 d16, r0
; CHECK-FP16-NEXT: vmov r0, r1, d11
; CHECK-FP16-NEXT: vbsl q8, q4, q6
-; CHECK-FP16-NEXT: rsbs r7, r9, #0
+; CHECK-FP16-NEXT: rsbs r7, r7, #0
; CHECK-FP16-NEXT: rscs r7, r8, #0
; CHECK-FP16-NEXT: mov r7, #0
; CHECK-FP16-NEXT: vmov r2, r3, d17
@@ -1126,7 +1116,7 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) {
; CHECK-FP16-NEXT: vmovn.i64 d1, q10
; CHECK-FP16-NEXT: vmovn.i64 d0, q8
; CHECK-FP16-NEXT: vpop {d8, d9, d10, d11, d12, d13}
-; CHECK-FP16-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
+; CHECK-FP16-NEXT: pop {r4, r5, r6, r7, r8, pc}
entry:
%conv = fptosi <4 x half> %x to <4 x i64>
%0 = icmp slt <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
@@ -1649,17 +1639,15 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) {
; CHECK-NEXT: vorr d0, d9, d9
; CHECK-NEXT: bl __fixdfti
; CHECK-NEXT: mov r4, r1
-; CHECK-NEXT: mvn r9, #0
-; CHECK-NEXT: subs r1, r0, r9
+; CHECK-NEXT: adds r1, r0, #1
; CHECK-NEXT: mvn r5, #-2147483648
; CHECK-NEXT: sbcs r1, r4, r5
-; CHECK-NEXT: vorr d0, d8, d8
; CHECK-NEXT: sbcs r1, r2, #0
-; CHECK-NEXT: mov r7, #0
+; CHECK-NEXT: mvn r9, #0
; CHECK-NEXT: sbcs r1, r3, #0
-; CHECK-NEXT: mov r8, #-2147483648
+; CHECK-NEXT: vorr d0, d8, d8
; CHECK-NEXT: mov r1, #0
-; CHECK-NEXT: mov r10, #0
+; CHECK-NEXT: mov r7, #0
; CHECK-NEXT: movwlt r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: moveq r3, r1
@@ -1667,7 +1655,9 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) {
; CHECK-NEXT: moveq r4, r5
; CHECK-NEXT: moveq r0, r9
; CHECK-NEXT: rsbs r2, r0, #0
+; CHECK-NEXT: mov r8, #-2147483648
; CHECK-NEXT: rscs r2, r4, #-2147483648
+; CHECK-NEXT: mov r10, #0
; CHECK-NEXT: sbcs r1, r9, r1
; CHECK-NEXT: sbcs r1, r9, r3
; CHECK-NEXT: movwlt r7, #1
@@ -1675,7 +1665,7 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) {
; CHECK-NEXT: movne r7, r0
; CHECK-NEXT: moveq r4, r8
; CHECK-NEXT: bl __fixdfti
-; CHECK-NEXT: subs r6, r0, r9
+; CHECK-NEXT: adds r6, r0, #1
; CHECK-NEXT: vmov.32 d1[0], r7
; CHECK-NEXT: sbcs r6, r1, r5
; CHECK-NEXT: sbcs r6, r2, #0
@@ -1828,17 +1818,15 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) {
; CHECK-NEXT: vmov.f32 s0, s17
; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: mov r4, r1
-; CHECK-NEXT: mvn r9, #0
-; CHECK-NEXT: subs r1, r0, r9
+; CHECK-NEXT: adds r1, r0, #1
; CHECK-NEXT: mvn r5, #-2147483648
; CHECK-NEXT: sbcs r1, r4, r5
-; CHECK-NEXT: vmov.f32 s0, s16
; CHECK-NEXT: sbcs r1, r2, #0
-; CHECK-NEXT: mov r7, #0
+; CHECK-NEXT: vmov.f32 s0, s16
; CHECK-NEXT: sbcs r1, r3, #0
-; CHECK-NEXT: mov r8, #-2147483648
+; CHECK-NEXT: mvn r9, #0
; CHECK-NEXT: mov r1, #0
-; CHECK-NEXT: mov r10, #0
+; CHECK-NEXT: mov r7, #0
; CHECK-NEXT: movwlt r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: moveq r3, r1
@@ -1846,7 +1834,9 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) {
; CHECK-NEXT: moveq r4, r5
; CHECK-NEXT: moveq r0, r9
; CHECK-NEXT: rsbs r2, r0, #0
+; CHECK-NEXT: mov r8, #-2147483648
; CHECK-NEXT: rscs r2, r4, #-2147483648
+; CHECK-NEXT: mov r10, #0
; CHECK-NEXT: sbcs r1, r9, r1
; CHECK-NEXT: sbcs r1, r9, r3
; CHECK-NEXT: movwlt r7, #1
@@ -1854,7 +1844,7 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) {
; CHECK-NEXT: movne r7, r0
; CHECK-NEXT: moveq r4, r8
; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: subs r6, r0, r9
+; CHECK-NEXT: adds r6, r0, #1
; CHECK-NEXT: vmov.32 d1[0], r7
; CHECK-NEXT: sbcs r6, r1, r5
; CHECK-NEXT: sbcs r6, r2, #0
@@ -2006,23 +1996,21 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) {
; CHECK-NEON-NEXT: vmov r0, s0
; CHECK-NEON-NEXT: vmov.f32 s16, s1
; CHECK-NEON-NEXT: bl __aeabi_h2f
-; CHECK-NEON-NEXT: mov r8, r0
+; CHECK-NEON-NEXT: mov r5, r0
; CHECK-NEON-NEXT: vmov r0, s16
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: vmov s0, r0
; CHECK-NEON-NEXT: bl __fixsfti
; CHECK-NEON-NEXT: mov r4, r1
-; CHECK-NEON-NEXT: mvn r9, #0
-; CHECK-NEON-NEXT: subs r1, r0, r9
+; CHECK-NEON-NEXT: adds r1, r0, #1
; CHECK-NEON-NEXT: mvn r6, #-2147483648
; CHECK-NEON-NEXT: sbcs r1, r4, r6
-; CHECK-NEON-NEXT: vmov s0, r8
; CHECK-NEON-NEXT: sbcs r1, r2, #0
-; CHECK-NEON-NEXT: mov r5, #0
+; CHECK-NEON-NEXT: mvn r9, #0
; CHECK-NEON-NEXT: sbcs r1, r3, #0
-; CHECK-NEON-NEXT: mov r8, #-2147483648
+; CHECK-NEON-NEXT: vmov s0, r5
; CHECK-NEON-NEXT: mov r1, #0
-; CHECK-NEON-NEXT: mov r10, #0
+; CHECK-NEON-NEXT: mov r5, #0
; CHECK-NEON-NEXT: movwlt r1, #1
; CHECK-NEON-NEXT: cmp r1, #0
; CHECK-NEON-NEXT: moveq r3, r1
@@ -2030,7 +2018,9 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) {
; CHECK-NEON-NEXT: moveq r4, r6
; CHECK-NEON-NEXT: moveq r0, r9
; CHECK-NEON-NEXT: rsbs r2, r0, #0
+; CHECK-NEON-NEXT: mov r8, #-2147483648
; CHECK-NEON-NEXT: rscs r2, r4, #-2147483648
+; CHECK-NEON-NEXT: mov r10, #0
; CHECK-NEON-NEXT: sbcs r1, r9, r1
; CHECK-NEON-NEXT: sbcs r1, r9, r3
; CHECK-NEON-NEXT: movwlt r5, #1
@@ -2038,7 +2028,7 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) {
; CHECK-NEON-NEXT: movne r5, r0
; CHECK-NEON-NEXT: moveq r4, r8
; CHECK-NEON-NEXT: bl __fixsfti
-; CHECK-NEON-NEXT: subs r7, r0, r9
+; CHECK-NEON-NEXT: adds r7, r0, #1
; CHECK-NEON-NEXT: vmov.32 d1[0], r5
; CHECK-NEON-NEXT: sbcs r7, r1, r6
; CHECK-NEON-NEXT: sbcs r7, r2, #0
@@ -2073,17 +2063,15 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) {
; CHECK-FP16-NEXT: vmov s0, r0
; CHECK-FP16-NEXT: bl __fixhfti
; CHECK-FP16-NEXT: mov r4, r1
-; CHECK-FP16-NEXT: mvn r9, #0
-; CHECK-FP16-NEXT: subs r1, r0, r9
+; CHECK-FP16-NEXT: adds r1, r0, #1
; CHECK-FP16-NEXT: mvn r5, #-2147483648
; CHECK-FP16-NEXT: sbcs r1, r4, r5
-; CHECK-FP16-NEXT: vmov s0, r7
; CHECK-FP16-NEXT: sbcs r1, r2, #0
-; CHECK-FP16-NEXT: mov r7, #0
+; CHECK-FP16-NEXT: mvn r9, #0
; CHECK-FP16-NEXT: sbcs r1, r3, #0
-; CHECK-FP16-NEXT: mov r8, #-2147483648
+; CHECK-FP16-NEXT: vmov s0, r7
; CHECK-FP16-NEXT: mov r1, #0
-; CHECK-FP16-NEXT: mov r10, #0
+; CHECK-FP16-NEXT: mov r7, #0
; CHECK-FP16-NEXT: movwlt r1, #1
; CHECK-FP16-NEXT: cmp r1, #0
; CHECK-FP16-NEXT: moveq r3, r1
@@ -2091,7 +2079,9 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) {
; CHECK-FP16-NEXT: moveq r4, r5
; CHECK-FP16-NEXT: moveq r0, r9
; CHECK-FP16-NEXT: rsbs r2, r0, #0
+; CHECK-FP16-NEXT: mov r8, #-2147483648
; CHECK-FP16-NEXT: rscs r2, r4, #-2147483648
+; CHECK-FP16-NEXT: mov r10, #0
; CHECK-FP16-NEXT: sbcs r1, r9, r1
; CHECK-FP16-NEXT: sbcs r1, r9, r3
; CHECK-FP16-NEXT: movwlt r7, #1
@@ -2099,7 +2089,7 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) {
; CHECK-FP16-NEXT: movne r7, r0
; CHECK-FP16-NEXT: moveq r4, r8
; CHECK-FP16-NEXT: bl __fixhfti
-; CHECK-FP16-NEXT: subs r6, r0, r9
+; CHECK-FP16-NEXT: adds r6, r0, #1
; CHECK-FP16-NEXT: vmov.32 d1[0], r7
; CHECK-FP16-NEXT: sbcs r6, r1, r5
; CHECK-FP16-NEXT: sbcs r6, r2, #0
@@ -2352,15 +2342,15 @@ define <2 x i32> @stest_f64i32_mm(<2 x double> %x) {
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r8, r1
; CHECK-NEXT: vmov r0, r1, d9
+; CHECK-NEXT: adds r2, r4, #-2147483647
; CHECK-NEXT: mvn r6, #-2147483648
-; CHECK-NEXT: subs r2, r4, r6
-; CHECK-NEXT: mov r5, #0
; CHECK-NEXT: sbcs r2, r8, #0
-; CHECK-NEXT: mov r7, #0
+; CHECK-NEXT: mov r5, #0
; CHECK-NEXT: movge r4, r6
+; CHECK-NEXT: mov r7, #0
; CHECK-NEXT: movwlt r5, #1
; CHECK-NEXT: bl __aeabi_d2lz
-; CHECK-NEXT: subs r2, r0, r6
+; CHECK-NEXT: adds r2, r0, #-2147483647
; CHECK-NEXT: sbcs r2, r1, #0
; CHECK-NEXT: movlt r6, r0
; CHECK-NEXT: movwlt r7, #1
@@ -2430,25 +2420,25 @@ define <2 x i32> @ustest_f64i32_mm(<2 x double> %x) {
; CHECK-NEXT: vmov r0, r1, d8
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: vmov r2, r12, d9
-; CHECK-NEXT: mvn r4, #0
-; CHECK-NEXT: subs r5, r0, r4
-; CHECK-NEXT: mov r3, #0
+; CHECK-NEXT: adds r5, r0, #1
; CHECK-NEXT: sbcs r5, r1, #0
-; CHECK-NEXT: mov r6, #0
-; CHECK-NEXT: movge r0, r4
+; CHECK-NEXT: mov r3, #0
+; CHECK-NEXT: mvn r4, #0
; CHECK-NEXT: movwlt r3, #1
+; CHECK-NEXT: movge r0, r4
; CHECK-NEXT: cmp r3, #0
-; CHECK-NEXT: mov r5, #0
; CHECK-NEXT: movne r3, r1
; CHECK-NEXT: rsbs r1, r0, #0
; CHECK-NEXT: rscs r1, r3, #0
+; CHECK-NEXT: mov r6, #0
; CHECK-NEXT: movwlt r6, #1
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: movne r6, r0
+; CHECK-NEXT: mov r5, #0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: mov r1, r12
; CHECK-NEXT: bl __aeabi_d2lz
-; CHECK-NEXT: subs r2, r0, r4
+; CHECK-NEXT: adds r2, r0, #1
; CHECK-NEXT: vmov.32 d0[0], r6
; CHECK-NEXT: sbcs r2, r1, #0
; CHECK-NEXT: movlt r4, r0
@@ -2495,7 +2485,7 @@ define <4 x i32> @stest_f32i32_mm(<4 x float> %x) {
; CHECK-NEXT: vmov r7, s16
; CHECK-NEXT: mov r4, #0
; CHECK-NEXT: str r2, [sp, #4] @ 4-byte Spill
-; CHECK-NEXT: subs r2, r11, r6
+; CHECK-NEXT: adds r2, r11, #-2147483647
; CHECK-NEXT: sbcs r2, r1, #0
; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: movge r11, r6
@@ -2507,7 +2497,7 @@ define <4 x i32> @stest_f32i32_mm(<4 x float> %x) {
; CHECK-NEXT: movge r11, r3
; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: mov r5, r0
-; CHECK-NEXT: subs r0, r0, r6
+; CHECK-NEXT: adds r0, r0, #-2147483647
; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: mov r9, #0
; CHECK-NEXT: mov r0, r7
@@ -2517,7 +2507,7 @@ define <4 x i32> @stest_f32i32_mm(<4 x float> %x) {
; CHECK-NEXT: movne r9, r1
; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: mov r7, r0
-; CHECK-NEXT: subs r0, r0, r6
+; CHECK-NEXT: adds r0, r0, #-2147483647
; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: mov r8, #0
; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
@@ -2526,7 +2516,7 @@ define <4 x i32> @stest_f32i32_mm(<4 x float> %x) {
; CHECK-NEXT: cmp r8, #0
; CHECK-NEXT: movne r8, r1
; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: subs r2, r0, r6
+; CHECK-NEXT: adds r2, r0, #-2147483647
; CHECK-NEXT: sbcs r2, r1, #0
; CHECK-NEXT: movlt r6, r0
; CHECK-NEXT: movwlt r4, #1
@@ -2615,11 +2605,9 @@ define <4 x i32> @ustest_f32i32_mm(<4 x float> %x) {
; CHECK-NEXT: vmov r0, s19
; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: vmov r2, s16
-; CHECK-NEXT: mvn r6, #0
-; CHECK-NEXT: subs r3, r0, r6
-; CHECK-NEXT: mov r4, #0
+; CHECK-NEXT: adds r3, r0, #1
; CHECK-NEXT: sbcs r3, r1, #0
-; CHECK-NEXT: vmov r8, s17
+; CHECK-NEXT: mvn r6, #0
; CHECK-NEXT: mov r3, #0
; CHECK-NEXT: movge r0, r6
; CHECK-NEXT: movwlt r3, #1
@@ -2627,14 +2615,16 @@ define <4 x i32> @ustest_f32i32_mm(<4 x float> %x) {
; CHECK-NEXT: movne r3, r1
; CHECK-NEXT: rsbs r1, r0, #0
; CHECK-NEXT: rscs r1, r3, #0
-; CHECK-NEXT: vmov r9, s18
+; CHECK-NEXT: mov r4, #0
; CHECK-NEXT: movwlt r4, #1
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: movne r4, r0
+; CHECK-NEXT: vmov r8, s17
+; CHECK-NEXT: vmov r9, s18
; CHECK-NEXT: mov r10, #0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: subs r2, r0, r6
+; CHECK-NEXT: adds r2, r0, #1
; CHECK-NEXT: mov r5, #0
; CHECK-NEXT: sbcs r2, r1, #0
; CHECK-NEXT: mov r2, #0
@@ -2649,7 +2639,7 @@ define <4 x i32> @ustest_f32i32_mm(<4 x float> %x) {
; CHECK-NEXT: movne r5, r0
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: subs r2, r0, r6
+; CHECK-NEXT: adds r2, r0, #1
; CHECK-NEXT: mov r7, #0
; CHECK-NEXT: sbcs r2, r1, #0
; CHECK-NEXT: mov r2, #0
@@ -2664,7 +2654,7 @@ define <4 x i32> @ustest_f32i32_mm(<4 x float> %x) {
; CHECK-NEXT: movne r7, r0
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: subs r2, r0, r6
+; CHECK-NEXT: adds r2, r0, #1
; CHECK-NEXT: vmov.32 d1[0], r7
; CHECK-NEXT: sbcs r2, r1, #0
; CHECK-NEXT: movlt r6, r0
@@ -2716,7 +2706,7 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) {
; CHECK-NEON-NEXT: vmov r7, s20
; CHECK-NEON-NEXT: mov r4, #0
; CHECK-NEON-NEXT: str r2, [sp, #4] @ 4-byte Spill
-; CHECK-NEON-NEXT: subs r2, r11, r6
+; CHECK-NEON-NEXT: adds r2, r11, #-2147483647
; CHECK-NEON-NEXT: sbcs r2, r1, #0
; CHECK-NEON-NEXT: mov r2, #0
; CHECK-NEON-NEXT: movge r11, r6
@@ -2729,7 +2719,7 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) {
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2lz
; CHECK-NEON-NEXT: mov r5, r0
-; CHECK-NEON-NEXT: subs r0, r0, r6
+; CHECK-NEON-NEXT: adds r0, r0, #-2147483647
; CHECK-NEON-NEXT: sbcs r0, r1, #0
; CHECK-NEON-NEXT: mov r8, #0
; CHECK-NEON-NEXT: mov r0, r7
@@ -2740,7 +2730,7 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) {
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2lz
; CHECK-NEON-NEXT: mov r7, r0
-; CHECK-NEON-NEXT: subs r0, r0, r6
+; CHECK-NEON-NEXT: adds r0, r0, #-2147483647
; CHECK-NEON-NEXT: sbcs r0, r1, #0
; CHECK-NEON-NEXT: mov r9, #0
; CHECK-NEON-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
@@ -2750,7 +2740,7 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) {
; CHECK-NEON-NEXT: movne r9, r1
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2lz
-; CHECK-NEON-NEXT: subs r2, r0, r6
+; CHECK-NEON-NEXT: adds r2, r0, #-2147483647
; CHECK-NEON-NEXT: sbcs r2, r1, #0
; CHECK-NEON-NEXT: movlt r6, r0
; CHECK-NEON-NEXT: movwlt r4, #1
@@ -2784,33 +2774,34 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) {
; CHECK-FP16-NEXT: .vsave {d8, d9}
; CHECK-FP16-NEXT: vpush {d8, d9}
; CHECK-FP16-NEXT: vmov.u16 r0, d0[3]
-; CHECK-FP16-NEXT: vmov.u16 r4, d0[2]
-; CHECK-FP16-NEXT: vmov.u16 r5, d0[0]
-; CHECK-FP16-NEXT: vmov.u16 r6, d0[1]
+; CHECK-FP16-NEXT: vorr d8, d0, d0
; CHECK-FP16-NEXT: vmov s0, r0
; CHECK-FP16-NEXT: bl __fixhfdi
; CHECK-FP16-NEXT: mov r10, r0
+; CHECK-FP16-NEXT: vmov.u16 r0, d8[2]
+; CHECK-FP16-NEXT: vmov.u16 r3, d8[1]
; CHECK-FP16-NEXT: mvn r7, #-2147483648
-; CHECK-FP16-NEXT: subs r0, r0, r7
-; CHECK-FP16-NEXT: vmov s0, r6
+; CHECK-FP16-NEXT: vmov.u16 r2, d8[0]
+; CHECK-FP16-NEXT: mov r6, #-2147483648
+; CHECK-FP16-NEXT: mvn r9, #0
+; CHECK-FP16-NEXT: mov r11, #0
+; CHECK-FP16-NEXT: vmov s16, r0
+; CHECK-FP16-NEXT: adds r0, r10, #-2147483647
; CHECK-FP16-NEXT: sbcs r0, r1, #0
-; CHECK-FP16-NEXT: mov r2, #-2147483648
+; CHECK-FP16-NEXT: vmov s0, r3
; CHECK-FP16-NEXT: mov r0, #0
; CHECK-FP16-NEXT: movge r10, r7
; CHECK-FP16-NEXT: movwlt r0, #1
; CHECK-FP16-NEXT: cmp r0, #0
; CHECK-FP16-NEXT: movne r0, r1
; CHECK-FP16-NEXT: rsbs r1, r10, #-2147483648
-; CHECK-FP16-NEXT: mvn r9, #0
; CHECK-FP16-NEXT: sbcs r0, r9, r0
-; CHECK-FP16-NEXT: vmov s16, r4
-; CHECK-FP16-NEXT: mov r11, #0
-; CHECK-FP16-NEXT: vmov s18, r5
-; CHECK-FP16-NEXT: movge r10, r2
+; CHECK-FP16-NEXT: vmov s18, r2
+; CHECK-FP16-NEXT: movge r10, r6
; CHECK-FP16-NEXT: bl __fixhfdi
; CHECK-FP16-NEXT: vmov.f32 s0, s18
; CHECK-FP16-NEXT: mov r5, r0
-; CHECK-FP16-NEXT: subs r0, r0, r7
+; CHECK-FP16-NEXT: adds r0, r0, #-2147483647
; CHECK-FP16-NEXT: mov r4, #0
; CHECK-FP16-NEXT: sbcs r0, r1, #0
; CHECK-FP16-NEXT: movge r5, r7
@@ -2820,7 +2811,7 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) {
; CHECK-FP16-NEXT: bl __fixhfdi
; CHECK-FP16-NEXT: vmov.f32 s0, s16
; CHECK-FP16-NEXT: mov r6, r0
-; CHECK-FP16-NEXT: subs r0, r0, r7
+; CHECK-FP16-NEXT: adds r0, r0, #-2147483647
; CHECK-FP16-NEXT: mov r8, #0
; CHECK-FP16-NEXT: sbcs r0, r1, #0
; CHECK-FP16-NEXT: movge r6, r7
@@ -2828,7 +2819,7 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) {
; CHECK-FP16-NEXT: cmp r8, #0
; CHECK-FP16-NEXT: movne r8, r1
; CHECK-FP16-NEXT: bl __fixhfdi
-; CHECK-FP16-NEXT: subs r2, r0, r7
+; CHECK-FP16-NEXT: adds r2, r0, #-2147483647
; CHECK-FP16-NEXT: sbcs r2, r1, #0
; CHECK-FP16-NEXT: movlt r7, r0
; CHECK-FP16-NEXT: movwlt r11, #1
@@ -2968,11 +2959,9 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2lz
; CHECK-NEON-NEXT: vmov r2, s20
-; CHECK-NEON-NEXT: mvn r6, #0
-; CHECK-NEON-NEXT: subs r3, r0, r6
-; CHECK-NEON-NEXT: mov r4, #0
+; CHECK-NEON-NEXT: adds r3, r0, #1
; CHECK-NEON-NEXT: sbcs r3, r1, #0
-; CHECK-NEON-NEXT: vmov r8, s18
+; CHECK-NEON-NEXT: mvn r6, #0
; CHECK-NEON-NEXT: mov r3, #0
; CHECK-NEON-NEXT: movge r0, r6
; CHECK-NEON-NEXT: movwlt r3, #1
@@ -2980,15 +2969,17 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {
; CHECK-NEON-NEXT: movne r3, r1
; CHECK-NEON-NEXT: rsbs r1, r0, #0
; CHECK-NEON-NEXT: rscs r1, r3, #0
-; CHECK-NEON-NEXT: vmov r9, s16
+; CHECK-NEON-NEXT: mov r4, #0
; CHECK-NEON-NEXT: movwlt r4, #1
; CHECK-NEON-NEXT: cmp r4, #0
; CHECK-NEON-NEXT: movne r4, r0
+; CHECK-NEON-NEXT: vmov r8, s18
+; CHECK-NEON-NEXT: vmov r9, s16
; CHECK-NEON-NEXT: mov r10, #0
; CHECK-NEON-NEXT: mov r0, r2
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2lz
-; CHECK-NEON-NEXT: subs r2, r0, r6
+; CHECK-NEON-NEXT: adds r2, r0, #1
; CHECK-NEON-NEXT: mov r5, #0
; CHECK-NEON-NEXT: sbcs r2, r1, #0
; CHECK-NEON-NEXT: mov r2, #0
@@ -3004,7 +2995,7 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {
; CHECK-NEON-NEXT: mov r0, r9
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2lz
-; CHECK-NEON-NEXT: subs r2, r0, r6
+; CHECK-NEON-NEXT: adds r2, r0, #1
; CHECK-NEON-NEXT: mov r7, #0
; CHECK-NEON-NEXT: sbcs r2, r1, #0
; CHECK-NEON-NEXT: mov r2, #0
@@ -3020,7 +3011,7 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {
; CHECK-NEON-NEXT: mov r0, r8
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2lz
-; CHECK-NEON-NEXT: subs r2, r0, r6
+; CHECK-NEON-NEXT: adds r2, r0, #1
; CHECK-NEON-NEXT: vmov.32 d1[0], r7
; CHECK-NEON-NEXT: sbcs r2, r1, #0
; CHECK-NEON-NEXT: movlt r6, r0
@@ -3048,18 +3039,18 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {
; CHECK-FP16-NEXT: vmov.u16 r0, d0[3]
; CHECK-FP16-NEXT: vorr d8, d0, d0
; CHECK-FP16-NEXT: vmov.u16 r5, d0[0]
+; CHECK-FP16-NEXT: vmov.u16 r6, d0[2]
; CHECK-FP16-NEXT: vmov s0, r0
; CHECK-FP16-NEXT: bl __fixhfdi
; CHECK-FP16-NEXT: vmov.u16 r2, d8[1]
; CHECK-FP16-NEXT: mvn r4, #0
-; CHECK-FP16-NEXT: vmov.u16 r3, d8[2]
-; CHECK-FP16-NEXT: vmov s0, r5
+; CHECK-FP16-NEXT: vmov s18, r6
; CHECK-FP16-NEXT: mov r6, #0
+; CHECK-FP16-NEXT: vmov s0, r5
; CHECK-FP16-NEXT: mov r8, #0
; CHECK-FP16-NEXT: vmov s16, r2
-; CHECK-FP16-NEXT: subs r2, r0, r4
+; CHECK-FP16-NEXT: adds r2, r0, #1
; CHECK-FP16-NEXT: sbcs r2, r1, #0
-; CHECK-FP16-NEXT: vmov s18, r3
; CHECK-FP16-NEXT: mov r2, #0
; CHECK-FP16-NEXT: movge r0, r4
; CHECK-FP16-NEXT: movwlt r2, #1
@@ -3071,7 +3062,7 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {
; CHECK-FP16-NEXT: cmp r6, #0
; CHECK-FP16-NEXT: movne r6, r0
; CHECK-FP16-NEXT: bl __fixhfdi
-; CHECK-FP16-NEXT: subs r2, r0, r4
+; CHECK-FP16-NEXT: adds r2, r0, #1
; CHECK-FP16-NEXT: vmov.f32 s0, s18
; CHECK-FP16-NEXT: sbcs r2, r1, #0
; CHECK-FP16-NEXT: mov r7, #0
@@ -3086,7 +3077,7 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {
; CHECK-FP16-NEXT: cmp r7, #0
; CHECK-FP16-NEXT: movne r7, r0
; CHECK-FP16-NEXT: bl __fixhfdi
-; CHECK-FP16-NEXT: subs r2, r0, r4
+; CHECK-FP16-NEXT: adds r2, r0, #1
; CHECK-FP16-NEXT: vmov.f32 s0, s16
; CHECK-FP16-NEXT: sbcs r2, r1, #0
; CHECK-FP16-NEXT: mov r5, #0
@@ -3101,7 +3092,7 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {
; CHECK-FP16-NEXT: cmp r5, #0
; CHECK-FP16-NEXT: movne r5, r0
; CHECK-FP16-NEXT: bl __fixhfdi
-; CHECK-FP16-NEXT: subs r2, r0, r4
+; CHECK-FP16-NEXT: adds r2, r0, #1
; CHECK-FP16-NEXT: vmov.32 d1[0], r5
; CHECK-FP16-NEXT: sbcs r2, r1, #0
; CHECK-FP16-NEXT: movlt r4, r0
@@ -3624,17 +3615,15 @@ define <2 x i64> @stest_f64i64_mm(<2 x double> %x) {
; CHECK-NEXT: vorr d0, d9, d9
; CHECK-NEXT: bl __fixdfti
; CHECK-NEXT: mov r4, r1
-; CHECK-NEXT: mvn r9, #0
-; CHECK-NEXT: subs r1, r0, r9
+; CHECK-NEXT: adds r1, r0, #1
; CHECK-NEXT: mvn r5, #-2147483648
; CHECK-NEXT: sbcs r1, r4, r5
-; CHECK-NEXT: vorr d0, d8, d8
; CHECK-NEXT: sbcs r1, r2, #0
-; CHECK-NEXT: mov r7, #0
+; CHECK-NEXT: mvn r9, #0
; CHECK-NEXT: sbcs r1, r3, #0
-; CHECK-NEXT: mov r8, #-2147483648
+; CHECK-NEXT: vorr d0, d8, d8
; CHECK-NEXT: mov r1, #0
-; CHECK-NEXT: mov r10, #0
+; CHECK-NEXT: mov r7, #0
; CHECK-NEXT: movwlt r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: moveq r3, r1
@@ -3642,7 +3631,9 @@ define <2 x i64> @stest_f64i64_mm(<2 x double> %x) {
; CHECK-NEXT: moveq r4, r5
; CHECK-NEXT: moveq r0, r9
; CHECK-NEXT: rsbs r2, r0, #0
+; CHECK-NEXT: mov r8, #-2147483648
; CHECK-NEXT: rscs r2, r4, #-2147483648
+; CHECK-NEXT: mov r10, #0
; CHECK-NEXT: sbcs r1, r9, r1
; CHECK-NEXT: sbcs r1, r9, r3
; CHECK-NEXT: movwlt r7, #1
@@ -3650,7 +3641,7 @@ define <2 x i64> @stest_f64i64_mm(<2 x double> %x) {
; CHECK-NEXT: movne r7, r0
; CHECK-NEXT: moveq r4, r8
; CHECK-NEXT: bl __fixdfti
-; CHECK-NEXT: subs r6, r0, r9
+; CHECK-NEXT: adds r6, r0, #1
; CHECK-NEXT: vmov.32 d1[0], r7
; CHECK-NEXT: sbcs r6, r1, r5
; CHECK-NEXT: sbcs r6, r2, #0
@@ -3784,17 +3775,15 @@ define <2 x i64> @stest_f32i64_mm(<2 x float> %x) {
; CHECK-NEXT: vmov.f32 s0, s17
; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: mov r4, r1
-; CHECK-NEXT: mvn r9, #0
-; CHECK-NEXT: subs r1, r0, r9
+; CHECK-NEXT: adds r1, r0, #1
; CHECK-NEXT: mvn r5, #-2147483648
; CHECK-NEXT: sbcs r1, r4, r5
-; CHECK-NEXT: vmov.f32 s0, s16
; CHECK-NEXT: sbcs r1, r2, #0
-; CHECK-NEXT: mov r7, #0
+; CHECK-NEXT: vmov.f32 s0, s16
; CHECK-NEXT: sbcs r1, r3, #0
-; CHECK-NEXT: mov r8, #-2147483648
+; CHECK-NEXT: mvn r9, #0
; CHECK-NEXT: mov r1, #0
-; CHECK-NEXT: mov r10, #0
+; CHECK-NEXT: mov r7, #0
; CHECK-NEXT: movwlt r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: moveq r3, r1
@@ -3802,7 +3791,9 @@ define <2 x i64> @stest_f32i64_mm(<2 x float> %x) {
; CHECK-NEXT: moveq r4, r5
; CHECK-NEXT: moveq r0, r9
; CHECK-NEXT: rsbs r2, r0, #0
+; CHECK-NEXT: mov r8, #-2147483648
; CHECK-NEXT: rscs r2, r4, #-2147483648
+; CHECK-NEXT: mov r10, #0
; CHECK-NEXT: sbcs r1, r9, r1
; CHECK-NEXT: sbcs r1, r9, r3
; CHECK-NEXT: movwlt r7, #1
@@ -3810,7 +3801,7 @@ define <2 x i64> @stest_f32i64_mm(<2 x float> %x) {
; CHECK-NEXT: movne r7, r0
; CHECK-NEXT: moveq r4, r8
; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: subs r6, r0, r9
+; CHECK-NEXT: adds r6, r0, #1
; CHECK-NEXT: vmov.32 d1[0], r7
; CHECK-NEXT: sbcs r6, r1, r5
; CHECK-NEXT: sbcs r6, r2, #0
@@ -3943,23 +3934,21 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) {
; CHECK-NEON-NEXT: vmov r0, s0
; CHECK-NEON-NEXT: vmov.f32 s16, s1
; CHECK-NEON-NEXT: bl __aeabi_h2f
-; CHECK-NEON-NEXT: mov r8, r0
+; CHECK-NEON-NEXT: mov r5, r0
; CHECK-NEON-NEXT: vmov r0, s16
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: vmov s0, r0
; CHECK-NEON-NEXT: bl __fixsfti
; CHECK-NEON-NEXT: mov r4, r1
-; CHECK-NEON-NEXT: mvn r9, #0
-; CHECK-NEON-NEXT: subs r1, r0, r9
+; CHECK-NEON-NEXT: adds r1, r0, #1
; CHECK-NEON-NEXT: mvn r6, #-2147483648
; CHECK-NEON-NEXT: sbcs r1, r4, r6
-; CHECK-NEON-NEXT: vmov s0, r8
; CHECK-NEON-NEXT: sbcs r1, r2, #0
-; CHECK-NEON-NEXT: mov r5, #0
+; CHECK-NEON-NEXT: mvn r9, #0
; CHECK-NEON-NEXT: sbcs r1, r3, #0
-; CHECK-NEON-NEXT: mov r8, #-2147483648
+; CHECK-NEON-NEXT: vmov s0, r5
; CHECK-NEON-NEXT: mov r1, #0
-; CHECK-NEON-NEXT: mov r10, #0
+; CHECK-NEON-NEXT: mov r5, #0
; CHECK-NEON-NEXT: movwlt r1, #1
; CHECK-NEON-NEXT: cmp r1, #0
; CHECK-NEON-NEXT: moveq r3, r1
@@ -3967,7 +3956,9 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) {
; CHECK-NEON-NEXT: moveq r4, r6
; CHECK-NEON-NEXT: moveq r0, r9
; CHECK-NEON-NEXT: rsbs r2, r0, #0
+; CHECK-NEON-NEXT: mov r8, #-2147483648
; CHECK-NEON-NEXT: rscs r2, r4, #-2147483648
+; CHECK-NEON-NEXT: mov r10, #0
; CHECK-NEON-NEXT: sbcs r1, r9, r1
; CHECK-NEON-NEXT: sbcs r1, r9, r3
; CHECK-NEON-NEXT: movwlt r5, #1
@@ -3975,7 +3966,7 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) {
; CHECK-NEON-NEXT: movne r5, r0
; CHECK-NEON-NEXT: moveq r4, r8
; CHECK-NEON-NEXT: bl __fixsfti
-; CHECK-NEON-NEXT: subs r7, r0, r9
+; CHECK-NEON-NEXT: adds r7, r0, #1
; CHECK-NEON-NEXT: vmov.32 d1[0], r5
; CHECK-NEON-NEXT: sbcs r7, r1, r6
; CHECK-NEON-NEXT: sbcs r7, r2, #0
@@ -4010,17 +4001,15 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) {
; CHECK-FP16-NEXT: vmov s0, r0
; CHECK-FP16-NEXT: bl __fixhfti
; CHECK-FP16-NEXT: mov r4, r1
-; CHECK-FP16-NEXT: mvn r9, #0
-; CHECK-FP16-NEXT: subs r1, r0, r9
+; CHECK-FP16-NEXT: adds r1, r0, #1
; CHECK-FP16-NEXT: mvn r5, #-2147483648
; CHECK-FP16-NEXT: sbcs r1, r4, r5
-; CHECK-FP16-NEXT: vmov s0, r7
; CHECK-FP16-NEXT: sbcs r1, r2, #0
-; CHECK-FP16-NEXT: mov r7, #0
+; CHECK-FP16-NEXT: mvn r9, #0
; CHECK-FP16-NEXT: sbcs r1, r3, #0
-; CHECK-FP16-NEXT: mov r8, #-2147483648
+; CHECK-FP16-NEXT: vmov s0, r7
; CHECK-FP16-NEXT: mov r1, #0
-; CHECK-FP16-NEXT: mov r10, #0
+; CHECK-FP16-NEXT: mov r7, #0
; CHECK-FP16-NEXT: movwlt r1, #1
; CHECK-FP16-NEXT: cmp r1, #0
; CHECK-FP16-NEXT: moveq r3, r1
@@ -4028,7 +4017,9 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) {
; CHECK-FP16-NEXT: moveq r4, r5
; CHECK-FP16-NEXT: moveq r0, r9
; CHECK-FP16-NEXT: rsbs r2, r0, #0
+; CHECK-FP16-NEXT: mov r8, #-2147483648
; CHECK-FP16-NEXT: rscs r2, r4, #-2147483648
+; CHECK-FP16-NEXT: mov r10, #0
; CHECK-FP16-NEXT: sbcs r1, r9, r1
; CHECK-FP16-NEXT: sbcs r1, r9, r3
; CHECK-FP16-NEXT: movwlt r7, #1
@@ -4036,7 +4027,7 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) {
; CHECK-FP16-NEXT: movne r7, r0
; CHECK-FP16-NEXT: moveq r4, r8
; CHECK-FP16-NEXT: bl __fixhfti
-; CHECK-FP16-NEXT: subs r6, r0, r9
+; CHECK-FP16-NEXT: adds r6, r0, #1
; CHECK-FP16-NEXT: vmov.32 d1[0], r7
; CHECK-FP16-NEXT: sbcs r6, r1, r5
; CHECK-FP16-NEXT: sbcs r6, r2, #0
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