[llvm] d565d51 - [LV] Add missing cost tests for various unary and binary ops (NFC) (#196841)
via llvm-commits
llvm-commits at lists.llvm.org
Sun May 10 14:14:32 PDT 2026
Author: Florian Hahn
Date: 2026-05-10T23:14:27+02:00
New Revision: d565d5185be40cf17b07d734c7ee21a5d59e764b
URL: https://github.com/llvm/llvm-project/commit/d565d5185be40cf17b07d734c7ee21a5d59e764b
DIFF: https://github.com/llvm/llvm-project/commit/d565d5185be40cf17b07d734c7ee21a5d59e764b.diff
LOG: [LV] Add missing cost tests for various unary and binary ops (NFC) (#196841)
Added:
Modified:
llvm/test/Transforms/LoopVectorize/AArch64/binop-costs.ll
llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/binop-costs.ll b/llvm/test/Transforms/LoopVectorize/AArch64/binop-costs.ll
index 343276bc9fe30..e42090d556f3c 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/binop-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/binop-costs.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter "[Cc]ost.*udiv"
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter "[Cc]ost.*(udiv|fneg|fmul)"
; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize %s -S -o - 2>&1 | FileCheck %s
; REQUIRES: asserts
@@ -36,4 +36,37 @@ exit:
ret void
}
+define void @fneg_used_by_fmul_scalar_cost_is_zero(ptr %dst) #0 {
+; CHECK-LABEL: 'fneg_used_by_fmul_scalar_cost_is_zero'
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: %neg = fneg double %conv
+; CHECK: LV: Found an estimated cost of 2 for VF 1 For instruction: %mul = fmul double %neg, 2.500000e-04
+; CHECK: Cost of 1 for VF 2: WIDEN ir<%neg> = fneg ir<%conv>
+; CHECK: Cost of 2 for VF 2: WIDEN ir<%mul> = fmul ir<%neg>, ir<2.500000e-04>
+; CHECK: Cost of 0 for VF 2: IR %neg = fneg double %conv
+; CHECK: Cost of 0 for VF 2: IR %mul = fmul double %neg, 2.500000e-04
+; CHECK: Cost of Invalid for VF vscale x 1: WIDEN ir<%neg> = fneg ir<%conv>
+; CHECK: Cost of Invalid for VF vscale x 1: WIDEN ir<%mul> = fmul ir<%neg>, ir<2.500000e-04>
+; CHECK: Cost of 1 for VF vscale x 2: WIDEN ir<%neg> = fneg ir<%conv>
+; CHECK: Cost of 2 for VF vscale x 2: WIDEN ir<%mul> = fmul ir<%neg>, ir<2.500000e-04>
+; CHECK: Cost of 0 for VF vscale x 2: IR %neg = fneg double %conv
+; CHECK: Cost of 0 for VF vscale x 2: IR %mul = fmul double %neg, 2.500000e-04
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %conv = uitofp i64 %iv to double
+ %neg = fneg double %conv
+ %mul = fmul double %neg, 2.500000e-04
+ %gep.dst = getelementptr double, ptr %dst, i64 %iv
+ store double %mul, ptr %gep.dst, align 8
+ %iv.next = add nuw nsw i64 %iv, 1
+ %exitcond = icmp eq i64 %iv.next, 1000
+ br i1 %exitcond, label %exit, label %loop
+
+exit:
+ ret void
+}
+
attributes #0 = { "target-cpu"="neoverse-v2" }
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll b/llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
index e5886d83c0182..92e75f26fffcb 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
@@ -59,3 +59,114 @@ exit:
%res = add i64 %ext, %mul
ret i64 %res
}
+
+; The scalar cost of this loop must include the freeze's cost, otherwise VF=2
+; is incorrectly rejected as unprofitable.
+define i32 @or_reduction_with_freeze(ptr %dst, ptr %src) {
+; CHECK-LABEL: define i32 @or_reduction_with_freeze(
+; CHECK-SAME: ptr [[DST:%.*]], ptr [[SRC:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[SRC7:%.*]] = ptrtoint ptr [[SRC]] to i64
+; CHECK-NEXT: [[DST6:%.*]] = ptrtoint ptr [[DST]] to i64
+; CHECK-NEXT: [[SRC4:%.*]] = ptrtoint ptr [[SRC]] to i64
+; CHECK-NEXT: [[DST3:%.*]] = ptrtoint ptr [[DST]] to i64
+; CHECK-NEXT: [[SRC2:%.*]] = ptrtoint ptr [[SRC]] to i64
+; CHECK-NEXT: [[DST1:%.*]] = ptrtoint ptr [[DST]] to i64
+; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[DST6]], [[SRC7]]
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3
+; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 18
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
+; CHECK: [[VECTOR_SCEVCHECK]]:
+; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[DST1]] to i3
+; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[SRC2]] to i3
+; CHECK-NEXT: [[TMP5:%.*]] = sub i3 [[TMP3]], [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = zext i3 [[TMP5]] to i64
+; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i64 [[TMP6]], 0
+; CHECK-NEXT: br i1 [[IDENT_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_MEMCHECK:.*]]
+; CHECK: [[VECTOR_MEMCHECK]]:
+; CHECK-NEXT: [[TMP7:%.*]] = sub i64 [[DST3]], [[SRC4]]
+; CHECK-NEXT: [[TMP8:%.*]] = lshr i64 [[TMP7]], 3
+; CHECK-NEXT: [[TMP9:%.*]] = shl nuw i64 [[TMP8]], 3
+; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 8
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP10]]
+; CHECK-NEXT: [[SCEVGEP5:%.*]] = getelementptr i8, ptr [[DST]], i64 8
+; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[SRC]], [[SCEVGEP5]]
+; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP]]
+; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
+; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 4
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]]
+; CHECK-NEXT: [[TMP11:%.*]] = load i64, ptr [[DST]], align 8, !alias.scope [[META4:![0-9]+]]
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[TMP11]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT]], <2 x i64> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP12:%.*]] = shl i64 [[N_VEC]], 3
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP12]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i64> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP20:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI8:%.*]] = phi <2 x i64> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP14:%.*]] = shl i64 [[INDEX]], 3
+; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP14]]
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i64 2
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[NEXT_GEP]], align 8, !alias.scope [[META7:![0-9]+]], !noalias [[META4]]
+; CHECK-NEXT: [[WIDE_LOAD9:%.*]] = load <2 x i64>, ptr [[TMP15]], align 8, !alias.scope [[META7]], !noalias [[META4]]
+; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr [[NEXT_GEP]], align 8, !alias.scope [[META7]], !noalias [[META4]]
+; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr [[TMP15]], align 8, !alias.scope [[META7]], !noalias [[META4]]
+; CHECK-NEXT: [[TMP16:%.*]] = or <2 x i64> [[WIDE_LOAD]], [[BROADCAST_SPLAT]]
+; CHECK-NEXT: [[TMP17:%.*]] = or <2 x i64> [[WIDE_LOAD9]], [[BROADCAST_SPLAT]]
+; CHECK-NEXT: [[TMP18:%.*]] = freeze <2 x i64> [[TMP16]]
+; CHECK-NEXT: [[TMP19:%.*]] = freeze <2 x i64> [[TMP17]]
+; CHECK-NEXT: [[TMP20]] = or <2 x i64> [[TMP18]], [[VEC_PHI]]
+; CHECK-NEXT: [[TMP21]] = or <2 x i64> [[TMP19]], [[VEC_PHI8]]
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP22]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[BIN_RDX:%.*]] = or <2 x i64> [[TMP21]], [[TMP20]]
+; CHECK-NEXT: [[TMP23:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[BIN_RDX]])
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP23]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP13]], %[[MIDDLE_BLOCK]] ], [ [[SRC]], %[[ENTRY]] ], [ [[SRC]], %[[VECTOR_SCEVCHECK]] ], [ [[SRC]], %[[VECTOR_MEMCHECK]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[MASK:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[OR:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INCDEC_PTR:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[L_SRC:%.*]] = load i64, ptr [[PTR_IV]], align 8
+; CHECK-NEXT: store i64 0, ptr [[PTR_IV]], align 8
+; CHECK-NEXT: [[L_DST:%.*]] = load i64, ptr [[DST]], align 8
+; CHECK-NEXT: [[OR_1:%.*]] = or i64 [[L_SRC]], [[L_DST]]
+; CHECK-NEXT: [[FR:%.*]] = freeze i64 [[OR_1]]
+; CHECK-NEXT: [[OR]] = or i64 [[FR]], [[MASK]]
+; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr i8, ptr [[PTR_IV]], i64 8
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq ptr [[PTR_IV]], [[DST]]
+; CHECK-NEXT: br i1 [[CMP]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP10:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[OR_LCSSA:%.*]] = phi i64 [ [[OR]], %[[LOOP]] ], [ [[TMP23]], %[[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[CAST:%.*]] = trunc i64 [[OR_LCSSA]] to i32
+; CHECK-NEXT: ret i32 [[CAST]]
+;
+entry:
+ br label %loop
+
+loop:
+ %mask = phi i64 [ 0, %entry ], [ %or, %loop ]
+ %ptr.iv = phi ptr [ %src, %entry ], [ %incdec.ptr, %loop ]
+ %l.src = load i64, ptr %ptr.iv, align 8
+ store i64 0, ptr %ptr.iv, align 8
+ %l.dst = load i64, ptr %dst, align 8
+ %or.1 = or i64 %l.src, %l.dst
+ %fr = freeze i64 %or.1
+ %or = or i64 %fr, %mask
+ %incdec.ptr = getelementptr i8, ptr %ptr.iv, i64 8
+ %cmp = icmp eq ptr %ptr.iv, %dst
+ br i1 %cmp, label %exit, label %loop
+
+exit:
+ %cast = trunc i64 %or to i32
+ ret i32 %cast
+}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
index 77f3f0da07c16..12d32872e1453 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter "Cost of"
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter "LV: Found an estimated cost of [0-9]+ for VF 1 For instruction" --filter "Cost of"
; RUN: opt -S -passes=loop-vectorize -mcpu=skylake-avx512 -mtriple=x86_64-apple-macosx -debug -disable-output -S %s 2>&1 | FileCheck %s
; REQUIRES: asserts
@@ -7,57 +7,70 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:
define void @wide_or_replaced_with_add_vpinstruction(ptr %src, ptr noalias %dst) {
; CHECK-LABEL: 'wide_or_replaced_with_add_vpinstruction'
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: %g.src = getelementptr inbounds i64, ptr %src, i64 %iv
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: %l = load i64, ptr %g.src, align 8
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: %iv.4 = add nuw nsw i64 %iv, 4
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: %c = icmp ule i64 %l, 128
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: br i1 %c, label %loop.then, label %loop.latch
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: %or = or disjoint i64 %iv.4, 1
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: %g.dst = getelementptr inbounds i64, ptr %dst, i64 %or
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: store i64 %iv.4, ptr %g.dst, align 4
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: br label %loop.latch
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: %iv.next = add nuw nsw i64 %iv, 1
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: %exitcond = icmp eq i64 %iv.next, 32
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: br i1 %exitcond, label %exit, label %loop.header
; CHECK: Cost of 1 for VF 2: induction instruction %iv.next = add nuw nsw i64 %iv, 1
; CHECK: Cost of 0 for VF 2: induction instruction %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
; CHECK: Cost of 1 for VF 2: exit condition instruction %exitcond = icmp eq i64 %iv.next, 32
-; CHECK: Cost of 0 for VF 2: ir<%iv> = WIDEN-INDUCTION nuw nsw ir<0>, ir<1>, vp<%0>
-; CHECK: Cost of 0 for VF 2: vp<%4> = SCALAR-STEPS vp<%3>, ir<1>, vp<%0>
-; CHECK: Cost of 0 for VF 2: CLONE ir<%g.src> = getelementptr inbounds ir<%src>, vp<%4>
-; CHECK: Cost of 0 for VF 2: vp<%5> = vector-pointer inbounds ir<%g.src>
-; CHECK: Cost of 1 for VF 2: WIDEN ir<%l> = load vp<%5>
+; CHECK: Cost of 0 for VF 2: ir<%iv> = WIDEN-INDUCTION nuw nsw ir<0>, ir<1>, vp<[[VP0:%[0-9]+]]>
+; CHECK: Cost of 0 for VF 2: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3:%[0-9]+]]>, ir<1>, vp<[[VP0]]>
+; CHECK: Cost of 0 for VF 2: CLONE ir<%g.src> = getelementptr inbounds ir<%src>, vp<[[VP4]]>
+; CHECK: Cost of 0 for VF 2: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%g.src>
+; CHECK: Cost of 1 for VF 2: WIDEN ir<%l> = load vp<[[VP5]]>
; CHECK: Cost of 1 for VF 2: WIDEN ir<%iv.4> = add ir<%iv>, ir<4>
; CHECK: Cost of 1 for VF 2: WIDEN ir<%c> = icmp ule ir<%l>, ir<128>
; CHECK: Cost of 1 for VF 2: EMIT ir<%or> = add ir<%iv.4>, ir<1>
; CHECK: Cost of 0 for VF 2: CLONE ir<%g.dst> = getelementptr ir<%dst>, ir<%or>
-; CHECK: Cost of 0 for VF 2: vp<%6> = vector-pointer ir<%g.dst>
-; CHECK: Cost of 1 for VF 2: WIDEN store vp<%6>, ir<%iv.4>, ir<%c>
-; CHECK: Cost of 0 for VF 2: EMIT vp<%index.next> = add nuw vp<%3>, vp<%1>
-; CHECK: Cost of 0 for VF 2: EMIT branch-on-count vp<%index.next>, vp<%2>
+; CHECK: Cost of 0 for VF 2: vp<[[VP6:%[0-9]+]]> = vector-pointer ir<%g.dst>
+; CHECK: Cost of 1 for VF 2: WIDEN store vp<[[VP6]]>, ir<%iv.4>, ir<%c>
+; CHECK: Cost of 0 for VF 2: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1:%[0-9]+]]>
+; CHECK: Cost of 0 for VF 2: EMIT branch-on-count vp<%index.next>, vp<[[VP2:%[0-9]+]]>
; CHECK: Cost of 0 for VF 2: vector loop backedge
-; CHECK: Cost of 0 for VF 2: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<%2>, middle.block ], [ ir<0>, ir-bb<entry> ]
+; CHECK: Cost of 0 for VF 2: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb<entry> ]
; CHECK: Cost of 0 for VF 2: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] (extra operand: vp<%bc.resume.val> from scalar.ph)
; CHECK: Cost of 0 for VF 2: IR %g.src = getelementptr inbounds i64, ptr %src, i64 %iv
; CHECK: Cost of 0 for VF 2: IR %l = load i64, ptr %g.src, align 8
; CHECK: Cost of 0 for VF 2: IR %iv.4 = add nuw nsw i64 %iv, 4
; CHECK: Cost of 0 for VF 2: IR %c = icmp ule i64 %l, 128
-; CHECK: Cost of 0 for VF 2: EMIT vp<%cmp.n> = icmp eq ir<32>, vp<%2>
+; CHECK: Cost of 0 for VF 2: EMIT vp<%cmp.n> = icmp eq ir<32>, vp<[[VP2]]>
; CHECK: Cost of 0 for VF 2: EMIT branch-on-cond vp<%cmp.n>
; CHECK: Cost of 1 for VF 4: induction instruction %iv.next = add nuw nsw i64 %iv, 1
; CHECK: Cost of 0 for VF 4: induction instruction %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
; CHECK: Cost of 1 for VF 4: exit condition instruction %exitcond = icmp eq i64 %iv.next, 32
-; CHECK: Cost of 0 for VF 4: ir<%iv> = WIDEN-INDUCTION nuw nsw ir<0>, ir<1>, vp<%0>
-; CHECK: Cost of 0 for VF 4: vp<%4> = SCALAR-STEPS vp<%3>, ir<1>, vp<%0>
-; CHECK: Cost of 0 for VF 4: CLONE ir<%g.src> = getelementptr inbounds ir<%src>, vp<%4>
-; CHECK: Cost of 0 for VF 4: vp<%5> = vector-pointer inbounds ir<%g.src>
-; CHECK: Cost of 1 for VF 4: WIDEN ir<%l> = load vp<%5>
+; CHECK: Cost of 0 for VF 4: ir<%iv> = WIDEN-INDUCTION nuw nsw ir<0>, ir<1>, vp<[[VP0]]>
+; CHECK: Cost of 0 for VF 4: vp<[[VP4]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]>
+; CHECK: Cost of 0 for VF 4: CLONE ir<%g.src> = getelementptr inbounds ir<%src>, vp<[[VP4]]>
+; CHECK: Cost of 0 for VF 4: vp<[[VP5]]> = vector-pointer inbounds ir<%g.src>
+; CHECK: Cost of 1 for VF 4: WIDEN ir<%l> = load vp<[[VP5]]>
; CHECK: Cost of 1 for VF 4: WIDEN ir<%iv.4> = add ir<%iv>, ir<4>
; CHECK: Cost of 1 for VF 4: WIDEN ir<%c> = icmp ule ir<%l>, ir<128>
; CHECK: Cost of 1 for VF 4: EMIT ir<%or> = add ir<%iv.4>, ir<1>
; CHECK: Cost of 0 for VF 4: CLONE ir<%g.dst> = getelementptr ir<%dst>, ir<%or>
-; CHECK: Cost of 0 for VF 4: vp<%6> = vector-pointer ir<%g.dst>
-; CHECK: Cost of 1 for VF 4: WIDEN store vp<%6>, ir<%iv.4>, ir<%c>
-; CHECK: Cost of 0 for VF 4: EMIT vp<%index.next> = add nuw vp<%3>, vp<%1>
-; CHECK: Cost of 0 for VF 4: EMIT branch-on-count vp<%index.next>, vp<%2>
+; CHECK: Cost of 0 for VF 4: vp<[[VP6]]> = vector-pointer ir<%g.dst>
+; CHECK: Cost of 1 for VF 4: WIDEN store vp<[[VP6]]>, ir<%iv.4>, ir<%c>
+; CHECK: Cost of 0 for VF 4: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
+; CHECK: Cost of 0 for VF 4: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
; CHECK: Cost of 0 for VF 4: vector loop backedge
-; CHECK: Cost of 0 for VF 4: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<%2>, middle.block ], [ ir<0>, ir-bb<entry> ]
+; CHECK: Cost of 0 for VF 4: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb<entry> ]
; CHECK: Cost of 0 for VF 4: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] (extra operand: vp<%bc.resume.val> from scalar.ph)
; CHECK: Cost of 0 for VF 4: IR %g.src = getelementptr inbounds i64, ptr %src, i64 %iv
; CHECK: Cost of 0 for VF 4: IR %l = load i64, ptr %g.src, align 8
; CHECK: Cost of 0 for VF 4: IR %iv.4 = add nuw nsw i64 %iv, 4
; CHECK: Cost of 0 for VF 4: IR %c = icmp ule i64 %l, 128
-; CHECK: Cost of 0 for VF 4: EMIT vp<%cmp.n> = icmp eq ir<32>, vp<%2>
+; CHECK: Cost of 0 for VF 4: EMIT vp<%cmp.n> = icmp eq ir<32>, vp<[[VP2]]>
; CHECK: Cost of 0 for VF 4: EMIT branch-on-cond vp<%cmp.n>
-; CHECK: Cost of 0 for VF 4: EMIT vp<%cmp.n> = icmp eq ir<32>, vp<%2>
+; CHECK: Cost of 0 for VF 4: EMIT vp<%cmp.n> = icmp eq ir<32>, vp<[[VP2]]>
; CHECK: Cost of 0 for VF 4: EMIT branch-on-cond vp<%cmp.n>
;
entry:
@@ -85,3 +98,283 @@ loop.latch:
exit:
ret void
}
+
+define void @test_vpinstruction_freeze_cost(ptr %src, ptr noalias %dst) {
+; CHECK-LABEL: 'test_vpinstruction_freeze_cost'
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: %g.src = getelementptr inbounds i64, ptr %src, i64 %iv
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: %l = load i64, ptr %g.src, align 8
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: %fr = freeze i64 %l
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: %g.dst = getelementptr inbounds i64, ptr %dst, i64 %iv
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: store i64 %fr, ptr %g.dst, align 8
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: %iv.next = add nuw nsw i64 %iv, 1
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: %ec = icmp eq i64 %iv.next, 32
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: br i1 %ec, label %exit, label %loop
+; CHECK: Cost of 1 for VF 2: induction instruction %iv.next = add nuw nsw i64 %iv, 1
+; CHECK: Cost of 0 for VF 2: induction instruction %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+; CHECK: Cost of 1 for VF 2: exit condition instruction %ec = icmp eq i64 %iv.next, 32
+; CHECK: Cost of 0 for VF 2: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3:%[0-9]+]]>, ir<1>, vp<[[VP0:%[0-9]+]]>
+; CHECK: Cost of 0 for VF 2: CLONE ir<%g.src> = getelementptr inbounds ir<%src>, vp<[[VP4]]>
+; CHECK: Cost of 0 for VF 2: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%g.src>
+; CHECK: Cost of 1 for VF 2: WIDEN ir<%l> = load vp<[[VP5]]>
+; CHECK: Cost of 2 for VF 2: WIDEN ir<%fr> = freeze ir<%l>
+; CHECK: Cost of 0 for VF 2: CLONE ir<%g.dst> = getelementptr inbounds ir<%dst>, vp<[[VP4]]>
+; CHECK: Cost of 0 for VF 2: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%g.dst>
+; CHECK: Cost of 1 for VF 2: WIDEN store vp<[[VP6]]>, ir<%fr>
+; CHECK: Cost of 0 for VF 2: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1:%[0-9]+]]>
+; CHECK: Cost of 0 for VF 2: EMIT branch-on-count vp<%index.next>, vp<[[VP2:%[0-9]+]]>
+; CHECK: Cost of 0 for VF 2: vector loop backedge
+; CHECK: Cost of 0 for VF 2: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb<entry> ]
+; CHECK: Cost of 0 for VF 2: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph)
+; CHECK: Cost of 0 for VF 2: IR %g.src = getelementptr inbounds i64, ptr %src, i64 %iv
+; CHECK: Cost of 0 for VF 2: IR %l = load i64, ptr %g.src, align 8
+; CHECK: Cost of 0 for VF 2: IR %fr = freeze i64 %l
+; CHECK: Cost of 0 for VF 2: IR %g.dst = getelementptr inbounds i64, ptr %dst, i64 %iv
+; CHECK: Cost of 0 for VF 2: IR store i64 %fr, ptr %g.dst, align 8
+; CHECK: Cost of 0 for VF 2: IR %iv.next = add nuw nsw i64 %iv, 1
+; CHECK: Cost of 0 for VF 2: IR %ec = icmp eq i64 %iv.next, 32
+; CHECK: Cost of 0 for VF 2: EMIT vp<%cmp.n> = icmp eq ir<32>, vp<[[VP2]]>
+; CHECK: Cost of 0 for VF 2: EMIT branch-on-cond vp<%cmp.n>
+; CHECK: Cost of 1 for VF 4: induction instruction %iv.next = add nuw nsw i64 %iv, 1
+; CHECK: Cost of 0 for VF 4: induction instruction %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+; CHECK: Cost of 1 for VF 4: exit condition instruction %ec = icmp eq i64 %iv.next, 32
+; CHECK: Cost of 0 for VF 4: vp<[[VP4]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]>
+; CHECK: Cost of 0 for VF 4: CLONE ir<%g.src> = getelementptr inbounds ir<%src>, vp<[[VP4]]>
+; CHECK: Cost of 0 for VF 4: vp<[[VP5]]> = vector-pointer inbounds ir<%g.src>
+; CHECK: Cost of 1 for VF 4: WIDEN ir<%l> = load vp<[[VP5]]>
+; CHECK: Cost of 2 for VF 4: WIDEN ir<%fr> = freeze ir<%l>
+; CHECK: Cost of 0 for VF 4: CLONE ir<%g.dst> = getelementptr inbounds ir<%dst>, vp<[[VP4]]>
+; CHECK: Cost of 0 for VF 4: vp<[[VP6]]> = vector-pointer inbounds ir<%g.dst>
+; CHECK: Cost of 1 for VF 4: WIDEN store vp<[[VP6]]>, ir<%fr>
+; CHECK: Cost of 0 for VF 4: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
+; CHECK: Cost of 0 for VF 4: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
+; CHECK: Cost of 0 for VF 4: vector loop backedge
+; CHECK: Cost of 0 for VF 4: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb<entry> ]
+; CHECK: Cost of 0 for VF 4: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph)
+; CHECK: Cost of 0 for VF 4: IR %g.src = getelementptr inbounds i64, ptr %src, i64 %iv
+; CHECK: Cost of 0 for VF 4: IR %l = load i64, ptr %g.src, align 8
+; CHECK: Cost of 0 for VF 4: IR %fr = freeze i64 %l
+; CHECK: Cost of 0 for VF 4: IR %g.dst = getelementptr inbounds i64, ptr %dst, i64 %iv
+; CHECK: Cost of 0 for VF 4: IR store i64 %fr, ptr %g.dst, align 8
+; CHECK: Cost of 0 for VF 4: IR %iv.next = add nuw nsw i64 %iv, 1
+; CHECK: Cost of 0 for VF 4: IR %ec = icmp eq i64 %iv.next, 32
+; CHECK: Cost of 0 for VF 4: EMIT vp<%cmp.n> = icmp eq ir<32>, vp<[[VP2]]>
+; CHECK: Cost of 0 for VF 4: EMIT branch-on-cond vp<%cmp.n>
+; CHECK: Cost of 0 for VF 4: EMIT vp<%cmp.n> = icmp eq ir<32>, vp<[[VP2]]>
+; CHECK: Cost of 0 for VF 4: EMIT branch-on-cond vp<%cmp.n>
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %g.src = getelementptr inbounds i64, ptr %src, i64 %iv
+ %l = load i64, ptr %g.src, align 8
+ %fr = freeze i64 %l
+ %g.dst = getelementptr inbounds i64, ptr %dst, i64 %iv
+ store i64 %fr, ptr %g.dst, align 8
+ %iv.next = add nuw nsw i64 %iv, 1
+ %ec = icmp eq i64 %iv.next, 32
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @test_vpinstruction_switch_cost(ptr %start, ptr %end) {
+; CHECK-LABEL: 'test_vpinstruction_switch_cost'
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ]
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: %l = load i64, ptr %ptr.iv, align 1
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: switch i64 %l, label %default [
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: store i64 1, ptr %ptr.iv, align 1
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: br label %loop.latch
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: store i64 0, ptr %ptr.iv, align 1
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: br label %loop.latch
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: store i64 42, ptr %ptr.iv, align 1
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: br label %loop.latch
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: store i64 2, ptr %ptr.iv, align 1
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: br label %loop.latch
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: %ptr.iv.next = getelementptr inbounds i64, ptr %ptr.iv, i64 1
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: %ec = icmp eq ptr %ptr.iv.next, %end
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: br i1 %ec, label %exit, label %loop.header
+; CHECK: Cost of 0 for VF 2: induction instruction %ptr.iv.next = getelementptr inbounds i64, ptr %ptr.iv, i64 1
+; CHECK: Cost of 0 for VF 2: induction instruction %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ]
+; CHECK: Cost of 1 for VF 2: exit condition instruction %ec = icmp eq ptr %ptr.iv.next, %end
+; CHECK: Cost of 0 for VF 2: vp<[[VP6:%[0-9]+]]> = DERIVED-IV ir<0> + vp<[[VP5:%[0-9]+]]> * ir<8>
+; CHECK: Cost of 0 for VF 2: vp<[[VP7:%[0-9]+]]> = SCALAR-STEPS vp<[[VP6]]>, ir<8>, vp<[[VP0:%[0-9]+]]>
+; CHECK: Cost of 0 for VF 2: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[VP7]]>
+; CHECK: Cost of 0 for VF 2: vp<[[VP8:%[0-9]+]]> = vector-pointer vp<%next.gep>
+; CHECK: Cost of 1 for VF 2: WIDEN ir<%l> = load vp<[[VP8]]>
+; CHECK: Cost of 1 for VF 2: EMIT vp<[[VP9:%[0-9]+]]> = icmp eq ir<%l>, ir<-12>
+; CHECK: Cost of 1 for VF 2: EMIT vp<[[VP10:%[0-9]+]]> = icmp eq ir<%l>, ir<13>
+; CHECK: Cost of 1 for VF 2: EMIT vp<[[VP11:%[0-9]+]]> = icmp eq ir<%l>, ir<0>
+; CHECK: Cost of 0 for VF 2: EMIT vp<[[VP12:%[0-9]+]]> = or vp<[[VP9]]>, vp<[[VP10]]>
+; CHECK: Cost of 0 for VF 2: EMIT vp<[[VP13:%[0-9]+]]> = or vp<[[VP12]]>, vp<[[VP11]]>
+; CHECK: Cost of 0 for VF 2: EMIT vp<[[VP14:%[0-9]+]]> = not vp<[[VP13]]>
+; CHECK: Cost of 0 for VF 2: vp<[[VP15:%[0-9]+]]> = vector-pointer vp<%next.gep>
+; CHECK: Cost of 1 for VF 2: WIDEN store vp<[[VP15]]>, ir<1>, vp<[[VP11]]>
+; CHECK: Cost of 0 for VF 2: vp<[[VP16:%[0-9]+]]> = vector-pointer vp<%next.gep>
+; CHECK: Cost of 1 for VF 2: WIDEN store vp<[[VP16]]>, ir<0>, vp<[[VP10]]>
+; CHECK: Cost of 0 for VF 2: vp<[[VP17:%[0-9]+]]> = vector-pointer vp<%next.gep>
+; CHECK: Cost of 1 for VF 2: WIDEN store vp<[[VP17]]>, ir<42>, vp<[[VP9]]>
+; CHECK: Cost of 0 for VF 2: vp<[[VP18:%[0-9]+]]> = vector-pointer vp<%next.gep>
+; CHECK: Cost of 1 for VF 2: WIDEN store vp<[[VP18]]>, ir<2>, vp<[[VP14]]>
+; CHECK: Cost of 0 for VF 2: EMIT vp<%index.next> = add nuw vp<[[VP5]]>, vp<[[VP1:%[0-9]+]]>
+; CHECK: Cost of 0 for VF 2: EMIT branch-on-count vp<%index.next>, vp<[[VP2:%[0-9]+]]>
+; CHECK: Cost of 0 for VF 2: vector loop backedge
+; CHECK: Cost of 0 for VF 2: EMIT vp<[[VP3:%[0-9]+]]> = EXPAND SCEV (1 + ((-8 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) /u 8))<nuw><nsw>
+; CHECK: Cost of 0 for VF 2: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP4:%[0-9]+]]>, middle.block ], [ ir<%start>, ir-bb<entry> ]
+; CHECK: Cost of 0 for VF 2: IR %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ] (extra operand: vp<%bc.resume.val> from scalar.ph)
+; CHECK: Cost of 0 for VF 2: IR %l = load i64, ptr %ptr.iv, align 1
+; CHECK: Cost of 0 for VF 2: vp<[[VP4]]> = DERIVED-IV ir<%start> + vp<[[VP2]]> * ir<8>
+; CHECK: Cost of 0 for VF 2: EMIT vp<%cmp.n> = icmp eq vp<[[VP3]]>, vp<[[VP2]]>
+; CHECK: Cost of 0 for VF 2: EMIT branch-on-cond vp<%cmp.n>
+; CHECK: Cost of 0 for VF 4: induction instruction %ptr.iv.next = getelementptr inbounds i64, ptr %ptr.iv, i64 1
+; CHECK: Cost of 0 for VF 4: induction instruction %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ]
+; CHECK: Cost of 1 for VF 4: exit condition instruction %ec = icmp eq ptr %ptr.iv.next, %end
+; CHECK: Cost of 0 for VF 4: vp<[[VP6]]> = DERIVED-IV ir<0> + vp<[[VP5]]> * ir<8>
+; CHECK: Cost of 0 for VF 4: vp<[[VP7]]> = SCALAR-STEPS vp<[[VP6]]>, ir<8>, vp<[[VP0]]>
+; CHECK: Cost of 0 for VF 4: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[VP7]]>
+; CHECK: Cost of 0 for VF 4: vp<[[VP8]]> = vector-pointer vp<%next.gep>
+; CHECK: Cost of 1 for VF 4: WIDEN ir<%l> = load vp<[[VP8]]>
+; CHECK: Cost of 1 for VF 4: EMIT vp<[[VP9]]> = icmp eq ir<%l>, ir<-12>
+; CHECK: Cost of 1 for VF 4: EMIT vp<[[VP10]]> = icmp eq ir<%l>, ir<13>
+; CHECK: Cost of 1 for VF 4: EMIT vp<[[VP11]]> = icmp eq ir<%l>, ir<0>
+; CHECK: Cost of 0 for VF 4: EMIT vp<[[VP12]]> = or vp<[[VP9]]>, vp<[[VP10]]>
+; CHECK: Cost of 0 for VF 4: EMIT vp<[[VP13]]> = or vp<[[VP12]]>, vp<[[VP11]]>
+; CHECK: Cost of 0 for VF 4: EMIT vp<[[VP14]]> = not vp<[[VP13]]>
+; CHECK: Cost of 0 for VF 4: vp<[[VP15]]> = vector-pointer vp<%next.gep>
+; CHECK: Cost of 1 for VF 4: WIDEN store vp<[[VP15]]>, ir<1>, vp<[[VP11]]>
+; CHECK: Cost of 0 for VF 4: vp<[[VP16]]> = vector-pointer vp<%next.gep>
+; CHECK: Cost of 1 for VF 4: WIDEN store vp<[[VP16]]>, ir<0>, vp<[[VP10]]>
+; CHECK: Cost of 0 for VF 4: vp<[[VP17]]> = vector-pointer vp<%next.gep>
+; CHECK: Cost of 1 for VF 4: WIDEN store vp<[[VP17]]>, ir<42>, vp<[[VP9]]>
+; CHECK: Cost of 0 for VF 4: vp<[[VP18]]> = vector-pointer vp<%next.gep>
+; CHECK: Cost of 1 for VF 4: WIDEN store vp<[[VP18]]>, ir<2>, vp<[[VP14]]>
+; CHECK: Cost of 0 for VF 4: EMIT vp<%index.next> = add nuw vp<[[VP5]]>, vp<[[VP1]]>
+; CHECK: Cost of 0 for VF 4: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
+; CHECK: Cost of 0 for VF 4: vector loop backedge
+; CHECK: Cost of 0 for VF 4: EMIT vp<[[VP3]]> = EXPAND SCEV (1 + ((-8 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) /u 8))<nuw><nsw>
+; CHECK: Cost of 0 for VF 4: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP4]]>, middle.block ], [ ir<%start>, ir-bb<entry> ]
+; CHECK: Cost of 0 for VF 4: IR %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ] (extra operand: vp<%bc.resume.val> from scalar.ph)
+; CHECK: Cost of 0 for VF 4: IR %l = load i64, ptr %ptr.iv, align 1
+; CHECK: Cost of 0 for VF 4: vp<[[VP4]]> = DERIVED-IV ir<%start> + vp<[[VP2]]> * ir<8>
+; CHECK: Cost of 0 for VF 4: EMIT vp<%cmp.n> = icmp eq vp<[[VP3]]>, vp<[[VP2]]>
+; CHECK: Cost of 0 for VF 4: EMIT branch-on-cond vp<%cmp.n>
+;
+entry:
+ br label %loop.header
+
+loop.header:
+ %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ]
+ %l = load i64, ptr %ptr.iv, align 1
+ switch i64 %l, label %default [
+ i64 -12, label %case1
+ i64 13, label %case2
+ i64 0, label %case3
+ ]
+
+case1:
+ store i64 42, ptr %ptr.iv, align 1
+ br label %loop.latch
+
+case2:
+ store i64 0, ptr %ptr.iv, align 1
+ br label %loop.latch
+
+case3:
+ store i64 1, ptr %ptr.iv, align 1
+ br label %loop.latch
+
+default:
+ store i64 2, ptr %ptr.iv, align 1
+ br label %loop.latch
+
+loop.latch:
+ %ptr.iv.next = getelementptr inbounds i64, ptr %ptr.iv, i64 1
+ %ec = icmp eq ptr %ptr.iv.next, %end
+ br i1 %ec, label %exit, label %loop.header
+
+exit:
+ ret void
+}
+
+define void @test_vpinstruction_extractvalue_cost(ptr noalias %dst, {i64, i64} %sv) {
+; CHECK-LABEL: 'test_vpinstruction_extractvalue_cost'
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: %a = extractvalue { i64, i64 } %sv, 0
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: %b = extractvalue { i64, i64 } %sv, 1
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: %add = add i64 %a, %b
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: %g.dst = getelementptr inbounds i64, ptr %dst, i64 %iv
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: store i64 %add, ptr %g.dst, align 8
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: %iv.next = add nuw nsw i64 %iv, 1
+; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: %ec = icmp eq i64 %iv.next, 1000
+; CHECK: LV: Found an estimated cost of 0 for VF 1 For instruction: br i1 %ec, label %exit, label %loop
+; CHECK: Cost of 1 for VF 2: induction instruction %iv.next = add nuw nsw i64 %iv, 1
+; CHECK: Cost of 0 for VF 2: induction instruction %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+; CHECK: Cost of 1 for VF 2: exit condition instruction %ec = icmp eq i64 %iv.next, 1000
+; CHECK: Cost of 0 for VF 2: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3:%[0-9]+]]>, ir<1>, vp<[[VP0:%[0-9]+]]>
+; CHECK: Cost of 0 for VF 2: CLONE ir<%g.dst> = getelementptr inbounds ir<%dst>, vp<[[VP4]]>
+; CHECK: Cost of 0 for VF 2: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%g.dst>
+; CHECK: Cost of 1 for VF 2: WIDEN store vp<[[VP5]]>, ir<%add>
+; CHECK: Cost of 0 for VF 2: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1:%[0-9]+]]>
+; CHECK: Cost of 0 for VF 2: EMIT branch-on-count vp<%index.next>, vp<[[VP2:%[0-9]+]]>
+; CHECK: Cost of 0 for VF 2: vector loop backedge
+; CHECK: Cost of 0 for VF 2: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb<entry> ]
+; CHECK: Cost of 0 for VF 2: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph)
+; CHECK: Cost of 0 for VF 2: IR %a = extractvalue { i64, i64 } %sv, 0
+; CHECK: Cost of 0 for VF 2: IR %b = extractvalue { i64, i64 } %sv, 1
+; CHECK: Cost of 0 for VF 2: IR %add = add i64 %a, %b
+; CHECK: Cost of 0 for VF 2: IR %g.dst = getelementptr inbounds i64, ptr %dst, i64 %iv
+; CHECK: Cost of 0 for VF 2: IR store i64 %add, ptr %g.dst, align 8
+; CHECK: Cost of 0 for VF 2: IR %iv.next = add nuw nsw i64 %iv, 1
+; CHECK: Cost of 0 for VF 2: IR %ec = icmp eq i64 %iv.next, 1000
+; CHECK: Cost of 0 for VF 2: CLONE ir<%a> = extractvalue ir<%sv>
+; CHECK: Cost of 0 for VF 2: CLONE ir<%b> = extractvalue ir<%sv>
+; CHECK: Cost of 1 for VF 2: CLONE ir<%add> = add ir<%a>, ir<%b>
+; CHECK: Cost of 0 for VF 2: EMIT vp<%cmp.n> = icmp eq ir<1000>, vp<[[VP2]]>
+; CHECK: Cost of 0 for VF 2: EMIT branch-on-cond vp<%cmp.n>
+; CHECK: Cost of 1 for VF 4: induction instruction %iv.next = add nuw nsw i64 %iv, 1
+; CHECK: Cost of 0 for VF 4: induction instruction %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+; CHECK: Cost of 1 for VF 4: exit condition instruction %ec = icmp eq i64 %iv.next, 1000
+; CHECK: Cost of 0 for VF 4: vp<[[VP4]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]>
+; CHECK: Cost of 0 for VF 4: CLONE ir<%g.dst> = getelementptr inbounds ir<%dst>, vp<[[VP4]]>
+; CHECK: Cost of 0 for VF 4: vp<[[VP5]]> = vector-pointer inbounds ir<%g.dst>
+; CHECK: Cost of 1 for VF 4: WIDEN store vp<[[VP5]]>, ir<%add>
+; CHECK: Cost of 0 for VF 4: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
+; CHECK: Cost of 0 for VF 4: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
+; CHECK: Cost of 0 for VF 4: vector loop backedge
+; CHECK: Cost of 0 for VF 4: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb<entry> ]
+; CHECK: Cost of 0 for VF 4: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph)
+; CHECK: Cost of 0 for VF 4: IR %a = extractvalue { i64, i64 } %sv, 0
+; CHECK: Cost of 0 for VF 4: IR %b = extractvalue { i64, i64 } %sv, 1
+; CHECK: Cost of 0 for VF 4: IR %add = add i64 %a, %b
+; CHECK: Cost of 0 for VF 4: IR %g.dst = getelementptr inbounds i64, ptr %dst, i64 %iv
+; CHECK: Cost of 0 for VF 4: IR store i64 %add, ptr %g.dst, align 8
+; CHECK: Cost of 0 for VF 4: IR %iv.next = add nuw nsw i64 %iv, 1
+; CHECK: Cost of 0 for VF 4: IR %ec = icmp eq i64 %iv.next, 1000
+; CHECK: Cost of 0 for VF 4: CLONE ir<%a> = extractvalue ir<%sv>
+; CHECK: Cost of 0 for VF 4: CLONE ir<%b> = extractvalue ir<%sv>
+; CHECK: Cost of 1 for VF 4: CLONE ir<%add> = add ir<%a>, ir<%b>
+; CHECK: Cost of 0 for VF 4: EMIT vp<%cmp.n> = icmp eq ir<1000>, vp<[[VP2]]>
+; CHECK: Cost of 0 for VF 4: EMIT branch-on-cond vp<%cmp.n>
+; CHECK: Cost of 0 for VF 4: EMIT vp<%cmp.n> = icmp eq ir<1000>, vp<[[VP2]]>
+; CHECK: Cost of 0 for VF 4: EMIT branch-on-cond vp<%cmp.n>
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %a = extractvalue {i64, i64} %sv, 0
+ %b = extractvalue {i64, i64} %sv, 1
+ %add = add i64 %a, %b
+ %g.dst = getelementptr inbounds i64, ptr %dst, i64 %iv
+ store i64 %add, ptr %g.dst, align 8
+ %iv.next = add nuw nsw i64 %iv, 1
+ %ec = icmp eq i64 %iv.next, 1000
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
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