[llvm] 7cc1f32 - [llvm][RISCV] Optimize fabs for fixed vectors (#194554)
via llvm-commits
llvm-commits at lists.llvm.org
Sun May 10 08:58:52 PDT 2026
Author: Brandon Wu
Date: 2026-05-10T23:58:48+08:00
New Revision: 7cc1f32481015e50f29c9caf92524201bbdb0a50
URL: https://github.com/llvm/llvm-project/commit/7cc1f32481015e50f29c9caf92524201bbdb0a50
DIFF: https://github.com/llvm/llvm-project/commit/7cc1f32481015e50f29c9caf92524201bbdb0a50.diff
LOG: [llvm][RISCV] Optimize fabs for fixed vectors (#194554)
vfabs is not available on zvfhmin or zvfbfmin, it's expected to expand
to integer operations instead of unrolling to scalar operations.
General expandFABS already handles that in most of cases except for
fixed vector types that are not promotable, we need to find a better
heuristic to gate this.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
llvm/test/CodeGen/ARM/vfloatintrinsics.ll
llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-sdnode.ll
llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll
llvm/test/CodeGen/Thumb2/mve-vabd.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 21f9bce565efe..c014494679130 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -2102,10 +2102,26 @@ SDValue VectorLegalizer::ExpandFABS(SDNode *Node) {
if (!TLI.isOperationLegalOrCustom(ISD::AND, IntVT))
return SDValue();
- // FIXME: The FSUB check is here to force unrolling v1f64 vectors on AArch64.
- if (!TLI.isOperationLegalOrCustomOrPromote(ISD::FSUB, VT) &&
- !VT.isScalableVector())
- return SDValue();
+ // Heuristic check to determine whether vector should be expanded to integer
+ // operations or unrolled to scalar operations.
+ // 1. Scalable vector is never unrolled.
+ // 2. Fixed vector is unrolled if one of followings is true:
+ // a. Vector only has 1 element and target knows how to handle scalar
+ // FABS(either legal or custom expand or promote).
+ // b. Vector has more than 1 element and target supports scalar
+ // FABS natively and vector length <= 2(1 AND + 1 CONST).
+ // FIXME: Scalar construction instruction count varies in every architecture,
+ // here we assume 1 instruction for now.
+ if (VT.isFixedLengthVector()) {
+ EVT EltVT = VT.getVectorElementType();
+ unsigned NumElts = VT.getVectorNumElements();
+ if ((NumElts == 1 &&
+ TLI.isOperationLegalOrCustomOrPromote(ISD::FABS, EltVT)) ||
+ (NumElts < 3 && TLI.isOperationLegal(ISD::FABS, EltVT) &&
+ TLI.isExtractVecEltCheap(VT, 0) &&
+ (NumElts == 1 || TLI.isExtractVecEltCheap(VT, 1))))
+ return SDValue();
+ }
SDLoc DL(Node);
SDValue Cast = DAG.getNode(ISD::BITCAST, DL, IntVT, Node->getOperand(0));
diff --git a/llvm/test/CodeGen/ARM/vfloatintrinsics.ll b/llvm/test/CodeGen/ARM/vfloatintrinsics.ll
index 74782d44c7423..60e772961236a 100644
--- a/llvm/test/CodeGen/ARM/vfloatintrinsics.ll
+++ b/llvm/test/CodeGen/ARM/vfloatintrinsics.ll
@@ -341,8 +341,8 @@ define %v2f64 @test_v2f64.fma(%v2f64 %a, %v2f64 %b, %v2f64 %c) {
}
; CHECK-LABEL: test_v2f64.fabs:{{.*}}
define %v2f64 @test_v2f64.fabs(%v2f64 %a) {
- ; CHECK: bfc {{r[1,3]}}, #31, #1
- ; CHECK: bfc {{r[1,3]}}, #31, #1
+ ; CHECK: vld1.64
+ ; CHECK: vand
%1 = call %v2f64 @llvm.fabs.v2f64(%v2f64 %a)
ret %v2f64 %1
}
diff --git a/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll b/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
index 3ebaf68d4a15f..9ba15737ff641 100644
--- a/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
@@ -1794,33 +1794,15 @@ define <2 x half> @test_fma(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
}
define <2 x half> @test_fabs(<2 x half> %a) #0 {
-; CHECK-F16-LABEL: test_fabs(
-; CHECK-F16: {
-; CHECK-F16-NEXT: .reg .b32 %r<3>;
-; CHECK-F16-EMPTY:
-; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fabs_param_0];
-; CHECK-F16-NEXT: and.b32 %r2, %r1, 2147450879;
-; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-F16-NEXT: ret;
-;
-; CHECK-NOF16-LABEL: test_fabs(
-; CHECK-NOF16: {
-; CHECK-NOF16-NEXT: .reg .b16 %rs<5>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
-; CHECK-NOF16-EMPTY:
-; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fabs_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
-; CHECK-NOF16-NEXT: abs.f32 %r3, %r2;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs3, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
-; CHECK-NOF16-NEXT: abs.f32 %r5, %r4;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs4, %r5;
-; CHECK-NOF16-NEXT: mov.b32 %r6, {%rs4, %rs3};
-; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r6;
-; CHECK-NOF16-NEXT: ret;
+; CHECK-LABEL: test_fabs(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_fabs_param_0];
+; CHECK-NEXT: and.b32 %r2, %r1, 2147450879;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.fabs.f16(<2 x half> %a)
ret <2 x half> %r
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-sdnode.ll
index 27c00de3c3487..5b76750e441aa 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-sdnode.ll
@@ -1,66 +1,205 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfa,+v \
-; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfa,+v \
-; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+experimental-zvfbfa \
+; RUN: -target-abi=ilp32d -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFA
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+experimental-zvfbfa \
+; RUN: -target-abi=lp64d -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFA
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin -target-abi=ilp32d \
+; RUN: -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin -target-abi=lp64d \
+; RUN: -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN
define <1 x bfloat> @v1bf16(<1 x bfloat> %v) {
-; CHECK-LABEL: v1bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: v1bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfabs.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: v1bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: addi a0, a0, -1
+; ZVFBFMIN-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a0
+; ZVFBFMIN-NEXT: ret
%r = call <1 x bfloat> @llvm.fabs.v1bf16(<1 x bfloat> %v)
ret <1 x bfloat> %r
}
define <2 x bfloat> @v2bf16(<2 x bfloat> %v) {
-; CHECK-LABEL: v2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: v2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfabs.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: v2bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: addi a0, a0, -1
+; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a0
+; ZVFBFMIN-NEXT: ret
%r = call <2 x bfloat> @llvm.fabs.v2bf16(<2 x bfloat> %v)
ret <2 x bfloat> %r
}
define <4 x bfloat> @v4bf16(<4 x bfloat> %v) {
-; CHECK-LABEL: v4bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: v4bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfabs.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: v4bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: addi a0, a0, -1
+; ZVFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a0
+; ZVFBFMIN-NEXT: ret
%r = call <4 x bfloat> @llvm.fabs.v4bf16(<4 x bfloat> %v)
ret <4 x bfloat> %r
}
define <8 x bfloat> @v8bf16(<8 x bfloat> %v) {
-; CHECK-LABEL: v8bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16alt, m1, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: v8bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 8, e16alt, m1, ta, ma
+; ZVFBFA-NEXT: vfabs.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: v8bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: addi a0, a0, -1
+; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a0
+; ZVFBFMIN-NEXT: ret
%r = call <8 x bfloat> @llvm.fabs.v8bf16(<8 x bfloat> %v)
ret <8 x bfloat> %r
}
define <16 x bfloat> @v16bf16(<16 x bfloat> %v) {
-; CHECK-LABEL: v16bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e16alt, m2, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: v16bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 16, e16alt, m2, ta, ma
+; ZVFBFA-NEXT: vfabs.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: v16bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: addi a0, a0, -1
+; ZVFBFMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a0
+; ZVFBFMIN-NEXT: ret
%r = call <16 x bfloat> @llvm.fabs.v16bf16(<16 x bfloat> %v)
ret <16 x bfloat> %r
}
define <32 x bfloat> @v32bf16(<32 x bfloat> %v) {
-; CHECK-LABEL: v32bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: v32bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: li a0, 32
+; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfabs.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: v32bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: addi a0, a0, -1
+; ZVFBFMIN-NEXT: li a1, 32
+; ZVFBFMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a0
+; ZVFBFMIN-NEXT: ret
%r = call <32 x bfloat> @llvm.fabs.v32bf16(<32 x bfloat> %v)
ret <32 x bfloat> %r
}
+
+define <64 x bfloat> @v64bf16(<64 x bfloat> %v) {
+; ZVFBFA-LABEL: v64bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: li a0, 64
+; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma
+; ZVFBFA-NEXT: vfabs.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: v64bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: addi a0, a0, -1
+; ZVFBFMIN-NEXT: li a1, 64
+; ZVFBFMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a0
+; ZVFBFMIN-NEXT: ret
+ %r = call <64 x bfloat> @llvm.fabs.v64bf16(<64 x bfloat> %v)
+ ret <64 x bfloat> %r
+}
+
+define <1 x half> @v1f16(<1 x half> %v) {
+; CHECK-LABEL: v1f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 8
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %r = call <1 x half> @llvm.fabs.v1f16(<1 x half> %v)
+ ret <1 x half> %r
+}
+
+define <2 x half> @v2f16(<2 x half> %v) {
+; CHECK-LABEL: v2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 8
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %r = call <2 x half> @llvm.fabs.v2f16(<2 x half> %v)
+ ret <2 x half> %r
+}
+
+define <8 x half> @v8f16(<8 x half> %v) {
+; CHECK-LABEL: v8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 8
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %r = call <8 x half> @llvm.fabs.v8f16(<8 x half> %v)
+ ret <8 x half> %r
+}
+
+define <32 x half> @v32f16(<32 x half> %v) {
+; CHECK-LABEL: v32f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 8
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: li a1, 32
+; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %r = call <32 x half> @llvm.fabs.v32f16(<32 x half> %v)
+ ret <32 x half> %r
+}
+
+define <64 x half> @v64f16(<64 x half> %v) {
+; CHECK-LABEL: v64f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 8
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: li a1, 64
+; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %r = call <64 x half> @llvm.fabs.v64f16(<64 x half> %v)
+ ret <64 x half> %r
+}
diff --git a/llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll b/llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll
index 8b8b897a32eda..c2cf7f9701e6d 100644
--- a/llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll
@@ -56,22 +56,7 @@ entry:
define arm_aapcs_vfpcc <8 x half> @fabs_float16_t(<8 x half> %src) {
; CHECK-MVE-LABEL: fabs_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vmovx.f16 s4, s0
-; CHECK-MVE-NEXT: vabs.f16 s0, s0
-; CHECK-MVE-NEXT: vabs.f16 s4, s4
-; CHECK-MVE-NEXT: vins.f16 s0, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s1
-; CHECK-MVE-NEXT: vabs.f16 s4, s4
-; CHECK-MVE-NEXT: vabs.f16 s1, s1
-; CHECK-MVE-NEXT: vins.f16 s1, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s2
-; CHECK-MVE-NEXT: vabs.f16 s4, s4
-; CHECK-MVE-NEXT: vabs.f16 s2, s2
-; CHECK-MVE-NEXT: vins.f16 s2, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s3
-; CHECK-MVE-NEXT: vabs.f16 s4, s4
-; CHECK-MVE-NEXT: vabs.f16 s3, s3
-; CHECK-MVE-NEXT: vins.f16 s3, s4
+; CHECK-MVE-NEXT: vbic.i16 q0, #0x8000
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: fabs_float16_t:
@@ -86,10 +71,7 @@ entry:
define arm_aapcs_vfpcc <4 x float> @fabs_float32_t(<4 x float> %src) {
; CHECK-MVE-LABEL: fabs_float32_t:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vabs.f32 s3, s3
-; CHECK-MVE-NEXT: vabs.f32 s2, s2
-; CHECK-MVE-NEXT: vabs.f32 s1, s1
-; CHECK-MVE-NEXT: vabs.f32 s0, s0
+; CHECK-MVE-NEXT: vbic.i32 q0, #0x80000000
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: fabs_float32_t:
@@ -104,21 +86,17 @@ entry:
define arm_aapcs_vfpcc <2 x double> @fabs_float64_t(<2 x double> %src) {
; CHECK-LABEL: fabs_float64_t:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vldr d2, .LCPI5_0
-; CHECK-NEXT: vmov r12, r3, d0
-; CHECK-NEXT: vmov r0, r1, d2
-; CHECK-NEXT: vmov r0, r2, d1
-; CHECK-NEXT: lsrs r1, r1, #31
-; CHECK-NEXT: bfi r2, r1, #31, #1
-; CHECK-NEXT: bfi r3, r1, #31, #1
-; CHECK-NEXT: vmov d1, r0, r2
-; CHECK-NEXT: vmov d0, r12, r3
+; CHECK-NEXT: adr r0, .LCPI5_0
+; CHECK-NEXT: vldrw.u32 q1, [r0]
+; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 3
+; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI5_0:
-; CHECK-NEXT: .long 0 @ double 0
-; CHECK-NEXT: .long 0
+; CHECK-NEXT: .long 4294967295 @ 0xffffffff
+; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
+; CHECK-NEXT: .long 4294967295 @ 0xffffffff
+; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
entry:
%0 = call nnan ninf nsz <2 x double> @llvm.fabs.v2f64(<2 x double> %src)
ret <2 x double> %0
diff --git a/llvm/test/CodeGen/Thumb2/mve-vabd.ll b/llvm/test/CodeGen/Thumb2/mve-vabd.ll
index 3c35a29c0a84c..7b05414373e69 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vabd.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vabd.ll
@@ -14,30 +14,24 @@ define arm_aapcs_vfpcc void @vabd_v4f32(<4 x float> %x, <4 x float> %y, ptr %z)
; CHECK-MVE-NEXT: vmov q4, q1
; CHECK-MVE-NEXT: vmov q5, q0
; CHECK-MVE-NEXT: mov r8, r0
-; CHECK-MVE-NEXT: vmov r0, r6, d10
-; CHECK-MVE-NEXT: vmov r1, r7, d8
+; CHECK-MVE-NEXT: vmov r0, r9, d11
+; CHECK-MVE-NEXT: vmov r1, r6, d9
; CHECK-MVE-NEXT: bl __aeabi_fsub
-; CHECK-MVE-NEXT: mov r9, r0
-; CHECK-MVE-NEXT: mov r0, r6
-; CHECK-MVE-NEXT: mov r1, r7
+; CHECK-MVE-NEXT: mov r7, r0
+; CHECK-MVE-NEXT: vmov r0, r4, d10
+; CHECK-MVE-NEXT: vmov r1, r5, d8
; CHECK-MVE-NEXT: bl __aeabi_fsub
-; CHECK-MVE-NEXT: mov r6, r0
-; CHECK-MVE-NEXT: vmov r0, r7, d11
-; CHECK-MVE-NEXT: vmov r1, r4, d9
+; CHECK-MVE-NEXT: vmov q4[2], q4[0], r0, r7
+; CHECK-MVE-NEXT: mov r0, r9
+; CHECK-MVE-NEXT: mov r1, r6
; CHECK-MVE-NEXT: bl __aeabi_fsub
-; CHECK-MVE-NEXT: mov r5, r0
-; CHECK-MVE-NEXT: mov r0, r7
-; CHECK-MVE-NEXT: mov r1, r4
+; CHECK-MVE-NEXT: mov r6, r0
+; CHECK-MVE-NEXT: mov r0, r4
+; CHECK-MVE-NEXT: mov r1, r5
; CHECK-MVE-NEXT: bl __aeabi_fsub
-; CHECK-MVE-NEXT: bic r0, r0, #-2147483648
-; CHECK-MVE-NEXT: vmov s3, r0
-; CHECK-MVE-NEXT: bic r0, r5, #-2147483648
-; CHECK-MVE-NEXT: vmov s2, r0
-; CHECK-MVE-NEXT: bic r0, r6, #-2147483648
-; CHECK-MVE-NEXT: vmov s1, r0
-; CHECK-MVE-NEXT: bic r0, r9, #-2147483648
-; CHECK-MVE-NEXT: vmov s0, r0
-; CHECK-MVE-NEXT: vstrw.32 q0, [r8]
+; CHECK-MVE-NEXT: vmov q4[3], q4[1], r0, r6
+; CHECK-MVE-NEXT: vbic.i32 q4, #0x80000000
+; CHECK-MVE-NEXT: vstrw.32 q4, [r8]
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: add sp, #4
; CHECK-MVE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
@@ -58,35 +52,32 @@ entry:
define arm_aapcs_vfpcc void @vabd_v8f16(<8 x half> %x, <8 x half> %y, ptr %z) {
; CHECK-MVE-LABEL: vabd_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: .save {r4, r5, r6, lr}
-; CHECK-MVE-NEXT: push {r4, r5, r6, lr}
+; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}
+; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-MVE-NEXT: mov r4, r0
-; CHECK-MVE-NEXT: vmov.u16 r0, q1[1]
+; CHECK-MVE-NEXT: vmov.u16 r0, q1[0]
; CHECK-MVE-NEXT: vmov q5, q1
; CHECK-MVE-NEXT: vmov q4, q0
; CHECK-MVE-NEXT: bl __aeabi_h2f
; CHECK-MVE-NEXT: mov r5, r0
-; CHECK-MVE-NEXT: vmov.u16 r0, q4[1]
+; CHECK-MVE-NEXT: vmov.u16 r0, q4[0]
; CHECK-MVE-NEXT: bl __aeabi_h2f
; CHECK-MVE-NEXT: mov r1, r5
; CHECK-MVE-NEXT: bl __aeabi_fsub
; CHECK-MVE-NEXT: bl __aeabi_f2h
-; CHECK-MVE-NEXT: mov r5, r0
-; CHECK-MVE-NEXT: vmov.u16 r0, q5[0]
+; CHECK-MVE-NEXT: vmov.16 q6[0], r0
+; CHECK-MVE-NEXT: vmov.u16 r0, q5[1]
; CHECK-MVE-NEXT: bl __aeabi_h2f
-; CHECK-MVE-NEXT: mov r6, r0
-; CHECK-MVE-NEXT: vmov.u16 r0, q4[0]
+; CHECK-MVE-NEXT: mov r5, r0
+; CHECK-MVE-NEXT: vmov.u16 r0, q4[1]
; CHECK-MVE-NEXT: bl __aeabi_h2f
-; CHECK-MVE-NEXT: mov r1, r6
+; CHECK-MVE-NEXT: mov r1, r5
; CHECK-MVE-NEXT: bl __aeabi_fsub
; CHECK-MVE-NEXT: bl __aeabi_f2h
-; CHECK-MVE-NEXT: bfc r0, #15, #17
-; CHECK-MVE-NEXT: bfc r5, #15, #17
-; CHECK-MVE-NEXT: vmov.16 q6[0], r0
+; CHECK-MVE-NEXT: vmov.16 q6[1], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q5[2]
-; CHECK-MVE-NEXT: vmov.16 q6[1], r5
; CHECK-MVE-NEXT: bl __aeabi_h2f
; CHECK-MVE-NEXT: mov r5, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q4[2]
@@ -94,7 +85,6 @@ define arm_aapcs_vfpcc void @vabd_v8f16(<8 x half> %x, <8 x half> %y, ptr %z) {
; CHECK-MVE-NEXT: mov r1, r5
; CHECK-MVE-NEXT: bl __aeabi_fsub
; CHECK-MVE-NEXT: bl __aeabi_f2h
-; CHECK-MVE-NEXT: bfc r0, #15, #17
; CHECK-MVE-NEXT: vmov.16 q6[2], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q5[3]
; CHECK-MVE-NEXT: bl __aeabi_h2f
@@ -104,7 +94,6 @@ define arm_aapcs_vfpcc void @vabd_v8f16(<8 x half> %x, <8 x half> %y, ptr %z) {
; CHECK-MVE-NEXT: mov r1, r5
; CHECK-MVE-NEXT: bl __aeabi_fsub
; CHECK-MVE-NEXT: bl __aeabi_f2h
-; CHECK-MVE-NEXT: bfc r0, #15, #17
; CHECK-MVE-NEXT: vmov.16 q6[3], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q5[4]
; CHECK-MVE-NEXT: bl __aeabi_h2f
@@ -114,7 +103,6 @@ define arm_aapcs_vfpcc void @vabd_v8f16(<8 x half> %x, <8 x half> %y, ptr %z) {
; CHECK-MVE-NEXT: mov r1, r5
; CHECK-MVE-NEXT: bl __aeabi_fsub
; CHECK-MVE-NEXT: bl __aeabi_f2h
-; CHECK-MVE-NEXT: bfc r0, #15, #17
; CHECK-MVE-NEXT: vmov.16 q6[4], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q5[5]
; CHECK-MVE-NEXT: bl __aeabi_h2f
@@ -124,7 +112,6 @@ define arm_aapcs_vfpcc void @vabd_v8f16(<8 x half> %x, <8 x half> %y, ptr %z) {
; CHECK-MVE-NEXT: mov r1, r5
; CHECK-MVE-NEXT: bl __aeabi_fsub
; CHECK-MVE-NEXT: bl __aeabi_f2h
-; CHECK-MVE-NEXT: bfc r0, #15, #17
; CHECK-MVE-NEXT: vmov.16 q6[5], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q5[6]
; CHECK-MVE-NEXT: bl __aeabi_h2f
@@ -134,7 +121,6 @@ define arm_aapcs_vfpcc void @vabd_v8f16(<8 x half> %x, <8 x half> %y, ptr %z) {
; CHECK-MVE-NEXT: mov r1, r5
; CHECK-MVE-NEXT: bl __aeabi_fsub
; CHECK-MVE-NEXT: bl __aeabi_f2h
-; CHECK-MVE-NEXT: bfc r0, #15, #17
; CHECK-MVE-NEXT: vmov.16 q6[6], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q5[7]
; CHECK-MVE-NEXT: bl __aeabi_h2f
@@ -144,11 +130,11 @@ define arm_aapcs_vfpcc void @vabd_v8f16(<8 x half> %x, <8 x half> %y, ptr %z) {
; CHECK-MVE-NEXT: mov r1, r5
; CHECK-MVE-NEXT: bl __aeabi_fsub
; CHECK-MVE-NEXT: bl __aeabi_f2h
-; CHECK-MVE-NEXT: bfc r0, #15, #17
; CHECK-MVE-NEXT: vmov.16 q6[7], r0
+; CHECK-MVE-NEXT: vbic.i16 q6, #0x8000
; CHECK-MVE-NEXT: vstrw.32 q6, [r4]
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11, d12, d13}
-; CHECK-MVE-NEXT: pop {r4, r5, r6, pc}
+; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
;
; CHECK-MVEFP-LABEL: vabd_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
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