[llvm] [AMDGPU] fix a scc clobber bug (PR #193143)
Zeng Wu via llvm-commits
llvm-commits at lists.llvm.org
Sat May 9 23:43:19 PDT 2026
https://github.com/zwu-2025 updated https://github.com/llvm/llvm-project/pull/193143
>From 267705050cf1c1eb0fb1f19d27516ab48f49c528 Mon Sep 17 00:00:00 2001
From: zwu-2025 <Zeng.Wu2 at amd.com>
Date: Wed, 29 Apr 2026 16:47:14 +0000
Subject: [PATCH 1/5] [NFC] typo fixes
---
llvm/lib/Target/AMDGPU/SIProgramInfo.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp b/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
index 471e2f7a3857c..99255e4060886 100644
--- a/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
@@ -138,11 +138,11 @@ static uint64_t getPGMRSrc1Reg(const SIProgramInfo &ProgInfo,
static uint64_t getComputePGMRSrc2Reg(const GCNSubtarget &ST,
const SIProgramInfo &ProgInfo) {
- uint64_t MaxNumerUserSGRPs = AMDGPU::getMaxNumUserSGPRs(ST);
+ uint64_t MaxNumUserSGRPs = AMDGPU::getMaxNumUserSGPRs(ST);
uint64_t Reg = 0;
- if (MaxNumerUserSGRPs == 32) {
+ if (MaxNumUserSGRPs == 32) {
Reg = S_00B84C_USER_SGPR_GFX1250(ProgInfo.UserSGPR);
- } else if (MaxNumerUserSGRPs == 16) {
+ } else if (MaxNumUserSGRPs == 16) {
Reg = (S_00B84C_USER_SGPR(ProgInfo.UserSGPR) |
S_00B84C_TRAP_HANDLER(ProgInfo.TrapHandlerEnable));
} else {
>From f25ab224f1bd9d47b80cd35ff6c609865d846f57 Mon Sep 17 00:00:00 2001
From: zwu-2025 <Zeng.Wu2 at amd.com>
Date: Fri, 1 May 2026 00:45:27 +0000
Subject: [PATCH 2/5] fix scc
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 5 +-
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 1 +
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 +
llvm/lib/Target/AMDGPU/CMakeLists.txt | 1 +
.../AMDGPU/SIFixPhysicalRegisterLiveInfo.cpp | 185 ++++++++++++++++++
.../AMDGPU/SIFixPhysicalRegisterLiveInfo.h | 30 +++
llvm/test/CodeGen/AMDGPU/early-term.mir | 8 +-
.../AMDGPU/finalize-isel-kill-scc-vcc.mir | 6 +-
llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir | 122 +++++++-----
llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 2 +
llvm/test/CodeGen/AMDGPU/llc-pipeline.ll | 8 +
...ate-branch-lowering-preserve-loop-info.mir | 3 +-
.../CodeGen/AMDGPU/si-lower-wwm-copies.mir | 4 +-
llvm/test/CodeGen/AMDGPU/skip-if-dead.ll | 10 +-
llvm/test/CodeGen/AMDGPU/wait-xcnt.mir | 40 ++--
15 files changed, 353 insertions(+), 79 deletions(-)
create mode 100644 llvm/lib/Target/AMDGPU/SIFixPhysicalRegisterLiveInfo.cpp
create mode 100644 llvm/lib/Target/AMDGPU/SIFixPhysicalRegisterLiveInfo.h
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 5c7259b7600a9..7ee417a385cb7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -55,7 +55,7 @@ FunctionPass *createSIMemoryLegalizerPass();
FunctionPass *createSIInsertWaitcntsPass();
FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
FunctionPass *createSIFormMemoryClausesLegacyPass();
-
+FunctionPass *createSIFixPhysicalRegisterLiveInfoLegacyPass();
FunctionPass *createSIPostRABundlerPass();
FunctionPass *createAMDGPUImageIntrinsicOptimizerPass(const TargetMachine *);
ModulePass *createAMDGPURemoveIncompatibleFunctionsPass(const TargetMachine *);
@@ -195,6 +195,9 @@ extern char &SIFixSGPRCopiesLegacyID;
void initializeSIFixVGPRCopiesLegacyPass(PassRegistry &);
extern char &SIFixVGPRCopiesID;
+void initializeSIFixPhysicalRegisterLiveInfoLegacyPass(PassRegistry &);
+extern char &SIFixPhysicalRegisterLiveInfoLegacyID;
+
void initializeAMDGPUNextUseAnalysisLegacyPassPass(PassRegistry &);
extern char &AMDGPUNextUseAnalysisLegacyID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 2a6560b309e62..62f795de87b4c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -153,6 +153,7 @@ MACHINE_FUNCTION_PASS("si-pre-allocate-wwm-regs", SIPreAllocateWWMRegsPass())
MACHINE_FUNCTION_PASS("si-pre-emit-peephole", SIPreEmitPeepholePass())
MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
MACHINE_FUNCTION_PASS("si-wqm", SIWholeQuadModePass())
+MACHINE_FUNCTION_PASS("si-fix-physical-register-live-info", SIFixPhysicalRegisterLiveInfoPass())
#undef MACHINE_FUNCTION_PASS
#define DUMMY_MACHINE_FUNCTION_PASS(NAME, CREATE_PASS)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index c892645c32123..19aed2a4016ff 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -49,6 +49,7 @@
#include "GCNVOPDUtils.h"
#include "R600.h"
#include "R600TargetMachine.h"
+#include "SIFixPhysicalRegisterLiveInfo.h"
#include "SIFixSGPRCopies.h"
#include "SIFixVGPRCopies.h"
#include "SIFoldOperands.h"
@@ -678,6 +679,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
initializeSIShrinkInstructionsLegacyPass(*PR);
initializeSIOptimizeExecMaskingPreRALegacyPass(*PR);
initializeSIOptimizeVGPRLiveRangeLegacyPass(*PR);
+ initializeSIFixPhysicalRegisterLiveInfoLegacyPass(*PR);
initializeAMDGPUNextUseAnalysisLegacyPassPass(*PR);
initializeAMDGPUNextUseAnalysisPrinterLegacyPassPass(*PR);
initializeSILoadStoreOptimizerLegacyPass(*PR);
@@ -1614,6 +1616,8 @@ bool GCNPassConfig::addPreISel() {
}
void GCNPassConfig::addMachineSSAOptimization() {
+ addPass(&SIFixPhysicalRegisterLiveInfoLegacyID);
+
TargetPassConfig::addMachineSSAOptimization();
// We want to fold operands after PeepholeOptimizer has run (or as part of
@@ -2419,6 +2423,9 @@ void AMDGPUCodeGenPassBuilder::addPreRewrite(PassManagerWrapper &PMW) const {
void AMDGPUCodeGenPassBuilder::addMachineSSAOptimization(
PassManagerWrapper &PMW) const {
+
+ // Just after finalize-isel
+ addMachineFunctionPass(SIFixPhysicalRegisterLiveInfoPass(), PMW);
Base::addMachineSSAOptimization(PMW);
addMachineFunctionPass(SIFoldOperandsPass(), PMW);
diff --git a/llvm/lib/Target/AMDGPU/CMakeLists.txt b/llvm/lib/Target/AMDGPU/CMakeLists.txt
index ae8f1c0fad5ba..c61b13e05ef4e 100644
--- a/llvm/lib/Target/AMDGPU/CMakeLists.txt
+++ b/llvm/lib/Target/AMDGPU/CMakeLists.txt
@@ -190,6 +190,7 @@ add_llvm_target(AMDGPUCodeGen
SIRegisterInfo.cpp
SIShrinkInstructions.cpp
SIWholeQuadMode.cpp
+ SIFixPhysicalRegisterLiveInfo.cpp
LINK_COMPONENTS
AMDGPUDesc
diff --git a/llvm/lib/Target/AMDGPU/SIFixPhysicalRegisterLiveInfo.cpp b/llvm/lib/Target/AMDGPU/SIFixPhysicalRegisterLiveInfo.cpp
new file mode 100644
index 0000000000000..46b99db4dbc92
--- /dev/null
+++ b/llvm/lib/Target/AMDGPU/SIFixPhysicalRegisterLiveInfo.cpp
@@ -0,0 +1,185 @@
+#include "SIFixPhysicalRegisterLiveInfo.h"
+#include "AMDGPU.h"
+#include "GCNSubtarget.h"
+#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/InitializePasses.h"
+#include "llvm/Target/TargetMachine.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "si-fix-physical-register-live-info"
+
+namespace {
+
+struct SIFixPhysicalRegisterLiveInfo {
+ MachineDominatorTree *MDT;
+ SIFixPhysicalRegisterLiveInfo(MachineDominatorTree *MDT) : MDT(MDT) {}
+ void getAnalysisUsage(AnalysisUsage &AU) const;
+ const MachineInstr *definedInBlock(const SIRegisterInfo *TRI,
+ MachineBasicBlock *MBB, Register Reg);
+
+ bool run(MachineFunction &MF);
+};
+
+struct SIFixPhysicalRegisterLiveInfoLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+
+ SIFixPhysicalRegisterLiveInfoLegacy() : MachineFunctionPass(ID) {}
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+
+ StringRef getPassName() const override {
+ return "SI Fix Physical Register Live Info";
+ }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.addRequired<MachineDominatorTreeWrapperPass>();
+ AU.addPreserved<MachineDominatorTreeWrapperPass>();
+ AU.setPreservesCFG();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+
+ MachineFunctionProperties getRequiredProperties() const override {
+ return MachineFunctionProperties().setIsSSA();
+ }
+};
+
+} // end of anonymous namespace
+
+INITIALIZE_PASS_BEGIN(SIFixPhysicalRegisterLiveInfoLegacy, DEBUG_TYPE,
+ "SI Fix Physical Register Live Info", false, false)
+INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
+INITIALIZE_PASS_END(SIFixPhysicalRegisterLiveInfoLegacy, DEBUG_TYPE,
+ "SI Fix Physical Register Live Info", false, false)
+
+char SIFixPhysicalRegisterLiveInfoLegacy::ID = 0;
+
+char &llvm::SIFixPhysicalRegisterLiveInfoLegacyID =
+ SIFixPhysicalRegisterLiveInfoLegacy::ID;
+
+FunctionPass *llvm::createSIFixPhysicalRegisterLiveInfoLegacyPass() {
+ return new SIFixPhysicalRegisterLiveInfoLegacy();
+}
+
+bool SIFixPhysicalRegisterLiveInfoLegacy::runOnMachineFunction(
+ MachineFunction &MF) {
+ if (skipFunction(MF.getFunction()))
+ return false;
+
+ MachineDominatorTree &MDT =
+ getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+ SIFixPhysicalRegisterLiveInfo Impl(&MDT);
+ return Impl.run(MF);
+}
+
+PreservedAnalyses
+SIFixPhysicalRegisterLiveInfoPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ MachineDominatorTree &MDT = MFAM.getResult<MachineDominatorTreeAnalysis>(MF);
+ SIFixPhysicalRegisterLiveInfo Impl(&MDT);
+ bool Changed = Impl.run(MF);
+ if (!Changed)
+ return PreservedAnalyses::all();
+
+ auto PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ return PA;
+}
+
+bool SIFixPhysicalRegisterLiveInfo::run(MachineFunction &MF) {
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+ if (!MRI.isSSA())
+ return false;
+
+ bool Changed = false;
+
+ const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
+ const SIRegisterInfo *TRI = ST.getRegisterInfo();
+ const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
+
+ // Check SCC for now.
+ for (Register Reg : {AMDGPU::SCC}) {
+ for (MachineBasicBlock &MBB : MF) {
+ if (!MBB.isLiveIn(Reg))
+ continue;
+
+ MachineBasicBlock *UseBB = &MBB;
+ MachineBasicBlock *DefBB = nullptr;
+ const MachineInstr *DefMI = nullptr;
+ // The PHI node is not considered here. Theoritically, if the physical
+ // register is live out of a block, the InstrEmitter in the DAG Isel will
+ // copy it out.
+ MachineDomTreeNode *Node = MDT->getNode(&MBB)->getIDom();
+ while (Node != nullptr) {
+ DefBB = Node->getBlock();
+ DefMI = definedInBlock(TRI, DefBB, Reg);
+ if (DefMI != nullptr)
+ break;
+
+ Node = Node->getIDom();
+ }
+
+ Register NewCopy =
+ MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0_XEXECRegClass);
+ if (DefMI == nullptr) {
+ // kernel arguments
+ MachineBasicBlock &EntryBB = MF.front();
+ assert(EntryBB.isLiveIn(Reg));
+ DebugLoc DL = DefMI->getDebugLoc();
+
+ BuildMI(EntryBB, EntryBB.getFirstTerminator(), DebugLoc(),
+ TII->get(TargetOpcode::COPY), NewCopy)
+ .addReg(Reg);
+
+ } else {
+ DebugLoc DL = DefMI->getDebugLoc();
+ // Insert a COPY just SCC instruction which defines it.
+ BuildMI(*DefBB,
+ std::next(const_cast<MachineInstr *>(DefMI)->getIterator()), DL,
+ TII->get(TargetOpcode::COPY), NewCopy)
+ .addReg(Reg);
+ }
+
+ // Copy back to $scc in the SplitBB
+ MachineBasicBlock::iterator InsertPt = UseBB->getFirstNonPHI();
+ BuildMI(*UseBB, InsertPt, InsertPt->getDebugLoc(),
+ TII->get(TargetOpcode::COPY), Reg)
+ .addReg(NewCopy, RegState::Kill);
+
+ // Now remove the scc from the livein of UseBB
+ UseBB->removeLiveIn(Reg);
+ }
+ }
+
+ return Changed;
+}
+
+// Returns the iterator where the Physical Reg is defined, so that an COPY out
+// will be inserted just after the definition point. Or else, the value could be
+// clobbered by the following instructions.
+const MachineInstr *SIFixPhysicalRegisterLiveInfo::definedInBlock(
+ const SIRegisterInfo *TRI, MachineBasicBlock *MBB, Register Reg) {
+ for (MachineBasicBlock::reverse_iterator I = MBB->rbegin(), E = MBB->rend();
+ I != E; ++I) {
+ if (I->isDebugInstr())
+ continue;
+
+ if (I->isCall()) {
+ // $scc is caller saved register, so if it is clobbered, we ingore it
+ // since the value of $scc is not a useful one.
+ continue;
+ }
+
+ if (I->definesRegister(Reg, TRI))
+ return &*I;
+ }
+
+ return nullptr;
+}
diff --git a/llvm/lib/Target/AMDGPU/SIFixPhysicalRegisterLiveInfo.h b/llvm/lib/Target/AMDGPU/SIFixPhysicalRegisterLiveInfo.h
new file mode 100644
index 0000000000000..85bd9b5050f9c
--- /dev/null
+++ b/llvm/lib/Target/AMDGPU/SIFixPhysicalRegisterLiveInfo.h
@@ -0,0 +1,30 @@
+//=======--- SIFixPhysicalRegisterLiveInfo.h - fix physical registers live info
+//---==========//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AMDGPU_SIFIXPHYSICALREGISTERLIVEINFO_H
+#define LLVM_LIB_TARGET_AMDGPU_SIFIXPHYSICALREGISTERLIVEINFO_H
+
+#include "AMDGPU.h"
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+class SIFixPhysicalRegisterLiveInfoPass
+ : public PassInfoMixin<SIFixPhysicalRegisterLiveInfoPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MAM);
+
+ MachineFunctionProperties getRequiredProperties() const {
+ return MachineFunctionProperties().setIsSSA();
+ }
+};
+
+} // end namespace llvm
+
+#endif // LLVM_LIB_TARGET_AMDGPU_GCNDPPCOMBINE_H
diff --git a/llvm/test/CodeGen/AMDGPU/early-term.mir b/llvm/test/CodeGen/AMDGPU/early-term.mir
index 2c43a15a109a7..c3279e07f8db7 100644
--- a/llvm/test/CodeGen/AMDGPU/early-term.mir
+++ b/llvm/test/CodeGen/AMDGPU/early-term.mir
@@ -1,8 +1,8 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-late-branch-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX9 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 -run-pass=si-late-branch-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX10 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -run-pass=si-late-branch-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX11 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=phi-node-elimination,si-late-branch-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX9 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 -run-pass=phi-node-elimination,si-late-branch-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX10 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -run-pass=phi-node-elimination,si-late-branch-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX11 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -passes=si-late-branch-lowering %s -o - | FileCheck -check-prefixes=GCN,GFX11 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -passes=phi-node-elimination,si-late-branch-lowering %s -o - | FileCheck -check-prefixes=GCN,GFX11 %s
--- |
define amdgpu_ps void @early_term_scc0_end_block() {
diff --git a/llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir b/llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir
index c33ed34e8cb40..70d25ed053b4d 100644
--- a/llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir
+++ b/llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn -run-pass finalize-isel -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -run-pass=finalize-isel,si-fix-physical-register-live-info -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs %s -o - | FileCheck %s
---
name: phi_use_def_before_kill
tracksRegLiveness: true
@@ -21,12 +21,14 @@ body: |
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; CHECK-NEXT: S_CMP_LG_U32 [[COPY]], killed [[S_MOV_B32_3]], implicit-def $scc
+ ; CHECK-NEXT: [[SCCCOPY:%[0-9]+]]:sreg_32_xm0_xexec = COPY $scc
; CHECK-NEXT: SI_KILL_F32_COND_IMM_TERMINATOR [[V_ADD_F32_e64_]], 0, 2, implicit-def $vcc_lo, implicit $exec
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK-NEXT: liveins: $vcc_lo, $scc
+ ; CHECK-NEXT: liveins: $vcc_lo
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: scc = COPY killed [[SCCCOPY]]
; CHECK-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo
; CHECK-NEXT: S_BRANCH %bb.2
diff --git a/llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir b/llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
index 7e81b78ac378c..2c6bc24d04df1 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
@@ -11,7 +11,7 @@ body: |
; GFX908-LABEL: name: test_sgpr_init_multiuse
; GFX908: bb.0:
; GFX908-NEXT: successors: %bb.1(0x80000000)
- ; GFX908-NEXT: liveins: $sgpr0, $scc
+ ; GFX908-NEXT: liveins: $sgpr0
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr0
; GFX908-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
@@ -22,7 +22,6 @@ body: |
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.1:
; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX908-NEXT: liveins: $scc
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[V_ACCVGPR_WRITE_B32_e64_3]], %bb.0, %13.sub0, %bb.1
; GFX908-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[V_ACCVGPR_WRITE_B32_e64_2]], %bb.0, %13.sub1, %bb.1
@@ -32,6 +31,7 @@ body: |
; GFX908-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
; GFX908-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
; GFX908-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
+ ; GFX908-NEXT: $scc = IMPLICIT_DEF
; GFX908-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY2]], %subreg.sub3
; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX908-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -44,7 +44,7 @@ body: |
; GFX90A-LABEL: name: test_sgpr_init_multiuse
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.1(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr0, $scc
+ ; GFX90A-NEXT: liveins: $sgpr0
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr0
; GFX90A-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
@@ -55,7 +55,6 @@ body: |
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.1:
; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX90A-NEXT: liveins: $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY5]], %bb.0, %13.sub0, %bb.1
; GFX90A-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %13.sub1, %bb.1
@@ -65,6 +64,7 @@ body: |
; GFX90A-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
; GFX90A-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
; GFX90A-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
+ ; GFX90A-NEXT: $scc = IMPLICIT_DEF
; GFX90A-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY8]], %subreg.sub1, [[COPY7]], %subreg.sub2, [[COPY6]], %subreg.sub3
; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX90A-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -74,20 +74,21 @@ body: |
; GFX90A-NEXT: bb.2:
; GFX90A-NEXT: S_ENDPGM 0
bb.0:
- liveins: $sgpr0, $scc
+ liveins: $sgpr0
successors: %bb.1
%0:sgpr_32 = COPY $sgpr0
%1:vgpr_32 = COPY %0
bb.1:
- liveins: $scc
successors: %bb.1, %bb.2
-
%8:vgpr_32 = PHI %1, %bb.0, %16, %bb.1
%9:vgpr_32 = PHI %1, %bb.0, %17, %bb.1
%10:vgpr_32 = PHI %1, %bb.0, %18, %bb.1
%11:vgpr_32 = PHI %1, %bb.0, %19, %bb.1
+
+ $scc = IMPLICIT_DEF
+
%12:areg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1, %10, %subreg.sub2, %11, %subreg.sub3
%13:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
%14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -110,7 +111,7 @@ body: |
; GFX908-LABEL: name: test_sgpr_init_multiuse_agprtuple
; GFX908: bb.0:
; GFX908-NEXT: successors: %bb.1(0x80000000)
- ; GFX908-NEXT: liveins: $sgpr0_sgpr1, $scc
+ ; GFX908-NEXT: liveins: $sgpr0_sgpr1
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1
; GFX908-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]]
@@ -119,12 +120,12 @@ body: |
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.1:
; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX908-NEXT: liveins: $scc
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[PHI:%[0-9]+]]:areg_64_align2 = PHI [[COPY3]], %bb.0, %9.sub0_sub1, %bb.1
; GFX908-NEXT: [[PHI1:%[0-9]+]]:areg_64_align2 = PHI [[COPY2]], %bb.0, %9.sub2_sub3, %bb.1
; GFX908-NEXT: [[COPY4:%[0-9]+]]:vreg_64_align2 = COPY [[PHI1]]
; GFX908-NEXT: [[COPY5:%[0-9]+]]:vreg_64_align2 = COPY [[PHI]]
+ ; GFX908-NEXT: $scc = IMPLICIT_DEF
; GFX908-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY5]].sub0, %subreg.sub0, [[COPY5]].sub1, %subreg.sub1, [[COPY4]].sub0, %subreg.sub2, [[COPY4]].sub1, %subreg.sub3
; GFX908-NEXT: [[V_MOV_B64_e32_:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_e32 1073741824, implicit $exec
; GFX908-NEXT: [[V_MOV_B64_e32_1:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_e32 1065353216, implicit $exec
@@ -137,7 +138,7 @@ body: |
; GFX90A-LABEL: name: test_sgpr_init_multiuse_agprtuple
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.1(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr0_sgpr1, $scc
+ ; GFX90A-NEXT: liveins: $sgpr0_sgpr1
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1
; GFX90A-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]]
@@ -146,12 +147,12 @@ body: |
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.1:
; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX90A-NEXT: liveins: $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[PHI:%[0-9]+]]:areg_64_align2 = PHI [[COPY3]], %bb.0, %9.sub0_sub1, %bb.1
; GFX90A-NEXT: [[PHI1:%[0-9]+]]:areg_64_align2 = PHI [[COPY2]], %bb.0, %9.sub2_sub3, %bb.1
; GFX90A-NEXT: [[COPY4:%[0-9]+]]:vreg_64_align2 = COPY [[PHI1]]
; GFX90A-NEXT: [[COPY5:%[0-9]+]]:vreg_64_align2 = COPY [[PHI]]
+ ; GFX90A-NEXT: $scc = IMPLICIT_DEF
; GFX90A-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY5]].sub0, %subreg.sub0, [[COPY5]].sub1, %subreg.sub1, [[COPY4]].sub0, %subreg.sub2, [[COPY4]].sub1, %subreg.sub3
; GFX90A-NEXT: [[V_MOV_B64_e32_:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_e32 1073741824, implicit $exec
; GFX90A-NEXT: [[V_MOV_B64_e32_1:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_e32 1065353216, implicit $exec
@@ -162,17 +163,19 @@ body: |
; GFX90A-NEXT: S_ENDPGM 0
bb.0:
successors: %bb.1
- liveins: $sgpr0_sgpr1, $scc
+ liveins: $sgpr0_sgpr1
%0:sgpr_64 = COPY $sgpr0_sgpr1
%1:vreg_64_align2 = COPY %0:sgpr_64
bb.1:
successors: %bb.1, %bb.2
- liveins: $scc
%2:vreg_64_align2 = PHI %1, %bb.0, %3, %bb.1
%4:vreg_64_align2 = PHI %1, %bb.0, %5, %bb.1
+
+ $scc = IMPLICIT_DEF
+
%6:areg_128_align2 = REG_SEQUENCE %2.sub0, %subreg.sub0, %2.sub1, %subreg.sub1, %4.sub0, %subreg.sub2, %4.sub1, %subreg.sub3
%7:vreg_64_align2 = V_MOV_B64_e32 1073741824, implicit $exec
%8:vreg_64_align2 = V_MOV_B64_e32 1065353216, implicit $exec
@@ -194,7 +197,7 @@ body: |
; GFX908-LABEL: name: test_sgpr_init_singleuse
; GFX908: bb.0:
; GFX908-NEXT: successors: %bb.1(0x80000000)
- ; GFX908-NEXT: liveins: $sgpr0, $scc
+ ; GFX908-NEXT: liveins: $sgpr0
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr0
; GFX908-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
@@ -208,7 +211,6 @@ body: |
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.1:
; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX908-NEXT: liveins: $scc
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY2]], %bb.0, %16.sub0, %bb.1
; GFX908-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %16.sub1, %bb.1
@@ -218,6 +220,7 @@ body: |
; GFX908-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
; GFX908-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
; GFX908-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
+ ; GFX908-NEXT: $scc = IMPLICIT_DEF
; GFX908-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY12]], %subreg.sub0, [[COPY11]], %subreg.sub1, [[COPY10]], %subreg.sub2, [[COPY9]], %subreg.sub3
; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX908-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -230,7 +233,7 @@ body: |
; GFX90A-LABEL: name: test_sgpr_init_singleuse
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.1(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr0, $scc
+ ; GFX90A-NEXT: liveins: $sgpr0
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr0
; GFX90A-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
@@ -244,7 +247,6 @@ body: |
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.1:
; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX90A-NEXT: liveins: $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY2]], %bb.0, %16.sub0, %bb.1
; GFX90A-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %16.sub1, %bb.1
@@ -254,6 +256,7 @@ body: |
; GFX90A-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
; GFX90A-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
; GFX90A-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
+ ; GFX90A-NEXT: $scc = IMPLICIT_DEF
; GFX90A-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY12]], %subreg.sub0, [[COPY11]], %subreg.sub1, [[COPY10]], %subreg.sub2, [[COPY9]], %subreg.sub3
; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX90A-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -263,7 +266,7 @@ body: |
; GFX90A-NEXT: bb.2:
; GFX90A-NEXT: S_ENDPGM 0
bb.0:
- liveins: $sgpr0, $scc
+ liveins: $sgpr0
successors: %bb.1
%0:sgpr_32 = COPY $sgpr0
@@ -273,13 +276,15 @@ body: |
%4:vgpr_32 = COPY %0
bb.1:
- liveins: $scc
successors: %bb.1, %bb.2
%8:vgpr_32 = PHI %1, %bb.0, %16, %bb.1
%9:vgpr_32 = PHI %2, %bb.0, %17, %bb.1
%10:vgpr_32 = PHI %3, %bb.0, %18, %bb.1
%11:vgpr_32 = PHI %4, %bb.0, %19, %bb.1
+
+ $scc = IMPLICIT_DEF
+
%12:areg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1, %10, %subreg.sub2, %11, %subreg.sub3
%13:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
%14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -302,7 +307,7 @@ body: |
; GFX908-LABEL: name: test_vgpr_init
; GFX908: bb.0:
; GFX908-NEXT: successors: %bb.1(0x80000000)
- ; GFX908-NEXT: liveins: $vgpr0, $scc
+ ; GFX908-NEXT: liveins: $vgpr0
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX908-NEXT: [[COPY1:%[0-9]+]]:agpr_32 = COPY [[COPY]]
@@ -312,7 +317,6 @@ body: |
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.1:
; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX908-NEXT: liveins: $scc
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %12.sub0, %bb.1
; GFX908-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY3]], %bb.0, %12.sub1, %bb.1
@@ -322,6 +326,7 @@ body: |
; GFX908-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
; GFX908-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
; GFX908-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
+ ; GFX908-NEXT: $scc = IMPLICIT_DEF
; GFX908-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY7]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY5]], %subreg.sub3
; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX908-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -334,7 +339,7 @@ body: |
; GFX90A-LABEL: name: test_vgpr_init
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.1(0x80000000)
- ; GFX90A-NEXT: liveins: $vgpr0, $scc
+ ; GFX90A-NEXT: liveins: $vgpr0
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX90A-NEXT: [[COPY1:%[0-9]+]]:agpr_32 = COPY [[COPY]]
@@ -344,7 +349,6 @@ body: |
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.1:
; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX90A-NEXT: liveins: $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %12.sub0, %bb.1
; GFX90A-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY3]], %bb.0, %12.sub1, %bb.1
@@ -354,6 +358,7 @@ body: |
; GFX90A-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
; GFX90A-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
; GFX90A-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
+ ; GFX90A-NEXT: $scc = IMPLICIT_DEF
; GFX90A-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY7]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY5]], %subreg.sub3
; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX90A-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -363,19 +368,21 @@ body: |
; GFX90A-NEXT: bb.2:
; GFX90A-NEXT: S_ENDPGM 0
bb.0:
- liveins: $vgpr0, $scc
+ liveins: $vgpr0
successors: %bb.1
%0:vgpr_32 = COPY $vgpr0
bb.1:
- liveins: $scc
successors: %bb.1, %bb.2
%8:vgpr_32 = PHI %0, %bb.0, %16, %bb.1
%9:vgpr_32 = PHI %0, %bb.0, %17, %bb.1
%10:vgpr_32 = PHI %0, %bb.0, %18, %bb.1
%11:vgpr_32 = PHI %0, %bb.0, %19, %bb.1
+
+ $scc = IMPLICIT_DEF
+
%12:areg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1, %10, %subreg.sub2, %11, %subreg.sub3
%13:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
%14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -398,7 +405,7 @@ body: |
; GFX908-LABEL: name: test_use_vgpr_temp
; GFX908: bb.0:
; GFX908-NEXT: successors: %bb.1(0x80000000)
- ; GFX908-NEXT: liveins: $sgpr0, $scc
+ ; GFX908-NEXT: liveins: $sgpr0
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $sgpr0
; GFX908-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
@@ -412,7 +419,6 @@ body: |
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.1:
; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX908-NEXT: liveins: $scc
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY1]], %bb.0, %18.sub0, %bb.1
; GFX908-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY1]], %bb.0, %18.sub1, %bb.1
@@ -422,6 +428,7 @@ body: |
; GFX908-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
; GFX908-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
; GFX908-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
+ ; GFX908-NEXT: $scc = IMPLICIT_DEF
; GFX908-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY3]], %subreg.sub3
; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX908-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -434,7 +441,7 @@ body: |
; GFX90A-LABEL: name: test_use_vgpr_temp
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.1(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr0, $scc
+ ; GFX90A-NEXT: liveins: $sgpr0
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $sgpr0
; GFX90A-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
@@ -446,7 +453,6 @@ body: |
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.1:
; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX90A-NEXT: liveins: $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[REG_SEQUENCE]].sub0, %bb.0, %18.sub0, %bb.1
; GFX90A-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[REG_SEQUENCE]].sub0, %bb.0, %18.sub1, %bb.1
@@ -456,6 +462,7 @@ body: |
; GFX90A-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
; GFX90A-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
; GFX90A-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
+ ; GFX90A-NEXT: $scc = IMPLICIT_DEF
; GFX90A-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY2]], %subreg.sub3
; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX90A-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -465,7 +472,7 @@ body: |
; GFX90A-NEXT: bb.2:
; GFX90A-NEXT: S_ENDPGM 0
bb.0:
- liveins: $sgpr0, $scc
+ liveins: $sgpr0
successors: %bb.1
%1:vgpr_32 = COPY $sgpr0
@@ -476,13 +483,15 @@ body: |
%6:areg_128_align2 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1, %4, %subreg.sub2, %5, %subreg.sub3
%7:vgpr_32 = COPY %6.sub0
bb.1:
- liveins: $scc
successors: %bb.1, %bb.2
%8:vgpr_32 = PHI %7, %bb.0, %16, %bb.1
%9:vgpr_32 = PHI %7, %bb.0, %17, %bb.1
%10:vgpr_32 = PHI %7, %bb.0, %18, %bb.1
%11:vgpr_32 = PHI %7, %bb.0, %19, %bb.1
+
+ $scc = IMPLICIT_DEF
+
%12:areg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1, %10, %subreg.sub2, %11, %subreg.sub3
%13:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
%14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -504,7 +513,7 @@ body: |
; GFX908-LABEL: name: test_vgpr_init_two_copies
; GFX908: bb.0:
; GFX908-NEXT: successors: %bb.1(0x80000000)
- ; GFX908-NEXT: liveins: $vgpr0, $scc
+ ; GFX908-NEXT: liveins: $vgpr0
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX908-NEXT: [[COPY1:%[0-9]+]]:agpr_32 = COPY [[COPY]]
@@ -514,7 +523,6 @@ body: |
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.1:
; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX908-NEXT: liveins: $scc
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %12.sub0, %bb.1
; GFX908-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY3]], %bb.0, %12.sub1, %bb.1
@@ -524,6 +532,7 @@ body: |
; GFX908-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
; GFX908-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
; GFX908-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
+ ; GFX908-NEXT: $scc = IMPLICIT_DEF
; GFX908-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY7]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY5]], %subreg.sub3
; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX908-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -536,7 +545,7 @@ body: |
; GFX90A-LABEL: name: test_vgpr_init_two_copies
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.1(0x80000000)
- ; GFX90A-NEXT: liveins: $vgpr0, $scc
+ ; GFX90A-NEXT: liveins: $vgpr0
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX90A-NEXT: [[COPY1:%[0-9]+]]:agpr_32 = COPY [[COPY]]
@@ -546,7 +555,6 @@ body: |
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.1:
; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX90A-NEXT: liveins: $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %12.sub0, %bb.1
; GFX90A-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY3]], %bb.0, %12.sub1, %bb.1
@@ -556,6 +564,7 @@ body: |
; GFX90A-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
; GFX90A-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
; GFX90A-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
+ ; GFX90A-NEXT: $scc = IMPLICIT_DEF
; GFX90A-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY7]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY5]], %subreg.sub3
; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX90A-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -565,19 +574,22 @@ body: |
; GFX90A-NEXT: bb.2:
; GFX90A-NEXT: S_ENDPGM 0
bb.0:
- liveins: $vgpr0, $scc
+ liveins: $vgpr0
+
successors: %bb.1
%0:vgpr_32 = COPY $vgpr0
bb.1:
- liveins: $scc
successors: %bb.1, %bb.2
%8:vgpr_32 = PHI %0, %bb.0, %17, %bb.1
%9:vgpr_32 = PHI %0, %bb.0, %18, %bb.1
%10:vgpr_32 = PHI %0, %bb.0, %19, %bb.1
%11:vgpr_32 = PHI %0, %bb.0, %20, %bb.1
+
+ $scc = IMPLICIT_DEF
+
%12:areg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1, %10, %subreg.sub2, %11, %subreg.sub3
%13:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
%14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -601,14 +613,13 @@ body: |
; GFX908-LABEL: name: test_vgpr_init_skip_phis_insertpt
; GFX908: bb.0:
; GFX908-NEXT: successors: %bb.1(0x80000000)
- ; GFX908-NEXT: liveins: $vgpr0, $vgpr1, $scc
+ ; GFX908-NEXT: liveins: $vgpr0, $vgpr1
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX908-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.1:
; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX908-NEXT: liveins: $scc
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
; GFX908-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
@@ -616,11 +627,11 @@ body: |
; GFX908-NEXT: [[COPY3:%[0-9]+]]:agpr_32 = COPY [[PHI]]
; GFX908-NEXT: [[COPY4:%[0-9]+]]:agpr_32 = COPY [[PHI]]
; GFX908-NEXT: [[COPY5:%[0-9]+]]:agpr_32 = COPY [[PHI]]
+ ; GFX908-NEXT: $scc = IMPLICIT_DEF
; GFX908-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.2:
; GFX908-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
- ; GFX908-NEXT: liveins: $scc
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[PHI2:%[0-9]+]]:agpr_32 = PHI [[COPY5]], %bb.1, %15.sub0, %bb.2
; GFX908-NEXT: [[PHI3:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.1, %15.sub1, %bb.2
@@ -630,6 +641,7 @@ body: |
; GFX908-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[PHI4]]
; GFX908-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[PHI3]]
; GFX908-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
+ ; GFX908-NEXT: $scc = IMPLICIT_DEF
; GFX908-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY8]], %subreg.sub1, [[COPY7]], %subreg.sub2, [[COPY6]], %subreg.sub3
; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX908-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -642,14 +654,13 @@ body: |
; GFX90A-LABEL: name: test_vgpr_init_skip_phis_insertpt
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.1(0x80000000)
- ; GFX90A-NEXT: liveins: $vgpr0, $vgpr1, $scc
+ ; GFX90A-NEXT: liveins: $vgpr0, $vgpr1
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX90A-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.1:
; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX90A-NEXT: liveins: $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
; GFX90A-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
@@ -657,11 +668,11 @@ body: |
; GFX90A-NEXT: [[COPY3:%[0-9]+]]:agpr_32 = COPY [[PHI]]
; GFX90A-NEXT: [[COPY4:%[0-9]+]]:agpr_32 = COPY [[PHI]]
; GFX90A-NEXT: [[COPY5:%[0-9]+]]:agpr_32 = COPY [[PHI]]
+ ; GFX90A-NEXT: $scc = IMPLICIT_DEF
; GFX90A-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.2:
; GFX90A-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
- ; GFX90A-NEXT: liveins: $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[PHI2:%[0-9]+]]:agpr_32 = PHI [[COPY5]], %bb.1, %15.sub0, %bb.2
; GFX90A-NEXT: [[PHI3:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.1, %15.sub1, %bb.2
@@ -671,6 +682,7 @@ body: |
; GFX90A-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[PHI4]]
; GFX90A-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[PHI3]]
; GFX90A-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
+ ; GFX90A-NEXT: $scc = IMPLICIT_DEF
; GFX90A-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY8]], %subreg.sub1, [[COPY7]], %subreg.sub2, [[COPY6]], %subreg.sub3
; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX90A-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -680,27 +692,28 @@ body: |
; GFX90A-NEXT: bb.3:
; GFX90A-NEXT: S_ENDPGM 0
bb.0:
- liveins: $vgpr0, $vgpr1, $scc
+ liveins: $vgpr0, $vgpr1
successors: %bb.1
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr0
bb.1:
- liveins: $scc
successors: %bb.1, %bb.2
%6:vgpr_32 = PHI %0, %bb.0, %1, %bb.1
%7:vgpr_32 = PHI %0, %bb.0, %1, %bb.1
+ $scc = IMPLICIT_DEF
S_CBRANCH_SCC1 %bb.1, implicit $scc
bb.2:
- liveins: $scc
successors: %bb.2, %bb.3
%8:vgpr_32 = PHI %6, %bb.1, %16, %bb.2
%9:vgpr_32 = PHI %6, %bb.1, %17, %bb.2
%10:vgpr_32 = PHI %6, %bb.1, %18, %bb.2
%11:vgpr_32 = PHI %6, %bb.1, %19, %bb.2
+
+ $scc = IMPLICIT_DEF
%12:areg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1, %10, %subreg.sub2, %11, %subreg.sub3
%13:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
%14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -722,8 +735,8 @@ body: |
; GFX908-LABEL: name: skip_optimize_agpr_phi_without_subreg_use
; GFX908: bb.0:
; GFX908-NEXT: successors: %bb.1(0x80000000)
- ; GFX908-NEXT: liveins: $scc
; GFX908-NEXT: {{ $}}
+ ; GFX908-NEXT: $scc = IMPLICIT_DEF
; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GFX908-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
; GFX908-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
@@ -734,9 +747,9 @@ body: |
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.1:
; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX908-NEXT: liveins: $scc
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[PHI:%[0-9]+]]:areg_128_align2 = PHI [[REG_SEQUENCE]], %bb.0, %7, %bb.1
+ ; GFX908-NEXT: $scc = IMPLICIT_DEF
; GFX908-NEXT: [[V_MFMA_F32_16X16X4F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X4F32_e64 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], [[PHI]], 0, 0, 0, implicit $mode, implicit $exec
; GFX908-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = COPY [[V_MFMA_F32_16X16X4F32_e64_]], implicit $exec
; GFX908-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
@@ -747,8 +760,8 @@ body: |
; GFX90A-LABEL: name: skip_optimize_agpr_phi_without_subreg_use
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.1(0x80000000)
- ; GFX90A-NEXT: liveins: $scc
; GFX90A-NEXT: {{ $}}
+ ; GFX90A-NEXT: $scc = IMPLICIT_DEF
; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GFX90A-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
; GFX90A-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
@@ -759,9 +772,9 @@ body: |
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.1:
; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX90A-NEXT: liveins: $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[PHI:%[0-9]+]]:areg_128_align2 = PHI [[REG_SEQUENCE]], %bb.0, %7, %bb.1
+ ; GFX90A-NEXT: $scc = IMPLICIT_DEF
; GFX90A-NEXT: [[V_MFMA_F32_16X16X4F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X4F32_e64 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], [[PHI]], 0, 0, 0, implicit $mode, implicit $exec
; GFX90A-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = COPY [[V_MFMA_F32_16X16X4F32_e64_]], implicit $exec
; GFX90A-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
@@ -769,9 +782,9 @@ body: |
; GFX90A-NEXT: bb.2:
; GFX90A-NEXT: S_ENDPGM 0
bb.0:
- liveins: $scc
successors: %bb.1
+ $scc = IMPLICIT_DEF
%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%1:sgpr_32 = S_MOV_B32 0
%2:sgpr_128 = REG_SEQUENCE %1, %subreg.sub0, %1, %subreg.sub1, %1, %subreg.sub2, %1, %subreg.sub3
@@ -780,10 +793,10 @@ body: |
%5:areg_128_align2 = COPY %3, implicit $exec
bb.1:
- liveins: $scc
successors: %bb.1, %bb.2
%9:areg_128_align2 = PHI %5, %bb.0, %10, %bb.1
+ $scc = IMPLICIT_DEF
%11:areg_128_align2 = V_MFMA_F32_16X16X4F32_e64 %0:vgpr_32, %0:vgpr_32, %9:areg_128_align2, 0, 0, 0, implicit $mode, implicit $exec
%12:vgpr_32 = COPY %11.sub3
%13:vgpr_32 = COPY %11.sub2
@@ -805,9 +818,9 @@ name: phi_output_reg_type_is_vgpr
tracksRegLiveness: true
body: |
bb.0:
- liveins: $scc
successors: %bb.1
+ $scc = IMPLICIT_DEF
%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%1:sgpr_32 = S_MOV_B32 0
%2:sgpr_128 = REG_SEQUENCE %1, %subreg.sub0, %1, %subreg.sub1, %1, %subreg.sub2, %1, %subreg.sub3
@@ -816,10 +829,11 @@ body: |
%5:areg_128_align2 = COPY %3, implicit $exec
bb.1:
- liveins: $scc
successors: %bb.1, %bb.2
%9:areg_128_align2 = PHI %5, %bb.0, %10, %bb.1
+ $scc = IMPLICIT_DEF
+
%11:areg_128_align2 = V_MFMA_F32_16X16X4F32_e64 %0:vgpr_32, %0:vgpr_32, %9:areg_128_align2, 0, 0, 0, implicit $mode, implicit $exec
%12:vgpr_32 = COPY %11.sub3
%13:vgpr_32 = COPY %11.sub2
diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
index c49b2b927bd31..16418c0d089a0 100644
--- a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
@@ -165,6 +165,7 @@
; GCN-O2-NEXT: si-fix-sgpr-copies
; GCN-O2-NEXT: si-i1-copies
; GCN-O2-NEXT: finalize-isel
+; GCN-O2-NEXT: si-fix-physical-register-live-info
; GCN-O2-NEXT: early-tailduplication
; GCN-O2-NEXT: opt-phis
; GCN-O2-NEXT: stack-coloring
@@ -334,6 +335,7 @@
; GCN-O3-NEXT: si-fix-sgpr-copies
; GCN-O3-NEXT: si-i1-copies
; GCN-O3-NEXT: finalize-isel
+; GCN-O3-NEXT: si-fix-physical-register-live-info
; GCN-O3-NEXT: early-tailduplication
; GCN-O3-NEXT: opt-phis
; GCN-O3-NEXT: stack-coloring
diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
index 070c873798647..05cf42a3edadd 100644
--- a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
+++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
@@ -318,6 +318,8 @@
; GCN-O1-NEXT: MachinePostDominator Tree Construction
; GCN-O1-NEXT: SI Lower i1 Copies
; GCN-O1-NEXT: Finalize ISel and expand pseudo-instructions
+; GCN-O1-NEXT: MachineDominator Tree Construction
+; GCN-O1-NEXT: SI Fix Physical Register Live Info
; GCN-O1-NEXT: Lazy Machine Block Frequency Analysis
; GCN-O1-NEXT: Early Tail Duplication
; GCN-O1-NEXT: Optimize machine instruction PHIs
@@ -629,6 +631,8 @@
; GCN-O1-OPTS-NEXT: MachinePostDominator Tree Construction
; GCN-O1-OPTS-NEXT: SI Lower i1 Copies
; GCN-O1-OPTS-NEXT: Finalize ISel and expand pseudo-instructions
+; GCN-O1-OPTS-NEXT: MachineDominator Tree Construction
+; GCN-O1-OPTS-NEXT: SI Fix Physical Register Live Info
; GCN-O1-OPTS-NEXT: Lazy Machine Block Frequency Analysis
; GCN-O1-OPTS-NEXT: Early Tail Duplication
; GCN-O1-OPTS-NEXT: Optimize machine instruction PHIs
@@ -951,6 +955,8 @@
; GCN-O2-NEXT: MachinePostDominator Tree Construction
; GCN-O2-NEXT: SI Lower i1 Copies
; GCN-O2-NEXT: Finalize ISel and expand pseudo-instructions
+; GCN-O2-NEXT: MachineDominator Tree Construction
+; GCN-O2-NEXT: SI Fix Physical Register Live Info
; GCN-O2-NEXT: Lazy Machine Block Frequency Analysis
; GCN-O2-NEXT: Early Tail Duplication
; GCN-O2-NEXT: Optimize machine instruction PHIs
@@ -1287,6 +1293,8 @@
; GCN-O3-NEXT: MachinePostDominator Tree Construction
; GCN-O3-NEXT: SI Lower i1 Copies
; GCN-O3-NEXT: Finalize ISel and expand pseudo-instructions
+; GCN-O3-NEXT: MachineDominator Tree Construction
+; GCN-O3-NEXT: SI Fix Physical Register Live Info
; GCN-O3-NEXT: Lazy Machine Block Frequency Analysis
; GCN-O3-NEXT: Early Tail Duplication
; GCN-O3-NEXT: Optimize machine instruction PHIs
diff --git a/llvm/test/CodeGen/AMDGPU/si-late-branch-lowering-preserve-loop-info.mir b/llvm/test/CodeGen/AMDGPU/si-late-branch-lowering-preserve-loop-info.mir
index b5c9319f809c0..3ab05b403432e 100644
--- a/llvm/test/CodeGen/AMDGPU/si-late-branch-lowering-preserve-loop-info.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-late-branch-lowering-preserve-loop-info.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes="require<machine-loops>,si-late-branch-lowering,print<machine-loops>" -debug-pass-manager -filetype=null %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes="phi-node-elimination,require<machine-loops>,si-late-branch-lowering,print<machine-loops>" -debug-pass-manager -filetype=null %s 2>&1 | FileCheck %s
# Test that MachineLoopInfo is preserved when splitting a block inside a loop
# due to early termination handling.
@@ -24,6 +24,7 @@ body: |
bb.1:
liveins: $vgpr0
successors: %bb.1, %bb.2
+ $scc = IMPLICIT_DEF
S_CMP_LG_U32 0, 1, implicit-def $scc
SI_EARLY_TERMINATE_SCC0 implicit $scc, implicit $exec
$vgpr1 = V_MOV_B32_e32 1, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-wwm-copies.mir b/llvm/test/CodeGen/AMDGPU/si-lower-wwm-copies.mir
index 039b6f9041129..aed4da55c1f2e 100644
--- a/llvm/test/CodeGen/AMDGPU/si-lower-wwm-copies.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-lower-wwm-copies.mir
@@ -15,7 +15,7 @@ body: |
; CHECK-LABEL: name: lower-wwm-copies
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
- ; CHECK-NEXT: liveins: $vgpr0, $scc
+ ; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $sgpr0 = IMPLICIT_DEF
; CHECK-NEXT: S_CMP_EQ_U32 $sgpr0, 0, implicit-def $scc
@@ -32,7 +32,7 @@ body: |
; CHECK-NEXT: $vgpr2 = COPY $vgpr1
; CHECK-NEXT: $exec = S_MOV_B64 killed $sgpr2_sgpr3
bb.0:
- liveins: $vgpr0, $scc
+ liveins: $vgpr0
$sgpr0 = IMPLICIT_DEF
S_CMP_EQ_U32 $sgpr0, 0, implicit-def $scc
$vgpr1 = WWM_COPY $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll b/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
index 08cc6f9b6fff0..6a3ac4665aab9 100644
--- a/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
+++ b/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
@@ -1963,13 +1963,15 @@ define amdgpu_ps void @scc_use_after_kill_inst(float inreg %x, i32 inreg %y) #0
; SI-NEXT: v_add_f32_e64 v1, s0, 1.0
; SI-NEXT: v_cmp_lt_f32_e32 vcc, 0, v1
; SI-NEXT: s_mov_b64 s[2:3], exec
-; SI-NEXT: s_cmp_lg_u32 s1, 0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc
+; SI-NEXT: s_cmp_lg_u32 s1, 0
; SI-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v1
+; SI-NEXT: s_cselect_b32 s0, 1, 0
; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc
; SI-NEXT: s_cbranch_scc0 .LBB17_6
; SI-NEXT: ; %bb.1: ; %bb
; SI-NEXT: s_andn2_b64 exec, exec, vcc
+; SI-NEXT: s_cmp_lg_u32 s0, 0
; SI-NEXT: s_cbranch_scc0 .LBB17_3
; SI-NEXT: ; %bb.2: ; %bb8
; SI-NEXT: s_mov_b32 s3, 0xf000
@@ -1999,6 +2001,7 @@ define amdgpu_ps void @scc_use_after_kill_inst(float inreg %x, i32 inreg %y) #0
; GFX10-WAVE64-NEXT: v_add_f32_e64 v1, s0, 1.0
; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec
; GFX10-WAVE64-NEXT: s_cmp_lg_u32 s1, 0
+; GFX10-WAVE64-NEXT: s_cselect_b32 s0, 1, 0
; GFX10-WAVE64-NEXT: v_cmp_lt_f32_e32 vcc, 0, v1
; GFX10-WAVE64-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc
; GFX10-WAVE64-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v1
@@ -2006,6 +2009,7 @@ define amdgpu_ps void @scc_use_after_kill_inst(float inreg %x, i32 inreg %y) #0
; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB17_6
; GFX10-WAVE64-NEXT: ; %bb.1: ; %bb
; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc
+; GFX10-WAVE64-NEXT: s_cmp_lg_u32 s0, 0
; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB17_3
; GFX10-WAVE64-NEXT: ; %bb.2: ; %bb8
; GFX10-WAVE64-NEXT: v_mov_b32_e32 v1, 8
@@ -2031,6 +2035,7 @@ define amdgpu_ps void @scc_use_after_kill_inst(float inreg %x, i32 inreg %y) #0
; GFX10-WAVE32-NEXT: v_add_f32_e64 v1, s0, 1.0
; GFX10-WAVE32-NEXT: s_mov_b32 s2, exec_lo
; GFX10-WAVE32-NEXT: s_cmp_lg_u32 s1, 0
+; GFX10-WAVE32-NEXT: s_cselect_b32 s0, 1, 0
; GFX10-WAVE32-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v1
; GFX10-WAVE32-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
; GFX10-WAVE32-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0, v1
@@ -2038,6 +2043,7 @@ define amdgpu_ps void @scc_use_after_kill_inst(float inreg %x, i32 inreg %y) #0
; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB17_6
; GFX10-WAVE32-NEXT: ; %bb.1: ; %bb
; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo
+; GFX10-WAVE32-NEXT: s_cmp_lg_u32 s0, 0
; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB17_3
; GFX10-WAVE32-NEXT: ; %bb.2: ; %bb8
; GFX10-WAVE32-NEXT: v_mov_b32_e32 v1, 8
@@ -2063,6 +2069,7 @@ define amdgpu_ps void @scc_use_after_kill_inst(float inreg %x, i32 inreg %y) #0
; GFX11-NEXT: v_add_f32_e64 v1, s0, 1.0
; GFX11-NEXT: s_mov_b64 s[2:3], exec
; GFX11-NEXT: s_cmp_lg_u32 s1, 0
+; GFX11-NEXT: s_cselect_b32 s0, 1, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cmp_lt_f32_e32 vcc, 0, v1
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc
@@ -2072,6 +2079,7 @@ define amdgpu_ps void @scc_use_after_kill_inst(float inreg %x, i32 inreg %y) #0
; GFX11-NEXT: s_cbranch_scc0 .LBB17_6
; GFX11-NEXT: ; %bb.1: ; %bb
; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc
+; GFX11-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-NEXT: s_cbranch_scc0 .LBB17_3
; GFX11-NEXT: ; %bb.2: ; %bb8
; GFX11-NEXT: v_mov_b32_e32 v1, 8
diff --git a/llvm/test/CodeGen/AMDGPU/wait-xcnt.mir b/llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
index 84f1d4e150d65..ad1e07c1663da 100644
--- a/llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
+++ b/llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -run-pass si-insert-waitcnts -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -run-pass=si-insert-waitcnts -o - %s | FileCheck -check-prefix=GCN %s
---
name: vmem_scratch_load
@@ -954,9 +954,10 @@ body: |
; GCN-LABEL: name: wait_kmcnt_with_outstanding_vmem_2
; GCN: bb.0:
; GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ ; GCN-NEXT: $scc = IMPLICIT_DEF
; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -973,8 +974,9 @@ body: |
; GCN-NEXT: S_WAIT_XCNT 0
; GCN-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
bb.0:
- liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ $scc = IMPLICIT_DEF
S_CBRANCH_SCC1 %bb.2, implicit $scc
bb.1:
liveins: $vgpr0_vgpr1, $sgpr2
@@ -994,9 +996,10 @@ body: |
; GCN-LABEL: name: wait_kmcnt_and_wait_loadcnt
; GCN: bb.0:
; GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ ; GCN-NEXT: $scc = IMPLICIT_DEF
; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -1013,8 +1016,9 @@ body: |
; GCN-NEXT: S_WAIT_LOADCNT 0
; GCN-NEXT: $vgpr2 = V_MOV_B32_e32 0, implicit $exec
bb.0:
- liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ $scc = IMPLICIT_DEF
S_CBRANCH_SCC1 %bb.2, implicit $scc
bb.1:
liveins: $vgpr0_vgpr1, $sgpr2
@@ -1034,9 +1038,10 @@ body: |
; GCN-LABEL: name: implicit_handling_of_pending_vmem_group
; GCN: bb.0:
; GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ ; GCN-NEXT: $scc = IMPLICIT_DEF
; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -1055,8 +1060,9 @@ body: |
; GCN-NEXT: S_WAIT_XCNT 0
; GCN-NEXT: $sgpr0 = S_MOV_B32 $sgpr0
bb.0:
- liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ $scc = IMPLICIT_DEF
S_CBRANCH_SCC1 %bb.2, implicit $scc
bb.1:
liveins: $vgpr0_vgpr1, $sgpr2
@@ -1078,10 +1084,11 @@ body: |
; GCN-LABEL: name: mixed_pending_events
; GCN: bb.0:
; GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
- ; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc
+ ; GCN-NEXT: $scc = IMPLICIT_DEF
+ ; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
; GCN-NEXT: successors: %bb.2(0x80000000)
@@ -1100,8 +1107,9 @@ body: |
; GCN-NEXT: S_WAIT_XCNT 0
; GCN-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
bb.0:
- liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ $scc = IMPLICIT_DEF
S_CBRANCH_SCC1 %bb.2, implicit $scc
bb.1:
liveins: $vgpr0_vgpr1, $sgpr2
@@ -1123,9 +1131,10 @@ body: |
; GCN-LABEL: name: pending_vmem_event_between_block
; GCN: bb.0:
; GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ ; GCN-NEXT: $scc = IMPLICIT_DEF
; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -1146,8 +1155,9 @@ body: |
; GCN-NEXT: $vgpr2 = V_MOV_B32_e32 0, implicit $exec
; GCN-NEXT: $sgpr0 = S_MOV_B32 $sgpr0
bb.0:
- liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ $scc = IMPLICIT_DEF
S_CBRANCH_SCC1 %bb.2, implicit $scc
bb.1:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr2
@@ -1170,9 +1180,10 @@ body: |
; GCN-LABEL: name: flushing_vmem_cnt_on_block_entry
; GCN: bb.0:
; GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ ; GCN-NEXT: $scc = IMPLICIT_DEF
; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -1190,8 +1201,9 @@ body: |
; GCN-NEXT: $vgpr2 = V_MOV_B32_e32 0, implicit $exec
; GCN-NEXT: $sgpr0 = S_MOV_B32 $sgpr0
bb.0:
- liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ $scc = IMPLICIT_DEF
S_CBRANCH_SCC1 %bb.2, implicit $scc
bb.1:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr2
>From b9f2b964151dafd6f033756ab4f4a1e165bbdaa6 Mon Sep 17 00:00:00 2001
From: zwu-2025 <Zeng.Wu2 at amd.com>
Date: Wed, 6 May 2026 23:04:06 +0000
Subject: [PATCH 3/5] Drop redundant changes
---
llvm/lib/Target/AMDGPU/SIProgramInfo.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp b/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
index 99255e4060886..471e2f7a3857c 100644
--- a/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
@@ -138,11 +138,11 @@ static uint64_t getPGMRSrc1Reg(const SIProgramInfo &ProgInfo,
static uint64_t getComputePGMRSrc2Reg(const GCNSubtarget &ST,
const SIProgramInfo &ProgInfo) {
- uint64_t MaxNumUserSGRPs = AMDGPU::getMaxNumUserSGPRs(ST);
+ uint64_t MaxNumerUserSGRPs = AMDGPU::getMaxNumUserSGPRs(ST);
uint64_t Reg = 0;
- if (MaxNumUserSGRPs == 32) {
+ if (MaxNumerUserSGRPs == 32) {
Reg = S_00B84C_USER_SGPR_GFX1250(ProgInfo.UserSGPR);
- } else if (MaxNumUserSGRPs == 16) {
+ } else if (MaxNumerUserSGRPs == 16) {
Reg = (S_00B84C_USER_SGPR(ProgInfo.UserSGPR) |
S_00B84C_TRAP_HANDLER(ProgInfo.TrapHandlerEnable));
} else {
>From 00aacd9cc44b2b3dc536deaf9586ecb02f994937 Mon Sep 17 00:00:00 2001
From: zwu-2025 <Zeng.Wu2 at amd.com>
Date: Sun, 10 May 2026 06:41:58 +0000
Subject: [PATCH 4/5] use splitbb to fix scc clobber bug
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 4 -
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 1 -
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 -
llvm/lib/Target/AMDGPU/CMakeLists.txt | 1 -
.../AMDGPU/SIFixPhysicalRegisterLiveInfo.cpp | 185 ------------------
.../AMDGPU/SIFixPhysicalRegisterLiveInfo.h | 30 ---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 42 ++++
.../AMDGPU/finalize-isel-kill-scc-vcc.mir | 2 +-
llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 2 -
llvm/test/CodeGen/AMDGPU/llc-pipeline.ll | 8 -
10 files changed, 43 insertions(+), 239 deletions(-)
delete mode 100644 llvm/lib/Target/AMDGPU/SIFixPhysicalRegisterLiveInfo.cpp
delete mode 100644 llvm/lib/Target/AMDGPU/SIFixPhysicalRegisterLiveInfo.h
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 7ee417a385cb7..6ace220ace071 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -55,7 +55,6 @@ FunctionPass *createSIMemoryLegalizerPass();
FunctionPass *createSIInsertWaitcntsPass();
FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
FunctionPass *createSIFormMemoryClausesLegacyPass();
-FunctionPass *createSIFixPhysicalRegisterLiveInfoLegacyPass();
FunctionPass *createSIPostRABundlerPass();
FunctionPass *createAMDGPUImageIntrinsicOptimizerPass(const TargetMachine *);
ModulePass *createAMDGPURemoveIncompatibleFunctionsPass(const TargetMachine *);
@@ -195,9 +194,6 @@ extern char &SIFixSGPRCopiesLegacyID;
void initializeSIFixVGPRCopiesLegacyPass(PassRegistry &);
extern char &SIFixVGPRCopiesID;
-void initializeSIFixPhysicalRegisterLiveInfoLegacyPass(PassRegistry &);
-extern char &SIFixPhysicalRegisterLiveInfoLegacyID;
-
void initializeAMDGPUNextUseAnalysisLegacyPassPass(PassRegistry &);
extern char &AMDGPUNextUseAnalysisLegacyID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 62f795de87b4c..2a6560b309e62 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -153,7 +153,6 @@ MACHINE_FUNCTION_PASS("si-pre-allocate-wwm-regs", SIPreAllocateWWMRegsPass())
MACHINE_FUNCTION_PASS("si-pre-emit-peephole", SIPreEmitPeepholePass())
MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
MACHINE_FUNCTION_PASS("si-wqm", SIWholeQuadModePass())
-MACHINE_FUNCTION_PASS("si-fix-physical-register-live-info", SIFixPhysicalRegisterLiveInfoPass())
#undef MACHINE_FUNCTION_PASS
#define DUMMY_MACHINE_FUNCTION_PASS(NAME, CREATE_PASS)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 19aed2a4016ff..c892645c32123 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -49,7 +49,6 @@
#include "GCNVOPDUtils.h"
#include "R600.h"
#include "R600TargetMachine.h"
-#include "SIFixPhysicalRegisterLiveInfo.h"
#include "SIFixSGPRCopies.h"
#include "SIFixVGPRCopies.h"
#include "SIFoldOperands.h"
@@ -679,7 +678,6 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
initializeSIShrinkInstructionsLegacyPass(*PR);
initializeSIOptimizeExecMaskingPreRALegacyPass(*PR);
initializeSIOptimizeVGPRLiveRangeLegacyPass(*PR);
- initializeSIFixPhysicalRegisterLiveInfoLegacyPass(*PR);
initializeAMDGPUNextUseAnalysisLegacyPassPass(*PR);
initializeAMDGPUNextUseAnalysisPrinterLegacyPassPass(*PR);
initializeSILoadStoreOptimizerLegacyPass(*PR);
@@ -1616,8 +1614,6 @@ bool GCNPassConfig::addPreISel() {
}
void GCNPassConfig::addMachineSSAOptimization() {
- addPass(&SIFixPhysicalRegisterLiveInfoLegacyID);
-
TargetPassConfig::addMachineSSAOptimization();
// We want to fold operands after PeepholeOptimizer has run (or as part of
@@ -2423,9 +2419,6 @@ void AMDGPUCodeGenPassBuilder::addPreRewrite(PassManagerWrapper &PMW) const {
void AMDGPUCodeGenPassBuilder::addMachineSSAOptimization(
PassManagerWrapper &PMW) const {
-
- // Just after finalize-isel
- addMachineFunctionPass(SIFixPhysicalRegisterLiveInfoPass(), PMW);
Base::addMachineSSAOptimization(PMW);
addMachineFunctionPass(SIFoldOperandsPass(), PMW);
diff --git a/llvm/lib/Target/AMDGPU/CMakeLists.txt b/llvm/lib/Target/AMDGPU/CMakeLists.txt
index c61b13e05ef4e..ae8f1c0fad5ba 100644
--- a/llvm/lib/Target/AMDGPU/CMakeLists.txt
+++ b/llvm/lib/Target/AMDGPU/CMakeLists.txt
@@ -190,7 +190,6 @@ add_llvm_target(AMDGPUCodeGen
SIRegisterInfo.cpp
SIShrinkInstructions.cpp
SIWholeQuadMode.cpp
- SIFixPhysicalRegisterLiveInfo.cpp
LINK_COMPONENTS
AMDGPUDesc
diff --git a/llvm/lib/Target/AMDGPU/SIFixPhysicalRegisterLiveInfo.cpp b/llvm/lib/Target/AMDGPU/SIFixPhysicalRegisterLiveInfo.cpp
deleted file mode 100644
index 46b99db4dbc92..0000000000000
--- a/llvm/lib/Target/AMDGPU/SIFixPhysicalRegisterLiveInfo.cpp
+++ /dev/null
@@ -1,185 +0,0 @@
-#include "SIFixPhysicalRegisterLiveInfo.h"
-#include "AMDGPU.h"
-#include "GCNSubtarget.h"
-#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
-#include "llvm/ADT/Statistic.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
-#include "llvm/CodeGen/MachineDominators.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/InitializePasses.h"
-#include "llvm/Target/TargetMachine.h"
-
-using namespace llvm;
-
-#define DEBUG_TYPE "si-fix-physical-register-live-info"
-
-namespace {
-
-struct SIFixPhysicalRegisterLiveInfo {
- MachineDominatorTree *MDT;
- SIFixPhysicalRegisterLiveInfo(MachineDominatorTree *MDT) : MDT(MDT) {}
- void getAnalysisUsage(AnalysisUsage &AU) const;
- const MachineInstr *definedInBlock(const SIRegisterInfo *TRI,
- MachineBasicBlock *MBB, Register Reg);
-
- bool run(MachineFunction &MF);
-};
-
-struct SIFixPhysicalRegisterLiveInfoLegacy : public MachineFunctionPass {
-public:
- static char ID;
-
- SIFixPhysicalRegisterLiveInfoLegacy() : MachineFunctionPass(ID) {}
-
- bool runOnMachineFunction(MachineFunction &MF) override;
-
- StringRef getPassName() const override {
- return "SI Fix Physical Register Live Info";
- }
-
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.addRequired<MachineDominatorTreeWrapperPass>();
- AU.addPreserved<MachineDominatorTreeWrapperPass>();
- AU.setPreservesCFG();
- MachineFunctionPass::getAnalysisUsage(AU);
- }
-
- MachineFunctionProperties getRequiredProperties() const override {
- return MachineFunctionProperties().setIsSSA();
- }
-};
-
-} // end of anonymous namespace
-
-INITIALIZE_PASS_BEGIN(SIFixPhysicalRegisterLiveInfoLegacy, DEBUG_TYPE,
- "SI Fix Physical Register Live Info", false, false)
-INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
-INITIALIZE_PASS_END(SIFixPhysicalRegisterLiveInfoLegacy, DEBUG_TYPE,
- "SI Fix Physical Register Live Info", false, false)
-
-char SIFixPhysicalRegisterLiveInfoLegacy::ID = 0;
-
-char &llvm::SIFixPhysicalRegisterLiveInfoLegacyID =
- SIFixPhysicalRegisterLiveInfoLegacy::ID;
-
-FunctionPass *llvm::createSIFixPhysicalRegisterLiveInfoLegacyPass() {
- return new SIFixPhysicalRegisterLiveInfoLegacy();
-}
-
-bool SIFixPhysicalRegisterLiveInfoLegacy::runOnMachineFunction(
- MachineFunction &MF) {
- if (skipFunction(MF.getFunction()))
- return false;
-
- MachineDominatorTree &MDT =
- getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
- SIFixPhysicalRegisterLiveInfo Impl(&MDT);
- return Impl.run(MF);
-}
-
-PreservedAnalyses
-SIFixPhysicalRegisterLiveInfoPass::run(MachineFunction &MF,
- MachineFunctionAnalysisManager &MFAM) {
- MachineDominatorTree &MDT = MFAM.getResult<MachineDominatorTreeAnalysis>(MF);
- SIFixPhysicalRegisterLiveInfo Impl(&MDT);
- bool Changed = Impl.run(MF);
- if (!Changed)
- return PreservedAnalyses::all();
-
- auto PA = getMachineFunctionPassPreservedAnalyses();
- PA.preserveSet<CFGAnalyses>();
- return PA;
-}
-
-bool SIFixPhysicalRegisterLiveInfo::run(MachineFunction &MF) {
- MachineRegisterInfo &MRI = MF.getRegInfo();
- if (!MRI.isSSA())
- return false;
-
- bool Changed = false;
-
- const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
- const SIRegisterInfo *TRI = ST.getRegisterInfo();
- const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
-
- // Check SCC for now.
- for (Register Reg : {AMDGPU::SCC}) {
- for (MachineBasicBlock &MBB : MF) {
- if (!MBB.isLiveIn(Reg))
- continue;
-
- MachineBasicBlock *UseBB = &MBB;
- MachineBasicBlock *DefBB = nullptr;
- const MachineInstr *DefMI = nullptr;
- // The PHI node is not considered here. Theoritically, if the physical
- // register is live out of a block, the InstrEmitter in the DAG Isel will
- // copy it out.
- MachineDomTreeNode *Node = MDT->getNode(&MBB)->getIDom();
- while (Node != nullptr) {
- DefBB = Node->getBlock();
- DefMI = definedInBlock(TRI, DefBB, Reg);
- if (DefMI != nullptr)
- break;
-
- Node = Node->getIDom();
- }
-
- Register NewCopy =
- MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0_XEXECRegClass);
- if (DefMI == nullptr) {
- // kernel arguments
- MachineBasicBlock &EntryBB = MF.front();
- assert(EntryBB.isLiveIn(Reg));
- DebugLoc DL = DefMI->getDebugLoc();
-
- BuildMI(EntryBB, EntryBB.getFirstTerminator(), DebugLoc(),
- TII->get(TargetOpcode::COPY), NewCopy)
- .addReg(Reg);
-
- } else {
- DebugLoc DL = DefMI->getDebugLoc();
- // Insert a COPY just SCC instruction which defines it.
- BuildMI(*DefBB,
- std::next(const_cast<MachineInstr *>(DefMI)->getIterator()), DL,
- TII->get(TargetOpcode::COPY), NewCopy)
- .addReg(Reg);
- }
-
- // Copy back to $scc in the SplitBB
- MachineBasicBlock::iterator InsertPt = UseBB->getFirstNonPHI();
- BuildMI(*UseBB, InsertPt, InsertPt->getDebugLoc(),
- TII->get(TargetOpcode::COPY), Reg)
- .addReg(NewCopy, RegState::Kill);
-
- // Now remove the scc from the livein of UseBB
- UseBB->removeLiveIn(Reg);
- }
- }
-
- return Changed;
-}
-
-// Returns the iterator where the Physical Reg is defined, so that an COPY out
-// will be inserted just after the definition point. Or else, the value could be
-// clobbered by the following instructions.
-const MachineInstr *SIFixPhysicalRegisterLiveInfo::definedInBlock(
- const SIRegisterInfo *TRI, MachineBasicBlock *MBB, Register Reg) {
- for (MachineBasicBlock::reverse_iterator I = MBB->rbegin(), E = MBB->rend();
- I != E; ++I) {
- if (I->isDebugInstr())
- continue;
-
- if (I->isCall()) {
- // $scc is caller saved register, so if it is clobbered, we ingore it
- // since the value of $scc is not a useful one.
- continue;
- }
-
- if (I->definesRegister(Reg, TRI))
- return &*I;
- }
-
- return nullptr;
-}
diff --git a/llvm/lib/Target/AMDGPU/SIFixPhysicalRegisterLiveInfo.h b/llvm/lib/Target/AMDGPU/SIFixPhysicalRegisterLiveInfo.h
deleted file mode 100644
index 85bd9b5050f9c..0000000000000
--- a/llvm/lib/Target/AMDGPU/SIFixPhysicalRegisterLiveInfo.h
+++ /dev/null
@@ -1,30 +0,0 @@
-//=======--- SIFixPhysicalRegisterLiveInfo.h - fix physical registers live info
-//---==========//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIB_TARGET_AMDGPU_SIFIXPHYSICALREGISTERLIVEINFO_H
-#define LLVM_LIB_TARGET_AMDGPU_SIFIXPHYSICALREGISTERLIVEINFO_H
-
-#include "AMDGPU.h"
-#include "llvm/CodeGen/MachinePassManager.h"
-
-namespace llvm {
-class SIFixPhysicalRegisterLiveInfoPass
- : public PassInfoMixin<SIFixPhysicalRegisterLiveInfoPass> {
-public:
- PreservedAnalyses run(MachineFunction &MF,
- MachineFunctionAnalysisManager &MAM);
-
- MachineFunctionProperties getRequiredProperties() const {
- return MachineFunctionProperties().setIsSSA();
- }
-};
-
-} // end namespace llvm
-
-#endif // LLVM_LIB_TARGET_AMDGPU_GCNDPPCOMBINE_H
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 92d9e305f2c3b..babacb7e1935a 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5011,6 +5011,48 @@ SITargetLowering::splitKillBlock(MachineInstr &MI,
MachineBasicBlock *BB) const {
MachineBasicBlock *SplitBB = BB->splitAt(MI, /*UpdateLiveIns=*/true);
const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
+
+ if (SplitBB->isLiveIn(AMDGPU::SCC)) {
+ const GCNSubtarget &ST = BB->getParent()->getSubtarget<GCNSubtarget>();
+ const SIRegisterInfo *TRI = ST.getRegisterInfo();
+ MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
+ DebugLoc DL = MI.getDebugLoc();
+
+ // Insert a COPY from SCC from the last instruction which defines SCC in
+ // `BB`
+ bool Inserted = false;
+ Register SCCCopy;
+ for (auto I = BB->rbegin(), E = BB->rend(); I != E; ++I) {
+ if (I->isDebugInstr())
+ continue;
+
+ if (I->isCall()) {
+ // $scc is caller saved register, so if it is clobbered, we ingore it
+ // since the value of $scc is not a useful one.
+ continue;
+ }
+ if (I->definesRegister(AMDGPU::SCC, TRI)) {
+ SCCCopy = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0_XEXECRegClass);
+ // const TargetRegisterClass *RC =
+ // TRI->getAllocatableClass(&AMDGPU::SCC_CLASSRegClass); SCCCopy =
+ // MRI.createVirtualRegister(RC);
+ BuildMI(*BB, std::next(I->getIterator()), DL,
+ TII->get(TargetOpcode::COPY), SCCCopy)
+ .addReg(AMDGPU::SCC);
+ Inserted = true;
+ break;
+ }
+ }
+
+ assert(Inserted);
+ // Copy back to $scc in the SplitBB
+ BuildMI(*SplitBB, SplitBB->getFirstNonPHI(), DL,
+ TII->get(TargetOpcode::COPY), AMDGPU::SCC)
+ .addReg(SCCCopy, RegState::Kill);
+ // Now remove the scc from the livein of splitBB
+ SplitBB->removeLiveIn(AMDGPU::SCC);
+ }
+
MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode()));
return SplitBB;
}
diff --git a/llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir b/llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir
index 70d25ed053b4d..706f78ecee3f1 100644
--- a/llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir
+++ b/llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn -run-pass=finalize-isel,si-fix-physical-register-live-info -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -run-pass=finalize-isel -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs %s -o - | FileCheck %s
---
name: phi_use_def_before_kill
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
index 16418c0d089a0..c49b2b927bd31 100644
--- a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
@@ -165,7 +165,6 @@
; GCN-O2-NEXT: si-fix-sgpr-copies
; GCN-O2-NEXT: si-i1-copies
; GCN-O2-NEXT: finalize-isel
-; GCN-O2-NEXT: si-fix-physical-register-live-info
; GCN-O2-NEXT: early-tailduplication
; GCN-O2-NEXT: opt-phis
; GCN-O2-NEXT: stack-coloring
@@ -335,7 +334,6 @@
; GCN-O3-NEXT: si-fix-sgpr-copies
; GCN-O3-NEXT: si-i1-copies
; GCN-O3-NEXT: finalize-isel
-; GCN-O3-NEXT: si-fix-physical-register-live-info
; GCN-O3-NEXT: early-tailduplication
; GCN-O3-NEXT: opt-phis
; GCN-O3-NEXT: stack-coloring
diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
index 05cf42a3edadd..070c873798647 100644
--- a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
+++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
@@ -318,8 +318,6 @@
; GCN-O1-NEXT: MachinePostDominator Tree Construction
; GCN-O1-NEXT: SI Lower i1 Copies
; GCN-O1-NEXT: Finalize ISel and expand pseudo-instructions
-; GCN-O1-NEXT: MachineDominator Tree Construction
-; GCN-O1-NEXT: SI Fix Physical Register Live Info
; GCN-O1-NEXT: Lazy Machine Block Frequency Analysis
; GCN-O1-NEXT: Early Tail Duplication
; GCN-O1-NEXT: Optimize machine instruction PHIs
@@ -631,8 +629,6 @@
; GCN-O1-OPTS-NEXT: MachinePostDominator Tree Construction
; GCN-O1-OPTS-NEXT: SI Lower i1 Copies
; GCN-O1-OPTS-NEXT: Finalize ISel and expand pseudo-instructions
-; GCN-O1-OPTS-NEXT: MachineDominator Tree Construction
-; GCN-O1-OPTS-NEXT: SI Fix Physical Register Live Info
; GCN-O1-OPTS-NEXT: Lazy Machine Block Frequency Analysis
; GCN-O1-OPTS-NEXT: Early Tail Duplication
; GCN-O1-OPTS-NEXT: Optimize machine instruction PHIs
@@ -955,8 +951,6 @@
; GCN-O2-NEXT: MachinePostDominator Tree Construction
; GCN-O2-NEXT: SI Lower i1 Copies
; GCN-O2-NEXT: Finalize ISel and expand pseudo-instructions
-; GCN-O2-NEXT: MachineDominator Tree Construction
-; GCN-O2-NEXT: SI Fix Physical Register Live Info
; GCN-O2-NEXT: Lazy Machine Block Frequency Analysis
; GCN-O2-NEXT: Early Tail Duplication
; GCN-O2-NEXT: Optimize machine instruction PHIs
@@ -1293,8 +1287,6 @@
; GCN-O3-NEXT: MachinePostDominator Tree Construction
; GCN-O3-NEXT: SI Lower i1 Copies
; GCN-O3-NEXT: Finalize ISel and expand pseudo-instructions
-; GCN-O3-NEXT: MachineDominator Tree Construction
-; GCN-O3-NEXT: SI Fix Physical Register Live Info
; GCN-O3-NEXT: Lazy Machine Block Frequency Analysis
; GCN-O3-NEXT: Early Tail Duplication
; GCN-O3-NEXT: Optimize machine instruction PHIs
>From a9a329e783f9bb2ae6b064c83b67beccae7b168a Mon Sep 17 00:00:00 2001
From: zwu-2025 <Zeng.Wu2 at amd.com>
Date: Sun, 10 May 2026 06:43:04 +0000
Subject: [PATCH 5/5] cleanup
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 6ace220ace071..5c7259b7600a9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -55,6 +55,7 @@ FunctionPass *createSIMemoryLegalizerPass();
FunctionPass *createSIInsertWaitcntsPass();
FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
FunctionPass *createSIFormMemoryClausesLegacyPass();
+
FunctionPass *createSIPostRABundlerPass();
FunctionPass *createAMDGPUImageIntrinsicOptimizerPass(const TargetMachine *);
ModulePass *createAMDGPURemoveIncompatibleFunctionsPass(const TargetMachine *);
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