[llvm] [AMDGPU] Add subtarget features for MAD NC and 64-bit MIN/MAX instructions (PR #196326)
Mariusz Sikora via llvm-commits
llvm-commits at lists.llvm.org
Fri May 8 09:43:47 PDT 2026
https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/196326
>From f803432eefb04d66b7516726495b304f62399a8c Mon Sep 17 00:00:00 2001
From: Mariusz Sikora <mariusz.sikora at amd.com>
Date: Thu, 7 May 2026 10:23:37 -0400
Subject: [PATCH 1/3] [AMDGPU] Add subtarget features for MAD NC and 64-bit
MIN/MAX instructions
---
llvm/lib/Target/AMDGPU/AMDGPU.td | 10 ++++++++++
llvm/lib/Target/AMDGPU/VOP3Instructions.td | 6 +++---
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 25fc64d178858..dde14ef6574a8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1317,10 +1317,18 @@ defm MadU32Inst : AMDGPUSubtargetFeature<"mad-u32-inst",
"Has v_mad_u32 instruction"
>;
+defm MadNC64_32Insts : AMDGPUSubtargetFeature<"mad-nc-64-32-insts",
+ "Has v_mad_nc_{u64_u32|i64_i32} instructions"
+>;
+
defm AddMinMaxInsts : AMDGPUSubtargetFeature<"add-min-max-insts",
"Has v_add_{min|max}_{i|u}32 instructions"
>;
+defm MinMax64Insts : AMDGPUSubtargetFeature<"min-max-64-insts",
+ "Has v_{min|max}_{i|u}64 instructions"
+>;
+
defm PkAddMinMaxInsts : AMDGPUSubtargetFeature<"pk-add-min-max-insts",
"Has v_pk_add_{min|max}_{i|u}16 instructions"
>;
@@ -2097,7 +2105,9 @@ def FeatureISAVersion12_50_Common : FeatureSet<
FeatureLshlAddU64Inst,
FeatureAddSubU64Insts,
FeatureMadU32Inst,
+ FeatureMadNC64_32Insts,
FeatureAddMinMaxInsts,
+ FeatureMinMax64Insts,
FeaturePkAddMinMaxInsts,
FeatureLdsBarrierArriveAtomic,
FeatureSetPrioIncWgInst,
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 41e76063386ec..4970d24125d45 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -191,7 +191,7 @@ let SubtargetPredicate = HasLerpInst in
let SchedRW = [WriteIntMul] in {
let SubtargetPredicate = HasMadU32Inst in
defm V_MAD_U32 : VOP3Inst <"v_mad_u32", V_MAD_U32_PROF>;
- let SubtargetPredicate = isGFX1250Plus in {
+ let SubtargetPredicate = HasMadNC64_32Insts in {
defm V_MAD_NC_U64_U32 : VOP3Inst<"v_mad_nc_u64_u32", VOP_I32_I32_I64_DPP>;
defm V_MAD_NC_I64_I32 : VOP3Inst<"v_mad_nc_i64_i32", VOP_I32_I32_I64_DPP>;
}
@@ -232,12 +232,12 @@ defm V_MAXIMUM_F64 : VOP3Inst <"v_maximum_f64", VOP3_Profile<VOP_F64_F64_F64>, f
} // End SchedRW = [WriteDoubleAdd], IsDPMACCInstruction = 1
} // End SubtargetPredicate = HasIEEEMinimumMaximumInsts, ReadsModeReg = 0, AddedComplexity = 1
-let SubtargetPredicate = isGFX1250Plus, SchedRW = [WriteDoubleAdd] in {
+let SubtargetPredicate = HasMinMax64Insts, SchedRW = [WriteDoubleAdd] in {
defm V_MAX_I64 : VOP3Inst <"v_max_i64", VOP_I64_I64_I64_DPP, smax>;
defm V_MAX_U64 : VOP3Inst <"v_max_u64", VOP_I64_I64_I64_DPP, umax>;
defm V_MIN_I64 : VOP3Inst <"v_min_i64", VOP_I64_I64_I64_DPP, smin>;
defm V_MIN_U64 : VOP3Inst <"v_min_u64", VOP_I64_I64_I64_DPP, umin>;
-} // End SubtargetPredicate = isGFX1250Plus, SchedRW = [WriteDoubleAdd]
+} // End SubtargetPredicate = HasMinMax64Insts, SchedRW = [WriteDoubleAdd]
} // End isReMaterializable = 1
>From b48415200e5fce565fa883af55dede6512a0efc1 Mon Sep 17 00:00:00 2001
From: Mariusz Sikora <mariusz.sikora at amd.com>
Date: Thu, 7 May 2026 15:11:25 -0400
Subject: [PATCH 2/3] change MinMax64 to MinMaxI64
---
llvm/lib/Target/AMDGPU/AMDGPU.td | 4 ++--
llvm/lib/Target/AMDGPU/VOP3Instructions.td | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index dde14ef6574a8..ee8cd705c2835 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1325,7 +1325,7 @@ defm AddMinMaxInsts : AMDGPUSubtargetFeature<"add-min-max-insts",
"Has v_add_{min|max}_{i|u}32 instructions"
>;
-defm MinMax64Insts : AMDGPUSubtargetFeature<"min-max-64-insts",
+defm MinMaxI64Insts : AMDGPUSubtargetFeature<"min-max-i64-insts",
"Has v_{min|max}_{i|u}64 instructions"
>;
@@ -2107,7 +2107,7 @@ def FeatureISAVersion12_50_Common : FeatureSet<
FeatureMadU32Inst,
FeatureMadNC64_32Insts,
FeatureAddMinMaxInsts,
- FeatureMinMax64Insts,
+ FeatureMinMaxI64Insts,
FeaturePkAddMinMaxInsts,
FeatureLdsBarrierArriveAtomic,
FeatureSetPrioIncWgInst,
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 4970d24125d45..fc772ffeb1141 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -232,12 +232,12 @@ defm V_MAXIMUM_F64 : VOP3Inst <"v_maximum_f64", VOP3_Profile<VOP_F64_F64_F64>, f
} // End SchedRW = [WriteDoubleAdd], IsDPMACCInstruction = 1
} // End SubtargetPredicate = HasIEEEMinimumMaximumInsts, ReadsModeReg = 0, AddedComplexity = 1
-let SubtargetPredicate = HasMinMax64Insts, SchedRW = [WriteDoubleAdd] in {
+let SubtargetPredicate = HasMinMaxI64Insts, SchedRW = [WriteDoubleAdd] in {
defm V_MAX_I64 : VOP3Inst <"v_max_i64", VOP_I64_I64_I64_DPP, smax>;
defm V_MAX_U64 : VOP3Inst <"v_max_u64", VOP_I64_I64_I64_DPP, umax>;
defm V_MIN_I64 : VOP3Inst <"v_min_i64", VOP_I64_I64_I64_DPP, smin>;
defm V_MIN_U64 : VOP3Inst <"v_min_u64", VOP_I64_I64_I64_DPP, umin>;
-} // End SubtargetPredicate = HasMinMax64Insts, SchedRW = [WriteDoubleAdd]
+} // End SubtargetPredicate = HasMinMaxI64Insts, SchedRW = [WriteDoubleAdd]
} // End isReMaterializable = 1
>From b10baa4d7b294d6cac26b3fa9a0a2df2514fb266 Mon Sep 17 00:00:00 2001
From: Mariusz Sikora <mariusz.sikora at amd.com>
Date: Fri, 8 May 2026 05:47:17 -0400
Subject: [PATCH 3/3] Remove extra space
---
llvm/lib/Target/AMDGPU/AMDGPU.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index ee8cd705c2835..f12c404c035ae 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1318,7 +1318,7 @@ defm MadU32Inst : AMDGPUSubtargetFeature<"mad-u32-inst",
>;
defm MadNC64_32Insts : AMDGPUSubtargetFeature<"mad-nc-64-32-insts",
- "Has v_mad_nc_{u64_u32|i64_i32} instructions"
+ "Has v_mad_nc_{u64_u32|i64_i32} instructions"
>;
defm AddMinMaxInsts : AMDGPUSubtargetFeature<"add-min-max-insts",
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