[llvm] [DAG][GISel] Rename CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF/CTTZ_ELTS_ZERO_UNDEF -> CTTZ_ZERO_POISON/CTLZ_ZERO_POISON/CTTZ_ELTS_ZERO_POISON (PR #196732)
via llvm-commits
llvm-commits at lists.llvm.org
Sat May 9 08:06:01 PDT 2026
github-actions[bot] wrote:
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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h llvm/include/llvm/CodeGen/GlobalISel/Utils.h llvm/include/llvm/CodeGen/ISDOpcodes.h llvm/include/llvm/CodeGen/TargetLowering.h llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp llvm/lib/CodeGen/GlobalISel/Utils.cpp llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/lib/CodeGen/TargetLoweringBase.cpp llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp llvm/lib/Target/AMDGPU/R600ISelLowering.cpp llvm/lib/Target/AMDGPU/SIISelLowering.cpp llvm/lib/Target/ARM/ARMISelLowering.cpp llvm/lib/Target/ARM/ARMLegalizerInfo.cpp llvm/lib/Target/BPF/BPFISelLowering.cpp llvm/lib/Target/Mips/MipsLegalizerInfo.cpp llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVISelLowering.h llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp llvm/lib/Target/Sparc/SparcISelLowering.cpp llvm/lib/Target/SystemZ/SystemZISelLowering.cpp llvm/lib/Target/VE/VEISelLowering.cpp llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp llvm/lib/Target/X86/X86ISelLowering.cpp llvm/lib/Target/X86/X86TargetTransformInfo.cpp llvm/lib/Target/Xtensa/XtensaISelLowering.cpp llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp --diff_from_common_commit
``````````
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``````````diff
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 259467f78..423f38d99 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -10466,7 +10466,8 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::SRL_PARTS:
case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
case ISD::CTTZ:
- case ISD::CTTZ_ZERO_POISON: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
+ case ISD::CTTZ_ZERO_POISON:
+ return LowerCTTZ(Op.getNode(), DAG, Subtarget);
case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
case ISD::SETCC: return LowerVSETCC(Op, DAG, Subtarget);
case ISD::SETCCCARRY: return LowerSETCCCARRY(Op, DAG);
diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
index 95074a1ef..03295a9fb 100644
--- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -259,8 +259,7 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
.legalFor({{s32, s32}})
.maxScalar(0, s32)
.maxScalar(1, s32);
- getActionDefinitionsBuilder(G_CTLZ_ZERO_POISON)
- .lowerFor({{s32, s32}});
+ getActionDefinitionsBuilder(G_CTLZ_ZERO_POISON).lowerFor({{s32, s32}});
getActionDefinitionsBuilder(G_CTTZ)
.lowerFor({{s32, s32}})
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 93e820b47..642473c89 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -866,14 +866,23 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::INTRINSIC_W_CHAIN, ISD::INTRINSIC_VOID},
MVT::Other, Custom);
- static const unsigned IntegerVPOps[] = {
- ISD::VP_SDIV, ISD::VP_UDIV, ISD::VP_SREM,
- ISD::VP_UREM, ISD::VP_REDUCE_ADD, ISD::VP_REDUCE_AND,
- ISD::VP_REDUCE_OR, ISD::VP_REDUCE_XOR, ISD::VP_REDUCE_SMAX,
- ISD::VP_REDUCE_SMIN, ISD::VP_REDUCE_UMAX, ISD::VP_REDUCE_UMIN,
- ISD::VP_MERGE,
- ISD::EXPERIMENTAL_VP_REVERSE, ISD::EXPERIMENTAL_VP_SPLICE,
- ISD::VP_CTTZ_ELTS, ISD::VP_CTTZ_ELTS_ZERO_POISON};
+ static const unsigned IntegerVPOps[] = {ISD::VP_SDIV,
+ ISD::VP_UDIV,
+ ISD::VP_SREM,
+ ISD::VP_UREM,
+ ISD::VP_REDUCE_ADD,
+ ISD::VP_REDUCE_AND,
+ ISD::VP_REDUCE_OR,
+ ISD::VP_REDUCE_XOR,
+ ISD::VP_REDUCE_SMAX,
+ ISD::VP_REDUCE_SMIN,
+ ISD::VP_REDUCE_UMAX,
+ ISD::VP_REDUCE_UMIN,
+ ISD::VP_MERGE,
+ ISD::EXPERIMENTAL_VP_REVERSE,
+ ISD::EXPERIMENTAL_VP_SPLICE,
+ ISD::VP_CTTZ_ELTS,
+ ISD::VP_CTTZ_ELTS_ZERO_POISON};
static const unsigned FloatingPointVPOps[] = {
ISD::VP_REDUCE_FADD, ISD::VP_REDUCE_SEQ_FADD,
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 81deed7da..62881c733 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -4434,110 +4434,112 @@ X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
{ ISD::CTPOP, MVT::i16, { 1, 1, 2, 2 } }, // popcnt(zext())
{ ISD::CTPOP, MVT::i8, { 1, 1, 2, 2 } }, // popcnt(zext())
};
- static const CostKindTblEntry X64CostTbl[] = { // 64-bit targets
- { ISD::ABS, MVT::i64, { 1, 2, 3, 3 } }, // SUB+CMOV
- { ISD::BITREVERSE, MVT::i64, { 10, 12, 20, 22 } },
- { ISD::BSWAP, MVT::i64, { 1, 2, 1, 2 } },
- { ISD::CTLZ, MVT::i64, { 1, 2, 3, 3 } }, // MOV+BSR+XOR
- { ISD::CTLZ, MVT::i32, { 1, 2, 3, 3 } }, // MOV+BSR+XOR
- { ISD::CTLZ, MVT::i16, { 2, 2, 3, 3 } }, // MOV+BSR+XOR
- { ISD::CTLZ, MVT::i8, { 2, 2, 4, 3 } }, // MOV+BSR+XOR
- { ISD::CTLZ_ZERO_POISON,MVT::i64,{ 1, 2, 2, 2 } }, // BSR+XOR
- { ISD::CTTZ, MVT::i64, { 1, 2, 2, 2 } }, // MOV+BSF
- { ISD::CTTZ, MVT::i32, { 1, 2, 2, 2 } }, // MOV+BSF
- { ISD::CTTZ, MVT::i16, { 2, 2, 2, 2 } }, // MOV+BSF
- { ISD::CTTZ, MVT::i8, { 2, 2, 2, 2 } }, // MOV+BSF
- { ISD::CTTZ_ZERO_POISON,MVT::i64,{ 1, 2, 1, 2 } }, // BSF
- { ISD::CTPOP, MVT::i64, { 10, 6, 19, 19 } },
- { ISD::ROTL, MVT::i64, { 2, 3, 1, 3 } },
- { ISD::ROTR, MVT::i64, { 2, 3, 1, 3 } },
- { X86ISD::VROTLI, MVT::i64, { 1, 1, 1, 1 } },
- { ISD::FSHL, MVT::i64, { 4, 4, 1, 4 } },
- { ISD::SADDSAT, MVT::i64, { 4, 4, 7, 10 } },
- { ISD::SSUBSAT, MVT::i64, { 4, 5, 8, 11 } },
- { ISD::UADDSAT, MVT::i64, { 2, 3, 4, 7 } },
- { ISD::USUBSAT, MVT::i64, { 2, 3, 4, 7 } },
- { ISD::SMAX, MVT::i64, { 1, 3, 2, 3 } },
- { ISD::SMIN, MVT::i64, { 1, 3, 2, 3 } },
- { ISD::UMAX, MVT::i64, { 1, 3, 2, 3 } },
- { ISD::UMIN, MVT::i64, { 1, 3, 2, 3 } },
- { ISD::SADDO, MVT::i64, { 2, 2, 4, 6 } },
- { ISD::UADDO, MVT::i64, { 2, 2, 4, 6 } },
- { ISD::SMULO, MVT::i64, { 4, 4, 4, 6 } },
- { ISD::UMULO, MVT::i64, { 8, 8, 4, 7 } },
+ static const CostKindTblEntry X64CostTbl[] = {
+ // 64-bit targets
+ {ISD::ABS, MVT::i64, {1, 2, 3, 3}}, // SUB+CMOV
+ {ISD::BITREVERSE, MVT::i64, {10, 12, 20, 22}},
+ {ISD::BSWAP, MVT::i64, {1, 2, 1, 2}},
+ {ISD::CTLZ, MVT::i64, {1, 2, 3, 3}}, // MOV+BSR+XOR
+ {ISD::CTLZ, MVT::i32, {1, 2, 3, 3}}, // MOV+BSR+XOR
+ {ISD::CTLZ, MVT::i16, {2, 2, 3, 3}}, // MOV+BSR+XOR
+ {ISD::CTLZ, MVT::i8, {2, 2, 4, 3}}, // MOV+BSR+XOR
+ {ISD::CTLZ_ZERO_POISON, MVT::i64, {1, 2, 2, 2}}, // BSR+XOR
+ {ISD::CTTZ, MVT::i64, {1, 2, 2, 2}}, // MOV+BSF
+ {ISD::CTTZ, MVT::i32, {1, 2, 2, 2}}, // MOV+BSF
+ {ISD::CTTZ, MVT::i16, {2, 2, 2, 2}}, // MOV+BSF
+ {ISD::CTTZ, MVT::i8, {2, 2, 2, 2}}, // MOV+BSF
+ {ISD::CTTZ_ZERO_POISON, MVT::i64, {1, 2, 1, 2}}, // BSF
+ {ISD::CTPOP, MVT::i64, {10, 6, 19, 19}},
+ {ISD::ROTL, MVT::i64, {2, 3, 1, 3}},
+ {ISD::ROTR, MVT::i64, {2, 3, 1, 3}},
+ {X86ISD::VROTLI, MVT::i64, {1, 1, 1, 1}},
+ {ISD::FSHL, MVT::i64, {4, 4, 1, 4}},
+ {ISD::SADDSAT, MVT::i64, {4, 4, 7, 10}},
+ {ISD::SSUBSAT, MVT::i64, {4, 5, 8, 11}},
+ {ISD::UADDSAT, MVT::i64, {2, 3, 4, 7}},
+ {ISD::USUBSAT, MVT::i64, {2, 3, 4, 7}},
+ {ISD::SMAX, MVT::i64, {1, 3, 2, 3}},
+ {ISD::SMIN, MVT::i64, {1, 3, 2, 3}},
+ {ISD::UMAX, MVT::i64, {1, 3, 2, 3}},
+ {ISD::UMIN, MVT::i64, {1, 3, 2, 3}},
+ {ISD::SADDO, MVT::i64, {2, 2, 4, 6}},
+ {ISD::UADDO, MVT::i64, {2, 2, 4, 6}},
+ {ISD::SMULO, MVT::i64, {4, 4, 4, 6}},
+ {ISD::UMULO, MVT::i64, {8, 8, 4, 7}},
};
- static const CostKindTblEntry X86CostTbl[] = { // 32 or 64-bit targets
- { ISD::ABS, MVT::i32, { 1, 2, 3, 3 } }, // SUB+XOR+SRA or SUB+CMOV
- { ISD::ABS, MVT::i16, { 2, 2, 3, 3 } }, // SUB+XOR+SRA or SUB+CMOV
- { ISD::ABS, MVT::i8, { 2, 4, 4, 3 } }, // SUB+XOR+SRA
- { ISD::BITREVERSE, MVT::i32, { 9, 12, 17, 19 } },
- { ISD::BITREVERSE, MVT::i16, { 9, 12, 17, 19 } },
- { ISD::BITREVERSE, MVT::i8, { 7, 9, 13, 14 } },
- { ISD::BSWAP, MVT::i32, { 1, 1, 1, 1 } },
- { ISD::BSWAP, MVT::i16, { 1, 2, 1, 2 } }, // ROL
- { ISD::CTLZ, MVT::i32, { 2, 2, 4, 5 } }, // BSR+XOR or BSR+XOR+CMOV
- { ISD::CTLZ, MVT::i16, { 2, 2, 4, 5 } }, // BSR+XOR or BSR+XOR+CMOV
- { ISD::CTLZ, MVT::i8, { 2, 2, 5, 6 } }, // BSR+XOR or BSR+XOR+CMOV
- { ISD::CTLZ_ZERO_POISON,MVT::i32,{ 1, 2, 2, 2 } }, // BSR+XOR
- { ISD::CTLZ_ZERO_POISON,MVT::i16,{ 2, 2, 2, 2 } }, // BSR+XOR
- { ISD::CTLZ_ZERO_POISON,MVT::i8, { 2, 2, 3, 3 } }, // BSR+XOR
- { ISD::CTTZ, MVT::i32, { 2, 2, 3, 3 } }, // TEST+BSF+CMOV/BRANCH
- { ISD::CTTZ, MVT::i16, { 2, 2, 2, 3 } }, // TEST+BSF+CMOV/BRANCH
- { ISD::CTTZ, MVT::i8, { 2, 2, 2, 3 } }, // TEST+BSF+CMOV/BRANCH
- { ISD::CTTZ_ZERO_POISON,MVT::i32,{ 1, 2, 1, 2 } }, // BSF
- { ISD::CTTZ_ZERO_POISON,MVT::i16,{ 2, 2, 1, 2 } }, // BSF
- { ISD::CTTZ_ZERO_POISON,MVT::i8, { 2, 2, 1, 2 } }, // BSF
- { ISD::CTPOP, MVT::i32, { 8, 7, 15, 15 } },
- { ISD::CTPOP, MVT::i16, { 9, 8, 17, 17 } },
- { ISD::CTPOP, MVT::i8, { 7, 6, 6, 6 } },
- { ISD::ROTL, MVT::i32, { 2, 3, 1, 3 } },
- { ISD::ROTL, MVT::i16, { 2, 3, 1, 3 } },
- { ISD::ROTL, MVT::i8, { 2, 3, 1, 3 } },
- { ISD::ROTR, MVT::i32, { 2, 3, 1, 3 } },
- { ISD::ROTR, MVT::i16, { 2, 3, 1, 3 } },
- { ISD::ROTR, MVT::i8, { 2, 3, 1, 3 } },
- { X86ISD::VROTLI, MVT::i32, { 1, 1, 1, 1 } },
- { X86ISD::VROTLI, MVT::i16, { 1, 1, 1, 1 } },
- { X86ISD::VROTLI, MVT::i8, { 1, 1, 1, 1 } },
- { ISD::FSHL, MVT::i32, { 4, 4, 1, 4 } },
- { ISD::FSHL, MVT::i16, { 4, 4, 2, 5 } },
- { ISD::FSHL, MVT::i8, { 4, 4, 2, 5 } },
- { ISD::SADDSAT, MVT::i32, { 3, 4, 6, 9 } },
- { ISD::SADDSAT, MVT::i16, { 4, 4, 7, 10 } },
- { ISD::SADDSAT, MVT::i8, { 4, 5, 8, 11 } },
- { ISD::SSUBSAT, MVT::i32, { 4, 4, 7, 10 } },
- { ISD::SSUBSAT, MVT::i16, { 4, 4, 7, 10 } },
- { ISD::SSUBSAT, MVT::i8, { 4, 5, 8, 11 } },
- { ISD::UADDSAT, MVT::i32, { 2, 3, 4, 7 } },
- { ISD::UADDSAT, MVT::i16, { 2, 3, 4, 7 } },
- { ISD::UADDSAT, MVT::i8, { 3, 3, 5, 8 } },
- { ISD::USUBSAT, MVT::i32, { 2, 3, 4, 7 } },
- { ISD::USUBSAT, MVT::i16, { 2, 3, 4, 7 } },
- { ISD::USUBSAT, MVT::i8, { 3, 3, 5, 8 } },
- { ISD::SMAX, MVT::i32, { 1, 2, 2, 3 } },
- { ISD::SMAX, MVT::i16, { 1, 4, 2, 4 } },
- { ISD::SMAX, MVT::i8, { 1, 4, 2, 4 } },
- { ISD::SMIN, MVT::i32, { 1, 2, 2, 3 } },
- { ISD::SMIN, MVT::i16, { 1, 4, 2, 4 } },
- { ISD::SMIN, MVT::i8, { 1, 4, 2, 4 } },
- { ISD::UMAX, MVT::i32, { 1, 2, 2, 3 } },
- { ISD::UMAX, MVT::i16, { 1, 4, 2, 4 } },
- { ISD::UMAX, MVT::i8, { 1, 4, 2, 4 } },
- { ISD::UMIN, MVT::i32, { 1, 2, 2, 3 } },
- { ISD::UMIN, MVT::i16, { 1, 4, 2, 4 } },
- { ISD::UMIN, MVT::i8, { 1, 4, 2, 4 } },
- { ISD::SADDO, MVT::i32, { 2, 2, 4, 6 } },
- { ISD::SADDO, MVT::i16, { 2, 2, 4, 6 } },
- { ISD::SADDO, MVT::i8, { 2, 2, 4, 6 } },
- { ISD::UADDO, MVT::i32, { 2, 2, 4, 6 } },
- { ISD::UADDO, MVT::i16, { 2, 2, 4, 6 } },
- { ISD::UADDO, MVT::i8, { 2, 2, 4, 6 } },
- { ISD::SMULO, MVT::i32, { 2, 2, 4, 6 } },
- { ISD::SMULO, MVT::i16, { 5, 5, 4, 6 } },
- { ISD::SMULO, MVT::i8, { 6, 6, 4, 6 } },
- { ISD::UMULO, MVT::i32, { 6, 6, 4, 8 } },
- { ISD::UMULO, MVT::i16, { 6, 6, 4, 9 } },
- { ISD::UMULO, MVT::i8, { 6, 6, 4, 6 } },
+ static const CostKindTblEntry X86CostTbl[] = {
+ // 32 or 64-bit targets
+ {ISD::ABS, MVT::i32, {1, 2, 3, 3}}, // SUB+XOR+SRA or SUB+CMOV
+ {ISD::ABS, MVT::i16, {2, 2, 3, 3}}, // SUB+XOR+SRA or SUB+CMOV
+ {ISD::ABS, MVT::i8, {2, 4, 4, 3}}, // SUB+XOR+SRA
+ {ISD::BITREVERSE, MVT::i32, {9, 12, 17, 19}},
+ {ISD::BITREVERSE, MVT::i16, {9, 12, 17, 19}},
+ {ISD::BITREVERSE, MVT::i8, {7, 9, 13, 14}},
+ {ISD::BSWAP, MVT::i32, {1, 1, 1, 1}},
+ {ISD::BSWAP, MVT::i16, {1, 2, 1, 2}}, // ROL
+ {ISD::CTLZ, MVT::i32, {2, 2, 4, 5}}, // BSR+XOR or BSR+XOR+CMOV
+ {ISD::CTLZ, MVT::i16, {2, 2, 4, 5}}, // BSR+XOR or BSR+XOR+CMOV
+ {ISD::CTLZ, MVT::i8, {2, 2, 5, 6}}, // BSR+XOR or BSR+XOR+CMOV
+ {ISD::CTLZ_ZERO_POISON, MVT::i32, {1, 2, 2, 2}}, // BSR+XOR
+ {ISD::CTLZ_ZERO_POISON, MVT::i16, {2, 2, 2, 2}}, // BSR+XOR
+ {ISD::CTLZ_ZERO_POISON, MVT::i8, {2, 2, 3, 3}}, // BSR+XOR
+ {ISD::CTTZ, MVT::i32, {2, 2, 3, 3}}, // TEST+BSF+CMOV/BRANCH
+ {ISD::CTTZ, MVT::i16, {2, 2, 2, 3}}, // TEST+BSF+CMOV/BRANCH
+ {ISD::CTTZ, MVT::i8, {2, 2, 2, 3}}, // TEST+BSF+CMOV/BRANCH
+ {ISD::CTTZ_ZERO_POISON, MVT::i32, {1, 2, 1, 2}}, // BSF
+ {ISD::CTTZ_ZERO_POISON, MVT::i16, {2, 2, 1, 2}}, // BSF
+ {ISD::CTTZ_ZERO_POISON, MVT::i8, {2, 2, 1, 2}}, // BSF
+ {ISD::CTPOP, MVT::i32, {8, 7, 15, 15}},
+ {ISD::CTPOP, MVT::i16, {9, 8, 17, 17}},
+ {ISD::CTPOP, MVT::i8, {7, 6, 6, 6}},
+ {ISD::ROTL, MVT::i32, {2, 3, 1, 3}},
+ {ISD::ROTL, MVT::i16, {2, 3, 1, 3}},
+ {ISD::ROTL, MVT::i8, {2, 3, 1, 3}},
+ {ISD::ROTR, MVT::i32, {2, 3, 1, 3}},
+ {ISD::ROTR, MVT::i16, {2, 3, 1, 3}},
+ {ISD::ROTR, MVT::i8, {2, 3, 1, 3}},
+ {X86ISD::VROTLI, MVT::i32, {1, 1, 1, 1}},
+ {X86ISD::VROTLI, MVT::i16, {1, 1, 1, 1}},
+ {X86ISD::VROTLI, MVT::i8, {1, 1, 1, 1}},
+ {ISD::FSHL, MVT::i32, {4, 4, 1, 4}},
+ {ISD::FSHL, MVT::i16, {4, 4, 2, 5}},
+ {ISD::FSHL, MVT::i8, {4, 4, 2, 5}},
+ {ISD::SADDSAT, MVT::i32, {3, 4, 6, 9}},
+ {ISD::SADDSAT, MVT::i16, {4, 4, 7, 10}},
+ {ISD::SADDSAT, MVT::i8, {4, 5, 8, 11}},
+ {ISD::SSUBSAT, MVT::i32, {4, 4, 7, 10}},
+ {ISD::SSUBSAT, MVT::i16, {4, 4, 7, 10}},
+ {ISD::SSUBSAT, MVT::i8, {4, 5, 8, 11}},
+ {ISD::UADDSAT, MVT::i32, {2, 3, 4, 7}},
+ {ISD::UADDSAT, MVT::i16, {2, 3, 4, 7}},
+ {ISD::UADDSAT, MVT::i8, {3, 3, 5, 8}},
+ {ISD::USUBSAT, MVT::i32, {2, 3, 4, 7}},
+ {ISD::USUBSAT, MVT::i16, {2, 3, 4, 7}},
+ {ISD::USUBSAT, MVT::i8, {3, 3, 5, 8}},
+ {ISD::SMAX, MVT::i32, {1, 2, 2, 3}},
+ {ISD::SMAX, MVT::i16, {1, 4, 2, 4}},
+ {ISD::SMAX, MVT::i8, {1, 4, 2, 4}},
+ {ISD::SMIN, MVT::i32, {1, 2, 2, 3}},
+ {ISD::SMIN, MVT::i16, {1, 4, 2, 4}},
+ {ISD::SMIN, MVT::i8, {1, 4, 2, 4}},
+ {ISD::UMAX, MVT::i32, {1, 2, 2, 3}},
+ {ISD::UMAX, MVT::i16, {1, 4, 2, 4}},
+ {ISD::UMAX, MVT::i8, {1, 4, 2, 4}},
+ {ISD::UMIN, MVT::i32, {1, 2, 2, 3}},
+ {ISD::UMIN, MVT::i16, {1, 4, 2, 4}},
+ {ISD::UMIN, MVT::i8, {1, 4, 2, 4}},
+ {ISD::SADDO, MVT::i32, {2, 2, 4, 6}},
+ {ISD::SADDO, MVT::i16, {2, 2, 4, 6}},
+ {ISD::SADDO, MVT::i8, {2, 2, 4, 6}},
+ {ISD::UADDO, MVT::i32, {2, 2, 4, 6}},
+ {ISD::UADDO, MVT::i16, {2, 2, 4, 6}},
+ {ISD::UADDO, MVT::i8, {2, 2, 4, 6}},
+ {ISD::SMULO, MVT::i32, {2, 2, 4, 6}},
+ {ISD::SMULO, MVT::i16, {5, 5, 4, 6}},
+ {ISD::SMULO, MVT::i8, {6, 6, 4, 6}},
+ {ISD::UMULO, MVT::i32, {6, 6, 4, 8}},
+ {ISD::UMULO, MVT::i16, {6, 6, 4, 9}},
+ {ISD::UMULO, MVT::i8, {6, 6, 4, 6}},
};
Type *RetTy = ICA.getReturnType();
@@ -4701,8 +4703,8 @@ X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
const SmallVectorImpl<const Value *> &Args = ICA.getArgs();
if (auto *Cst = dyn_cast<ConstantInt>(Args[1]))
if (Cst->isAllOnesValue())
- ISD = ISD == ISD::CTTZ ? ISD::CTTZ_ZERO_POISON
- : ISD::CTLZ_ZERO_POISON;
+ ISD =
+ ISD == ISD::CTTZ ? ISD::CTTZ_ZERO_POISON : ISD::CTLZ_ZERO_POISON;
}
// FSQRT is a single instruction.
``````````
</details>
https://github.com/llvm/llvm-project/pull/196732
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