[llvm] [DAG][GISel] Rename CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF/CTTZ_ELTS_ZERO_UNDEF -> CTTZ_ZERO_POISON/CTLZ_ZERO_POISON/CTTZ_ELTS_ZERO_POISON (PR #196732)
via llvm-commits
llvm-commits at lists.llvm.org
Sat May 9 08:05:06 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-sparc
Author: Simon Pilgrim (RKSimon)
<details>
<summary>Changes</summary>
DAG/GISel are ambiguous about whether zero-input results in UNDEF/POISON, unlike the rest of LLVM which makes it clear its poison.
I've tried to clean this up once and for all by ensuring SelectionDAG::canCreateUndefOrPoison does a includesPoison(Kind) check, renaming the opcodes (including the VP variants) and updating as many comments/tests as possible (I may still have missed some...).
If people prefer I can look at doing this in smaller stages, but I'd prefer to remove as much ambiguity as possible in one patch.
---
Patch is 662.03 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/196732.diff
123 Files Affected:
- (modified) llvm/docs/GlobalISel/GenericOpcode.rst (+7-7)
- (modified) llvm/docs/ReleaseNotes.md (+14)
- (modified) llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h (+1-1)
- (modified) llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h (+8-6)
- (modified) llvm/include/llvm/CodeGen/GlobalISel/Utils.h (+1-1)
- (modified) llvm/include/llvm/CodeGen/ISDOpcodes.h (+3-3)
- (modified) llvm/include/llvm/CodeGen/TargetLowering.h (+5-5)
- (modified) llvm/include/llvm/IR/VPIntrinsics.def (+7-7)
- (modified) llvm/include/llvm/Support/TargetOpcodes.def (+4-4)
- (modified) llvm/include/llvm/Target/GenericOpcodes.td (+2-2)
- (modified) llvm/include/llvm/Target/GlobalISel/Combine.td (+3-3)
- (modified) llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td (+2-2)
- (modified) llvm/include/llvm/Target/TargetSelectionDAG.td (+2-2)
- (modified) llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp (+2-2)
- (modified) llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp (+1-1)
- (modified) llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp (+2-2)
- (modified) llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp (+5-5)
- (modified) llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (+33-35)
- (modified) llvm/lib/CodeGen/GlobalISel/Utils.cpp (+2-2)
- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+31-31)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (+10-10)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (+15-15)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (+6-6)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (+13-13)
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (+10-9)
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (+8-8)
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp (+2-2)
- (modified) llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (+13-13)
- (modified) llvm/lib/CodeGen/TargetLoweringBase.cpp (+1-1)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp (+2-2)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp (+20-20)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td (+2-2)
- (modified) llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (+8-8)
- (modified) llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h (+2-2)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp (+5-5)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp (+2-2)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (+11-11)
- (modified) llvm/lib/Target/AMDGPU/R600ISelLowering.cpp (+2-2)
- (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+4-4)
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+11-11)
- (modified) llvm/lib/Target/ARM/ARMLegalizerInfo.cpp (+2-2)
- (modified) llvm/lib/Target/BPF/BPFISelLowering.cpp (+2-2)
- (modified) llvm/lib/Target/Mips/MipsLegalizerInfo.cpp (+2-2)
- (modified) llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp (+1-1)
- (modified) llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp (+4-4)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+31-31)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.h (+1-1)
- (modified) llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp (+2-2)
- (modified) llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp (+1-1)
- (modified) llvm/lib/Target/Sparc/SparcISelLowering.cpp (+12-12)
- (modified) llvm/lib/Target/Sparc/SparcInstrVIS.td (+2-2)
- (modified) llvm/lib/Target/SystemZ/SystemZISelLowering.cpp (+2-2)
- (modified) llvm/lib/Target/VE/VEISelLowering.cpp (+1-1)
- (modified) llvm/lib/Target/VE/VEInstrInfo.td (+1-1)
- (modified) llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp (+1-1)
- (modified) llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp (+1-1)
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+28-28)
- (modified) llvm/lib/Target/X86/X86InstrCompiler.td (+7-7)
- (modified) llvm/lib/Target/X86/X86TargetTransformInfo.cpp (+11-10)
- (modified) llvm/lib/Target/Xtensa/XtensaISelLowering.cpp (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (+3-3)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-unary-int.mir (+6-6)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir (+7-7)
- (renamed) llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz-zero-poison.mir (+4-4)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir (+2-2)
- (renamed) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-poison.mir (+12-12)
- (renamed) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-poison.mir (+12-12)
- (renamed) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-poison.mir (+46-46)
- (renamed) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-poison.mir (+54-54)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir (+10-10)
- (renamed) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir (+18-18)
- (renamed) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir (+18-18)
- (modified) llvm/test/CodeGen/AMDGPU/ctls.ll (+8-8)
- (renamed) llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll (+170-170)
- (renamed) llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll (+60-60)
- (modified) llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir (+9-9)
- (modified) llvm/test/CodeGen/ARM/cttz.ll (+20-20)
- (modified) llvm/test/CodeGen/ARM/cttz_vector.ll (+28-28)
- (modified) llvm/test/CodeGen/Lanai/i32.ll (+4-4)
- (modified) llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir (+2-2)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir (+2-2)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv32.mir (+16-16)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir (+16-16)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv32.mir (+16-16)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir (+16-16)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll (+3-3)
- (modified) llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll (+64-64)
- (modified) llvm/test/CodeGen/RISCV/rv64xtheadbb.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rv64zbb.ll (+3-3)
- (modified) llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll (+108-108)
- (modified) llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll (+153-153)
- (modified) llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll (+108-108)
- (modified) llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll (+147-147)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll (+72-72)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll (+42-42)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll (+72-72)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll (+42-42)
- (modified) llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll (+32-32)
- (modified) llvm/test/CodeGen/SystemZ/vec-ctlz-01.ll (+4-4)
- (modified) llvm/test/CodeGen/SystemZ/vec-cttz-01.ll (+4-4)
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir (+9-9)
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir (+9-9)
- (modified) llvm/test/CodeGen/WebAssembly/i128.ll (+6-6)
- (modified) llvm/test/CodeGen/WebAssembly/i32.ll (+6-6)
- (modified) llvm/test/CodeGen/WebAssembly/i64.ll (+6-6)
- (modified) llvm/test/CodeGen/X86/GlobalISel/legalize-leading-zeros.mir (+5-5)
- (renamed) llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-poison.mir (+22-22)
- (modified) llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir (+10-10)
- (modified) llvm/test/CodeGen/X86/bitcnt-big-integer.ll (+135-135)
- (modified) llvm/test/CodeGen/X86/freeze-unary.ll (+18-18)
- (modified) llvm/test/CodeGen/X86/known-never-zero.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/widen_bitcnt.ll (+29-29)
- (modified) llvm/test/CodeGen/Xtensa/ctlz-cttz-ctpop.ll (+4-4)
- (modified) llvm/test/Transforms/InstCombine/X86/x86-sse4a-inseltpoison.ll (+1-1)
- (modified) llvm/test/Transforms/InstCombine/add2.ll (+2-2)
- (modified) llvm/test/Transforms/InstCombine/cttz.ll (+12-12)
- (modified) llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll (+1-1)
- (modified) llvm/test/Transforms/InstCombine/umin_cttz_ctlz.ll (+54-54)
- (modified) llvm/test/Transforms/SLPVectorizer/X86/ctlz.ll (+31-31)
- (modified) llvm/test/Transforms/SLPVectorizer/X86/cttz.ll (+31-31)
- (modified) llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp (+32-32)
- (modified) llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp (+4-4)
``````````diff
diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst
index f9872c8926d6d..d212b39720c5a 100644
--- a/llvm/docs/GlobalISel/GenericOpcode.rst
+++ b/llvm/docs/GlobalISel/GenericOpcode.rst
@@ -486,20 +486,20 @@ Count leading zeros, trailing zeros, or number of set bits.
.. code-block:: none
- %2:_(s33) = G_CTLZ_ZERO_UNDEF %1
- %2:_(s33) = G_CTTZ_ZERO_UNDEF %1
+ %2:_(s33) = G_CTLZ_ZERO_POISON %1
+ %2:_(s33) = G_CTTZ_ZERO_POISON %1
%2:_(s33) = G_CTPOP %1
-G_CTLZ_ZERO_UNDEF, G_CTTZ_ZERO_UNDEF
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+G_CTLZ_ZERO_POISON, G_CTTZ_ZERO_POISON
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Count leading zeros or trailing zeros. If the value is zero then the result is
-undefined.
+poison.
.. code-block:: none
- %2:_(s33) = G_CTLZ_ZERO_UNDEF %1
- %2:_(s33) = G_CTTZ_ZERO_UNDEF %1
+ %2:_(s33) = G_CTLZ_ZERO_POISON %1
+ %2:_(s33) = G_CTTZ_ZERO_POISON %1
G_CTLS
^^^^^^
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 98f2205bc06a7..7363c2fd8c52b 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -231,6 +231,20 @@ Makes programs 10x faster by doing Special New Thing.
### Changes to the CodeGen infrastructure
+* Renamed ISD::CTLZ_ZERO_UNDEF to ISD::CTLZ_ZERO_POISON opcode to make it clear that
+ a zero input results in poison.
+
+* Renamed ISD::CTTZ_ZERO_UNDEF to ISD::CTTZ_ZERO_POISON opcode to make it clear that
+ a zero input results in poison.
+
+### Changes to the GlobalISel infrastructure
+
+* Renamed G_CTLZ_ZERO_UNDEF to G_CTLZ_ZERO_POISON opcode to make it clear that
+ a zero input results in poison.
+
+* Renamed G_CTTZ_ZERO_UNDEF to G_CTTZ_ZERO_POISON opcode to make it clear that
+ a zero input results in poison.
+
### Changes to the Metadata Info
### Changes to the Debug Info
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
index 97f29015c6911..3687adbe60f1a 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
@@ -410,7 +410,7 @@ class CombinerHelper {
const ConstantFP *Cst) const;
/// Constant fold a unary integer op (G_CTLZ, G_CTTZ, G_CTPOP and their
- /// _ZERO_UNDEF variants, G_ABS, G_BSWAP, G_BITREVERSE) when the operand is
+ /// _ZERO_POISON variants, G_ABS, G_BSWAP, G_BITREVERSE) when the operand is
/// a scalar constant or a G_BUILD_VECTOR of constants.
bool matchConstantFoldUnaryIntOp(MachineInstr &MI,
BuildFnTy &MatchInfo) const;
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index c7973a8a9fb00..511bc17161e03 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -2061,9 +2061,10 @@ class LLVM_ABI MachineIRBuilder {
return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0});
}
- /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0
- MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) {
- return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0});
+ /// Build and insert \p Res = G_CTLZ_ZERO_POISON \p Op0, \p Src0
+ MachineInstrBuilder buildCTLZ_ZERO_POISON(const DstOp &Dst,
+ const SrcOp &Src0) {
+ return buildInstr(TargetOpcode::G_CTLZ_ZERO_POISON, {Dst}, {Src0});
}
/// Build and insert \p Res = G_CTTZ \p Op0, \p Src0
@@ -2071,9 +2072,10 @@ class LLVM_ABI MachineIRBuilder {
return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0});
}
- /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0
- MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) {
- return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
+ /// Build and insert \p Res = G_CTTZ_ZERO_POISON \p Op0, \p Src0
+ MachineInstrBuilder buildCTTZ_ZERO_POISON(const DstOp &Dst,
+ const SrcOp &Src0) {
+ return buildInstr(TargetOpcode::G_CTTZ_ZERO_POISON, {Dst}, {Src0});
}
/// Build and insert \p Res = G_CTLS \p Op0, \p Src0
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
index a861a60ecfcd3..a78bbe80b2f61 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
@@ -320,7 +320,7 @@ ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src,
const MachineRegisterInfo &MRI);
/// Tries to constant fold a unary integer operation (G_CTLZ, G_CTTZ, G_CTPOP
-/// and their _ZERO_UNDEF variants, G_ABS, G_BSWAP, G_BITREVERSE) on \p Src.
+/// and their _ZERO_POISON variants, G_ABS, G_BSWAP, G_BITREVERSE) on \p Src.
/// If \p Src is a vector then it tries to do an element-wise constant fold.
LLVM_ABI SmallVector<APInt>
ConstantFoldUnaryIntOp(unsigned Opcode, LLT DstTy, Register Src,
diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h
index 8a8a9ee71ca02..7dc57d9f32c87 100644
--- a/llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -783,9 +783,9 @@ enum NodeType {
BITREVERSE,
PARITY,
- /// Bit counting operators with an undefined result for zero inputs.
- CTTZ_ZERO_UNDEF,
- CTLZ_ZERO_UNDEF,
+ /// Bit counting operators with an poisoned result for zero inputs.
+ CTTZ_ZERO_POISON,
+ CTLZ_ZERO_POISON,
/// Count leading redundant sign bits. Equivalent to
/// (sub (ctlz (x < 0 ? ~x : x)), 1).
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index f1119e4acce58..318763113fb42 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -5663,13 +5663,13 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
/// \returns The expansion result or SDValue() if it fails.
SDValue expandVPCTPOP(SDNode *N, SelectionDAG &DAG) const;
- /// Expand CTLZ/CTLZ_ZERO_UNDEF nodes. Expands vector/scalar CTLZ nodes,
+ /// Expand CTLZ/CTLZ_ZERO_POISON nodes. Expands vector/scalar CTLZ nodes,
/// vector nodes can only succeed if all operations are legal/custom.
/// \param N Node to expand
/// \returns The expansion result or SDValue() if it fails.
SDValue expandCTLZ(SDNode *N, SelectionDAG &DAG) const;
- /// Expand VP_CTLZ/VP_CTLZ_ZERO_UNDEF nodes.
+ /// Expand VP_CTLZ/VP_CTLZ_ZERO_POISON nodes.
/// \param N Node to expand
/// \returns The expansion result or SDValue() if it fails.
SDValue expandVPCTLZ(SDNode *N, SelectionDAG &DAG) const;
@@ -5686,18 +5686,18 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
SDValue CTTZTableLookup(SDNode *N, SelectionDAG &DAG, const SDLoc &DL, EVT VT,
SDValue Op, unsigned NumBitsPerElt) const;
- /// Expand CTTZ/CTTZ_ZERO_UNDEF nodes. Expands vector/scalar CTTZ nodes,
+ /// Expand CTTZ/CTTZ_ZERO_POISON nodes. Expands vector/scalar CTTZ nodes,
/// vector nodes can only succeed if all operations are legal/custom.
/// \param N Node to expand
/// \returns The expansion result or SDValue() if it fails.
SDValue expandCTTZ(SDNode *N, SelectionDAG &DAG) const;
- /// Expand VP_CTTZ/VP_CTTZ_ZERO_UNDEF nodes.
+ /// Expand VP_CTTZ/VP_CTTZ_ZERO_POISON nodes.
/// \param N Node to expand
/// \returns The expansion result or SDValue() if it fails.
SDValue expandVPCTTZ(SDNode *N, SelectionDAG &DAG) const;
- /// Expand VP_CTTZ_ELTS/VP_CTTZ_ELTS_ZERO_UNDEF nodes.
+ /// Expand VP_CTTZ_ELTS/VP_CTTZ_ELTS_ZERO_POISON nodes.
/// \param N Node to expand
/// \returns The expansion result or SDValue() if it fails.
SDValue expandVPCTTZElements(SDNode *N, SelectionDAG &DAG) const;
diff --git a/llvm/include/llvm/IR/VPIntrinsics.def b/llvm/include/llvm/IR/VPIntrinsics.def
index 0b0c744487b92..7015bd5a6f0ce 100644
--- a/llvm/include/llvm/IR/VPIntrinsics.def
+++ b/llvm/include/llvm/IR/VPIntrinsics.def
@@ -240,9 +240,9 @@ BEGIN_REGISTER_VP_SDNODE(VP_CTLZ, -1, vp_ctlz, 1, 2)
VP_PROPERTY_FUNCTIONAL_INTRINSIC(ctlz)
VP_PROPERTY_FUNCTIONAL_SDOPC(CTLZ)
END_REGISTER_VP_SDNODE(VP_CTLZ)
-BEGIN_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_UNDEF, -1, vp_ctlz_zero_undef, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(CTLZ_ZERO_UNDEF)
-END_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_UNDEF)
+BEGIN_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_POISON, -1, vp_ctlz_zero_poison, 1, 2)
+VP_PROPERTY_FUNCTIONAL_SDOPC(CTLZ_ZERO_POISON)
+END_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_POISON)
END_REGISTER_VP_INTRINSIC(vp_ctlz)
// llvm.vp.cttz(x,is_zero_poison,mask,vlen)
@@ -251,8 +251,8 @@ BEGIN_REGISTER_VP_SDNODE(VP_CTTZ, -1, vp_cttz, 1, 2)
VP_PROPERTY_FUNCTIONAL_INTRINSIC(cttz)
VP_PROPERTY_FUNCTIONAL_SDOPC(CTTZ)
END_REGISTER_VP_SDNODE(VP_CTTZ)
-BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_UNDEF, -1, vp_cttz_zero_undef, 1, 2)
-END_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_UNDEF)
+BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_POISON, -1, vp_cttz_zero_poison, 1, 2)
+END_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_POISON)
END_REGISTER_VP_INTRINSIC(vp_cttz)
// llvm.vp.cttz.elts(x,is_zero_poison,mask,vl)
@@ -260,8 +260,8 @@ BEGIN_REGISTER_VP_INTRINSIC(vp_cttz_elts, 2, 3)
VP_PROPERTY_NO_FUNCTIONAL
BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ELTS, 0, vp_cttz_elts, 1, 2)
END_REGISTER_VP_SDNODE(VP_CTTZ_ELTS)
-BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ELTS_ZERO_UNDEF, 0, vp_cttz_elts_zero_undef, 1, 2)
-END_REGISTER_VP_SDNODE(VP_CTTZ_ELTS_ZERO_UNDEF)
+BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ELTS_ZERO_POISON, 0, vp_cttz_elts_zero_poison, 1, 2)
+END_REGISTER_VP_SDNODE(VP_CTTZ_ELTS_ZERO_POISON)
END_REGISTER_VP_INTRINSIC(vp_cttz_elts)
// llvm.vp.fshl(x,y,z,mask,vlen)
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index a8db3c1d75aa0..68a80dde6b3fe 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -838,14 +838,14 @@ HANDLE_TARGET_OPCODE(G_VECTOR_COMPRESS)
/// Generic count trailing zeroes.
HANDLE_TARGET_OPCODE(G_CTTZ)
-/// Same as above, undefined for zero inputs.
-HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_UNDEF)
+/// Same as above, poisoned for zero inputs.
+HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_POISON)
/// Generic count leading zeroes.
HANDLE_TARGET_OPCODE(G_CTLZ)
-/// Same as above, undefined for zero inputs.
-HANDLE_TARGET_OPCODE(G_CTLZ_ZERO_UNDEF)
+/// Same as above, poisoned for zero inputs.
+HANDLE_TARGET_OPCODE(G_CTLZ_ZERO_POISON)
/// Generic count extra sign bits.
HANDLE_TARGET_OPCODE(G_CTLS)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index 3612e3c458f90..37a185a226b63 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -202,7 +202,7 @@ def G_CTLZ : GenericInstruction {
let hasSideEffects = false;
}
-def G_CTLZ_ZERO_UNDEF : GenericInstruction {
+def G_CTLZ_ZERO_POISON : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
let hasSideEffects = false;
@@ -214,7 +214,7 @@ def G_CTTZ : GenericInstruction {
let hasSideEffects = false;
}
-def G_CTTZ_ZERO_UNDEF : GenericInstruction {
+def G_CTTZ_ZERO_POISON : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
let hasSideEffects = false;
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 2091554304771..5d9025b5cc9c8 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -1404,7 +1404,7 @@ def constant_fold_cast_op : GICombineRule<
def unary_int_op_frags : GICombinePatFrag<
(outs root:$dst), (ins),
!foreach(op,
- [G_CTLZ, G_CTLZ_ZERO_UNDEF, G_CTTZ, G_CTTZ_ZERO_UNDEF, G_CTPOP,
+ [G_CTLZ, G_CTLZ_ZERO_POISON, G_CTTZ, G_CTTZ_ZERO_POISON, G_CTPOP,
G_ABS, G_BSWAP, G_BITREVERSE],
(pattern (op $dst, $src)))>;
@@ -2230,11 +2230,11 @@ class ctlz_to_ctls_op<Instruction ctlzOpcode> : GICombineRule <
(apply [{Helper.applyBuildFn(*${root}, ${matchinfo});}])>;
def ctlz_to_ctls : ctlz_to_ctls_op<G_CTLZ>;
-def ctlz_zero_undef_to_ctls : ctlz_to_ctls_op<G_CTLZ_ZERO_UNDEF>;
+def ctlz_zero_poison_to_ctls : ctlz_to_ctls_op<G_CTLZ_ZERO_POISON>;
def ctls_combines : GICombineGroup<[
ctlz_to_ctls,
- ctlz_zero_undef_to_ctls,
+ ctlz_zero_poison_to_ctls,
]>;
def narrow_binop_add : narrow_binop_opcode<G_ADD>;
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index abfd41864c8bf..6933176b0fb53 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -157,8 +157,8 @@ def : GINodeEquiv<G_FSHL, fshl>;
def : GINodeEquiv<G_FSHR, fshr>;
def : GINodeEquiv<G_CTLZ, ctlz>;
def : GINodeEquiv<G_CTTZ, cttz>;
-def : GINodeEquiv<G_CTLZ_ZERO_UNDEF, ctlz_zero_undef>;
-def : GINodeEquiv<G_CTTZ_ZERO_UNDEF, cttz_zero_undef>;
+def : GINodeEquiv<G_CTLZ_ZERO_POISON, ctlz_zero_poison>;
+def : GINodeEquiv<G_CTTZ_ZERO_POISON, cttz_zero_poison>;
def : GINodeEquiv<G_CTLS, ctls>;
def : GINodeEquiv<G_CTPOP, ctpop>;
def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, extractelt>;
diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index 573342846b4cf..ec8fbd84d5166 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -535,8 +535,8 @@ def ctlz : SDNode<"ISD::CTLZ" , SDTIntBitCountUnaryOp>;
def cttz : SDNode<"ISD::CTTZ" , SDTIntBitCountUnaryOp>;
def ctpop : SDNode<"ISD::CTPOP" , SDTIntBitCountUnaryOp>;
def ctls : SDNode<"ISD::CTLS" , SDTIntBitCountUnaryOp>;
-def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntBitCountUnaryOp>;
-def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntBitCountUnaryOp>;
+def ctlz_zero_poison : SDNode<"ISD::CTLZ_ZERO_POISON", SDTIntBitCountUnaryOp>;
+def cttz_zero_poison : SDNode<"ISD::CTTZ_ZERO_POISON", SDTIntBitCountUnaryOp>;
def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
diff --git a/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
index ff96d7a3cbd9a..8e5bf2120dd40 100644
--- a/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
@@ -282,9 +282,9 @@ MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc,
break;
}
case TargetOpcode::G_CTLZ:
- case TargetOpcode::G_CTLZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTLZ_ZERO_POISON:
case TargetOpcode::G_CTTZ:
- case TargetOpcode::G_CTTZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTTZ_ZERO_POISON:
case TargetOpcode::G_CTPOP:
case TargetOpcode::G_ABS:
case TargetOpcode::G_BSWAP:
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index c58fb84a3890e..0f2617b9b5b1c 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -8642,7 +8642,7 @@ bool CombinerHelper::matchSuboCarryOut(const MachineInstr &MI,
bool CombinerHelper::matchCtls(MachineInstr &CtlzMI,
BuildFnTy &MatchInfo) const {
assert((CtlzMI.getOpcode() == TargetOpcode::G_CTLZ ||
- CtlzMI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) &&
+ CtlzMI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_POISON) &&
"Expected G_CTLZ variant");
const Register Dst = CtlzMI.getOperand(0).getReg();
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 5fcc84d0d76a1..44298258da11c 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -793,7 +793,7 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
break;
}
case TargetOpcode::G_CTTZ:
- case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
+ case TargetOpcode::G_CTTZ_ZERO_POISON: {
KnownBits SrcOpKnown;
computeKnownBitsImpl(MI.getOperand(1).getReg(), SrcOpKnown, DemandedElts,
Depth + 1);
@@ -804,7 +804,7 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
break;
}
case TargetOpcode::G_CTLZ:
- case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
+ case TargetOpcode::G_CTLZ_ZERO_POISON: {
KnownBits SrcOpKnown;
computeKnownBitsImpl(MI.getOperand(1).getReg(), SrcOpKnown, DemandedElts,
Depth + 1);
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 7db3e2d4e02b7..8c8e08865744a 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -2482,11 +2482,11 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
case Intrinsic::ctlz: {
ConstantInt *Cst = cast<ConstantInt>(CI.getArgOperand(1));
bool isTrailing = ID == Intrinsic::cttz;
- unsigned Opcode = isTrailing
- ? Cst->isZero() ? TargetOpcode::G_CTTZ
- : TargetOpcode::G_CTTZ_ZERO_UNDEF
- : Cst->isZero() ? TargetOpcode::G_CTLZ
- : TargetOpcode::G_CTLZ_ZERO_UNDEF;
+ unsigned Opcode = isTrailing ? Cst->isZero()
+ ? TargetOpcode::G_CTTZ
+ : TargetOpcode::G_CTTZ_ZERO_POISON
+ : Cst->isZero() ? TargetOpcode::G_CTLZ
+ : TargetOpcode::G_CTLZ_ZERO_POISON;
MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(CI)},
{getOrCreateVReg(*CI.getArgOperand(0))});
return true;
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 71cda8a480dd7..909decfb015b5 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -427,7 +427,7 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
RTLIBCASE_INT(SREM_I);
case TargetOpcode::G_UREM:
RTLIBCASE_INT(UREM_I);
- case TargetOpcode::G_CTLZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTLZ_ZERO_POISON:
RTLIBCASE_INT(CTLZ_I);
case TargetOpcode::G_FADD:
RTLIBCASE(ADD_F);
@@ -1318,7 +1318,7 @@ LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) {
case TargetOpcode::G_UDIV:
case TargetOpcode::G_SREM:
case TargetOpcode::G_UREM:
- case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
+ case TargetOpcode::G_CTLZ_ZERO_POISON: {
LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
unsigned Size = LLTy.getSizeInBits();
Type *HLTy = IntegerType::get(Ctx, Size);
@@ -1781,18 +1781,18 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
case TargetOpcode::G_ASHR:
return narrowScalarShift(MI, TypeIdx, NarrowTy);
case TargetOpcode::G_CTLZ:
- case TargetOpcode::G_CTLZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTLZ_ZERO_POISON:
case TargetOpcode::G_CTTZ:
- case TargetOpcode::G_CTTZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTTZ_ZERO_POISON:
case TargetOpcode::G_CTLS:
case TargetOpcode::G_CTPOP:
if (TypeIdx == 1)
switch (MI.getOpcode()) {
case TargetOpcode::G_CTLZ:
- case TargetOpcode::G_CTLZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTLZ_ZERO_POISON:
return narrowScalarCTLZ(MI, TypeIdx, NarrowTy);
case TargetOpcode::G_CTTZ:
- case TargetOpcode::G_CTTZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTTZ_ZERO_POISON:
return narrowScalarCTTZ(MI, TypeIdx, NarrowTy);
case TargetOpcode::G_CTPOP:
return narrowScalarCTPOP(MI, TypeIdx, NarrowTy);
@@ -2822,9 +2822,9 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
case TargetOpcode::G_USHLSAT:
return widenScalarAddSubShlSat(...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/196732
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