[llvm] [DAG][GISel] Rename CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF/CTTZ_ELTS_ZERO_UNDEF -> CTTZ_ZERO_POISON/CTLZ_ZERO_POISON/CTTZ_ELTS_ZERO_POISON (PR #196732)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat May 9 08:04:28 PDT 2026
https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/196732
DAG/GISel are ambiguous about whether zero-input results in UNDEF/POISON, unlike the rest of LLVM which makes it clear its poison.
I've tried to clean this up once and for all by ensuring SelectionDAG::canCreateUndefOrPoison does a includesPoison(Kind) check, renaming the opcodes (including the VP variants) and updating as many comments/tests as possible (I may still have missed some...).
If people prefer I can look at doing this in smaller stages, but I'd prefer to remove as much ambiguity as possible in one patch.
>From 6bce55ea70199a8952971296a4b8a38c36537acb Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Sat, 9 May 2026 16:01:49 +0100
Subject: [PATCH] [DAG][GISel] Renaname
CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF/CTTZ_ELTS_ZERO_UNDEF ->
CTTZ_ZERO_POISON/CTLZ_ZERO_POISON/CTTZ_ELTS_ZERO_POISON
DAG/GISel are ambiguous about whether zero-input results in UNDEF/POISON, unlike the rest of LLVM which makes it clear its poison.
I've tried to clean this up once and for all by ensuring canCreateUndefOrPoison does a includesPoison(Kind) check, renaming the opcodes (including the VP variants) and updating as many comments/tests as possible (I may still have missed some...).
If people prefer I can look at doing this in smaller stages, but I'd prefer to remove as much ambiguity as possible in one patch.
---
llvm/docs/GlobalISel/GenericOpcode.rst | 14 +-
llvm/docs/ReleaseNotes.md | 14 +
.../llvm/CodeGen/GlobalISel/CombinerHelper.h | 2 +-
.../CodeGen/GlobalISel/MachineIRBuilder.h | 14 +-
llvm/include/llvm/CodeGen/GlobalISel/Utils.h | 2 +-
llvm/include/llvm/CodeGen/ISDOpcodes.h | 6 +-
llvm/include/llvm/CodeGen/TargetLowering.h | 10 +-
llvm/include/llvm/IR/VPIntrinsics.def | 14 +-
llvm/include/llvm/Support/TargetOpcodes.def | 8 +-
llvm/include/llvm/Target/GenericOpcodes.td | 4 +-
.../include/llvm/Target/GlobalISel/Combine.td | 6 +-
.../Target/GlobalISel/SelectionDAGCompat.td | 4 +-
.../include/llvm/Target/TargetSelectionDAG.td | 4 +-
llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp | 4 +-
.../lib/CodeGen/GlobalISel/CombinerHelper.cpp | 2 +-
.../CodeGen/GlobalISel/GISelValueTracking.cpp | 4 +-
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 10 +-
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 68 ++--
llvm/lib/CodeGen/GlobalISel/Utils.cpp | 4 +-
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 62 ++--
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 20 +-
.../SelectionDAG/LegalizeIntegerTypes.cpp | 30 +-
.../SelectionDAG/LegalizeVectorOps.cpp | 12 +-
.../SelectionDAG/LegalizeVectorTypes.cpp | 26 +-
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 19 +-
.../SelectionDAG/SelectionDAGBuilder.cpp | 16 +-
.../SelectionDAG/SelectionDAGDumper.cpp | 4 +-
.../CodeGen/SelectionDAG/TargetLowering.cpp | 26 +-
llvm/lib/CodeGen/TargetLoweringBase.cpp | 2 +-
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 4 +-
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 40 +--
llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td | 4 +-
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 16 +-
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 4 +-
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp | 10 +-
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 4 +-
.../Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 22 +-
llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | 4 +-
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 8 +-
llvm/lib/Target/ARM/ARMISelLowering.cpp | 22 +-
llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | 4 +-
llvm/lib/Target/BPF/BPFISelLowering.cpp | 4 +-
llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 4 +-
llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 2 +-
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 8 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 62 ++--
llvm/lib/Target/RISCV/RISCVISelLowering.h | 2 +-
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 4 +-
llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp | 2 +-
llvm/lib/Target/Sparc/SparcISelLowering.cpp | 24 +-
llvm/lib/Target/Sparc/SparcInstrVIS.td | 4 +-
.../Target/SystemZ/SystemZISelLowering.cpp | 4 +-
llvm/lib/Target/VE/VEISelLowering.cpp | 2 +-
llvm/lib/Target/VE/VEInstrInfo.td | 2 +-
.../GISel/WebAssemblyLegalizerInfo.cpp | 2 +-
.../lib/Target/X86/GISel/X86LegalizerInfo.cpp | 2 +-
llvm/lib/Target/X86/X86ISelLowering.cpp | 56 +--
llvm/lib/Target/X86/X86InstrCompiler.td | 14 +-
.../lib/Target/X86/X86TargetTransformInfo.cpp | 21 +-
llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 4 +-
.../AArch64/GlobalISel/arm64-irtranslator.ll | 6 +-
.../combine-constant-fold-unary-int.mir | 12 +-
.../AArch64/GlobalISel/legalize-ctlz.mir | 14 +-
...ndef.mir => legalize-cttz-zero-poison.mir} | 8 +-
.../GlobalISel/legalizer-info-validation.mir | 4 +-
...f.mir => inst-select-ctlz-zero-poison.mir} | 24 +-
...f.mir => inst-select-cttz-zero-poison.mir} | 24 +-
...ndef.mir => legalize-ctlz-zero-poison.mir} | 92 ++---
...ndef.mir => legalize-cttz-zero-poison.mir} | 108 +++---
.../AMDGPU/GlobalISel/legalize-cttz.mir | 20 +-
...mir => regbankselect-ctlz-zero-poison.mir} | 36 +-
...mir => regbankselect-cttz-zero-poison.mir} | 36 +-
llvm/test/CodeGen/AMDGPU/ctls.ll | 16 +-
...ctlz_zero_undef.ll => ctlz_zero_poison.ll} | 340 +++++++++---------
...cttz_zero_undef.ll => cttz_zero_poison.ll} | 120 +++----
.../ARM/GlobalISel/arm-legalize-bitcounts.mir | 18 +-
llvm/test/CodeGen/ARM/cttz.ll | 40 +--
llvm/test/CodeGen/ARM/cttz_vector.ll | 56 +--
llvm/test/CodeGen/Lanai/i32.ll | 8 +-
.../Mips/GlobalISel/legalizer/cttz.mir | 4 +-
.../GlobalISel/legalizer-info-validation.mir | 4 +-
.../legalizer/legalize-ctlz-rv32.mir | 32 +-
.../legalizer/legalize-ctlz-rv64.mir | 32 +-
.../legalizer/legalize-cttz-rv32.mir | 32 +-
.../legalizer/legalize-cttz-rv64.mir | 32 +-
llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll | 6 +-
llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll | 128 +++----
llvm/test/CodeGen/RISCV/rv64xtheadbb.ll | 8 +-
llvm/test/CodeGen/RISCV/rv64zbb.ll | 6 +-
llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll | 216 +++++------
llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll | 306 ++++++++--------
llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll | 216 +++++------
llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll | 294 +++++++--------
.../RISCV/rvv/fixed-vectors-ctlz-vp.ll | 144 ++++----
.../CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll | 84 ++---
.../RISCV/rvv/fixed-vectors-cttz-vp.ll | 144 ++++----
.../CodeGen/RISCV/rvv/fixed-vectors-cttz.ll | 84 ++---
.../CodeGen/RISCV/rvv/known-never-zero.ll | 2 +-
.../test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll | 64 ++--
llvm/test/CodeGen/SystemZ/vec-ctlz-01.ll | 8 +-
llvm/test/CodeGen/SystemZ/vec-cttz-01.ll | 8 +-
.../GlobalISel/instructions/ctlz.mir | 18 +-
.../GlobalISel/instructions/cttz.mir | 18 +-
llvm/test/CodeGen/WebAssembly/i128.ll | 12 +-
llvm/test/CodeGen/WebAssembly/i32.ll | 12 +-
llvm/test/CodeGen/WebAssembly/i64.ll | 12 +-
.../X86/GlobalISel/legalize-leading-zeros.mir | 10 +-
...mir => legalize-trailing-zeros-poison.mir} | 44 +--
.../GlobalISel/legalize-trailing-zeros.mir | 20 +-
llvm/test/CodeGen/X86/bitcnt-big-integer.ll | 270 +++++++-------
llvm/test/CodeGen/X86/freeze-unary.ll | 36 +-
llvm/test/CodeGen/X86/known-never-zero.ll | 2 +-
llvm/test/CodeGen/X86/widen_bitcnt.ll | 58 +--
llvm/test/CodeGen/Xtensa/ctlz-cttz-ctpop.ll | 8 +-
.../InstCombine/X86/x86-sse4a-inseltpoison.ll | 2 +-
llvm/test/Transforms/InstCombine/add2.ll | 4 +-
llvm/test/Transforms/InstCombine/cttz.ll | 24 +-
.../InstCombine/select-cmp-cttz-ctlz.ll | 2 +-
.../Transforms/InstCombine/umin_cttz_ctlz.ll | 108 +++---
.../test/Transforms/SLPVectorizer/X86/ctlz.ll | 62 ++--
.../test/Transforms/SLPVectorizer/X86/cttz.ll | 62 ++--
.../GlobalISel/LegalizerHelperTest.cpp | 64 ++--
.../GlobalISel/MachineIRBuilderTest.cpp | 8 +-
123 files changed, 2242 insertions(+), 2226 deletions(-)
rename llvm/test/CodeGen/AArch64/GlobalISel/{legalize-cttz-zero-undef.mir => legalize-cttz-zero-poison.mir} (95%)
rename llvm/test/CodeGen/AMDGPU/GlobalISel/{inst-select-ctlz-zero-undef.mir => inst-select-ctlz-zero-poison.mir} (80%)
rename llvm/test/CodeGen/AMDGPU/GlobalISel/{inst-select-cttz-zero-undef.mir => inst-select-cttz-zero-poison.mir} (79%)
rename llvm/test/CodeGen/AMDGPU/GlobalISel/{legalize-ctlz-zero-undef.mir => legalize-ctlz-zero-poison.mir} (67%)
rename llvm/test/CodeGen/AMDGPU/GlobalISel/{legalize-cttz-zero-undef.mir => legalize-cttz-zero-poison.mir} (54%)
rename llvm/test/CodeGen/AMDGPU/GlobalISel/{regbankselect-ctlz-zero-undef.mir => regbankselect-ctlz-zero-poison.mir} (66%)
rename llvm/test/CodeGen/AMDGPU/GlobalISel/{regbankselect-cttz-zero-undef.mir => regbankselect-cttz-zero-poison.mir} (66%)
rename llvm/test/CodeGen/AMDGPU/{ctlz_zero_undef.ll => ctlz_zero_poison.ll} (90%)
rename llvm/test/CodeGen/AMDGPU/{cttz_zero_undef.ll => cttz_zero_poison.ll} (94%)
rename llvm/test/CodeGen/X86/GlobalISel/{legalize-trailing-zeros-undef.mir => legalize-trailing-zeros-poison.mir} (78%)
diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst
index f9872c8926d6d..d212b39720c5a 100644
--- a/llvm/docs/GlobalISel/GenericOpcode.rst
+++ b/llvm/docs/GlobalISel/GenericOpcode.rst
@@ -486,20 +486,20 @@ Count leading zeros, trailing zeros, or number of set bits.
.. code-block:: none
- %2:_(s33) = G_CTLZ_ZERO_UNDEF %1
- %2:_(s33) = G_CTTZ_ZERO_UNDEF %1
+ %2:_(s33) = G_CTLZ_ZERO_POISON %1
+ %2:_(s33) = G_CTTZ_ZERO_POISON %1
%2:_(s33) = G_CTPOP %1
-G_CTLZ_ZERO_UNDEF, G_CTTZ_ZERO_UNDEF
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+G_CTLZ_ZERO_POISON, G_CTTZ_ZERO_POISON
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Count leading zeros or trailing zeros. If the value is zero then the result is
-undefined.
+poison.
.. code-block:: none
- %2:_(s33) = G_CTLZ_ZERO_UNDEF %1
- %2:_(s33) = G_CTTZ_ZERO_UNDEF %1
+ %2:_(s33) = G_CTLZ_ZERO_POISON %1
+ %2:_(s33) = G_CTTZ_ZERO_POISON %1
G_CTLS
^^^^^^
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 98f2205bc06a7..7363c2fd8c52b 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -231,6 +231,20 @@ Makes programs 10x faster by doing Special New Thing.
### Changes to the CodeGen infrastructure
+* Renamed ISD::CTLZ_ZERO_UNDEF to ISD::CTLZ_ZERO_POISON opcode to make it clear that
+ a zero input results in poison.
+
+* Renamed ISD::CTTZ_ZERO_UNDEF to ISD::CTTZ_ZERO_POISON opcode to make it clear that
+ a zero input results in poison.
+
+### Changes to the GlobalISel infrastructure
+
+* Renamed G_CTLZ_ZERO_UNDEF to G_CTLZ_ZERO_POISON opcode to make it clear that
+ a zero input results in poison.
+
+* Renamed G_CTTZ_ZERO_UNDEF to G_CTTZ_ZERO_POISON opcode to make it clear that
+ a zero input results in poison.
+
### Changes to the Metadata Info
### Changes to the Debug Info
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
index 97f29015c6911..3687adbe60f1a 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
@@ -410,7 +410,7 @@ class CombinerHelper {
const ConstantFP *Cst) const;
/// Constant fold a unary integer op (G_CTLZ, G_CTTZ, G_CTPOP and their
- /// _ZERO_UNDEF variants, G_ABS, G_BSWAP, G_BITREVERSE) when the operand is
+ /// _ZERO_POISON variants, G_ABS, G_BSWAP, G_BITREVERSE) when the operand is
/// a scalar constant or a G_BUILD_VECTOR of constants.
bool matchConstantFoldUnaryIntOp(MachineInstr &MI,
BuildFnTy &MatchInfo) const;
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index c7973a8a9fb00..511bc17161e03 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -2061,9 +2061,10 @@ class LLVM_ABI MachineIRBuilder {
return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0});
}
- /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0
- MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) {
- return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0});
+ /// Build and insert \p Res = G_CTLZ_ZERO_POISON \p Op0, \p Src0
+ MachineInstrBuilder buildCTLZ_ZERO_POISON(const DstOp &Dst,
+ const SrcOp &Src0) {
+ return buildInstr(TargetOpcode::G_CTLZ_ZERO_POISON, {Dst}, {Src0});
}
/// Build and insert \p Res = G_CTTZ \p Op0, \p Src0
@@ -2071,9 +2072,10 @@ class LLVM_ABI MachineIRBuilder {
return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0});
}
- /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0
- MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) {
- return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
+ /// Build and insert \p Res = G_CTTZ_ZERO_POISON \p Op0, \p Src0
+ MachineInstrBuilder buildCTTZ_ZERO_POISON(const DstOp &Dst,
+ const SrcOp &Src0) {
+ return buildInstr(TargetOpcode::G_CTTZ_ZERO_POISON, {Dst}, {Src0});
}
/// Build and insert \p Res = G_CTLS \p Op0, \p Src0
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
index a861a60ecfcd3..a78bbe80b2f61 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
@@ -320,7 +320,7 @@ ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src,
const MachineRegisterInfo &MRI);
/// Tries to constant fold a unary integer operation (G_CTLZ, G_CTTZ, G_CTPOP
-/// and their _ZERO_UNDEF variants, G_ABS, G_BSWAP, G_BITREVERSE) on \p Src.
+/// and their _ZERO_POISON variants, G_ABS, G_BSWAP, G_BITREVERSE) on \p Src.
/// If \p Src is a vector then it tries to do an element-wise constant fold.
LLVM_ABI SmallVector<APInt>
ConstantFoldUnaryIntOp(unsigned Opcode, LLT DstTy, Register Src,
diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h
index 8a8a9ee71ca02..7dc57d9f32c87 100644
--- a/llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -783,9 +783,9 @@ enum NodeType {
BITREVERSE,
PARITY,
- /// Bit counting operators with an undefined result for zero inputs.
- CTTZ_ZERO_UNDEF,
- CTLZ_ZERO_UNDEF,
+ /// Bit counting operators with an poisoned result for zero inputs.
+ CTTZ_ZERO_POISON,
+ CTLZ_ZERO_POISON,
/// Count leading redundant sign bits. Equivalent to
/// (sub (ctlz (x < 0 ? ~x : x)), 1).
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index f1119e4acce58..318763113fb42 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -5663,13 +5663,13 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
/// \returns The expansion result or SDValue() if it fails.
SDValue expandVPCTPOP(SDNode *N, SelectionDAG &DAG) const;
- /// Expand CTLZ/CTLZ_ZERO_UNDEF nodes. Expands vector/scalar CTLZ nodes,
+ /// Expand CTLZ/CTLZ_ZERO_POISON nodes. Expands vector/scalar CTLZ nodes,
/// vector nodes can only succeed if all operations are legal/custom.
/// \param N Node to expand
/// \returns The expansion result or SDValue() if it fails.
SDValue expandCTLZ(SDNode *N, SelectionDAG &DAG) const;
- /// Expand VP_CTLZ/VP_CTLZ_ZERO_UNDEF nodes.
+ /// Expand VP_CTLZ/VP_CTLZ_ZERO_POISON nodes.
/// \param N Node to expand
/// \returns The expansion result or SDValue() if it fails.
SDValue expandVPCTLZ(SDNode *N, SelectionDAG &DAG) const;
@@ -5686,18 +5686,18 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
SDValue CTTZTableLookup(SDNode *N, SelectionDAG &DAG, const SDLoc &DL, EVT VT,
SDValue Op, unsigned NumBitsPerElt) const;
- /// Expand CTTZ/CTTZ_ZERO_UNDEF nodes. Expands vector/scalar CTTZ nodes,
+ /// Expand CTTZ/CTTZ_ZERO_POISON nodes. Expands vector/scalar CTTZ nodes,
/// vector nodes can only succeed if all operations are legal/custom.
/// \param N Node to expand
/// \returns The expansion result or SDValue() if it fails.
SDValue expandCTTZ(SDNode *N, SelectionDAG &DAG) const;
- /// Expand VP_CTTZ/VP_CTTZ_ZERO_UNDEF nodes.
+ /// Expand VP_CTTZ/VP_CTTZ_ZERO_POISON nodes.
/// \param N Node to expand
/// \returns The expansion result or SDValue() if it fails.
SDValue expandVPCTTZ(SDNode *N, SelectionDAG &DAG) const;
- /// Expand VP_CTTZ_ELTS/VP_CTTZ_ELTS_ZERO_UNDEF nodes.
+ /// Expand VP_CTTZ_ELTS/VP_CTTZ_ELTS_ZERO_POISON nodes.
/// \param N Node to expand
/// \returns The expansion result or SDValue() if it fails.
SDValue expandVPCTTZElements(SDNode *N, SelectionDAG &DAG) const;
diff --git a/llvm/include/llvm/IR/VPIntrinsics.def b/llvm/include/llvm/IR/VPIntrinsics.def
index 0b0c744487b92..7015bd5a6f0ce 100644
--- a/llvm/include/llvm/IR/VPIntrinsics.def
+++ b/llvm/include/llvm/IR/VPIntrinsics.def
@@ -240,9 +240,9 @@ BEGIN_REGISTER_VP_SDNODE(VP_CTLZ, -1, vp_ctlz, 1, 2)
VP_PROPERTY_FUNCTIONAL_INTRINSIC(ctlz)
VP_PROPERTY_FUNCTIONAL_SDOPC(CTLZ)
END_REGISTER_VP_SDNODE(VP_CTLZ)
-BEGIN_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_UNDEF, -1, vp_ctlz_zero_undef, 1, 2)
-VP_PROPERTY_FUNCTIONAL_SDOPC(CTLZ_ZERO_UNDEF)
-END_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_UNDEF)
+BEGIN_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_POISON, -1, vp_ctlz_zero_poison, 1, 2)
+VP_PROPERTY_FUNCTIONAL_SDOPC(CTLZ_ZERO_POISON)
+END_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_POISON)
END_REGISTER_VP_INTRINSIC(vp_ctlz)
// llvm.vp.cttz(x,is_zero_poison,mask,vlen)
@@ -251,8 +251,8 @@ BEGIN_REGISTER_VP_SDNODE(VP_CTTZ, -1, vp_cttz, 1, 2)
VP_PROPERTY_FUNCTIONAL_INTRINSIC(cttz)
VP_PROPERTY_FUNCTIONAL_SDOPC(CTTZ)
END_REGISTER_VP_SDNODE(VP_CTTZ)
-BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_UNDEF, -1, vp_cttz_zero_undef, 1, 2)
-END_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_UNDEF)
+BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_POISON, -1, vp_cttz_zero_poison, 1, 2)
+END_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_POISON)
END_REGISTER_VP_INTRINSIC(vp_cttz)
// llvm.vp.cttz.elts(x,is_zero_poison,mask,vl)
@@ -260,8 +260,8 @@ BEGIN_REGISTER_VP_INTRINSIC(vp_cttz_elts, 2, 3)
VP_PROPERTY_NO_FUNCTIONAL
BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ELTS, 0, vp_cttz_elts, 1, 2)
END_REGISTER_VP_SDNODE(VP_CTTZ_ELTS)
-BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ELTS_ZERO_UNDEF, 0, vp_cttz_elts_zero_undef, 1, 2)
-END_REGISTER_VP_SDNODE(VP_CTTZ_ELTS_ZERO_UNDEF)
+BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ELTS_ZERO_POISON, 0, vp_cttz_elts_zero_poison, 1, 2)
+END_REGISTER_VP_SDNODE(VP_CTTZ_ELTS_ZERO_POISON)
END_REGISTER_VP_INTRINSIC(vp_cttz_elts)
// llvm.vp.fshl(x,y,z,mask,vlen)
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index a8db3c1d75aa0..68a80dde6b3fe 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -838,14 +838,14 @@ HANDLE_TARGET_OPCODE(G_VECTOR_COMPRESS)
/// Generic count trailing zeroes.
HANDLE_TARGET_OPCODE(G_CTTZ)
-/// Same as above, undefined for zero inputs.
-HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_UNDEF)
+/// Same as above, poisoned for zero inputs.
+HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_POISON)
/// Generic count leading zeroes.
HANDLE_TARGET_OPCODE(G_CTLZ)
-/// Same as above, undefined for zero inputs.
-HANDLE_TARGET_OPCODE(G_CTLZ_ZERO_UNDEF)
+/// Same as above, poisoned for zero inputs.
+HANDLE_TARGET_OPCODE(G_CTLZ_ZERO_POISON)
/// Generic count extra sign bits.
HANDLE_TARGET_OPCODE(G_CTLS)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index 3612e3c458f90..37a185a226b63 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -202,7 +202,7 @@ def G_CTLZ : GenericInstruction {
let hasSideEffects = false;
}
-def G_CTLZ_ZERO_UNDEF : GenericInstruction {
+def G_CTLZ_ZERO_POISON : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
let hasSideEffects = false;
@@ -214,7 +214,7 @@ def G_CTTZ : GenericInstruction {
let hasSideEffects = false;
}
-def G_CTTZ_ZERO_UNDEF : GenericInstruction {
+def G_CTTZ_ZERO_POISON : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
let hasSideEffects = false;
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 2091554304771..5d9025b5cc9c8 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -1404,7 +1404,7 @@ def constant_fold_cast_op : GICombineRule<
def unary_int_op_frags : GICombinePatFrag<
(outs root:$dst), (ins),
!foreach(op,
- [G_CTLZ, G_CTLZ_ZERO_UNDEF, G_CTTZ, G_CTTZ_ZERO_UNDEF, G_CTPOP,
+ [G_CTLZ, G_CTLZ_ZERO_POISON, G_CTTZ, G_CTTZ_ZERO_POISON, G_CTPOP,
G_ABS, G_BSWAP, G_BITREVERSE],
(pattern (op $dst, $src)))>;
@@ -2230,11 +2230,11 @@ class ctlz_to_ctls_op<Instruction ctlzOpcode> : GICombineRule <
(apply [{Helper.applyBuildFn(*${root}, ${matchinfo});}])>;
def ctlz_to_ctls : ctlz_to_ctls_op<G_CTLZ>;
-def ctlz_zero_undef_to_ctls : ctlz_to_ctls_op<G_CTLZ_ZERO_UNDEF>;
+def ctlz_zero_poison_to_ctls : ctlz_to_ctls_op<G_CTLZ_ZERO_POISON>;
def ctls_combines : GICombineGroup<[
ctlz_to_ctls,
- ctlz_zero_undef_to_ctls,
+ ctlz_zero_poison_to_ctls,
]>;
def narrow_binop_add : narrow_binop_opcode<G_ADD>;
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index abfd41864c8bf..6933176b0fb53 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -157,8 +157,8 @@ def : GINodeEquiv<G_FSHL, fshl>;
def : GINodeEquiv<G_FSHR, fshr>;
def : GINodeEquiv<G_CTLZ, ctlz>;
def : GINodeEquiv<G_CTTZ, cttz>;
-def : GINodeEquiv<G_CTLZ_ZERO_UNDEF, ctlz_zero_undef>;
-def : GINodeEquiv<G_CTTZ_ZERO_UNDEF, cttz_zero_undef>;
+def : GINodeEquiv<G_CTLZ_ZERO_POISON, ctlz_zero_poison>;
+def : GINodeEquiv<G_CTTZ_ZERO_POISON, cttz_zero_poison>;
def : GINodeEquiv<G_CTLS, ctls>;
def : GINodeEquiv<G_CTPOP, ctpop>;
def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, extractelt>;
diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index 573342846b4cf..ec8fbd84d5166 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -535,8 +535,8 @@ def ctlz : SDNode<"ISD::CTLZ" , SDTIntBitCountUnaryOp>;
def cttz : SDNode<"ISD::CTTZ" , SDTIntBitCountUnaryOp>;
def ctpop : SDNode<"ISD::CTPOP" , SDTIntBitCountUnaryOp>;
def ctls : SDNode<"ISD::CTLS" , SDTIntBitCountUnaryOp>;
-def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntBitCountUnaryOp>;
-def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntBitCountUnaryOp>;
+def ctlz_zero_poison : SDNode<"ISD::CTLZ_ZERO_POISON", SDTIntBitCountUnaryOp>;
+def cttz_zero_poison : SDNode<"ISD::CTTZ_ZERO_POISON", SDTIntBitCountUnaryOp>;
def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
diff --git a/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
index ff96d7a3cbd9a..8e5bf2120dd40 100644
--- a/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
@@ -282,9 +282,9 @@ MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc,
break;
}
case TargetOpcode::G_CTLZ:
- case TargetOpcode::G_CTLZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTLZ_ZERO_POISON:
case TargetOpcode::G_CTTZ:
- case TargetOpcode::G_CTTZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTTZ_ZERO_POISON:
case TargetOpcode::G_CTPOP:
case TargetOpcode::G_ABS:
case TargetOpcode::G_BSWAP:
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index c58fb84a3890e..0f2617b9b5b1c 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -8642,7 +8642,7 @@ bool CombinerHelper::matchSuboCarryOut(const MachineInstr &MI,
bool CombinerHelper::matchCtls(MachineInstr &CtlzMI,
BuildFnTy &MatchInfo) const {
assert((CtlzMI.getOpcode() == TargetOpcode::G_CTLZ ||
- CtlzMI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) &&
+ CtlzMI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_POISON) &&
"Expected G_CTLZ variant");
const Register Dst = CtlzMI.getOperand(0).getReg();
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 5fcc84d0d76a1..44298258da11c 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -793,7 +793,7 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
break;
}
case TargetOpcode::G_CTTZ:
- case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
+ case TargetOpcode::G_CTTZ_ZERO_POISON: {
KnownBits SrcOpKnown;
computeKnownBitsImpl(MI.getOperand(1).getReg(), SrcOpKnown, DemandedElts,
Depth + 1);
@@ -804,7 +804,7 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
break;
}
case TargetOpcode::G_CTLZ:
- case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
+ case TargetOpcode::G_CTLZ_ZERO_POISON: {
KnownBits SrcOpKnown;
computeKnownBitsImpl(MI.getOperand(1).getReg(), SrcOpKnown, DemandedElts,
Depth + 1);
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 7db3e2d4e02b7..8c8e08865744a 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -2482,11 +2482,11 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
case Intrinsic::ctlz: {
ConstantInt *Cst = cast<ConstantInt>(CI.getArgOperand(1));
bool isTrailing = ID == Intrinsic::cttz;
- unsigned Opcode = isTrailing
- ? Cst->isZero() ? TargetOpcode::G_CTTZ
- : TargetOpcode::G_CTTZ_ZERO_UNDEF
- : Cst->isZero() ? TargetOpcode::G_CTLZ
- : TargetOpcode::G_CTLZ_ZERO_UNDEF;
+ unsigned Opcode = isTrailing ? Cst->isZero()
+ ? TargetOpcode::G_CTTZ
+ : TargetOpcode::G_CTTZ_ZERO_POISON
+ : Cst->isZero() ? TargetOpcode::G_CTLZ
+ : TargetOpcode::G_CTLZ_ZERO_POISON;
MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(CI)},
{getOrCreateVReg(*CI.getArgOperand(0))});
return true;
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 71cda8a480dd7..909decfb015b5 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -427,7 +427,7 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
RTLIBCASE_INT(SREM_I);
case TargetOpcode::G_UREM:
RTLIBCASE_INT(UREM_I);
- case TargetOpcode::G_CTLZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTLZ_ZERO_POISON:
RTLIBCASE_INT(CTLZ_I);
case TargetOpcode::G_FADD:
RTLIBCASE(ADD_F);
@@ -1318,7 +1318,7 @@ LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) {
case TargetOpcode::G_UDIV:
case TargetOpcode::G_SREM:
case TargetOpcode::G_UREM:
- case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
+ case TargetOpcode::G_CTLZ_ZERO_POISON: {
LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
unsigned Size = LLTy.getSizeInBits();
Type *HLTy = IntegerType::get(Ctx, Size);
@@ -1781,18 +1781,18 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
case TargetOpcode::G_ASHR:
return narrowScalarShift(MI, TypeIdx, NarrowTy);
case TargetOpcode::G_CTLZ:
- case TargetOpcode::G_CTLZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTLZ_ZERO_POISON:
case TargetOpcode::G_CTTZ:
- case TargetOpcode::G_CTTZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTTZ_ZERO_POISON:
case TargetOpcode::G_CTLS:
case TargetOpcode::G_CTPOP:
if (TypeIdx == 1)
switch (MI.getOpcode()) {
case TargetOpcode::G_CTLZ:
- case TargetOpcode::G_CTLZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTLZ_ZERO_POISON:
return narrowScalarCTLZ(MI, TypeIdx, NarrowTy);
case TargetOpcode::G_CTTZ:
- case TargetOpcode::G_CTTZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTTZ_ZERO_POISON:
return narrowScalarCTTZ(MI, TypeIdx, NarrowTy);
case TargetOpcode::G_CTPOP:
return narrowScalarCTPOP(MI, TypeIdx, NarrowTy);
@@ -2822,9 +2822,9 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
case TargetOpcode::G_USHLSAT:
return widenScalarAddSubShlSat(MI, TypeIdx, WideTy);
case TargetOpcode::G_CTTZ:
- case TargetOpcode::G_CTTZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTTZ_ZERO_POISON:
case TargetOpcode::G_CTLZ:
- case TargetOpcode::G_CTLZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTLZ_ZERO_POISON:
case TargetOpcode::G_CTLS:
case TargetOpcode::G_CTPOP: {
if (TypeIdx == 0) {
@@ -2840,8 +2840,8 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
unsigned ExtOpc;
switch (Opcode) {
case TargetOpcode::G_CTTZ:
- case TargetOpcode::G_CTTZ_ZERO_UNDEF:
- case TargetOpcode::G_CTLZ_ZERO_UNDEF: // undef bits shifted out below
+ case TargetOpcode::G_CTTZ_ZERO_POISON:
+ case TargetOpcode::G_CTLZ_ZERO_POISON: // poison shifted out below
ExtOpc = TargetOpcode::G_ANYEXT;
break;
case TargetOpcode::G_CTLS:
@@ -2863,13 +2863,13 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
MIBSrc = MIRBuilder.buildOr(
WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit));
// Now we know the operand is non-zero, use the more relaxed opcode.
- NewOpc = TargetOpcode::G_CTTZ_ZERO_UNDEF;
+ NewOpc = TargetOpcode::G_CTTZ_ZERO_POISON;
}
unsigned SizeDiff =
WideTy.getScalarSizeInBits() - CurTy.getScalarSizeInBits();
- if (Opcode == TargetOpcode::G_CTLZ_ZERO_UNDEF) {
+ if (Opcode == TargetOpcode::G_CTLZ_ZERO_POISON) {
// An optimization where the result is the CTLZ after the left shift by
// (Difference in widety and current ty), that is,
// MIBSrc = MIBSrc << (sizeinbits(WideTy) - sizeinbits(CurTy))
@@ -4727,8 +4727,8 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
return lowerLoad(cast<GAnyLoad>(MI));
case TargetOpcode::G_STORE:
return lowerStore(cast<GStore>(MI));
- case TargetOpcode::G_CTLZ_ZERO_UNDEF:
- case TargetOpcode::G_CTTZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTLZ_ZERO_POISON:
+ case TargetOpcode::G_CTTZ_ZERO_POISON:
case TargetOpcode::G_CTLZ:
case TargetOpcode::G_CTTZ:
case TargetOpcode::G_CTPOP:
@@ -5682,9 +5682,9 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
case G_SSHLSAT:
case G_USHLSAT:
case G_CTLZ:
- case G_CTLZ_ZERO_UNDEF:
+ case G_CTLZ_ZERO_POISON:
case G_CTTZ:
- case G_CTTZ_ZERO_UNDEF:
+ case G_CTTZ_ZERO_POISON:
case G_CTPOP:
case G_CTLS:
case G_FCOPYSIGN:
@@ -7577,7 +7577,7 @@ LegalizerHelper::narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx,
unsigned NarrowSize = NarrowTy.getSizeInBits();
if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) {
- const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF;
+ const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_POISON;
MachineIRBuilder &B = MIRBuilder;
auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg);
@@ -7585,12 +7585,11 @@ LegalizerHelper::narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx,
auto C_0 = B.buildConstant(NarrowTy, 0);
auto HiIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::integer(1),
UnmergeSrc.getReg(1), C_0);
- auto LoCTLZ = IsUndef ?
- B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)) :
- B.buildCTLZ(DstTy, UnmergeSrc.getReg(0));
+ auto LoCTLZ = IsUndef ? B.buildCTLZ_ZERO_POISON(DstTy, UnmergeSrc.getReg(0))
+ : B.buildCTLZ(DstTy, UnmergeSrc.getReg(0));
auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize);
auto HiIsZeroCTLZ = B.buildAdd(DstTy, LoCTLZ, C_NarrowSize);
- auto HiCTLZ = B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1));
+ auto HiCTLZ = B.buildCTLZ_ZERO_POISON(DstTy, UnmergeSrc.getReg(1));
B.buildSelect(DstReg, HiIsZero, HiIsZeroCTLZ, HiCTLZ);
MI.eraseFromParent();
@@ -7610,7 +7609,7 @@ LegalizerHelper::narrowScalarCTTZ(MachineInstr &MI, unsigned TypeIdx,
unsigned NarrowSize = NarrowTy.getSizeInBits();
if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) {
- const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTTZ_ZERO_UNDEF;
+ const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTTZ_ZERO_POISON;
MachineIRBuilder &B = MIRBuilder;
auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg);
@@ -7618,12 +7617,11 @@ LegalizerHelper::narrowScalarCTTZ(MachineInstr &MI, unsigned TypeIdx,
auto C_0 = B.buildConstant(NarrowTy, 0);
auto LoIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
UnmergeSrc.getReg(0), C_0);
- auto HiCTTZ = IsUndef ?
- B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1)) :
- B.buildCTTZ(DstTy, UnmergeSrc.getReg(1));
+ auto HiCTTZ = IsUndef ? B.buildCTTZ_ZERO_POISON(DstTy, UnmergeSrc.getReg(1))
+ : B.buildCTTZ(DstTy, UnmergeSrc.getReg(1));
auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize);
auto LoIsZeroCTTZ = B.buildAdd(DstTy, HiCTTZ, C_NarrowSize);
- auto LoCTTZ = B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0));
+ auto LoCTTZ = B.buildCTTZ_ZERO_POISON(DstTy, UnmergeSrc.getReg(0));
B.buildSelect(DstReg, LoIsZero, LoIsZeroCTTZ, LoCTTZ);
MI.eraseFromParent();
@@ -7734,7 +7732,7 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI) {
switch (Opc) {
default:
return UnableToLegalize;
- case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
+ case TargetOpcode::G_CTLZ_ZERO_POISON: {
// This trivially expands to CTLZ.
Observer.changingInstr(MI);
MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
@@ -7745,9 +7743,9 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI) {
auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
unsigned Len = SrcTy.getScalarSizeInBits();
- if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {DstTy, SrcTy}})) {
- // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
- auto CtlzZU = MIRBuilder.buildCTLZ_ZERO_UNDEF(DstTy, SrcReg);
+ if (isSupported({TargetOpcode::G_CTLZ_ZERO_POISON, {DstTy, SrcTy}})) {
+ // If CTLZ_ZERO_POISON is supported, emit that and a select for zero.
+ auto CtlzZU = MIRBuilder.buildCTLZ_ZERO_POISON(DstTy, SrcReg);
auto ZeroSrc = MIRBuilder.buildConstant(SrcTy, 0);
auto ICmp = MIRBuilder.buildICmp(
CmpInst::ICMP_EQ, SrcTy.changeElementSize(1), SrcReg, ZeroSrc);
@@ -7781,7 +7779,7 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI) {
MI.eraseFromParent();
return Legalized;
}
- case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
+ case TargetOpcode::G_CTTZ_ZERO_POISON: {
// This trivially expands to CTTZ.
Observer.changingInstr(MI);
MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
@@ -7792,10 +7790,10 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI) {
auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
unsigned Len = SrcTy.getScalarSizeInBits();
- if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {DstTy, SrcTy}})) {
- // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
+ if (isSupported({TargetOpcode::G_CTTZ_ZERO_POISON, {DstTy, SrcTy}})) {
+ // If CTTZ_ZERO_POISON is legal or custom, emit that and a select with
// zero.
- auto CttzZU = MIRBuilder.buildCTTZ_ZERO_UNDEF(DstTy, SrcReg);
+ auto CttzZU = MIRBuilder.buildCTTZ_ZERO_POISON(DstTy, SrcReg);
auto Zero = MIRBuilder.buildConstant(SrcTy, 0);
auto ICmp = MIRBuilder.buildICmp(
CmpInst::ICMP_EQ, DstTy.changeElementSize(1), SrcReg, Zero);
@@ -8261,7 +8259,7 @@ LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
auto Zero32 = MIRBuilder.buildConstant(S32, 0);
auto Zero64 = MIRBuilder.buildConstant(S64, 0);
- auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src);
+ auto LZ = MIRBuilder.buildCTLZ_ZERO_POISON(S32, Src);
auto K = MIRBuilder.buildConstant(S32, 127U + 63U);
auto Sub = MIRBuilder.buildSub(S32, K, LZ);
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index f552fb7de45dd..5d1e088fcb066 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -948,10 +948,10 @@ llvm::ConstantFoldUnaryIntOp(unsigned Opcode, LLT DstTy, Register Src,
auto Fold = [Opcode, EltBits](const APInt &V) -> APInt {
switch (Opcode) {
case TargetOpcode::G_CTLZ:
- case TargetOpcode::G_CTLZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTLZ_ZERO_POISON:
return APInt(EltBits, V.countl_zero());
case TargetOpcode::G_CTTZ:
- case TargetOpcode::G_CTTZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTTZ_ZERO_POISON:
return APInt(EltBits, V.countr_zero());
case TargetOpcode::G_CTPOP:
return APInt(EltBits, V.popcount());
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5a467a5a5ba53..21072c4341ae9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -476,9 +476,9 @@ namespace {
SDValue visitBSWAP(SDNode *N);
SDValue visitBITREVERSE(SDNode *N);
SDValue visitCTLZ(SDNode *N);
- SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
+ SDValue visitCTLZ_ZERO_POISON(SDNode *N);
SDValue visitCTTZ(SDNode *N);
- SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
+ SDValue visitCTTZ_ZERO_POISON(SDNode *N);
SDValue visitCTPOP(SDNode *N);
SDValue visitSELECT(SDNode *N);
SDValue visitVSELECT(SDNode *N);
@@ -1997,9 +1997,9 @@ SDValue DAGCombiner::visit(SDNode *N) {
case ISD::BSWAP: return visitBSWAP(N);
case ISD::BITREVERSE: return visitBITREVERSE(N);
case ISD::CTLZ: return visitCTLZ(N);
- case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
+ case ISD::CTLZ_ZERO_POISON: return visitCTLZ_ZERO_POISON(N);
case ISD::CTTZ: return visitCTTZ(N);
- case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
+ case ISD::CTTZ_ZERO_POISON: return visitCTTZ_ZERO_POISON(N);
case ISD::CTPOP: return visitCTPOP(N);
case ISD::SELECT: return visitSELECT(N);
case ISD::VSELECT: return visitVSELECT(N);
@@ -4104,8 +4104,8 @@ SDValue DAGCombiner::foldSubToUSubSat(EVT DstVT, SDNode *N, const SDLoc &DL) {
// if BitWidthDiff == BitWidth(Node) - BitWidth(Src)
// -->
//
-// (ctlz_zero_undef (not (shl (anyextend Src)
-// BitWidthDiff)))
+// (ctlz_zero_poison (not (shl (anyextend Src)
+// BitWidthDiff)))
//
// * Type Legalisation Pattern:
//
@@ -4118,7 +4118,7 @@ SDValue DAGCombiner::foldSubToUSubSat(EVT DstVT, SDNode *N, const SDLoc &DL) {
// and XorMask has more trailing ones than AndMask
// -->
//
-// (ctlz_zero_undef (not (shl Src BitWidthDiff)))
+// (ctlz_zero_poison (not (shl Src BitWidthDiff)))
template <class MatchContextClass>
static SDValue foldSubCtlzNot(SDNode *N, SelectionDAG &DAG) {
const SDLoc DL(N);
@@ -4164,7 +4164,7 @@ static SDValue foldSubCtlzNot(SDNode *N, SelectionDAG &DAG) {
SDValue Not =
Matcher.getNode(ISD::XOR, DL, VT, LShift, DAG.getAllOnesConstant(DL, VT));
- return Matcher.getNode(ISD::CTLZ_ZERO_UNDEF, DL, VT, Not);
+ return Matcher.getNode(ISD::CTLZ_ZERO_POISON, DL, VT, Not);
}
// Fold sub(x, mul(divrem(x,y)[0], y)) to divrem(x, y)[1]
@@ -11048,7 +11048,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
// target.
if (((N1.getOpcode() == ISD::CTTZ &&
VT.getScalarSizeInBits() <= ShiftVT.getScalarSizeInBits()) ||
- N1.getOpcode() == ISD::CTTZ_ZERO_UNDEF) &&
+ N1.getOpcode() == ISD::CTTZ_ZERO_POISON) &&
N1.hasOneUse() && !TLI.isOperationLegalOrCustom(ISD::CTTZ, ShiftVT) &&
TLI.isOperationLegalOrCustom(ISD::MUL, VT)) {
SDValue Y = N1.getOperand(0);
@@ -12308,10 +12308,10 @@ SDValue DAGCombiner::visitCTLZ(SDNode *N) {
if (SDValue C = DAG.FoldConstantArithmetic(ISD::CTLZ, DL, VT, {N0}))
return C;
- // If the value is known never to be zero, switch to the undef version.
- if (!LegalOperations || TLI.isOperationLegal(ISD::CTLZ_ZERO_UNDEF, VT))
+ // If the value is known never to be zero, switch to the poison version.
+ if (!LegalOperations || TLI.isOperationLegal(ISD::CTLZ_ZERO_POISON, VT))
if (DAG.isKnownNeverZero(N0))
- return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, DL, VT, N0);
+ return DAG.getNode(ISD::CTLZ_ZERO_POISON, DL, VT, N0);
if (SDValue V = foldCTLZToCTLS(N0, DL))
return V;
@@ -12319,14 +12319,14 @@ SDValue DAGCombiner::visitCTLZ(SDNode *N) {
return SDValue();
}
-SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
+SDValue DAGCombiner::visitCTLZ_ZERO_POISON(SDNode *N) {
SDValue N0 = N->getOperand(0);
EVT VT = N->getValueType(0);
SDLoc DL(N);
- // fold (ctlz_zero_undef c1) -> c2
+ // fold (ctlz_zero_poison c1) -> c2
if (SDValue C =
- DAG.FoldConstantArithmetic(ISD::CTLZ_ZERO_UNDEF, DL, VT, {N0}))
+ DAG.FoldConstantArithmetic(ISD::CTLZ_ZERO_POISON, DL, VT, {N0}))
return C;
if (SDValue V = foldCTLZToCTLS(N0, DL))
@@ -12344,22 +12344,22 @@ SDValue DAGCombiner::visitCTTZ(SDNode *N) {
if (SDValue C = DAG.FoldConstantArithmetic(ISD::CTTZ, DL, VT, {N0}))
return C;
- // If the value is known never to be zero, switch to the undef version.
- if (!LegalOperations || TLI.isOperationLegal(ISD::CTTZ_ZERO_UNDEF, VT))
+ // If the value is known never to be zero, switch to the poison version.
+ if (!LegalOperations || TLI.isOperationLegal(ISD::CTTZ_ZERO_POISON, VT))
if (DAG.isKnownNeverZero(N0))
- return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, DL, VT, N0);
+ return DAG.getNode(ISD::CTTZ_ZERO_POISON, DL, VT, N0);
return SDValue();
}
-SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
+SDValue DAGCombiner::visitCTTZ_ZERO_POISON(SDNode *N) {
SDValue N0 = N->getOperand(0);
EVT VT = N->getValueType(0);
SDLoc DL(N);
- // fold (cttz_zero_undef c1) -> c2
+ // fold (cttz_zero_poison c1) -> c2
if (SDValue C =
- DAG.FoldConstantArithmetic(ISD::CTTZ_ZERO_UNDEF, DL, VT, {N0}))
+ DAG.FoldConstantArithmetic(ISD::CTTZ_ZERO_POISON, DL, VT, {N0}))
return C;
return SDValue();
}
@@ -17964,8 +17964,8 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
// operands via the operand numbers. The typical scenario is that we have
// something like this
// t262: i32 = freeze t181
- // t150: i32 = ctlz_zero_undef t262
- // t184: i32 = ctlz_zero_undef t181
+ // t150: i32 = ctlz_zero_poison t262
+ // t184: i32 = ctlz_zero_poison t181
// t268: i32 = select_cc t181, Constant:i32<0>, t184, t186, setne:ch
// When freezing the t181 operand we get t262 back, and then the
// ReplaceAllUsesOfValueWith call will not only replace t181 by t262, but
@@ -30480,13 +30480,13 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
}
// select_cc seteq X, 0, sizeof(X), ctlz(X) -> ctlz(X)
- // select_cc seteq X, 0, sizeof(X), ctlz_zero_undef(X) -> ctlz(X)
+ // select_cc seteq X, 0, sizeof(X), ctlz_zero_poison(X) -> ctlz(X)
// select_cc seteq X, 0, sizeof(X), cttz(X) -> cttz(X)
- // select_cc seteq X, 0, sizeof(X), cttz_zero_undef(X) -> cttz(X)
+ // select_cc seteq X, 0, sizeof(X), cttz_zero_poison(X) -> cttz(X)
// select_cc setne X, 0, ctlz(X), sizeof(X) -> ctlz(X)
- // select_cc setne X, 0, ctlz_zero_undef(X), sizeof(X) -> ctlz(X)
+ // select_cc setne X, 0, ctlz_zero_poison(X), sizeof(X) -> ctlz(X)
// select_cc setne X, 0, cttz(X), sizeof(X) -> cttz(X)
- // select_cc setne X, 0, cttz_zero_undef(X), sizeof(X) -> cttz(X)
+ // select_cc setne X, 0, cttz_zero_poison(X), sizeof(X) -> cttz(X)
if (N1C && N1C->isZero() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
SDValue ValueOnZero = N2;
SDValue Count = N3;
@@ -30496,17 +30496,17 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
// Check if the value on zero is a constant equal to the bits in the type.
if (auto *ValueOnZeroC = dyn_cast<ConstantSDNode>(ValueOnZero)) {
if (ValueOnZeroC->getAPIntValue() == VT.getSizeInBits()) {
- // If the other operand is cttz/cttz_zero_undef of N0, and cttz is
+ // If the other operand is cttz/cttz_zero_poison of N0, and cttz is
// legal, combine to just cttz.
if ((Count.getOpcode() == ISD::CTTZ ||
- Count.getOpcode() == ISD::CTTZ_ZERO_UNDEF) &&
+ Count.getOpcode() == ISD::CTTZ_ZERO_POISON) &&
N0 == Count.getOperand(0) &&
(!LegalOperations || TLI.isOperationLegal(ISD::CTTZ, VT)))
return DAG.getNode(ISD::CTTZ, DL, VT, N0);
- // If the other operand is ctlz/ctlz_zero_undef of N0, and ctlz is
+ // If the other operand is ctlz/ctlz_zero_poison of N0, and ctlz is
// legal, combine to just ctlz.
if ((Count.getOpcode() == ISD::CTLZ ||
- Count.getOpcode() == ISD::CTLZ_ZERO_UNDEF) &&
+ Count.getOpcode() == ISD::CTLZ_ZERO_POISON) &&
N0 == Count.getOperand(0) &&
(!LegalOperations || TLI.isOperationLegal(ISD::CTLZ, VT)))
return DAG.getNode(ISD::CTLZ, DL, VT, N0);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 4550d9e67d8f3..9e4f169cd4f3f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1283,7 +1283,7 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
case ISD::CTTZ_ELTS:
case ISD::CTTZ_ELTS_ZERO_POISON:
case ISD::VP_CTTZ_ELTS:
- case ISD::VP_CTTZ_ELTS_ZERO_UNDEF:
+ case ISD::VP_CTTZ_ELTS_ZERO_POISON:
Action = TLI.getOperationAction(Node->getOpcode(),
Node->getOperand(0).getValueType());
break;
@@ -3261,7 +3261,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Results.push_back(Tmp1);
break;
case ISD::CTLZ:
- case ISD::CTLZ_ZERO_UNDEF:
+ case ISD::CTLZ_ZERO_POISON:
if ((Tmp1 = TLI.expandCTLZ(Node, DAG)))
Results.push_back(Tmp1);
break;
@@ -3270,7 +3270,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Results.push_back(Tmp1);
break;
case ISD::CTTZ:
- case ISD::CTTZ_ZERO_UNDEF:
+ case ISD::CTTZ_ZERO_POISON:
if ((Tmp1 = TLI.expandCTTZ(Node, DAG)))
Results.push_back(Tmp1);
break;
@@ -4623,7 +4623,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Results.push_back(TLI.expandVecReduce(Node, DAG));
break;
case ISD::VP_CTTZ_ELTS:
- case ISD::VP_CTTZ_ELTS_ZERO_UNDEF:
+ case ISD::VP_CTTZ_ELTS_ZERO_POISON:
Results.push_back(TLI.expandVPCTTZElements(Node, DAG));
break;
case ISD::CLEAR_CACHE:
@@ -5373,7 +5373,7 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
RTLIB::MUL_I16, RTLIB::MUL_I32,
RTLIB::MUL_I64, RTLIB::MUL_I128));
break;
- case ISD::CTLZ_ZERO_UNDEF:
+ case ISD::CTLZ_ZERO_POISON:
Results.push_back(ExpandBitCountingLibCall(
Node, RTLIB::CTLZ_I32, RTLIB::CTLZ_I64, RTLIB::CTLZ_I128));
break;
@@ -5510,12 +5510,12 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
SDValue Tmp1, Tmp2, Tmp3, Tmp4;
switch (Node->getOpcode()) {
case ISD::CTTZ:
- case ISD::CTTZ_ZERO_UNDEF:
+ case ISD::CTTZ_ZERO_POISON:
case ISD::CTLZ:
case ISD::CTPOP: {
// Zero extend the argument unless its cttz, then use any_extend.
if (Node->getOpcode() == ISD::CTTZ ||
- Node->getOpcode() == ISD::CTTZ_ZERO_UNDEF)
+ Node->getOpcode() == ISD::CTTZ_ZERO_POISON)
Tmp1 = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0));
else
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
@@ -5529,9 +5529,9 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
OVT.getSizeInBits());
Tmp1 = DAG.getNode(ISD::OR, dl, NVT, Tmp1,
DAG.getConstant(TopBit, dl, NVT));
- NewOpc = ISD::CTTZ_ZERO_UNDEF;
+ NewOpc = ISD::CTTZ_ZERO_POISON;
}
- // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
+ // Perform the larger operation. For CTPOP and CTTZ_ZERO_POISON, this is
// already the correct result.
Tmp1 = DAG.getNode(NewOpc, dl, NVT, Tmp1);
if (NewOpc == ISD::CTLZ) {
@@ -5544,7 +5544,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1, SDNodeFlags::NoWrap));
break;
}
- case ISD::CTLZ_ZERO_UNDEF: {
+ case ISD::CTLZ_ZERO_POISON: {
// We know that the argument is unlikely to be zero, hence we can take a
// different approach as compared to ISD::CTLZ
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index e7bf5a74cba34..070c366556186 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -66,21 +66,21 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
- case ISD::VP_CTLZ_ZERO_UNDEF:
+ case ISD::VP_CTLZ_ZERO_POISON:
case ISD::VP_CTLZ:
- case ISD::CTLZ_ZERO_UNDEF:
+ case ISD::CTLZ_ZERO_POISON:
case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
case ISD::CTLS: Res = PromoteIntRes_CTLS(N); break;
case ISD::PARITY:
case ISD::VP_CTPOP:
case ISD::CTPOP: Res = PromoteIntRes_CTPOP_PARITY(N); break;
- case ISD::VP_CTTZ_ZERO_UNDEF:
+ case ISD::VP_CTTZ_ZERO_POISON:
case ISD::VP_CTTZ:
- case ISD::CTTZ_ZERO_UNDEF:
+ case ISD::CTTZ_ZERO_POISON:
case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
case ISD::CTTZ_ELTS_ZERO_POISON:
case ISD::CTTZ_ELTS:
- case ISD::VP_CTTZ_ELTS_ZERO_UNDEF:
+ case ISD::VP_CTTZ_ELTS_ZERO_POISON:
case ISD::VP_CTTZ_ELTS:
Res = PromoteIntRes_VP_CttzElements(N);
break;
@@ -737,7 +737,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
// original type.
if (!OVT.isVector() && TLI.isTypeLegal(NVT) &&
!TLI.isOperationLegalOrCustomOrPromote(ISD::CTLZ, NVT) &&
- !TLI.isOperationLegalOrCustomOrPromote(ISD::CTLZ_ZERO_UNDEF, NVT)) {
+ !TLI.isOperationLegalOrCustomOrPromote(ISD::CTLZ_ZERO_POISON, NVT)) {
if (SDValue Result = TLI.expandCTLZ(N, DAG)) {
Result = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Result);
return Result;
@@ -765,8 +765,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
ExtractLeadingBits, Mask, EVL,
SDNodeFlags::NoUnsignedWrap);
}
- if (CtlzOpcode == ISD::CTLZ_ZERO_UNDEF ||
- CtlzOpcode == ISD::VP_CTLZ_ZERO_UNDEF) {
+ if (CtlzOpcode == ISD::CTLZ_ZERO_POISON ||
+ CtlzOpcode == ISD::VP_CTLZ_ZERO_POISON) {
// Any Extend the argument
SDValue Op = GetPromotedInteger(N->getOperand(0));
// Op = Op << (sizeinbits(NVT) - sizeinbits(Old VT))
@@ -839,7 +839,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
// larger type.
if (!OVT.isVector() && TLI.isTypeLegal(NVT) &&
!TLI.isOperationLegalOrCustomOrPromote(ISD::CTTZ, NVT) &&
- !TLI.isOperationLegalOrCustomOrPromote(ISD::CTTZ_ZERO_UNDEF, NVT) &&
+ !TLI.isOperationLegalOrCustomOrPromote(ISD::CTTZ_ZERO_POISON, NVT) &&
!TLI.isOperationLegal(ISD::CTPOP, NVT) &&
!TLI.isOperationLegal(ISD::CTLZ, NVT)) {
if (SDValue Result = TLI.expandCTTZ(N, DAG)) {
@@ -857,12 +857,12 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
OVT.getScalarSizeInBits());
if (NewOpc == ISD::CTTZ) {
Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT));
- NewOpc = ISD::CTTZ_ZERO_UNDEF;
+ NewOpc = ISD::CTTZ_ZERO_POISON;
} else {
Op =
DAG.getNode(ISD::VP_OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT),
N->getOperand(1), N->getOperand(2));
- NewOpc = ISD::VP_CTTZ_ZERO_UNDEF;
+ NewOpc = ISD::VP_CTTZ_ZERO_POISON;
}
}
if (!N->isVPOpcode())
@@ -3139,11 +3139,11 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::ABS: ExpandIntRes_ABS(N, Lo, Hi); break;
case ISD::ABDS:
case ISD::ABDU: ExpandIntRes_ABD(N, Lo, Hi); break;
- case ISD::CTLZ_ZERO_UNDEF:
+ case ISD::CTLZ_ZERO_POISON:
case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
case ISD::CTLS: ExpandIntRes_CTLS(N, Lo, Hi); break;
case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
- case ISD::CTTZ_ZERO_UNDEF:
+ case ISD::CTTZ_ZERO_POISON:
case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
case ISD::GET_ROUNDING:ExpandIntRes_GET_ROUNDING(N, Lo, Hi); break;
case ISD::STRICT_FP_TO_SINT:
@@ -4240,7 +4240,7 @@ void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
DAG.getConstant(0, dl, NVT), ISD::SETNE);
SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
- SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
+ SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_POISON, dl, NVT, Hi);
Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
@@ -4321,7 +4321,7 @@ void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
DAG.getConstant(0, dl, NVT), ISD::SETNE);
- SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
+ SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_POISON, dl, NVT, Lo);
SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index f054ab3fdc911..0a9c3dda7f330 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -389,8 +389,8 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
case ISD::BITREVERSE:
case ISD::CTLZ:
case ISD::CTTZ:
- case ISD::CTLZ_ZERO_UNDEF:
- case ISD::CTTZ_ZERO_UNDEF:
+ case ISD::CTLZ_ZERO_POISON:
+ case ISD::CTTZ_ZERO_POISON:
case ISD::CTPOP:
case ISD::CLMUL:
case ISD::CLMULH:
@@ -1151,28 +1151,28 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
}
break;
case ISD::CTLZ:
- case ISD::CTLZ_ZERO_UNDEF:
+ case ISD::CTLZ_ZERO_POISON:
if (SDValue Expanded = TLI.expandCTLZ(Node, DAG)) {
Results.push_back(Expanded);
return;
}
break;
case ISD::VP_CTLZ:
- case ISD::VP_CTLZ_ZERO_UNDEF:
+ case ISD::VP_CTLZ_ZERO_POISON:
if (SDValue Expanded = TLI.expandVPCTLZ(Node, DAG)) {
Results.push_back(Expanded);
return;
}
break;
case ISD::CTTZ:
- case ISD::CTTZ_ZERO_UNDEF:
+ case ISD::CTTZ_ZERO_POISON:
if (SDValue Expanded = TLI.expandCTTZ(Node, DAG)) {
Results.push_back(Expanded);
return;
}
break;
case ISD::VP_CTTZ:
- case ISD::VP_CTTZ_ZERO_UNDEF:
+ case ISD::VP_CTTZ_ZERO_POISON:
if (SDValue Expanded = TLI.expandVPCTTZ(Node, DAG)) {
Results.push_back(Expanded);
return;
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index cbd67675aab96..d363cf91f0e6c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -96,10 +96,10 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
case ISD::BITREVERSE:
case ISD::BSWAP:
case ISD::CTLZ:
- case ISD::CTLZ_ZERO_UNDEF:
+ case ISD::CTLZ_ZERO_POISON:
case ISD::CTPOP:
case ISD::CTTZ:
- case ISD::CTTZ_ZERO_UNDEF:
+ case ISD::CTTZ_ZERO_POISON:
case ISD::FABS:
case ISD::FACOS:
case ISD::FASIN:
@@ -1412,10 +1412,10 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
case ISD::VP_CTLZ:
case ISD::CTTZ:
case ISD::VP_CTTZ:
- case ISD::CTLZ_ZERO_UNDEF:
- case ISD::VP_CTLZ_ZERO_UNDEF:
- case ISD::CTTZ_ZERO_UNDEF:
- case ISD::VP_CTTZ_ZERO_UNDEF:
+ case ISD::CTLZ_ZERO_POISON:
+ case ISD::VP_CTLZ_ZERO_POISON:
+ case ISD::CTTZ_ZERO_POISON:
+ case ISD::VP_CTTZ_ZERO_POISON:
case ISD::CTPOP:
case ISD::VP_CTPOP:
case ISD::FABS: case ISD::VP_FABS:
@@ -3841,7 +3841,7 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
Res = SplitVecOp_CttzElts(N);
break;
case ISD::VP_CTTZ_ELTS:
- case ISD::VP_CTTZ_ELTS_ZERO_UNDEF:
+ case ISD::VP_CTTZ_ELTS_ZERO_POISON:
Res = SplitVecOp_VP_CttzElements(N);
break;
case ISD::EXPERIMENTAL_VECTOR_HISTOGRAM:
@@ -4967,7 +4967,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_VP_CttzElements(SDNode *N) {
SDValue VLo = DAG.getZExtOrTrunc(EVLLo, DL, ResVT);
// if VP_CTTZ_ELTS(Lo) != EVLLo => VP_CTTZ_ELTS(Lo).
- // else => EVLLo + (VP_CTTZ_ELTS(Hi) or VP_CTTZ_ELTS_ZERO_UNDEF(Hi)).
+ // else => EVLLo + (VP_CTTZ_ELTS(Hi) or VP_CTTZ_ELTS_ZERO_POISON(Hi)).
SDValue ResLo = DAG.getNode(ISD::VP_CTTZ_ELTS, DL, ResVT, Lo, MaskLo, EVLLo);
SDValue ResLoNotEVL =
DAG.getSetCC(DL, getSetCCResultType(ResVT), ResLo, VLo, ISD::SETNE);
@@ -5356,14 +5356,14 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
case ISD::VP_BSWAP:
case ISD::CTLZ:
case ISD::VP_CTLZ:
- case ISD::CTLZ_ZERO_UNDEF:
- case ISD::VP_CTLZ_ZERO_UNDEF:
+ case ISD::CTLZ_ZERO_POISON:
+ case ISD::VP_CTLZ_ZERO_POISON:
case ISD::CTPOP:
case ISD::VP_CTPOP:
case ISD::CTTZ:
case ISD::VP_CTTZ:
- case ISD::CTTZ_ZERO_UNDEF:
- case ISD::VP_CTTZ_ZERO_UNDEF:
+ case ISD::CTTZ_ZERO_POISON:
+ case ISD::VP_CTTZ_ZERO_POISON:
case ISD::FNEG: case ISD::VP_FNEG:
case ISD::FABS: case ISD::VP_FABS:
case ISD::VP_SQRT:
@@ -7500,7 +7500,7 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
Res = WidenVecOp_VP_REDUCE(N);
break;
case ISD::VP_CTTZ_ELTS:
- case ISD::VP_CTTZ_ELTS_ZERO_UNDEF:
+ case ISD::VP_CTTZ_ELTS_ZERO_POISON:
Res = WidenVecOp_VP_CttzElements(N);
break;
case ISD::VECTOR_FIND_LAST_ACTIVE:
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 0b7d8b7946f99..38e3df58a5384 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -3914,7 +3914,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
break;
}
case ISD::CTTZ:
- case ISD::CTTZ_ZERO_UNDEF: {
+ case ISD::CTTZ_ZERO_POISON: {
Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
// If we have a known 1, its position is our upper bound.
unsigned PossibleTZ = Known2.countMaxTrailingZeros();
@@ -3923,7 +3923,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
break;
}
case ISD::CTLZ:
- case ISD::CTLZ_ZERO_UNDEF: {
+ case ISD::CTLZ_ZERO_POISON: {
Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
// If we have a known 1, its position is our upper bound.
unsigned PossibleLZ = Known2.countMaxLeadingZeros();
@@ -5980,11 +5980,12 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
return includesPoison(Kind) &&
!getValidMaximumShiftAmount(Op, DemandedElts, Depth + 1);
- case ISD::CTTZ_ZERO_UNDEF:
- case ISD::CTLZ_ZERO_UNDEF:
+ case ISD::CTTZ_ZERO_POISON:
+ case ISD::CTLZ_ZERO_POISON:
// If the amount is zero then the result will be poison.
// TODO: Add isKnownNeverZero DemandedElts handling.
- return !isKnownNeverZero(Op.getOperand(0), Depth + 1);
+ return includesPoison(Kind) &&
+ !isKnownNeverZero(Op.getOperand(0), Depth + 1);
case ISD::SCALAR_TO_VECTOR:
// Check if we demand any upper (undef) elements.
@@ -7014,9 +7015,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
case ISD::BITREVERSE:
case ISD::BSWAP:
case ISD::CTLZ:
- case ISD::CTLZ_ZERO_UNDEF:
+ case ISD::CTLZ_ZERO_POISON:
case ISD::CTTZ:
- case ISD::CTTZ_ZERO_UNDEF:
+ case ISD::CTTZ_ZERO_POISON:
case ISD::CTPOP:
case ISD::CTLS:
case ISD::STEP_VECTOR: {
@@ -7551,11 +7552,11 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL,
return getConstant(Val.popcount(), DL, VT, C->isTargetOpcode(),
C->isOpaque());
case ISD::CTLZ:
- case ISD::CTLZ_ZERO_UNDEF:
+ case ISD::CTLZ_ZERO_POISON:
return getConstant(Val.countl_zero(), DL, VT, C->isTargetOpcode(),
C->isOpaque());
case ISD::CTTZ:
- case ISD::CTTZ_ZERO_UNDEF:
+ case ISD::CTTZ_ZERO_POISON:
return getConstant(Val.countr_zero(), DL, VT, C->isTargetOpcode(),
C->isOpaque());
case ISD::CTLS:
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 894f04bb4668d..e88a07901e289 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -7341,7 +7341,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
SDValue Arg = getValue(I.getArgOperand(0));
ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
EVT Ty = Arg.getValueType();
- setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
+ setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_POISON,
sdl, Ty, Arg));
return;
}
@@ -7349,7 +7349,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
SDValue Arg = getValue(I.getArgOperand(0));
ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
EVT Ty = Arg.getValueType();
- setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
+ setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_POISON,
sdl, Ty, Arg));
return;
}
@@ -8622,17 +8622,17 @@ static unsigned getISDForVPIntrinsic(const VPIntrinsic &VPIntrin) {
switch (VPIntrin.getIntrinsicID()) {
case Intrinsic::vp_ctlz: {
bool IsZeroUndef = cast<ConstantInt>(VPIntrin.getArgOperand(1))->isOne();
- ResOPC = IsZeroUndef ? ISD::VP_CTLZ_ZERO_UNDEF : ISD::VP_CTLZ;
+ ResOPC = IsZeroUndef ? ISD::VP_CTLZ_ZERO_POISON : ISD::VP_CTLZ;
break;
}
case Intrinsic::vp_cttz: {
bool IsZeroUndef = cast<ConstantInt>(VPIntrin.getArgOperand(1))->isOne();
- ResOPC = IsZeroUndef ? ISD::VP_CTTZ_ZERO_UNDEF : ISD::VP_CTTZ;
+ ResOPC = IsZeroUndef ? ISD::VP_CTTZ_ZERO_POISON : ISD::VP_CTTZ;
break;
}
case Intrinsic::vp_cttz_elts: {
bool IsZeroPoison = cast<ConstantInt>(VPIntrin.getArgOperand(1))->isOne();
- ResOPC = IsZeroPoison ? ISD::VP_CTTZ_ELTS_ZERO_UNDEF : ISD::VP_CTTZ_ELTS;
+ ResOPC = IsZeroPoison ? ISD::VP_CTTZ_ELTS_ZERO_POISON : ISD::VP_CTTZ_ELTS;
break;
}
#define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD) \
@@ -9025,10 +9025,10 @@ void SelectionDAGBuilder::visitVectorPredicationIntrinsic(
}
case ISD::VP_ABS:
case ISD::VP_CTLZ:
- case ISD::VP_CTLZ_ZERO_UNDEF:
+ case ISD::VP_CTLZ_ZERO_POISON:
case ISD::VP_CTTZ:
- case ISD::VP_CTTZ_ZERO_UNDEF:
- case ISD::VP_CTTZ_ELTS_ZERO_UNDEF:
+ case ISD::VP_CTTZ_ZERO_POISON:
+ case ISD::VP_CTTZ_ELTS_ZERO_POISON:
case ISD::VP_CTTZ_ELTS: {
SDValue Result =
DAG.getNode(Opcode, DL, VTs, {OpValues[0], OpValues[2], OpValues[3]});
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
index ce78072d21114..4aab651978bce 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
@@ -521,9 +521,9 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::BSWAP: return "bswap";
case ISD::CTPOP: return "ctpop";
case ISD::CTTZ: return "cttz";
- case ISD::CTTZ_ZERO_UNDEF: return "cttz_zero_undef";
+ case ISD::CTTZ_ZERO_POISON: return "cttz_zero_poison";
case ISD::CTLZ: return "ctlz";
- case ISD::CTLZ_ZERO_UNDEF: return "ctlz_zero_undef";
+ case ISD::CTLZ_ZERO_POISON: return "ctlz_zero_poison";
case ISD::CTLS: return "ctls";
case ISD::PARITY: return "parity";
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 7161caab53da3..ce1493200b9b1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -9161,7 +9161,7 @@ TargetLowering::expandCONVERT_FROM_ARBITRARY_FP(SDNode *Node,
{
const unsigned IntVTBits = DstBits;
SDValue LeadingZeros =
- DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, IntVT, MantField);
+ DAG.getNode(ISD::CTLZ_ZERO_POISON, dl, IntVT, MantField);
const int DenormExpConst =
(int)IntVTBits + DstBias - SrcBias - (int)SrcMant;
@@ -10225,16 +10225,16 @@ SDValue TargetLowering::expandCTLZ(SDNode *Node, SelectionDAG &DAG) const {
SDValue Op = Node->getOperand(0);
unsigned NumBitsPerElt = VT.getScalarSizeInBits();
- // If the non-ZERO_UNDEF version is supported we can use that instead.
- if (Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF &&
+ // If the non-ZERO_POISON version is supported we can use that instead.
+ if (Node->getOpcode() == ISD::CTLZ_ZERO_POISON &&
isOperationLegalOrCustom(ISD::CTLZ, VT))
return DAG.getNode(ISD::CTLZ, dl, VT, Op);
- // If the ZERO_UNDEF version is supported use that and handle the zero case.
- if (isOperationLegalOrCustom(ISD::CTLZ_ZERO_UNDEF, VT)) {
+ // If the ZERO_POISON version is supported use that and handle the zero case.
+ if (isOperationLegalOrCustom(ISD::CTLZ_ZERO_POISON, VT)) {
EVT SetCCVT =
getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
- SDValue CTLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, VT, Op);
+ SDValue CTLZ = DAG.getNode(ISD::CTLZ_ZERO_POISON, dl, VT, Op);
SDValue Zero = DAG.getConstant(0, dl, VT);
SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ);
return DAG.getSelect(dl, VT, SrcIsZero,
@@ -10309,7 +10309,7 @@ SDValue TargetLowering::expandCTLS(SDNode *Node, SelectionDAG &DAG) const {
SDValue Shl =
DAG.getNode(ISD::SHL, dl, VT, Xor, DAG.getShiftAmountConstant(1, VT, dl));
SDValue Or = DAG.getNode(ISD::OR, dl, VT, Shl, DAG.getConstant(1, dl, VT));
- return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, VT, Or);
+ return DAG.getNode(ISD::CTLZ_ZERO_POISON, dl, VT, Or);
}
SDValue TargetLowering::CTTZTableLookup(SDNode *Node, SelectionDAG &DAG,
@@ -10349,7 +10349,7 @@ SDValue TargetLowering::CTTZTableLookup(SDNode *Node, SelectionDAG &DAG,
SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, VT, DAG.getEntryNode(),
DAG.getMemBasePlusOffset(CPIdx, Lookup, DL),
PtrInfo, MVT::i8);
- if (Node->getOpcode() == ISD::CTTZ_ZERO_UNDEF)
+ if (Node->getOpcode() == ISD::CTTZ_ZERO_POISON)
return ExtLoad;
EVT SetCCVT =
@@ -10366,16 +10366,16 @@ SDValue TargetLowering::expandCTTZ(SDNode *Node, SelectionDAG &DAG) const {
SDValue Op = Node->getOperand(0);
unsigned NumBitsPerElt = VT.getScalarSizeInBits();
- // If the non-ZERO_UNDEF version is supported we can use that instead.
- if (Node->getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
+ // If the non-ZERO_POISON version is supported we can use that instead.
+ if (Node->getOpcode() == ISD::CTTZ_ZERO_POISON &&
isOperationLegalOrCustom(ISD::CTTZ, VT))
return DAG.getNode(ISD::CTTZ, dl, VT, Op);
- // If the ZERO_UNDEF version is supported use that and handle the zero case.
- if (isOperationLegalOrCustom(ISD::CTTZ_ZERO_UNDEF, VT)) {
+ // If the ZERO_POISON version is supported use that and handle the zero case.
+ if (isOperationLegalOrCustom(ISD::CTTZ_ZERO_POISON, VT)) {
EVT SetCCVT =
getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
- SDValue CTTZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, VT, Op);
+ SDValue CTTZ = DAG.getNode(ISD::CTTZ_ZERO_POISON, dl, VT, Op);
SDValue Zero = DAG.getConstant(0, dl, VT);
SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ);
return DAG.getSelect(dl, VT, SrcIsZero,
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 7dcdf7f952e27..e50e1832e37a6 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -1194,7 +1194,7 @@ void TargetLoweringBase::initActions() {
setOperationAction(ISD::TRUNCATE_USAT_U, VT, Expand);
// These default to Expand so they will be expanded to CTLZ/CTTZ by default.
- setOperationAction({ISD::CTLZ_ZERO_UNDEF, ISD::CTTZ_ZERO_UNDEF}, VT,
+ setOperationAction({ISD::CTLZ_ZERO_POISON, ISD::CTTZ_ZERO_POISON}, VT,
Expand);
setOperationAction(ISD::CTLS, VT, Expand);
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 7d87847d7fc67..14a3f7547fb09 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -397,7 +397,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.scalarizeIf(scalarOrEltWiderThan(0, 32), 0)
.scalarSameSizeAs(0, 1);
- getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF).lower();
+ getActionDefinitionsBuilder(G_CTLZ_ZERO_POISON).lower();
getActionDefinitionsBuilder(G_CTTZ)
.lowerIf(isVector(0))
@@ -407,7 +407,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.legalFor(HasCSSC, {s32, s64})
.customFor(!HasCSSC, {s32, s64});
- getActionDefinitionsBuilder(G_CTTZ_ZERO_UNDEF).lower();
+ getActionDefinitionsBuilder(G_CTTZ_ZERO_POISON).lower();
getActionDefinitionsBuilder(G_BITREVERSE)
.legalFor({i32, i64, v8i8, v16i8})
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 058ca9c29625f..34e85ed2aa170 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -514,11 +514,11 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
Legal);
setOperationAction(
- {ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF},
+ {ISD::CTTZ, ISD::CTTZ_ZERO_POISON, ISD::CTLZ, ISD::CTLZ_ZERO_POISON},
MVT::i64, Custom);
for (auto VT : {MVT::i8, MVT::i16})
- setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, VT, Custom);
+ setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_POISON}, VT, Custom);
static const MVT::SimpleValueType VectorIntTypes[] = {
MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32, MVT::v6i32, MVT::v7i32,
@@ -1475,9 +1475,9 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
case ISD::FP_TO_UINT_SAT:
return LowerFP_TO_INT_SAT(Op, DAG);
case ISD::CTTZ:
- case ISD::CTTZ_ZERO_UNDEF:
+ case ISD::CTTZ_ZERO_POISON:
case ISD::CTLZ:
- case ISD::CTLZ_ZERO_UNDEF:
+ case ISD::CTLZ_ZERO_POISON:
return LowerCTLZ_CTTZ(Op, DAG);
case ISD::CTLS:
return LowerCTLS(Op, DAG);
@@ -1517,7 +1517,7 @@ void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
Results.push_back(Lowered);
return;
case ISD::CTLZ:
- case ISD::CTLZ_ZERO_UNDEF:
+ case ISD::CTLZ_ZERO_POISON:
if (auto Lowered = lowerCTLZResults(SDValue(N, 0u), DAG))
Results.push_back(Lowered);
return;
@@ -3329,11 +3329,11 @@ SDValue AMDGPUTargetLowering::lowerFEXP(SDValue Op, SelectionDAG &DAG) const {
}
static bool isCtlzOpc(unsigned Opc) {
- return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF;
+ return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_POISON;
}
static bool isCttzOpc(unsigned Opc) {
- return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_UNDEF;
+ return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_POISON;
}
SDValue AMDGPUTargetLowering::lowerCTLZResults(SDValue Op,
@@ -3353,7 +3353,7 @@ SDValue AMDGPUTargetLowering::lowerCTLZResults(SDValue Op,
SDValue NumExtBits = DAG.getConstant(32u - NumBits, SL, MVT::i32);
SDValue NewOp;
- if (Opc == ISD::CTLZ_ZERO_UNDEF) {
+ if (Opc == ISD::CTLZ_ZERO_POISON) {
NewOp = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Arg);
NewOp = DAG.getNode(ISD::SHL, SL, MVT::i32, NewOp, NumExtBits);
NewOp = DAG.getNode(Opc, SL, MVT::i32, NewOp);
@@ -3374,21 +3374,21 @@ SDValue AMDGPUTargetLowering::LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) cons
bool Ctlz = isCtlzOpc(Op.getOpcode());
unsigned NewOpc = Ctlz ? AMDGPUISD::FFBH_U32 : AMDGPUISD::FFBL_B32;
- bool ZeroUndef = Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF ||
- Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF;
+ bool ZeroUndef = Op.getOpcode() == ISD::CTLZ_ZERO_POISON ||
+ Op.getOpcode() == ISD::CTTZ_ZERO_POISON;
bool Is64BitScalar = !Src->isDivergent() && Src.getValueType() == MVT::i64;
if (Src.getValueType() == MVT::i32 || Is64BitScalar) {
// (ctlz hi:lo) -> (umin (ffbh src), 32)
// (cttz hi:lo) -> (umin (ffbl src), 32)
- // (ctlz_zero_undef src) -> (ffbh src)
- // (cttz_zero_undef src) -> (ffbl src)
+ // (ctlz_zero_poison src) -> (ffbh src)
+ // (cttz_zero_poison src) -> (ffbl src)
// 64-bit scalar version produce 32-bit result
// (ctlz hi:lo) -> (umin (S_FLBIT_I32_B64 src), 64)
// (cttz hi:lo) -> (umin (S_FF1_I32_B64 src), 64)
- // (ctlz_zero_undef src) -> (S_FLBIT_I32_B64 src)
- // (cttz_zero_undef src) -> (S_FF1_I32_B64 src)
+ // (ctlz_zero_poison src) -> (S_FLBIT_I32_B64 src)
+ // (cttz_zero_poison src) -> (S_FF1_I32_B64 src)
SDValue NewOpr = DAG.getNode(NewOpc, SL, MVT::i32, Src);
if (!ZeroUndef) {
const SDValue ConstVal = DAG.getConstant(
@@ -3406,8 +3406,8 @@ SDValue AMDGPUTargetLowering::LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) cons
// (ctlz hi:lo) -> (umin3 (ffbh hi), (uaddsat (ffbh lo), 32), 64)
// (cttz hi:lo) -> (umin3 (uaddsat (ffbl hi), 32), (ffbl lo), 64)
- // (ctlz_zero_undef hi:lo) -> (umin (ffbh hi), (add (ffbh lo), 32))
- // (cttz_zero_undef hi:lo) -> (umin (add (ffbl hi), 32), (ffbl lo))
+ // (ctlz_zero_poison hi:lo) -> (umin (ffbh hi), (add (ffbh lo), 32))
+ // (cttz_zero_poison hi:lo) -> (umin (add (ffbl hi), 32), (ffbl lo))
unsigned AddOpc = ZeroUndef ? ISD::ADD : ISD::UADDSAT;
const SDValue Const32 = DAG.getConstant(32, SL, MVT::i32);
@@ -4994,8 +4994,8 @@ SDValue AMDGPUTargetLowering::performCtlz_CttzCombine(const SDLoc &SL, SDValue C
ISD::CondCode CCOpcode = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
SDValue CmpLHS = Cond.getOperand(0);
- // select (setcc x, 0, eq), -1, (ctlz_zero_undef x) -> ffbh_u32 x
- // select (setcc x, 0, eq), -1, (cttz_zero_undef x) -> ffbl_u32 x
+ // select (setcc x, 0, eq), -1, (ctlz_zero_poison x) -> ffbh_u32 x
+ // select (setcc x, 0, eq), -1, (cttz_zero_poison x) -> ffbl_u32 x
if (CCOpcode == ISD::SETEQ &&
(isCtlzOpc(RHS.getOpcode()) || isCttzOpc(RHS.getOpcode())) &&
RHS.getOperand(0) == CmpLHS && isAllOnesConstant(LHS)) {
@@ -5004,8 +5004,8 @@ SDValue AMDGPUTargetLowering::performCtlz_CttzCombine(const SDLoc &SL, SDValue C
return getFFBX_U32(DAG, CmpLHS, SL, Opc);
}
- // select (setcc x, 0, ne), (ctlz_zero_undef x), -1 -> ffbh_u32 x
- // select (setcc x, 0, ne), (cttz_zero_undef x), -1 -> ffbl_u32 x
+ // select (setcc x, 0, ne), (ctlz_zero_poison x), -1 -> ffbh_u32 x
+ // select (setcc x, 0, ne), (cttz_zero_poison x), -1 -> ffbl_u32 x
if (CCOpcode == ISD::SETNE &&
(isCtlzOpc(LHS.getOpcode()) || isCttzOpc(LHS.getOpcode())) &&
LHS.getOperand(0) == CmpLHS && isAllOnesConstant(RHS)) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
index 1b9a8869d18b6..ae6546939d0a7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
@@ -495,11 +495,11 @@ def AMDGPUdiv_fixup : PatFrags<(ops node:$src0, node:$src1, node:$src2),
def AMDGPUffbh_u32 : PatFrags<(ops node:$src),
- [(ctlz_zero_undef node:$src),
+ [(ctlz_zero_poison node:$src),
(AMDGPUffbh_u32_impl node:$src)]>;
def AMDGPUffbl_b32 : PatFrags<(ops node:$src),
- [(cttz_zero_undef node:$src),
+ [(cttz_zero_poison node:$src),
(AMDGPUffbl_b32_impl node:$src)]>;
def AMDGPUpkrtz_f16_f32 : PatFrags<(ops node:$src0, node:$src1),
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 36365111f15a1..43db1ead84c80 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -1376,7 +1376,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.custom();
// The 64-bit versions produce 32-bit results, but only on the SALU.
- getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
+ getActionDefinitionsBuilder(G_CTLZ_ZERO_POISON)
.legalFor({{S32, S32}, {S32, S64}})
.customIf(scalarNarrowerThan(1, 32))
.clampScalar(0, S32, S32)
@@ -1385,7 +1385,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.widenScalarToNextPow2(0, 32)
.widenScalarToNextPow2(1, 32);
- getActionDefinitionsBuilder(G_CTTZ_ZERO_UNDEF)
+ getActionDefinitionsBuilder(G_CTTZ_ZERO_POISON)
.legalFor({{S32, S32}, {S32, S64}})
.clampScalar(0, S32, S32)
.clampScalar(1, S32, S64)
@@ -2324,8 +2324,8 @@ bool AMDGPULegalizerInfo::legalizeCustom(
return legalizeCTLZ_CTTZ(MI, MRI, B);
case TargetOpcode::G_CTLS:
return legalizeCTLS(MI, MRI, B);
- case TargetOpcode::G_CTLZ_ZERO_UNDEF:
- return legalizeCTLZ_ZERO_UNDEF(MI, MRI, B);
+ case TargetOpcode::G_CTLZ_ZERO_POISON:
+ return legalizeCTLZ_ZERO_POISON(MI, MRI, B);
case TargetOpcode::G_STACKSAVE:
return legalizeStackSave(MI, B);
case TargetOpcode::G_GET_FPENV:
@@ -4658,7 +4658,7 @@ bool AMDGPULegalizerInfo::legalizeMul(LegalizerHelper &Helper,
}
// Legalize ctlz/cttz to ffbh/ffbl instead of the default legalization to
-// ctlz/cttz_zero_undef. This allows us to fix up the result for the zero input
+// ctlz/cttz_zero_poison. This allows us to fix up the result for the zero input
// case with a single min instruction instead of a compare+select.
bool AMDGPULegalizerInfo::legalizeCTLZ_CTTZ(MachineInstr &MI,
MachineRegisterInfo &MRI,
@@ -4678,9 +4678,9 @@ bool AMDGPULegalizerInfo::legalizeCTLZ_CTTZ(MachineInstr &MI,
return true;
}
-bool AMDGPULegalizerInfo::legalizeCTLZ_ZERO_UNDEF(MachineInstr &MI,
- MachineRegisterInfo &MRI,
- MachineIRBuilder &B) const {
+bool AMDGPULegalizerInfo::legalizeCTLZ_ZERO_POISON(MachineInstr &MI,
+ MachineRegisterInfo &MRI,
+ MachineIRBuilder &B) const {
Register Dst = MI.getOperand(0).getReg();
Register Src = MI.getOperand(1).getReg();
LLT SrcTy = MRI.getType(Src);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
index 36ce5d9740762..53cd6d786ee2f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
@@ -117,8 +117,8 @@ class AMDGPULegalizerInfo final : public LegalizerInfo {
bool legalizeMul(LegalizerHelper &Helper, MachineInstr &MI) const;
bool legalizeCTLZ_CTTZ(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
- bool legalizeCTLZ_ZERO_UNDEF(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &B) const;
+ bool legalizeCTLZ_ZERO_POISON(MachineInstr &MI, MachineRegisterInfo &MRI,
+ MachineIRBuilder &B) const;
bool legalizeCTLS(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 090ffed1e1e53..a6e302d48c008 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -828,12 +828,12 @@ bool RegBankLegalizeHelper::lowerSplitBitCount64To32(MachineInstr &MI) {
// Split 64-bit find-first-bit operations into 32-bit halves:
// (ffbh hi:lo) -> umin(ffbh(hi), uaddsat(ffbh(lo), 32))
// (ffbl hi:lo) -> umin(ffbl(lo), uaddsat(ffbl(hi), 32))
- // (ctlz_zero_undef hi:lo) -> umin(ffbh(hi), add(ffbh(lo), 32))
- // (cttz_zero_undef hi:lo) -> umin(ffbl(lo), add(ffbl(hi), 32))
+ // (ctlz_zero_poison hi:lo) -> umin(ffbh(hi), add(ffbh(lo), 32))
+ // (cttz_zero_poison hi:lo) -> umin(ffbl(lo), add(ffbl(hi), 32))
unsigned Opc = MI.getOpcode();
// FFBH/FFBL return 0xFFFFFFFF on zero input, using uaddsat to avoid
- // wrapping. CTLZ/CTTZ guarantee non-zero input (zero_undef), so plain add
+ // wrapping. CTLZ/CTTZ guarantee non-zero input (zero_poison), so plain add
// is fine.
unsigned FFBOpc;
unsigned AddOpc;
@@ -849,12 +849,12 @@ bool RegBankLegalizeHelper::lowerSplitBitCount64To32(MachineInstr &MI) {
AddOpc = AMDGPU::G_UADDSAT;
SearchFromMSB = false;
break;
- case AMDGPU::G_CTLZ_ZERO_UNDEF:
+ case AMDGPU::G_CTLZ_ZERO_POISON:
FFBOpc = AMDGPU::G_AMDGPU_FFBH_U32;
AddOpc = AMDGPU::G_ADD;
SearchFromMSB = true;
break;
- case AMDGPU::G_CTTZ_ZERO_UNDEF:
+ case AMDGPU::G_CTTZ_ZERO_POISON:
FFBOpc = AMDGPU::G_AMDGPU_FFBL_B32;
AddOpc = AMDGPU::G_ADD;
SearchFromMSB = false;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 5cc0d073df17b..061b8dc070ead 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1284,8 +1284,8 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S64, {{Sgpr64}, {Sgpr64}})
.Div(S64, {{Vgpr64}, {Vgpr64}});
- addRulesForGOpcs({G_AMDGPU_FFBH_U32, G_AMDGPU_FFBL_B32, G_CTLZ_ZERO_UNDEF,
- G_CTTZ_ZERO_UNDEF})
+ addRulesForGOpcs({G_AMDGPU_FFBH_U32, G_AMDGPU_FFBL_B32, G_CTLZ_ZERO_POISON,
+ G_CTTZ_ZERO_POISON})
.Any({{UniS32, S32}, {{Sgpr32}, {Sgpr32}}})
.Any({{DivS32, S32}, {{Vgpr32}, {Vgpr32}}})
.Any({{UniS32, S64}, {{Sgpr32}, {Sgpr64}}})
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index ebdd709c34f08..15eae3cd6d088 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -2707,8 +2707,8 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
}
case AMDGPU::G_AMDGPU_FFBH_U32:
case AMDGPU::G_AMDGPU_FFBL_B32:
- case AMDGPU::G_CTLZ_ZERO_UNDEF:
- case AMDGPU::G_CTTZ_ZERO_UNDEF: {
+ case AMDGPU::G_CTLZ_ZERO_POISON:
+ case AMDGPU::G_CTTZ_ZERO_POISON: {
const RegisterBank *DstBank =
OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
if (DstBank == &AMDGPU::SGPRRegBank)
@@ -2722,22 +2722,22 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
// We can narrow this more efficiently than Helper can by using ffbh/ffbl
// which return -1 when the input is zero:
- // (ctlz_zero_undef hi:lo) -> (umin (ffbh hi), (add (ffbh lo), 32))
- // (cttz_zero_undef hi:lo) -> (umin (add (ffbl hi), 32), (ffbl lo))
+ // (ctlz_zero_poison hi:lo) -> (umin (ffbh hi), (add (ffbh lo), 32))
+ // (cttz_zero_poison hi:lo) -> (umin (add (ffbl hi), 32), (ffbl lo))
// (ffbh hi:lo) -> (umin (ffbh hi), (uaddsat (ffbh lo), 32))
// (ffbl hi:lo) -> (umin (uaddsat (ffbh hi), 32), (ffbh lo))
ApplyRegBankMapping ApplyVALU(B, *this, MRI, &AMDGPU::VGPRRegBank);
SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1));
- unsigned NewOpc = Opc == AMDGPU::G_CTLZ_ZERO_UNDEF
+ unsigned NewOpc = Opc == AMDGPU::G_CTLZ_ZERO_POISON
? (unsigned)AMDGPU::G_AMDGPU_FFBH_U32
- : Opc == AMDGPU::G_CTTZ_ZERO_UNDEF
- ? (unsigned)AMDGPU::G_AMDGPU_FFBL_B32
- : Opc;
+ : Opc == AMDGPU::G_CTTZ_ZERO_POISON
+ ? (unsigned)AMDGPU::G_AMDGPU_FFBL_B32
+ : Opc;
unsigned Idx = NewOpc == AMDGPU::G_AMDGPU_FFBH_U32;
auto X = B.buildInstr(NewOpc, {S32}, {SrcRegs[Idx]});
auto Y = B.buildInstr(NewOpc, {S32}, {SrcRegs[Idx ^ 1]});
unsigned AddOpc =
- Opc == AMDGPU::G_CTLZ_ZERO_UNDEF || Opc == AMDGPU::G_CTTZ_ZERO_UNDEF
+ Opc == AMDGPU::G_CTLZ_ZERO_POISON || Opc == AMDGPU::G_CTTZ_ZERO_POISON
? AMDGPU::G_ADD
: AMDGPU::G_UADDSAT;
Y = B.buildInstr(AddOpc, {S32}, {Y, B.buildConstant(S32, 32)});
@@ -4294,8 +4294,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
}
case AMDGPU::G_AMDGPU_FFBH_U32:
case AMDGPU::G_AMDGPU_FFBL_B32:
- case AMDGPU::G_CTLZ_ZERO_UNDEF:
- case AMDGPU::G_CTTZ_ZERO_UNDEF: {
+ case AMDGPU::G_CTLZ_ZERO_POISON:
+ case AMDGPU::G_CTTZ_ZERO_POISON: {
unsigned Size = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI);
OpdsMapping[0] = AMDGPU::getValueMapping(BankID, 32);
diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
index 4ebe154166b3f..ae8e73eb5f329 100644
--- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -177,10 +177,10 @@ R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::CTPOP, MVT::i64, Expand);
if (Subtarget->hasFFBH())
- setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom);
+ setOperationAction(ISD::CTLZ_ZERO_POISON, MVT::i32, Custom);
if (Subtarget->hasFFBL())
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Custom);
+ setOperationAction(ISD::CTTZ_ZERO_POISON, MVT::i32, Custom);
// FIXME: This was moved from AMDGPUTargetLowering, I'm not sure if we
// need it for R600.
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 95b214f0da4c8..8b89366f89c5a 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -518,8 +518,8 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
if (Subtarget->hasMadMacF32Insts())
setOperationAction(ISD::FMAD, MVT::f32, Legal);
- setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i32, Custom);
- setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF}, MVT::i32, Custom);
+ setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_POISON}, MVT::i32, Custom);
+ setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_POISON}, MVT::i32, Custom);
setOperationAction(ISD::CTLS, MVT::i32, Custom);
// We only really have 32-bit BFE instructions (and 16-bit on VI).
@@ -592,7 +592,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
setOperationAction({ISD::SIGN_EXTEND, ISD::SDIV, ISD::UDIV, ISD::SREM,
ISD::UREM, ISD::BITREVERSE, ISD::CTTZ,
- ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF,
+ ISD::CTTZ_ZERO_POISON, ISD::CTLZ, ISD::CTLZ_ZERO_POISON,
ISD::CTPOP},
MVT::i16, Promote);
@@ -17420,7 +17420,7 @@ SDValue SITargetLowering::performPtrAddCombine(SDNode *N,
}
static bool isCtlzOpc(unsigned Opc) {
- return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF;
+ return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_POISON;
}
SDValue SITargetLowering::performSubCombine(SDNode *N,
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index ff8df9b33b3cc..259467f78afb4 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -775,15 +775,15 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
+ setOperationAction(ISD::CTTZ_ZERO_POISON, MVT::v8i8, Custom);
+ setOperationAction(ISD::CTTZ_ZERO_POISON, MVT::v4i16, Custom);
+ setOperationAction(ISD::CTTZ_ZERO_POISON, MVT::v2i32, Custom);
+ setOperationAction(ISD::CTTZ_ZERO_POISON, MVT::v1i64, Custom);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
+ setOperationAction(ISD::CTTZ_ZERO_POISON, MVT::v16i8, Custom);
+ setOperationAction(ISD::CTTZ_ZERO_POISON, MVT::v8i16, Custom);
+ setOperationAction(ISD::CTTZ_ZERO_POISON, MVT::v4i32, Custom);
+ setOperationAction(ISD::CTTZ_ZERO_POISON, MVT::v2i64, Custom);
for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
setOperationAction(ISD::MULHS, VT, Expand);
@@ -1025,7 +1025,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
setOperationAction(ISD::CTPOP, MVT::i64, Expand);
if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
setOperationAction(ISD::CTLZ, MVT::i32, Expand);
- setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall);
+ setOperationAction(ISD::CTLZ_ZERO_POISON, MVT::i32, LibCall);
}
// @llvm.readcyclecounter requires the Performance Monitors extension.
@@ -6285,7 +6285,7 @@ static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
}
if ((ElemTy == MVT::i16 || ElemTy == MVT::i32) &&
- (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) {
+ (N->getOpcode() == ISD::CTTZ_ZERO_POISON)) {
// Compute with: cttz(x) = (width - 1) - ctlz(lsb), if x != 0
unsigned NumBits = ElemTy.getSizeInBits();
SDValue WidthMinus1 =
@@ -10466,7 +10466,7 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::SRL_PARTS:
case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
case ISD::CTTZ:
- case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
+ case ISD::CTTZ_ZERO_POISON: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
case ISD::SETCC: return LowerVSETCC(Op, DAG, Subtarget);
case ISD::SETCCCARRY: return LowerSETCCCARRY(Op, DAG);
diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
index ad3e4f116321b..8b334fe84be45 100644
--- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -211,12 +211,12 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) : ST(ST) {
.legalFor({s32, s32})
.clampScalar(1, s32, s32)
.clampScalar(0, s32, s32);
- getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
+ getActionDefinitionsBuilder(G_CTLZ_ZERO_POISON)
.lowerFor({s32, s32})
.clampScalar(1, s32, s32)
.clampScalar(0, s32, s32);
} else {
- getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
+ getActionDefinitionsBuilder(G_CTLZ_ZERO_POISON)
.libcallFor({s32, s32})
.clampScalar(1, s32, s32)
.clampScalar(0, s32, s32);
diff --git a/llvm/lib/Target/BPF/BPFISelLowering.cpp b/llvm/lib/Target/BPF/BPFISelLowering.cpp
index 6ffa9d1693bc0..a05e7d48ec6be 100644
--- a/llvm/lib/Target/BPF/BPFISelLowering.cpp
+++ b/llvm/lib/Target/BPF/BPFISelLowering.cpp
@@ -132,8 +132,8 @@ BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::CTPOP, VT, Expand);
setOperationAction(ISD::CTTZ, VT, Expand);
setOperationAction(ISD::CTLZ, VT, Expand);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
- setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
+ setOperationAction(ISD::CTTZ_ZERO_POISON, VT, Expand);
+ setOperationAction(ISD::CTLZ_ZERO_POISON, VT, Expand);
setOperationAction(ISD::SETCC, VT, Expand);
setOperationAction(ISD::SELECT, VT, Expand);
diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
index e487d80e845f5..95074a1efc2ef 100644
--- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -259,14 +259,14 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
.legalFor({{s32, s32}})
.maxScalar(0, s32)
.maxScalar(1, s32);
- getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
+ getActionDefinitionsBuilder(G_CTLZ_ZERO_POISON)
.lowerFor({{s32, s32}});
getActionDefinitionsBuilder(G_CTTZ)
.lowerFor({{s32, s32}})
.maxScalar(0, s32)
.maxScalar(1, s32);
- getActionDefinitionsBuilder(G_CTTZ_ZERO_UNDEF)
+ getActionDefinitionsBuilder(G_CTTZ_ZERO_POISON)
.lowerFor({{s32, s32}, {s64, s64}});
getActionDefinitionsBuilder(G_CTPOP)
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index edd372a9db344..bc673859ff03f 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -805,7 +805,7 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
setOperationAction({ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX},
{MVT::i16, MVT::i32, MVT::i64}, Legal);
- setOperationAction({ISD::CTPOP, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i16,
+ setOperationAction({ISD::CTPOP, ISD::CTLZ, ISD::CTLZ_ZERO_POISON}, MVT::i16,
Promote);
setOperationAction({ISD::CTPOP, ISD::CTLZ}, MVT::i32, Legal);
setOperationAction({ISD::CTPOP, ISD::CTLZ}, MVT::i64, Custom);
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index b7efee8bf4c83..6a690402696e6 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -219,8 +219,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
BSWAPActions.maxScalar(0, sXLen).lower();
auto &CountZerosActions = getActionDefinitionsBuilder({G_CTLZ, G_CTTZ});
- auto &CountZerosUndefActions =
- getActionDefinitionsBuilder({G_CTLZ_ZERO_UNDEF, G_CTTZ_ZERO_UNDEF});
+ auto &CountZerosPoisonActions =
+ getActionDefinitionsBuilder({G_CTLZ_ZERO_POISON, G_CTTZ_ZERO_POISON});
if (ST.hasStdExtZbb()) {
CountZerosActions.legalFor({{sXLen, sXLen}})
.customFor({{s32, s32}})
@@ -229,9 +229,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.scalarSameSizeAs(1, 0);
} else {
CountZerosActions.maxScalar(0, sXLen).scalarSameSizeAs(1, 0).lower();
- CountZerosUndefActions.maxScalar(0, sXLen).scalarSameSizeAs(1, 0);
+ CountZerosPoisonActions.maxScalar(0, sXLen).scalarSameSizeAs(1, 0);
}
- CountZerosUndefActions.lower();
+ CountZerosPoisonActions.lower();
auto &CountSignActions = getActionDefinitionsBuilder(G_CTLS);
if (ST.hasStdExtP()) {
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2191d189fea49..93e820b4713ec 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -427,7 +427,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
if (Subtarget.hasCTZLike()) {
if (Subtarget.is64Bit())
- setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF}, MVT::i32, Custom);
+ setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_POISON}, MVT::i32, Custom);
} else {
setOperationAction(ISD::CTTZ, XLenVT, Expand);
}
@@ -448,7 +448,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
// Use default promotion for i32 without Zbb.
if (Subtarget.is64Bit() &&
(Subtarget.hasStdExtZbb() || Subtarget.hasStdExtP()))
- setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i32, Custom);
+ setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_POISON}, MVT::i32, Custom);
} else {
setOperationAction(ISD::CTLZ, XLenVT, Expand);
}
@@ -873,7 +873,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::VP_REDUCE_SMIN, ISD::VP_REDUCE_UMAX, ISD::VP_REDUCE_UMIN,
ISD::VP_MERGE,
ISD::EXPERIMENTAL_VP_REVERSE, ISD::EXPERIMENTAL_VP_SPLICE,
- ISD::VP_CTTZ_ELTS, ISD::VP_CTTZ_ELTS_ZERO_UNDEF};
+ ISD::VP_CTTZ_ELTS, ISD::VP_CTTZ_ELTS_ZERO_POISON};
static const unsigned FloatingPointVPOps[] = {
ISD::VP_REDUCE_FADD, ISD::VP_REDUCE_SEQ_FADD,
@@ -929,7 +929,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::VP_MERGE, VT, Custom);
setOperationAction({ISD::CTTZ_ELTS, ISD::CTTZ_ELTS_ZERO_POISON,
- ISD::VP_CTTZ_ELTS, ISD::VP_CTTZ_ELTS_ZERO_UNDEF},
+ ISD::VP_CTTZ_ELTS, ISD::VP_CTTZ_ELTS_ZERO_POISON},
VT, Custom);
setOperationAction(
@@ -1082,12 +1082,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BITREVERSE, VT, Expand);
setOperationAction({ISD::CTLZ, ISD::CTTZ, ISD::CTPOP}, VT, Expand);
- // Lower CTLZ_ZERO_UNDEF and CTTZ_ZERO_UNDEF if element of VT in the
+ // Lower CTLZ_ZERO_POISON and CTTZ_ZERO_POISON if element of VT in the
// range of f32.
EVT FloatVT = MVT::getVectorVT(MVT::f32, VT.getVectorElementCount());
if (isTypeLegal(FloatVT)) {
setOperationAction(
- {ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF, ISD::CTTZ_ZERO_UNDEF}, VT,
+ {ISD::CTLZ, ISD::CTLZ_ZERO_POISON, ISD::CTTZ_ZERO_POISON}, VT,
Custom);
}
}
@@ -1587,16 +1587,16 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::BSWAP, ISD::ROTL, ISD::ROTR}, VT, Custom);
if (Subtarget.hasStdExtZvbb()) {
- setOperationAction({ISD::BITREVERSE, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF,
- ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTPOP},
+ setOperationAction({ISD::BITREVERSE, ISD::CTLZ, ISD::CTLZ_ZERO_POISON,
+ ISD::CTTZ, ISD::CTTZ_ZERO_POISON, ISD::CTPOP},
VT, Custom);
} else {
- // Lower CTLZ_ZERO_UNDEF and CTTZ_ZERO_UNDEF if element of VT in the
+ // Lower CTLZ_ZERO_POISON and CTTZ_ZERO_POISON if element of VT in the
// range of f32.
EVT FloatVT = MVT::getVectorVT(MVT::f32, VT.getVectorElementCount());
if (isTypeLegal(FloatVT))
setOperationAction(
- {ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF, ISD::CTTZ_ZERO_UNDEF}, VT,
+ {ISD::CTLZ, ISD::CTLZ_ZERO_POISON, ISD::CTTZ_ZERO_POISON}, VT,
Custom);
}
@@ -6867,11 +6867,11 @@ bool RISCVTargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const {
isInterleaveShuffle(M, SVT, Dummy1, Dummy2, Subtarget);
}
-// Lower CTLZ_ZERO_UNDEF or CTTZ_ZERO_UNDEF by converting to FP and extracting
+// Lower CTLZ_ZERO_POISON or CTTZ_ZERO_POISON by converting to FP and extracting
// the exponent.
SDValue
-RISCVTargetLowering::lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op,
- SelectionDAG &DAG) const {
+RISCVTargetLowering::lowerCTLZ_CTTZ_ZERO_POISON(SDValue Op,
+ SelectionDAG &DAG) const {
MVT VT = Op.getSimpleValueType();
unsigned EltSize = VT.getScalarSizeInBits();
SDValue Src = Op.getOperand(0);
@@ -6892,9 +6892,9 @@ RISCVTargetLowering::lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op,
assert(DAG.getTargetLoweringInfo().isTypeLegal(FloatVT) &&
"Expected legal float type!");
- // For CTTZ_ZERO_UNDEF, we need to extract the lowest set bit using X & -X.
+ // For CTTZ_ZERO_POISON, we need to extract the lowest set bit using X & -X.
// The trailing zero count is equal to log2 of this single bit value.
- if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF) {
+ if (Op.getOpcode() == ISD::CTTZ_ZERO_POISON) {
SDValue Neg = DAG.getNegative(Src, DL, VT);
Src = DAG.getNode(ISD::AND, DL, VT, Src, Neg);
}
@@ -6935,7 +6935,7 @@ RISCVTargetLowering::lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op,
// The exponent contains log2 of the value in biased form.
unsigned ExponentBias = FloatEltVT == MVT::f64 ? 1023 : 127;
// For trailing zeros, we just need to subtract the bias.
- if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF)
+ if (Op.getOpcode() == ISD::CTTZ_ZERO_POISON)
return DAG.getNode(ISD::SUB, DL, VT, Exp,
DAG.getConstant(ExponentBias, DL, VT));
@@ -6980,7 +6980,7 @@ SDValue RISCVTargetLowering::lowerVPCttzElements(SDValue Op,
}
SDValue Res = DAG.getNode(RISCVISD::VFIRST_VL, DL, XLenVT, Source, Mask, EVL);
- if (Op->getOpcode() == ISD::VP_CTTZ_ELTS_ZERO_UNDEF)
+ if (Op->getOpcode() == ISD::VP_CTTZ_ELTS_ZERO_POISON)
// In this case, we can interpret poison as -1, so nothing to do further.
return Res;
@@ -7563,9 +7563,9 @@ static unsigned getRISCVVLOp(SDValue Op) {
VP_CASE(SREM) // VP_SREM
VP_CASE(UDIV) // VP_UDIV
VP_CASE(UREM) // VP_UREM
- case ISD::CTLZ_ZERO_UNDEF:
+ case ISD::CTLZ_ZERO_POISON:
return RISCVISD::CTLZ_VL;
- case ISD::CTTZ_ZERO_UNDEF:
+ case ISD::CTTZ_ZERO_POISON:
return RISCVISD::CTTZ_VL;
case ISD::FMA:
return RISCVISD::VFMADD_VL;
@@ -8377,7 +8377,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
return lowerVectorMaskVecReduction(Op, DAG, /*IsVP*/ true);
return lowerVPREDUCE(Op, DAG);
case ISD::VP_CTTZ_ELTS:
- case ISD::VP_CTTZ_ELTS_ZERO_UNDEF:
+ case ISD::VP_CTTZ_ELTS_ZERO_POISON:
return lowerVPCttzElements(Op, DAG);
case ISD::UNDEF: {
MVT ContainerVT = getContainerForFixedLengthVector(Op.getSimpleValueType());
@@ -8892,13 +8892,13 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::ABS:
return lowerABS(Op, DAG);
case ISD::CTLZ:
- case ISD::CTLZ_ZERO_UNDEF:
+ case ISD::CTLZ_ZERO_POISON:
case ISD::CTTZ:
- case ISD::CTTZ_ZERO_UNDEF:
+ case ISD::CTTZ_ZERO_POISON:
if (Subtarget.hasStdExtZvbb())
return lowerToScalableOp(Op, DAG);
assert(Op.getOpcode() != ISD::CTTZ);
- return lowerCTLZ_CTTZ_ZERO_UNDEF(Op, DAG);
+ return lowerCTLZ_CTTZ_ZERO_POISON(Op, DAG);
case ISD::CLMUL: {
MVT VT = Op.getSimpleValueType();
assert(VT.isScalableVector() && Subtarget.hasStdExtZvbc() &&
@@ -15003,9 +15003,9 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
Results.push_back(customLegalizeToWOp(N, DAG));
break;
case ISD::CTTZ:
- case ISD::CTTZ_ZERO_UNDEF:
+ case ISD::CTTZ_ZERO_POISON:
case ISD::CTLZ:
- case ISD::CTLZ_ZERO_UNDEF:
+ case ISD::CTLZ_ZERO_POISON:
case ISD::CTLS: {
assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
"Unexpected custom legalisation");
@@ -15016,11 +15016,11 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
switch (N->getOpcode()) {
default: llvm_unreachable("Unexpected opcode");
case ISD::CTTZ:
- case ISD::CTTZ_ZERO_UNDEF:
+ case ISD::CTTZ_ZERO_POISON:
Opc = RISCVISD::CTZW;
break;
case ISD::CTLZ:
- case ISD::CTLZ_ZERO_UNDEF:
+ case ISD::CTLZ_ZERO_POISON:
Opc = RISCVISD::CLZW;
break;
case ISD::CTLS:
@@ -19698,9 +19698,9 @@ static SDValue foldSelectOfCTTZOrCTLZ(SDNode *N, SelectionDAG &DAG) {
CountZeroes = CountZeroes.getOperand(0);
if (CountZeroes.getOpcode() != ISD::CTTZ &&
- CountZeroes.getOpcode() != ISD::CTTZ_ZERO_UNDEF &&
+ CountZeroes.getOpcode() != ISD::CTTZ_ZERO_POISON &&
CountZeroes.getOpcode() != ISD::CTLZ &&
- CountZeroes.getOpcode() != ISD::CTLZ_ZERO_UNDEF)
+ CountZeroes.getOpcode() != ISD::CTLZ_ZERO_POISON)
return SDValue();
if (!isNullConstant(ValOnZero))
@@ -19714,10 +19714,10 @@ static SDValue foldSelectOfCTTZOrCTLZ(SDNode *N, SelectionDAG &DAG) {
if (!isPowerOf2_32(BitWidth))
return SDValue();
- if (CountZeroes.getOpcode() == ISD::CTTZ_ZERO_UNDEF) {
+ if (CountZeroes.getOpcode() == ISD::CTTZ_ZERO_POISON) {
CountZeroes = DAG.getNode(ISD::CTTZ, SDLoc(CountZeroes),
CountZeroes.getValueType(), CountZeroesArgument);
- } else if (CountZeroes.getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
+ } else if (CountZeroes.getOpcode() == ISD::CTLZ_ZERO_POISON) {
CountZeroes = DAG.getNode(ISD::CTLZ, SDLoc(CountZeroes),
CountZeroes.getValueType(), CountZeroesArgument);
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 54802cf62a13e..7ef15bc2c5a00 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -552,7 +552,7 @@ class RISCVTargetLowering : public TargetLowering {
SDValue lowerRESET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
- SDValue lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerCTLZ_CTTZ_ZERO_POISON(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerStrictFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 0a3c1489c40c0..338f53c8d791d 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -1183,10 +1183,10 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
return selectExtInst(ResVReg, ResType, I, CL::sqrt, GL::Sqrt);
case TargetOpcode::G_CTTZ:
- case TargetOpcode::G_CTTZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTTZ_ZERO_POISON:
return selectExtInst(ResVReg, ResType, I, CL::ctz);
case TargetOpcode::G_CTLZ:
- case TargetOpcode::G_CTLZ_ZERO_UNDEF:
+ case TargetOpcode::G_CTLZ_ZERO_POISON:
return selectExtInst(ResVReg, ResType, I, CL::clz);
case TargetOpcode::G_INTRINSIC_ROUND:
diff --git a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
index 47ffecc4085ab..378b0846fb106 100644
--- a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
@@ -502,7 +502,7 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
if (ST.canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) {
getActionDefinitionsBuilder(
- {G_CTTZ, G_CTTZ_ZERO_UNDEF, G_CTLZ, G_CTLZ_ZERO_UNDEF})
+ {G_CTTZ, G_CTTZ_ZERO_POISON, G_CTLZ, G_CTLZ_ZERO_POISON})
.legalForCartesianProduct(allIntScalarsAndVectors,
allIntScalarsAndVectors);
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index bfca95c9b1a38..3d37517a65eda 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1990,38 +1990,38 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
if (Subtarget->isVIS3()) {
setOperationAction(ISD::CTLZ, MVT::i32, Legal);
setOperationAction(ISD::CTLZ, MVT::i64, Legal);
- setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Legal);
- setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Legal);
+ setOperationAction(ISD::CTLZ_ZERO_POISON, MVT::i32, Legal);
+ setOperationAction(ISD::CTLZ_ZERO_POISON, MVT::i64, Legal);
setOperationAction(ISD::CTTZ, MVT::i32,
Subtarget->is64Bit() ? Promote : Expand);
setOperationAction(ISD::CTTZ, MVT::i64, Expand);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32,
+ setOperationAction(ISD::CTTZ_ZERO_POISON, MVT::i32,
Subtarget->is64Bit() ? Promote : Expand);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
+ setOperationAction(ISD::CTTZ_ZERO_POISON, MVT::i64, Expand);
} else if (Subtarget->usePopc()) {
setOperationAction(ISD::CTLZ, MVT::i32, Expand);
setOperationAction(ISD::CTLZ, MVT::i64, Expand);
- setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
- setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
+ setOperationAction(ISD::CTLZ_ZERO_POISON, MVT::i32, Expand);
+ setOperationAction(ISD::CTLZ_ZERO_POISON, MVT::i64, Expand);
setOperationAction(ISD::CTTZ, MVT::i32, Expand);
setOperationAction(ISD::CTTZ, MVT::i64, Expand);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
+ setOperationAction(ISD::CTTZ_ZERO_POISON, MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ_ZERO_POISON, MVT::i64, Expand);
} else {
setOperationAction(ISD::CTLZ, MVT::i32, Expand);
setOperationAction(ISD::CTLZ, MVT::i64, Expand);
- setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32,
+ setOperationAction(ISD::CTLZ_ZERO_POISON, MVT::i32,
Subtarget->is64Bit() ? Promote : LibCall);
- setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, LibCall);
+ setOperationAction(ISD::CTLZ_ZERO_POISON, MVT::i64, LibCall);
// FIXME here we don't have any ISA extensions that could help us, so to
// prevent large expansions those should be made into LibCalls.
setOperationAction(ISD::CTTZ, MVT::i32, Expand);
setOperationAction(ISD::CTTZ, MVT::i64, Expand);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
+ setOperationAction(ISD::CTTZ_ZERO_POISON, MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ_ZERO_POISON, MVT::i64, Expand);
}
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
diff --git a/llvm/lib/Target/Sparc/SparcInstrVIS.td b/llvm/lib/Target/Sparc/SparcInstrVIS.td
index 4a0907fc64bea..353f6fc299e6a 100644
--- a/llvm/lib/Target/Sparc/SparcInstrVIS.td
+++ b/llvm/lib/Target/Sparc/SparcInstrVIS.td
@@ -318,14 +318,14 @@ def : Pat<(i64 (mulhs i64:$lhs, i64:$rhs)),
(ANDrr (SRAXri $rhs, 63), $lhs)))>;
def : Pat<(i64 (ctlz i64:$src)), (LZCNT $src)>;
-def : Pat<(i64 (ctlz_zero_undef i64:$src)), (LZCNT $src)>;
+def : Pat<(i64 (ctlz_zero_poison i64:$src)), (LZCNT $src)>;
// 32-bit LZCNT.
// The zero extension will leave us with 32 extra leading zeros,
// so we need to compensate for it.
// FIXME remove this when the codegen supports using 64-bit values directly
// in V8+ mode.
def : Pat<(i32 (ctlz i32:$src)), (ADDri (LZCNT (SRLri $src, 0)), (i32 -32))>;
-def : Pat<(i32 (ctlz_zero_undef i32:$src)), (ADDri (LZCNT (SRLri $src, 0)), (i32 -32))>;
+def : Pat<(i32 (ctlz_zero_poison i32:$src)), (ADDri (LZCNT (SRLri $src, 0)), (i32 -32))>;
def : Pat<(i32 (bitconvert f32:$src)), (MOVSTOUW $src)>;
def : Pat<(i64 (zanyext (i32 (bitconvert f32:$src)))), (MOVSTOUW $src)>;
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 8084aebe0ba52..26cc921b6b169 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -350,13 +350,13 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
// We have native support for a 64-bit CTLZ, via FLOGR.
setOperationAction(ISD::CTLZ, MVT::i32, Promote);
- setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Promote);
+ setOperationAction(ISD::CTLZ_ZERO_POISON, MVT::i32, Promote);
setOperationAction(ISD::CTLZ, MVT::i64, Legal);
// On z17 we have native support for a 64-bit CTTZ.
if (Subtarget.hasMiscellaneousExtensions4()) {
setOperationAction(ISD::CTTZ, MVT::i32, Promote);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Promote);
+ setOperationAction(ISD::CTTZ_ZERO_POISON, MVT::i32, Promote);
setOperationAction(ISD::CTTZ, MVT::i64, Legal);
}
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index 141196c332074..23eb3034fe3e6 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -194,7 +194,7 @@ void VETargetLowering::initSPUActions() {
LegalizeAction Act = (IntVT == MVT::i32) ? Promote : Legal;
setOperationAction(ISD::BITREVERSE, IntVT, Act);
setOperationAction(ISD::CTLZ, IntVT, Act);
- setOperationAction(ISD::CTLZ_ZERO_UNDEF, IntVT, Act);
+ setOperationAction(ISD::CTLZ_ZERO_POISON, IntVT, Act);
setOperationAction(ISD::CTPOP, IntVT, Act);
// VE has only 64 bits instructions which work as i64 AND/OR/XOR operations.
diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td
index 9869f95ae5661..a6b1a3a60aaf1 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.td
+++ b/llvm/lib/Target/VE/VEInstrInfo.td
@@ -1289,7 +1289,7 @@ defm MRG : RRMRGm<"mrg", 0x56, I64>;
// Section 8.5.7 - LDZ (Leading Zero Count)
def ctlz_pat : PatFrags<(ops node:$src),
[(ctlz node:$src),
- (ctlz_zero_undef node:$src)]>;
+ (ctlz_zero_poison node:$src)]>;
defm LDZ : RRI1m<"ldz", 0x67, I64, i64, ctlz_pat>;
// Section 8.5.8 - PCNT (Population Count)
diff --git a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp
index 7178934ccd1a5..fb499d0db1733 100644
--- a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp
@@ -57,7 +57,7 @@ WebAssemblyLegalizerInfo::WebAssemblyLegalizerInfo(
.clampScalar(1, s32, s64)
.scalarSameSizeAs(0, 1);
- getActionDefinitionsBuilder({G_CTLZ_ZERO_UNDEF, G_CTTZ_ZERO_UNDEF}).lower();
+ getActionDefinitionsBuilder({G_CTLZ_ZERO_POISON, G_CTTZ_ZERO_POISON}).lower();
getActionDefinitionsBuilder({G_ROTL, G_ROTR})
.legalFor({{i32, i32}, {i64, i64}})
diff --git a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
index c342511e99b77..ce922538cfdc9 100644
--- a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
+++ b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
@@ -300,7 +300,7 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
.scalarSameSizeAs(0, 1);
// count trailing zeros
- getActionDefinitionsBuilder(G_CTTZ_ZERO_UNDEF)
+ getActionDefinitionsBuilder(G_CTTZ_ZERO_POISON)
.legalFor({{s16, s16}, {s32, s32}})
.legalFor(Is64Bit, {{s64, s64}})
.widenScalarToNextPow2(1, /*Min=*/16)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index e580715151186..4b193c8db3303 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -399,34 +399,34 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
// Promote the i8 variants and force them on up to i32 which has a shorter
// encoding.
- setOperationPromotedToType(ISD::CTTZ , MVT::i8 , MVT::i32);
- setOperationPromotedToType(ISD::CTTZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
+ setOperationPromotedToType(ISD::CTTZ, MVT::i8, MVT::i32);
+ setOperationPromotedToType(ISD::CTTZ_ZERO_POISON, MVT::i8, MVT::i32);
// Promoted i16. tzcntw has a false dependency on Intel CPUs. For BSF, we emit
// a REP prefix to encode it as TZCNT for modern CPUs so it makes sense to
// promote that too.
- setOperationPromotedToType(ISD::CTTZ , MVT::i16 , MVT::i32);
- setOperationPromotedToType(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , MVT::i32);
+ setOperationPromotedToType(ISD::CTTZ, MVT::i16, MVT::i32);
+ setOperationPromotedToType(ISD::CTTZ_ZERO_POISON, MVT::i16, MVT::i32);
if (!Subtarget.hasBMI()) {
- setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Legal);
+ setOperationAction(ISD::CTTZ, MVT::i32, Custom);
+ setOperationAction(ISD::CTTZ_ZERO_POISON, MVT::i32, Legal);
if (Subtarget.is64Bit()) {
- setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Legal);
+ setOperationAction(ISD::CTTZ, MVT::i64, Custom);
+ setOperationAction(ISD::CTTZ_ZERO_POISON, MVT::i64, Legal);
}
}
if (Subtarget.hasLZCNT()) {
// When promoting the i8 variants, force them to i32 for a shorter
// encoding.
- setOperationPromotedToType(ISD::CTLZ , MVT::i8 , MVT::i32);
- setOperationPromotedToType(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
+ setOperationPromotedToType(ISD::CTLZ, MVT::i8, MVT::i32);
+ setOperationPromotedToType(ISD::CTLZ_ZERO_POISON, MVT::i8, MVT::i32);
} else {
for (auto VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
if (VT == MVT::i64 && !Subtarget.is64Bit())
continue;
- setOperationAction(ISD::CTLZ , VT, Custom);
- setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Custom);
+ setOperationAction(ISD::CTLZ, VT, Custom);
+ setOperationAction(ISD::CTLZ_ZERO_POISON, VT, Custom);
}
}
@@ -2266,8 +2266,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
continue;
setOperationAction(ISD::CTLZ, VT, Custom);
setOperationAction(ISD::CTTZ, VT, Custom);
- setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Custom);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Custom);
+ setOperationAction(ISD::CTLZ_ZERO_POISON, VT, Custom);
+ setOperationAction(ISD::CTTZ_ZERO_POISON, VT, Custom);
}
for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
setOperationAction(ISD::CTLZ, VT, Legal);
@@ -25832,12 +25832,12 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
unsigned CondCode = Cond.getConstantOperandVal(0);
// Special handling for __builtin_ffs(X) - 1 pattern which looks like
- // (select (seteq X, 0), -1, (cttz_zero_undef X)). Disable the special
+ // (select (seteq X, 0), -1, (cttz_zero_poison X)). Disable the special
// handle to keep the CMP with 0. This should be removed by
// optimizeCompareInst by using the flags from the BSR/TZCNT used for the
- // cttz_zero_undef.
+ // cttz_zero_poison.
auto MatchFFSMinus1 = [&](SDValue Op1, SDValue Op2) {
- return (Op1.getOpcode() == ISD::CTTZ_ZERO_UNDEF && Op1.hasOneUse() &&
+ return (Op1.getOpcode() == ISD::CTTZ_ZERO_POISON && Op1.hasOneUse() &&
Op1.getOperand(0) == CmpOp0 && isAllOnesConstant(Op2));
};
if (Subtarget.canUseCMOV() && (VT == MVT::i32 || VT == MVT::i64) &&
@@ -34485,9 +34485,9 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::SET_FPENV_MEM: return LowerSET_FPENV_MEM(Op, DAG);
case ISD::RESET_FPENV: return LowerRESET_FPENV(Op, DAG);
case ISD::CTLZ:
- case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ(Op, Subtarget, DAG);
+ case ISD::CTLZ_ZERO_POISON: return LowerCTLZ(Op, Subtarget, DAG);
case ISD::CTTZ:
- case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, Subtarget, DAG);
+ case ISD::CTTZ_ZERO_POISON: return LowerCTTZ(Op, Subtarget, DAG);
case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
case ISD::MULHS:
case ISD::MULHU: return LowerMULH(Op, Subtarget, DAG);
@@ -34964,8 +34964,8 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
}
case ISD::CTLZ:
case ISD::CTTZ:
- case ISD::CTLZ_ZERO_UNDEF:
- case ISD::CTTZ_ZERO_UNDEF: {
+ case ISD::CTLZ_ZERO_POISON:
+ case ISD::CTTZ_ZERO_POISON: {
// Fold i256/i512 CTLZ/CTTZ patterns to make use of AVX512
// vXi64 CTLZ/CTTZ and VECTOR_COMPRESS.
// Compute the CTLZ/CTTZ of each element, add the element's bit offset,
@@ -34994,7 +34994,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
// CTLZ - reverse the elements as we want the top non-zero element at the
// bottom for compression.
unsigned VecOpc = ISD::CTTZ;
- if (Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF) {
+ if (Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_POISON) {
VecOpc = ISD::CTLZ;
Vec = DAG.getVectorShuffle(VecVT, dl, Vec, Vec, RevMask);
}
@@ -50200,7 +50200,7 @@ static SDValue combineCMov(SDNode *N, SelectionDAG &DAG,
// Ok, now make sure that Add is (add (cttz X), C2) and Const is a constant.
if (isa<ConstantSDNode>(Const) && Add.getOpcode() == ISD::ADD &&
Add.hasOneUse() && isa<ConstantSDNode>(Add.getOperand(1)) &&
- (Add.getOperand(0).getOpcode() == ISD::CTTZ_ZERO_UNDEF ||
+ (Add.getOperand(0).getOpcode() == ISD::CTTZ_ZERO_POISON ||
Add.getOperand(0).getOpcode() == ISD::CTTZ) &&
Add.getOperand(0).getOperand(0) == Cond.getOperand(0)) {
// This should constant fold.
@@ -56273,14 +56273,14 @@ static SDValue combineXorSubCTLZ(SDNode *N, const SDLoc &DL, SelectionDAG &DAG,
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
- if (N0.getOpcode() != ISD::CTLZ_ZERO_UNDEF &&
- N1.getOpcode() != ISD::CTLZ_ZERO_UNDEF)
+ if (N0.getOpcode() != ISD::CTLZ_ZERO_POISON &&
+ N1.getOpcode() != ISD::CTLZ_ZERO_POISON)
return SDValue();
SDValue OpCTLZ;
SDValue OpSizeTM1;
- if (N1.getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
+ if (N1.getOpcode() == ISD::CTLZ_ZERO_POISON) {
OpCTLZ = N1;
OpSizeTM1 = N0;
} else if (N->getOpcode() == ISD::SUB) {
@@ -60653,8 +60653,8 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
case ISD::CTPOP:
case ISD::CTTZ:
case ISD::CTLZ:
- case ISD::CTTZ_ZERO_UNDEF:
- case ISD::CTLZ_ZERO_UNDEF:
+ case ISD::CTTZ_ZERO_POISON:
+ case ISD::CTLZ_ZERO_POISON:
if (!IsSplat && ((VT.is256BitVector() && Subtarget.hasInt256()) ||
(VT.is512BitVector() && Subtarget.useBWIRegs()))) {
return DAG.getNode(Opcode, DL, VT, ConcatSubOperand(VT, Ops, 0));
diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td
index ebbfa48d2660c..48291cdf91f72 100644
--- a/llvm/lib/Target/X86/X86InstrCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrCompiler.td
@@ -2284,13 +2284,13 @@ def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
(IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
-// Bit scan instruction patterns to match explicit zero-undef behavior.
-def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr (i16 (IMPLICIT_DEF)), GR16:$src)>;
-def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr (i32 (IMPLICIT_DEF)), GR32:$src)>;
-def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr (i64 (IMPLICIT_DEF)), GR64:$src)>;
-def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm (i16 (IMPLICIT_DEF)), addr:$src)>;
-def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm (i32 (IMPLICIT_DEF)), addr:$src)>;
-def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm (i64 (IMPLICIT_DEF)), addr:$src)>;
+// Bit scan instruction patterns to match explicit zero-poison behavior.
+def : Pat<(cttz_zero_poison GR16:$src), (BSF16rr (i16 (IMPLICIT_DEF)), GR16:$src)>;
+def : Pat<(cttz_zero_poison GR32:$src), (BSF32rr (i32 (IMPLICIT_DEF)), GR32:$src)>;
+def : Pat<(cttz_zero_poison GR64:$src), (BSF64rr (i64 (IMPLICIT_DEF)), GR64:$src)>;
+def : Pat<(cttz_zero_poison (loadi16 addr:$src)), (BSF16rm (i16 (IMPLICIT_DEF)), addr:$src)>;
+def : Pat<(cttz_zero_poison (loadi32 addr:$src)), (BSF32rm (i32 (IMPLICIT_DEF)), addr:$src)>;
+def : Pat<(cttz_zero_poison (loadi64 addr:$src)), (BSF64rm (i64 (IMPLICIT_DEF)), addr:$src)>;
// When HasMOVBE is enabled it is possible to get a non-legalized
// register-register 16 bit bswap. This maps it to a ROL instruction.
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index b2b77265b06a5..81deed7da6537 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -4442,12 +4442,12 @@ X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
{ ISD::CTLZ, MVT::i32, { 1, 2, 3, 3 } }, // MOV+BSR+XOR
{ ISD::CTLZ, MVT::i16, { 2, 2, 3, 3 } }, // MOV+BSR+XOR
{ ISD::CTLZ, MVT::i8, { 2, 2, 4, 3 } }, // MOV+BSR+XOR
- { ISD::CTLZ_ZERO_UNDEF, MVT::i64,{ 1, 2, 2, 2 } }, // BSR+XOR
+ { ISD::CTLZ_ZERO_POISON,MVT::i64,{ 1, 2, 2, 2 } }, // BSR+XOR
{ ISD::CTTZ, MVT::i64, { 1, 2, 2, 2 } }, // MOV+BSF
{ ISD::CTTZ, MVT::i32, { 1, 2, 2, 2 } }, // MOV+BSF
{ ISD::CTTZ, MVT::i16, { 2, 2, 2, 2 } }, // MOV+BSF
{ ISD::CTTZ, MVT::i8, { 2, 2, 2, 2 } }, // MOV+BSF
- { ISD::CTTZ_ZERO_UNDEF, MVT::i64,{ 1, 2, 1, 2 } }, // BSF
+ { ISD::CTTZ_ZERO_POISON,MVT::i64,{ 1, 2, 1, 2 } }, // BSF
{ ISD::CTPOP, MVT::i64, { 10, 6, 19, 19 } },
{ ISD::ROTL, MVT::i64, { 2, 3, 1, 3 } },
{ ISD::ROTR, MVT::i64, { 2, 3, 1, 3 } },
@@ -4478,15 +4478,15 @@ X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
{ ISD::CTLZ, MVT::i32, { 2, 2, 4, 5 } }, // BSR+XOR or BSR+XOR+CMOV
{ ISD::CTLZ, MVT::i16, { 2, 2, 4, 5 } }, // BSR+XOR or BSR+XOR+CMOV
{ ISD::CTLZ, MVT::i8, { 2, 2, 5, 6 } }, // BSR+XOR or BSR+XOR+CMOV
- { ISD::CTLZ_ZERO_UNDEF, MVT::i32,{ 1, 2, 2, 2 } }, // BSR+XOR
- { ISD::CTLZ_ZERO_UNDEF, MVT::i16,{ 2, 2, 2, 2 } }, // BSR+XOR
- { ISD::CTLZ_ZERO_UNDEF, MVT::i8, { 2, 2, 3, 3 } }, // BSR+XOR
+ { ISD::CTLZ_ZERO_POISON,MVT::i32,{ 1, 2, 2, 2 } }, // BSR+XOR
+ { ISD::CTLZ_ZERO_POISON,MVT::i16,{ 2, 2, 2, 2 } }, // BSR+XOR
+ { ISD::CTLZ_ZERO_POISON,MVT::i8, { 2, 2, 3, 3 } }, // BSR+XOR
{ ISD::CTTZ, MVT::i32, { 2, 2, 3, 3 } }, // TEST+BSF+CMOV/BRANCH
{ ISD::CTTZ, MVT::i16, { 2, 2, 2, 3 } }, // TEST+BSF+CMOV/BRANCH
{ ISD::CTTZ, MVT::i8, { 2, 2, 2, 3 } }, // TEST+BSF+CMOV/BRANCH
- { ISD::CTTZ_ZERO_UNDEF, MVT::i32,{ 1, 2, 1, 2 } }, // BSF
- { ISD::CTTZ_ZERO_UNDEF, MVT::i16,{ 2, 2, 1, 2 } }, // BSF
- { ISD::CTTZ_ZERO_UNDEF, MVT::i8, { 2, 2, 1, 2 } }, // BSF
+ { ISD::CTTZ_ZERO_POISON,MVT::i32,{ 1, 2, 1, 2 } }, // BSF
+ { ISD::CTTZ_ZERO_POISON,MVT::i16,{ 2, 2, 1, 2 } }, // BSF
+ { ISD::CTTZ_ZERO_POISON,MVT::i8, { 2, 2, 1, 2 } }, // BSF
{ ISD::CTPOP, MVT::i32, { 8, 7, 15, 15 } },
{ ISD::CTPOP, MVT::i16, { 9, 8, 17, 17 } },
{ ISD::CTPOP, MVT::i8, { 7, 6, 6, 6 } },
@@ -4694,14 +4694,15 @@ X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(OpTy);
MVT MTy = LT.second;
- // Without BMI/LZCNT see if we're only looking for a *_ZERO_UNDEF cost.
+ // Without BMI/LZCNT see if we're only looking for a *_ZERO_POISON cost.
if (((ISD == ISD::CTTZ && !ST->hasBMI()) ||
(ISD == ISD::CTLZ && !ST->hasLZCNT())) &&
!MTy.isVector() && !ICA.isTypeBasedOnly()) {
const SmallVectorImpl<const Value *> &Args = ICA.getArgs();
if (auto *Cst = dyn_cast<ConstantInt>(Args[1]))
if (Cst->isAllOnesValue())
- ISD = ISD == ISD::CTTZ ? ISD::CTTZ_ZERO_UNDEF : ISD::CTLZ_ZERO_UNDEF;
+ ISD = ISD == ISD::CTTZ ? ISD::CTTZ_ZERO_POISON
+ : ISD::CTLZ_ZERO_POISON;
}
// FSQRT is a single instruction.
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index d9ffc8571f960..090037c28704f 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -174,8 +174,8 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::CTPOP, MVT::i32, Custom);
setOperationAction(ISD::CTTZ, MVT::i32, Expand);
setOperationAction(ISD::CTLZ, MVT::i32, Expand);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
- setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ_ZERO_POISON, MVT::i32, Expand);
+ setOperationAction(ISD::CTLZ_ZERO_POISON, MVT::i32, Expand);
setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, MVT::i32,
Subtarget.hasMINMAX() ? Legal : Expand);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index be18264454efa..8548f63bd1150 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -1408,10 +1408,10 @@ define i32 @test_ctlz_intrinsic_zero_not_undef(i32 %a) {
}
declare i32 @llvm.cttz.i32(i32, i1)
-define i32 @test_cttz_intrinsic_zero_undef(i32 %a) {
-; CHECK-LABEL: name: test_cttz_intrinsic_zero_undef
+define i32 @test_cttz_intrinsic_zero_poison(i32 %a) {
+; CHECK-LABEL: name: test_cttz_intrinsic_zero_poison
; CHECK: [[A:%[0-9]+]]:_(i32) = COPY $w0
-; CHECK: [[RES:%[0-9]+]]:_(i32) = G_CTTZ_ZERO_UNDEF [[A]]
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_CTTZ_ZERO_POISON [[A]]
; CHECK: $w0 = COPY [[RES]]
%res = call i32 @llvm.cttz.i32(i32 %a, i1 1)
ret i32 %res
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-unary-int.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-unary-int.mir
index cba19b49d7687..8dc8d3d69209b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-unary-int.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-unary-int.mir
@@ -41,15 +41,15 @@ body: |
RET_ReallyLR implicit $x0
...
---
-name: ctlz_zero_undef_s32
+name: ctlz_zero_poison_s32
body: |
bb.0:
- ; CHECK-LABEL: name: ctlz_zero_undef_s32
+ ; CHECK-LABEL: name: ctlz_zero_poison_s32
; CHECK: %res:_(s32) = G_CONSTANT i32 24
; CHECK-NEXT: $w0 = COPY %res(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%a:_(s32) = G_CONSTANT i32 128
- %res:_(s32) = G_CTLZ_ZERO_UNDEF %a
+ %res:_(s32) = G_CTLZ_ZERO_POISON %a
$w0 = COPY %res(s32)
RET_ReallyLR implicit $w0
...
@@ -93,15 +93,15 @@ body: |
RET_ReallyLR implicit $x0
...
---
-name: cttz_zero_undef_s32
+name: cttz_zero_poison_s32
body: |
bb.0:
- ; CHECK-LABEL: name: cttz_zero_undef_s32
+ ; CHECK-LABEL: name: cttz_zero_poison_s32
; CHECK: %res:_(s32) = G_CONSTANT i32 5
; CHECK-NEXT: $w0 = COPY %res(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%a:_(s32) = G_CONSTANT i32 96
- %res:_(s32) = G_CTTZ_ZERO_UNDEF %a
+ %res:_(s32) = G_CTTZ_ZERO_POISON %a
$w0 = COPY %res(s32)
RET_ReallyLR implicit $w0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir
index 954adcf98d38a..58b5df6ec55d5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir
@@ -172,15 +172,15 @@ body: |
...
-# The ZERO_UNDEF variants just lower into the vanilla ones.
+# The ZERO_POISON variants just lower into the vanilla ones.
---
-name: test_s32_zeroundef
+name: test_s32_zeropoison
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $s0
- ; CHECK-LABEL: name: test_s32_zeroundef
+ ; CHECK-LABEL: name: test_s32_zeropoison
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
@@ -190,20 +190,20 @@ body: |
; CHECK-NEXT: RET_ReallyLR implicit $s0
%0:_(s32) = COPY $s0
%2:_(s32) = COPY %0(s32)
- %1:_(s32) = G_CTLZ_ZERO_UNDEF %2(s32)
+ %1:_(s32) = G_CTLZ_ZERO_POISON %2(s32)
$s0 = COPY %1(s32)
RET_ReallyLR implicit $s0
...
---
-name: test_s64_zeroundef
+name: test_s64_zeropoison
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0
- ; CHECK-LABEL: name: test_s64_zeroundef
+ ; CHECK-LABEL: name: test_s64_zeropoison
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
@@ -213,7 +213,7 @@ body: |
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(s64) = COPY $d0
%2:_(s64) = COPY %0(s64)
- %1:_(s64) = G_CTLZ_ZERO_UNDEF %2(s64)
+ %1:_(s64) = G_CTLZ_ZERO_POISON %2(s64)
$d0 = COPY %1(s64)
RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz-zero-undef.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz-zero-poison.mir
similarity index 95%
rename from llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz-zero-undef.mir
rename to llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz-zero-poison.mir
index cf51a3776790f..a0aa32f1a698d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz-zero-undef.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz-zero-poison.mir
@@ -29,7 +29,7 @@ body: |
; CHECK-CSSC-NEXT: $w0 = COPY [[CTTZ]](s32)
; CHECK-CSSC-NEXT: RET_ReallyLR implicit $w0
%val:_(s8) = G_IMPLICIT_DEF
- %cttz:_(s8) = G_CTTZ_ZERO_UNDEF %val(s8)
+ %cttz:_(s8) = G_CTTZ_ZERO_POISON %val(s8)
%ext:_(s32) = G_ANYEXT %cttz(s8)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
@@ -62,7 +62,7 @@ body: |
; CHECK-CSSC-NEXT: $w0 = COPY [[CTTZ]](s32)
; CHECK-CSSC-NEXT: RET_ReallyLR implicit $w0
%val:_(s16) = G_IMPLICIT_DEF
- %cttz:_(s16) = G_CTTZ_ZERO_UNDEF %val(s16)
+ %cttz:_(s16) = G_CTTZ_ZERO_POISON %val(s16)
%ext:_(s32) = G_ANYEXT %cttz(s16)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
@@ -93,7 +93,7 @@ body: |
; CHECK-CSSC-NEXT: $w0 = COPY [[CTTZ]](s32)
; CHECK-CSSC-NEXT: RET_ReallyLR implicit $w0
%val:_(s32) = COPY $w0
- %1:_(s32) = G_CTTZ_ZERO_UNDEF %val(s32)
+ %1:_(s32) = G_CTTZ_ZERO_POISON %val(s32)
$w0 = COPY %1(s32)
RET_ReallyLR implicit $w0
@@ -123,7 +123,7 @@ body: |
; CHECK-CSSC-NEXT: $x0 = COPY [[CTTZ]](s64)
; CHECK-CSSC-NEXT: RET_ReallyLR implicit $x0
%val:_(s64) = COPY $x0
- %1:_(s64) = G_CTTZ_ZERO_UNDEF %val(s64)
+ %1:_(s64) = G_CTTZ_ZERO_POISON %val(s64)
$x0 = COPY %1(s64)
RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 17bb373070568..2e0b781785785 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -748,13 +748,13 @@
# DEBUG-NEXT: G_CTTZ (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
-# DEBUG-NEXT: G_CTTZ_ZERO_UNDEF (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
+# DEBUG-NEXT: G_CTTZ_ZERO_POISON (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_CTLZ (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
-# DEBUG-NEXT: G_CTLZ_ZERO_UNDEF (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
+# DEBUG-NEXT: G_CTLZ_ZERO_POISON (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_CTLS (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-undef.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-poison.mir
similarity index 80%
rename from llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-undef.mir
rename to llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-poison.mir
index 6820077ad4870..53519493d503e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-poison.mir
@@ -2,7 +2,7 @@
# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
-name: ctlz_zero_undef_s32_ss
+name: ctlz_zero_poison_s32_ss
legalized: true
regBankSelected: true
tracksRegLiveness: true
@@ -11,19 +11,19 @@ body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: ctlz_zero_undef_s32_ss
+ ; CHECK-LABEL: name: ctlz_zero_poison_s32_ss
; CHECK: liveins: $sgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK-NEXT: [[S_FLBIT_I32_B32_:%[0-9]+]]:sreg_32 = S_FLBIT_I32_B32 [[COPY]]
; CHECK-NEXT: S_ENDPGM 0, implicit [[S_FLBIT_I32_B32_]]
%0:sgpr(s32) = COPY $sgpr0
- %1:sgpr(s32) = G_CTLZ_ZERO_UNDEF %0
+ %1:sgpr(s32) = G_CTLZ_ZERO_POISON %0
S_ENDPGM 0, implicit %1
...
---
-name: ctlz_zero_undef_s32_vs
+name: ctlz_zero_poison_s32_vs
legalized: true
regBankSelected: true
tracksRegLiveness: true
@@ -32,19 +32,19 @@ body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: ctlz_zero_undef_s32_vs
+ ; CHECK-LABEL: name: ctlz_zero_poison_s32_vs
; CHECK: liveins: $sgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK-NEXT: [[V_FFBH_U32_e64_:%[0-9]+]]:vgpr_32 = V_FFBH_U32_e64 [[COPY]], implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FFBH_U32_e64_]]
%0:sgpr(s32) = COPY $sgpr0
- %1:vgpr(s32) = G_CTLZ_ZERO_UNDEF %0
+ %1:vgpr(s32) = G_CTLZ_ZERO_POISON %0
S_ENDPGM 0, implicit %1
...
---
-name: ctlz_zero_undef_s32_vv
+name: ctlz_zero_poison_s32_vv
legalized: true
regBankSelected: true
tracksRegLiveness: true
@@ -53,19 +53,19 @@ body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: ctlz_zero_undef_s32_vv
+ ; CHECK-LABEL: name: ctlz_zero_poison_s32_vv
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[V_FFBH_U32_e64_:%[0-9]+]]:vgpr_32 = V_FFBH_U32_e64 [[COPY]], implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FFBH_U32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
- %1:vgpr(s32) = G_CTLZ_ZERO_UNDEF %0
+ %1:vgpr(s32) = G_CTLZ_ZERO_POISON %0
S_ENDPGM 0, implicit %1
...
---
-name: ctlz_zero_undef_s64_ss
+name: ctlz_zero_poison_s64_ss
legalized: true
regBankSelected: true
tracksRegLiveness: true
@@ -74,13 +74,13 @@ body: |
bb.0:
liveins: $sgpr0_sgpr1
- ; CHECK-LABEL: name: ctlz_zero_undef_s64_ss
+ ; CHECK-LABEL: name: ctlz_zero_poison_s64_ss
; CHECK: liveins: $sgpr0_sgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK-NEXT: [[S_FLBIT_I32_B64_:%[0-9]+]]:sreg_32 = S_FLBIT_I32_B64 [[COPY]]
; CHECK-NEXT: S_ENDPGM 0, implicit [[S_FLBIT_I32_B64_]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1
- %1:sgpr(s32) = G_CTLZ_ZERO_UNDEF %0
+ %1:sgpr(s32) = G_CTLZ_ZERO_POISON %0
S_ENDPGM 0, implicit %1
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-undef.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-poison.mir
similarity index 79%
rename from llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-undef.mir
rename to llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-poison.mir
index a0d5db38813a3..9cc1577c5bfbb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-poison.mir
@@ -2,7 +2,7 @@
# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
-name: cttz_zero_undef_s32_ss
+name: cttz_zero_poison_s32_ss
legalized: true
regBankSelected: true
tracksRegLiveness: true
@@ -11,19 +11,19 @@ body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: cttz_zero_undef_s32_ss
+ ; CHECK-LABEL: name: cttz_zero_poison_s32_ss
; CHECK: liveins: $sgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK-NEXT: [[S_FF1_I32_B32_:%[0-9]+]]:sreg_32 = S_FF1_I32_B32 [[COPY]]
; CHECK-NEXT: S_ENDPGM 0, implicit [[S_FF1_I32_B32_]]
%0:sgpr(s32) = COPY $sgpr0
- %1:sgpr(s32) = G_CTTZ_ZERO_UNDEF %0
+ %1:sgpr(s32) = G_CTTZ_ZERO_POISON %0
S_ENDPGM 0, implicit %1
...
---
-name: cttz_zero_undef_s32_vs
+name: cttz_zero_poison_s32_vs
legalized: true
regBankSelected: true
tracksRegLiveness: true
@@ -32,19 +32,19 @@ body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: cttz_zero_undef_s32_vs
+ ; CHECK-LABEL: name: cttz_zero_poison_s32_vs
; CHECK: liveins: $sgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK-NEXT: [[V_FFBL_B32_e64_:%[0-9]+]]:vgpr_32 = V_FFBL_B32_e64 [[COPY]], implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FFBL_B32_e64_]]
%0:sgpr(s32) = COPY $sgpr0
- %1:vgpr(s32) = G_CTTZ_ZERO_UNDEF %0
+ %1:vgpr(s32) = G_CTTZ_ZERO_POISON %0
S_ENDPGM 0, implicit %1
...
---
-name: cttz_zero_undef_s32_vv
+name: cttz_zero_poison_s32_vv
legalized: true
regBankSelected: true
tracksRegLiveness: true
@@ -53,19 +53,19 @@ body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: cttz_zero_undef_s32_vv
+ ; CHECK-LABEL: name: cttz_zero_poison_s32_vv
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[V_FFBL_B32_e64_:%[0-9]+]]:vgpr_32 = V_FFBL_B32_e64 [[COPY]], implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FFBL_B32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
- %1:vgpr(s32) = G_CTTZ_ZERO_UNDEF %0
+ %1:vgpr(s32) = G_CTTZ_ZERO_POISON %0
S_ENDPGM 0, implicit %1
...
---
-name: cttz_zero_undef_s64_ss
+name: cttz_zero_poison_s64_ss
legalized: true
regBankSelected: true
tracksRegLiveness: true
@@ -74,13 +74,13 @@ body: |
bb.0:
liveins: $sgpr0_sgpr1
- ; CHECK-LABEL: name: cttz_zero_undef_s64_ss
+ ; CHECK-LABEL: name: cttz_zero_poison_s64_ss
; CHECK: liveins: $sgpr0_sgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK-NEXT: [[S_FF1_I32_B64_:%[0-9]+]]:sreg_32 = S_FF1_I32_B64 [[COPY]]
; CHECK-NEXT: S_ENDPGM 0, implicit [[S_FF1_I32_B64_]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1
- %1:sgpr(s32) = G_CTTZ_ZERO_UNDEF %0
+ %1:sgpr(s32) = G_CTTZ_ZERO_POISON %0
S_ENDPGM 0, implicit %1
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-poison.mir
similarity index 67%
rename from llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
rename to llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-poison.mir
index f0f62dd2f98be..ab8129d6016c9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-poison.mir
@@ -2,82 +2,82 @@
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
---
-name: ctlz_zero_undef_s32_s32
+name: ctlz_zero_poison_s32_s32
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: ctlz_zero_undef_s32_s32
+ ; CHECK-LABEL: name: ctlz_zero_poison_s32_s32
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[CTLZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTLZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_POISON [[COPY]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[CTLZ_ZERO_POISON]](s32)
%0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_CTLZ_ZERO_UNDEF %0
+ %1:_(s32) = G_CTLZ_ZERO_POISON %0
$vgpr0 = COPY %1
...
---
-name: ctlz_zero_undef_s32_s64
+name: ctlz_zero_poison_s32_s64
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: ctlz_zero_undef_s32_s64
+ ; CHECK-LABEL: name: ctlz_zero_poison_s32_s64
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s64)
- ; CHECK-NEXT: $vgpr0 = COPY [[CTLZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTLZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_POISON [[COPY]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[CTLZ_ZERO_POISON]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s32) = G_CTLZ_ZERO_UNDEF %0
+ %1:_(s32) = G_CTLZ_ZERO_POISON %0
$vgpr0 = COPY %1
...
---
-name: ctlz_zero_undef_s64_s64
+name: ctlz_zero_poison_s64_s64
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: ctlz_zero_undef_s64_s64
+ ; CHECK-LABEL: name: ctlz_zero_poison_s64_s64
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s64)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTLZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTLZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_POISON [[COPY]](s64)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTLZ_ZERO_POISON]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = G_CTLZ_ZERO_UNDEF %0
+ %1:_(s64) = G_CTLZ_ZERO_POISON %0
$vgpr0_vgpr1 = COPY %1
...
---
-name: ctlz_zero_undef_s16_s32
+name: ctlz_zero_poison_s16_s32
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: ctlz_zero_undef_s16_s32
+ ; CHECK-LABEL: name: ctlz_zero_poison_s16_s32
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[CTLZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTLZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_POISON [[COPY]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[CTLZ_ZERO_POISON]](s32)
%0:_(s32) = COPY $vgpr0
- %1:_(s16) = G_CTLZ_ZERO_UNDEF %0
+ %1:_(s16) = G_CTLZ_ZERO_POISON %0
%2:_(s32) = G_ZEXT %1
$vgpr0 = COPY %2
...
---
-name: ctlz_zero_undef_s16_s16
+name: ctlz_zero_poison_s16_s16
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: ctlz_zero_undef_s16_s16
+ ; CHECK-LABEL: name: ctlz_zero_poison_s16_s16
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
@@ -89,58 +89,58 @@ body: |
; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
- %2:_(s16) = G_CTLZ_ZERO_UNDEF %1
+ %2:_(s16) = G_CTLZ_ZERO_POISON %1
%3:_(s32) = G_ZEXT %2
$vgpr0 = COPY %3
...
---
-name: ctlz_zero_undef_v2s32_v2s32
+name: ctlz_zero_poison_v2s32_v2s32
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: ctlz_zero_undef_v2s32_v2s32
+ ; CHECK-LABEL: name: ctlz_zero_poison_v2s32_v2s32
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[UV]](s32)
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[UV1]](s32)
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[CTLZ_ZERO_UNDEF]](s32), [[CTLZ_ZERO_UNDEF1]](s32)
+ ; CHECK-NEXT: [[CTLZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_POISON [[UV]](s32)
+ ; CHECK-NEXT: [[CTLZ_ZERO_POISON1:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_POISON [[UV1]](s32)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[CTLZ_ZERO_POISON]](s32), [[CTLZ_ZERO_POISON1]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = G_CTLZ_ZERO_UNDEF %0
+ %1:_(<2 x s32>) = G_CTLZ_ZERO_POISON %0
$vgpr0_vgpr1 = COPY %1
...
---
-name: ctlz_zero_undef_v2s32_v2s64
+name: ctlz_zero_poison_v2s32_v2s64
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-LABEL: name: ctlz_zero_undef_v2s32_v2s64
+ ; CHECK-LABEL: name: ctlz_zero_poison_v2s32_v2s64
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[UV]](s64)
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[UV1]](s64)
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[CTLZ_ZERO_UNDEF]](s32), [[CTLZ_ZERO_UNDEF1]](s32)
+ ; CHECK-NEXT: [[CTLZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_POISON [[UV]](s64)
+ ; CHECK-NEXT: [[CTLZ_ZERO_POISON1:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_POISON [[UV1]](s64)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[CTLZ_ZERO_POISON]](s32), [[CTLZ_ZERO_POISON1]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(<2 x s32>) = G_CTLZ_ZERO_UNDEF %0
+ %1:_(<2 x s32>) = G_CTLZ_ZERO_POISON %0
$vgpr0_vgpr1 = COPY %1
...
---
-name: ctlz_zero_undef_v2s16_v2s16
+name: ctlz_zero_poison_v2s16_v2s16
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: ctlz_zero_undef_v2s16_v2s16
+ ; CHECK-LABEL: name: ctlz_zero_poison_v2s16_v2s16
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
@@ -159,18 +159,18 @@ body: |
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
- %1:_(<2 x s16>) = G_CTLZ_ZERO_UNDEF %0
+ %1:_(<2 x s16>) = G_CTLZ_ZERO_POISON %0
$vgpr0 = COPY %1
...
---
-name: ctlz_zero_undef_s7_s7
+name: ctlz_zero_poison_s7_s7
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: ctlz_zero_undef_s7_s7
+ ; CHECK-LABEL: name: ctlz_zero_poison_s7_s7
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
@@ -182,30 +182,30 @@ body: |
; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
- %2:_(s7) = G_CTLZ_ZERO_UNDEF %1
+ %2:_(s7) = G_CTLZ_ZERO_POISON %1
%3:_(s32) = G_ZEXT %2
$vgpr0 = COPY %3
...
---
-name: ctlz_zero_undef_s33_s33
+name: ctlz_zero_poison_s33_s33
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: ctlz_zero_undef_s33_s33
+ ; CHECK-LABEL: name: ctlz_zero_poison_s33_s33
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32)
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[SHL]](s64)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTLZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTLZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_POISON [[SHL]](s64)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTLZ_ZERO_POISON]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0
- %2:_(s33) = G_CTLZ_ZERO_UNDEF %1
+ %2:_(s33) = G_CTLZ_ZERO_POISON %1
%3:_(s64) = G_ANYEXT %2
$vgpr0_vgpr1 = COPY %3
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-poison.mir
similarity index 54%
rename from llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir
rename to llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-poison.mir
index ecad6cb8bbd18..fb78db82e447d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-poison.mir
@@ -2,199 +2,199 @@
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
---
-name: cttz_zero_undef_s32_s32
+name: cttz_zero_poison_s32_s32
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: cttz_zero_undef_s32_s32
+ ; CHECK-LABEL: name: cttz_zero_poison_s32_s32
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[COPY]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[CTTZ_ZERO_POISON]](s32)
%0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_CTTZ_ZERO_UNDEF %0
+ %1:_(s32) = G_CTTZ_ZERO_POISON %0
$vgpr0 = COPY %1
...
---
-name: cttz_zero_undef_s32_s64
+name: cttz_zero_poison_s32_s64
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: cttz_zero_undef_s32_s64
+ ; CHECK-LABEL: name: cttz_zero_poison_s32_s64
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s64)
- ; CHECK-NEXT: $vgpr0 = COPY [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[COPY]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[CTTZ_ZERO_POISON]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s32) = G_CTTZ_ZERO_UNDEF %0
+ %1:_(s32) = G_CTTZ_ZERO_POISON %0
$vgpr0 = COPY %1
...
---
-name: cttz_zero_undef_s64_s64
+name: cttz_zero_poison_s64_s64
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: cttz_zero_undef_s64_s64
+ ; CHECK-LABEL: name: cttz_zero_poison_s64_s64
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s64)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[COPY]](s64)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTTZ_ZERO_POISON]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = G_CTTZ_ZERO_UNDEF %0
+ %1:_(s64) = G_CTTZ_ZERO_POISON %0
$vgpr0_vgpr1 = COPY %1
...
---
-name: cttz_zero_undef_s16_s32
+name: cttz_zero_poison_s16_s32
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: cttz_zero_undef_s16_s32
+ ; CHECK-LABEL: name: cttz_zero_poison_s16_s32
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[COPY]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[CTTZ_ZERO_POISON]](s32)
%0:_(s32) = COPY $vgpr0
- %1:_(s16) = G_CTTZ_ZERO_UNDEF %0
+ %1:_(s16) = G_CTTZ_ZERO_POISON %0
%2:_(s32) = G_ZEXT %1
$vgpr0 = COPY %2
...
---
-name: cttz_zero_undef_s16_s16
+name: cttz_zero_poison_s16_s16
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: cttz_zero_undef_s16_s16
+ ; CHECK-LABEL: name: cttz_zero_poison_s16_s16
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_POISON]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
- %2:_(s16) = G_CTTZ_ZERO_UNDEF %1
+ %2:_(s16) = G_CTTZ_ZERO_POISON %1
%3:_(s32) = G_ZEXT %2
$vgpr0 = COPY %3
...
---
-name: cttz_zero_undef_v2s32_v2s32
+name: cttz_zero_poison_v2s32_v2s32
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: cttz_zero_undef_v2s32_v2s32
+ ; CHECK-LABEL: name: cttz_zero_poison_v2s32_v2s32
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV]](s32)
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV1]](s32)
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[CTTZ_ZERO_UNDEF]](s32), [[CTTZ_ZERO_UNDEF1]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[UV]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[UV1]](s32)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[CTTZ_ZERO_POISON]](s32), [[CTTZ_ZERO_POISON1]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = G_CTTZ_ZERO_UNDEF %0
+ %1:_(<2 x s32>) = G_CTTZ_ZERO_POISON %0
$vgpr0_vgpr1 = COPY %1
...
---
-name: cttz_zero_undef_v2s32_v2s64
+name: cttz_zero_poison_v2s32_v2s64
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-LABEL: name: cttz_zero_undef_v2s32_v2s64
+ ; CHECK-LABEL: name: cttz_zero_poison_v2s32_v2s64
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV]](s64)
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV1]](s64)
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[CTTZ_ZERO_UNDEF]](s32), [[CTTZ_ZERO_UNDEF1]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[UV]](s64)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[UV1]](s64)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[CTTZ_ZERO_POISON]](s32), [[CTTZ_ZERO_POISON1]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(<2 x s32>) = G_CTTZ_ZERO_UNDEF %0
+ %1:_(<2 x s32>) = G_CTTZ_ZERO_POISON %0
$vgpr0_vgpr1 = COPY %1
...
---
-name: cttz_zero_undef_v2s16_v2s16
+name: cttz_zero_poison_v2s16_v2s16
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: cttz_zero_undef_v2s16_v2s16
+ ; CHECK-LABEL: name: cttz_zero_poison_v2s16_v2s16
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[BITCAST]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[LSHR]](s32)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF1]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[BITCAST]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_POISON]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[LSHR]](s32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_POISON1]](s32)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[SHL]]
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
- %1:_(<2 x s16>) = G_CTTZ_ZERO_UNDEF %0
+ %1:_(<2 x s16>) = G_CTTZ_ZERO_POISON %0
$vgpr0 = COPY %1
...
---
-name: cttz_zero_undef_s7_s7
+name: cttz_zero_poison_s7_s7
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: cttz_zero_undef_s7_s7
+ ; CHECK-LABEL: name: cttz_zero_poison_s7_s7
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_POISON]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
- %2:_(s7) = G_CTTZ_ZERO_UNDEF %1
+ %2:_(s7) = G_CTTZ_ZERO_POISON %1
%3:_(s32) = G_ZEXT %2
$vgpr0 = COPY %3
...
---
-name: cttz_zero_undef_s33_s33
+name: cttz_zero_poison_s33_s33
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: cttz_zero_undef_s33_s33
+ ; CHECK-LABEL: name: cttz_zero_poison_s33_s33
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s64)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[COPY]](s64)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTTZ_ZERO_POISON]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0
- %2:_(s33) = G_CTTZ_ZERO_UNDEF %1
+ %2:_(s33) = G_CTTZ_ZERO_POISON %1
%3:_(s64) = G_ANYEXT %2
$vgpr0_vgpr1 = COPY %3
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
index 46d5bdbd309c4..00b8ee312e170 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
@@ -91,8 +91,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]]
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[OR]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_POISON]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
@@ -162,11 +162,11 @@ body: |
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[BITCAST]], [[C1]]
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[OR]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_POISON]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[C1]]
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR1]](s32)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF1]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[OR1]](s32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_POISON1]](s32)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[SHL]]
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -189,8 +189,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]]
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[OR]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_POISON]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
@@ -212,8 +212,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934592
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[C]]
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s64)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[OR]](s64)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTTZ_ZERO_POISON]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-undef.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
similarity index 66%
rename from llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-undef.mir
rename to llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
index 733d1342ff186..1828424c578d8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
@@ -3,67 +3,67 @@
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
-name: ctlz_zero_undef_s32_s
+name: ctlz_zero_poison_s32_s
legalized: true
body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: ctlz_zero_undef_s32_s
+ ; CHECK-LABEL: name: ctlz_zero_poison_s32_s
; CHECK: liveins: $sgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:sgpr(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s32)
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[CTLZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTLZ_ZERO_POISON:%[0-9]+]]:sgpr(s32) = G_CTLZ_ZERO_POISON [[COPY]](s32)
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[CTLZ_ZERO_POISON]](s32)
%0:_(s32) = COPY $sgpr0
- %1:_(s32) = G_CTLZ_ZERO_UNDEF %0
+ %1:_(s32) = G_CTLZ_ZERO_POISON %0
S_ENDPGM 0, implicit %1
...
---
-name: ctlz_zero_undef_s32_v
+name: ctlz_zero_poison_s32_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: ctlz_zero_undef_s32_v
+ ; CHECK-LABEL: name: ctlz_zero_poison_s32_v
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:vgpr(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s32)
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[CTLZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTLZ_ZERO_POISON:%[0-9]+]]:vgpr(s32) = G_CTLZ_ZERO_POISON [[COPY]](s32)
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[CTLZ_ZERO_POISON]](s32)
%0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_CTLZ_ZERO_UNDEF %0
+ %1:_(s32) = G_CTLZ_ZERO_POISON %0
S_ENDPGM 0, implicit %1
...
---
-name: ctlz_zero_undef_s64_s
+name: ctlz_zero_poison_s64_s
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
- ; CHECK-LABEL: name: ctlz_zero_undef_s64_s
+ ; CHECK-LABEL: name: ctlz_zero_poison_s64_s
; CHECK: liveins: $sgpr0_sgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:sgpr(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s64)
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[CTLZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTLZ_ZERO_POISON:%[0-9]+]]:sgpr(s32) = G_CTLZ_ZERO_POISON [[COPY]](s64)
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[CTLZ_ZERO_POISON]](s32)
%0:_(s64) = COPY $sgpr0_sgpr1
- %1:_(s32) = G_CTLZ_ZERO_UNDEF %0
+ %1:_(s32) = G_CTLZ_ZERO_POISON %0
S_ENDPGM 0, implicit %1
...
---
-name: ctlz_zero_undef_s64_v
+name: ctlz_zero_poison_s64_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: ctlz_zero_undef_s64_v
+ ; CHECK-LABEL: name: ctlz_zero_poison_s64_v
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
@@ -75,6 +75,6 @@ body: |
; CHECK-NEXT: [[UMIN:%[0-9]+]]:vgpr(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[ADD]]
; CHECK-NEXT: S_ENDPGM 0, implicit [[UMIN]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s32) = G_CTLZ_ZERO_UNDEF %0
+ %1:_(s32) = G_CTLZ_ZERO_POISON %0
S_ENDPGM 0, implicit %1
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
similarity index 66%
rename from llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir
rename to llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
index 8dfcefbcd32df..c0421b784c600 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
@@ -3,67 +3,67 @@
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
-name: cttz_zero_undef_s32_s
+name: cttz_zero_poison_s32_s
legalized: true
body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: cttz_zero_undef_s32_s
+ ; CHECK-LABEL: name: cttz_zero_poison_s32_s
; CHECK: liveins: $sgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:sgpr(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:sgpr(s32) = G_CTTZ_ZERO_POISON [[COPY]](s32)
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[CTTZ_ZERO_POISON]](s32)
%0:_(s32) = COPY $sgpr0
- %1:_(s32) = G_CTTZ_ZERO_UNDEF %0
+ %1:_(s32) = G_CTTZ_ZERO_POISON %0
S_ENDPGM 0, implicit %1
...
---
-name: cttz_zero_undef_s32_v
+name: cttz_zero_poison_s32_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: cttz_zero_undef_s32_v
+ ; CHECK-LABEL: name: cttz_zero_poison_s32_v
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:vgpr(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:vgpr(s32) = G_CTTZ_ZERO_POISON [[COPY]](s32)
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[CTTZ_ZERO_POISON]](s32)
%0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_CTTZ_ZERO_UNDEF %0
+ %1:_(s32) = G_CTTZ_ZERO_POISON %0
S_ENDPGM 0, implicit %1
...
---
-name: cttz_zero_undef_s64_s
+name: cttz_zero_poison_s64_s
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
- ; CHECK-LABEL: name: cttz_zero_undef_s64_s
+ ; CHECK-LABEL: name: cttz_zero_poison_s64_s
; CHECK: liveins: $sgpr0_sgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:sgpr(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s64)
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:sgpr(s32) = G_CTTZ_ZERO_POISON [[COPY]](s64)
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[CTTZ_ZERO_POISON]](s32)
%0:_(s64) = COPY $sgpr0_sgpr1
- %1:_(s32) = G_CTTZ_ZERO_UNDEF %0
+ %1:_(s32) = G_CTTZ_ZERO_POISON %0
S_ENDPGM 0, implicit %1
...
---
-name: cttz_zero_undef_s64_v
+name: cttz_zero_poison_s64_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: cttz_zero_undef_s64_v
+ ; CHECK-LABEL: name: cttz_zero_poison_s64_v
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
@@ -75,6 +75,6 @@ body: |
; CHECK-NEXT: [[UMIN:%[0-9]+]]:vgpr(s32) = G_UMIN [[AMDGPU_FFBL_B32_]], [[ADD]]
; CHECK-NEXT: S_ENDPGM 0, implicit [[UMIN]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s32) = G_CTTZ_ZERO_UNDEF %0
+ %1:_(s32) = G_CTTZ_ZERO_POISON %0
S_ENDPGM 0, implicit %1
...
diff --git a/llvm/test/CodeGen/AMDGPU/ctls.ll b/llvm/test/CodeGen/AMDGPU/ctls.ll
index 3181b0032875d..00673b4a6d288 100644
--- a/llvm/test/CodeGen/AMDGPU/ctls.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctls.ll
@@ -85,8 +85,8 @@ define i32 @ctls_i32_xor_commuted(i32 %x) {
ret i32 %d
}
-define i32 @ctls_i32_zero_undef(i32 %x) {
-; GFX6-LABEL: ctls_i32_zero_undef:
+define i32 @ctls_i32_zero_poison(i32 %x) {
+; GFX6-LABEL: ctls_i32_zero_poison:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_ffbh_i32_e32 v0, v0
@@ -94,7 +94,7 @@ define i32 @ctls_i32_zero_undef(i32 %x) {
; GFX6-NEXT: v_add_i32_e32 v0, vcc, -1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: ctls_i32_zero_undef:
+; GFX11-LABEL: ctls_i32_zero_poison:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cls_i32_e32 v0, v0
@@ -104,7 +104,7 @@ define i32 @ctls_i32_zero_undef(i32 %x) {
; GFX11-NEXT: s_setpc_b64 s[30:31]
%a = ashr i32 %x, 31
%b = xor i32 %x, %a
- %c = call i32 @llvm.ctlz.i32(i32 %b, i1 true) ; zero_undef = true
+ %c = call i32 @llvm.ctlz.i32(i32 %b, i1 true) ; zero_poison = true
%d = sub i32 %c, 1
ret i32 %d
}
@@ -362,9 +362,9 @@ define <2 x i32> @ctls_v2i32_known_mixed_bits(<2 x i32> %x) {
ret <2 x i32> %d
}
-; Vector with ctlz_zero_undef.
-define <2 x i32> @ctls_v2i32_zero_undef(<2 x i32> %x) {
-; GFX6-LABEL: ctls_v2i32_zero_undef:
+; Vector with ctlz_zero_poison.
+define <2 x i32> @ctls_v2i32_zero_poison(<2 x i32> %x) {
+; GFX6-LABEL: ctls_v2i32_zero_poison:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v1
@@ -377,7 +377,7 @@ define <2 x i32> @ctls_v2i32_zero_undef(<2 x i32> %x) {
; GFX6-NEXT: v_add_i32_e32 v1, vcc, -1, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: ctls_v2i32_zero_undef:
+; GFX11-LABEL: ctls_v2i32_zero_poison:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_ashrrev_i32_e32 v2, 31, v0
diff --git a/llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll b/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
similarity index 90%
rename from llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
rename to llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
index 0f459959310e1..8c288ec551063 100644
--- a/llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
@@ -26,8 +26,8 @@ declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1) nounwind readnone
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
-define amdgpu_kernel void @s_ctlz_zero_undef_i32(ptr addrspace(1) noalias %out, i32 %val) nounwind {
-; SI-LABEL: s_ctlz_zero_undef_i32:
+define amdgpu_kernel void @s_ctlz_zero_poison_i32(ptr addrspace(1) noalias %out, i32 %val) nounwind {
+; SI-LABEL: s_ctlz_zero_poison_i32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dword s2, s[4:5], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
@@ -39,7 +39,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i32(ptr addrspace(1) noalias %out,
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: s_ctlz_zero_undef_i32:
+; VI-LABEL: s_ctlz_zero_poison_i32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
@@ -51,7 +51,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i32(ptr addrspace(1) noalias %out,
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: s_ctlz_zero_undef_i32:
+; EG-LABEL: s_ctlz_zero_poison_i32:
; EG: ; %bb.0:
; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
@@ -62,7 +62,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i32(ptr addrspace(1) noalias %out,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; EG-NEXT: FFBH_UINT * T1.X, KC0[2].Z,
;
-; GFX9-GISEL-LABEL: s_ctlz_zero_undef_i32:
+; GFX9-GISEL-LABEL: s_ctlz_zero_poison_i32:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
@@ -77,8 +77,8 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i32(ptr addrspace(1) noalias %out,
ret void
}
-define amdgpu_kernel void @v_ctlz_zero_undef_i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
-; SI-LABEL: v_ctlz_zero_undef_i32:
+define amdgpu_kernel void @v_ctlz_zero_poison_i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
+; SI-LABEL: v_ctlz_zero_poison_i32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -97,7 +97,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32(ptr addrspace(1) noalias %out,
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_ctlz_zero_undef_i32:
+; VI-LABEL: v_ctlz_zero_poison_i32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -113,7 +113,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32(ptr addrspace(1) noalias %out,
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_ctlz_zero_undef_i32:
+; EG-LABEL: v_ctlz_zero_poison_i32:
; EG: ; %bb.0:
; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -132,7 +132,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32(ptr addrspace(1) noalias %out,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i32:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_i32:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -151,8 +151,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32(ptr addrspace(1) noalias %out,
ret void
}
-define amdgpu_kernel void @v_ctlz_zero_undef_v2i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
-; SI-LABEL: v_ctlz_zero_undef_v2i32:
+define amdgpu_kernel void @v_ctlz_zero_poison_v2i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
+; SI-LABEL: v_ctlz_zero_poison_v2i32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -172,7 +172,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_v2i32(ptr addrspace(1) noalias %out
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_ctlz_zero_undef_v2i32:
+; VI-LABEL: v_ctlz_zero_poison_v2i32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
@@ -189,7 +189,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_v2i32(ptr addrspace(1) noalias %out
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_ctlz_zero_undef_v2i32:
+; EG-LABEL: v_ctlz_zero_poison_v2i32:
; EG: ; %bb.0:
; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -209,7 +209,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_v2i32(ptr addrspace(1) noalias %out
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v2i32:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_v2i32:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 3, v0
@@ -229,8 +229,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_v2i32(ptr addrspace(1) noalias %out
ret void
}
-define amdgpu_kernel void @v_ctlz_zero_undef_v4i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
-; SI-LABEL: v_ctlz_zero_undef_v4i32:
+define amdgpu_kernel void @v_ctlz_zero_poison_v4i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
+; SI-LABEL: v_ctlz_zero_poison_v4i32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -252,7 +252,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_v4i32(ptr addrspace(1) noalias %out
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_ctlz_zero_undef_v4i32:
+; VI-LABEL: v_ctlz_zero_poison_v4i32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 4, v0
@@ -271,7 +271,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_v4i32(ptr addrspace(1) noalias %out
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_ctlz_zero_undef_v4i32:
+; EG-LABEL: v_ctlz_zero_poison_v4i32:
; EG: ; %bb.0:
; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -293,7 +293,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_v4i32(ptr addrspace(1) noalias %out
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v4i32:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_v4i32:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 4, v0
@@ -315,8 +315,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_v4i32(ptr addrspace(1) noalias %out
ret void
}
-define amdgpu_kernel void @s_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noalias %out, i8 %val) nounwind {
-; SI-LABEL: s_ctlz_zero_undef_i8_with_select:
+define amdgpu_kernel void @s_ctlz_zero_poison_i8_with_select(ptr addrspace(1) noalias %out, i8 %val) nounwind {
+; SI-LABEL: s_ctlz_zero_poison_i8_with_select:
; SI: ; %bb.0:
; SI-NEXT: s_load_dword s2, s[4:5], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
@@ -329,7 +329,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: s_ctlz_zero_undef_i8_with_select:
+; VI-LABEL: s_ctlz_zero_poison_i8_with_select:
; VI: ; %bb.0:
; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
@@ -342,7 +342,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
; VI-NEXT: flat_store_byte v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: s_ctlz_zero_undef_i8_with_select:
+; EG-LABEL: s_ctlz_zero_poison_i8_with_select:
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @8, KC0[], KC1[]
; EG-NEXT: TEX 0 @6
@@ -371,7 +371,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: s_ctlz_zero_undef_i8_with_select:
+; GFX9-GISEL-LABEL: s_ctlz_zero_poison_i8_with_select:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
@@ -389,8 +389,8 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
ret void
}
-define amdgpu_kernel void @s_ctlz_zero_undef_i16_with_select(ptr addrspace(1) noalias %out, i16 %val) nounwind {
-; SI-LABEL: s_ctlz_zero_undef_i16_with_select:
+define amdgpu_kernel void @s_ctlz_zero_poison_i16_with_select(ptr addrspace(1) noalias %out, i16 %val) nounwind {
+; SI-LABEL: s_ctlz_zero_poison_i16_with_select:
; SI: ; %bb.0:
; SI-NEXT: s_load_dword s2, s[4:5], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
@@ -403,7 +403,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: s_ctlz_zero_undef_i16_with_select:
+; VI-LABEL: s_ctlz_zero_poison_i16_with_select:
; VI: ; %bb.0:
; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
@@ -416,7 +416,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: s_ctlz_zero_undef_i16_with_select:
+; EG-LABEL: s_ctlz_zero_poison_i16_with_select:
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @8, KC0[], KC1[]
; EG-NEXT: TEX 0 @6
@@ -445,7 +445,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: s_ctlz_zero_undef_i16_with_select:
+; GFX9-GISEL-LABEL: s_ctlz_zero_poison_i16_with_select:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
@@ -463,8 +463,8 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
ret void
}
-define amdgpu_kernel void @s_ctlz_zero_undef_i32_with_select(ptr addrspace(1) noalias %out, i32 %val) nounwind {
-; SI-LABEL: s_ctlz_zero_undef_i32_with_select:
+define amdgpu_kernel void @s_ctlz_zero_poison_i32_with_select(ptr addrspace(1) noalias %out, i32 %val) nounwind {
+; SI-LABEL: s_ctlz_zero_poison_i32_with_select:
; SI: ; %bb.0:
; SI-NEXT: s_load_dword s2, s[4:5], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
@@ -476,7 +476,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i32_with_select(ptr addrspace(1) no
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: s_ctlz_zero_undef_i32_with_select:
+; VI-LABEL: s_ctlz_zero_poison_i32_with_select:
; VI: ; %bb.0:
; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
@@ -488,7 +488,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i32_with_select(ptr addrspace(1) no
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: s_ctlz_zero_undef_i32_with_select:
+; EG-LABEL: s_ctlz_zero_poison_i32_with_select:
; EG: ; %bb.0:
; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
@@ -499,7 +499,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i32_with_select(ptr addrspace(1) no
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; EG-NEXT: FFBH_UINT * T1.X, KC0[2].Z,
;
-; GFX9-GISEL-LABEL: s_ctlz_zero_undef_i32_with_select:
+; GFX9-GISEL-LABEL: s_ctlz_zero_poison_i32_with_select:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
@@ -516,8 +516,8 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i32_with_select(ptr addrspace(1) no
ret void
}
-define amdgpu_kernel void @s_ctlz_zero_undef_i64_with_select(ptr addrspace(1) noalias %out, i64 %val) nounwind {
-; SI-LABEL: s_ctlz_zero_undef_i64_with_select:
+define amdgpu_kernel void @s_ctlz_zero_poison_i64_with_select(ptr addrspace(1) noalias %out, i64 %val) nounwind {
+; SI-LABEL: s_ctlz_zero_poison_i64_with_select:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -531,7 +531,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i64_with_select(ptr addrspace(1) no
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: s_ctlz_zero_undef_i64_with_select:
+; VI-LABEL: s_ctlz_zero_poison_i64_with_select:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: v_mov_b32_e32 v3, 0
@@ -543,7 +543,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i64_with_select(ptr addrspace(1) no
; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-NEXT: s_endpgm
;
-; EG-LABEL: s_ctlz_zero_undef_i64_with_select:
+; EG-LABEL: s_ctlz_zero_poison_i64_with_select:
; EG: ; %bb.0:
; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
@@ -559,7 +559,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i64_with_select(ptr addrspace(1) no
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: s_ctlz_zero_undef_i64_with_select:
+; GFX9-GISEL-LABEL: s_ctlz_zero_poison_i64_with_select:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: s_mov_b32 s5, 0
@@ -577,8 +577,8 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i64_with_select(ptr addrspace(1) no
ret void
}
-define amdgpu_kernel void @v_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {
-; SI-LABEL: v_ctlz_zero_undef_i8_with_select:
+define amdgpu_kernel void @v_ctlz_zero_poison_i8_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {
+; SI-LABEL: v_ctlz_zero_poison_i8_with_select:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -599,7 +599,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_ctlz_zero_undef_i8_with_select:
+; VI-LABEL: v_ctlz_zero_poison_i8_with_select:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
@@ -617,7 +617,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
; VI-NEXT: flat_store_byte v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_ctlz_zero_undef_i8_with_select:
+; EG-LABEL: v_ctlz_zero_poison_i8_with_select:
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -648,7 +648,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i8_with_select:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_i8_with_select:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0
@@ -671,8 +671,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
ret void
}
-define amdgpu_kernel void @v_ctlz_zero_undef_i16_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {
-; SI-LABEL: v_ctlz_zero_undef_i16_with_select:
+define amdgpu_kernel void @v_ctlz_zero_poison_i16_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {
+; SI-LABEL: v_ctlz_zero_poison_i16_with_select:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -697,7 +697,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_ctlz_zero_undef_i16_with_select:
+; VI-LABEL: v_ctlz_zero_poison_i16_with_select:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
@@ -725,7 +725,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_ctlz_zero_undef_i16_with_select:
+; EG-LABEL: v_ctlz_zero_poison_i16_with_select:
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -756,7 +756,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i16_with_select:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_i16_with_select:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0
@@ -784,8 +784,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
ret void
}
-define amdgpu_kernel void @v_ctlz_zero_undef_i32_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {
-; SI-LABEL: v_ctlz_zero_undef_i32_with_select:
+define amdgpu_kernel void @v_ctlz_zero_poison_i32_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {
+; SI-LABEL: v_ctlz_zero_poison_i32_with_select:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -816,7 +816,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_with_select(ptr addrspace(1) no
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_ctlz_zero_undef_i32_with_select:
+; VI-LABEL: v_ctlz_zero_poison_i32_with_select:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
@@ -854,7 +854,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_with_select(ptr addrspace(1) no
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_ctlz_zero_undef_i32_with_select:
+; EG-LABEL: v_ctlz_zero_poison_i32_with_select:
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 1 @6
@@ -876,7 +876,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_with_select(ptr addrspace(1) no
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45)
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i32_with_select:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_i32_with_select:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0
@@ -912,8 +912,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_with_select(ptr addrspace(1) no
ret void
}
-define amdgpu_kernel void @v_ctlz_zero_undef_i64_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {
-; SI-LABEL: v_ctlz_zero_undef_i64_with_select:
+define amdgpu_kernel void @v_ctlz_zero_poison_i64_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {
+; SI-LABEL: v_ctlz_zero_poison_i64_with_select:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000
@@ -958,7 +958,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i64_with_select(ptr addrspace(1) no
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_ctlz_zero_undef_i64_with_select:
+; VI-LABEL: v_ctlz_zero_poison_i64_with_select:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
@@ -1029,7 +1029,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i64_with_select(ptr addrspace(1) no
; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_ctlz_zero_undef_i64_with_select:
+; EG-LABEL: v_ctlz_zero_poison_i64_with_select:
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 3 @6
@@ -1062,7 +1062,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i64_with_select(ptr addrspace(1) no
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i64_with_select:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_i64_with_select:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0
@@ -1119,8 +1119,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i64_with_select(ptr addrspace(1) no
ret void
}
-define amdgpu_kernel void @v_ctlz_zero_undef_i8(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
-; SI-LABEL: v_ctlz_zero_undef_i8:
+define amdgpu_kernel void @v_ctlz_zero_poison_i8(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
+; SI-LABEL: v_ctlz_zero_poison_i8:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -1139,7 +1139,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8(ptr addrspace(1) noalias %out, p
; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_ctlz_zero_undef_i8:
+; VI-LABEL: v_ctlz_zero_poison_i8:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
@@ -1155,7 +1155,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8(ptr addrspace(1) noalias %out, p
; VI-NEXT: flat_store_byte v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_ctlz_zero_undef_i8:
+; EG-LABEL: v_ctlz_zero_poison_i8:
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -1184,7 +1184,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8(ptr addrspace(1) noalias %out, p
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i8:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_i8:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v0
@@ -1208,8 +1208,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8(ptr addrspace(1) noalias %out, p
ret void
}
-define amdgpu_kernel void @s_ctlz_zero_undef_i64(ptr addrspace(1) noalias %out, [8 x i32], i64 %val) nounwind {
-; SI-LABEL: s_ctlz_zero_undef_i64:
+define amdgpu_kernel void @s_ctlz_zero_poison_i64(ptr addrspace(1) noalias %out, [8 x i32], i64 %val) nounwind {
+; SI-LABEL: s_ctlz_zero_poison_i64:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x13
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
@@ -1222,7 +1222,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i64(ptr addrspace(1) noalias %out,
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: s_ctlz_zero_undef_i64:
+; VI-LABEL: s_ctlz_zero_poison_i64:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x4c
; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
@@ -1235,7 +1235,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i64(ptr addrspace(1) noalias %out,
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
;
-; EG-LABEL: s_ctlz_zero_undef_i64:
+; EG-LABEL: s_ctlz_zero_poison_i64:
; EG: ; %bb.0:
; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
@@ -1251,7 +1251,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i64(ptr addrspace(1) noalias %out,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: s_ctlz_zero_undef_i64:
+; GFX9-GISEL-LABEL: s_ctlz_zero_poison_i64:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x4c
; GFX9-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
@@ -1268,8 +1268,8 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i64(ptr addrspace(1) noalias %out,
ret void
}
-define amdgpu_kernel void @s_ctlz_zero_undef_i64_trunc(ptr addrspace(1) noalias %out, i64 %val) nounwind {
-; SI-LABEL: s_ctlz_zero_undef_i64_trunc:
+define amdgpu_kernel void @s_ctlz_zero_poison_i64_trunc(ptr addrspace(1) noalias %out, i64 %val) nounwind {
+; SI-LABEL: s_ctlz_zero_poison_i64_trunc:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -1282,7 +1282,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i64_trunc(ptr addrspace(1) noalias
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: s_ctlz_zero_undef_i64_trunc:
+; VI-LABEL: s_ctlz_zero_poison_i64_trunc:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
@@ -1293,7 +1293,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i64_trunc(ptr addrspace(1) noalias
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: s_ctlz_zero_undef_i64_trunc:
+; EG-LABEL: s_ctlz_zero_poison_i64_trunc:
; EG: ; %bb.0:
; EG-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
@@ -1308,7 +1308,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i64_trunc(ptr addrspace(1) noalias
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: s_ctlz_zero_undef_i64_trunc:
+; GFX9-GISEL-LABEL: s_ctlz_zero_poison_i64_trunc:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0
@@ -1323,8 +1323,8 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i64_trunc(ptr addrspace(1) noalias
ret void
}
-define amdgpu_kernel void @v_ctlz_zero_undef_i64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {
-; SI-LABEL: v_ctlz_zero_undef_i64:
+define amdgpu_kernel void @v_ctlz_zero_poison_i64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {
+; SI-LABEL: v_ctlz_zero_poison_i64:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -1344,7 +1344,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i64(ptr addrspace(1) noalias %out,
; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_ctlz_zero_undef_i64:
+; VI-LABEL: v_ctlz_zero_poison_i64:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v3, 3, v0
@@ -1365,7 +1365,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i64(ptr addrspace(1) noalias %out,
; VI-NEXT: flat_store_dwordx2 v[3:4], v[1:2]
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_ctlz_zero_undef_i64:
+; EG-LABEL: v_ctlz_zero_poison_i64:
; EG: ; %bb.0:
; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -1390,7 +1390,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i64(ptr addrspace(1) noalias %out,
; EG-NEXT: LSHR * T1.X, PV.W, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i64:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_i64:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v3, 3, v0
@@ -1413,8 +1413,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i64(ptr addrspace(1) noalias %out,
ret void
}
-define amdgpu_kernel void @v_ctlz_zero_undef_i64_trunc(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {
-; SI-LABEL: v_ctlz_zero_undef_i64_trunc:
+define amdgpu_kernel void @v_ctlz_zero_poison_i64_trunc(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {
+; SI-LABEL: v_ctlz_zero_poison_i64_trunc:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -1434,7 +1434,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i64_trunc(ptr addrspace(1) noalias
; SI-NEXT: buffer_store_dword v0, v[1:2], s[0:3], 0 addr64
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_ctlz_zero_undef_i64_trunc:
+; VI-LABEL: v_ctlz_zero_poison_i64_trunc:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v1, 3, v0
@@ -1455,7 +1455,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i64_trunc(ptr addrspace(1) noalias
; VI-NEXT: flat_store_dword v[3:4], v0
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_ctlz_zero_undef_i64_trunc:
+; EG-LABEL: v_ctlz_zero_poison_i64_trunc:
; EG: ; %bb.0:
; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -1480,7 +1480,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i64_trunc(ptr addrspace(1) noalias
; EG-NEXT: LSHR * T1.X, PV.W, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i64_trunc:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_i64_trunc:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v1, 3, v0
@@ -1504,8 +1504,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i64_trunc(ptr addrspace(1) noalias
ret void
}
-define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
-; SI-LABEL: v_ctlz_zero_undef_i32_sel_eq_neg1:
+define amdgpu_kernel void @v_ctlz_zero_poison_i32_sel_eq_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
+; SI-LABEL: v_ctlz_zero_poison_i32_sel_eq_neg1:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -1524,7 +1524,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1(ptr addrspace(1) no
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_ctlz_zero_undef_i32_sel_eq_neg1:
+; VI-LABEL: v_ctlz_zero_poison_i32_sel_eq_neg1:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -1540,7 +1540,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1(ptr addrspace(1) no
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_ctlz_zero_undef_i32_sel_eq_neg1:
+; EG-LABEL: v_ctlz_zero_poison_i32_sel_eq_neg1:
; EG: ; %bb.0:
; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -1560,7 +1560,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1(ptr addrspace(1) no
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
; EG-NEXT: -1(nan), 2(2.802597e-45)
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i32_sel_eq_neg1:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_i32_sel_eq_neg1:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -1583,8 +1583,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1(ptr addrspace(1) no
ret void
}
-define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
-; SI-LABEL: v_ctlz_zero_undef_i32_sel_ne_neg1:
+define amdgpu_kernel void @v_ctlz_zero_poison_i32_sel_ne_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
+; SI-LABEL: v_ctlz_zero_poison_i32_sel_ne_neg1:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -1603,7 +1603,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_neg1(ptr addrspace(1) no
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_ctlz_zero_undef_i32_sel_ne_neg1:
+; VI-LABEL: v_ctlz_zero_poison_i32_sel_ne_neg1:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -1619,7 +1619,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_neg1(ptr addrspace(1) no
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_ctlz_zero_undef_i32_sel_ne_neg1:
+; EG-LABEL: v_ctlz_zero_poison_i32_sel_ne_neg1:
; EG: ; %bb.0:
; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -1639,7 +1639,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_neg1(ptr addrspace(1) no
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
; EG-NEXT: -1(nan), 2(2.802597e-45)
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i32_sel_ne_neg1:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_i32_sel_ne_neg1:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -1662,8 +1662,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_neg1(ptr addrspace(1) no
ret void
}
-define amdgpu_kernel void @v_ctlz_zero_undef_i8_sel_eq_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
-; SI-LABEL: v_ctlz_zero_undef_i8_sel_eq_neg1:
+define amdgpu_kernel void @v_ctlz_zero_poison_i8_sel_eq_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
+; SI-LABEL: v_ctlz_zero_poison_i8_sel_eq_neg1:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -1681,7 +1681,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8_sel_eq_neg1(ptr addrspace(1) noa
; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_ctlz_zero_undef_i8_sel_eq_neg1:
+; VI-LABEL: v_ctlz_zero_poison_i8_sel_eq_neg1:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
@@ -1696,7 +1696,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8_sel_eq_neg1(ptr addrspace(1) noa
; VI-NEXT: flat_store_byte v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_ctlz_zero_undef_i8_sel_eq_neg1:
+; EG-LABEL: v_ctlz_zero_poison_i8_sel_eq_neg1:
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -1723,7 +1723,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8_sel_eq_neg1(ptr addrspace(1) noa
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i8_sel_eq_neg1:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_i8_sel_eq_neg1:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v0
@@ -1752,8 +1752,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8_sel_eq_neg1(ptr addrspace(1) noa
ret void
}
-define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1_two_use(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
-; SI-LABEL: v_ctlz_zero_undef_i32_sel_eq_neg1_two_use:
+define amdgpu_kernel void @v_ctlz_zero_poison_i32_sel_eq_neg1_two_use(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
+; SI-LABEL: v_ctlz_zero_poison_i32_sel_eq_neg1_two_use:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -1777,7 +1777,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1_two_use(ptr addrspa
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_ctlz_zero_undef_i32_sel_eq_neg1_two_use:
+; VI-LABEL: v_ctlz_zero_poison_i32_sel_eq_neg1_two_use:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -1798,7 +1798,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1_two_use(ptr addrspa
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_ctlz_zero_undef_i32_sel_eq_neg1_two_use:
+; EG-LABEL: v_ctlz_zero_poison_i32_sel_eq_neg1_two_use:
; EG: ; %bb.0:
; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -1826,7 +1826,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1_two_use(ptr addrspa
; EG-NEXT: LSHR * T3.X, KC0[2].Y, literal.y,
; EG-NEXT: -1(nan), 2(2.802597e-45)
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i32_sel_eq_neg1_two_use:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_i32_sel_eq_neg1_two_use:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -1855,8 +1855,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1_two_use(ptr addrspa
}
; Selected on wrong constant
-define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_0(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
-; SI-LABEL: v_ctlz_zero_undef_i32_sel_eq_0:
+define amdgpu_kernel void @v_ctlz_zero_poison_i32_sel_eq_0(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
+; SI-LABEL: v_ctlz_zero_poison_i32_sel_eq_0:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -1877,7 +1877,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_0(ptr addrspace(1) noali
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_ctlz_zero_undef_i32_sel_eq_0:
+; VI-LABEL: v_ctlz_zero_poison_i32_sel_eq_0:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -1895,7 +1895,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_0(ptr addrspace(1) noali
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_ctlz_zero_undef_i32_sel_eq_0:
+; EG-LABEL: v_ctlz_zero_poison_i32_sel_eq_0:
; EG: ; %bb.0:
; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -1915,7 +1915,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_0(ptr addrspace(1) noali
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i32_sel_eq_0:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_i32_sel_eq_0:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -1939,8 +1939,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_0(ptr addrspace(1) noali
}
; Selected on wrong constant
-define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_0(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
-; SI-LABEL: v_ctlz_zero_undef_i32_sel_ne_0:
+define amdgpu_kernel void @v_ctlz_zero_poison_i32_sel_ne_0(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
+; SI-LABEL: v_ctlz_zero_poison_i32_sel_ne_0:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -1961,7 +1961,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_0(ptr addrspace(1) noali
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_ctlz_zero_undef_i32_sel_ne_0:
+; VI-LABEL: v_ctlz_zero_poison_i32_sel_ne_0:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -1979,7 +1979,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_0(ptr addrspace(1) noali
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_ctlz_zero_undef_i32_sel_ne_0:
+; EG-LABEL: v_ctlz_zero_poison_i32_sel_ne_0:
; EG: ; %bb.0:
; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -1999,7 +1999,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_0(ptr addrspace(1) noali
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i32_sel_ne_0:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_i32_sel_ne_0:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -2023,8 +2023,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_0(ptr addrspace(1) noali
}
; Compare on wrong constant
-define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_cmp_non0(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
-; SI-LABEL: v_ctlz_zero_undef_i32_sel_eq_cmp_non0:
+define amdgpu_kernel void @v_ctlz_zero_poison_i32_sel_eq_cmp_non0(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
+; SI-LABEL: v_ctlz_zero_poison_i32_sel_eq_cmp_non0:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -2045,7 +2045,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_cmp_non0(ptr addrspace(1
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_ctlz_zero_undef_i32_sel_eq_cmp_non0:
+; VI-LABEL: v_ctlz_zero_poison_i32_sel_eq_cmp_non0:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -2063,7 +2063,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_cmp_non0(ptr addrspace(1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_ctlz_zero_undef_i32_sel_eq_cmp_non0:
+; EG-LABEL: v_ctlz_zero_poison_i32_sel_eq_cmp_non0:
; EG: ; %bb.0:
; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -2084,7 +2084,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_cmp_non0(ptr addrspace(1
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i32_sel_eq_cmp_non0:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_i32_sel_eq_cmp_non0:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -2108,8 +2108,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_cmp_non0(ptr addrspace(1
}
; Selected on wrong constant
-define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_cmp_non0(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
-; SI-LABEL: v_ctlz_zero_undef_i32_sel_ne_cmp_non0:
+define amdgpu_kernel void @v_ctlz_zero_poison_i32_sel_ne_cmp_non0(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
+; SI-LABEL: v_ctlz_zero_poison_i32_sel_ne_cmp_non0:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -2130,7 +2130,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_cmp_non0(ptr addrspace(1
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_ctlz_zero_undef_i32_sel_ne_cmp_non0:
+; VI-LABEL: v_ctlz_zero_poison_i32_sel_ne_cmp_non0:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -2148,7 +2148,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_cmp_non0(ptr addrspace(1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_ctlz_zero_undef_i32_sel_ne_cmp_non0:
+; EG-LABEL: v_ctlz_zero_poison_i32_sel_ne_cmp_non0:
; EG: ; %bb.0:
; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -2169,7 +2169,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_cmp_non0(ptr addrspace(1
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i32_sel_ne_cmp_non0:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_i32_sel_ne_cmp_non0:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -2192,27 +2192,27 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_cmp_non0(ptr addrspace(1
ret void
}
-define i7 @v_ctlz_zero_undef_i7(i7 %val) {
-; SI-LABEL: v_ctlz_zero_undef_i7:
+define i7 @v_ctlz_zero_poison_i7(i7 %val) {
+; SI-LABEL: v_ctlz_zero_poison_i7:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 25, v0
; SI-NEXT: v_ffbh_u32_e32 v0, v0
; SI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_ctlz_zero_undef_i7:
+; VI-LABEL: v_ctlz_zero_poison_i7:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshlrev_b32_e32 v0, 25, v0
; VI-NEXT: v_ffbh_u32_e32 v0, v0
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; EG-LABEL: v_ctlz_zero_undef_i7:
+; EG-LABEL: v_ctlz_zero_poison_i7:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i7:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_i7:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 25, v0
@@ -2222,8 +2222,8 @@ define i7 @v_ctlz_zero_undef_i7(i7 %val) {
ret i7 %ctlz
}
-define amdgpu_kernel void @s_ctlz_zero_undef_i18(ptr addrspace(1) noalias %out, i18 %val) nounwind {
-; SI-LABEL: s_ctlz_zero_undef_i18:
+define amdgpu_kernel void @s_ctlz_zero_poison_i18(ptr addrspace(1) noalias %out, i18 %val) nounwind {
+; SI-LABEL: s_ctlz_zero_poison_i18:
; SI: ; %bb.0:
; SI-NEXT: s_load_dword s2, s[4:5], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
@@ -2240,7 +2240,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i18(ptr addrspace(1) noalias %out,
; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:2
; SI-NEXT: s_endpgm
;
-; VI-LABEL: s_ctlz_zero_undef_i18:
+; VI-LABEL: s_ctlz_zero_poison_i18:
; VI: ; %bb.0:
; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
@@ -2260,7 +2260,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i18(ptr addrspace(1) noalias %out,
; VI-NEXT: flat_store_byte v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: s_ctlz_zero_undef_i18:
+; EG-LABEL: s_ctlz_zero_poison_i18:
; EG: ; %bb.0:
; EG-NEXT: ALU 28, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT MSKOR T1.XW, T3.X
@@ -2297,7 +2297,7 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i18(ptr addrspace(1) noalias %out,
; EG-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: s_ctlz_zero_undef_i18:
+; GFX9-GISEL-LABEL: s_ctlz_zero_poison_i18:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
@@ -2317,27 +2317,27 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i18(ptr addrspace(1) noalias %out,
ret void
}
-define i18 @v_ctlz_zero_undef_i18(i18 %val) {
-; SI-LABEL: v_ctlz_zero_undef_i18:
+define i18 @v_ctlz_zero_poison_i18(i18 %val) {
+; SI-LABEL: v_ctlz_zero_poison_i18:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 14, v0
; SI-NEXT: v_ffbh_u32_e32 v0, v0
; SI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_ctlz_zero_undef_i18:
+; VI-LABEL: v_ctlz_zero_poison_i18:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshlrev_b32_e32 v0, 14, v0
; VI-NEXT: v_ffbh_u32_e32 v0, v0
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; EG-LABEL: v_ctlz_zero_undef_i18:
+; EG-LABEL: v_ctlz_zero_poison_i18:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i18:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_i18:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 14, v0
@@ -2347,8 +2347,8 @@ define i18 @v_ctlz_zero_undef_i18(i18 %val) {
ret i18 %ctlz
}
-define <2 x i18> @v_ctlz_zero_undef_v2i18(<2 x i18> %val) {
-; SI-LABEL: v_ctlz_zero_undef_v2i18:
+define <2 x i18> @v_ctlz_zero_poison_v2i18(<2 x i18> %val) {
+; SI-LABEL: v_ctlz_zero_poison_v2i18:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 14, v0
@@ -2357,7 +2357,7 @@ define <2 x i18> @v_ctlz_zero_undef_v2i18(<2 x i18> %val) {
; SI-NEXT: v_ffbh_u32_e32 v1, v1
; SI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_ctlz_zero_undef_v2i18:
+; VI-LABEL: v_ctlz_zero_poison_v2i18:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshlrev_b32_e32 v0, 14, v0
@@ -2366,12 +2366,12 @@ define <2 x i18> @v_ctlz_zero_undef_v2i18(<2 x i18> %val) {
; VI-NEXT: v_ffbh_u32_e32 v1, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; EG-LABEL: v_ctlz_zero_undef_v2i18:
+; EG-LABEL: v_ctlz_zero_poison_v2i18:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v2i18:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_v2i18:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 14, v0
@@ -2383,8 +2383,8 @@ define <2 x i18> @v_ctlz_zero_undef_v2i18(<2 x i18> %val) {
ret <2 x i18> %ctlz
}
-define <2 x i16> @v_ctlz_zero_undef_v2i16(<2 x i16> %val) {
-; SI-LABEL: v_ctlz_zero_undef_v2i16:
+define <2 x i16> @v_ctlz_zero_poison_v2i16(<2 x i16> %val) {
+; SI-LABEL: v_ctlz_zero_poison_v2i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
@@ -2395,7 +2395,7 @@ define <2 x i16> @v_ctlz_zero_undef_v2i16(<2 x i16> %val) {
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_ctlz_zero_undef_v2i16:
+; VI-LABEL: v_ctlz_zero_poison_v2i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
@@ -2405,12 +2405,12 @@ define <2 x i16> @v_ctlz_zero_undef_v2i16(<2 x i16> %val) {
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; EG-LABEL: v_ctlz_zero_undef_v2i16:
+; EG-LABEL: v_ctlz_zero_poison_v2i16:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v2i16:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_v2i16:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
@@ -2425,8 +2425,8 @@ define <2 x i16> @v_ctlz_zero_undef_v2i16(<2 x i16> %val) {
ret <2 x i16> %ctlz
}
-define <3 x i16> @v_ctlz_zero_undef_v3i16(<3 x i16> %val) {
-; SI-LABEL: v_ctlz_zero_undef_v3i16:
+define <3 x i16> @v_ctlz_zero_poison_v3i16(<3 x i16> %val) {
+; SI-LABEL: v_ctlz_zero_poison_v3i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
@@ -2439,7 +2439,7 @@ define <3 x i16> @v_ctlz_zero_undef_v3i16(<3 x i16> %val) {
; SI-NEXT: v_or_b32_e32 v0, v0, v2
; SI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_ctlz_zero_undef_v3i16:
+; VI-LABEL: v_ctlz_zero_poison_v3i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v0
@@ -2451,12 +2451,12 @@ define <3 x i16> @v_ctlz_zero_undef_v3i16(<3 x i16> %val) {
; VI-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; EG-LABEL: v_ctlz_zero_undef_v3i16:
+; EG-LABEL: v_ctlz_zero_poison_v3i16:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v3i16:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_v3i16:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -2475,8 +2475,8 @@ define <3 x i16> @v_ctlz_zero_undef_v3i16(<3 x i16> %val) {
ret <3 x i16> %ctlz
}
-define <4 x i16> @v_ctlz_zero_undef_v4i16(<4 x i16> %val) {
-; SI-LABEL: v_ctlz_zero_undef_v4i16:
+define <4 x i16> @v_ctlz_zero_poison_v4i16(<4 x i16> %val) {
+; SI-LABEL: v_ctlz_zero_poison_v4i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
@@ -2494,7 +2494,7 @@ define <4 x i16> @v_ctlz_zero_undef_v4i16(<4 x i16> %val) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_ctlz_zero_undef_v4i16:
+; VI-LABEL: v_ctlz_zero_poison_v4i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v1
@@ -2509,12 +2509,12 @@ define <4 x i16> @v_ctlz_zero_undef_v4i16(<4 x i16> %val) {
; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; EG-LABEL: v_ctlz_zero_undef_v4i16:
+; EG-LABEL: v_ctlz_zero_poison_v4i16:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v4i16:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_v4i16:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -2536,8 +2536,8 @@ define <4 x i16> @v_ctlz_zero_undef_v4i16(<4 x i16> %val) {
ret <4 x i16> %ctlz
}
-define <2 x i8> @v_ctlz_zero_undef_v2i8(<2 x i8> %val) {
-; SI-LABEL: v_ctlz_zero_undef_v2i8:
+define <2 x i8> @v_ctlz_zero_poison_v2i8(<2 x i8> %val) {
+; SI-LABEL: v_ctlz_zero_poison_v2i8:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
@@ -2548,7 +2548,7 @@ define <2 x i8> @v_ctlz_zero_undef_v2i8(<2 x i8> %val) {
; SI-NEXT: v_or_b32_e32 v0, v0, v2
; SI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_ctlz_zero_undef_v2i8:
+; VI-LABEL: v_ctlz_zero_poison_v2i8:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
@@ -2560,12 +2560,12 @@ define <2 x i8> @v_ctlz_zero_undef_v2i8(<2 x i8> %val) {
; VI-NEXT: v_and_b32_e32 v1, 0xff, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; EG-LABEL: v_ctlz_zero_undef_v2i8:
+; EG-LABEL: v_ctlz_zero_poison_v2i8:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v2i8:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_v2i8:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 24, v0
@@ -2577,8 +2577,8 @@ define <2 x i8> @v_ctlz_zero_undef_v2i8(<2 x i8> %val) {
ret <2 x i8> %ctlz
}
-define <2 x i7> @v_ctlz_zero_undef_v2i7(<2 x i7> %val) {
-; SI-LABEL: v_ctlz_zero_undef_v2i7:
+define <2 x i7> @v_ctlz_zero_poison_v2i7(<2 x i7> %val) {
+; SI-LABEL: v_ctlz_zero_poison_v2i7:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 25, v0
@@ -2587,7 +2587,7 @@ define <2 x i7> @v_ctlz_zero_undef_v2i7(<2 x i7> %val) {
; SI-NEXT: v_ffbh_u32_e32 v1, v1
; SI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_ctlz_zero_undef_v2i7:
+; VI-LABEL: v_ctlz_zero_poison_v2i7:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshlrev_b32_e32 v0, 25, v0
@@ -2596,12 +2596,12 @@ define <2 x i7> @v_ctlz_zero_undef_v2i7(<2 x i7> %val) {
; VI-NEXT: v_ffbh_u32_e32 v1, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; EG-LABEL: v_ctlz_zero_undef_v2i7:
+; EG-LABEL: v_ctlz_zero_poison_v2i7:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
;
-; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v2i7:
+; GFX9-GISEL-LABEL: v_ctlz_zero_poison_v2i7:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 25, v0
diff --git a/llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll b/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
similarity index 94%
rename from llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
rename to llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
index cbfda51a61c29..0f5ee9d407f25 100644
--- a/llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
+++ b/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
@@ -13,8 +13,8 @@ declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1) nounwind readnone
declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1) nounwind readnone
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
-define amdgpu_kernel void @s_cttz_zero_undef_i32(ptr addrspace(1) noalias %out, i32 %val) nounwind {
-; SI-LABEL: s_cttz_zero_undef_i32:
+define amdgpu_kernel void @s_cttz_zero_poison_i32(ptr addrspace(1) noalias %out, i32 %val) nounwind {
+; SI-LABEL: s_cttz_zero_poison_i32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dword s2, s[4:5], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
@@ -26,7 +26,7 @@ define amdgpu_kernel void @s_cttz_zero_undef_i32(ptr addrspace(1) noalias %out,
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: s_cttz_zero_undef_i32:
+; VI-LABEL: s_cttz_zero_poison_i32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
@@ -38,7 +38,7 @@ define amdgpu_kernel void @s_cttz_zero_undef_i32(ptr addrspace(1) noalias %out,
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: s_cttz_zero_undef_i32:
+; EG-LABEL: s_cttz_zero_poison_i32:
; EG: ; %bb.0:
; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
@@ -49,7 +49,7 @@ define amdgpu_kernel void @s_cttz_zero_undef_i32(ptr addrspace(1) noalias %out,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; EG-NEXT: FFBL_INT * T1.X, KC0[2].Z,
;
-; GFX9-GISEL-LABEL: s_cttz_zero_undef_i32:
+; GFX9-GISEL-LABEL: s_cttz_zero_poison_i32:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
@@ -64,8 +64,8 @@ define amdgpu_kernel void @s_cttz_zero_undef_i32(ptr addrspace(1) noalias %out,
ret void
}
-define amdgpu_kernel void @v_cttz_zero_undef_i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
-; SI-LABEL: v_cttz_zero_undef_i32:
+define amdgpu_kernel void @v_cttz_zero_poison_i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
+; SI-LABEL: v_cttz_zero_poison_i32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -84,7 +84,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_i32(ptr addrspace(1) noalias %out,
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_cttz_zero_undef_i32:
+; VI-LABEL: v_cttz_zero_poison_i32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -100,7 +100,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_i32(ptr addrspace(1) noalias %out,
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_cttz_zero_undef_i32:
+; EG-LABEL: v_cttz_zero_poison_i32:
; EG: ; %bb.0:
; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -119,7 +119,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_i32(ptr addrspace(1) noalias %out,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: v_cttz_zero_undef_i32:
+; GFX9-GISEL-LABEL: v_cttz_zero_poison_i32:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -138,8 +138,8 @@ define amdgpu_kernel void @v_cttz_zero_undef_i32(ptr addrspace(1) noalias %out,
ret void
}
-define amdgpu_kernel void @v_cttz_zero_undef_v2i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
-; SI-LABEL: v_cttz_zero_undef_v2i32:
+define amdgpu_kernel void @v_cttz_zero_poison_v2i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
+; SI-LABEL: v_cttz_zero_poison_v2i32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -159,7 +159,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_v2i32(ptr addrspace(1) noalias %out
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_cttz_zero_undef_v2i32:
+; VI-LABEL: v_cttz_zero_poison_v2i32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
@@ -176,7 +176,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_v2i32(ptr addrspace(1) noalias %out
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_cttz_zero_undef_v2i32:
+; EG-LABEL: v_cttz_zero_poison_v2i32:
; EG: ; %bb.0:
; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -196,7 +196,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_v2i32(ptr addrspace(1) noalias %out
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: v_cttz_zero_undef_v2i32:
+; GFX9-GISEL-LABEL: v_cttz_zero_poison_v2i32:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 3, v0
@@ -216,8 +216,8 @@ define amdgpu_kernel void @v_cttz_zero_undef_v2i32(ptr addrspace(1) noalias %out
ret void
}
-define amdgpu_kernel void @v_cttz_zero_undef_v4i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
-; SI-LABEL: v_cttz_zero_undef_v4i32:
+define amdgpu_kernel void @v_cttz_zero_poison_v4i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
+; SI-LABEL: v_cttz_zero_poison_v4i32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -239,7 +239,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_v4i32(ptr addrspace(1) noalias %out
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_cttz_zero_undef_v4i32:
+; VI-LABEL: v_cttz_zero_poison_v4i32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 4, v0
@@ -258,7 +258,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_v4i32(ptr addrspace(1) noalias %out
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_cttz_zero_undef_v4i32:
+; EG-LABEL: v_cttz_zero_poison_v4i32:
; EG: ; %bb.0:
; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -280,7 +280,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_v4i32(ptr addrspace(1) noalias %out
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: v_cttz_zero_undef_v4i32:
+; GFX9-GISEL-LABEL: v_cttz_zero_poison_v4i32:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 4, v0
@@ -302,8 +302,8 @@ define amdgpu_kernel void @v_cttz_zero_undef_v4i32(ptr addrspace(1) noalias %out
ret void
}
-define amdgpu_kernel void @s_cttz_zero_undef_i8_with_select(ptr addrspace(1) noalias %out, i8 %val) nounwind {
-; SI-LABEL: s_cttz_zero_undef_i8_with_select:
+define amdgpu_kernel void @s_cttz_zero_poison_i8_with_select(ptr addrspace(1) noalias %out, i8 %val) nounwind {
+; SI-LABEL: s_cttz_zero_poison_i8_with_select:
; SI: ; %bb.0:
; SI-NEXT: s_load_dword s2, s[4:5], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
@@ -315,7 +315,7 @@ define amdgpu_kernel void @s_cttz_zero_undef_i8_with_select(ptr addrspace(1) noa
; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: s_cttz_zero_undef_i8_with_select:
+; VI-LABEL: s_cttz_zero_poison_i8_with_select:
; VI: ; %bb.0:
; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
@@ -327,7 +327,7 @@ define amdgpu_kernel void @s_cttz_zero_undef_i8_with_select(ptr addrspace(1) noa
; VI-NEXT: flat_store_byte v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: s_cttz_zero_undef_i8_with_select:
+; EG-LABEL: s_cttz_zero_poison_i8_with_select:
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @8, KC0[], KC1[]
; EG-NEXT: TEX 0 @6
@@ -354,7 +354,7 @@ define amdgpu_kernel void @s_cttz_zero_undef_i8_with_select(ptr addrspace(1) noa
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: s_cttz_zero_undef_i8_with_select:
+; GFX9-GISEL-LABEL: s_cttz_zero_poison_i8_with_select:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
@@ -371,8 +371,8 @@ define amdgpu_kernel void @s_cttz_zero_undef_i8_with_select(ptr addrspace(1) noa
ret void
}
-define amdgpu_kernel void @s_cttz_zero_undef_i16_with_select(ptr addrspace(1) noalias %out, i16 %val) nounwind {
-; SI-LABEL: s_cttz_zero_undef_i16_with_select:
+define amdgpu_kernel void @s_cttz_zero_poison_i16_with_select(ptr addrspace(1) noalias %out, i16 %val) nounwind {
+; SI-LABEL: s_cttz_zero_poison_i16_with_select:
; SI: ; %bb.0:
; SI-NEXT: s_load_dword s2, s[4:5], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
@@ -384,7 +384,7 @@ define amdgpu_kernel void @s_cttz_zero_undef_i16_with_select(ptr addrspace(1) no
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: s_cttz_zero_undef_i16_with_select:
+; VI-LABEL: s_cttz_zero_poison_i16_with_select:
; VI: ; %bb.0:
; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
@@ -396,7 +396,7 @@ define amdgpu_kernel void @s_cttz_zero_undef_i16_with_select(ptr addrspace(1) no
; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: s_cttz_zero_undef_i16_with_select:
+; EG-LABEL: s_cttz_zero_poison_i16_with_select:
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @8, KC0[], KC1[]
; EG-NEXT: TEX 0 @6
@@ -423,7 +423,7 @@ define amdgpu_kernel void @s_cttz_zero_undef_i16_with_select(ptr addrspace(1) no
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: s_cttz_zero_undef_i16_with_select:
+; GFX9-GISEL-LABEL: s_cttz_zero_poison_i16_with_select:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
@@ -440,8 +440,8 @@ define amdgpu_kernel void @s_cttz_zero_undef_i16_with_select(ptr addrspace(1) no
ret void
}
-define amdgpu_kernel void @s_cttz_zero_undef_i32_with_select(ptr addrspace(1) noalias %out, i32 %val) nounwind {
-; SI-LABEL: s_cttz_zero_undef_i32_with_select:
+define amdgpu_kernel void @s_cttz_zero_poison_i32_with_select(ptr addrspace(1) noalias %out, i32 %val) nounwind {
+; SI-LABEL: s_cttz_zero_poison_i32_with_select:
; SI: ; %bb.0:
; SI-NEXT: s_load_dword s2, s[4:5], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
@@ -453,7 +453,7 @@ define amdgpu_kernel void @s_cttz_zero_undef_i32_with_select(ptr addrspace(1) no
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: s_cttz_zero_undef_i32_with_select:
+; VI-LABEL: s_cttz_zero_poison_i32_with_select:
; VI: ; %bb.0:
; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
@@ -465,7 +465,7 @@ define amdgpu_kernel void @s_cttz_zero_undef_i32_with_select(ptr addrspace(1) no
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: s_cttz_zero_undef_i32_with_select:
+; EG-LABEL: s_cttz_zero_poison_i32_with_select:
; EG: ; %bb.0:
; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
@@ -476,7 +476,7 @@ define amdgpu_kernel void @s_cttz_zero_undef_i32_with_select(ptr addrspace(1) no
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; EG-NEXT: FFBL_INT * T1.X, KC0[2].Z,
;
-; GFX9-GISEL-LABEL: s_cttz_zero_undef_i32_with_select:
+; GFX9-GISEL-LABEL: s_cttz_zero_poison_i32_with_select:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
@@ -493,8 +493,8 @@ define amdgpu_kernel void @s_cttz_zero_undef_i32_with_select(ptr addrspace(1) no
ret void
}
-define amdgpu_kernel void @s_cttz_zero_undef_i64_with_select(ptr addrspace(1) noalias %out, i64 %val) nounwind {
-; SI-LABEL: s_cttz_zero_undef_i64_with_select:
+define amdgpu_kernel void @s_cttz_zero_poison_i64_with_select(ptr addrspace(1) noalias %out, i64 %val) nounwind {
+; SI-LABEL: s_cttz_zero_poison_i64_with_select:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -508,7 +508,7 @@ define amdgpu_kernel void @s_cttz_zero_undef_i64_with_select(ptr addrspace(1) no
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: s_cttz_zero_undef_i64_with_select:
+; VI-LABEL: s_cttz_zero_poison_i64_with_select:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: v_mov_b32_e32 v3, 0
@@ -520,7 +520,7 @@ define amdgpu_kernel void @s_cttz_zero_undef_i64_with_select(ptr addrspace(1) no
; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-NEXT: s_endpgm
;
-; EG-LABEL: s_cttz_zero_undef_i64_with_select:
+; EG-LABEL: s_cttz_zero_poison_i64_with_select:
; EG: ; %bb.0:
; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
@@ -536,7 +536,7 @@ define amdgpu_kernel void @s_cttz_zero_undef_i64_with_select(ptr addrspace(1) no
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: s_cttz_zero_undef_i64_with_select:
+; GFX9-GISEL-LABEL: s_cttz_zero_poison_i64_with_select:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: s_mov_b32 s5, 0
@@ -554,8 +554,8 @@ define amdgpu_kernel void @s_cttz_zero_undef_i64_with_select(ptr addrspace(1) no
ret void
}
-define amdgpu_kernel void @v_cttz_zero_undef_i8_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {
-; SI-LABEL: v_cttz_zero_undef_i8_with_select:
+define amdgpu_kernel void @v_cttz_zero_poison_i8_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {
+; SI-LABEL: v_cttz_zero_poison_i8_with_select:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -575,7 +575,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_i8_with_select(ptr addrspace(1) noa
; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_cttz_zero_undef_i8_with_select:
+; VI-LABEL: v_cttz_zero_poison_i8_with_select:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
@@ -592,7 +592,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_i8_with_select(ptr addrspace(1) noa
; VI-NEXT: flat_store_byte v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_cttz_zero_undef_i8_with_select:
+; EG-LABEL: v_cttz_zero_poison_i8_with_select:
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -621,7 +621,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_i8_with_select(ptr addrspace(1) noa
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: v_cttz_zero_undef_i8_with_select:
+; GFX9-GISEL-LABEL: v_cttz_zero_poison_i8_with_select:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0
@@ -643,8 +643,8 @@ define amdgpu_kernel void @v_cttz_zero_undef_i8_with_select(ptr addrspace(1) noa
ret void
}
-define amdgpu_kernel void @v_cttz_zero_undef_i16_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {
-; SI-LABEL: v_cttz_zero_undef_i16_with_select:
+define amdgpu_kernel void @v_cttz_zero_poison_i16_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {
+; SI-LABEL: v_cttz_zero_poison_i16_with_select:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -668,7 +668,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_i16_with_select(ptr addrspace(1) no
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_cttz_zero_undef_i16_with_select:
+; VI-LABEL: v_cttz_zero_poison_i16_with_select:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
@@ -693,7 +693,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_i16_with_select(ptr addrspace(1) no
; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_cttz_zero_undef_i16_with_select:
+; EG-LABEL: v_cttz_zero_poison_i16_with_select:
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
@@ -722,7 +722,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_i16_with_select(ptr addrspace(1) no
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: v_cttz_zero_undef_i16_with_select:
+; GFX9-GISEL-LABEL: v_cttz_zero_poison_i16_with_select:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0
@@ -749,8 +749,8 @@ define amdgpu_kernel void @v_cttz_zero_undef_i16_with_select(ptr addrspace(1) no
ret void
}
-define amdgpu_kernel void @v_cttz_zero_undef_i32_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {
-; SI-LABEL: v_cttz_zero_undef_i32_with_select:
+define amdgpu_kernel void @v_cttz_zero_poison_i32_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {
+; SI-LABEL: v_cttz_zero_poison_i32_with_select:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
@@ -781,7 +781,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_i32_with_select(ptr addrspace(1) no
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_cttz_zero_undef_i32_with_select:
+; VI-LABEL: v_cttz_zero_poison_i32_with_select:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
@@ -819,7 +819,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_i32_with_select(ptr addrspace(1) no
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_cttz_zero_undef_i32_with_select:
+; EG-LABEL: v_cttz_zero_poison_i32_with_select:
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 1 @6
@@ -841,7 +841,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_i32_with_select(ptr addrspace(1) no
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45)
;
-; GFX9-GISEL-LABEL: v_cttz_zero_undef_i32_with_select:
+; GFX9-GISEL-LABEL: v_cttz_zero_poison_i32_with_select:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0
@@ -877,8 +877,8 @@ define amdgpu_kernel void @v_cttz_zero_undef_i32_with_select(ptr addrspace(1) no
ret void
}
-define amdgpu_kernel void @v_cttz_zero_undef_i64_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {
-; SI-LABEL: v_cttz_zero_undef_i64_with_select:
+define amdgpu_kernel void @v_cttz_zero_poison_i64_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {
+; SI-LABEL: v_cttz_zero_poison_i64_with_select:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000
@@ -923,7 +923,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_i64_with_select(ptr addrspace(1) no
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_cttz_zero_undef_i64_with_select:
+; VI-LABEL: v_cttz_zero_poison_i64_with_select:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
@@ -994,7 +994,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_i64_with_select(ptr addrspace(1) no
; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-NEXT: s_endpgm
;
-; EG-LABEL: v_cttz_zero_undef_i64_with_select:
+; EG-LABEL: v_cttz_zero_poison_i64_with_select:
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 3 @6
@@ -1027,7 +1027,7 @@ define amdgpu_kernel void @v_cttz_zero_undef_i64_with_select(ptr addrspace(1) no
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX9-GISEL-LABEL: v_cttz_zero_undef_i64_with_select:
+; GFX9-GISEL-LABEL: v_cttz_zero_poison_i64_with_select:
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir
index 42c3ae3a889ba..b3ee77360798f 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir
@@ -3,11 +3,11 @@
# RUN: llc -O0 -mtriple arm-linux-gnueabi -mattr=-v5t -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,LIBCALLS
--- |
define void @test_ctlz_s32() { ret void }
- define void @test_ctlz_zero_undef_s32() { ret void }
+ define void @test_ctlz_zero_poison_s32() { ret void }
; same as above but with extensions
define void @test_ctlz_s16() { ret void }
- define void @test_ctlz_zero_undef_s8() { ret void }
+ define void @test_ctlz_zero_poison_s8() { ret void }
...
---
name: test_ctlz_s32
@@ -47,8 +47,8 @@ body: |
BX_RET 14, $noreg, implicit $r0
...
---
-name: test_ctlz_zero_undef_s32
-# CHECK-LABEL: name: test_ctlz_zero_undef_s32
+name: test_ctlz_zero_poison_s32
+# CHECK-LABEL: name: test_ctlz_zero_poison_s32
legalized: false
# CHECK: legalized: true
regBankSelected: false
@@ -72,7 +72,7 @@ body: |
; LIBCALLS: [[R:%[0-9]+]]:_(s32) = COPY $r0
; LIBCALLS: ADJCALLSTACKUP
; LIBCALLS-NOT: G_CTLZ
- %1(s32) = G_CTLZ_ZERO_UNDEF %0
+ %1(s32) = G_CTLZ_ZERO_POISON %0
; CHECK: $r0 = COPY [[R]]
$r0 = COPY %1(s32)
@@ -128,8 +128,8 @@ body: |
BX_RET 14, $noreg, implicit $r0
...
---
-name: test_ctlz_zero_undef_s8
-# CHECK-LABEL: name: test_ctlz_zero_undef_s8
+name: test_ctlz_zero_poison_s8
+# CHECK-LABEL: name: test_ctlz_zero_poison_s8
legalized: false
# CHECK: legalized: true
regBankSelected: false
@@ -159,8 +159,8 @@ body: |
; LIBCALLS: ADJCALLSTACKUP
; LIBCALLS-NOT: G_CTLZ
; CLZ: [[COUNT:%[0-9]+]]:_(s32) = G_CTLZ [[R32]]
- ; CLZ-NOT: G_CTLZ_ZERO_UNDEF
- %2(s8) = G_CTLZ_ZERO_UNDEF %1
+ ; CLZ-NOT: G_CTLZ_ZERO_POISON
+ %2(s8) = G_CTLZ_ZERO_POISON %1
; LIBCALLS: [[SHIFTEDR:%[0-9]+]]:_(s32) = G_SHL [[COUNT]], [[BITDIFF]]
; LIBCALLS: [[R:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDR]], [[BITDIFF]]
diff --git a/llvm/test/CodeGen/ARM/cttz.ll b/llvm/test/CodeGen/ARM/cttz.ll
index ae76452b4d2cd..b6c410b2639e0 100644
--- a/llvm/test/CodeGen/ARM/cttz.ll
+++ b/llvm/test/CodeGen/ARM/cttz.ll
@@ -366,8 +366,8 @@ define i64 @test_i64(i64 %a) {
;------------------------------------------------------------------------------
-define i8 @test_i8_zero_undef(i8 %a) {
-; CHECK-5-LABEL: test_i8_zero_undef:
+define i8 @test_i8_zero_poison(i8 %a) {
+; CHECK-5-LABEL: test_i8_zero_poison:
; CHECK-5: @ %bb.0:
; CHECK-5-NEXT: sub r1, r0, #1
; CHECK-5-NEXT: bic r0, r1, r0
@@ -375,13 +375,13 @@ define i8 @test_i8_zero_undef(i8 %a) {
; CHECK-5-NEXT: rsb r0, r0, #32
; CHECK-5-NEXT: bx lr
;
-; CHECK-LABEL: test_i8_zero_undef:
+; CHECK-LABEL: test_i8_zero_poison:
; CHECK: @ %bb.0:
; CHECK-NEXT: rbit r0, r0
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: bx lr
;
-; CHECK-6M-LABEL: test_i8_zero_undef:
+; CHECK-6M-LABEL: test_i8_zero_poison:
; CHECK-6M: @ %bb.0:
; CHECK-6M-NEXT: cmp r0, #0
; CHECK-6M-NEXT: beq .LBB4_2
@@ -404,7 +404,7 @@ define i8 @test_i8_zero_undef(i8 %a) {
; CHECK-6M-NEXT: .LCPI4_1:
; CHECK-6M-NEXT: .ascii "\000\001\034\002\035\016\030\003\036\026\024\017\031\021\004\b\037\033\r\027\025\023\020\007\032\f\022\006\013\005\n\t"
;
-; CHECK-8MBASE-LABEL: test_i8_zero_undef:
+; CHECK-8MBASE-LABEL: test_i8_zero_poison:
; CHECK-8MBASE: @ %bb.0:
; CHECK-8MBASE-NEXT: cbz r0, .LBB4_2
; CHECK-8MBASE-NEXT: @ %bb.1:
@@ -428,8 +428,8 @@ define i8 @test_i8_zero_undef(i8 %a) {
ret i8 %tmp
}
-define i16 @test_i16_zero_undef(i16 %a) {
-; CHECK-5-LABEL: test_i16_zero_undef:
+define i16 @test_i16_zero_poison(i16 %a) {
+; CHECK-5-LABEL: test_i16_zero_poison:
; CHECK-5: @ %bb.0:
; CHECK-5-NEXT: sub r1, r0, #1
; CHECK-5-NEXT: bic r0, r1, r0
@@ -437,13 +437,13 @@ define i16 @test_i16_zero_undef(i16 %a) {
; CHECK-5-NEXT: rsb r0, r0, #32
; CHECK-5-NEXT: bx lr
;
-; CHECK-LABEL: test_i16_zero_undef:
+; CHECK-LABEL: test_i16_zero_poison:
; CHECK: @ %bb.0:
; CHECK-NEXT: rbit r0, r0
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: bx lr
;
-; CHECK-6M-LABEL: test_i16_zero_undef:
+; CHECK-6M-LABEL: test_i16_zero_poison:
; CHECK-6M: @ %bb.0:
; CHECK-6M-NEXT: cmp r0, #0
; CHECK-6M-NEXT: beq .LBB5_2
@@ -466,7 +466,7 @@ define i16 @test_i16_zero_undef(i16 %a) {
; CHECK-6M-NEXT: .LCPI5_1:
; CHECK-6M-NEXT: .ascii "\000\001\034\002\035\016\030\003\036\026\024\017\031\021\004\b\037\033\r\027\025\023\020\007\032\f\022\006\013\005\n\t"
;
-; CHECK-8MBASE-LABEL: test_i16_zero_undef:
+; CHECK-8MBASE-LABEL: test_i16_zero_poison:
; CHECK-8MBASE: @ %bb.0:
; CHECK-8MBASE-NEXT: cbz r0, .LBB5_2
; CHECK-8MBASE-NEXT: @ %bb.1:
@@ -491,8 +491,8 @@ define i16 @test_i16_zero_undef(i16 %a) {
}
-define i32 @test_i32_zero_undef(i32 %a) {
-; CHECK-5-LABEL: test_i32_zero_undef:
+define i32 @test_i32_zero_poison(i32 %a) {
+; CHECK-5-LABEL: test_i32_zero_poison:
; CHECK-5: @ %bb.0:
; CHECK-5-NEXT: sub r1, r0, #1
; CHECK-5-NEXT: bic r0, r1, r0
@@ -500,13 +500,13 @@ define i32 @test_i32_zero_undef(i32 %a) {
; CHECK-5-NEXT: rsb r0, r0, #32
; CHECK-5-NEXT: bx lr
;
-; CHECK-LABEL: test_i32_zero_undef:
+; CHECK-LABEL: test_i32_zero_poison:
; CHECK: @ %bb.0:
; CHECK-NEXT: rbit r0, r0
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: bx lr
;
-; CHECK-6M-LABEL: test_i32_zero_undef:
+; CHECK-6M-LABEL: test_i32_zero_poison:
; CHECK-6M: @ %bb.0:
; CHECK-6M-NEXT: cmp r0, #0
; CHECK-6M-NEXT: beq .LBB6_2
@@ -529,7 +529,7 @@ define i32 @test_i32_zero_undef(i32 %a) {
; CHECK-6M-NEXT: .LCPI6_1:
; CHECK-6M-NEXT: .ascii "\000\001\034\002\035\016\030\003\036\026\024\017\031\021\004\b\037\033\r\027\025\023\020\007\032\f\022\006\013\005\n\t"
;
-; CHECK-8MBASE-LABEL: test_i32_zero_undef:
+; CHECK-8MBASE-LABEL: test_i32_zero_poison:
; CHECK-8MBASE: @ %bb.0:
; CHECK-8MBASE-NEXT: cbz r0, .LBB6_2
; CHECK-8MBASE-NEXT: @ %bb.1:
@@ -553,8 +553,8 @@ define i32 @test_i32_zero_undef(i32 %a) {
ret i32 %tmp
}
-define i64 @test_i64_zero_undef(i64 %a) {
-; CHECK-5-LABEL: test_i64_zero_undef:
+define i64 @test_i64_zero_poison(i64 %a) {
+; CHECK-5-LABEL: test_i64_zero_poison:
; CHECK-5: @ %bb.0:
; CHECK-5-NEXT: sub r3, r1, #1
; CHECK-5-NEXT: sub r2, r0, #1
@@ -569,7 +569,7 @@ define i64 @test_i64_zero_undef(i64 %a) {
; CHECK-5-NEXT: mov r1, #0
; CHECK-5-NEXT: bx lr
;
-; CHECK-LABEL: test_i64_zero_undef:
+; CHECK-LABEL: test_i64_zero_poison:
; CHECK: @ %bb.0:
; CHECK-NEXT: rbit r1, r1
; CHECK-NEXT: rbit r2, r0
@@ -581,7 +581,7 @@ define i64 @test_i64_zero_undef(i64 %a) {
; CHECK-NEXT: mov r1, #0
; CHECK-NEXT: bx lr
;
-; CHECK-6M-LABEL: test_i64_zero_undef:
+; CHECK-6M-LABEL: test_i64_zero_poison:
; CHECK-6M: @ %bb.0:
; CHECK-6M-NEXT: .save {r4, r5, r7, lr}
; CHECK-6M-NEXT: push {r4, r5, r7, lr}
@@ -625,7 +625,7 @@ define i64 @test_i64_zero_undef(i64 %a) {
; CHECK-6M-NEXT: .LCPI7_1:
; CHECK-6M-NEXT: .ascii "\000\001\034\002\035\016\030\003\036\026\024\017\031\021\004\b\037\033\r\027\025\023\020\007\032\f\022\006\013\005\n\t"
;
-; CHECK-8MBASE-LABEL: test_i64_zero_undef:
+; CHECK-8MBASE-LABEL: test_i64_zero_poison:
; CHECK-8MBASE: @ %bb.0:
; CHECK-8MBASE-NEXT: .save {r4, r5, r7, lr}
; CHECK-8MBASE-NEXT: push {r4, r5, r7, lr}
diff --git a/llvm/test/CodeGen/ARM/cttz_vector.ll b/llvm/test/CodeGen/ARM/cttz_vector.ll
index 988ea5d4acb12..ba4fb074db9c2 100644
--- a/llvm/test/CodeGen/ARM/cttz_vector.ll
+++ b/llvm/test/CodeGen/ARM/cttz_vector.ll
@@ -282,8 +282,8 @@ define void @test_v2i64(ptr %p) {
;------------------------------------------------------------------------------
-define void @test_v1i8_zero_undef(ptr %p) {
-; CHECK-LABEL: test_v1i8_zero_undef:
+define void @test_v1i8_zero_poison(ptr %p) {
+; CHECK-LABEL: test_v1i8_zero_poison:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldrb r1, [r0]
; CHECK-NEXT: rbit r1, r1
@@ -296,8 +296,8 @@ define void @test_v1i8_zero_undef(ptr %p) {
ret void
}
-define void @test_v2i8_zero_undef(ptr %p) {
-; CHECK-LABEL: test_v2i8_zero_undef:
+define void @test_v2i8_zero_poison(ptr %p) {
+; CHECK-LABEL: test_v2i8_zero_poison:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.16 {d16[0]}, [r0:16]
; CHECK-NEXT: vmovl.u8 q8, d16
@@ -318,8 +318,8 @@ define void @test_v2i8_zero_undef(ptr %p) {
ret void
}
-define void @test_v4i8_zero_undef(ptr %p) {
-; CHECK-LABEL: test_v4i8_zero_undef:
+define void @test_v4i8_zero_poison(ptr %p) {
+; CHECK-LABEL: test_v4i8_zero_poison:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.32 {d16[0]}, [r0:32]
; CHECK-NEXT: vmovl.u8 q8, d16
@@ -337,8 +337,8 @@ define void @test_v4i8_zero_undef(ptr %p) {
ret void
}
-define void @test_v8i8_zero_undef(ptr %p) {
-; CHECK-LABEL: test_v8i8_zero_undef:
+define void @test_v8i8_zero_poison(ptr %p) {
+; CHECK-LABEL: test_v8i8_zero_poison:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vmov.i8 d18, #0x1
@@ -354,8 +354,8 @@ define void @test_v8i8_zero_undef(ptr %p) {
ret void
}
-define void @test_v16i8_zero_undef(ptr %p) {
-; CHECK-LABEL: test_v16i8_zero_undef:
+define void @test_v16i8_zero_poison(ptr %p) {
+; CHECK-LABEL: test_v16i8_zero_poison:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vmov.i8 q10, #0x1
@@ -371,8 +371,8 @@ define void @test_v16i8_zero_undef(ptr %p) {
ret void
}
-define void @test_v1i16_zero_undef(ptr %p) {
-; CHECK-LABEL: test_v1i16_zero_undef:
+define void @test_v1i16_zero_poison(ptr %p) {
+; CHECK-LABEL: test_v1i16_zero_poison:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldrh r1, [r0]
; CHECK-NEXT: rbit r1, r1
@@ -385,8 +385,8 @@ define void @test_v1i16_zero_undef(ptr %p) {
ret void
}
-define void @test_v2i16_zero_undef(ptr %p) {
-; CHECK-LABEL: test_v2i16_zero_undef:
+define void @test_v2i16_zero_poison(ptr %p) {
+; CHECK-LABEL: test_v2i16_zero_poison:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.32 {d16[0]}, [r0:32]
; CHECK-NEXT: vmovl.u16 q8, d16
@@ -404,8 +404,8 @@ define void @test_v2i16_zero_undef(ptr %p) {
ret void
}
-define void @test_v4i16_zero_undef(ptr %p) {
-; CHECK-LABEL: test_v4i16_zero_undef:
+define void @test_v4i16_zero_poison(ptr %p) {
+; CHECK-LABEL: test_v4i16_zero_poison:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vneg.s16 d17, d16
@@ -421,8 +421,8 @@ define void @test_v4i16_zero_undef(ptr %p) {
ret void
}
-define void @test_v8i16_zero_undef(ptr %p) {
-; CHECK-LABEL: test_v8i16_zero_undef:
+define void @test_v8i16_zero_poison(ptr %p) {
+; CHECK-LABEL: test_v8i16_zero_poison:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vneg.s16 q9, q8
@@ -438,8 +438,8 @@ define void @test_v8i16_zero_undef(ptr %p) {
ret void
}
-define void @test_v1i32_zero_undef(ptr %p) {
-; CHECK-LABEL: test_v1i32_zero_undef:
+define void @test_v1i32_zero_poison(ptr %p) {
+; CHECK-LABEL: test_v1i32_zero_poison:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r1, [r0]
; CHECK-NEXT: rbit r1, r1
@@ -452,8 +452,8 @@ define void @test_v1i32_zero_undef(ptr %p) {
ret void
}
-define void @test_v2i32_zero_undef(ptr %p) {
-; CHECK-LABEL: test_v2i32_zero_undef:
+define void @test_v2i32_zero_poison(ptr %p) {
+; CHECK-LABEL: test_v2i32_zero_poison:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vneg.s32 d17, d16
@@ -469,8 +469,8 @@ define void @test_v2i32_zero_undef(ptr %p) {
ret void
}
-define void @test_v4i32_zero_undef(ptr %p) {
-; CHECK-LABEL: test_v4i32_zero_undef:
+define void @test_v4i32_zero_poison(ptr %p) {
+; CHECK-LABEL: test_v4i32_zero_poison:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vneg.s32 q9, q8
@@ -486,8 +486,8 @@ define void @test_v4i32_zero_undef(ptr %p) {
ret void
}
-define void @test_v1i64_zero_undef(ptr %p) {
-; CHECK-LABEL: test_v1i64_zero_undef:
+define void @test_v1i64_zero_poison(ptr %p) {
+; CHECK-LABEL: test_v1i64_zero_poison:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 d16, #0x0
; CHECK-NEXT: vldr d17, [r0]
@@ -507,8 +507,8 @@ define void @test_v1i64_zero_undef(ptr %p) {
ret void
}
-define void @test_v2i64_zero_undef(ptr %p) {
-; CHECK-LABEL: test_v2i64_zero_undef:
+define void @test_v2i64_zero_poison(ptr %p) {
+; CHECK-LABEL: test_v2i64_zero_poison:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 q8, #0x0
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
diff --git a/llvm/test/CodeGen/Lanai/i32.ll b/llvm/test/CodeGen/Lanai/i32.ll
index 632cc467d6811..a8a588ccbf506 100644
--- a/llvm/test/CodeGen/Lanai/i32.ll
+++ b/llvm/test/CodeGen/Lanai/i32.ll
@@ -114,10 +114,10 @@ define i32 @clz32(i32 %x) {
ret i32 %a
}
-; CHECK-LABEL: clz32_zero_undef:
+; CHECK-LABEL: clz32_zero_poison:
; CHECK-NOT: sub.f
; CHECK: leadz %r{{[0-9]+}}, %rv
-define i32 @clz32_zero_undef(i32 %x) {
+define i32 @clz32_zero_poison(i32 %x) {
%a = call i32 @llvm.ctlz.i32(i32 %x, i1 true)
ret i32 %a
}
@@ -129,10 +129,10 @@ define i32 @ctz32(i32 %x) {
ret i32 %a
}
-; CHECK-LABEL: ctz32_zero_undef:
+; CHECK-LABEL: ctz32_zero_poison:
; CHECK-NOT: sub.f
; CHECK: trailz %r{{[0-9]+}}, %rv
-define i32 @ctz32_zero_undef(i32 %x) {
+define i32 @ctz32_zero_poison(i32 %x) {
%a = call i32 @llvm.cttz.i32(i32 %x, i1 true)
ret i32 %a
}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir
index a06bb6da45d23..64cb476d961e2 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir
@@ -98,7 +98,7 @@ body: |
%0:_(s32) = COPY $a0
%2:_(s32) = G_CONSTANT i32 1
%4:_(s32) = G_CONSTANT i32 0
- %1:_(s32) = G_CTTZ_ZERO_UNDEF %0(s32)
+ %1:_(s32) = G_CTTZ_ZERO_POISON %0(s32)
%3:_(s32) = nuw nsw G_ADD %1, %2
%5:_(s1) = G_ICMP intpred(eq), %0(s32), %4
%6:_(s32) = G_SELECT %5(s1), %4, %3
@@ -158,7 +158,7 @@ body: |
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%4:_(s64) = G_CONSTANT i64 1
%6:_(s64) = G_CONSTANT i64 0
- %3:_(s64) = G_CTTZ_ZERO_UNDEF %0(s64)
+ %3:_(s64) = G_CTTZ_ZERO_POISON %0(s64)
%5:_(s64) = nuw nsw G_ADD %3, %4
%7:_(s1) = G_ICMP intpred(eq), %0(s64), %6
%8:_(s64) = G_SELECT %7(s1), %6, %5
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
index f3e00ed6521c4..edc8bb70ef21e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
@@ -737,14 +737,14 @@
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
-# DEBUG-NEXT: G_CTTZ_ZERO_UNDEF (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
+# DEBUG-NEXT: G_CTTZ_ZERO_POISON (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_CTLZ (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
-# DEBUG-NEXT: G_CTLZ_ZERO_UNDEF (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
+# DEBUG-NEXT: G_CTLZ_ZERO_POISON (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_CTLS (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv32.mir
index cb6a0da298fe8..f2d8683959222 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv32.mir
@@ -303,12 +303,12 @@ body: |
...
---
-name: ctlz_zero_undef_i8
+name: ctlz_zero_poison_i8
body: |
bb.1:
liveins: $x10
- ; RV32I-LABEL: name: ctlz_zero_undef_i8
+ ; RV32I-LABEL: name: ctlz_zero_poison_i8
; RV32I: liveins: $x10
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
@@ -348,7 +348,7 @@ body: |
; RV32I-NEXT: $x10 = COPY [[SUB1]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
- ; RV32ZBB-LABEL: name: ctlz_zero_undef_i8
+ ; RV32ZBB-LABEL: name: ctlz_zero_poison_i8
; RV32ZBB: liveins: $x10
; RV32ZBB-NEXT: {{ $}}
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
@@ -362,19 +362,19 @@ body: |
; RV32ZBB-NEXT: PseudoRET implicit $x10
%1:_(s32) = COPY $x10
%0:_(s8) = G_TRUNC %1(s32)
- %2:_(s8) = G_CTLZ_ZERO_UNDEF %0(s8)
+ %2:_(s8) = G_CTLZ_ZERO_POISON %0(s8)
%3:_(s32) = G_ANYEXT %2(s8)
$x10 = COPY %3(s32)
PseudoRET implicit $x10
...
---
-name: ctlz_zero_undef_i16
+name: ctlz_zero_poison_i16
body: |
bb.1:
liveins: $x10
- ; RV32I-LABEL: name: ctlz_zero_undef_i16
+ ; RV32I-LABEL: name: ctlz_zero_poison_i16
; RV32I: liveins: $x10
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
@@ -419,7 +419,7 @@ body: |
; RV32I-NEXT: $x10 = COPY [[SUB1]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
- ; RV32ZBB-LABEL: name: ctlz_zero_undef_i16
+ ; RV32ZBB-LABEL: name: ctlz_zero_poison_i16
; RV32ZBB: liveins: $x10
; RV32ZBB-NEXT: {{ $}}
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
@@ -433,19 +433,19 @@ body: |
; RV32ZBB-NEXT: PseudoRET implicit $x10
%1:_(s32) = COPY $x10
%0:_(s16) = G_TRUNC %1(s32)
- %2:_(s16) = G_CTLZ_ZERO_UNDEF %0(s16)
+ %2:_(s16) = G_CTLZ_ZERO_POISON %0(s16)
%3:_(s32) = G_ANYEXT %2(s16)
$x10 = COPY %3(s32)
PseudoRET implicit $x10
...
---
-name: ctlz_zero_undef_i32
+name: ctlz_zero_poison_i32
body: |
bb.1:
liveins: $x10
- ; RV32I-LABEL: name: ctlz_zero_undef_i32
+ ; RV32I-LABEL: name: ctlz_zero_poison_i32
; RV32I: liveins: $x10
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
@@ -486,7 +486,7 @@ body: |
; RV32I-NEXT: $x10 = COPY [[SUB1]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
- ; RV32ZBB-LABEL: name: ctlz_zero_undef_i32
+ ; RV32ZBB-LABEL: name: ctlz_zero_poison_i32
; RV32ZBB: liveins: $x10
; RV32ZBB-NEXT: {{ $}}
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
@@ -494,18 +494,18 @@ body: |
; RV32ZBB-NEXT: $x10 = COPY [[CTLZ]](s32)
; RV32ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
- %1:_(s32) = G_CTLZ_ZERO_UNDEF %0(s32)
+ %1:_(s32) = G_CTLZ_ZERO_POISON %0(s32)
$x10 = COPY %1(s32)
PseudoRET implicit $x10
...
---
-name: ctlz_zero_undef_i64
+name: ctlz_zero_poison_i64
body: |
bb.1:
liveins: $x10, $x11
- ; RV32I-LABEL: name: ctlz_zero_undef_i64
+ ; RV32I-LABEL: name: ctlz_zero_poison_i64
; RV32I: liveins: $x10, $x11
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
@@ -575,7 +575,7 @@ body: |
; RV32I-NEXT: $x11 = COPY [[C]](s32)
; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11
;
- ; RV32ZBB-LABEL: name: ctlz_zero_undef_i64
+ ; RV32ZBB-LABEL: name: ctlz_zero_poison_i64
; RV32ZBB: liveins: $x10, $x11
; RV32ZBB-NEXT: {{ $}}
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
@@ -593,7 +593,7 @@ body: |
%1:_(s32) = COPY $x10
%2:_(s32) = COPY $x11
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
- %3:_(s64) = G_CTLZ_ZERO_UNDEF %0(s64)
+ %3:_(s64) = G_CTLZ_ZERO_POISON %0(s64)
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
$x10 = COPY %4(s32)
$x11 = COPY %5(s32)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
index d65b1f26aa900..32288a44dcfac 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
@@ -280,12 +280,12 @@ body: |
...
---
-name: ctlz_zero_undef_i8
+name: ctlz_zero_poison_i8
body: |
bb.1:
liveins: $x10
- ; RV64I-LABEL: name: ctlz_zero_undef_i8
+ ; RV64I-LABEL: name: ctlz_zero_poison_i8
; RV64I: liveins: $x10
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
@@ -325,7 +325,7 @@ body: |
; RV64I-NEXT: $x10 = COPY [[SUB1]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
- ; RV64ZBB-LABEL: name: ctlz_zero_undef_i8
+ ; RV64ZBB-LABEL: name: ctlz_zero_poison_i8
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
@@ -339,19 +339,19 @@ body: |
; RV64ZBB-NEXT: PseudoRET implicit $x10
%1:_(s64) = COPY $x10
%0:_(s8) = G_TRUNC %1(s64)
- %2:_(s8) = G_CTLZ_ZERO_UNDEF %0(s8)
+ %2:_(s8) = G_CTLZ_ZERO_POISON %0(s8)
%3:_(s64) = G_ANYEXT %2(s8)
$x10 = COPY %3(s64)
PseudoRET implicit $x10
...
---
-name: ctlz_zero_undef_i16
+name: ctlz_zero_poison_i16
body: |
bb.1:
liveins: $x10
- ; RV64I-LABEL: name: ctlz_zero_undef_i16
+ ; RV64I-LABEL: name: ctlz_zero_poison_i16
; RV64I: liveins: $x10
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
@@ -396,7 +396,7 @@ body: |
; RV64I-NEXT: $x10 = COPY [[SUB1]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
- ; RV64ZBB-LABEL: name: ctlz_zero_undef_i16
+ ; RV64ZBB-LABEL: name: ctlz_zero_poison_i16
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
@@ -410,19 +410,19 @@ body: |
; RV64ZBB-NEXT: PseudoRET implicit $x10
%1:_(s64) = COPY $x10
%0:_(s16) = G_TRUNC %1(s64)
- %2:_(s16) = G_CTLZ_ZERO_UNDEF %0(s16)
+ %2:_(s16) = G_CTLZ_ZERO_POISON %0(s16)
%3:_(s64) = G_ANYEXT %2(s16)
$x10 = COPY %3(s64)
PseudoRET implicit $x10
...
---
-name: ctlz_zero_undef_i32
+name: ctlz_zero_poison_i32
body: |
bb.1:
liveins: $x10
- ; RV64I-LABEL: name: ctlz_zero_undef_i32
+ ; RV64I-LABEL: name: ctlz_zero_poison_i32
; RV64I: liveins: $x10
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
@@ -476,7 +476,7 @@ body: |
; RV64I-NEXT: $x10 = COPY [[SEXT_INREG3]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
- ; RV64ZBB-LABEL: name: ctlz_zero_undef_i32
+ ; RV64ZBB-LABEL: name: ctlz_zero_poison_i32
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
@@ -485,19 +485,19 @@ body: |
; RV64ZBB-NEXT: PseudoRET implicit $x10
%1:_(s64) = COPY $x10
%0:_(s32) = G_TRUNC %1(s64)
- %2:_(s32) = G_CTLZ_ZERO_UNDEF %0(s32)
+ %2:_(s32) = G_CTLZ_ZERO_POISON %0(s32)
%3:_(s64) = G_ANYEXT %2(s32)
$x10 = COPY %3(s64)
PseudoRET implicit $x10
...
---
-name: ctlz_zero_undef_i64
+name: ctlz_zero_poison_i64
body: |
bb.1:
liveins: $x10
- ; RV64I-LABEL: name: ctlz_zero_undef_i64
+ ; RV64I-LABEL: name: ctlz_zero_poison_i64
; RV64I: liveins: $x10
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
@@ -541,7 +541,7 @@ body: |
; RV64I-NEXT: $x10 = COPY [[SUB1]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
- ; RV64ZBB-LABEL: name: ctlz_zero_undef_i64
+ ; RV64ZBB-LABEL: name: ctlz_zero_poison_i64
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
@@ -549,7 +549,7 @@ body: |
; RV64ZBB-NEXT: $x10 = COPY [[CTLZ]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
- %1:_(s64) = G_CTLZ_ZERO_UNDEF %0(s64)
+ %1:_(s64) = G_CTLZ_ZERO_POISON %0(s64)
$x10 = COPY %1(s64)
PseudoRET implicit $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv32.mir
index a4a06854fa18d..df05cf770e07d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv32.mir
@@ -255,12 +255,12 @@ body: |
...
---
-name: cttz_zero_undef_i8
+name: cttz_zero_poison_i8
body: |
bb.1:
liveins: $x10
- ; RV32I-LABEL: name: cttz_zero_undef_i8
+ ; RV32I-LABEL: name: cttz_zero_poison_i8
; RV32I: liveins: $x10
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
@@ -293,7 +293,7 @@ body: |
; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
- ; RV32ZBB-LABEL: name: cttz_zero_undef_i8
+ ; RV32ZBB-LABEL: name: cttz_zero_poison_i8
; RV32ZBB: liveins: $x10
; RV32ZBB-NEXT: {{ $}}
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
@@ -305,19 +305,19 @@ body: |
; RV32ZBB-NEXT: PseudoRET implicit $x10
%1:_(s32) = COPY $x10
%0:_(s8) = G_TRUNC %1(s32)
- %2:_(s8) = G_CTTZ_ZERO_UNDEF %0(s8)
+ %2:_(s8) = G_CTTZ_ZERO_POISON %0(s8)
%3:_(s32) = G_ANYEXT %2(s8)
$x10 = COPY %3(s32)
PseudoRET implicit $x10
...
---
-name: cttz_zero_undef_i16
+name: cttz_zero_poison_i16
body: |
bb.1:
liveins: $x10
- ; RV32I-LABEL: name: cttz_zero_undef_i16
+ ; RV32I-LABEL: name: cttz_zero_poison_i16
; RV32I: liveins: $x10
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
@@ -352,7 +352,7 @@ body: |
; RV32I-NEXT: $x10 = COPY [[AND7]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
- ; RV32ZBB-LABEL: name: cttz_zero_undef_i16
+ ; RV32ZBB-LABEL: name: cttz_zero_poison_i16
; RV32ZBB: liveins: $x10
; RV32ZBB-NEXT: {{ $}}
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
@@ -364,19 +364,19 @@ body: |
; RV32ZBB-NEXT: PseudoRET implicit $x10
%1:_(s32) = COPY $x10
%0:_(s16) = G_TRUNC %1(s32)
- %2:_(s16) = G_CTTZ_ZERO_UNDEF %0(s16)
+ %2:_(s16) = G_CTTZ_ZERO_POISON %0(s16)
%3:_(s32) = G_ANYEXT %2(s16)
$x10 = COPY %3(s32)
PseudoRET implicit $x10
...
---
-name: cttz_zero_undef_i32
+name: cttz_zero_poison_i32
body: |
bb.1:
liveins: $x10
- ; RV32I-LABEL: name: cttz_zero_undef_i32
+ ; RV32I-LABEL: name: cttz_zero_poison_i32
; RV32I: liveins: $x10
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
@@ -407,7 +407,7 @@ body: |
; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
- ; RV32ZBB-LABEL: name: cttz_zero_undef_i32
+ ; RV32ZBB-LABEL: name: cttz_zero_poison_i32
; RV32ZBB: liveins: $x10
; RV32ZBB-NEXT: {{ $}}
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
@@ -415,18 +415,18 @@ body: |
; RV32ZBB-NEXT: $x10 = COPY [[CTTZ]](s32)
; RV32ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
- %1:_(s32) = G_CTTZ_ZERO_UNDEF %0(s32)
+ %1:_(s32) = G_CTTZ_ZERO_POISON %0(s32)
$x10 = COPY %1(s32)
PseudoRET implicit $x10
...
---
-name: cttz_zero_undef_i64
+name: cttz_zero_poison_i64
body: |
bb.1:
liveins: $x10, $x11
- ; RV32I-LABEL: name: cttz_zero_undef_i64
+ ; RV32I-LABEL: name: cttz_zero_poison_i64
; RV32I: liveins: $x10, $x11
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
@@ -479,7 +479,7 @@ body: |
; RV32I-NEXT: $x11 = COPY [[C]](s32)
; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11
;
- ; RV32ZBB-LABEL: name: cttz_zero_undef_i64
+ ; RV32ZBB-LABEL: name: cttz_zero_poison_i64
; RV32ZBB: liveins: $x10, $x11
; RV32ZBB-NEXT: {{ $}}
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
@@ -497,7 +497,7 @@ body: |
%1:_(s32) = COPY $x10
%2:_(s32) = COPY $x11
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
- %3:_(s64) = G_CTTZ_ZERO_UNDEF %0(s64)
+ %3:_(s64) = G_CTTZ_ZERO_POISON %0(s64)
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
$x10 = COPY %4(s32)
$x11 = COPY %5(s32)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
index 82220a27d015d..289fce339f707 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
@@ -229,12 +229,12 @@ body: |
...
---
-name: cttz_zero_undef_i8
+name: cttz_zero_poison_i8
body: |
bb.1:
liveins: $x10
- ; RV64I-LABEL: name: cttz_zero_undef_i8
+ ; RV64I-LABEL: name: cttz_zero_poison_i8
; RV64I: liveins: $x10
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
@@ -267,7 +267,7 @@ body: |
; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
- ; RV64ZBB-LABEL: name: cttz_zero_undef_i8
+ ; RV64ZBB-LABEL: name: cttz_zero_poison_i8
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
@@ -278,19 +278,19 @@ body: |
; RV64ZBB-NEXT: PseudoRET implicit $x10
%1:_(s64) = COPY $x10
%0:_(s8) = G_TRUNC %1(s64)
- %2:_(s8) = G_CTTZ_ZERO_UNDEF %0(s8)
+ %2:_(s8) = G_CTTZ_ZERO_POISON %0(s8)
%3:_(s64) = G_ANYEXT %2(s8)
$x10 = COPY %3(s64)
PseudoRET implicit $x10
...
---
-name: cttz_zero_undef_i16
+name: cttz_zero_poison_i16
body: |
bb.1:
liveins: $x10
- ; RV64I-LABEL: name: cttz_zero_undef_i16
+ ; RV64I-LABEL: name: cttz_zero_poison_i16
; RV64I: liveins: $x10
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
@@ -325,7 +325,7 @@ body: |
; RV64I-NEXT: $x10 = COPY [[AND7]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
- ; RV64ZBB-LABEL: name: cttz_zero_undef_i16
+ ; RV64ZBB-LABEL: name: cttz_zero_poison_i16
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
@@ -336,19 +336,19 @@ body: |
; RV64ZBB-NEXT: PseudoRET implicit $x10
%1:_(s64) = COPY $x10
%0:_(s16) = G_TRUNC %1(s64)
- %2:_(s16) = G_CTTZ_ZERO_UNDEF %0(s16)
+ %2:_(s16) = G_CTTZ_ZERO_POISON %0(s16)
%3:_(s64) = G_ANYEXT %2(s16)
$x10 = COPY %3(s64)
PseudoRET implicit $x10
...
---
-name: cttz_zero_undef_i32
+name: cttz_zero_poison_i32
body: |
bb.1:
liveins: $x10
- ; RV64I-LABEL: name: cttz_zero_undef_i32
+ ; RV64I-LABEL: name: cttz_zero_poison_i32
; RV64I: liveins: $x10
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
@@ -387,7 +387,7 @@ body: |
; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
- ; RV64ZBB-LABEL: name: cttz_zero_undef_i32
+ ; RV64ZBB-LABEL: name: cttz_zero_poison_i32
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
@@ -396,19 +396,19 @@ body: |
; RV64ZBB-NEXT: PseudoRET implicit $x10
%1:_(s64) = COPY $x10
%0:_(s32) = G_TRUNC %1(s64)
- %2:_(s32) = G_CTTZ_ZERO_UNDEF %0(s32)
+ %2:_(s32) = G_CTTZ_ZERO_POISON %0(s32)
%3:_(s64) = G_ANYEXT %2(s32)
$x10 = COPY %3(s64)
PseudoRET implicit $x10
...
---
-name: cttz_zero_undef_i64
+name: cttz_zero_poison_i64
body: |
bb.1:
liveins: $x10
- ; RV64I-LABEL: name: cttz_zero_undef_i64
+ ; RV64I-LABEL: name: cttz_zero_poison_i64
; RV64I: liveins: $x10
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
@@ -439,7 +439,7 @@ body: |
; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
- ; RV64ZBB-LABEL: name: cttz_zero_undef_i64
+ ; RV64ZBB-LABEL: name: cttz_zero_poison_i64
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
@@ -447,7 +447,7 @@ body: |
; RV64ZBB-NEXT: $x10 = COPY [[CTTZ]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
- %1:_(s64) = G_CTTZ_ZERO_UNDEF %0(s64)
+ %1:_(s64) = G_CTTZ_ZERO_POISON %0(s64)
$x10 = COPY %1(s64)
PseudoRET implicit $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
index daac8440e5763..466f855d9aff4 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
@@ -435,8 +435,8 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind {
ret i32 %1
}
-define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
-; RV64I-LABEL: cttz_zero_undef_i32:
+define signext i32 @cttz_zero_poison_i32(i32 signext %a) nounwind {
+; RV64I-LABEL: cttz_zero_poison_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
@@ -467,7 +467,7 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64ZBB-LABEL: cttz_zero_undef_i32:
+; RV64ZBB-LABEL: cttz_zero_poison_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: ctzw a0, a0
; RV64ZBB-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
index 7f089782d87e0..fd21901d99186 100644
--- a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
+++ b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
@@ -558,8 +558,8 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
ret i64 %tmp
}
-define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
-; RV32_NOZBB-LABEL: test_cttz_i8_zero_undef:
+define i8 @test_cttz_i8_zero_poison(i8 %a) nounwind {
+; RV32_NOZBB-LABEL: test_cttz_i8_zero_poison:
; RV32_NOZBB: # %bb.0:
; RV32_NOZBB-NEXT: addi a1, a0, -1
; RV32_NOZBB-NEXT: not a0, a0
@@ -576,7 +576,7 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
; RV32_NOZBB-NEXT: andi a0, a0, 15
; RV32_NOZBB-NEXT: ret
;
-; RV64NOZBB-LABEL: test_cttz_i8_zero_undef:
+; RV64NOZBB-LABEL: test_cttz_i8_zero_poison:
; RV64NOZBB: # %bb.0:
; RV64NOZBB-NEXT: addi a1, a0, -1
; RV64NOZBB-NEXT: not a0, a0
@@ -593,17 +593,17 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
; RV64NOZBB-NEXT: andi a0, a0, 15
; RV64NOZBB-NEXT: ret
;
-; RV32ZBB-LABEL: test_cttz_i8_zero_undef:
+; RV32ZBB-LABEL: test_cttz_i8_zero_poison:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: ctz a0, a0
; RV32ZBB-NEXT: ret
;
-; RV64ZBB-LABEL: test_cttz_i8_zero_undef:
+; RV64ZBB-LABEL: test_cttz_i8_zero_poison:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: ctz a0, a0
; RV64ZBB-NEXT: ret
;
-; RV32XTHEADBB-LABEL: test_cttz_i8_zero_undef:
+; RV32XTHEADBB-LABEL: test_cttz_i8_zero_poison:
; RV32XTHEADBB: # %bb.0:
; RV32XTHEADBB-NEXT: addi a1, a0, -1
; RV32XTHEADBB-NEXT: not a0, a0
@@ -613,7 +613,7 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
; RV32XTHEADBB-NEXT: sub a0, a1, a0
; RV32XTHEADBB-NEXT: ret
;
-; RV64XTHEADBB-LABEL: test_cttz_i8_zero_undef:
+; RV64XTHEADBB-LABEL: test_cttz_i8_zero_poison:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: addi a1, a0, -1
; RV64XTHEADBB-NEXT: not a0, a0
@@ -626,8 +626,8 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
ret i8 %tmp
}
-define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
-; RV32_NOZBB-LABEL: test_cttz_i16_zero_undef:
+define i16 @test_cttz_i16_zero_poison(i16 %a) nounwind {
+; RV32_NOZBB-LABEL: test_cttz_i16_zero_poison:
; RV32_NOZBB: # %bb.0:
; RV32_NOZBB-NEXT: addi a1, a0, -1
; RV32_NOZBB-NEXT: not a0, a0
@@ -651,7 +651,7 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
; RV32_NOZBB-NEXT: add a0, a1, a0
; RV32_NOZBB-NEXT: ret
;
-; RV64NOZBB-LABEL: test_cttz_i16_zero_undef:
+; RV64NOZBB-LABEL: test_cttz_i16_zero_poison:
; RV64NOZBB: # %bb.0:
; RV64NOZBB-NEXT: addi a1, a0, -1
; RV64NOZBB-NEXT: not a0, a0
@@ -675,17 +675,17 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
; RV64NOZBB-NEXT: add a0, a1, a0
; RV64NOZBB-NEXT: ret
;
-; RV32ZBB-LABEL: test_cttz_i16_zero_undef:
+; RV32ZBB-LABEL: test_cttz_i16_zero_poison:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: ctz a0, a0
; RV32ZBB-NEXT: ret
;
-; RV64ZBB-LABEL: test_cttz_i16_zero_undef:
+; RV64ZBB-LABEL: test_cttz_i16_zero_poison:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: ctz a0, a0
; RV64ZBB-NEXT: ret
;
-; RV32XTHEADBB-LABEL: test_cttz_i16_zero_undef:
+; RV32XTHEADBB-LABEL: test_cttz_i16_zero_poison:
; RV32XTHEADBB: # %bb.0:
; RV32XTHEADBB-NEXT: addi a1, a0, -1
; RV32XTHEADBB-NEXT: not a0, a0
@@ -695,7 +695,7 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
; RV32XTHEADBB-NEXT: sub a0, a1, a0
; RV32XTHEADBB-NEXT: ret
;
-; RV64XTHEADBB-LABEL: test_cttz_i16_zero_undef:
+; RV64XTHEADBB-LABEL: test_cttz_i16_zero_poison:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: addi a1, a0, -1
; RV64XTHEADBB-NEXT: not a0, a0
@@ -708,8 +708,8 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
ret i16 %tmp
}
-define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
-; RV32I-LABEL: test_cttz_i32_zero_undef:
+define i32 @test_cttz_i32_zero_poison(i32 %a) nounwind {
+; RV32I-LABEL: test_cttz_i32_zero_poison:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
@@ -727,7 +727,7 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV64I-LABEL: test_cttz_i32_zero_undef:
+; RV64I-LABEL: test_cttz_i32_zero_poison:
; RV64I: # %bb.0:
; RV64I-NEXT: neg a1, a0
; RV64I-NEXT: and a0, a0, a1
@@ -758,7 +758,7 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
; RV64I-NEXT: lbu a0, 0(a0)
; RV64I-NEXT: ret
;
-; RV32M-LABEL: test_cttz_i32_zero_undef:
+; RV32M-LABEL: test_cttz_i32_zero_poison:
; RV32M: # %bb.0:
; RV32M-NEXT: neg a1, a0
; RV32M-NEXT: and a0, a0, a1
@@ -772,7 +772,7 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
; RV32M-NEXT: lbu a0, 0(a0)
; RV32M-NEXT: ret
;
-; RV64M-LABEL: test_cttz_i32_zero_undef:
+; RV64M-LABEL: test_cttz_i32_zero_poison:
; RV64M: # %bb.0:
; RV64M-NEXT: neg a1, a0
; RV64M-NEXT: and a0, a0, a1
@@ -786,17 +786,17 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
; RV64M-NEXT: lbu a0, 0(a0)
; RV64M-NEXT: ret
;
-; RV32ZBB-LABEL: test_cttz_i32_zero_undef:
+; RV32ZBB-LABEL: test_cttz_i32_zero_poison:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: ctz a0, a0
; RV32ZBB-NEXT: ret
;
-; RV64ZBB-LABEL: test_cttz_i32_zero_undef:
+; RV64ZBB-LABEL: test_cttz_i32_zero_poison:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: ctzw a0, a0
; RV64ZBB-NEXT: ret
;
-; RV32XTHEADBB-LABEL: test_cttz_i32_zero_undef:
+; RV32XTHEADBB-LABEL: test_cttz_i32_zero_poison:
; RV32XTHEADBB: # %bb.0:
; RV32XTHEADBB-NEXT: addi a1, a0, -1
; RV32XTHEADBB-NEXT: not a0, a0
@@ -806,7 +806,7 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
; RV32XTHEADBB-NEXT: sub a0, a1, a0
; RV32XTHEADBB-NEXT: ret
;
-; RV64XTHEADBB-LABEL: test_cttz_i32_zero_undef:
+; RV64XTHEADBB-LABEL: test_cttz_i32_zero_poison:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: addi a1, a0, -1
; RV64XTHEADBB-NEXT: not a0, a0
@@ -819,8 +819,8 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
ret i32 %tmp
}
-define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
-; RV32I-LABEL: test_cttz_i64_zero_undef:
+define i64 @test_cttz_i64_zero_poison(i64 %a) nounwind {
+; RV32I-LABEL: test_cttz_i64_zero_poison:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
@@ -866,7 +866,7 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
-; RV64I-LABEL: test_cttz_i64_zero_undef:
+; RV64I-LABEL: test_cttz_i64_zero_poison:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
@@ -884,7 +884,7 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV32M-LABEL: test_cttz_i64_zero_undef:
+; RV32M-LABEL: test_cttz_i64_zero_poison:
; RV32M: # %bb.0:
; RV32M-NEXT: lui a3, 30667
; RV32M-NEXT: addi a3, a3, 1329
@@ -911,7 +911,7 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32M-NEXT: li a1, 0
; RV32M-NEXT: ret
;
-; RV64M-LABEL: test_cttz_i64_zero_undef:
+; RV64M-LABEL: test_cttz_i64_zero_poison:
; RV64M: # %bb.0:
; RV64M-NEXT: lui a1, %hi(.LCPI7_0)
; RV64M-NEXT: ld a1, %lo(.LCPI7_0)(a1)
@@ -925,7 +925,7 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV64M-NEXT: lbu a0, 0(a0)
; RV64M-NEXT: ret
;
-; RV32ZBB-LABEL: test_cttz_i64_zero_undef:
+; RV32ZBB-LABEL: test_cttz_i64_zero_poison:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: bnez a0, .LBB7_2
; RV32ZBB-NEXT: # %bb.1:
@@ -938,12 +938,12 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32ZBB-NEXT: li a1, 0
; RV32ZBB-NEXT: ret
;
-; RV64ZBB-LABEL: test_cttz_i64_zero_undef:
+; RV64ZBB-LABEL: test_cttz_i64_zero_poison:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: ctz a0, a0
; RV64ZBB-NEXT: ret
;
-; RV32XTHEADBB-LABEL: test_cttz_i64_zero_undef:
+; RV32XTHEADBB-LABEL: test_cttz_i64_zero_poison:
; RV32XTHEADBB: # %bb.0:
; RV32XTHEADBB-NEXT: bnez a0, .LBB7_2
; RV32XTHEADBB-NEXT: # %bb.1:
@@ -964,7 +964,7 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32XTHEADBB-NEXT: li a1, 0
; RV32XTHEADBB-NEXT: ret
;
-; RV64XTHEADBB-LABEL: test_cttz_i64_zero_undef:
+; RV64XTHEADBB-LABEL: test_cttz_i64_zero_poison:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: addi a1, a0, -1
; RV64XTHEADBB-NEXT: not a0, a0
@@ -1658,8 +1658,8 @@ define i64 @test_ctlz_i64(i64 %a) nounwind {
ret i64 %tmp
}
-define i8 @test_ctlz_i8_zero_undef(i8 %a) nounwind {
-; RV32_NOZBB-LABEL: test_ctlz_i8_zero_undef:
+define i8 @test_ctlz_i8_zero_poison(i8 %a) nounwind {
+; RV32_NOZBB-LABEL: test_ctlz_i8_zero_poison:
; RV32_NOZBB: # %bb.0:
; RV32_NOZBB-NEXT: slli a1, a0, 24
; RV32_NOZBB-NEXT: srli a1, a1, 25
@@ -1683,7 +1683,7 @@ define i8 @test_ctlz_i8_zero_undef(i8 %a) nounwind {
; RV32_NOZBB-NEXT: andi a0, a0, 15
; RV32_NOZBB-NEXT: ret
;
-; RV64NOZBB-LABEL: test_ctlz_i8_zero_undef:
+; RV64NOZBB-LABEL: test_ctlz_i8_zero_poison:
; RV64NOZBB: # %bb.0:
; RV64NOZBB-NEXT: slli a1, a0, 56
; RV64NOZBB-NEXT: srli a1, a1, 57
@@ -1707,25 +1707,25 @@ define i8 @test_ctlz_i8_zero_undef(i8 %a) nounwind {
; RV64NOZBB-NEXT: andi a0, a0, 15
; RV64NOZBB-NEXT: ret
;
-; RV32ZBB-LABEL: test_ctlz_i8_zero_undef:
+; RV32ZBB-LABEL: test_ctlz_i8_zero_poison:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: slli a0, a0, 24
; RV32ZBB-NEXT: clz a0, a0
; RV32ZBB-NEXT: ret
;
-; RV64ZBB-LABEL: test_ctlz_i8_zero_undef:
+; RV64ZBB-LABEL: test_ctlz_i8_zero_poison:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: slli a0, a0, 56
; RV64ZBB-NEXT: clz a0, a0
; RV64ZBB-NEXT: ret
;
-; RV32XTHEADBB-LABEL: test_ctlz_i8_zero_undef:
+; RV32XTHEADBB-LABEL: test_ctlz_i8_zero_poison:
; RV32XTHEADBB: # %bb.0:
; RV32XTHEADBB-NEXT: slli a0, a0, 24
; RV32XTHEADBB-NEXT: th.ff1 a0, a0
; RV32XTHEADBB-NEXT: ret
;
-; RV64XTHEADBB-LABEL: test_ctlz_i8_zero_undef:
+; RV64XTHEADBB-LABEL: test_ctlz_i8_zero_poison:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: slli a0, a0, 56
; RV64XTHEADBB-NEXT: th.ff1 a0, a0
@@ -1734,8 +1734,8 @@ define i8 @test_ctlz_i8_zero_undef(i8 %a) nounwind {
ret i8 %tmp
}
-define i16 @test_ctlz_i16_zero_undef(i16 %a) nounwind {
-; RV32_NOZBB-LABEL: test_ctlz_i16_zero_undef:
+define i16 @test_ctlz_i16_zero_poison(i16 %a) nounwind {
+; RV32_NOZBB-LABEL: test_ctlz_i16_zero_poison:
; RV32_NOZBB: # %bb.0:
; RV32_NOZBB-NEXT: slli a1, a0, 16
; RV32_NOZBB-NEXT: lui a2, 5
@@ -1769,7 +1769,7 @@ define i16 @test_ctlz_i16_zero_undef(i16 %a) nounwind {
; RV32_NOZBB-NEXT: add a0, a1, a0
; RV32_NOZBB-NEXT: ret
;
-; RV64NOZBB-LABEL: test_ctlz_i16_zero_undef:
+; RV64NOZBB-LABEL: test_ctlz_i16_zero_poison:
; RV64NOZBB: # %bb.0:
; RV64NOZBB-NEXT: slli a1, a0, 48
; RV64NOZBB-NEXT: lui a2, 5
@@ -1803,25 +1803,25 @@ define i16 @test_ctlz_i16_zero_undef(i16 %a) nounwind {
; RV64NOZBB-NEXT: add a0, a1, a0
; RV64NOZBB-NEXT: ret
;
-; RV32ZBB-LABEL: test_ctlz_i16_zero_undef:
+; RV32ZBB-LABEL: test_ctlz_i16_zero_poison:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: slli a0, a0, 16
; RV32ZBB-NEXT: clz a0, a0
; RV32ZBB-NEXT: ret
;
-; RV64ZBB-LABEL: test_ctlz_i16_zero_undef:
+; RV64ZBB-LABEL: test_ctlz_i16_zero_poison:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: slli a0, a0, 48
; RV64ZBB-NEXT: clz a0, a0
; RV64ZBB-NEXT: ret
;
-; RV32XTHEADBB-LABEL: test_ctlz_i16_zero_undef:
+; RV32XTHEADBB-LABEL: test_ctlz_i16_zero_poison:
; RV32XTHEADBB: # %bb.0:
; RV32XTHEADBB-NEXT: slli a0, a0, 16
; RV32XTHEADBB-NEXT: th.ff1 a0, a0
; RV32XTHEADBB-NEXT: ret
;
-; RV64XTHEADBB-LABEL: test_ctlz_i16_zero_undef:
+; RV64XTHEADBB-LABEL: test_ctlz_i16_zero_poison:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: slli a0, a0, 48
; RV64XTHEADBB-NEXT: th.ff1 a0, a0
@@ -1830,8 +1830,8 @@ define i16 @test_ctlz_i16_zero_undef(i16 %a) nounwind {
ret i16 %tmp
}
-define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind {
-; RV32I-LABEL: test_ctlz_i32_zero_undef:
+define i32 @test_ctlz_i32_zero_poison(i32 %a) nounwind {
+; RV32I-LABEL: test_ctlz_i32_zero_poison:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525
@@ -1867,7 +1867,7 @@ define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind {
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: ret
;
-; RV64I-LABEL: test_ctlz_i32_zero_undef:
+; RV64I-LABEL: test_ctlz_i32_zero_poison:
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: lui a2, 349525
@@ -1903,7 +1903,7 @@ define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind {
; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ret
;
-; RV32M-LABEL: test_ctlz_i32_zero_undef:
+; RV32M-LABEL: test_ctlz_i32_zero_poison:
; RV32M: # %bb.0:
; RV32M-NEXT: srli a1, a0, 1
; RV32M-NEXT: lui a2, 349525
@@ -1938,7 +1938,7 @@ define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind {
; RV32M-NEXT: srli a0, a0, 24
; RV32M-NEXT: ret
;
-; RV64M-LABEL: test_ctlz_i32_zero_undef:
+; RV64M-LABEL: test_ctlz_i32_zero_poison:
; RV64M: # %bb.0:
; RV64M-NEXT: srliw a1, a0, 1
; RV64M-NEXT: lui a2, 349525
@@ -1973,22 +1973,22 @@ define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind {
; RV64M-NEXT: srliw a0, a0, 24
; RV64M-NEXT: ret
;
-; RV32ZBB-LABEL: test_ctlz_i32_zero_undef:
+; RV32ZBB-LABEL: test_ctlz_i32_zero_poison:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: clz a0, a0
; RV32ZBB-NEXT: ret
;
-; RV64ZBB-LABEL: test_ctlz_i32_zero_undef:
+; RV64ZBB-LABEL: test_ctlz_i32_zero_poison:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: clzw a0, a0
; RV64ZBB-NEXT: ret
;
-; RV32XTHEADBB-LABEL: test_ctlz_i32_zero_undef:
+; RV32XTHEADBB-LABEL: test_ctlz_i32_zero_poison:
; RV32XTHEADBB: # %bb.0:
; RV32XTHEADBB-NEXT: th.ff1 a0, a0
; RV32XTHEADBB-NEXT: ret
;
-; RV64XTHEADBB-LABEL: test_ctlz_i32_zero_undef:
+; RV64XTHEADBB-LABEL: test_ctlz_i32_zero_poison:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: slli a0, a0, 32
; RV64XTHEADBB-NEXT: th.ff1 a0, a0
@@ -1997,8 +1997,8 @@ define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind {
ret i32 %tmp
}
-define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
-; RV32I-LABEL: test_ctlz_i64_zero_undef:
+define i64 @test_ctlz_i64_zero_poison(i64 %a) nounwind {
+; RV32I-LABEL: test_ctlz_i64_zero_poison:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: lui a3, 209715
@@ -2067,7 +2067,7 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: ret
;
-; RV64I-LABEL: test_ctlz_i64_zero_undef:
+; RV64I-LABEL: test_ctlz_i64_zero_poison:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: lui a2, 349525
@@ -2113,7 +2113,7 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: ret
;
-; RV32M-LABEL: test_ctlz_i64_zero_undef:
+; RV32M-LABEL: test_ctlz_i64_zero_poison:
; RV32M: # %bb.0:
; RV32M-NEXT: lui a2, 349525
; RV32M-NEXT: lui a3, 209715
@@ -2178,7 +2178,7 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
; RV32M-NEXT: li a1, 0
; RV32M-NEXT: ret
;
-; RV64M-LABEL: test_ctlz_i64_zero_undef:
+; RV64M-LABEL: test_ctlz_i64_zero_poison:
; RV64M: # %bb.0:
; RV64M-NEXT: srli a1, a0, 1
; RV64M-NEXT: lui a2, 349525
@@ -2223,7 +2223,7 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
; RV64M-NEXT: srli a0, a0, 56
; RV64M-NEXT: ret
;
-; RV32ZBB-LABEL: test_ctlz_i64_zero_undef:
+; RV32ZBB-LABEL: test_ctlz_i64_zero_poison:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: bnez a1, .LBB15_2
; RV32ZBB-NEXT: # %bb.1:
@@ -2236,12 +2236,12 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
; RV32ZBB-NEXT: li a1, 0
; RV32ZBB-NEXT: ret
;
-; RV64ZBB-LABEL: test_ctlz_i64_zero_undef:
+; RV64ZBB-LABEL: test_ctlz_i64_zero_poison:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: clz a0, a0
; RV64ZBB-NEXT: ret
;
-; RV32XTHEADBB-LABEL: test_ctlz_i64_zero_undef:
+; RV32XTHEADBB-LABEL: test_ctlz_i64_zero_poison:
; RV32XTHEADBB: # %bb.0:
; RV32XTHEADBB-NEXT: bnez a1, .LBB15_2
; RV32XTHEADBB-NEXT: # %bb.1:
@@ -2254,7 +2254,7 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
; RV32XTHEADBB-NEXT: li a1, 0
; RV32XTHEADBB-NEXT: ret
;
-; RV64XTHEADBB-LABEL: test_ctlz_i64_zero_undef:
+; RV64XTHEADBB-LABEL: test_ctlz_i64_zero_poison:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: th.ff1 a0, a0
; RV64XTHEADBB-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
index c62fb0ae63555..4331d7ca79123 100644
--- a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
@@ -444,8 +444,8 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind {
ret i32 %1
}
-define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
-; RV64I-LABEL: cttz_zero_undef_i32:
+define signext i32 @cttz_zero_poison_i32(i32 signext %a) nounwind {
+; RV64I-LABEL: cttz_zero_poison_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: neg a1, a0
; RV64I-NEXT: and a0, a0, a1
@@ -476,7 +476,7 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
; RV64I-NEXT: lbu a0, 0(a0)
; RV64I-NEXT: ret
;
-; RV64XTHEADBB-NOB-LABEL: cttz_zero_undef_i32:
+; RV64XTHEADBB-NOB-LABEL: cttz_zero_poison_i32:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: addi a1, a0, -1
; RV64XTHEADBB-NOB-NEXT: not a0, a0
@@ -486,7 +486,7 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
; RV64XTHEADBB-NOB-NEXT: sub a0, a1, a0
; RV64XTHEADBB-NOB-NEXT: ret
;
-; RV64XTHEADBB-B-LABEL: cttz_zero_undef_i32:
+; RV64XTHEADBB-B-LABEL: cttz_zero_poison_i32:
; RV64XTHEADBB-B: # %bb.0:
; RV64XTHEADBB-B-NEXT: ctzw a0, a0
; RV64XTHEADBB-B-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64zbb.ll
index e840605710f21..759bf84262461 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb.ll
@@ -381,8 +381,8 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind {
ret i32 %1
}
-define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
-; RV64I-LABEL: cttz_zero_undef_i32:
+define signext i32 @cttz_zero_poison_i32(i32 signext %a) nounwind {
+; RV64I-LABEL: cttz_zero_poison_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: neg a1, a0
; RV64I-NEXT: and a0, a0, a1
@@ -413,7 +413,7 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
; RV64I-NEXT: lbu a0, 0(a0)
; RV64I-NEXT: ret
;
-; RV64ZBB-LABEL: cttz_zero_undef_i32:
+; RV64ZBB-LABEL: cttz_zero_poison_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: ctzw a0, a0
; RV64ZBB-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
index 1f45e45f23164..b2e62251f630f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
@@ -1666,8 +1666,8 @@ define <vscale x 8 x i64> @ctlz_nxv8i64(<vscale x 8 x i64> %va) {
ret <vscale x 8 x i64> %a
}
-define <vscale x 1 x i8> @ctlz_zero_undef_nxv1i8(<vscale x 1 x i8> %va) {
-; CHECK-ZVE64X-LABEL: ctlz_zero_undef_nxv1i8:
+define <vscale x 1 x i8> @ctlz_zero_poison_nxv1i8(<vscale x 1 x i8> %va) {
+; CHECK-ZVE64X-LABEL: ctlz_zero_poison_nxv1i8:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
@@ -1691,7 +1691,7 @@ define <vscale x 1 x i8> @ctlz_zero_undef_nxv1i8(<vscale x 1 x i8> %va) {
; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: ctlz_zero_undef_nxv1i8:
+; CHECK-F-LABEL: ctlz_zero_poison_nxv1i8:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-F-NEXT: vzext.vf2 v9, v8
@@ -1703,7 +1703,7 @@ define <vscale x 1 x i8> @ctlz_zero_undef_nxv1i8(<vscale x 1 x i8> %va) {
; CHECK-F-NEXT: vrsub.vx v8, v8, a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: ctlz_zero_undef_nxv1i8:
+; CHECK-D-LABEL: ctlz_zero_poison_nxv1i8:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-D-NEXT: vzext.vf2 v9, v8
@@ -1715,7 +1715,7 @@ define <vscale x 1 x i8> @ctlz_zero_undef_nxv1i8(<vscale x 1 x i8> %va) {
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv1i8:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv1i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1724,8 +1724,8 @@ define <vscale x 1 x i8> @ctlz_zero_undef_nxv1i8(<vscale x 1 x i8> %va) {
ret <vscale x 1 x i8> %a
}
-define <vscale x 2 x i8> @ctlz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) {
-; CHECK-ZVE64X-LABEL: ctlz_zero_undef_nxv2i8:
+define <vscale x 2 x i8> @ctlz_zero_poison_nxv2i8(<vscale x 2 x i8> %va) {
+; CHECK-ZVE64X-LABEL: ctlz_zero_poison_nxv2i8:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
@@ -1749,7 +1749,7 @@ define <vscale x 2 x i8> @ctlz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) {
; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: ctlz_zero_undef_nxv2i8:
+; CHECK-F-LABEL: ctlz_zero_poison_nxv2i8:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-F-NEXT: vzext.vf2 v9, v8
@@ -1761,7 +1761,7 @@ define <vscale x 2 x i8> @ctlz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) {
; CHECK-F-NEXT: vrsub.vx v8, v8, a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: ctlz_zero_undef_nxv2i8:
+; CHECK-D-LABEL: ctlz_zero_poison_nxv2i8:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-D-NEXT: vzext.vf2 v9, v8
@@ -1773,7 +1773,7 @@ define <vscale x 2 x i8> @ctlz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) {
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv2i8:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv2i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1782,8 +1782,8 @@ define <vscale x 2 x i8> @ctlz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) {
ret <vscale x 2 x i8> %a
}
-define <vscale x 4 x i8> @ctlz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) {
-; CHECK-ZVE64X-LABEL: ctlz_zero_undef_nxv4i8:
+define <vscale x 4 x i8> @ctlz_zero_poison_nxv4i8(<vscale x 4 x i8> %va) {
+; CHECK-ZVE64X-LABEL: ctlz_zero_poison_nxv4i8:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
@@ -1807,7 +1807,7 @@ define <vscale x 4 x i8> @ctlz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) {
; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: ctlz_zero_undef_nxv4i8:
+; CHECK-F-LABEL: ctlz_zero_poison_nxv4i8:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-F-NEXT: vzext.vf2 v10, v8
@@ -1819,7 +1819,7 @@ define <vscale x 4 x i8> @ctlz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) {
; CHECK-F-NEXT: vrsub.vx v8, v8, a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: ctlz_zero_undef_nxv4i8:
+; CHECK-D-LABEL: ctlz_zero_poison_nxv4i8:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-D-NEXT: vzext.vf2 v10, v8
@@ -1831,7 +1831,7 @@ define <vscale x 4 x i8> @ctlz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) {
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv4i8:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv4i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1840,8 +1840,8 @@ define <vscale x 4 x i8> @ctlz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) {
ret <vscale x 4 x i8> %a
}
-define <vscale x 8 x i8> @ctlz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) {
-; CHECK-ZVE64X-LABEL: ctlz_zero_undef_nxv8i8:
+define <vscale x 8 x i8> @ctlz_zero_poison_nxv8i8(<vscale x 8 x i8> %va) {
+; CHECK-ZVE64X-LABEL: ctlz_zero_poison_nxv8i8:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
@@ -1865,7 +1865,7 @@ define <vscale x 8 x i8> @ctlz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) {
; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: ctlz_zero_undef_nxv8i8:
+; CHECK-F-LABEL: ctlz_zero_poison_nxv8i8:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-F-NEXT: vzext.vf2 v12, v8
@@ -1877,7 +1877,7 @@ define <vscale x 8 x i8> @ctlz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) {
; CHECK-F-NEXT: vrsub.vx v8, v8, a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: ctlz_zero_undef_nxv8i8:
+; CHECK-D-LABEL: ctlz_zero_poison_nxv8i8:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-D-NEXT: vzext.vf2 v12, v8
@@ -1889,7 +1889,7 @@ define <vscale x 8 x i8> @ctlz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) {
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv8i8:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv8i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1898,8 +1898,8 @@ define <vscale x 8 x i8> @ctlz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) {
ret <vscale x 8 x i8> %a
}
-define <vscale x 16 x i8> @ctlz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
-; CHECK-ZVE64X-LABEL: ctlz_zero_undef_nxv16i8:
+define <vscale x 16 x i8> @ctlz_zero_poison_nxv16i8(<vscale x 16 x i8> %va) {
+; CHECK-ZVE64X-LABEL: ctlz_zero_poison_nxv16i8:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
@@ -1923,7 +1923,7 @@ define <vscale x 16 x i8> @ctlz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: ctlz_zero_undef_nxv16i8:
+; CHECK-F-LABEL: ctlz_zero_poison_nxv16i8:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-F-NEXT: vzext.vf2 v16, v8
@@ -1935,7 +1935,7 @@ define <vscale x 16 x i8> @ctlz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
; CHECK-F-NEXT: vrsub.vx v8, v8, a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: ctlz_zero_undef_nxv16i8:
+; CHECK-D-LABEL: ctlz_zero_poison_nxv16i8:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-D-NEXT: vzext.vf2 v16, v8
@@ -1947,7 +1947,7 @@ define <vscale x 16 x i8> @ctlz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv16i8:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv16i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1956,8 +1956,8 @@ define <vscale x 16 x i8> @ctlz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
ret <vscale x 16 x i8> %a
}
-define <vscale x 32 x i8> @ctlz_zero_undef_nxv32i8(<vscale x 32 x i8> %va) {
-; CHECK-LABEL: ctlz_zero_undef_nxv32i8:
+define <vscale x 32 x i8> @ctlz_zero_poison_nxv32i8(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: ctlz_zero_poison_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v8, 1
@@ -1981,7 +1981,7 @@ define <vscale x 32 x i8> @ctlz_zero_undef_nxv32i8(<vscale x 32 x i8> %va) {
; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv32i8:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv32i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1990,8 +1990,8 @@ define <vscale x 32 x i8> @ctlz_zero_undef_nxv32i8(<vscale x 32 x i8> %va) {
ret <vscale x 32 x i8> %a
}
-define <vscale x 64 x i8> @ctlz_zero_undef_nxv64i8(<vscale x 64 x i8> %va) {
-; CHECK-LABEL: ctlz_zero_undef_nxv64i8:
+define <vscale x 64 x i8> @ctlz_zero_poison_nxv64i8(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: ctlz_zero_poison_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vsrl.vi v16, v8, 1
@@ -2015,7 +2015,7 @@ define <vscale x 64 x i8> @ctlz_zero_undef_nxv64i8(<vscale x 64 x i8> %va) {
; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv64i8:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv64i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2024,8 +2024,8 @@ define <vscale x 64 x i8> @ctlz_zero_undef_nxv64i8(<vscale x 64 x i8> %va) {
ret <vscale x 64 x i8> %a
}
-define <vscale x 1 x i16> @ctlz_zero_undef_nxv1i16(<vscale x 1 x i16> %va) {
-; CHECK-ZVE64X-LABEL: ctlz_zero_undef_nxv1i16:
+define <vscale x 1 x i16> @ctlz_zero_poison_nxv1i16(<vscale x 1 x i16> %va) {
+; CHECK-ZVE64X-LABEL: ctlz_zero_poison_nxv1i16:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
@@ -2058,7 +2058,7 @@ define <vscale x 1 x i16> @ctlz_zero_undef_nxv1i16(<vscale x 1 x i16> %va) {
; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: ctlz_zero_undef_nxv1i16:
+; CHECK-F-LABEL: ctlz_zero_poison_nxv1i16:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-F-NEXT: vfwcvt.f.xu.v v9, v8
@@ -2067,7 +2067,7 @@ define <vscale x 1 x i16> @ctlz_zero_undef_nxv1i16(<vscale x 1 x i16> %va) {
; CHECK-F-NEXT: vrsub.vx v8, v8, a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: ctlz_zero_undef_nxv1i16:
+; CHECK-D-LABEL: ctlz_zero_poison_nxv1i16:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v8
@@ -2076,7 +2076,7 @@ define <vscale x 1 x i16> @ctlz_zero_undef_nxv1i16(<vscale x 1 x i16> %va) {
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv1i16:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv1i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2085,8 +2085,8 @@ define <vscale x 1 x i16> @ctlz_zero_undef_nxv1i16(<vscale x 1 x i16> %va) {
ret <vscale x 1 x i16> %a
}
-define <vscale x 2 x i16> @ctlz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {
-; CHECK-ZVE64X-LABEL: ctlz_zero_undef_nxv2i16:
+define <vscale x 2 x i16> @ctlz_zero_poison_nxv2i16(<vscale x 2 x i16> %va) {
+; CHECK-ZVE64X-LABEL: ctlz_zero_poison_nxv2i16:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
@@ -2119,7 +2119,7 @@ define <vscale x 2 x i16> @ctlz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {
; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: ctlz_zero_undef_nxv2i16:
+; CHECK-F-LABEL: ctlz_zero_poison_nxv2i16:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-F-NEXT: vfwcvt.f.xu.v v9, v8
@@ -2128,7 +2128,7 @@ define <vscale x 2 x i16> @ctlz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {
; CHECK-F-NEXT: vrsub.vx v8, v8, a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: ctlz_zero_undef_nxv2i16:
+; CHECK-D-LABEL: ctlz_zero_poison_nxv2i16:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v8
@@ -2137,7 +2137,7 @@ define <vscale x 2 x i16> @ctlz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv2i16:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv2i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2146,8 +2146,8 @@ define <vscale x 2 x i16> @ctlz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {
ret <vscale x 2 x i16> %a
}
-define <vscale x 4 x i16> @ctlz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {
-; CHECK-ZVE64X-LABEL: ctlz_zero_undef_nxv4i16:
+define <vscale x 4 x i16> @ctlz_zero_poison_nxv4i16(<vscale x 4 x i16> %va) {
+; CHECK-ZVE64X-LABEL: ctlz_zero_poison_nxv4i16:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
@@ -2180,7 +2180,7 @@ define <vscale x 4 x i16> @ctlz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {
; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: ctlz_zero_undef_nxv4i16:
+; CHECK-F-LABEL: ctlz_zero_poison_nxv4i16:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-F-NEXT: vfwcvt.f.xu.v v10, v8
@@ -2189,7 +2189,7 @@ define <vscale x 4 x i16> @ctlz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {
; CHECK-F-NEXT: vrsub.vx v8, v8, a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: ctlz_zero_undef_nxv4i16:
+; CHECK-D-LABEL: ctlz_zero_poison_nxv4i16:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v8
@@ -2198,7 +2198,7 @@ define <vscale x 4 x i16> @ctlz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv4i16:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv4i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2207,8 +2207,8 @@ define <vscale x 4 x i16> @ctlz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {
ret <vscale x 4 x i16> %a
}
-define <vscale x 8 x i16> @ctlz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
-; CHECK-ZVE64X-LABEL: ctlz_zero_undef_nxv8i16:
+define <vscale x 8 x i16> @ctlz_zero_poison_nxv8i16(<vscale x 8 x i16> %va) {
+; CHECK-ZVE64X-LABEL: ctlz_zero_poison_nxv8i16:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
@@ -2241,7 +2241,7 @@ define <vscale x 8 x i16> @ctlz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: ctlz_zero_undef_nxv8i16:
+; CHECK-F-LABEL: ctlz_zero_poison_nxv8i16:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-F-NEXT: vfwcvt.f.xu.v v12, v8
@@ -2250,7 +2250,7 @@ define <vscale x 8 x i16> @ctlz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
; CHECK-F-NEXT: vrsub.vx v8, v8, a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: ctlz_zero_undef_nxv8i16:
+; CHECK-D-LABEL: ctlz_zero_poison_nxv8i16:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v8
@@ -2259,7 +2259,7 @@ define <vscale x 8 x i16> @ctlz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv8i16:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv8i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2268,8 +2268,8 @@ define <vscale x 8 x i16> @ctlz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
ret <vscale x 8 x i16> %a
}
-define <vscale x 16 x i16> @ctlz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
-; CHECK-ZVE64X-LABEL: ctlz_zero_undef_nxv16i16:
+define <vscale x 16 x i16> @ctlz_zero_poison_nxv16i16(<vscale x 16 x i16> %va) {
+; CHECK-ZVE64X-LABEL: ctlz_zero_poison_nxv16i16:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
@@ -2302,7 +2302,7 @@ define <vscale x 16 x i16> @ctlz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: ctlz_zero_undef_nxv16i16:
+; CHECK-F-LABEL: ctlz_zero_poison_nxv16i16:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-F-NEXT: vfwcvt.f.xu.v v16, v8
@@ -2311,7 +2311,7 @@ define <vscale x 16 x i16> @ctlz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
; CHECK-F-NEXT: vrsub.vx v8, v8, a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: ctlz_zero_undef_nxv16i16:
+; CHECK-D-LABEL: ctlz_zero_poison_nxv16i16:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v8
@@ -2320,7 +2320,7 @@ define <vscale x 16 x i16> @ctlz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv16i16:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv16i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2329,8 +2329,8 @@ define <vscale x 16 x i16> @ctlz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
ret <vscale x 16 x i16> %a
}
-define <vscale x 32 x i16> @ctlz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) {
-; CHECK-LABEL: ctlz_zero_undef_nxv32i16:
+define <vscale x 32 x i16> @ctlz_zero_poison_nxv32i16(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: ctlz_zero_poison_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v16, v8, 1
@@ -2363,7 +2363,7 @@ define <vscale x 32 x i16> @ctlz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) {
; CHECK-NEXT: vsrl.vi v8, v8, 8
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv32i16:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv32i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2372,8 +2372,8 @@ define <vscale x 32 x i16> @ctlz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) {
ret <vscale x 32 x i16> %a
}
-define <vscale x 1 x i32> @ctlz_zero_undef_nxv1i32(<vscale x 1 x i32> %va) {
-; CHECK-ZVE64X-LABEL: ctlz_zero_undef_nxv1i32:
+define <vscale x 1 x i32> @ctlz_zero_poison_nxv1i32(<vscale x 1 x i32> %va) {
+; CHECK-ZVE64X-LABEL: ctlz_zero_poison_nxv1i32:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
@@ -2409,7 +2409,7 @@ define <vscale x 1 x i32> @ctlz_zero_undef_nxv1i32(<vscale x 1 x i32> %va) {
; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: ctlz_zero_undef_nxv1i32:
+; CHECK-F-LABEL: ctlz_zero_poison_nxv1i32:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: fsrmi a0, 1
; CHECK-F-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
@@ -2420,7 +2420,7 @@ define <vscale x 1 x i32> @ctlz_zero_undef_nxv1i32(<vscale x 1 x i32> %va) {
; CHECK-F-NEXT: fsrm a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: ctlz_zero_undef_nxv1i32:
+; CHECK-D-LABEL: ctlz_zero_poison_nxv1i32:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v8
@@ -2430,7 +2430,7 @@ define <vscale x 1 x i32> @ctlz_zero_undef_nxv1i32(<vscale x 1 x i32> %va) {
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv1i32:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv1i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2439,8 +2439,8 @@ define <vscale x 1 x i32> @ctlz_zero_undef_nxv1i32(<vscale x 1 x i32> %va) {
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @ctlz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
-; CHECK-ZVE64X-LABEL: ctlz_zero_undef_nxv2i32:
+define <vscale x 2 x i32> @ctlz_zero_poison_nxv2i32(<vscale x 2 x i32> %va) {
+; CHECK-ZVE64X-LABEL: ctlz_zero_poison_nxv2i32:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
@@ -2476,7 +2476,7 @@ define <vscale x 2 x i32> @ctlz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: ctlz_zero_undef_nxv2i32:
+; CHECK-F-LABEL: ctlz_zero_poison_nxv2i32:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: fsrmi a0, 1
; CHECK-F-NEXT: vsetvli a1, zero, e32, m1, ta, ma
@@ -2487,7 +2487,7 @@ define <vscale x 2 x i32> @ctlz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
; CHECK-F-NEXT: fsrm a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: ctlz_zero_undef_nxv2i32:
+; CHECK-D-LABEL: ctlz_zero_poison_nxv2i32:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v8
@@ -2497,7 +2497,7 @@ define <vscale x 2 x i32> @ctlz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv2i32:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv2i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2506,8 +2506,8 @@ define <vscale x 2 x i32> @ctlz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @ctlz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
-; CHECK-ZVE64X-LABEL: ctlz_zero_undef_nxv4i32:
+define <vscale x 4 x i32> @ctlz_zero_poison_nxv4i32(<vscale x 4 x i32> %va) {
+; CHECK-ZVE64X-LABEL: ctlz_zero_poison_nxv4i32:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
@@ -2543,7 +2543,7 @@ define <vscale x 4 x i32> @ctlz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: ctlz_zero_undef_nxv4i32:
+; CHECK-F-LABEL: ctlz_zero_poison_nxv4i32:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: fsrmi a0, 1
; CHECK-F-NEXT: vsetvli a1, zero, e32, m2, ta, ma
@@ -2554,7 +2554,7 @@ define <vscale x 4 x i32> @ctlz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
; CHECK-F-NEXT: fsrm a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: ctlz_zero_undef_nxv4i32:
+; CHECK-D-LABEL: ctlz_zero_poison_nxv4i32:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v8
@@ -2564,7 +2564,7 @@ define <vscale x 4 x i32> @ctlz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv4i32:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv4i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2573,8 +2573,8 @@ define <vscale x 4 x i32> @ctlz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @ctlz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
-; CHECK-ZVE64X-LABEL: ctlz_zero_undef_nxv8i32:
+define <vscale x 8 x i32> @ctlz_zero_poison_nxv8i32(<vscale x 8 x i32> %va) {
+; CHECK-ZVE64X-LABEL: ctlz_zero_poison_nxv8i32:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
@@ -2610,7 +2610,7 @@ define <vscale x 8 x i32> @ctlz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: ctlz_zero_undef_nxv8i32:
+; CHECK-F-LABEL: ctlz_zero_poison_nxv8i32:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: fsrmi a0, 1
; CHECK-F-NEXT: vsetvli a1, zero, e32, m4, ta, ma
@@ -2621,7 +2621,7 @@ define <vscale x 8 x i32> @ctlz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
; CHECK-F-NEXT: fsrm a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: ctlz_zero_undef_nxv8i32:
+; CHECK-D-LABEL: ctlz_zero_poison_nxv8i32:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v8
@@ -2631,7 +2631,7 @@ define <vscale x 8 x i32> @ctlz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv8i32:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv8i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2640,8 +2640,8 @@ define <vscale x 8 x i32> @ctlz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @ctlz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
-; CHECK-ZVE64X-LABEL: ctlz_zero_undef_nxv16i32:
+define <vscale x 16 x i32> @ctlz_zero_poison_nxv16i32(<vscale x 16 x i32> %va) {
+; CHECK-ZVE64X-LABEL: ctlz_zero_poison_nxv16i32:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-ZVE64X-NEXT: vsrl.vi v16, v8, 1
@@ -2677,7 +2677,7 @@ define <vscale x 16 x i32> @ctlz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: ctlz_zero_undef_nxv16i32:
+; CHECK-F-LABEL: ctlz_zero_poison_nxv16i32:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: fsrmi a0, 1
; CHECK-F-NEXT: vsetvli a1, zero, e32, m8, ta, ma
@@ -2688,7 +2688,7 @@ define <vscale x 16 x i32> @ctlz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
; CHECK-F-NEXT: fsrm a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: ctlz_zero_undef_nxv16i32:
+; CHECK-D-LABEL: ctlz_zero_poison_nxv16i32:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: fsrmi a0, 1
; CHECK-D-NEXT: vsetvli a1, zero, e32, m8, ta, ma
@@ -2699,7 +2699,7 @@ define <vscale x 16 x i32> @ctlz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
; CHECK-D-NEXT: fsrm a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv16i32:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv16i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2708,8 +2708,8 @@ define <vscale x 16 x i32> @ctlz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i64> @ctlz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
-; RV32I-LABEL: ctlz_zero_undef_nxv1i64:
+define <vscale x 1 x i64> @ctlz_zero_poison_nxv1i64(<vscale x 1 x i64> %va) {
+; RV32I-LABEL: ctlz_zero_poison_nxv1i64:
; RV32I: # %bb.0:
; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32I-NEXT: vsrl.vi v9, v8, 1
@@ -2761,7 +2761,7 @@ define <vscale x 1 x i64> @ctlz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
; RV32I-NEXT: vsrl.vx v8, v8, a0
; RV32I-NEXT: ret
;
-; RV64I-LABEL: ctlz_zero_undef_nxv1i64:
+; RV64I-LABEL: ctlz_zero_poison_nxv1i64:
; RV64I: # %bb.0:
; RV64I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV64I-NEXT: vsrl.vi v9, v8, 1
@@ -2809,7 +2809,7 @@ define <vscale x 1 x i64> @ctlz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret
;
-; CHECK-F-LABEL: ctlz_zero_undef_nxv1i64:
+; CHECK-F-LABEL: ctlz_zero_poison_nxv1i64:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: li a0, 190
; CHECK-F-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
@@ -2821,7 +2821,7 @@ define <vscale x 1 x i64> @ctlz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
; CHECK-F-NEXT: fsrm a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: ctlz_zero_undef_nxv1i64:
+; CHECK-D-LABEL: ctlz_zero_poison_nxv1i64:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: fsrmi a0, 1
; CHECK-D-NEXT: vsetvli a1, zero, e64, m1, ta, ma
@@ -2833,7 +2833,7 @@ define <vscale x 1 x i64> @ctlz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
; CHECK-D-NEXT: fsrm a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv1i64:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv1i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2842,8 +2842,8 @@ define <vscale x 1 x i64> @ctlz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
ret <vscale x 1 x i64> %a
}
-define <vscale x 2 x i64> @ctlz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
-; RV32I-LABEL: ctlz_zero_undef_nxv2i64:
+define <vscale x 2 x i64> @ctlz_zero_poison_nxv2i64(<vscale x 2 x i64> %va) {
+; RV32I-LABEL: ctlz_zero_poison_nxv2i64:
; RV32I: # %bb.0:
; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV32I-NEXT: vsrl.vi v10, v8, 1
@@ -2895,7 +2895,7 @@ define <vscale x 2 x i64> @ctlz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
; RV32I-NEXT: vsrl.vx v8, v8, a0
; RV32I-NEXT: ret
;
-; RV64I-LABEL: ctlz_zero_undef_nxv2i64:
+; RV64I-LABEL: ctlz_zero_poison_nxv2i64:
; RV64I: # %bb.0:
; RV64I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV64I-NEXT: vsrl.vi v10, v8, 1
@@ -2943,7 +2943,7 @@ define <vscale x 2 x i64> @ctlz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret
;
-; CHECK-F-LABEL: ctlz_zero_undef_nxv2i64:
+; CHECK-F-LABEL: ctlz_zero_poison_nxv2i64:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: li a0, 190
; CHECK-F-NEXT: vsetvli a1, zero, e32, m1, ta, ma
@@ -2955,7 +2955,7 @@ define <vscale x 2 x i64> @ctlz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
; CHECK-F-NEXT: fsrm a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: ctlz_zero_undef_nxv2i64:
+; CHECK-D-LABEL: ctlz_zero_poison_nxv2i64:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: fsrmi a0, 1
; CHECK-D-NEXT: vsetvli a1, zero, e64, m2, ta, ma
@@ -2967,7 +2967,7 @@ define <vscale x 2 x i64> @ctlz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
; CHECK-D-NEXT: fsrm a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv2i64:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv2i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2976,8 +2976,8 @@ define <vscale x 2 x i64> @ctlz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
ret <vscale x 2 x i64> %a
}
-define <vscale x 4 x i64> @ctlz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
-; RV32I-LABEL: ctlz_zero_undef_nxv4i64:
+define <vscale x 4 x i64> @ctlz_zero_poison_nxv4i64(<vscale x 4 x i64> %va) {
+; RV32I-LABEL: ctlz_zero_poison_nxv4i64:
; RV32I: # %bb.0:
; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV32I-NEXT: vsrl.vi v12, v8, 1
@@ -3029,7 +3029,7 @@ define <vscale x 4 x i64> @ctlz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
; RV32I-NEXT: vsrl.vx v8, v8, a0
; RV32I-NEXT: ret
;
-; RV64I-LABEL: ctlz_zero_undef_nxv4i64:
+; RV64I-LABEL: ctlz_zero_poison_nxv4i64:
; RV64I: # %bb.0:
; RV64I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV64I-NEXT: vsrl.vi v12, v8, 1
@@ -3077,7 +3077,7 @@ define <vscale x 4 x i64> @ctlz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret
;
-; CHECK-F-LABEL: ctlz_zero_undef_nxv4i64:
+; CHECK-F-LABEL: ctlz_zero_poison_nxv4i64:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: li a0, 190
; CHECK-F-NEXT: vsetvli a1, zero, e32, m2, ta, ma
@@ -3089,7 +3089,7 @@ define <vscale x 4 x i64> @ctlz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
; CHECK-F-NEXT: fsrm a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: ctlz_zero_undef_nxv4i64:
+; CHECK-D-LABEL: ctlz_zero_poison_nxv4i64:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: fsrmi a0, 1
; CHECK-D-NEXT: vsetvli a1, zero, e64, m4, ta, ma
@@ -3101,7 +3101,7 @@ define <vscale x 4 x i64> @ctlz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
; CHECK-D-NEXT: fsrm a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv4i64:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv4i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -3110,8 +3110,8 @@ define <vscale x 4 x i64> @ctlz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
ret <vscale x 4 x i64> %a
}
-define <vscale x 8 x i64> @ctlz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
-; RV32I-LABEL: ctlz_zero_undef_nxv8i64:
+define <vscale x 8 x i64> @ctlz_zero_poison_nxv8i64(<vscale x 8 x i64> %va) {
+; RV32I-LABEL: ctlz_zero_poison_nxv8i64:
; RV32I: # %bb.0:
; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32I-NEXT: vsrl.vi v16, v8, 1
@@ -3163,7 +3163,7 @@ define <vscale x 8 x i64> @ctlz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
; RV32I-NEXT: vsrl.vx v8, v8, a0
; RV32I-NEXT: ret
;
-; RV64I-LABEL: ctlz_zero_undef_nxv8i64:
+; RV64I-LABEL: ctlz_zero_poison_nxv8i64:
; RV64I: # %bb.0:
; RV64I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV64I-NEXT: vsrl.vi v16, v8, 1
@@ -3211,7 +3211,7 @@ define <vscale x 8 x i64> @ctlz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret
;
-; CHECK-F-LABEL: ctlz_zero_undef_nxv8i64:
+; CHECK-F-LABEL: ctlz_zero_poison_nxv8i64:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: li a0, 190
; CHECK-F-NEXT: vsetvli a1, zero, e32, m4, ta, ma
@@ -3223,7 +3223,7 @@ define <vscale x 8 x i64> @ctlz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
; CHECK-F-NEXT: fsrm a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: ctlz_zero_undef_nxv8i64:
+; CHECK-D-LABEL: ctlz_zero_poison_nxv8i64:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: fsrmi a0, 1
; CHECK-D-NEXT: vsetvli a1, zero, e64, m8, ta, ma
@@ -3235,7 +3235,7 @@ define <vscale x 8 x i64> @ctlz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
; CHECK-D-NEXT: fsrm a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv8i64:
+; CHECK-ZVBB-LABEL: ctlz_zero_poison_nxv8i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
index 26b778f061e95..f266fcc8787f8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
@@ -1200,8 +1200,8 @@ define <vscale x 16 x i64> @vp_ctlz_nxv16i64_unmasked(<vscale x 16 x i64> %va, i
ret <vscale x 16 x i64> %v
}
-define <vscale x 1 x i8> @vp_ctlz_zero_undef_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i8:
+define <vscale x 1 x i8> @vp_ctlz_zero_poison_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vzext.vf2 v9, v8
@@ -1213,7 +1213,7 @@ define <vscale x 1 x i8> @vp_ctlz_zero_undef_nxv1i8(<vscale x 1 x i8> %va, <vsca
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i8:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv1i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1222,8 +1222,8 @@ define <vscale x 1 x i8> @vp_ctlz_zero_undef_nxv1i8(<vscale x 1 x i8> %va, <vsca
ret <vscale x 1 x i8> %v
}
-define <vscale x 1 x i8> @vp_ctlz_zero_undef_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i8_unmasked:
+define <vscale x 1 x i8> @vp_ctlz_zero_poison_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv1i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vzext.vf2 v9, v8
@@ -1235,7 +1235,7 @@ define <vscale x 1 x i8> @vp_ctlz_zero_undef_nxv1i8_unmasked(<vscale x 1 x i8> %
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i8_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv1i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1244,8 +1244,8 @@ define <vscale x 1 x i8> @vp_ctlz_zero_undef_nxv1i8_unmasked(<vscale x 1 x i8> %
ret <vscale x 1 x i8> %v
}
-define <vscale x 2 x i8> @vp_ctlz_zero_undef_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i8:
+define <vscale x 2 x i8> @vp_ctlz_zero_poison_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vzext.vf2 v9, v8
@@ -1257,7 +1257,7 @@ define <vscale x 2 x i8> @vp_ctlz_zero_undef_nxv2i8(<vscale x 2 x i8> %va, <vsca
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv2i8:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv2i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1266,8 +1266,8 @@ define <vscale x 2 x i8> @vp_ctlz_zero_undef_nxv2i8(<vscale x 2 x i8> %va, <vsca
ret <vscale x 2 x i8> %v
}
-define <vscale x 2 x i8> @vp_ctlz_zero_undef_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i8_unmasked:
+define <vscale x 2 x i8> @vp_ctlz_zero_poison_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv2i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vzext.vf2 v9, v8
@@ -1279,7 +1279,7 @@ define <vscale x 2 x i8> @vp_ctlz_zero_undef_nxv2i8_unmasked(<vscale x 2 x i8> %
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv2i8_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv2i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1288,8 +1288,8 @@ define <vscale x 2 x i8> @vp_ctlz_zero_undef_nxv2i8_unmasked(<vscale x 2 x i8> %
ret <vscale x 2 x i8> %v
}
-define <vscale x 4 x i8> @vp_ctlz_zero_undef_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i8:
+define <vscale x 4 x i8> @vp_ctlz_zero_poison_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8
@@ -1301,7 +1301,7 @@ define <vscale x 4 x i8> @vp_ctlz_zero_undef_nxv4i8(<vscale x 4 x i8> %va, <vsca
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv4i8:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv4i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1310,8 +1310,8 @@ define <vscale x 4 x i8> @vp_ctlz_zero_undef_nxv4i8(<vscale x 4 x i8> %va, <vsca
ret <vscale x 4 x i8> %v
}
-define <vscale x 4 x i8> @vp_ctlz_zero_undef_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i8_unmasked:
+define <vscale x 4 x i8> @vp_ctlz_zero_poison_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv4i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8
@@ -1323,7 +1323,7 @@ define <vscale x 4 x i8> @vp_ctlz_zero_undef_nxv4i8_unmasked(<vscale x 4 x i8> %
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv4i8_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv4i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1332,8 +1332,8 @@ define <vscale x 4 x i8> @vp_ctlz_zero_undef_nxv4i8_unmasked(<vscale x 4 x i8> %
ret <vscale x 4 x i8> %v
}
-define <vscale x 8 x i8> @vp_ctlz_zero_undef_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i8:
+define <vscale x 8 x i8> @vp_ctlz_zero_poison_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v12, v8
@@ -1345,7 +1345,7 @@ define <vscale x 8 x i8> @vp_ctlz_zero_undef_nxv8i8(<vscale x 8 x i8> %va, <vsca
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv8i8:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv8i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1354,8 +1354,8 @@ define <vscale x 8 x i8> @vp_ctlz_zero_undef_nxv8i8(<vscale x 8 x i8> %va, <vsca
ret <vscale x 8 x i8> %v
}
-define <vscale x 8 x i8> @vp_ctlz_zero_undef_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i8_unmasked:
+define <vscale x 8 x i8> @vp_ctlz_zero_poison_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv8i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v12, v8
@@ -1367,7 +1367,7 @@ define <vscale x 8 x i8> @vp_ctlz_zero_undef_nxv8i8_unmasked(<vscale x 8 x i8> %
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv8i8_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv8i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1376,8 +1376,8 @@ define <vscale x 8 x i8> @vp_ctlz_zero_undef_nxv8i8_unmasked(<vscale x 8 x i8> %
ret <vscale x 8 x i8> %v
}
-define <vscale x 16 x i8> @vp_ctlz_zero_undef_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i8:
+define <vscale x 16 x i8> @vp_ctlz_zero_poison_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vzext.vf2 v16, v8
@@ -1389,7 +1389,7 @@ define <vscale x 16 x i8> @vp_ctlz_zero_undef_nxv16i8(<vscale x 16 x i8> %va, <v
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i8:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv16i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1398,8 +1398,8 @@ define <vscale x 16 x i8> @vp_ctlz_zero_undef_nxv16i8(<vscale x 16 x i8> %va, <v
ret <vscale x 16 x i8> %v
}
-define <vscale x 16 x i8> @vp_ctlz_zero_undef_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i8_unmasked:
+define <vscale x 16 x i8> @vp_ctlz_zero_poison_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv16i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vzext.vf2 v16, v8
@@ -1411,7 +1411,7 @@ define <vscale x 16 x i8> @vp_ctlz_zero_undef_nxv16i8_unmasked(<vscale x 16 x i8
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i8_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv16i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1420,8 +1420,8 @@ define <vscale x 16 x i8> @vp_ctlz_zero_undef_nxv16i8_unmasked(<vscale x 16 x i8
ret <vscale x 16 x i8> %v
}
-define <vscale x 32 x i8> @vp_ctlz_zero_undef_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv32i8:
+define <vscale x 32 x i8> @vp_ctlz_zero_poison_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v8, 1
@@ -1445,7 +1445,7 @@ define <vscale x 32 x i8> @vp_ctlz_zero_undef_nxv32i8(<vscale x 32 x i8> %va, <v
; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv32i8:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv32i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1454,8 +1454,8 @@ define <vscale x 32 x i8> @vp_ctlz_zero_undef_nxv32i8(<vscale x 32 x i8> %va, <v
ret <vscale x 32 x i8> %v
}
-define <vscale x 32 x i8> @vp_ctlz_zero_undef_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv32i8_unmasked:
+define <vscale x 32 x i8> @vp_ctlz_zero_poison_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv32i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v8, 1
@@ -1479,7 +1479,7 @@ define <vscale x 32 x i8> @vp_ctlz_zero_undef_nxv32i8_unmasked(<vscale x 32 x i8
; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv32i8_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv32i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1488,8 +1488,8 @@ define <vscale x 32 x i8> @vp_ctlz_zero_undef_nxv32i8_unmasked(<vscale x 32 x i8
ret <vscale x 32 x i8> %v
}
-define <vscale x 64 x i8> @vp_ctlz_zero_undef_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv64i8:
+define <vscale x 64 x i8> @vp_ctlz_zero_poison_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vsrl.vi v16, v8, 1
@@ -1513,7 +1513,7 @@ define <vscale x 64 x i8> @vp_ctlz_zero_undef_nxv64i8(<vscale x 64 x i8> %va, <v
; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv64i8:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv64i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1522,8 +1522,8 @@ define <vscale x 64 x i8> @vp_ctlz_zero_undef_nxv64i8(<vscale x 64 x i8> %va, <v
ret <vscale x 64 x i8> %v
}
-define <vscale x 64 x i8> @vp_ctlz_zero_undef_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv64i8_unmasked:
+define <vscale x 64 x i8> @vp_ctlz_zero_poison_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv64i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vsrl.vi v16, v8, 1
@@ -1547,7 +1547,7 @@ define <vscale x 64 x i8> @vp_ctlz_zero_undef_nxv64i8_unmasked(<vscale x 64 x i8
; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv64i8_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv64i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1556,8 +1556,8 @@ define <vscale x 64 x i8> @vp_ctlz_zero_undef_nxv64i8_unmasked(<vscale x 64 x i8
ret <vscale x 64 x i8> %v
}
-define <vscale x 1 x i16> @vp_ctlz_zero_undef_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i16:
+define <vscale x 1 x i16> @vp_ctlz_zero_poison_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
@@ -1566,7 +1566,7 @@ define <vscale x 1 x i16> @vp_ctlz_zero_undef_nxv1i16(<vscale x 1 x i16> %va, <v
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i16:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv1i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1575,8 +1575,8 @@ define <vscale x 1 x i16> @vp_ctlz_zero_undef_nxv1i16(<vscale x 1 x i16> %va, <v
ret <vscale x 1 x i16> %v
}
-define <vscale x 1 x i16> @vp_ctlz_zero_undef_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i16_unmasked:
+define <vscale x 1 x i16> @vp_ctlz_zero_poison_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv1i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
@@ -1585,7 +1585,7 @@ define <vscale x 1 x i16> @vp_ctlz_zero_undef_nxv1i16_unmasked(<vscale x 1 x i16
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i16_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv1i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1594,8 +1594,8 @@ define <vscale x 1 x i16> @vp_ctlz_zero_undef_nxv1i16_unmasked(<vscale x 1 x i16
ret <vscale x 1 x i16> %v
}
-define <vscale x 2 x i16> @vp_ctlz_zero_undef_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i16:
+define <vscale x 2 x i16> @vp_ctlz_zero_poison_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
@@ -1604,7 +1604,7 @@ define <vscale x 2 x i16> @vp_ctlz_zero_undef_nxv2i16(<vscale x 2 x i16> %va, <v
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv2i16:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv2i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1613,8 +1613,8 @@ define <vscale x 2 x i16> @vp_ctlz_zero_undef_nxv2i16(<vscale x 2 x i16> %va, <v
ret <vscale x 2 x i16> %v
}
-define <vscale x 2 x i16> @vp_ctlz_zero_undef_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i16_unmasked:
+define <vscale x 2 x i16> @vp_ctlz_zero_poison_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv2i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
@@ -1623,7 +1623,7 @@ define <vscale x 2 x i16> @vp_ctlz_zero_undef_nxv2i16_unmasked(<vscale x 2 x i16
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv2i16_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv2i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1632,8 +1632,8 @@ define <vscale x 2 x i16> @vp_ctlz_zero_undef_nxv2i16_unmasked(<vscale x 2 x i16
ret <vscale x 2 x i16> %v
}
-define <vscale x 4 x i16> @vp_ctlz_zero_undef_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i16:
+define <vscale x 4 x i16> @vp_ctlz_zero_poison_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
@@ -1642,7 +1642,7 @@ define <vscale x 4 x i16> @vp_ctlz_zero_undef_nxv4i16(<vscale x 4 x i16> %va, <v
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv4i16:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv4i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1651,8 +1651,8 @@ define <vscale x 4 x i16> @vp_ctlz_zero_undef_nxv4i16(<vscale x 4 x i16> %va, <v
ret <vscale x 4 x i16> %v
}
-define <vscale x 4 x i16> @vp_ctlz_zero_undef_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i16_unmasked:
+define <vscale x 4 x i16> @vp_ctlz_zero_poison_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv4i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
@@ -1661,7 +1661,7 @@ define <vscale x 4 x i16> @vp_ctlz_zero_undef_nxv4i16_unmasked(<vscale x 4 x i16
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv4i16_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv4i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1670,8 +1670,8 @@ define <vscale x 4 x i16> @vp_ctlz_zero_undef_nxv4i16_unmasked(<vscale x 4 x i16
ret <vscale x 4 x i16> %v
}
-define <vscale x 8 x i16> @vp_ctlz_zero_undef_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i16:
+define <vscale x 8 x i16> @vp_ctlz_zero_poison_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
@@ -1680,7 +1680,7 @@ define <vscale x 8 x i16> @vp_ctlz_zero_undef_nxv8i16(<vscale x 8 x i16> %va, <v
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv8i16:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv8i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1689,8 +1689,8 @@ define <vscale x 8 x i16> @vp_ctlz_zero_undef_nxv8i16(<vscale x 8 x i16> %va, <v
ret <vscale x 8 x i16> %v
}
-define <vscale x 8 x i16> @vp_ctlz_zero_undef_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i16_unmasked:
+define <vscale x 8 x i16> @vp_ctlz_zero_poison_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv8i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
@@ -1699,7 +1699,7 @@ define <vscale x 8 x i16> @vp_ctlz_zero_undef_nxv8i16_unmasked(<vscale x 8 x i16
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv8i16_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv8i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1708,8 +1708,8 @@ define <vscale x 8 x i16> @vp_ctlz_zero_undef_nxv8i16_unmasked(<vscale x 8 x i16
ret <vscale x 8 x i16> %v
}
-define <vscale x 16 x i16> @vp_ctlz_zero_undef_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i16:
+define <vscale x 16 x i16> @vp_ctlz_zero_poison_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v16, v8
@@ -1718,7 +1718,7 @@ define <vscale x 16 x i16> @vp_ctlz_zero_undef_nxv16i16(<vscale x 16 x i16> %va,
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i16:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv16i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1727,8 +1727,8 @@ define <vscale x 16 x i16> @vp_ctlz_zero_undef_nxv16i16(<vscale x 16 x i16> %va,
ret <vscale x 16 x i16> %v
}
-define <vscale x 16 x i16> @vp_ctlz_zero_undef_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i16_unmasked:
+define <vscale x 16 x i16> @vp_ctlz_zero_poison_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv16i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v16, v8
@@ -1737,7 +1737,7 @@ define <vscale x 16 x i16> @vp_ctlz_zero_undef_nxv16i16_unmasked(<vscale x 16 x
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i16_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv16i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1746,8 +1746,8 @@ define <vscale x 16 x i16> @vp_ctlz_zero_undef_nxv16i16_unmasked(<vscale x 16 x
ret <vscale x 16 x i16> %v
}
-define <vscale x 32 x i16> @vp_ctlz_zero_undef_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv32i16:
+define <vscale x 32 x i16> @vp_ctlz_zero_poison_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v16, v8, 1
@@ -1780,7 +1780,7 @@ define <vscale x 32 x i16> @vp_ctlz_zero_undef_nxv32i16(<vscale x 32 x i16> %va,
; CHECK-NEXT: vsrl.vi v8, v8, 8
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv32i16:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv32i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1789,8 +1789,8 @@ define <vscale x 32 x i16> @vp_ctlz_zero_undef_nxv32i16(<vscale x 32 x i16> %va,
ret <vscale x 32 x i16> %v
}
-define <vscale x 32 x i16> @vp_ctlz_zero_undef_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv32i16_unmasked:
+define <vscale x 32 x i16> @vp_ctlz_zero_poison_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv32i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v16, v8, 1
@@ -1823,7 +1823,7 @@ define <vscale x 32 x i16> @vp_ctlz_zero_undef_nxv32i16_unmasked(<vscale x 32 x
; CHECK-NEXT: vsrl.vi v8, v8, 8
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv32i16_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv32i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1832,8 +1832,8 @@ define <vscale x 32 x i16> @vp_ctlz_zero_undef_nxv32i16_unmasked(<vscale x 32 x
ret <vscale x 32 x i16> %v
}
-define <vscale x 1 x i32> @vp_ctlz_zero_undef_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i32:
+define <vscale x 1 x i32> @vp_ctlz_zero_poison_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
@@ -1843,7 +1843,7 @@ define <vscale x 1 x i32> @vp_ctlz_zero_undef_nxv1i32(<vscale x 1 x i32> %va, <v
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i32:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv1i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1852,8 +1852,8 @@ define <vscale x 1 x i32> @vp_ctlz_zero_undef_nxv1i32(<vscale x 1 x i32> %va, <v
ret <vscale x 1 x i32> %v
}
-define <vscale x 1 x i32> @vp_ctlz_zero_undef_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i32_unmasked:
+define <vscale x 1 x i32> @vp_ctlz_zero_poison_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv1i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
@@ -1863,7 +1863,7 @@ define <vscale x 1 x i32> @vp_ctlz_zero_undef_nxv1i32_unmasked(<vscale x 1 x i32
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i32_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv1i32_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1872,8 +1872,8 @@ define <vscale x 1 x i32> @vp_ctlz_zero_undef_nxv1i32_unmasked(<vscale x 1 x i32
ret <vscale x 1 x i32> %v
}
-define <vscale x 2 x i32> @vp_ctlz_zero_undef_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i32:
+define <vscale x 2 x i32> @vp_ctlz_zero_poison_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
@@ -1883,7 +1883,7 @@ define <vscale x 2 x i32> @vp_ctlz_zero_undef_nxv2i32(<vscale x 2 x i32> %va, <v
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv2i32:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv2i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1892,8 +1892,8 @@ define <vscale x 2 x i32> @vp_ctlz_zero_undef_nxv2i32(<vscale x 2 x i32> %va, <v
ret <vscale x 2 x i32> %v
}
-define <vscale x 2 x i32> @vp_ctlz_zero_undef_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i32_unmasked:
+define <vscale x 2 x i32> @vp_ctlz_zero_poison_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv2i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
@@ -1903,7 +1903,7 @@ define <vscale x 2 x i32> @vp_ctlz_zero_undef_nxv2i32_unmasked(<vscale x 2 x i32
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv2i32_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv2i32_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1912,8 +1912,8 @@ define <vscale x 2 x i32> @vp_ctlz_zero_undef_nxv2i32_unmasked(<vscale x 2 x i32
ret <vscale x 2 x i32> %v
}
-define <vscale x 4 x i32> @vp_ctlz_zero_undef_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i32:
+define <vscale x 4 x i32> @vp_ctlz_zero_poison_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
@@ -1923,7 +1923,7 @@ define <vscale x 4 x i32> @vp_ctlz_zero_undef_nxv4i32(<vscale x 4 x i32> %va, <v
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv4i32:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv4i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1932,8 +1932,8 @@ define <vscale x 4 x i32> @vp_ctlz_zero_undef_nxv4i32(<vscale x 4 x i32> %va, <v
ret <vscale x 4 x i32> %v
}
-define <vscale x 4 x i32> @vp_ctlz_zero_undef_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i32_unmasked:
+define <vscale x 4 x i32> @vp_ctlz_zero_poison_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv4i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
@@ -1943,7 +1943,7 @@ define <vscale x 4 x i32> @vp_ctlz_zero_undef_nxv4i32_unmasked(<vscale x 4 x i32
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv4i32_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv4i32_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1952,8 +1952,8 @@ define <vscale x 4 x i32> @vp_ctlz_zero_undef_nxv4i32_unmasked(<vscale x 4 x i32
ret <vscale x 4 x i32> %v
}
-define <vscale x 8 x i32> @vp_ctlz_zero_undef_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i32:
+define <vscale x 8 x i32> @vp_ctlz_zero_poison_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v16, v8
@@ -1963,7 +1963,7 @@ define <vscale x 8 x i32> @vp_ctlz_zero_undef_nxv8i32(<vscale x 8 x i32> %va, <v
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv8i32:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv8i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1972,8 +1972,8 @@ define <vscale x 8 x i32> @vp_ctlz_zero_undef_nxv8i32(<vscale x 8 x i32> %va, <v
ret <vscale x 8 x i32> %v
}
-define <vscale x 8 x i32> @vp_ctlz_zero_undef_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i32_unmasked:
+define <vscale x 8 x i32> @vp_ctlz_zero_poison_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv8i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v16, v8
@@ -1983,7 +1983,7 @@ define <vscale x 8 x i32> @vp_ctlz_zero_undef_nxv8i32_unmasked(<vscale x 8 x i32
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv8i32_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv8i32_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -1992,8 +1992,8 @@ define <vscale x 8 x i32> @vp_ctlz_zero_undef_nxv8i32_unmasked(<vscale x 8 x i32
ret <vscale x 8 x i32> %v
}
-define <vscale x 16 x i32> @vp_ctlz_zero_undef_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i32:
+define <vscale x 16 x i32> @vp_ctlz_zero_poison_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
@@ -2004,7 +2004,7 @@ define <vscale x 16 x i32> @vp_ctlz_zero_undef_nxv16i32(<vscale x 16 x i32> %va,
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i32:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv16i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2013,8 +2013,8 @@ define <vscale x 16 x i32> @vp_ctlz_zero_undef_nxv16i32(<vscale x 16 x i32> %va,
ret <vscale x 16 x i32> %v
}
-define <vscale x 16 x i32> @vp_ctlz_zero_undef_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i32_unmasked:
+define <vscale x 16 x i32> @vp_ctlz_zero_poison_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv16i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
@@ -2025,7 +2025,7 @@ define <vscale x 16 x i32> @vp_ctlz_zero_undef_nxv16i32_unmasked(<vscale x 16 x
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i32_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv16i32_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2034,8 +2034,8 @@ define <vscale x 16 x i32> @vp_ctlz_zero_undef_nxv16i32_unmasked(<vscale x 16 x
ret <vscale x 16 x i32> %v
}
-define <vscale x 1 x i64> @vp_ctlz_zero_undef_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i64:
+define <vscale x 1 x i64> @vp_ctlz_zero_poison_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
@@ -2047,7 +2047,7 @@ define <vscale x 1 x i64> @vp_ctlz_zero_undef_nxv1i64(<vscale x 1 x i64> %va, <v
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i64:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv1i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2056,8 +2056,8 @@ define <vscale x 1 x i64> @vp_ctlz_zero_undef_nxv1i64(<vscale x 1 x i64> %va, <v
ret <vscale x 1 x i64> %v
}
-define <vscale x 1 x i64> @vp_ctlz_zero_undef_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i64_unmasked:
+define <vscale x 1 x i64> @vp_ctlz_zero_poison_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv1i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
@@ -2069,7 +2069,7 @@ define <vscale x 1 x i64> @vp_ctlz_zero_undef_nxv1i64_unmasked(<vscale x 1 x i64
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i64_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv1i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2078,8 +2078,8 @@ define <vscale x 1 x i64> @vp_ctlz_zero_undef_nxv1i64_unmasked(<vscale x 1 x i64
ret <vscale x 1 x i64> %v
}
-define <vscale x 2 x i64> @vp_ctlz_zero_undef_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i64:
+define <vscale x 2 x i64> @vp_ctlz_zero_poison_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
@@ -2091,7 +2091,7 @@ define <vscale x 2 x i64> @vp_ctlz_zero_undef_nxv2i64(<vscale x 2 x i64> %va, <v
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv2i64:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv2i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2100,8 +2100,8 @@ define <vscale x 2 x i64> @vp_ctlz_zero_undef_nxv2i64(<vscale x 2 x i64> %va, <v
ret <vscale x 2 x i64> %v
}
-define <vscale x 2 x i64> @vp_ctlz_zero_undef_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i64_unmasked:
+define <vscale x 2 x i64> @vp_ctlz_zero_poison_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv2i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
@@ -2113,7 +2113,7 @@ define <vscale x 2 x i64> @vp_ctlz_zero_undef_nxv2i64_unmasked(<vscale x 2 x i64
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv2i64_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv2i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2122,8 +2122,8 @@ define <vscale x 2 x i64> @vp_ctlz_zero_undef_nxv2i64_unmasked(<vscale x 2 x i64
ret <vscale x 2 x i64> %v
}
-define <vscale x 4 x i64> @vp_ctlz_zero_undef_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i64:
+define <vscale x 4 x i64> @vp_ctlz_zero_poison_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma
@@ -2135,7 +2135,7 @@ define <vscale x 4 x i64> @vp_ctlz_zero_undef_nxv4i64(<vscale x 4 x i64> %va, <v
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv4i64:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv4i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2144,8 +2144,8 @@ define <vscale x 4 x i64> @vp_ctlz_zero_undef_nxv4i64(<vscale x 4 x i64> %va, <v
ret <vscale x 4 x i64> %v
}
-define <vscale x 4 x i64> @vp_ctlz_zero_undef_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i64_unmasked:
+define <vscale x 4 x i64> @vp_ctlz_zero_poison_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv4i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma
@@ -2157,7 +2157,7 @@ define <vscale x 4 x i64> @vp_ctlz_zero_undef_nxv4i64_unmasked(<vscale x 4 x i64
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv4i64_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv4i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2166,8 +2166,8 @@ define <vscale x 4 x i64> @vp_ctlz_zero_undef_nxv4i64_unmasked(<vscale x 4 x i64
ret <vscale x 4 x i64> %v
}
-define <vscale x 7 x i64> @vp_ctlz_zero_undef_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv7i64:
+define <vscale x 7 x i64> @vp_ctlz_zero_poison_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv7i64:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
@@ -2179,7 +2179,7 @@ define <vscale x 7 x i64> @vp_ctlz_zero_undef_nxv7i64(<vscale x 7 x i64> %va, <v
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv7i64:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv7i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2188,8 +2188,8 @@ define <vscale x 7 x i64> @vp_ctlz_zero_undef_nxv7i64(<vscale x 7 x i64> %va, <v
ret <vscale x 7 x i64> %v
}
-define <vscale x 7 x i64> @vp_ctlz_zero_undef_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv7i64_unmasked:
+define <vscale x 7 x i64> @vp_ctlz_zero_poison_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv7i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
@@ -2201,7 +2201,7 @@ define <vscale x 7 x i64> @vp_ctlz_zero_undef_nxv7i64_unmasked(<vscale x 7 x i64
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv7i64_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv7i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2210,8 +2210,8 @@ define <vscale x 7 x i64> @vp_ctlz_zero_undef_nxv7i64_unmasked(<vscale x 7 x i64
ret <vscale x 7 x i64> %v
}
-define <vscale x 8 x i64> @vp_ctlz_zero_undef_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i64:
+define <vscale x 8 x i64> @vp_ctlz_zero_poison_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
@@ -2223,7 +2223,7 @@ define <vscale x 8 x i64> @vp_ctlz_zero_undef_nxv8i64(<vscale x 8 x i64> %va, <v
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv8i64:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv8i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2232,8 +2232,8 @@ define <vscale x 8 x i64> @vp_ctlz_zero_undef_nxv8i64(<vscale x 8 x i64> %va, <v
ret <vscale x 8 x i64> %v
}
-define <vscale x 8 x i64> @vp_ctlz_zero_undef_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i64_unmasked:
+define <vscale x 8 x i64> @vp_ctlz_zero_poison_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv8i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
@@ -2245,7 +2245,7 @@ define <vscale x 8 x i64> @vp_ctlz_zero_undef_nxv8i64_unmasked(<vscale x 8 x i64
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv8i64_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv8i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2254,8 +2254,8 @@ define <vscale x 8 x i64> @vp_ctlz_zero_undef_nxv8i64_unmasked(<vscale x 8 x i64
ret <vscale x 8 x i64> %v
}
-define <vscale x 16 x i64> @vp_ctlz_zero_undef_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i64:
+define <vscale x 16 x i64> @vp_ctlz_zero_poison_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
@@ -2270,7 +2270,7 @@ define <vscale x 16 x i64> @vp_ctlz_zero_undef_nxv16i64(<vscale x 16 x i64> %va,
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i64:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv16i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2280,8 +2280,8 @@ define <vscale x 16 x i64> @vp_ctlz_zero_undef_nxv16i64(<vscale x 16 x i64> %va,
ret <vscale x 16 x i64> %v
}
-define <vscale x 16 x i64> @vp_ctlz_zero_undef_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i64_unmasked:
+define <vscale x 16 x i64> @vp_ctlz_zero_poison_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv16i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
@@ -2296,7 +2296,7 @@ define <vscale x 16 x i64> @vp_ctlz_zero_undef_nxv16i64_unmasked(<vscale x 16 x
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i64_unmasked:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv16i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v8, v8
@@ -2333,8 +2333,8 @@ define <vscale x 1 x i9> @vp_ctlz_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1
%v = call <vscale x 1 x i9> @llvm.vp.ctlz.nxv1i9(<vscale x 1 x i9> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i9> %v
}
-define <vscale x 1 x i9> @vp_ctlz_zero_undef_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i9:
+define <vscale x 1 x i9> @vp_ctlz_zero_poison_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_nxv1i9:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 7
@@ -2344,7 +2344,7 @@ define <vscale x 1 x i9> @vp_ctlz_zero_undef_nxv1i9(<vscale x 1 x i9> %va, <vsca
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i9:
+; CHECK-ZVBB-LABEL: vp_ctlz_zero_poison_nxv1i9:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-ZVBB-NEXT: vsll.vi v8, v8, 7
@@ -2376,8 +2376,8 @@ define <vscale x 1 x i9> @vp_ctlo_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1
%v = call <vscale x 1 x i9> @llvm.vp.ctlz.nxv1i9(<vscale x 1 x i9> %va.not, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i9> %v
}
-define <vscale x 1 x i9> @vp_ctlo_zero_undef_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlo_zero_undef_nxv1i9:
+define <vscale x 1 x i9> @vp_ctlo_zero_poison_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlo_zero_poison_nxv1i9:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 511
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
@@ -2389,7 +2389,7 @@ define <vscale x 1 x i9> @vp_ctlo_zero_undef_nxv1i9(<vscale x 1 x i9> %va, <vsca
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlo_zero_undef_nxv1i9:
+; CHECK-ZVBB-LABEL: vp_ctlo_zero_poison_nxv1i9:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: li a0, 511
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
@@ -2426,8 +2426,8 @@ define <vscale x 1 x i9> @vp_ctlo_nxv1i9_vp_xor(<vscale x 1 x i9> %va, <vscale x
ret <vscale x 1 x i9> %v
}
-define <vscale x 1 x i9> @vp_ctlo_zero_undef_nxv1i9_vp_xor(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlo_zero_undef_nxv1i9_vp_xor:
+define <vscale x 1 x i9> @vp_ctlo_zero_poison_nxv1i9_vp_xor(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlo_zero_poison_nxv1i9_vp_xor:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 511
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
@@ -2439,7 +2439,7 @@ define <vscale x 1 x i9> @vp_ctlo_zero_undef_nxv1i9_vp_xor(<vscale x 1 x i9> %va
; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_ctlo_zero_undef_nxv1i9_vp_xor:
+; CHECK-ZVBB-LABEL: vp_ctlo_zero_poison_nxv1i9_vp_xor:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: li a0, 511
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
index 79af06db4171e..7a4e948634333 100644
--- a/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
@@ -1588,8 +1588,8 @@ define <vscale x 8 x i64> @cttz_nxv8i64(<vscale x 8 x i64> %va) {
ret <vscale x 8 x i64> %a
}
-define <vscale x 1 x i8> @cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va) {
-; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv1i8:
+define <vscale x 1 x i8> @cttz_zero_poison_nxv1i8(<vscale x 1 x i8> %va) {
+; CHECK-ZVE64X-LABEL: cttz_zero_poison_nxv1i8:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-ZVE64X-NEXT: vadd.vi v9, v8, -1
@@ -1609,7 +1609,7 @@ define <vscale x 1 x i8> @cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va) {
; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: cttz_zero_undef_nxv1i8:
+; CHECK-F-LABEL: cttz_zero_poison_nxv1i8:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-F-NEXT: vrsub.vi v9, v8, 0
@@ -1624,7 +1624,7 @@ define <vscale x 1 x i8> @cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va) {
; CHECK-F-NEXT: vsub.vx v8, v8, a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: cttz_zero_undef_nxv1i8:
+; CHECK-D-LABEL: cttz_zero_poison_nxv1i8:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-D-NEXT: vrsub.vi v9, v8, 0
@@ -1639,7 +1639,7 @@ define <vscale x 1 x i8> @cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va) {
; CHECK-D-NEXT: vsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv1i8:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv1i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1648,8 +1648,8 @@ define <vscale x 1 x i8> @cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va) {
ret <vscale x 1 x i8> %a
}
-define <vscale x 2 x i8> @cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) {
-; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv2i8:
+define <vscale x 2 x i8> @cttz_zero_poison_nxv2i8(<vscale x 2 x i8> %va) {
+; CHECK-ZVE64X-LABEL: cttz_zero_poison_nxv2i8:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-ZVE64X-NEXT: vadd.vi v9, v8, -1
@@ -1669,7 +1669,7 @@ define <vscale x 2 x i8> @cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) {
; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: cttz_zero_undef_nxv2i8:
+; CHECK-F-LABEL: cttz_zero_poison_nxv2i8:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-F-NEXT: vrsub.vi v9, v8, 0
@@ -1684,7 +1684,7 @@ define <vscale x 2 x i8> @cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) {
; CHECK-F-NEXT: vsub.vx v8, v8, a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: cttz_zero_undef_nxv2i8:
+; CHECK-D-LABEL: cttz_zero_poison_nxv2i8:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-D-NEXT: vrsub.vi v9, v8, 0
@@ -1699,7 +1699,7 @@ define <vscale x 2 x i8> @cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) {
; CHECK-D-NEXT: vsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv2i8:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv2i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1708,8 +1708,8 @@ define <vscale x 2 x i8> @cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) {
ret <vscale x 2 x i8> %a
}
-define <vscale x 4 x i8> @cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) {
-; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv4i8:
+define <vscale x 4 x i8> @cttz_zero_poison_nxv4i8(<vscale x 4 x i8> %va) {
+; CHECK-ZVE64X-LABEL: cttz_zero_poison_nxv4i8:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-ZVE64X-NEXT: vadd.vi v9, v8, -1
@@ -1729,7 +1729,7 @@ define <vscale x 4 x i8> @cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) {
; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: cttz_zero_undef_nxv4i8:
+; CHECK-F-LABEL: cttz_zero_poison_nxv4i8:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-F-NEXT: vrsub.vi v9, v8, 0
@@ -1744,7 +1744,7 @@ define <vscale x 4 x i8> @cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) {
; CHECK-F-NEXT: vsub.vx v8, v8, a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: cttz_zero_undef_nxv4i8:
+; CHECK-D-LABEL: cttz_zero_poison_nxv4i8:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-D-NEXT: vrsub.vi v9, v8, 0
@@ -1759,7 +1759,7 @@ define <vscale x 4 x i8> @cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) {
; CHECK-D-NEXT: vsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv4i8:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv4i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1768,8 +1768,8 @@ define <vscale x 4 x i8> @cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) {
ret <vscale x 4 x i8> %a
}
-define <vscale x 8 x i8> @cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) {
-; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv8i8:
+define <vscale x 8 x i8> @cttz_zero_poison_nxv8i8(<vscale x 8 x i8> %va) {
+; CHECK-ZVE64X-LABEL: cttz_zero_poison_nxv8i8:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-ZVE64X-NEXT: vadd.vi v9, v8, -1
@@ -1789,7 +1789,7 @@ define <vscale x 8 x i8> @cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) {
; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: cttz_zero_undef_nxv8i8:
+; CHECK-F-LABEL: cttz_zero_poison_nxv8i8:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-F-NEXT: vrsub.vi v9, v8, 0
@@ -1804,7 +1804,7 @@ define <vscale x 8 x i8> @cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) {
; CHECK-F-NEXT: vsub.vx v8, v8, a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: cttz_zero_undef_nxv8i8:
+; CHECK-D-LABEL: cttz_zero_poison_nxv8i8:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-D-NEXT: vrsub.vi v9, v8, 0
@@ -1819,7 +1819,7 @@ define <vscale x 8 x i8> @cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) {
; CHECK-D-NEXT: vsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv8i8:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv8i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1828,8 +1828,8 @@ define <vscale x 8 x i8> @cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) {
ret <vscale x 8 x i8> %a
}
-define <vscale x 16 x i8> @cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
-; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv16i8:
+define <vscale x 16 x i8> @cttz_zero_poison_nxv16i8(<vscale x 16 x i8> %va) {
+; CHECK-ZVE64X-LABEL: cttz_zero_poison_nxv16i8:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-ZVE64X-NEXT: vadd.vi v10, v8, -1
@@ -1849,7 +1849,7 @@ define <vscale x 16 x i8> @cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: cttz_zero_undef_nxv16i8:
+; CHECK-F-LABEL: cttz_zero_poison_nxv16i8:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-F-NEXT: vrsub.vi v10, v8, 0
@@ -1864,7 +1864,7 @@ define <vscale x 16 x i8> @cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
; CHECK-F-NEXT: vsub.vx v8, v8, a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: cttz_zero_undef_nxv16i8:
+; CHECK-D-LABEL: cttz_zero_poison_nxv16i8:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-D-NEXT: vrsub.vi v10, v8, 0
@@ -1879,7 +1879,7 @@ define <vscale x 16 x i8> @cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
; CHECK-D-NEXT: vsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv16i8:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv16i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1888,8 +1888,8 @@ define <vscale x 16 x i8> @cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
ret <vscale x 16 x i8> %a
}
-define <vscale x 32 x i8> @cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va) {
-; CHECK-LABEL: cttz_zero_undef_nxv32i8:
+define <vscale x 32 x i8> @cttz_zero_poison_nxv32i8(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: cttz_zero_poison_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vadd.vi v12, v8, -1
@@ -1909,7 +1909,7 @@ define <vscale x 32 x i8> @cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va) {
; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv32i8:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv32i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1918,8 +1918,8 @@ define <vscale x 32 x i8> @cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va) {
ret <vscale x 32 x i8> %a
}
-define <vscale x 64 x i8> @cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va) {
-; CHECK-LABEL: cttz_zero_undef_nxv64i8:
+define <vscale x 64 x i8> @cttz_zero_poison_nxv64i8(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: cttz_zero_poison_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v8, -1
@@ -1939,7 +1939,7 @@ define <vscale x 64 x i8> @cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va) {
; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv64i8:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv64i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1948,8 +1948,8 @@ define <vscale x 64 x i8> @cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va) {
ret <vscale x 64 x i8> %a
}
-define <vscale x 1 x i16> @cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va) {
-; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv1i16:
+define <vscale x 1 x i16> @cttz_zero_poison_nxv1i16(<vscale x 1 x i16> %va) {
+; CHECK-ZVE64X-LABEL: cttz_zero_poison_nxv1i16:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-ZVE64X-NEXT: vadd.vi v9, v8, -1
@@ -1976,7 +1976,7 @@ define <vscale x 1 x i16> @cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va) {
; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: cttz_zero_undef_nxv1i16:
+; CHECK-F-LABEL: cttz_zero_poison_nxv1i16:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-F-NEXT: vrsub.vi v9, v8, 0
@@ -1987,7 +1987,7 @@ define <vscale x 1 x i16> @cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va) {
; CHECK-F-NEXT: vsub.vx v8, v8, a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: cttz_zero_undef_nxv1i16:
+; CHECK-D-LABEL: cttz_zero_poison_nxv1i16:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-D-NEXT: vrsub.vi v9, v8, 0
@@ -1998,7 +1998,7 @@ define <vscale x 1 x i16> @cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va) {
; CHECK-D-NEXT: vsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv1i16:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv1i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2007,8 +2007,8 @@ define <vscale x 1 x i16> @cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va) {
ret <vscale x 1 x i16> %a
}
-define <vscale x 2 x i16> @cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {
-; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv2i16:
+define <vscale x 2 x i16> @cttz_zero_poison_nxv2i16(<vscale x 2 x i16> %va) {
+; CHECK-ZVE64X-LABEL: cttz_zero_poison_nxv2i16:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-ZVE64X-NEXT: vadd.vi v9, v8, -1
@@ -2035,7 +2035,7 @@ define <vscale x 2 x i16> @cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {
; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: cttz_zero_undef_nxv2i16:
+; CHECK-F-LABEL: cttz_zero_poison_nxv2i16:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-F-NEXT: vrsub.vi v9, v8, 0
@@ -2046,7 +2046,7 @@ define <vscale x 2 x i16> @cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {
; CHECK-F-NEXT: vsub.vx v8, v8, a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: cttz_zero_undef_nxv2i16:
+; CHECK-D-LABEL: cttz_zero_poison_nxv2i16:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-D-NEXT: vrsub.vi v9, v8, 0
@@ -2057,7 +2057,7 @@ define <vscale x 2 x i16> @cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {
; CHECK-D-NEXT: vsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv2i16:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv2i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2066,8 +2066,8 @@ define <vscale x 2 x i16> @cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {
ret <vscale x 2 x i16> %a
}
-define <vscale x 4 x i16> @cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {
-; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv4i16:
+define <vscale x 4 x i16> @cttz_zero_poison_nxv4i16(<vscale x 4 x i16> %va) {
+; CHECK-ZVE64X-LABEL: cttz_zero_poison_nxv4i16:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-ZVE64X-NEXT: vadd.vi v9, v8, -1
@@ -2094,7 +2094,7 @@ define <vscale x 4 x i16> @cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {
; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: cttz_zero_undef_nxv4i16:
+; CHECK-F-LABEL: cttz_zero_poison_nxv4i16:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-F-NEXT: vrsub.vi v9, v8, 0
@@ -2105,7 +2105,7 @@ define <vscale x 4 x i16> @cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {
; CHECK-F-NEXT: vsub.vx v8, v10, a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: cttz_zero_undef_nxv4i16:
+; CHECK-D-LABEL: cttz_zero_poison_nxv4i16:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-D-NEXT: vrsub.vi v9, v8, 0
@@ -2116,7 +2116,7 @@ define <vscale x 4 x i16> @cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {
; CHECK-D-NEXT: vsub.vx v8, v10, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv4i16:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv4i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2125,8 +2125,8 @@ define <vscale x 4 x i16> @cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {
ret <vscale x 4 x i16> %a
}
-define <vscale x 8 x i16> @cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
-; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv8i16:
+define <vscale x 8 x i16> @cttz_zero_poison_nxv8i16(<vscale x 8 x i16> %va) {
+; CHECK-ZVE64X-LABEL: cttz_zero_poison_nxv8i16:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-ZVE64X-NEXT: vadd.vi v10, v8, -1
@@ -2153,7 +2153,7 @@ define <vscale x 8 x i16> @cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: cttz_zero_undef_nxv8i16:
+; CHECK-F-LABEL: cttz_zero_poison_nxv8i16:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-F-NEXT: vrsub.vi v10, v8, 0
@@ -2164,7 +2164,7 @@ define <vscale x 8 x i16> @cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
; CHECK-F-NEXT: vsub.vx v8, v12, a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: cttz_zero_undef_nxv8i16:
+; CHECK-D-LABEL: cttz_zero_poison_nxv8i16:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-D-NEXT: vrsub.vi v10, v8, 0
@@ -2175,7 +2175,7 @@ define <vscale x 8 x i16> @cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
; CHECK-D-NEXT: vsub.vx v8, v12, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv8i16:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv8i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2184,8 +2184,8 @@ define <vscale x 8 x i16> @cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
ret <vscale x 8 x i16> %a
}
-define <vscale x 16 x i16> @cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
-; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv16i16:
+define <vscale x 16 x i16> @cttz_zero_poison_nxv16i16(<vscale x 16 x i16> %va) {
+; CHECK-ZVE64X-LABEL: cttz_zero_poison_nxv16i16:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-ZVE64X-NEXT: vadd.vi v12, v8, -1
@@ -2212,7 +2212,7 @@ define <vscale x 16 x i16> @cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: cttz_zero_undef_nxv16i16:
+; CHECK-F-LABEL: cttz_zero_poison_nxv16i16:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-F-NEXT: vrsub.vi v12, v8, 0
@@ -2223,7 +2223,7 @@ define <vscale x 16 x i16> @cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
; CHECK-F-NEXT: vsub.vx v8, v16, a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: cttz_zero_undef_nxv16i16:
+; CHECK-D-LABEL: cttz_zero_poison_nxv16i16:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-D-NEXT: vrsub.vi v12, v8, 0
@@ -2234,7 +2234,7 @@ define <vscale x 16 x i16> @cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
; CHECK-D-NEXT: vsub.vx v8, v16, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv16i16:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv16i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2243,8 +2243,8 @@ define <vscale x 16 x i16> @cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
ret <vscale x 16 x i16> %a
}
-define <vscale x 32 x i16> @cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) {
-; CHECK-LABEL: cttz_zero_undef_nxv32i16:
+define <vscale x 32 x i16> @cttz_zero_poison_nxv32i16(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: cttz_zero_poison_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v8, -1
@@ -2271,7 +2271,7 @@ define <vscale x 32 x i16> @cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) {
; CHECK-NEXT: vsrl.vi v8, v8, 8
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv32i16:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv32i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2280,8 +2280,8 @@ define <vscale x 32 x i16> @cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) {
ret <vscale x 32 x i16> %a
}
-define <vscale x 1 x i32> @cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va) {
-; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv1i32:
+define <vscale x 1 x i32> @cttz_zero_poison_nxv1i32(<vscale x 1 x i32> %va) {
+; CHECK-ZVE64X-LABEL: cttz_zero_poison_nxv1i32:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-ZVE64X-NEXT: vadd.vi v9, v8, -1
@@ -2309,7 +2309,7 @@ define <vscale x 1 x i32> @cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va) {
; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: cttz_zero_undef_nxv1i32:
+; CHECK-F-LABEL: cttz_zero_poison_nxv1i32:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-F-NEXT: vrsub.vi v9, v8, 0
@@ -2322,7 +2322,7 @@ define <vscale x 1 x i32> @cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va) {
; CHECK-F-NEXT: fsrm a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: cttz_zero_undef_nxv1i32:
+; CHECK-D-LABEL: cttz_zero_poison_nxv1i32:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-D-NEXT: vrsub.vi v9, v8, 0
@@ -2334,7 +2334,7 @@ define <vscale x 1 x i32> @cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va) {
; CHECK-D-NEXT: vsub.vx v8, v8, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv1i32:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv1i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2343,8 +2343,8 @@ define <vscale x 1 x i32> @cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va) {
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
-; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv2i32:
+define <vscale x 2 x i32> @cttz_zero_poison_nxv2i32(<vscale x 2 x i32> %va) {
+; CHECK-ZVE64X-LABEL: cttz_zero_poison_nxv2i32:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-ZVE64X-NEXT: vadd.vi v9, v8, -1
@@ -2372,7 +2372,7 @@ define <vscale x 2 x i32> @cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: cttz_zero_undef_nxv2i32:
+; CHECK-F-LABEL: cttz_zero_poison_nxv2i32:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-F-NEXT: vrsub.vi v9, v8, 0
@@ -2385,7 +2385,7 @@ define <vscale x 2 x i32> @cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
; CHECK-F-NEXT: fsrm a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: cttz_zero_undef_nxv2i32:
+; CHECK-D-LABEL: cttz_zero_poison_nxv2i32:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-D-NEXT: vrsub.vi v9, v8, 0
@@ -2397,7 +2397,7 @@ define <vscale x 2 x i32> @cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
; CHECK-D-NEXT: vsub.vx v8, v10, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv2i32:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv2i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2406,8 +2406,8 @@ define <vscale x 2 x i32> @cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
-; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv4i32:
+define <vscale x 4 x i32> @cttz_zero_poison_nxv4i32(<vscale x 4 x i32> %va) {
+; CHECK-ZVE64X-LABEL: cttz_zero_poison_nxv4i32:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-ZVE64X-NEXT: vadd.vi v10, v8, -1
@@ -2435,7 +2435,7 @@ define <vscale x 4 x i32> @cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: cttz_zero_undef_nxv4i32:
+; CHECK-F-LABEL: cttz_zero_poison_nxv4i32:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-F-NEXT: vrsub.vi v10, v8, 0
@@ -2448,7 +2448,7 @@ define <vscale x 4 x i32> @cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
; CHECK-F-NEXT: fsrm a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: cttz_zero_undef_nxv4i32:
+; CHECK-D-LABEL: cttz_zero_poison_nxv4i32:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-D-NEXT: vrsub.vi v10, v8, 0
@@ -2460,7 +2460,7 @@ define <vscale x 4 x i32> @cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
; CHECK-D-NEXT: vsub.vx v8, v12, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv4i32:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv4i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2469,8 +2469,8 @@ define <vscale x 4 x i32> @cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
-; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv8i32:
+define <vscale x 8 x i32> @cttz_zero_poison_nxv8i32(<vscale x 8 x i32> %va) {
+; CHECK-ZVE64X-LABEL: cttz_zero_poison_nxv8i32:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-ZVE64X-NEXT: vadd.vi v12, v8, -1
@@ -2498,7 +2498,7 @@ define <vscale x 8 x i32> @cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: cttz_zero_undef_nxv8i32:
+; CHECK-F-LABEL: cttz_zero_poison_nxv8i32:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-F-NEXT: vrsub.vi v12, v8, 0
@@ -2511,7 +2511,7 @@ define <vscale x 8 x i32> @cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
; CHECK-F-NEXT: fsrm a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: cttz_zero_undef_nxv8i32:
+; CHECK-D-LABEL: cttz_zero_poison_nxv8i32:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-D-NEXT: vrsub.vi v12, v8, 0
@@ -2523,7 +2523,7 @@ define <vscale x 8 x i32> @cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
; CHECK-D-NEXT: vsub.vx v8, v16, a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv8i32:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv8i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2532,8 +2532,8 @@ define <vscale x 8 x i32> @cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
-; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv16i32:
+define <vscale x 16 x i32> @cttz_zero_poison_nxv16i32(<vscale x 16 x i32> %va) {
+; CHECK-ZVE64X-LABEL: cttz_zero_poison_nxv16i32:
; CHECK-ZVE64X: # %bb.0:
; CHECK-ZVE64X-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-ZVE64X-NEXT: vadd.vi v16, v8, -1
@@ -2561,7 +2561,7 @@ define <vscale x 16 x i32> @cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
; CHECK-ZVE64X-NEXT: ret
;
-; CHECK-F-LABEL: cttz_zero_undef_nxv16i32:
+; CHECK-F-LABEL: cttz_zero_poison_nxv16i32:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-F-NEXT: vrsub.vi v16, v8, 0
@@ -2574,7 +2574,7 @@ define <vscale x 16 x i32> @cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
; CHECK-F-NEXT: fsrm a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: cttz_zero_undef_nxv16i32:
+; CHECK-D-LABEL: cttz_zero_poison_nxv16i32:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-D-NEXT: vrsub.vi v16, v8, 0
@@ -2587,7 +2587,7 @@ define <vscale x 16 x i32> @cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
; CHECK-D-NEXT: fsrm a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv16i32:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv16i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2596,8 +2596,8 @@ define <vscale x 16 x i32> @cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i64> @cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
-; RV32I-LABEL: cttz_zero_undef_nxv1i64:
+define <vscale x 1 x i64> @cttz_zero_poison_nxv1i64(<vscale x 1 x i64> %va) {
+; RV32I-LABEL: cttz_zero_poison_nxv1i64:
; RV32I: # %bb.0:
; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32I-NEXT: vadd.vi v9, v8, -1
@@ -2638,7 +2638,7 @@ define <vscale x 1 x i64> @cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
; RV32I-NEXT: vsrl.vx v8, v8, a0
; RV32I-NEXT: ret
;
-; RV64I-LABEL: cttz_zero_undef_nxv1i64:
+; RV64I-LABEL: cttz_zero_poison_nxv1i64:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a0, 349525
; RV64I-NEXT: lui a1, 209715
@@ -2675,7 +2675,7 @@ define <vscale x 1 x i64> @cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret
;
-; CHECK-F-LABEL: cttz_zero_undef_nxv1i64:
+; CHECK-F-LABEL: cttz_zero_poison_nxv1i64:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-F-NEXT: vrsub.vi v9, v8, 0
@@ -2689,7 +2689,7 @@ define <vscale x 1 x i64> @cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
; CHECK-F-NEXT: fsrm a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: cttz_zero_undef_nxv1i64:
+; CHECK-D-LABEL: cttz_zero_poison_nxv1i64:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-D-NEXT: vrsub.vi v9, v8, 0
@@ -2703,7 +2703,7 @@ define <vscale x 1 x i64> @cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
; CHECK-D-NEXT: fsrm a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv1i64:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv1i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2712,8 +2712,8 @@ define <vscale x 1 x i64> @cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
ret <vscale x 1 x i64> %a
}
-define <vscale x 2 x i64> @cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
-; RV32I-LABEL: cttz_zero_undef_nxv2i64:
+define <vscale x 2 x i64> @cttz_zero_poison_nxv2i64(<vscale x 2 x i64> %va) {
+; RV32I-LABEL: cttz_zero_poison_nxv2i64:
; RV32I: # %bb.0:
; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV32I-NEXT: vadd.vi v10, v8, -1
@@ -2754,7 +2754,7 @@ define <vscale x 2 x i64> @cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
; RV32I-NEXT: vsrl.vx v8, v8, a0
; RV32I-NEXT: ret
;
-; RV64I-LABEL: cttz_zero_undef_nxv2i64:
+; RV64I-LABEL: cttz_zero_poison_nxv2i64:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a0, 349525
; RV64I-NEXT: lui a1, 209715
@@ -2791,7 +2791,7 @@ define <vscale x 2 x i64> @cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret
;
-; CHECK-F-LABEL: cttz_zero_undef_nxv2i64:
+; CHECK-F-LABEL: cttz_zero_poison_nxv2i64:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-F-NEXT: vrsub.vi v10, v8, 0
@@ -2805,7 +2805,7 @@ define <vscale x 2 x i64> @cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
; CHECK-F-NEXT: fsrm a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: cttz_zero_undef_nxv2i64:
+; CHECK-D-LABEL: cttz_zero_poison_nxv2i64:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-D-NEXT: vrsub.vi v10, v8, 0
@@ -2819,7 +2819,7 @@ define <vscale x 2 x i64> @cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
; CHECK-D-NEXT: fsrm a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv2i64:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv2i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2828,8 +2828,8 @@ define <vscale x 2 x i64> @cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
ret <vscale x 2 x i64> %a
}
-define <vscale x 4 x i64> @cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
-; RV32I-LABEL: cttz_zero_undef_nxv4i64:
+define <vscale x 4 x i64> @cttz_zero_poison_nxv4i64(<vscale x 4 x i64> %va) {
+; RV32I-LABEL: cttz_zero_poison_nxv4i64:
; RV32I: # %bb.0:
; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV32I-NEXT: vadd.vi v12, v8, -1
@@ -2870,7 +2870,7 @@ define <vscale x 4 x i64> @cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
; RV32I-NEXT: vsrl.vx v8, v8, a0
; RV32I-NEXT: ret
;
-; RV64I-LABEL: cttz_zero_undef_nxv4i64:
+; RV64I-LABEL: cttz_zero_poison_nxv4i64:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a0, 349525
; RV64I-NEXT: lui a1, 209715
@@ -2907,7 +2907,7 @@ define <vscale x 4 x i64> @cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret
;
-; CHECK-F-LABEL: cttz_zero_undef_nxv4i64:
+; CHECK-F-LABEL: cttz_zero_poison_nxv4i64:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-F-NEXT: vrsub.vi v12, v8, 0
@@ -2921,7 +2921,7 @@ define <vscale x 4 x i64> @cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
; CHECK-F-NEXT: fsrm a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: cttz_zero_undef_nxv4i64:
+; CHECK-D-LABEL: cttz_zero_poison_nxv4i64:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-D-NEXT: vrsub.vi v12, v8, 0
@@ -2935,7 +2935,7 @@ define <vscale x 4 x i64> @cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
; CHECK-D-NEXT: fsrm a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv4i64:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv4i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2944,8 +2944,8 @@ define <vscale x 4 x i64> @cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
ret <vscale x 4 x i64> %a
}
-define <vscale x 8 x i64> @cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
-; RV32I-LABEL: cttz_zero_undef_nxv8i64:
+define <vscale x 8 x i64> @cttz_zero_poison_nxv8i64(<vscale x 8 x i64> %va) {
+; RV32I-LABEL: cttz_zero_poison_nxv8i64:
; RV32I: # %bb.0:
; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32I-NEXT: vadd.vi v16, v8, -1
@@ -2986,7 +2986,7 @@ define <vscale x 8 x i64> @cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
; RV32I-NEXT: vsrl.vx v8, v8, a0
; RV32I-NEXT: ret
;
-; RV64I-LABEL: cttz_zero_undef_nxv8i64:
+; RV64I-LABEL: cttz_zero_poison_nxv8i64:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a0, 349525
; RV64I-NEXT: lui a1, 209715
@@ -3023,7 +3023,7 @@ define <vscale x 8 x i64> @cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret
;
-; CHECK-F-LABEL: cttz_zero_undef_nxv8i64:
+; CHECK-F-LABEL: cttz_zero_poison_nxv8i64:
; CHECK-F: # %bb.0:
; CHECK-F-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-F-NEXT: vrsub.vi v16, v8, 0
@@ -3037,7 +3037,7 @@ define <vscale x 8 x i64> @cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
; CHECK-F-NEXT: fsrm a0
; CHECK-F-NEXT: ret
;
-; CHECK-D-LABEL: cttz_zero_undef_nxv8i64:
+; CHECK-D-LABEL: cttz_zero_poison_nxv8i64:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-D-NEXT: vrsub.vi v16, v8, 0
@@ -3051,7 +3051,7 @@ define <vscale x 8 x i64> @cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
; CHECK-D-NEXT: fsrm a0
; CHECK-D-NEXT: ret
;
-; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv8i64:
+; CHECK-ZVBB-LABEL: cttz_zero_poison_nxv8i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
index 9b2f220dd802e..fe371817bf494 100644
--- a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
@@ -1306,8 +1306,8 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64_unmasked(<vscale x 16 x i64> %va, i
ret <vscale x 16 x i64> %v
}
-define <vscale x 1 x i8> @vp_cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv1i8:
+define <vscale x 1 x i8> @vp_cttz_zero_poison_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1322,7 +1322,7 @@ define <vscale x 1 x i8> @vp_cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va, <vsca
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i8:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv1i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1331,8 +1331,8 @@ define <vscale x 1 x i8> @vp_cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va, <vsca
ret <vscale x 1 x i8> %v
}
-define <vscale x 1 x i8> @vp_cttz_zero_undef_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv1i8_unmasked:
+define <vscale x 1 x i8> @vp_cttz_zero_poison_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv1i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1347,7 +1347,7 @@ define <vscale x 1 x i8> @vp_cttz_zero_undef_nxv1i8_unmasked(<vscale x 1 x i8> %
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i8_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv1i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1356,8 +1356,8 @@ define <vscale x 1 x i8> @vp_cttz_zero_undef_nxv1i8_unmasked(<vscale x 1 x i8> %
ret <vscale x 1 x i8> %v
}
-define <vscale x 2 x i8> @vp_cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv2i8:
+define <vscale x 2 x i8> @vp_cttz_zero_poison_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1372,7 +1372,7 @@ define <vscale x 2 x i8> @vp_cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va, <vsca
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i8:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv2i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1381,8 +1381,8 @@ define <vscale x 2 x i8> @vp_cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va, <vsca
ret <vscale x 2 x i8> %v
}
-define <vscale x 2 x i8> @vp_cttz_zero_undef_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv2i8_unmasked:
+define <vscale x 2 x i8> @vp_cttz_zero_poison_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv2i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1397,7 +1397,7 @@ define <vscale x 2 x i8> @vp_cttz_zero_undef_nxv2i8_unmasked(<vscale x 2 x i8> %
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i8_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv2i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1406,8 +1406,8 @@ define <vscale x 2 x i8> @vp_cttz_zero_undef_nxv2i8_unmasked(<vscale x 2 x i8> %
ret <vscale x 2 x i8> %v
}
-define <vscale x 4 x i8> @vp_cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv4i8:
+define <vscale x 4 x i8> @vp_cttz_zero_poison_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1422,7 +1422,7 @@ define <vscale x 4 x i8> @vp_cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va, <vsca
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i8:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv4i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1431,8 +1431,8 @@ define <vscale x 4 x i8> @vp_cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va, <vsca
ret <vscale x 4 x i8> %v
}
-define <vscale x 4 x i8> @vp_cttz_zero_undef_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv4i8_unmasked:
+define <vscale x 4 x i8> @vp_cttz_zero_poison_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv4i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1447,7 +1447,7 @@ define <vscale x 4 x i8> @vp_cttz_zero_undef_nxv4i8_unmasked(<vscale x 4 x i8> %
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i8_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv4i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1456,8 +1456,8 @@ define <vscale x 4 x i8> @vp_cttz_zero_undef_nxv4i8_unmasked(<vscale x 4 x i8> %
ret <vscale x 4 x i8> %v
}
-define <vscale x 8 x i8> @vp_cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv8i8:
+define <vscale x 8 x i8> @vp_cttz_zero_poison_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1472,7 +1472,7 @@ define <vscale x 8 x i8> @vp_cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va, <vsca
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i8:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv8i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1481,8 +1481,8 @@ define <vscale x 8 x i8> @vp_cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va, <vsca
ret <vscale x 8 x i8> %v
}
-define <vscale x 8 x i8> @vp_cttz_zero_undef_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv8i8_unmasked:
+define <vscale x 8 x i8> @vp_cttz_zero_poison_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv8i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1497,7 +1497,7 @@ define <vscale x 8 x i8> @vp_cttz_zero_undef_nxv8i8_unmasked(<vscale x 8 x i8> %
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i8_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv8i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1506,8 +1506,8 @@ define <vscale x 8 x i8> @vp_cttz_zero_undef_nxv8i8_unmasked(<vscale x 8 x i8> %
ret <vscale x 8 x i8> %v
}
-define <vscale x 16 x i8> @vp_cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv16i8:
+define <vscale x 16 x i8> @vp_cttz_zero_poison_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
@@ -1522,7 +1522,7 @@ define <vscale x 16 x i8> @vp_cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va, <v
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i8:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv16i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1531,8 +1531,8 @@ define <vscale x 16 x i8> @vp_cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va, <v
ret <vscale x 16 x i8> %v
}
-define <vscale x 16 x i8> @vp_cttz_zero_undef_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv16i8_unmasked:
+define <vscale x 16 x i8> @vp_cttz_zero_poison_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv16i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
@@ -1547,7 +1547,7 @@ define <vscale x 16 x i8> @vp_cttz_zero_undef_nxv16i8_unmasked(<vscale x 16 x i8
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i8_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv16i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1556,8 +1556,8 @@ define <vscale x 16 x i8> @vp_cttz_zero_undef_nxv16i8_unmasked(<vscale x 16 x i8
ret <vscale x 16 x i8> %v
}
-define <vscale x 32 x i8> @vp_cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv32i8:
+define <vscale x 32 x i8> @vp_cttz_zero_poison_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vadd.vi v12, v8, -1
@@ -1577,7 +1577,7 @@ define <vscale x 32 x i8> @vp_cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va, <v
; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv32i8:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv32i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1586,8 +1586,8 @@ define <vscale x 32 x i8> @vp_cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va, <v
ret <vscale x 32 x i8> %v
}
-define <vscale x 32 x i8> @vp_cttz_zero_undef_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv32i8_unmasked:
+define <vscale x 32 x i8> @vp_cttz_zero_poison_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv32i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vadd.vi v12, v8, -1
@@ -1607,7 +1607,7 @@ define <vscale x 32 x i8> @vp_cttz_zero_undef_nxv32i8_unmasked(<vscale x 32 x i8
; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv32i8_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv32i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1616,8 +1616,8 @@ define <vscale x 32 x i8> @vp_cttz_zero_undef_nxv32i8_unmasked(<vscale x 32 x i8
ret <vscale x 32 x i8> %v
}
-define <vscale x 64 x i8> @vp_cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv64i8:
+define <vscale x 64 x i8> @vp_cttz_zero_poison_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v8, -1
@@ -1637,7 +1637,7 @@ define <vscale x 64 x i8> @vp_cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va, <v
; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv64i8:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv64i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1646,8 +1646,8 @@ define <vscale x 64 x i8> @vp_cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va, <v
ret <vscale x 64 x i8> %v
}
-define <vscale x 64 x i8> @vp_cttz_zero_undef_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv64i8_unmasked:
+define <vscale x 64 x i8> @vp_cttz_zero_poison_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv64i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v8, -1
@@ -1667,7 +1667,7 @@ define <vscale x 64 x i8> @vp_cttz_zero_undef_nxv64i8_unmasked(<vscale x 64 x i8
; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv64i8_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv64i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1676,8 +1676,8 @@ define <vscale x 64 x i8> @vp_cttz_zero_undef_nxv64i8_unmasked(<vscale x 64 x i8
ret <vscale x 64 x i8> %v
}
-define <vscale x 1 x i16> @vp_cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv1i16:
+define <vscale x 1 x i16> @vp_cttz_zero_poison_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1688,7 +1688,7 @@ define <vscale x 1 x i16> @vp_cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va, <v
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i16:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv1i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1697,8 +1697,8 @@ define <vscale x 1 x i16> @vp_cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va, <v
ret <vscale x 1 x i16> %v
}
-define <vscale x 1 x i16> @vp_cttz_zero_undef_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv1i16_unmasked:
+define <vscale x 1 x i16> @vp_cttz_zero_poison_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv1i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1709,7 +1709,7 @@ define <vscale x 1 x i16> @vp_cttz_zero_undef_nxv1i16_unmasked(<vscale x 1 x i16
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i16_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv1i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1718,8 +1718,8 @@ define <vscale x 1 x i16> @vp_cttz_zero_undef_nxv1i16_unmasked(<vscale x 1 x i16
ret <vscale x 1 x i16> %v
}
-define <vscale x 2 x i16> @vp_cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv2i16:
+define <vscale x 2 x i16> @vp_cttz_zero_poison_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1730,7 +1730,7 @@ define <vscale x 2 x i16> @vp_cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va, <v
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i16:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv2i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1739,8 +1739,8 @@ define <vscale x 2 x i16> @vp_cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va, <v
ret <vscale x 2 x i16> %v
}
-define <vscale x 2 x i16> @vp_cttz_zero_undef_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv2i16_unmasked:
+define <vscale x 2 x i16> @vp_cttz_zero_poison_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv2i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1751,7 +1751,7 @@ define <vscale x 2 x i16> @vp_cttz_zero_undef_nxv2i16_unmasked(<vscale x 2 x i16
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i16_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv2i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1760,8 +1760,8 @@ define <vscale x 2 x i16> @vp_cttz_zero_undef_nxv2i16_unmasked(<vscale x 2 x i16
ret <vscale x 2 x i16> %v
}
-define <vscale x 4 x i16> @vp_cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv4i16:
+define <vscale x 4 x i16> @vp_cttz_zero_poison_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1772,7 +1772,7 @@ define <vscale x 4 x i16> @vp_cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va, <v
; CHECK-NEXT: vsub.vx v8, v10, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i16:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv4i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1781,8 +1781,8 @@ define <vscale x 4 x i16> @vp_cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va, <v
ret <vscale x 4 x i16> %v
}
-define <vscale x 4 x i16> @vp_cttz_zero_undef_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv4i16_unmasked:
+define <vscale x 4 x i16> @vp_cttz_zero_poison_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv4i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1793,7 +1793,7 @@ define <vscale x 4 x i16> @vp_cttz_zero_undef_nxv4i16_unmasked(<vscale x 4 x i16
; CHECK-NEXT: vsub.vx v8, v10, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i16_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv4i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1802,8 +1802,8 @@ define <vscale x 4 x i16> @vp_cttz_zero_undef_nxv4i16_unmasked(<vscale x 4 x i16
ret <vscale x 4 x i16> %v
}
-define <vscale x 8 x i16> @vp_cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv8i16:
+define <vscale x 8 x i16> @vp_cttz_zero_poison_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
@@ -1814,7 +1814,7 @@ define <vscale x 8 x i16> @vp_cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va, <v
; CHECK-NEXT: vsub.vx v8, v12, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i16:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv8i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1823,8 +1823,8 @@ define <vscale x 8 x i16> @vp_cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va, <v
ret <vscale x 8 x i16> %v
}
-define <vscale x 8 x i16> @vp_cttz_zero_undef_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv8i16_unmasked:
+define <vscale x 8 x i16> @vp_cttz_zero_poison_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv8i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
@@ -1835,7 +1835,7 @@ define <vscale x 8 x i16> @vp_cttz_zero_undef_nxv8i16_unmasked(<vscale x 8 x i16
; CHECK-NEXT: vsub.vx v8, v12, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i16_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv8i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1844,8 +1844,8 @@ define <vscale x 8 x i16> @vp_cttz_zero_undef_nxv8i16_unmasked(<vscale x 8 x i16
ret <vscale x 8 x i16> %v
}
-define <vscale x 16 x i16> @vp_cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv16i16:
+define <vscale x 16 x i16> @vp_cttz_zero_poison_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
@@ -1856,7 +1856,7 @@ define <vscale x 16 x i16> @vp_cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va,
; CHECK-NEXT: vsub.vx v8, v16, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i16:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv16i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1865,8 +1865,8 @@ define <vscale x 16 x i16> @vp_cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va,
ret <vscale x 16 x i16> %v
}
-define <vscale x 16 x i16> @vp_cttz_zero_undef_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv16i16_unmasked:
+define <vscale x 16 x i16> @vp_cttz_zero_poison_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv16i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
@@ -1877,7 +1877,7 @@ define <vscale x 16 x i16> @vp_cttz_zero_undef_nxv16i16_unmasked(<vscale x 16 x
; CHECK-NEXT: vsub.vx v8, v16, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i16_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv16i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1886,8 +1886,8 @@ define <vscale x 16 x i16> @vp_cttz_zero_undef_nxv16i16_unmasked(<vscale x 16 x
ret <vscale x 16 x i16> %v
}
-define <vscale x 32 x i16> @vp_cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv32i16:
+define <vscale x 32 x i16> @vp_cttz_zero_poison_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v8, -1
@@ -1914,7 +1914,7 @@ define <vscale x 32 x i16> @vp_cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va,
; CHECK-NEXT: vsrl.vi v8, v8, 8
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv32i16:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv32i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1923,8 +1923,8 @@ define <vscale x 32 x i16> @vp_cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va,
ret <vscale x 32 x i16> %v
}
-define <vscale x 32 x i16> @vp_cttz_zero_undef_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv32i16_unmasked:
+define <vscale x 32 x i16> @vp_cttz_zero_poison_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv32i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v8, -1
@@ -1951,7 +1951,7 @@ define <vscale x 32 x i16> @vp_cttz_zero_undef_nxv32i16_unmasked(<vscale x 32 x
; CHECK-NEXT: vsrl.vi v8, v8, 8
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv32i16_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv32i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1960,8 +1960,8 @@ define <vscale x 32 x i16> @vp_cttz_zero_undef_nxv32i16_unmasked(<vscale x 32 x
ret <vscale x 32 x i16> %v
}
-define <vscale x 1 x i32> @vp_cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv1i32:
+define <vscale x 1 x i32> @vp_cttz_zero_poison_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1973,7 +1973,7 @@ define <vscale x 1 x i32> @vp_cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va, <v
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i32:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv1i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -1982,8 +1982,8 @@ define <vscale x 1 x i32> @vp_cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va, <v
ret <vscale x 1 x i32> %v
}
-define <vscale x 1 x i32> @vp_cttz_zero_undef_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv1i32_unmasked:
+define <vscale x 1 x i32> @vp_cttz_zero_poison_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv1i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1995,7 +1995,7 @@ define <vscale x 1 x i32> @vp_cttz_zero_undef_nxv1i32_unmasked(<vscale x 1 x i32
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i32_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv1i32_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2004,8 +2004,8 @@ define <vscale x 1 x i32> @vp_cttz_zero_undef_nxv1i32_unmasked(<vscale x 1 x i32
ret <vscale x 1 x i32> %v
}
-define <vscale x 2 x i32> @vp_cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv2i32:
+define <vscale x 2 x i32> @vp_cttz_zero_poison_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -2017,7 +2017,7 @@ define <vscale x 2 x i32> @vp_cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va, <v
; CHECK-NEXT: vsub.vx v8, v10, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i32:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv2i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2026,8 +2026,8 @@ define <vscale x 2 x i32> @vp_cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va, <v
ret <vscale x 2 x i32> %v
}
-define <vscale x 2 x i32> @vp_cttz_zero_undef_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv2i32_unmasked:
+define <vscale x 2 x i32> @vp_cttz_zero_poison_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv2i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -2039,7 +2039,7 @@ define <vscale x 2 x i32> @vp_cttz_zero_undef_nxv2i32_unmasked(<vscale x 2 x i32
; CHECK-NEXT: vsub.vx v8, v10, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i32_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv2i32_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2048,8 +2048,8 @@ define <vscale x 2 x i32> @vp_cttz_zero_undef_nxv2i32_unmasked(<vscale x 2 x i32
ret <vscale x 2 x i32> %v
}
-define <vscale x 4 x i32> @vp_cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv4i32:
+define <vscale x 4 x i32> @vp_cttz_zero_poison_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
@@ -2061,7 +2061,7 @@ define <vscale x 4 x i32> @vp_cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va, <v
; CHECK-NEXT: vsub.vx v8, v12, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i32:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv4i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2070,8 +2070,8 @@ define <vscale x 4 x i32> @vp_cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va, <v
ret <vscale x 4 x i32> %v
}
-define <vscale x 4 x i32> @vp_cttz_zero_undef_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv4i32_unmasked:
+define <vscale x 4 x i32> @vp_cttz_zero_poison_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv4i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
@@ -2083,7 +2083,7 @@ define <vscale x 4 x i32> @vp_cttz_zero_undef_nxv4i32_unmasked(<vscale x 4 x i32
; CHECK-NEXT: vsub.vx v8, v12, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i32_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv4i32_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2092,8 +2092,8 @@ define <vscale x 4 x i32> @vp_cttz_zero_undef_nxv4i32_unmasked(<vscale x 4 x i32
ret <vscale x 4 x i32> %v
}
-define <vscale x 8 x i32> @vp_cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv8i32:
+define <vscale x 8 x i32> @vp_cttz_zero_poison_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
@@ -2105,7 +2105,7 @@ define <vscale x 8 x i32> @vp_cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va, <v
; CHECK-NEXT: vsub.vx v8, v16, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i32:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv8i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2114,8 +2114,8 @@ define <vscale x 8 x i32> @vp_cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va, <v
ret <vscale x 8 x i32> %v
}
-define <vscale x 8 x i32> @vp_cttz_zero_undef_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv8i32_unmasked:
+define <vscale x 8 x i32> @vp_cttz_zero_poison_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv8i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
@@ -2127,7 +2127,7 @@ define <vscale x 8 x i32> @vp_cttz_zero_undef_nxv8i32_unmasked(<vscale x 8 x i32
; CHECK-NEXT: vsub.vx v8, v16, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i32_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv8i32_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2136,8 +2136,8 @@ define <vscale x 8 x i32> @vp_cttz_zero_undef_nxv8i32_unmasked(<vscale x 8 x i32
ret <vscale x 8 x i32> %v
}
-define <vscale x 16 x i32> @vp_cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv16i32:
+define <vscale x 16 x i32> @vp_cttz_zero_poison_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
@@ -2150,7 +2150,7 @@ define <vscale x 16 x i32> @vp_cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va,
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i32:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv16i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2159,8 +2159,8 @@ define <vscale x 16 x i32> @vp_cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va,
ret <vscale x 16 x i32> %v
}
-define <vscale x 16 x i32> @vp_cttz_zero_undef_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv16i32_unmasked:
+define <vscale x 16 x i32> @vp_cttz_zero_poison_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv16i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
@@ -2173,7 +2173,7 @@ define <vscale x 16 x i32> @vp_cttz_zero_undef_nxv16i32_unmasked(<vscale x 16 x
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i32_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv16i32_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2182,8 +2182,8 @@ define <vscale x 16 x i32> @vp_cttz_zero_undef_nxv16i32_unmasked(<vscale x 16 x
ret <vscale x 16 x i32> %v
}
-define <vscale x 1 x i64> @vp_cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv1i64:
+define <vscale x 1 x i64> @vp_cttz_zero_poison_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -2197,7 +2197,7 @@ define <vscale x 1 x i64> @vp_cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va, <v
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i64:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv1i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2206,8 +2206,8 @@ define <vscale x 1 x i64> @vp_cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va, <v
ret <vscale x 1 x i64> %v
}
-define <vscale x 1 x i64> @vp_cttz_zero_undef_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv1i64_unmasked:
+define <vscale x 1 x i64> @vp_cttz_zero_poison_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv1i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -2221,7 +2221,7 @@ define <vscale x 1 x i64> @vp_cttz_zero_undef_nxv1i64_unmasked(<vscale x 1 x i64
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i64_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv1i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2230,8 +2230,8 @@ define <vscale x 1 x i64> @vp_cttz_zero_undef_nxv1i64_unmasked(<vscale x 1 x i64
ret <vscale x 1 x i64> %v
}
-define <vscale x 2 x i64> @vp_cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv2i64:
+define <vscale x 2 x i64> @vp_cttz_zero_poison_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
@@ -2245,7 +2245,7 @@ define <vscale x 2 x i64> @vp_cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va, <v
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i64:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv2i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2254,8 +2254,8 @@ define <vscale x 2 x i64> @vp_cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va, <v
ret <vscale x 2 x i64> %v
}
-define <vscale x 2 x i64> @vp_cttz_zero_undef_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv2i64_unmasked:
+define <vscale x 2 x i64> @vp_cttz_zero_poison_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv2i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
@@ -2269,7 +2269,7 @@ define <vscale x 2 x i64> @vp_cttz_zero_undef_nxv2i64_unmasked(<vscale x 2 x i64
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i64_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv2i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2278,8 +2278,8 @@ define <vscale x 2 x i64> @vp_cttz_zero_undef_nxv2i64_unmasked(<vscale x 2 x i64
ret <vscale x 2 x i64> %v
}
-define <vscale x 4 x i64> @vp_cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv4i64:
+define <vscale x 4 x i64> @vp_cttz_zero_poison_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
@@ -2293,7 +2293,7 @@ define <vscale x 4 x i64> @vp_cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va, <v
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i64:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv4i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2302,8 +2302,8 @@ define <vscale x 4 x i64> @vp_cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va, <v
ret <vscale x 4 x i64> %v
}
-define <vscale x 4 x i64> @vp_cttz_zero_undef_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv4i64_unmasked:
+define <vscale x 4 x i64> @vp_cttz_zero_poison_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv4i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
@@ -2317,7 +2317,7 @@ define <vscale x 4 x i64> @vp_cttz_zero_undef_nxv4i64_unmasked(<vscale x 4 x i64
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i64_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv4i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2326,8 +2326,8 @@ define <vscale x 4 x i64> @vp_cttz_zero_undef_nxv4i64_unmasked(<vscale x 4 x i64
ret <vscale x 4 x i64> %v
}
-define <vscale x 7 x i64> @vp_cttz_zero_undef_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv7i64:
+define <vscale x 7 x i64> @vp_cttz_zero_poison_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv7i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
@@ -2341,7 +2341,7 @@ define <vscale x 7 x i64> @vp_cttz_zero_undef_nxv7i64(<vscale x 7 x i64> %va, <v
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv7i64:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv7i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2350,8 +2350,8 @@ define <vscale x 7 x i64> @vp_cttz_zero_undef_nxv7i64(<vscale x 7 x i64> %va, <v
ret <vscale x 7 x i64> %v
}
-define <vscale x 7 x i64> @vp_cttz_zero_undef_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv7i64_unmasked:
+define <vscale x 7 x i64> @vp_cttz_zero_poison_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv7i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
@@ -2365,7 +2365,7 @@ define <vscale x 7 x i64> @vp_cttz_zero_undef_nxv7i64_unmasked(<vscale x 7 x i64
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv7i64_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv7i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2374,8 +2374,8 @@ define <vscale x 7 x i64> @vp_cttz_zero_undef_nxv7i64_unmasked(<vscale x 7 x i64
ret <vscale x 7 x i64> %v
}
-define <vscale x 8 x i64> @vp_cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv8i64:
+define <vscale x 8 x i64> @vp_cttz_zero_poison_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
@@ -2389,7 +2389,7 @@ define <vscale x 8 x i64> @vp_cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va, <v
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i64:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv8i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2398,8 +2398,8 @@ define <vscale x 8 x i64> @vp_cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va, <v
ret <vscale x 8 x i64> %v
}
-define <vscale x 8 x i64> @vp_cttz_zero_undef_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv8i64_unmasked:
+define <vscale x 8 x i64> @vp_cttz_zero_poison_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv8i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
@@ -2413,7 +2413,7 @@ define <vscale x 8 x i64> @vp_cttz_zero_undef_nxv8i64_unmasked(<vscale x 8 x i64
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i64_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv8i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2422,8 +2422,8 @@ define <vscale x 8 x i64> @vp_cttz_zero_undef_nxv8i64_unmasked(<vscale x 8 x i64
ret <vscale x 8 x i64> %v
}
-define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv16i64:
+define <vscale x 16 x i64> @vp_cttz_zero_poison_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v24, v8, 0
@@ -2442,7 +2442,7 @@ define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64(<vscale x 16 x i64> %va,
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i64:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv16i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2452,8 +2452,8 @@ define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64(<vscale x 16 x i64> %va,
ret <vscale x 16 x i64> %v
}
-define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_nxv16i64_unmasked:
+define <vscale x 16 x i64> @vp_cttz_zero_poison_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_nxv16i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v24, v8, 0
@@ -2472,7 +2472,7 @@ define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64_unmasked(<vscale x 16 x
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i64_unmasked:
+; CHECK-ZVBB-LABEL: vp_cttz_zero_poison_nxv16i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
@@ -2507,8 +2507,8 @@ define <vscale x 1 x i9> @vp_cttz_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1
%v = call <vscale x 1 x i9> @llvm.vp.cttz.nxv1i9(<vscale x 1 x i9> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i9> %v
}
-define <vscale x 1 x i9> @vp_zero_undef_cttz_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_zero_undef_cttz_nxv1i9:
+define <vscale x 1 x i9> @vp_zero_poison_cttz_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_zero_poison_cttz_nxv1i9:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -2519,7 +2519,7 @@ define <vscale x 1 x i9> @vp_zero_undef_cttz_nxv1i9(<vscale x 1 x i9> %va, <vsca
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: vp_zero_undef_cttz_nxv1i9:
+; CHECK-ZVBB-LABEL: vp_zero_poison_cttz_nxv1i9:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
index 31322e4bc9201..d62e281320e6d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
@@ -620,8 +620,8 @@ define <32 x i64> @vp_ctlz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
ret <32 x i64> %v
}
-define <2 x i8> @vp_ctlz_zero_undef_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v2i8:
+define <2 x i8> @vp_ctlz_zero_poison_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vzext.vf2 v9, v8
@@ -636,8 +636,8 @@ define <2 x i8> @vp_ctlz_zero_undef_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext
ret <2 x i8> %v
}
-define <2 x i8> @vp_ctlz_zero_undef_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v2i8_unmasked:
+define <2 x i8> @vp_ctlz_zero_poison_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v2i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vzext.vf2 v9, v8
@@ -652,8 +652,8 @@ define <2 x i8> @vp_ctlz_zero_undef_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl
ret <2 x i8> %v
}
-define <4 x i8> @vp_ctlz_zero_undef_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v4i8:
+define <4 x i8> @vp_ctlz_zero_poison_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vzext.vf2 v9, v8
@@ -668,8 +668,8 @@ define <4 x i8> @vp_ctlz_zero_undef_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext
ret <4 x i8> %v
}
-define <4 x i8> @vp_ctlz_zero_undef_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v4i8_unmasked:
+define <4 x i8> @vp_ctlz_zero_poison_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v4i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vzext.vf2 v9, v8
@@ -684,8 +684,8 @@ define <4 x i8> @vp_ctlz_zero_undef_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl
ret <4 x i8> %v
}
-define <8 x i8> @vp_ctlz_zero_undef_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v8i8:
+define <8 x i8> @vp_ctlz_zero_poison_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8
@@ -700,8 +700,8 @@ define <8 x i8> @vp_ctlz_zero_undef_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext
ret <8 x i8> %v
}
-define <8 x i8> @vp_ctlz_zero_undef_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v8i8_unmasked:
+define <8 x i8> @vp_ctlz_zero_poison_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v8i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8
@@ -716,8 +716,8 @@ define <8 x i8> @vp_ctlz_zero_undef_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl
ret <8 x i8> %v
}
-define <16 x i8> @vp_ctlz_zero_undef_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v16i8:
+define <16 x i8> @vp_ctlz_zero_poison_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v12, v8
@@ -732,8 +732,8 @@ define <16 x i8> @vp_ctlz_zero_undef_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zero
ret <16 x i8> %v
}
-define <16 x i8> @vp_ctlz_zero_undef_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v16i8_unmasked:
+define <16 x i8> @vp_ctlz_zero_poison_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v16i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v12, v8
@@ -748,8 +748,8 @@ define <16 x i8> @vp_ctlz_zero_undef_v16i8_unmasked(<16 x i8> %va, i32 zeroext %
ret <16 x i8> %v
}
-define <2 x i16> @vp_ctlz_zero_undef_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v2i16:
+define <2 x i16> @vp_ctlz_zero_poison_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
@@ -761,8 +761,8 @@ define <2 x i16> @vp_ctlz_zero_undef_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroe
ret <2 x i16> %v
}
-define <2 x i16> @vp_ctlz_zero_undef_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v2i16_unmasked:
+define <2 x i16> @vp_ctlz_zero_poison_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v2i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
@@ -774,8 +774,8 @@ define <2 x i16> @vp_ctlz_zero_undef_v2i16_unmasked(<2 x i16> %va, i32 zeroext %
ret <2 x i16> %v
}
-define <4 x i16> @vp_ctlz_zero_undef_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v4i16:
+define <4 x i16> @vp_ctlz_zero_poison_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
@@ -787,8 +787,8 @@ define <4 x i16> @vp_ctlz_zero_undef_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroe
ret <4 x i16> %v
}
-define <4 x i16> @vp_ctlz_zero_undef_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v4i16_unmasked:
+define <4 x i16> @vp_ctlz_zero_poison_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v4i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
@@ -800,8 +800,8 @@ define <4 x i16> @vp_ctlz_zero_undef_v4i16_unmasked(<4 x i16> %va, i32 zeroext %
ret <4 x i16> %v
}
-define <8 x i16> @vp_ctlz_zero_undef_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v8i16:
+define <8 x i16> @vp_ctlz_zero_poison_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
@@ -813,8 +813,8 @@ define <8 x i16> @vp_ctlz_zero_undef_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroe
ret <8 x i16> %v
}
-define <8 x i16> @vp_ctlz_zero_undef_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v8i16_unmasked:
+define <8 x i16> @vp_ctlz_zero_poison_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v8i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
@@ -826,8 +826,8 @@ define <8 x i16> @vp_ctlz_zero_undef_v8i16_unmasked(<8 x i16> %va, i32 zeroext %
ret <8 x i16> %v
}
-define <16 x i16> @vp_ctlz_zero_undef_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v16i16:
+define <16 x i16> @vp_ctlz_zero_poison_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
@@ -839,8 +839,8 @@ define <16 x i16> @vp_ctlz_zero_undef_v16i16(<16 x i16> %va, <16 x i1> %m, i32 z
ret <16 x i16> %v
}
-define <16 x i16> @vp_ctlz_zero_undef_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v16i16_unmasked:
+define <16 x i16> @vp_ctlz_zero_poison_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v16i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
@@ -852,8 +852,8 @@ define <16 x i16> @vp_ctlz_zero_undef_v16i16_unmasked(<16 x i16> %va, i32 zeroex
ret <16 x i16> %v
}
-define <2 x i32> @vp_ctlz_zero_undef_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v2i32:
+define <2 x i32> @vp_ctlz_zero_poison_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
@@ -866,8 +866,8 @@ define <2 x i32> @vp_ctlz_zero_undef_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroe
ret <2 x i32> %v
}
-define <2 x i32> @vp_ctlz_zero_undef_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v2i32_unmasked:
+define <2 x i32> @vp_ctlz_zero_poison_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v2i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
@@ -880,8 +880,8 @@ define <2 x i32> @vp_ctlz_zero_undef_v2i32_unmasked(<2 x i32> %va, i32 zeroext %
ret <2 x i32> %v
}
-define <4 x i32> @vp_ctlz_zero_undef_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v4i32:
+define <4 x i32> @vp_ctlz_zero_poison_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
@@ -894,8 +894,8 @@ define <4 x i32> @vp_ctlz_zero_undef_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroe
ret <4 x i32> %v
}
-define <4 x i32> @vp_ctlz_zero_undef_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v4i32_unmasked:
+define <4 x i32> @vp_ctlz_zero_poison_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v4i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
@@ -908,8 +908,8 @@ define <4 x i32> @vp_ctlz_zero_undef_v4i32_unmasked(<4 x i32> %va, i32 zeroext %
ret <4 x i32> %v
}
-define <8 x i32> @vp_ctlz_zero_undef_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v8i32:
+define <8 x i32> @vp_ctlz_zero_poison_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
@@ -922,8 +922,8 @@ define <8 x i32> @vp_ctlz_zero_undef_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroe
ret <8 x i32> %v
}
-define <8 x i32> @vp_ctlz_zero_undef_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v8i32_unmasked:
+define <8 x i32> @vp_ctlz_zero_poison_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v8i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
@@ -936,8 +936,8 @@ define <8 x i32> @vp_ctlz_zero_undef_v8i32_unmasked(<8 x i32> %va, i32 zeroext %
ret <8 x i32> %v
}
-define <16 x i32> @vp_ctlz_zero_undef_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v16i32:
+define <16 x i32> @vp_ctlz_zero_poison_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v16, v8
@@ -950,8 +950,8 @@ define <16 x i32> @vp_ctlz_zero_undef_v16i32(<16 x i32> %va, <16 x i1> %m, i32 z
ret <16 x i32> %v
}
-define <16 x i32> @vp_ctlz_zero_undef_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v16i32_unmasked:
+define <16 x i32> @vp_ctlz_zero_poison_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v16i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v16, v8
@@ -964,8 +964,8 @@ define <16 x i32> @vp_ctlz_zero_undef_v16i32_unmasked(<16 x i32> %va, i32 zeroex
ret <16 x i32> %v
}
-define <2 x i64> @vp_ctlz_zero_undef_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v2i64:
+define <2 x i64> @vp_ctlz_zero_poison_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
@@ -980,8 +980,8 @@ define <2 x i64> @vp_ctlz_zero_undef_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroe
ret <2 x i64> %v
}
-define <2 x i64> @vp_ctlz_zero_undef_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v2i64_unmasked:
+define <2 x i64> @vp_ctlz_zero_poison_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v2i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
@@ -996,8 +996,8 @@ define <2 x i64> @vp_ctlz_zero_undef_v2i64_unmasked(<2 x i64> %va, i32 zeroext %
ret <2 x i64> %v
}
-define <4 x i64> @vp_ctlz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v4i64:
+define <4 x i64> @vp_ctlz_zero_poison_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
@@ -1012,8 +1012,8 @@ define <4 x i64> @vp_ctlz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroe
ret <4 x i64> %v
}
-define <4 x i64> @vp_ctlz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v4i64_unmasked:
+define <4 x i64> @vp_ctlz_zero_poison_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v4i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
@@ -1028,8 +1028,8 @@ define <4 x i64> @vp_ctlz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext %
ret <4 x i64> %v
}
-define <8 x i64> @vp_ctlz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v8i64:
+define <8 x i64> @vp_ctlz_zero_poison_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
@@ -1044,8 +1044,8 @@ define <8 x i64> @vp_ctlz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroe
ret <8 x i64> %v
}
-define <8 x i64> @vp_ctlz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v8i64_unmasked:
+define <8 x i64> @vp_ctlz_zero_poison_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v8i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
@@ -1060,8 +1060,8 @@ define <8 x i64> @vp_ctlz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext %
ret <8 x i64> %v
}
-define <15 x i64> @vp_ctlz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v15i64:
+define <15 x i64> @vp_ctlz_zero_poison_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v15i64:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
@@ -1076,8 +1076,8 @@ define <15 x i64> @vp_ctlz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 z
ret <15 x i64> %v
}
-define <15 x i64> @vp_ctlz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v15i64_unmasked:
+define <15 x i64> @vp_ctlz_zero_poison_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v15i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
@@ -1092,8 +1092,8 @@ define <15 x i64> @vp_ctlz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroex
ret <15 x i64> %v
}
-define <16 x i64> @vp_ctlz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v16i64:
+define <16 x i64> @vp_ctlz_zero_poison_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
@@ -1108,8 +1108,8 @@ define <16 x i64> @vp_ctlz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 z
ret <16 x i64> %v
}
-define <16 x i64> @vp_ctlz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v16i64_unmasked:
+define <16 x i64> @vp_ctlz_zero_poison_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v16i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
@@ -1124,8 +1124,8 @@ define <16 x i64> @vp_ctlz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroex
ret <16 x i64> %v
}
-define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v32i64:
+define <32 x i64> @vp_ctlz_zero_poison_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
@@ -1143,8 +1143,8 @@ define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
ret <32 x i64> %v
}
-define <32 x i64> @vp_ctlz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_ctlz_zero_undef_v32i64_unmasked:
+define <32 x i64> @vp_ctlz_zero_poison_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_ctlz_zero_poison_v32i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
index 02e1ec8da49fe..6340f0b71c563 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
@@ -778,8 +778,8 @@ define void @ctlz_v4i64(ptr %x, ptr %y) nounwind {
ret void
}
-define void @ctlz_zero_undef_v16i8(ptr %x, ptr %y) nounwind {
-; RVI-LABEL: ctlz_zero_undef_v16i8:
+define void @ctlz_zero_poison_v16i8(ptr %x, ptr %y) nounwind {
+; RVI-LABEL: ctlz_zero_poison_v16i8:
; RVI: # %bb.0:
; RVI-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RVI-NEXT: vle8.v v8, (a0)
@@ -805,7 +805,7 @@ define void @ctlz_zero_undef_v16i8(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vse8.v v8, (a0)
; RVI-NEXT: ret
;
-; RVF-LABEL: ctlz_zero_undef_v16i8:
+; RVF-LABEL: ctlz_zero_poison_v16i8:
; RVF: # %bb.0:
; RVF-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RVF-NEXT: vle8.v v8, (a0)
@@ -819,7 +819,7 @@ define void @ctlz_zero_undef_v16i8(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vse8.v v8, (a0)
; RVF-NEXT: ret
;
-; RVD-LABEL: ctlz_zero_undef_v16i8:
+; RVD-LABEL: ctlz_zero_poison_v16i8:
; RVD: # %bb.0:
; RVD-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RVD-NEXT: vle8.v v8, (a0)
@@ -833,7 +833,7 @@ define void @ctlz_zero_undef_v16i8(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vse8.v v8, (a0)
; RVD-NEXT: ret
;
-; ZVBB-LABEL: ctlz_zero_undef_v16i8:
+; ZVBB-LABEL: ctlz_zero_poison_v16i8:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; ZVBB-NEXT: vle8.v v8, (a0)
@@ -847,8 +847,8 @@ define void @ctlz_zero_undef_v16i8(ptr %x, ptr %y) nounwind {
ret void
}
-define void @ctlz_zero_undef_v8i16(ptr %x, ptr %y) nounwind {
-; RVI-LABEL: ctlz_zero_undef_v8i16:
+define void @ctlz_zero_poison_v8i16(ptr %x, ptr %y) nounwind {
+; RVI-LABEL: ctlz_zero_poison_v8i16:
; RVI: # %bb.0:
; RVI-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RVI-NEXT: vle16.v v8, (a0)
@@ -883,7 +883,7 @@ define void @ctlz_zero_undef_v8i16(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vse16.v v8, (a0)
; RVI-NEXT: ret
;
-; RVF-LABEL: ctlz_zero_undef_v8i16:
+; RVF-LABEL: ctlz_zero_poison_v8i16:
; RVF: # %bb.0:
; RVF-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RVF-NEXT: vle16.v v10, (a0)
@@ -894,7 +894,7 @@ define void @ctlz_zero_undef_v8i16(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vse16.v v8, (a0)
; RVF-NEXT: ret
;
-; RVD-LABEL: ctlz_zero_undef_v8i16:
+; RVD-LABEL: ctlz_zero_poison_v8i16:
; RVD: # %bb.0:
; RVD-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RVD-NEXT: vle16.v v10, (a0)
@@ -905,7 +905,7 @@ define void @ctlz_zero_undef_v8i16(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vse16.v v8, (a0)
; RVD-NEXT: ret
;
-; ZVBB-LABEL: ctlz_zero_undef_v8i16:
+; ZVBB-LABEL: ctlz_zero_poison_v8i16:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVBB-NEXT: vle16.v v8, (a0)
@@ -919,8 +919,8 @@ define void @ctlz_zero_undef_v8i16(ptr %x, ptr %y) nounwind {
ret void
}
-define void @ctlz_zero_undef_v4i32(ptr %x, ptr %y) nounwind {
-; RVI-LABEL: ctlz_zero_undef_v4i32:
+define void @ctlz_zero_poison_v4i32(ptr %x, ptr %y) nounwind {
+; RVI-LABEL: ctlz_zero_poison_v4i32:
; RVI: # %bb.0:
; RVI-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RVI-NEXT: vle32.v v8, (a0)
@@ -958,7 +958,7 @@ define void @ctlz_zero_undef_v4i32(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vse32.v v8, (a0)
; RVI-NEXT: ret
;
-; RVF-LABEL: ctlz_zero_undef_v4i32:
+; RVF-LABEL: ctlz_zero_poison_v4i32:
; RVF: # %bb.0:
; RVF-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RVF-NEXT: vle32.v v8, (a0)
@@ -971,7 +971,7 @@ define void @ctlz_zero_undef_v4i32(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vse32.v v8, (a0)
; RVF-NEXT: ret
;
-; RVD-LABEL: ctlz_zero_undef_v4i32:
+; RVD-LABEL: ctlz_zero_poison_v4i32:
; RVD: # %bb.0:
; RVD-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RVD-NEXT: vle32.v v10, (a0)
@@ -983,7 +983,7 @@ define void @ctlz_zero_undef_v4i32(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vse32.v v8, (a0)
; RVD-NEXT: ret
;
-; ZVBB-LABEL: ctlz_zero_undef_v4i32:
+; ZVBB-LABEL: ctlz_zero_poison_v4i32:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVBB-NEXT: vle32.v v8, (a0)
@@ -997,8 +997,8 @@ define void @ctlz_zero_undef_v4i32(ptr %x, ptr %y) nounwind {
ret void
}
-define void @ctlz_zero_undef_v2i64(ptr %x, ptr %y) nounwind {
-; RV32I-LABEL: ctlz_zero_undef_v2i64:
+define void @ctlz_zero_poison_v2i64(ptr %x, ptr %y) nounwind {
+; RV32I-LABEL: ctlz_zero_poison_v2i64:
; RV32I: # %bb.0:
; RV32I-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32I-NEXT: vle64.v v8, (a0)
@@ -1052,7 +1052,7 @@ define void @ctlz_zero_undef_v2i64(ptr %x, ptr %y) nounwind {
; RV32I-NEXT: vse64.v v8, (a0)
; RV32I-NEXT: ret
;
-; RV64I-LABEL: ctlz_zero_undef_v2i64:
+; RV64I-LABEL: ctlz_zero_poison_v2i64:
; RV64I: # %bb.0:
; RV64I-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64I-NEXT: vle64.v v8, (a0)
@@ -1102,7 +1102,7 @@ define void @ctlz_zero_undef_v2i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: vse64.v v8, (a0)
; RV64I-NEXT: ret
;
-; RVF-LABEL: ctlz_zero_undef_v2i64:
+; RVF-LABEL: ctlz_zero_poison_v2i64:
; RVF: # %bb.0:
; RVF-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RVF-NEXT: vle64.v v8, (a0)
@@ -1116,7 +1116,7 @@ define void @ctlz_zero_undef_v2i64(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vse64.v v10, (a0)
; RVF-NEXT: ret
;
-; RVD-LABEL: ctlz_zero_undef_v2i64:
+; RVD-LABEL: ctlz_zero_poison_v2i64:
; RVD: # %bb.0:
; RVD-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RVD-NEXT: vle64.v v8, (a0)
@@ -1130,7 +1130,7 @@ define void @ctlz_zero_undef_v2i64(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vse64.v v8, (a0)
; RVD-NEXT: ret
;
-; ZVBB-LABEL: ctlz_zero_undef_v2i64:
+; ZVBB-LABEL: ctlz_zero_poison_v2i64:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; ZVBB-NEXT: vle64.v v8, (a0)
@@ -1144,8 +1144,8 @@ define void @ctlz_zero_undef_v2i64(ptr %x, ptr %y) nounwind {
ret void
}
-define void @ctlz_zero_undef_v32i8(ptr %x, ptr %y) nounwind {
-; RVI-LABEL: ctlz_zero_undef_v32i8:
+define void @ctlz_zero_poison_v32i8(ptr %x, ptr %y) nounwind {
+; RVI-LABEL: ctlz_zero_poison_v32i8:
; RVI: # %bb.0:
; RVI-NEXT: li a1, 32
; RVI-NEXT: vsetvli zero, a1, e8, m2, ta, ma
@@ -1172,7 +1172,7 @@ define void @ctlz_zero_undef_v32i8(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vse8.v v8, (a0)
; RVI-NEXT: ret
;
-; RVF-LABEL: ctlz_zero_undef_v32i8:
+; RVF-LABEL: ctlz_zero_poison_v32i8:
; RVF: # %bb.0:
; RVF-NEXT: li a1, 32
; RVF-NEXT: vsetvli zero, a1, e16, m4, ta, ma
@@ -1187,7 +1187,7 @@ define void @ctlz_zero_undef_v32i8(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vse8.v v8, (a0)
; RVF-NEXT: ret
;
-; RVD-LABEL: ctlz_zero_undef_v32i8:
+; RVD-LABEL: ctlz_zero_poison_v32i8:
; RVD: # %bb.0:
; RVD-NEXT: li a1, 32
; RVD-NEXT: vsetvli zero, a1, e16, m4, ta, ma
@@ -1202,7 +1202,7 @@ define void @ctlz_zero_undef_v32i8(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vse8.v v8, (a0)
; RVD-NEXT: ret
;
-; ZVBB-LABEL: ctlz_zero_undef_v32i8:
+; ZVBB-LABEL: ctlz_zero_poison_v32i8:
; ZVBB: # %bb.0:
; ZVBB-NEXT: li a1, 32
; ZVBB-NEXT: vsetvli zero, a1, e8, m2, ta, ma
@@ -1217,8 +1217,8 @@ define void @ctlz_zero_undef_v32i8(ptr %x, ptr %y) nounwind {
ret void
}
-define void @ctlz_zero_undef_v16i16(ptr %x, ptr %y) nounwind {
-; RVI-LABEL: ctlz_zero_undef_v16i16:
+define void @ctlz_zero_poison_v16i16(ptr %x, ptr %y) nounwind {
+; RVI-LABEL: ctlz_zero_poison_v16i16:
; RVI: # %bb.0:
; RVI-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RVI-NEXT: vle16.v v8, (a0)
@@ -1253,7 +1253,7 @@ define void @ctlz_zero_undef_v16i16(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vse16.v v8, (a0)
; RVI-NEXT: ret
;
-; RVF-LABEL: ctlz_zero_undef_v16i16:
+; RVF-LABEL: ctlz_zero_poison_v16i16:
; RVF: # %bb.0:
; RVF-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RVF-NEXT: vle16.v v12, (a0)
@@ -1264,7 +1264,7 @@ define void @ctlz_zero_undef_v16i16(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vse16.v v8, (a0)
; RVF-NEXT: ret
;
-; RVD-LABEL: ctlz_zero_undef_v16i16:
+; RVD-LABEL: ctlz_zero_poison_v16i16:
; RVD: # %bb.0:
; RVD-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RVD-NEXT: vle16.v v12, (a0)
@@ -1275,7 +1275,7 @@ define void @ctlz_zero_undef_v16i16(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vse16.v v8, (a0)
; RVD-NEXT: ret
;
-; ZVBB-LABEL: ctlz_zero_undef_v16i16:
+; ZVBB-LABEL: ctlz_zero_poison_v16i16:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVBB-NEXT: vle16.v v8, (a0)
@@ -1289,8 +1289,8 @@ define void @ctlz_zero_undef_v16i16(ptr %x, ptr %y) nounwind {
ret void
}
-define void @ctlz_zero_undef_v8i32(ptr %x, ptr %y) nounwind {
-; RVI-LABEL: ctlz_zero_undef_v8i32:
+define void @ctlz_zero_poison_v8i32(ptr %x, ptr %y) nounwind {
+; RVI-LABEL: ctlz_zero_poison_v8i32:
; RVI: # %bb.0:
; RVI-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RVI-NEXT: vle32.v v8, (a0)
@@ -1328,7 +1328,7 @@ define void @ctlz_zero_undef_v8i32(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vse32.v v8, (a0)
; RVI-NEXT: ret
;
-; RVF-LABEL: ctlz_zero_undef_v8i32:
+; RVF-LABEL: ctlz_zero_poison_v8i32:
; RVF: # %bb.0:
; RVF-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RVF-NEXT: vle32.v v8, (a0)
@@ -1341,7 +1341,7 @@ define void @ctlz_zero_undef_v8i32(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vse32.v v8, (a0)
; RVF-NEXT: ret
;
-; RVD-LABEL: ctlz_zero_undef_v8i32:
+; RVD-LABEL: ctlz_zero_poison_v8i32:
; RVD: # %bb.0:
; RVD-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RVD-NEXT: vle32.v v12, (a0)
@@ -1353,7 +1353,7 @@ define void @ctlz_zero_undef_v8i32(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vse32.v v8, (a0)
; RVD-NEXT: ret
;
-; ZVBB-LABEL: ctlz_zero_undef_v8i32:
+; ZVBB-LABEL: ctlz_zero_poison_v8i32:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVBB-NEXT: vle32.v v8, (a0)
@@ -1367,8 +1367,8 @@ define void @ctlz_zero_undef_v8i32(ptr %x, ptr %y) nounwind {
ret void
}
-define void @ctlz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
-; RV32I-LABEL: ctlz_zero_undef_v4i64:
+define void @ctlz_zero_poison_v4i64(ptr %x, ptr %y) nounwind {
+; RV32I-LABEL: ctlz_zero_poison_v4i64:
; RV32I: # %bb.0:
; RV32I-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32I-NEXT: vle64.v v8, (a0)
@@ -1422,7 +1422,7 @@ define void @ctlz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
; RV32I-NEXT: vse64.v v8, (a0)
; RV32I-NEXT: ret
;
-; RV64I-LABEL: ctlz_zero_undef_v4i64:
+; RV64I-LABEL: ctlz_zero_poison_v4i64:
; RV64I: # %bb.0:
; RV64I-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64I-NEXT: vle64.v v8, (a0)
@@ -1472,7 +1472,7 @@ define void @ctlz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: vse64.v v8, (a0)
; RV64I-NEXT: ret
;
-; RVF-LABEL: ctlz_zero_undef_v4i64:
+; RVF-LABEL: ctlz_zero_poison_v4i64:
; RVF: # %bb.0:
; RVF-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RVF-NEXT: vle64.v v8, (a0)
@@ -1486,7 +1486,7 @@ define void @ctlz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vse64.v v8, (a0)
; RVF-NEXT: ret
;
-; RVD-LABEL: ctlz_zero_undef_v4i64:
+; RVD-LABEL: ctlz_zero_poison_v4i64:
; RVD: # %bb.0:
; RVD-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RVD-NEXT: vle64.v v8, (a0)
@@ -1500,7 +1500,7 @@ define void @ctlz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vse64.v v8, (a0)
; RVD-NEXT: ret
;
-; ZVBB-LABEL: ctlz_zero_undef_v4i64:
+; ZVBB-LABEL: ctlz_zero_poison_v4i64:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVBB-NEXT: vle64.v v8, (a0)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
index 0d54224154494..65582b3f5d972 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
@@ -736,8 +736,8 @@ define <32 x i64> @vp_cttz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
ret <32 x i64> %v
}
-define <2 x i8> @vp_cttz_zero_undef_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v2i8:
+define <2 x i8> @vp_cttz_zero_poison_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -755,8 +755,8 @@ define <2 x i8> @vp_cttz_zero_undef_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext
ret <2 x i8> %v
}
-define <2 x i8> @vp_cttz_zero_undef_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v2i8_unmasked:
+define <2 x i8> @vp_cttz_zero_poison_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v2i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -774,8 +774,8 @@ define <2 x i8> @vp_cttz_zero_undef_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl
ret <2 x i8> %v
}
-define <4 x i8> @vp_cttz_zero_undef_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v4i8:
+define <4 x i8> @vp_cttz_zero_poison_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -793,8 +793,8 @@ define <4 x i8> @vp_cttz_zero_undef_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext
ret <4 x i8> %v
}
-define <4 x i8> @vp_cttz_zero_undef_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v4i8_unmasked:
+define <4 x i8> @vp_cttz_zero_poison_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v4i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -812,8 +812,8 @@ define <4 x i8> @vp_cttz_zero_undef_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl
ret <4 x i8> %v
}
-define <8 x i8> @vp_cttz_zero_undef_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v8i8:
+define <8 x i8> @vp_cttz_zero_poison_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -831,8 +831,8 @@ define <8 x i8> @vp_cttz_zero_undef_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext
ret <8 x i8> %v
}
-define <8 x i8> @vp_cttz_zero_undef_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v8i8_unmasked:
+define <8 x i8> @vp_cttz_zero_poison_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v8i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -850,8 +850,8 @@ define <8 x i8> @vp_cttz_zero_undef_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl
ret <8 x i8> %v
}
-define <16 x i8> @vp_cttz_zero_undef_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v16i8:
+define <16 x i8> @vp_cttz_zero_poison_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -869,8 +869,8 @@ define <16 x i8> @vp_cttz_zero_undef_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zero
ret <16 x i8> %v
}
-define <16 x i8> @vp_cttz_zero_undef_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v16i8_unmasked:
+define <16 x i8> @vp_cttz_zero_poison_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v16i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -888,8 +888,8 @@ define <16 x i8> @vp_cttz_zero_undef_v16i8_unmasked(<16 x i8> %va, i32 zeroext %
ret <16 x i8> %v
}
-define <2 x i16> @vp_cttz_zero_undef_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v2i16:
+define <2 x i16> @vp_cttz_zero_poison_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -903,8 +903,8 @@ define <2 x i16> @vp_cttz_zero_undef_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroe
ret <2 x i16> %v
}
-define <2 x i16> @vp_cttz_zero_undef_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v2i16_unmasked:
+define <2 x i16> @vp_cttz_zero_poison_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v2i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -918,8 +918,8 @@ define <2 x i16> @vp_cttz_zero_undef_v2i16_unmasked(<2 x i16> %va, i32 zeroext %
ret <2 x i16> %v
}
-define <4 x i16> @vp_cttz_zero_undef_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v4i16:
+define <4 x i16> @vp_cttz_zero_poison_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -933,8 +933,8 @@ define <4 x i16> @vp_cttz_zero_undef_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroe
ret <4 x i16> %v
}
-define <4 x i16> @vp_cttz_zero_undef_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v4i16_unmasked:
+define <4 x i16> @vp_cttz_zero_poison_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v4i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -948,8 +948,8 @@ define <4 x i16> @vp_cttz_zero_undef_v4i16_unmasked(<4 x i16> %va, i32 zeroext %
ret <4 x i16> %v
}
-define <8 x i16> @vp_cttz_zero_undef_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v8i16:
+define <8 x i16> @vp_cttz_zero_poison_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -963,8 +963,8 @@ define <8 x i16> @vp_cttz_zero_undef_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroe
ret <8 x i16> %v
}
-define <8 x i16> @vp_cttz_zero_undef_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v8i16_unmasked:
+define <8 x i16> @vp_cttz_zero_poison_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v8i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -978,8 +978,8 @@ define <8 x i16> @vp_cttz_zero_undef_v8i16_unmasked(<8 x i16> %va, i32 zeroext %
ret <8 x i16> %v
}
-define <16 x i16> @vp_cttz_zero_undef_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v16i16:
+define <16 x i16> @vp_cttz_zero_poison_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
@@ -993,8 +993,8 @@ define <16 x i16> @vp_cttz_zero_undef_v16i16(<16 x i16> %va, <16 x i1> %m, i32 z
ret <16 x i16> %v
}
-define <16 x i16> @vp_cttz_zero_undef_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v16i16_unmasked:
+define <16 x i16> @vp_cttz_zero_poison_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v16i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
@@ -1008,8 +1008,8 @@ define <16 x i16> @vp_cttz_zero_undef_v16i16_unmasked(<16 x i16> %va, i32 zeroex
ret <16 x i16> %v
}
-define <2 x i32> @vp_cttz_zero_undef_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v2i32:
+define <2 x i32> @vp_cttz_zero_poison_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1024,8 +1024,8 @@ define <2 x i32> @vp_cttz_zero_undef_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroe
ret <2 x i32> %v
}
-define <2 x i32> @vp_cttz_zero_undef_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v2i32_unmasked:
+define <2 x i32> @vp_cttz_zero_poison_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v2i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1040,8 +1040,8 @@ define <2 x i32> @vp_cttz_zero_undef_v2i32_unmasked(<2 x i32> %va, i32 zeroext %
ret <2 x i32> %v
}
-define <4 x i32> @vp_cttz_zero_undef_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v4i32:
+define <4 x i32> @vp_cttz_zero_poison_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1056,8 +1056,8 @@ define <4 x i32> @vp_cttz_zero_undef_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroe
ret <4 x i32> %v
}
-define <4 x i32> @vp_cttz_zero_undef_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v4i32_unmasked:
+define <4 x i32> @vp_cttz_zero_poison_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v4i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1072,8 +1072,8 @@ define <4 x i32> @vp_cttz_zero_undef_v4i32_unmasked(<4 x i32> %va, i32 zeroext %
ret <4 x i32> %v
}
-define <8 x i32> @vp_cttz_zero_undef_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v8i32:
+define <8 x i32> @vp_cttz_zero_poison_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
@@ -1088,8 +1088,8 @@ define <8 x i32> @vp_cttz_zero_undef_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroe
ret <8 x i32> %v
}
-define <8 x i32> @vp_cttz_zero_undef_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v8i32_unmasked:
+define <8 x i32> @vp_cttz_zero_poison_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v8i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
@@ -1104,8 +1104,8 @@ define <8 x i32> @vp_cttz_zero_undef_v8i32_unmasked(<8 x i32> %va, i32 zeroext %
ret <8 x i32> %v
}
-define <16 x i32> @vp_cttz_zero_undef_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v16i32:
+define <16 x i32> @vp_cttz_zero_poison_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
@@ -1120,8 +1120,8 @@ define <16 x i32> @vp_cttz_zero_undef_v16i32(<16 x i32> %va, <16 x i1> %m, i32 z
ret <16 x i32> %v
}
-define <16 x i32> @vp_cttz_zero_undef_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v16i32_unmasked:
+define <16 x i32> @vp_cttz_zero_poison_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v16i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
@@ -1136,8 +1136,8 @@ define <16 x i32> @vp_cttz_zero_undef_v16i32_unmasked(<16 x i32> %va, i32 zeroex
ret <16 x i32> %v
}
-define <2 x i64> @vp_cttz_zero_undef_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v2i64:
+define <2 x i64> @vp_cttz_zero_poison_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1154,8 +1154,8 @@ define <2 x i64> @vp_cttz_zero_undef_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroe
ret <2 x i64> %v
}
-define <2 x i64> @vp_cttz_zero_undef_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v2i64_unmasked:
+define <2 x i64> @vp_cttz_zero_poison_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v2i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
@@ -1172,8 +1172,8 @@ define <2 x i64> @vp_cttz_zero_undef_v2i64_unmasked(<2 x i64> %va, i32 zeroext %
ret <2 x i64> %v
}
-define <4 x i64> @vp_cttz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v4i64:
+define <4 x i64> @vp_cttz_zero_poison_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
@@ -1190,8 +1190,8 @@ define <4 x i64> @vp_cttz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroe
ret <4 x i64> %v
}
-define <4 x i64> @vp_cttz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v4i64_unmasked:
+define <4 x i64> @vp_cttz_zero_poison_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v4i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
@@ -1208,8 +1208,8 @@ define <4 x i64> @vp_cttz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext %
ret <4 x i64> %v
}
-define <8 x i64> @vp_cttz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v8i64:
+define <8 x i64> @vp_cttz_zero_poison_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
@@ -1226,8 +1226,8 @@ define <8 x i64> @vp_cttz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroe
ret <8 x i64> %v
}
-define <8 x i64> @vp_cttz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v8i64_unmasked:
+define <8 x i64> @vp_cttz_zero_poison_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v8i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
@@ -1244,8 +1244,8 @@ define <8 x i64> @vp_cttz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext %
ret <8 x i64> %v
}
-define <15 x i64> @vp_cttz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v15i64:
+define <15 x i64> @vp_cttz_zero_poison_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v15i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
@@ -1262,8 +1262,8 @@ define <15 x i64> @vp_cttz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 z
ret <15 x i64> %v
}
-define <15 x i64> @vp_cttz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v15i64_unmasked:
+define <15 x i64> @vp_cttz_zero_poison_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v15i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
@@ -1280,8 +1280,8 @@ define <15 x i64> @vp_cttz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroex
ret <15 x i64> %v
}
-define <16 x i64> @vp_cttz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v16i64:
+define <16 x i64> @vp_cttz_zero_poison_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
@@ -1298,8 +1298,8 @@ define <16 x i64> @vp_cttz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 z
ret <16 x i64> %v
}
-define <16 x i64> @vp_cttz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v16i64_unmasked:
+define <16 x i64> @vp_cttz_zero_poison_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v16i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
@@ -1316,8 +1316,8 @@ define <16 x i64> @vp_cttz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroex
ret <16 x i64> %v
}
-define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v32i64:
+define <32 x i64> @vp_cttz_zero_poison_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v24, v8, 0
@@ -1339,8 +1339,8 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
ret <32 x i64> %v
}
-define <32 x i64> @vp_cttz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vp_cttz_zero_undef_v32i64_unmasked:
+define <32 x i64> @vp_cttz_zero_poison_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
+; CHECK-LABEL: vp_cttz_zero_poison_v32i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v24, v8, 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
index ad51cab1ba8d2..259561fbfcf4a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
@@ -750,8 +750,8 @@ define void @cttz_v4i64(ptr %x, ptr %y) nounwind {
ret void
}
-define void @cttz_zero_undef_v16i8(ptr %x, ptr %y) nounwind {
-; RVI-LABEL: cttz_zero_undef_v16i8:
+define void @cttz_zero_poison_v16i8(ptr %x, ptr %y) nounwind {
+; RVI-LABEL: cttz_zero_poison_v16i8:
; RVI: # %bb.0:
; RVI-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RVI-NEXT: vle8.v v8, (a0)
@@ -773,7 +773,7 @@ define void @cttz_zero_undef_v16i8(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vse8.v v8, (a0)
; RVI-NEXT: ret
;
-; RVF-LABEL: cttz_zero_undef_v16i8:
+; RVF-LABEL: cttz_zero_poison_v16i8:
; RVF: # %bb.0:
; RVF-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RVF-NEXT: vle8.v v8, (a0)
@@ -790,7 +790,7 @@ define void @cttz_zero_undef_v16i8(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vse8.v v8, (a0)
; RVF-NEXT: ret
;
-; RVD-LABEL: cttz_zero_undef_v16i8:
+; RVD-LABEL: cttz_zero_poison_v16i8:
; RVD: # %bb.0:
; RVD-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RVD-NEXT: vle8.v v8, (a0)
@@ -807,7 +807,7 @@ define void @cttz_zero_undef_v16i8(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vse8.v v8, (a0)
; RVD-NEXT: ret
;
-; ZVBB-LABEL: cttz_zero_undef_v16i8:
+; ZVBB-LABEL: cttz_zero_poison_v16i8:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; ZVBB-NEXT: vle8.v v8, (a0)
@@ -821,8 +821,8 @@ define void @cttz_zero_undef_v16i8(ptr %x, ptr %y) nounwind {
ret void
}
-define void @cttz_zero_undef_v8i16(ptr %x, ptr %y) nounwind {
-; RVI-LABEL: cttz_zero_undef_v8i16:
+define void @cttz_zero_poison_v8i16(ptr %x, ptr %y) nounwind {
+; RVI-LABEL: cttz_zero_poison_v8i16:
; RVI: # %bb.0:
; RVI-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RVI-NEXT: vle16.v v8, (a0)
@@ -851,7 +851,7 @@ define void @cttz_zero_undef_v8i16(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vse16.v v8, (a0)
; RVI-NEXT: ret
;
-; RVF-LABEL: cttz_zero_undef_v8i16:
+; RVF-LABEL: cttz_zero_poison_v8i16:
; RVF: # %bb.0:
; RVF-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RVF-NEXT: vle16.v v8, (a0)
@@ -864,7 +864,7 @@ define void @cttz_zero_undef_v8i16(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vse16.v v8, (a0)
; RVF-NEXT: ret
;
-; RVD-LABEL: cttz_zero_undef_v8i16:
+; RVD-LABEL: cttz_zero_poison_v8i16:
; RVD: # %bb.0:
; RVD-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RVD-NEXT: vle16.v v8, (a0)
@@ -877,7 +877,7 @@ define void @cttz_zero_undef_v8i16(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vse16.v v8, (a0)
; RVD-NEXT: ret
;
-; ZVBB-LABEL: cttz_zero_undef_v8i16:
+; ZVBB-LABEL: cttz_zero_poison_v8i16:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVBB-NEXT: vle16.v v8, (a0)
@@ -891,8 +891,8 @@ define void @cttz_zero_undef_v8i16(ptr %x, ptr %y) nounwind {
ret void
}
-define void @cttz_zero_undef_v4i32(ptr %x, ptr %y) nounwind {
-; RVI-LABEL: cttz_zero_undef_v4i32:
+define void @cttz_zero_poison_v4i32(ptr %x, ptr %y) nounwind {
+; RVI-LABEL: cttz_zero_poison_v4i32:
; RVI: # %bb.0:
; RVI-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RVI-NEXT: vle32.v v8, (a0)
@@ -922,7 +922,7 @@ define void @cttz_zero_undef_v4i32(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vse32.v v8, (a0)
; RVI-NEXT: ret
;
-; RVF-LABEL: cttz_zero_undef_v4i32:
+; RVF-LABEL: cttz_zero_poison_v4i32:
; RVF: # %bb.0:
; RVF-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RVF-NEXT: vle32.v v8, (a0)
@@ -937,7 +937,7 @@ define void @cttz_zero_undef_v4i32(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vse32.v v8, (a0)
; RVF-NEXT: ret
;
-; RVD-LABEL: cttz_zero_undef_v4i32:
+; RVD-LABEL: cttz_zero_poison_v4i32:
; RVD: # %bb.0:
; RVD-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RVD-NEXT: vle32.v v8, (a0)
@@ -951,7 +951,7 @@ define void @cttz_zero_undef_v4i32(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vse32.v v8, (a0)
; RVD-NEXT: ret
;
-; ZVBB-LABEL: cttz_zero_undef_v4i32:
+; ZVBB-LABEL: cttz_zero_poison_v4i32:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVBB-NEXT: vle32.v v8, (a0)
@@ -965,8 +965,8 @@ define void @cttz_zero_undef_v4i32(ptr %x, ptr %y) nounwind {
ret void
}
-define void @cttz_zero_undef_v2i64(ptr %x, ptr %y) nounwind {
-; RV32I-LABEL: cttz_zero_undef_v2i64:
+define void @cttz_zero_poison_v2i64(ptr %x, ptr %y) nounwind {
+; RV32I-LABEL: cttz_zero_poison_v2i64:
; RV32I: # %bb.0:
; RV32I-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32I-NEXT: vle64.v v8, (a0)
@@ -1009,7 +1009,7 @@ define void @cttz_zero_undef_v2i64(ptr %x, ptr %y) nounwind {
; RV32I-NEXT: vse64.v v8, (a0)
; RV32I-NEXT: ret
;
-; RV64I-LABEL: cttz_zero_undef_v2i64:
+; RV64I-LABEL: cttz_zero_poison_v2i64:
; RV64I: # %bb.0:
; RV64I-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64I-NEXT: vle64.v v8, (a0)
@@ -1048,7 +1048,7 @@ define void @cttz_zero_undef_v2i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: vse64.v v8, (a0)
; RV64I-NEXT: ret
;
-; RVF-LABEL: cttz_zero_undef_v2i64:
+; RVF-LABEL: cttz_zero_poison_v2i64:
; RVF: # %bb.0:
; RVF-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RVF-NEXT: vle64.v v8, (a0)
@@ -1064,7 +1064,7 @@ define void @cttz_zero_undef_v2i64(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vse64.v v9, (a0)
; RVF-NEXT: ret
;
-; RVD-LABEL: cttz_zero_undef_v2i64:
+; RVD-LABEL: cttz_zero_poison_v2i64:
; RVD: # %bb.0:
; RVD-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RVD-NEXT: vle64.v v8, (a0)
@@ -1080,7 +1080,7 @@ define void @cttz_zero_undef_v2i64(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vse64.v v8, (a0)
; RVD-NEXT: ret
;
-; ZVBB-LABEL: cttz_zero_undef_v2i64:
+; ZVBB-LABEL: cttz_zero_poison_v2i64:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; ZVBB-NEXT: vle64.v v8, (a0)
@@ -1094,8 +1094,8 @@ define void @cttz_zero_undef_v2i64(ptr %x, ptr %y) nounwind {
ret void
}
-define void @cttz_zero_undef_v32i8(ptr %x, ptr %y) nounwind {
-; RVI-LABEL: cttz_zero_undef_v32i8:
+define void @cttz_zero_poison_v32i8(ptr %x, ptr %y) nounwind {
+; RVI-LABEL: cttz_zero_poison_v32i8:
; RVI: # %bb.0:
; RVI-NEXT: li a1, 32
; RVI-NEXT: vsetvli zero, a1, e8, m2, ta, ma
@@ -1118,7 +1118,7 @@ define void @cttz_zero_undef_v32i8(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vse8.v v8, (a0)
; RVI-NEXT: ret
;
-; RVF-LABEL: cttz_zero_undef_v32i8:
+; RVF-LABEL: cttz_zero_poison_v32i8:
; RVF: # %bb.0:
; RVF-NEXT: li a1, 32
; RVF-NEXT: vsetvli zero, a1, e8, m2, ta, ma
@@ -1136,7 +1136,7 @@ define void @cttz_zero_undef_v32i8(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vse8.v v8, (a0)
; RVF-NEXT: ret
;
-; RVD-LABEL: cttz_zero_undef_v32i8:
+; RVD-LABEL: cttz_zero_poison_v32i8:
; RVD: # %bb.0:
; RVD-NEXT: li a1, 32
; RVD-NEXT: vsetvli zero, a1, e8, m2, ta, ma
@@ -1154,7 +1154,7 @@ define void @cttz_zero_undef_v32i8(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vse8.v v8, (a0)
; RVD-NEXT: ret
;
-; ZVBB-LABEL: cttz_zero_undef_v32i8:
+; ZVBB-LABEL: cttz_zero_poison_v32i8:
; ZVBB: # %bb.0:
; ZVBB-NEXT: li a1, 32
; ZVBB-NEXT: vsetvli zero, a1, e8, m2, ta, ma
@@ -1169,8 +1169,8 @@ define void @cttz_zero_undef_v32i8(ptr %x, ptr %y) nounwind {
ret void
}
-define void @cttz_zero_undef_v16i16(ptr %x, ptr %y) nounwind {
-; RVI-LABEL: cttz_zero_undef_v16i16:
+define void @cttz_zero_poison_v16i16(ptr %x, ptr %y) nounwind {
+; RVI-LABEL: cttz_zero_poison_v16i16:
; RVI: # %bb.0:
; RVI-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RVI-NEXT: vle16.v v8, (a0)
@@ -1199,7 +1199,7 @@ define void @cttz_zero_undef_v16i16(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vse16.v v8, (a0)
; RVI-NEXT: ret
;
-; RVF-LABEL: cttz_zero_undef_v16i16:
+; RVF-LABEL: cttz_zero_poison_v16i16:
; RVF: # %bb.0:
; RVF-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RVF-NEXT: vle16.v v8, (a0)
@@ -1212,7 +1212,7 @@ define void @cttz_zero_undef_v16i16(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vse16.v v8, (a0)
; RVF-NEXT: ret
;
-; RVD-LABEL: cttz_zero_undef_v16i16:
+; RVD-LABEL: cttz_zero_poison_v16i16:
; RVD: # %bb.0:
; RVD-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RVD-NEXT: vle16.v v8, (a0)
@@ -1225,7 +1225,7 @@ define void @cttz_zero_undef_v16i16(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vse16.v v8, (a0)
; RVD-NEXT: ret
;
-; ZVBB-LABEL: cttz_zero_undef_v16i16:
+; ZVBB-LABEL: cttz_zero_poison_v16i16:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVBB-NEXT: vle16.v v8, (a0)
@@ -1239,8 +1239,8 @@ define void @cttz_zero_undef_v16i16(ptr %x, ptr %y) nounwind {
ret void
}
-define void @cttz_zero_undef_v8i32(ptr %x, ptr %y) nounwind {
-; RVI-LABEL: cttz_zero_undef_v8i32:
+define void @cttz_zero_poison_v8i32(ptr %x, ptr %y) nounwind {
+; RVI-LABEL: cttz_zero_poison_v8i32:
; RVI: # %bb.0:
; RVI-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RVI-NEXT: vle32.v v8, (a0)
@@ -1270,7 +1270,7 @@ define void @cttz_zero_undef_v8i32(ptr %x, ptr %y) nounwind {
; RVI-NEXT: vse32.v v8, (a0)
; RVI-NEXT: ret
;
-; RVF-LABEL: cttz_zero_undef_v8i32:
+; RVF-LABEL: cttz_zero_poison_v8i32:
; RVF: # %bb.0:
; RVF-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RVF-NEXT: vle32.v v8, (a0)
@@ -1285,7 +1285,7 @@ define void @cttz_zero_undef_v8i32(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vse32.v v8, (a0)
; RVF-NEXT: ret
;
-; RVD-LABEL: cttz_zero_undef_v8i32:
+; RVD-LABEL: cttz_zero_poison_v8i32:
; RVD: # %bb.0:
; RVD-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RVD-NEXT: vle32.v v8, (a0)
@@ -1299,7 +1299,7 @@ define void @cttz_zero_undef_v8i32(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vse32.v v8, (a0)
; RVD-NEXT: ret
;
-; ZVBB-LABEL: cttz_zero_undef_v8i32:
+; ZVBB-LABEL: cttz_zero_poison_v8i32:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVBB-NEXT: vle32.v v8, (a0)
@@ -1313,8 +1313,8 @@ define void @cttz_zero_undef_v8i32(ptr %x, ptr %y) nounwind {
ret void
}
-define void @cttz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
-; RV32I-LABEL: cttz_zero_undef_v4i64:
+define void @cttz_zero_poison_v4i64(ptr %x, ptr %y) nounwind {
+; RV32I-LABEL: cttz_zero_poison_v4i64:
; RV32I: # %bb.0:
; RV32I-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32I-NEXT: vle64.v v8, (a0)
@@ -1357,7 +1357,7 @@ define void @cttz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
; RV32I-NEXT: vse64.v v8, (a0)
; RV32I-NEXT: ret
;
-; RV64I-LABEL: cttz_zero_undef_v4i64:
+; RV64I-LABEL: cttz_zero_poison_v4i64:
; RV64I: # %bb.0:
; RV64I-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64I-NEXT: vle64.v v8, (a0)
@@ -1396,7 +1396,7 @@ define void @cttz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: vse64.v v8, (a0)
; RV64I-NEXT: ret
;
-; RVF-LABEL: cttz_zero_undef_v4i64:
+; RVF-LABEL: cttz_zero_poison_v4i64:
; RVF: # %bb.0:
; RVF-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RVF-NEXT: vle64.v v8, (a0)
@@ -1412,7 +1412,7 @@ define void @cttz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vse64.v v8, (a0)
; RVF-NEXT: ret
;
-; RVD-LABEL: cttz_zero_undef_v4i64:
+; RVD-LABEL: cttz_zero_poison_v4i64:
; RVD: # %bb.0:
; RVD-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RVD-NEXT: vle64.v v8, (a0)
@@ -1428,7 +1428,7 @@ define void @cttz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vse64.v v8, (a0)
; RVD-NEXT: ret
;
-; ZVBB-LABEL: cttz_zero_undef_v4i64:
+; ZVBB-LABEL: cttz_zero_poison_v4i64:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVBB-NEXT: vle64.v v8, (a0)
diff --git a/llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll b/llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll
index 9687dced7eb2e..7778f127dea80 100644
--- a/llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll
@@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s
; Use cttz to test if we properly prove never-zero. There is a very
-; simple transform from cttz -> cttz_zero_undef if its operand is
+; simple transform from cttz -> cttz_zero_poison if its operand is
; known never zero.
; Even without vscale_range, vscale is always guaranteed to be non-zero.
diff --git a/llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll b/llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
index a25ed44b805d1..2080bfd0cb518 100644
--- a/llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
+++ b/llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
@@ -225,8 +225,8 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
ret i64 %tmp
}
-define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
-; RV32I-LABEL: test_cttz_i8_zero_undef:
+define i8 @test_cttz_i8_zero_poison(i8 %a) nounwind {
+; RV32I-LABEL: test_cttz_i8_zero_poison:
; RV32I: # %bb.0:
; RV32I-NEXT: not a1, a0
; RV32I-NEXT: addi a1, a1, -1
@@ -243,13 +243,13 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
; RV32I-NEXT: andi a0, a0, 15
; RV32I-NEXT: ret
;
-; RV32ZBB-LABEL: test_cttz_i8_zero_undef:
+; RV32ZBB-LABEL: test_cttz_i8_zero_poison:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: not a0, a0
; RV32ZBB-NEXT: ctz a0, a0
; RV32ZBB-NEXT: ret
;
-; RV32ZBBXQCIBM-LABEL: test_cttz_i8_zero_undef:
+; RV32ZBBXQCIBM-LABEL: test_cttz_i8_zero_poison:
; RV32ZBBXQCIBM: # %bb.0:
; RV32ZBBXQCIBM-NEXT: qc.cto a0, a0
; RV32ZBBXQCIBM-NEXT: ret
@@ -258,8 +258,8 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
ret i8 %tmp
}
-define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
-; RV32I-LABEL: test_cttz_i16_zero_undef:
+define i16 @test_cttz_i16_zero_poison(i16 %a) nounwind {
+; RV32I-LABEL: test_cttz_i16_zero_poison:
; RV32I: # %bb.0:
; RV32I-NEXT: not a1, a0
; RV32I-NEXT: lui a2, 5
@@ -283,13 +283,13 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32ZBB-LABEL: test_cttz_i16_zero_undef:
+; RV32ZBB-LABEL: test_cttz_i16_zero_poison:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: not a0, a0
; RV32ZBB-NEXT: ctz a0, a0
; RV32ZBB-NEXT: ret
;
-; RV32ZBBXQCIBM-LABEL: test_cttz_i16_zero_undef:
+; RV32ZBBXQCIBM-LABEL: test_cttz_i16_zero_poison:
; RV32ZBBXQCIBM: # %bb.0:
; RV32ZBBXQCIBM-NEXT: qc.cto a0, a0
; RV32ZBBXQCIBM-NEXT: ret
@@ -298,8 +298,8 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
ret i16 %tmp
}
-define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
-; RV32I-LABEL: test_cttz_i32_zero_undef:
+define i32 @test_cttz_i32_zero_poison(i32 %a) nounwind {
+; RV32I-LABEL: test_cttz_i32_zero_poison:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
@@ -318,13 +318,13 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32ZBB-LABEL: test_cttz_i32_zero_undef:
+; RV32ZBB-LABEL: test_cttz_i32_zero_poison:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: not a0, a0
; RV32ZBB-NEXT: ctz a0, a0
; RV32ZBB-NEXT: ret
;
-; RV32ZBBXQCIBM-LABEL: test_cttz_i32_zero_undef:
+; RV32ZBBXQCIBM-LABEL: test_cttz_i32_zero_poison:
; RV32ZBBXQCIBM: # %bb.0:
; RV32ZBBXQCIBM-NEXT: qc.cto a0, a0
; RV32ZBBXQCIBM-NEXT: ret
@@ -333,8 +333,8 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
ret i32 %tmp
}
-define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
-; RV32I-LABEL: test_cttz_i64_zero_undef:
+define i64 @test_cttz_i64_zero_poison(i64 %a) nounwind {
+; RV32I-LABEL: test_cttz_i64_zero_poison:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
@@ -380,7 +380,7 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
-; RV32ZBB-LABEL: test_cttz_i64_zero_undef:
+; RV32ZBB-LABEL: test_cttz_i64_zero_poison:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: not a0, a0
; RV32ZBB-NEXT: bnez a0, .LBB7_2
@@ -395,7 +395,7 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32ZBB-NEXT: li a1, 0
; RV32ZBB-NEXT: ret
;
-; RV32ZBBXQCIBM-LABEL: test_cttz_i64_zero_undef:
+; RV32ZBBXQCIBM-LABEL: test_cttz_i64_zero_poison:
; RV32ZBBXQCIBM: # %bb.0:
; RV32ZBBXQCIBM-NEXT: not a2, a0
; RV32ZBBXQCIBM-NEXT: bnez a2, .LBB7_2
@@ -690,8 +690,8 @@ define i64 @test_ctlz_i64(i64 %a) nounwind {
ret i64 %tmp
}
-define i8 @test_ctlz_i8_zero_undef(i8 %a) nounwind {
-; RV32I-LABEL: test_ctlz_i8_zero_undef:
+define i8 @test_ctlz_i8_zero_poison(i8 %a) nounwind {
+; RV32I-LABEL: test_ctlz_i8_zero_poison:
; RV32I: # %bb.0:
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: slli a1, a0, 24
@@ -716,14 +716,14 @@ define i8 @test_ctlz_i8_zero_undef(i8 %a) nounwind {
; RV32I-NEXT: andi a0, a0, 15
; RV32I-NEXT: ret
;
-; RV32ZBB-LABEL: test_ctlz_i8_zero_undef:
+; RV32ZBB-LABEL: test_ctlz_i8_zero_poison:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: not a0, a0
; RV32ZBB-NEXT: slli a0, a0, 24
; RV32ZBB-NEXT: clz a0, a0
; RV32ZBB-NEXT: ret
;
-; RV32ZBBXQCIBM-LABEL: test_ctlz_i8_zero_undef:
+; RV32ZBBXQCIBM-LABEL: test_ctlz_i8_zero_poison:
; RV32ZBBXQCIBM: # %bb.0:
; RV32ZBBXQCIBM-NEXT: not a0, a0
; RV32ZBBXQCIBM-NEXT: slli a0, a0, 24
@@ -734,8 +734,8 @@ define i8 @test_ctlz_i8_zero_undef(i8 %a) nounwind {
ret i8 %tmp
}
-define i16 @test_ctlz_i16_zero_undef(i16 %a) nounwind {
-; RV32I-LABEL: test_ctlz_i16_zero_undef:
+define i16 @test_ctlz_i16_zero_poison(i16 %a) nounwind {
+; RV32I-LABEL: test_ctlz_i16_zero_poison:
; RV32I: # %bb.0:
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: lui a1, 5
@@ -770,14 +770,14 @@ define i16 @test_ctlz_i16_zero_undef(i16 %a) nounwind {
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32ZBB-LABEL: test_ctlz_i16_zero_undef:
+; RV32ZBB-LABEL: test_ctlz_i16_zero_poison:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: not a0, a0
; RV32ZBB-NEXT: slli a0, a0, 16
; RV32ZBB-NEXT: clz a0, a0
; RV32ZBB-NEXT: ret
;
-; RV32ZBBXQCIBM-LABEL: test_ctlz_i16_zero_undef:
+; RV32ZBBXQCIBM-LABEL: test_ctlz_i16_zero_poison:
; RV32ZBBXQCIBM: # %bb.0:
; RV32ZBBXQCIBM-NEXT: not a0, a0
; RV32ZBBXQCIBM-NEXT: slli a0, a0, 16
@@ -788,8 +788,8 @@ define i16 @test_ctlz_i16_zero_undef(i16 %a) nounwind {
ret i16 %tmp
}
-define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind {
-; RV32I-LABEL: test_ctlz_i32_zero_undef:
+define i32 @test_ctlz_i32_zero_poison(i32 %a) nounwind {
+; RV32I-LABEL: test_ctlz_i32_zero_poison:
; RV32I: # %bb.0:
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: lui a1, 349525
@@ -826,13 +826,13 @@ define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind {
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: ret
;
-; RV32ZBB-LABEL: test_ctlz_i32_zero_undef:
+; RV32ZBB-LABEL: test_ctlz_i32_zero_poison:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: not a0, a0
; RV32ZBB-NEXT: clz a0, a0
; RV32ZBB-NEXT: ret
;
-; RV32ZBBXQCIBM-LABEL: test_ctlz_i32_zero_undef:
+; RV32ZBBXQCIBM-LABEL: test_ctlz_i32_zero_poison:
; RV32ZBBXQCIBM: # %bb.0:
; RV32ZBBXQCIBM-NEXT: qc.clo a0, a0
; RV32ZBBXQCIBM-NEXT: ret
@@ -841,8 +841,8 @@ define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind {
ret i32 %tmp
}
-define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
-; RV32I-LABEL: test_ctlz_i64_zero_undef:
+define i64 @test_ctlz_i64_zero_poison(i64 %a) nounwind {
+; RV32I-LABEL: test_ctlz_i64_zero_poison:
; RV32I: # %bb.0:
; RV32I-NEXT: not a4, a1
; RV32I-NEXT: lui a1, 349525
@@ -913,7 +913,7 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: ret
;
-; RV32ZBB-LABEL: test_ctlz_i64_zero_undef:
+; RV32ZBB-LABEL: test_ctlz_i64_zero_poison:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: not a1, a1
; RV32ZBB-NEXT: bnez a1, .LBB15_2
@@ -928,7 +928,7 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
; RV32ZBB-NEXT: li a1, 0
; RV32ZBB-NEXT: ret
;
-; RV32ZBBXQCIBM-LABEL: test_ctlz_i64_zero_undef:
+; RV32ZBBXQCIBM-LABEL: test_ctlz_i64_zero_poison:
; RV32ZBBXQCIBM: # %bb.0:
; RV32ZBBXQCIBM-NEXT: not a2, a1
; RV32ZBBXQCIBM-NEXT: bnez a2, .LBB15_2
diff --git a/llvm/test/CodeGen/SystemZ/vec-ctlz-01.ll b/llvm/test/CodeGen/SystemZ/vec-ctlz-01.ll
index f6502202ef582..4c59dad8953bf 100644
--- a/llvm/test/CodeGen/SystemZ/vec-ctlz-01.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-ctlz-01.ll
@@ -2,10 +2,10 @@
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
-declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %src, i1 %is_zero_undef)
-declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %src, i1 %is_zero_undef)
-declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %src, i1 %is_zero_undef)
-declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 %is_zero_undef)
+declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %src, i1 %is_zero_poison)
+declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %src, i1 %is_zero_poison)
+declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %src, i1 %is_zero_poison)
+declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 %is_zero_poison)
define <16 x i8> @f1(<16 x i8> %a) {
; CHECK-LABEL: f1:
diff --git a/llvm/test/CodeGen/SystemZ/vec-cttz-01.ll b/llvm/test/CodeGen/SystemZ/vec-cttz-01.ll
index 00a0d21b42fec..6e34ce12fba6b 100644
--- a/llvm/test/CodeGen/SystemZ/vec-cttz-01.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-cttz-01.ll
@@ -2,10 +2,10 @@
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
-declare <16 x i8> @llvm.cttz.v16i8(<16 x i8> %src, i1 %is_zero_undef)
-declare <8 x i16> @llvm.cttz.v8i16(<8 x i16> %src, i1 %is_zero_undef)
-declare <4 x i32> @llvm.cttz.v4i32(<4 x i32> %src, i1 %is_zero_undef)
-declare <2 x i64> @llvm.cttz.v2i64(<2 x i64> %src, i1 %is_zero_undef)
+declare <16 x i8> @llvm.cttz.v16i8(<16 x i8> %src, i1 %is_zero_poison)
+declare <8 x i16> @llvm.cttz.v8i16(<8 x i16> %src, i1 %is_zero_poison)
+declare <4 x i32> @llvm.cttz.v4i32(<4 x i32> %src, i1 %is_zero_poison)
+declare <2 x i64> @llvm.cttz.v2i64(<2 x i64> %src, i1 %is_zero_poison)
define <16 x i8> @f1(<16 x i8> %a) {
; CHECK-LABEL: f1:
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir
index e8bdb5cb911c2..4a5238cc535d5 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir
@@ -59,31 +59,31 @@ body: |
---
-name: ctlz_zundef_i32_i8
+name: ctlz_zpoison_i32_i8
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $arguments
- ; CHECK-LABEL: name: ctlz_zundef_i32_i8
+ ; CHECK-LABEL: name: ctlz_zpoison_i32_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[CLZ_I32_]], implicit-def $arguments
%0:i32(i32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(i8) = G_CTLZ_ZERO_UNDEF %0
+ %1:_(i8) = G_CTLZ_ZERO_POISON %0
%2:_(i32) = G_ANYEXT %1(i8)
RETURN %2(i32), implicit-def $arguments
...
---
-name: ctlz_zundef_i64_i8
+name: ctlz_zpoison_i64_i8
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $arguments
- ; CHECK-LABEL: name: ctlz_zundef_i64_i8
+ ; CHECK-LABEL: name: ctlz_zpoison_i64_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
@@ -91,18 +91,18 @@ body: |
; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CLZ_I64_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
%0:i64(i64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(i8) = G_CTLZ_ZERO_UNDEF %0
+ %1:_(i8) = G_CTLZ_ZERO_POISON %0
%2:_(i32) = G_ANYEXT %1(i8)
RETURN %2(i32), implicit-def $arguments
...
---
-name: ctlz_zundef_i64_i32
+name: ctlz_zpoison_i64_i32
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $arguments
- ; CHECK-LABEL: name: ctlz_zundef_i64_i32
+ ; CHECK-LABEL: name: ctlz_zpoison_i64_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
@@ -110,6 +110,6 @@ body: |
; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CLZ_I64_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
%0:i64(i64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(i32) = G_CTLZ_ZERO_UNDEF %0
+ %1:_(i32) = G_CTLZ_ZERO_POISON %0
RETURN %1(i32), implicit-def $arguments
...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir
index 465b4a051cf73..cb4e099c66d60 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir
@@ -59,31 +59,31 @@ body: |
---
-name: cttz_zundef_i32_i8
+name: cttz_zpoison_i32_i8
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $arguments
- ; CHECK-LABEL: name: cttz_zundef_i32_i8
+ ; CHECK-LABEL: name: cttz_zpoison_i32_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
%0:i32(i32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(i8) = G_CTTZ_ZERO_UNDEF %0
+ %1:_(i8) = G_CTTZ_ZERO_POISON %0
%2:_(i32) = G_ANYEXT %1(i8)
RETURN %2(i32), implicit-def $arguments
...
---
-name: cttz_zundef_i64_i8
+name: cttz_zpoison_i64_i8
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $arguments
- ; CHECK-LABEL: name: cttz_zundef_i64_i8
+ ; CHECK-LABEL: name: cttz_zpoison_i64_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
@@ -91,18 +91,18 @@ body: |
; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CTZ_I64_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
%0:i64(i64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(i8) = G_CTTZ_ZERO_UNDEF %0
+ %1:_(i8) = G_CTTZ_ZERO_POISON %0
%2:_(i32) = G_ANYEXT %1(i8)
RETURN %2(i32), implicit-def $arguments
...
---
-name: cttz_zundef_i64_i32
+name: cttz_zpoison_i64_i32
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $arguments
- ; CHECK-LABEL: name: cttz_zundef_i64_i32
+ ; CHECK-LABEL: name: cttz_zpoison_i64_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
@@ -110,6 +110,6 @@ body: |
; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CTZ_I64_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
%0:i64(i64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(i32) = G_CTTZ_ZERO_UNDEF %0
+ %1:_(i32) = G_CTTZ_ZERO_POISON %0
RETURN %1(i32), implicit-def $arguments
...
diff --git a/llvm/test/CodeGen/WebAssembly/i128.ll b/llvm/test/CodeGen/WebAssembly/i128.ll
index d9bec9b8ae887..353c38473b2e8 100644
--- a/llvm/test/CodeGen/WebAssembly/i128.ll
+++ b/llvm/test/CodeGen/WebAssembly/i128.ll
@@ -403,9 +403,9 @@ define i128 @clz128(i128 %x) {
ret i128 %a
}
-define i128 @clz128_zero_undef(i128 %x) {
-; CHECK-LABEL: clz128_zero_undef:
-; CHECK: .functype clz128_zero_undef (i32, i64, i64) -> ()
+define i128 @clz128_zero_poison(i128 %x) {
+; CHECK-LABEL: clz128_zero_poison:
+; CHECK: .functype clz128_zero_poison (i32, i64, i64) -> ()
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get $push8=, 0
; CHECK-NEXT: i64.const $push0=, 0
@@ -451,9 +451,9 @@ define i128 @ctz128(i128 %x) {
ret i128 %a
}
-define i128 @ctz128_zero_undef(i128 %x) {
-; CHECK-LABEL: ctz128_zero_undef:
-; CHECK: .functype ctz128_zero_undef (i32, i64, i64) -> ()
+define i128 @ctz128_zero_poison(i128 %x) {
+; CHECK-LABEL: ctz128_zero_poison:
+; CHECK: .functype ctz128_zero_poison (i32, i64, i64) -> ()
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get $push8=, 0
; CHECK-NEXT: i64.const $push0=, 0
diff --git a/llvm/test/CodeGen/WebAssembly/i32.ll b/llvm/test/CodeGen/WebAssembly/i32.ll
index be5f779ae8102..8aa4aa582b436 100644
--- a/llvm/test/CodeGen/WebAssembly/i32.ll
+++ b/llvm/test/CodeGen/WebAssembly/i32.ll
@@ -161,12 +161,12 @@ define i32 @clz32(i32 %x) {
ret i32 %a
}
-; CHECK-LABEL: clz32_zero_undef:
-; CHECK-NEXT: .functype clz32_zero_undef (i32) -> (i32){{$}}
+; CHECK-LABEL: clz32_zero_poison:
+; CHECK-NEXT: .functype clz32_zero_poison (i32) -> (i32){{$}}
; CHECK-NEXT: local.get $push[[L0:[0-9]+]]=, 0{{$}}
; CHECK-NEXT: i32.clz $push0=, $pop[[L0]]{{$}}
; CHECK-NEXT: return $pop0{{$}}
-define i32 @clz32_zero_undef(i32 %x) {
+define i32 @clz32_zero_poison(i32 %x) {
%a = call i32 @llvm.ctlz.i32(i32 %x, i1 true)
ret i32 %a
}
@@ -181,12 +181,12 @@ define i32 @ctz32(i32 %x) {
ret i32 %a
}
-; CHECK-LABEL: ctz32_zero_undef:
-; CHECK-NEXT: .functype ctz32_zero_undef (i32) -> (i32){{$}}
+; CHECK-LABEL: ctz32_zero_poison:
+; CHECK-NEXT: .functype ctz32_zero_poison (i32) -> (i32){{$}}
; CHECK-NEXT: local.get $push[[L0:[0-9]+]]=, 0{{$}}
; CHECK-NEXT: i32.ctz $push0=, $pop[[L0]]{{$}}
; CHECK-NEXT: return $pop0{{$}}
-define i32 @ctz32_zero_undef(i32 %x) {
+define i32 @ctz32_zero_poison(i32 %x) {
%a = call i32 @llvm.cttz.i32(i32 %x, i1 true)
ret i32 %a
}
diff --git a/llvm/test/CodeGen/WebAssembly/i64.ll b/llvm/test/CodeGen/WebAssembly/i64.ll
index c93f43080c409..cbceceee18d40 100644
--- a/llvm/test/CodeGen/WebAssembly/i64.ll
+++ b/llvm/test/CodeGen/WebAssembly/i64.ll
@@ -161,12 +161,12 @@ define i64 @clz64(i64 %x) {
ret i64 %a
}
-; CHECK-LABEL: clz64_zero_undef:
-; CHECK-NEXT: .functype clz64_zero_undef (i64) -> (i64){{$}}
+; CHECK-LABEL: clz64_zero_poison:
+; CHECK-NEXT: .functype clz64_zero_poison (i64) -> (i64){{$}}
; CHECK-NEXT: local.get $push[[L0:[0-9]+]]=, 0{{$}}
; CHECK-NEXT: i64.clz $push0=, $pop[[L0]]{{$}}
; CHECK-NEXT: return $pop0{{$}}
-define i64 @clz64_zero_undef(i64 %x) {
+define i64 @clz64_zero_poison(i64 %x) {
%a = call i64 @llvm.ctlz.i64(i64 %x, i1 true)
ret i64 %a
}
@@ -181,12 +181,12 @@ define i64 @ctz64(i64 %x) {
ret i64 %a
}
-; CHECK-LABEL: ctz64_zero_undef:
-; CHECK-NEXT: .functype ctz64_zero_undef (i64) -> (i64){{$}}
+; CHECK-LABEL: ctz64_zero_poison:
+; CHECK-NEXT: .functype ctz64_zero_poison (i64) -> (i64){{$}}
; CHECK-NEXT: local.get $push[[L0:[0-9]+]]=, 0{{$}}
; CHECK-NEXT: i64.ctz $push0=, $pop[[L0]]{{$}}
; CHECK-NEXT: return $pop0{{$}}
-define i64 @ctz64_zero_undef(i64 %x) {
+define i64 @ctz64_zero_poison(i64 %x) {
%a = call i64 @llvm.cttz.i64(i64 %x, i1 true)
ret i64 %a
}
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-leading-zeros.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-leading-zeros.mir
index 2e4adaaa4e48e..c877f33cc9822 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-leading-zeros.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-leading-zeros.mir
@@ -3,7 +3,7 @@
# RUN: llc -mtriple=i386-linux-gnu -mattr=+lzcnt -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel*' %s 2>%t -o - | FileCheck %s --check-prefixes=CHECK,X86
# RUN: FileCheck -check-prefix=ERR32 %s < %t
-# ERR32: remark: <unknown>:0:0: unable to legalize instruction: %10:_(s64) = G_CTLZ_ZERO_UNDEF %4:_(s32) (in function: test_ctlz64)
+# ERR32: remark: <unknown>:0:0: unable to legalize instruction: %10:_(s64) = G_CTLZ_ZERO_POISON %4:_(s32) (in function: test_ctlz64)
# test count leading zeros for s16, s32, and s64
@@ -35,10 +35,10 @@ body: |
; X86-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[UV]](s32)
; X86-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; X86-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[CTLZ]], [[C1]]
- ; X86-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTLZ_ZERO_UNDEF [[UV1]](s32)
+ ; X86-NEXT: [[CTLZ_ZERO_POISON:%[0-9]+]]:_(s64) = G_CTLZ_ZERO_POISON [[UV1]](s32)
; X86-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ADD]](s64)
- ; X86-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[CTLZ_ZERO_UNDEF]](s64)
+ ; X86-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[CTLZ_ZERO_POISON]](s64)
; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ZEXT1]](s32), [[UV2]], [[UV4]]
; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ZEXT1]](s32), [[UV3]], [[UV5]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
@@ -109,10 +109,10 @@ body: |
; X86-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[UV]](s32)
; X86-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; X86-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[CTLZ]], [[C1]]
- ; X86-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTLZ_ZERO_UNDEF [[UV1]](s32)
+ ; X86-NEXT: [[CTLZ_ZERO_POISON:%[0-9]+]]:_(s64) = G_CTLZ_ZERO_POISON [[UV1]](s32)
; X86-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ADD]](s64)
- ; X86-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[CTLZ_ZERO_UNDEF]](s64)
+ ; X86-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[CTLZ_ZERO_POISON]](s64)
; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ZEXT]](s32), [[UV2]], [[UV4]]
; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ZEXT]](s32), [[UV3]], [[UV5]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-poison.mir
similarity index 78%
rename from llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir
rename to llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-poison.mir
index 148aac1ab46fe..cf3a246b8fcf9 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-poison.mir
@@ -17,8 +17,8 @@ body: |
; X64: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
; X64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
; X64-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[C]]
- ; X64-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTTZ_ZERO_UNDEF [[OR]](s64)
- ; X64-NEXT: RET 0, implicit [[CTTZ_ZERO_UNDEF]](s64)
+ ; X64-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s64) = G_CTTZ_ZERO_POISON [[OR]](s64)
+ ; X64-NEXT: RET 0, implicit [[CTTZ_ZERO_POISON]](s64)
;
; X86-LABEL: name: test_cttz35
; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
@@ -28,15 +28,15 @@ body: |
; X86-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[C]]
; X86-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[UV1]], [[C1]]
; X86-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(eq), [[OR]](s32), [[C]]
- ; X86-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR1]](s32)
+ ; X86-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[OR1]](s32)
; X86-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C2]]
+ ; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[CTTZ_ZERO_POISON]], [[C2]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s8) = G_UADDE [[C]], [[C]], [[UADDO1]]
- ; X86-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
+ ; X86-NEXT: [[CTTZ_ZERO_POISON1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[OR]](s32)
; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
; X86-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
- ; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDO]], [[CTTZ_ZERO_UNDEF1]]
+ ; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDO]], [[CTTZ_ZERO_POISON1]]
; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDE]], [[C]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
; X86-NEXT: RET 0, implicit [[MV]](s64)
@@ -59,12 +59,12 @@ body: |
; CHECK-LABEL: name: test_cttz8
; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[DEF]](s8)
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s16) = G_CTTZ_ZERO_UNDEF [[ANYEXT]](s16)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[CTTZ_ZERO_UNDEF]](s16)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s16) = G_CTTZ_ZERO_POISON [[ANYEXT]](s16)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[CTTZ_ZERO_POISON]](s16)
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY [[TRUNC]](s8)
; CHECK-NEXT: RET 0, implicit [[COPY]](s8)
%0:_(s8) = IMPLICIT_DEF
- %1:_(s8) = G_CTTZ_ZERO_UNDEF %0
+ %1:_(s8) = G_CTTZ_ZERO_POISON %0
%2:_(s8) = COPY %1(s8)
RET 0, implicit %2
...
@@ -80,8 +80,8 @@ body: |
bb.1:
; X64-LABEL: name: test_cttz64
; X64: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
- ; X64-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTTZ_ZERO_UNDEF [[DEF]](s64)
- ; X64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[CTTZ_ZERO_UNDEF]](s64)
+ ; X64-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s64) = G_CTTZ_ZERO_POISON [[DEF]](s64)
+ ; X64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[CTTZ_ZERO_POISON]](s64)
; X64-NEXT: RET 0, implicit [[COPY]](s64)
;
; X86-LABEL: name: test_cttz64
@@ -89,21 +89,21 @@ body: |
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
; X86-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; X86-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(eq), [[UV]](s32), [[C]]
- ; X86-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV1]](s32)
+ ; X86-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[UV1]](s32)
; X86-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C1]]
+ ; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[CTTZ_ZERO_POISON]], [[C1]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s8) = G_UADDE [[C]], [[C]], [[UADDO1]]
- ; X86-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV]](s32)
+ ; X86-NEXT: [[CTTZ_ZERO_POISON1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[UV]](s32)
; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
; X86-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
- ; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDO]], [[CTTZ_ZERO_UNDEF1]]
+ ; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDO]], [[CTTZ_ZERO_POISON1]]
; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDE]], [[C]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
; X86-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; X86-NEXT: RET 0, implicit [[COPY]](s64)
%0:_(s64) = IMPLICIT_DEF
- %1:_(s64) = G_CTTZ_ZERO_UNDEF %0
+ %1:_(s64) = G_CTTZ_ZERO_POISON %0
%2:_(s64) = COPY %1(s64)
RET 0, implicit %2
...
@@ -119,11 +119,11 @@ body: |
bb.1:
; CHECK-LABEL: name: test_cttz32
; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[DEF]](s32)
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[DEF]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_POISON]](s32)
; CHECK-NEXT: RET 0, implicit [[COPY]](s32)
%0:_(s32) = IMPLICIT_DEF
- %1:_(s32) = G_CTTZ_ZERO_UNDEF %0
+ %1:_(s32) = G_CTTZ_ZERO_POISON %0
%2:_(s32) = COPY %1(s32)
RET 0, implicit %2
...
@@ -139,11 +139,11 @@ body: |
bb.1:
; CHECK-LABEL: name: test_cttz16
; CHECK: [[DEF:%[0-9]+]]:_(s16) = IMPLICIT_DEF
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s16) = G_CTTZ_ZERO_UNDEF [[DEF]](s16)
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY [[CTTZ_ZERO_UNDEF]](s16)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s16) = G_CTTZ_ZERO_POISON [[DEF]](s16)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY [[CTTZ_ZERO_POISON]](s16)
; CHECK-NEXT: RET 0, implicit [[COPY]](s16)
%0:_(s16) = IMPLICIT_DEF
- %1:_(s16) = G_CTTZ_ZERO_UNDEF %0
+ %1:_(s16) = G_CTTZ_ZERO_POISON %0
%2:_(s16) = COPY %1(s16)
RET 0, implicit %2
...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir
index 17469289821f1..32b3061256de7 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir
@@ -17,8 +17,8 @@ body: |
; X64: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
; X64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
; X64-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[C]]
- ; X64-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTTZ_ZERO_UNDEF [[OR]](s64)
- ; X64-NEXT: RET 0, implicit [[CTTZ_ZERO_UNDEF]](s64)
+ ; X64-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s64) = G_CTTZ_ZERO_POISON [[OR]](s64)
+ ; X64-NEXT: RET 0, implicit [[CTTZ_ZERO_POISON]](s64)
;
; X86-LABEL: name: test_cttz35
; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
@@ -28,15 +28,15 @@ body: |
; X86-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[C]]
; X86-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[UV1]], [[C1]]
; X86-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(eq), [[OR]](s32), [[C]]
- ; X86-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR1]](s32)
+ ; X86-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[OR1]](s32)
; X86-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C2]]
+ ; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[CTTZ_ZERO_POISON]], [[C2]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s8) = G_UADDE [[C]], [[C]], [[UADDO1]]
- ; X86-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
+ ; X86-NEXT: [[CTTZ_ZERO_POISON1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[OR]](s32)
; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
; X86-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
- ; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDO]], [[CTTZ_ZERO_UNDEF1]]
+ ; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDO]], [[CTTZ_ZERO_POISON1]]
; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDE]], [[C]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
; X86-NEXT: RET 0, implicit [[MV]](s64)
@@ -61,8 +61,8 @@ body: |
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[DEF]](s8)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 256
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[ANYEXT]], [[C]]
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s16) = G_CTTZ_ZERO_UNDEF [[OR]](s16)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[CTTZ_ZERO_UNDEF]](s16)
+ ; CHECK-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s16) = G_CTTZ_ZERO_POISON [[OR]](s16)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[CTTZ_ZERO_POISON]](s16)
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY [[TRUNC]](s8)
; CHECK-NEXT: RET 0, implicit [[COPY]](s8)
%0:_(s8) = IMPLICIT_DEF
@@ -95,11 +95,11 @@ body: |
; X86-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[CTTZ]], [[C1]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s8) = G_UADDE [[C]], [[C]], [[UADDO1]]
- ; X86-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV]](s32)
+ ; X86-NEXT: [[CTTZ_ZERO_POISON:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[UV]](s32)
; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
; X86-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
- ; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDO]], [[CTTZ_ZERO_UNDEF]]
+ ; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDO]], [[CTTZ_ZERO_POISON]]
; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDE]], [[C]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
; X86-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
diff --git a/llvm/test/CodeGen/X86/bitcnt-big-integer.ll b/llvm/test/CodeGen/X86/bitcnt-big-integer.ll
index 31adbb71f271e..6dcdd697e639a 100644
--- a/llvm/test/CodeGen/X86/bitcnt-big-integer.ll
+++ b/llvm/test/CodeGen/X86/bitcnt-big-integer.ll
@@ -3366,11 +3366,11 @@ define i32 @load_ctlz_i1024(ptr %p0) nounwind {
}
;
-; CTLZ_ZERO_UNDEF
+; CTLZ_ZERO_POISON
;
-define i32 @test_ctlz_undef_i128(i128 %a0) nounwind {
-; SSE-LABEL: test_ctlz_undef_i128:
+define i32 @test_ctlz_poison_i128(i128 %a0) nounwind {
+; SSE-LABEL: test_ctlz_poison_i128:
; SSE: # %bb.0:
; SSE-NEXT: bsrq %rsi, %rcx
; SSE-NEXT: xorl $63, %ecx
@@ -3382,7 +3382,7 @@ define i32 @test_ctlz_undef_i128(i128 %a0) nounwind {
; SSE-NEXT: # kill: def $eax killed $eax killed $rax
; SSE-NEXT: retq
;
-; AVX2-LABEL: test_ctlz_undef_i128:
+; AVX2-LABEL: test_ctlz_poison_i128:
; AVX2: # %bb.0:
; AVX2-NEXT: lzcntq %rsi, %rcx
; AVX2-NEXT: lzcntq %rdi, %rax
@@ -3392,7 +3392,7 @@ define i32 @test_ctlz_undef_i128(i128 %a0) nounwind {
; AVX2-NEXT: # kill: def $eax killed $eax killed $rax
; AVX2-NEXT: retq
;
-; AVX512-LABEL: test_ctlz_undef_i128:
+; AVX512-LABEL: test_ctlz_poison_i128:
; AVX512: # %bb.0:
; AVX512-NEXT: lzcntq %rsi, %rcx
; AVX512-NEXT: lzcntq %rdi, %rax
@@ -3406,8 +3406,8 @@ define i32 @test_ctlz_undef_i128(i128 %a0) nounwind {
ret i32 %res
}
-define i32 @load_ctlz_undef_i128(ptr %p0) nounwind {
-; SSE-LABEL: load_ctlz_undef_i128:
+define i32 @load_ctlz_poison_i128(ptr %p0) nounwind {
+; SSE-LABEL: load_ctlz_poison_i128:
; SSE: # %bb.0:
; SSE-NEXT: movq 8(%rdi), %rcx
; SSE-NEXT: bsrq %rcx, %rdx
@@ -3420,7 +3420,7 @@ define i32 @load_ctlz_undef_i128(ptr %p0) nounwind {
; SSE-NEXT: # kill: def $eax killed $eax killed $rax
; SSE-NEXT: retq
;
-; AVX2-LABEL: load_ctlz_undef_i128:
+; AVX2-LABEL: load_ctlz_poison_i128:
; AVX2: # %bb.0:
; AVX2-NEXT: movq 8(%rdi), %rcx
; AVX2-NEXT: lzcntq %rcx, %rdx
@@ -3431,7 +3431,7 @@ define i32 @load_ctlz_undef_i128(ptr %p0) nounwind {
; AVX2-NEXT: # kill: def $eax killed $eax killed $rax
; AVX2-NEXT: retq
;
-; AVX512-LABEL: load_ctlz_undef_i128:
+; AVX512-LABEL: load_ctlz_poison_i128:
; AVX512: # %bb.0:
; AVX512-NEXT: movq 8(%rdi), %rcx
; AVX512-NEXT: lzcntq %rcx, %rdx
@@ -3447,8 +3447,8 @@ define i32 @load_ctlz_undef_i128(ptr %p0) nounwind {
ret i32 %res
}
-define i32 @vector_ctlz_undef_i128(<4 x i32> %v0) nounwind {
-; SSE-LABEL: vector_ctlz_undef_i128:
+define i32 @vector_ctlz_poison_i128(<4 x i32> %v0) nounwind {
+; SSE-LABEL: vector_ctlz_poison_i128:
; SSE: # %bb.0:
; SSE-NEXT: movq %xmm0, %rax
; SSE-NEXT: pextrq $1, %xmm0, %rcx
@@ -3462,7 +3462,7 @@ define i32 @vector_ctlz_undef_i128(<4 x i32> %v0) nounwind {
; SSE-NEXT: # kill: def $eax killed $eax killed $rax
; SSE-NEXT: retq
;
-; AVX2-LABEL: vector_ctlz_undef_i128:
+; AVX2-LABEL: vector_ctlz_poison_i128:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
@@ -3474,7 +3474,7 @@ define i32 @vector_ctlz_undef_i128(<4 x i32> %v0) nounwind {
; AVX2-NEXT: # kill: def $eax killed $eax killed $rax
; AVX2-NEXT: retq
;
-; AVX512F-LABEL: vector_ctlz_undef_i128:
+; AVX512F-LABEL: vector_ctlz_poison_i128:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vpextrq $1, %xmm0, %rcx
@@ -3486,7 +3486,7 @@ define i32 @vector_ctlz_undef_i128(<4 x i32> %v0) nounwind {
; AVX512F-NEXT: # kill: def $eax killed $eax killed $rax
; AVX512F-NEXT: retq
;
-; AVX512POPCNT-LABEL: vector_ctlz_undef_i128:
+; AVX512POPCNT-LABEL: vector_ctlz_poison_i128:
; AVX512POPCNT: # %bb.0:
; AVX512POPCNT-NEXT: vmovq %xmm0, %rax
; AVX512POPCNT-NEXT: vpextrq $1, %xmm0, %rcx
@@ -3498,7 +3498,7 @@ define i32 @vector_ctlz_undef_i128(<4 x i32> %v0) nounwind {
; AVX512POPCNT-NEXT: # kill: def $eax killed $eax killed $rax
; AVX512POPCNT-NEXT: retq
;
-; AVX512VL-LABEL: vector_ctlz_undef_i128:
+; AVX512VL-LABEL: vector_ctlz_poison_i128:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rcx
; AVX512VL-NEXT: vmovq %xmm0, %rax
@@ -3510,7 +3510,7 @@ define i32 @vector_ctlz_undef_i128(<4 x i32> %v0) nounwind {
; AVX512VL-NEXT: # kill: def $eax killed $eax killed $rax
; AVX512VL-NEXT: retq
;
-; AVX512VLPOPCNT-LABEL: vector_ctlz_undef_i128:
+; AVX512VLPOPCNT-LABEL: vector_ctlz_poison_i128:
; AVX512VLPOPCNT: # %bb.0:
; AVX512VLPOPCNT-NEXT: vpextrq $1, %xmm0, %rcx
; AVX512VLPOPCNT-NEXT: vmovq %xmm0, %rax
@@ -3527,8 +3527,8 @@ define i32 @vector_ctlz_undef_i128(<4 x i32> %v0) nounwind {
ret i32 %res
}
-define i32 @test_ctlz_undef_i256(i256 %a0) nounwind {
-; SSE-LABEL: test_ctlz_undef_i256:
+define i32 @test_ctlz_poison_i256(i256 %a0) nounwind {
+; SSE-LABEL: test_ctlz_poison_i256:
; SSE: # %bb.0:
; SSE-NEXT: bsrq %rcx, %rax
; SSE-NEXT: xorl $63, %eax
@@ -3550,7 +3550,7 @@ define i32 @test_ctlz_undef_i256(i256 %a0) nounwind {
; SSE-NEXT: # kill: def $eax killed $eax killed $rax
; SSE-NEXT: retq
;
-; AVX2-LABEL: test_ctlz_undef_i256:
+; AVX2-LABEL: test_ctlz_poison_i256:
; AVX2: # %bb.0:
; AVX2-NEXT: lzcntq %rcx, %rax
; AVX2-NEXT: lzcntq %rdx, %r8
@@ -3569,7 +3569,7 @@ define i32 @test_ctlz_undef_i256(i256 %a0) nounwind {
; AVX2-NEXT: # kill: def $eax killed $eax killed $rax
; AVX2-NEXT: retq
;
-; AVX512-LABEL: test_ctlz_undef_i256:
+; AVX512-LABEL: test_ctlz_poison_i256:
; AVX512: # %bb.0:
; AVX512-NEXT: lzcntq %rcx, %rax
; AVX512-NEXT: lzcntq %rdx, %r8
@@ -3591,8 +3591,8 @@ define i32 @test_ctlz_undef_i256(i256 %a0) nounwind {
ret i32 %res
}
-define i32 @load_ctlz_undef_i256(ptr %p0) nounwind {
-; SSE-LABEL: load_ctlz_undef_i256:
+define i32 @load_ctlz_poison_i256(ptr %p0) nounwind {
+; SSE-LABEL: load_ctlz_poison_i256:
; SSE: # %bb.0:
; SSE-NEXT: movq 8(%rdi), %rdx
; SSE-NEXT: movq 16(%rdi), %rcx
@@ -3617,7 +3617,7 @@ define i32 @load_ctlz_undef_i256(ptr %p0) nounwind {
; SSE-NEXT: # kill: def $eax killed $eax killed $rax
; SSE-NEXT: retq
;
-; AVX2-LABEL: load_ctlz_undef_i256:
+; AVX2-LABEL: load_ctlz_poison_i256:
; AVX2: # %bb.0:
; AVX2-NEXT: movq 16(%rdi), %rcx
; AVX2-NEXT: movq 24(%rdi), %rdx
@@ -3639,7 +3639,7 @@ define i32 @load_ctlz_undef_i256(ptr %p0) nounwind {
; AVX2-NEXT: # kill: def $eax killed $eax killed $rax
; AVX2-NEXT: retq
;
-; AVX512F-LABEL: load_ctlz_undef_i256:
+; AVX512F-LABEL: load_ctlz_poison_i256:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpermq {{.*#+}} ymm0 = mem[3,2,1,0]
; AVX512F-NEXT: vplzcntq %zmm0, %zmm1
@@ -3651,7 +3651,7 @@ define i32 @load_ctlz_undef_i256(ptr %p0) nounwind {
; AVX512F-NEXT: vmovd %xmm0, %eax
; AVX512F-NEXT: retq
;
-; AVX512POPCNT-LABEL: load_ctlz_undef_i256:
+; AVX512POPCNT-LABEL: load_ctlz_poison_i256:
; AVX512POPCNT: # %bb.0:
; AVX512POPCNT-NEXT: vpermq {{.*#+}} ymm0 = mem[3,2,1,0]
; AVX512POPCNT-NEXT: vplzcntq %zmm0, %zmm1
@@ -3663,7 +3663,7 @@ define i32 @load_ctlz_undef_i256(ptr %p0) nounwind {
; AVX512POPCNT-NEXT: vmovd %xmm0, %eax
; AVX512POPCNT-NEXT: retq
;
-; AVX512VL-LABEL: load_ctlz_undef_i256:
+; AVX512VL-LABEL: load_ctlz_poison_i256:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpermq {{.*#+}} ymm0 = mem[3,2,1,0]
; AVX512VL-NEXT: vptestmq %ymm0, %ymm0, %k1
@@ -3674,7 +3674,7 @@ define i32 @load_ctlz_undef_i256(ptr %p0) nounwind {
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
-; AVX512VLPOPCNT-LABEL: load_ctlz_undef_i256:
+; AVX512VLPOPCNT-LABEL: load_ctlz_poison_i256:
; AVX512VLPOPCNT: # %bb.0:
; AVX512VLPOPCNT-NEXT: vpermq {{.*#+}} ymm0 = mem[3,2,1,0]
; AVX512VLPOPCNT-NEXT: vptestmq %ymm0, %ymm0, %k1
@@ -3690,8 +3690,8 @@ define i32 @load_ctlz_undef_i256(ptr %p0) nounwind {
ret i32 %res
}
-define i32 @vector_ctlz_undef_i256(<8 x i32> %v0) nounwind {
-; SSE-LABEL: vector_ctlz_undef_i256:
+define i32 @vector_ctlz_poison_i256(<8 x i32> %v0) nounwind {
+; SSE-LABEL: vector_ctlz_poison_i256:
; SSE: # %bb.0:
; SSE-NEXT: pextrq $1, %xmm0, %rcx
; SSE-NEXT: movq %xmm0, %rax
@@ -3717,7 +3717,7 @@ define i32 @vector_ctlz_undef_i256(<8 x i32> %v0) nounwind {
; SSE-NEXT: # kill: def $eax killed $eax killed $rax
; SSE-NEXT: retq
;
-; AVX2-LABEL: vector_ctlz_undef_i256:
+; AVX2-LABEL: vector_ctlz_poison_i256:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
@@ -3742,7 +3742,7 @@ define i32 @vector_ctlz_undef_i256(<8 x i32> %v0) nounwind {
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
-; AVX512F-LABEL: vector_ctlz_undef_i256:
+; AVX512F-LABEL: vector_ctlz_poison_i256:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,2,1,0]
; AVX512F-NEXT: vplzcntq %zmm0, %zmm1
@@ -3754,7 +3754,7 @@ define i32 @vector_ctlz_undef_i256(<8 x i32> %v0) nounwind {
; AVX512F-NEXT: vmovd %xmm0, %eax
; AVX512F-NEXT: retq
;
-; AVX512POPCNT-LABEL: vector_ctlz_undef_i256:
+; AVX512POPCNT-LABEL: vector_ctlz_poison_i256:
; AVX512POPCNT: # %bb.0:
; AVX512POPCNT-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,2,1,0]
; AVX512POPCNT-NEXT: vplzcntq %zmm0, %zmm1
@@ -3766,7 +3766,7 @@ define i32 @vector_ctlz_undef_i256(<8 x i32> %v0) nounwind {
; AVX512POPCNT-NEXT: vmovd %xmm0, %eax
; AVX512POPCNT-NEXT: retq
;
-; AVX512VL-LABEL: vector_ctlz_undef_i256:
+; AVX512VL-LABEL: vector_ctlz_poison_i256:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,2,1,0]
; AVX512VL-NEXT: vptestmq %ymm0, %ymm0, %k1
@@ -3777,7 +3777,7 @@ define i32 @vector_ctlz_undef_i256(<8 x i32> %v0) nounwind {
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
-; AVX512VLPOPCNT-LABEL: vector_ctlz_undef_i256:
+; AVX512VLPOPCNT-LABEL: vector_ctlz_poison_i256:
; AVX512VLPOPCNT: # %bb.0:
; AVX512VLPOPCNT-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,2,1,0]
; AVX512VLPOPCNT-NEXT: vptestmq %ymm0, %ymm0, %k1
@@ -3793,8 +3793,8 @@ define i32 @vector_ctlz_undef_i256(<8 x i32> %v0) nounwind {
ret i32 %res
}
-define i32 @test_ctlz_undef_i512(i512 %a0) nounwind {
-; SSE-LABEL: test_ctlz_undef_i512:
+define i32 @test_ctlz_poison_i512(i512 %a0) nounwind {
+; SSE-LABEL: test_ctlz_poison_i512:
; SSE: # %bb.0:
; SSE-NEXT: pushq %r15
; SSE-NEXT: pushq %r14
@@ -3847,7 +3847,7 @@ define i32 @test_ctlz_undef_i512(i512 %a0) nounwind {
; SSE-NEXT: popq %r15
; SSE-NEXT: retq
;
-; AVX2-LABEL: test_ctlz_undef_i512:
+; AVX2-LABEL: test_ctlz_poison_i512:
; AVX2: # %bb.0:
; AVX2-NEXT: pushq %r15
; AVX2-NEXT: pushq %r14
@@ -3899,7 +3899,7 @@ define i32 @test_ctlz_undef_i512(i512 %a0) nounwind {
; AVX2-NEXT: popq %r15
; AVX2-NEXT: retq
;
-; AVX512F-LABEL: test_ctlz_undef_i512:
+; AVX512F-LABEL: test_ctlz_poison_i512:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovq %rdi, %xmm0
; AVX512F-NEXT: vmovq %rsi, %xmm1
@@ -3921,7 +3921,7 @@ define i32 @test_ctlz_undef_i512(i512 %a0) nounwind {
; AVX512F-NEXT: vmovd %xmm0, %eax
; AVX512F-NEXT: retq
;
-; AVX512POPCNT-LABEL: test_ctlz_undef_i512:
+; AVX512POPCNT-LABEL: test_ctlz_poison_i512:
; AVX512POPCNT: # %bb.0:
; AVX512POPCNT-NEXT: vmovq %rdi, %xmm0
; AVX512POPCNT-NEXT: vmovq %rsi, %xmm1
@@ -3943,7 +3943,7 @@ define i32 @test_ctlz_undef_i512(i512 %a0) nounwind {
; AVX512POPCNT-NEXT: vmovd %xmm0, %eax
; AVX512POPCNT-NEXT: retq
;
-; AVX512VL-LABEL: test_ctlz_undef_i512:
+; AVX512VL-LABEL: test_ctlz_poison_i512:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovq %rdi, %xmm0
; AVX512VL-NEXT: vmovq %rsi, %xmm1
@@ -3966,7 +3966,7 @@ define i32 @test_ctlz_undef_i512(i512 %a0) nounwind {
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
-; AVX512VLPOPCNT-LABEL: test_ctlz_undef_i512:
+; AVX512VLPOPCNT-LABEL: test_ctlz_poison_i512:
; AVX512VLPOPCNT: # %bb.0:
; AVX512VLPOPCNT-NEXT: vmovq %rdi, %xmm0
; AVX512VLPOPCNT-NEXT: vmovq %rsi, %xmm1
@@ -3993,8 +3993,8 @@ define i32 @test_ctlz_undef_i512(i512 %a0) nounwind {
ret i32 %res
}
-define i32 @load_ctlz_undef_i512(ptr %p0) nounwind {
-; SSE-LABEL: load_ctlz_undef_i512:
+define i32 @load_ctlz_poison_i512(ptr %p0) nounwind {
+; SSE-LABEL: load_ctlz_poison_i512:
; SSE: # %bb.0:
; SSE-NEXT: pushq %rbx
; SSE-NEXT: movdqa 32(%rdi), %xmm0
@@ -4046,7 +4046,7 @@ define i32 @load_ctlz_undef_i512(ptr %p0) nounwind {
; SSE-NEXT: popq %rbx
; SSE-NEXT: retq
;
-; AVX2-LABEL: load_ctlz_undef_i512:
+; AVX2-LABEL: load_ctlz_poison_i512:
; AVX2: # %bb.0:
; AVX2-NEXT: movq 16(%rdi), %rcx
; AVX2-NEXT: movq 24(%rdi), %rdx
@@ -4093,7 +4093,7 @@ define i32 @load_ctlz_undef_i512(ptr %p0) nounwind {
; AVX2-NEXT: # kill: def $eax killed $eax killed $rax
; AVX2-NEXT: retq
;
-; AVX512F-LABEL: load_ctlz_undef_i512:
+; AVX512F-LABEL: load_ctlz_poison_i512:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm0 = [7,6,5,4,3,2,1,0]
; AVX512F-NEXT: vpermq (%rdi), %zmm0, %zmm0
@@ -4104,7 +4104,7 @@ define i32 @load_ctlz_undef_i512(ptr %p0) nounwind {
; AVX512F-NEXT: vmovd %xmm0, %eax
; AVX512F-NEXT: retq
;
-; AVX512POPCNT-LABEL: load_ctlz_undef_i512:
+; AVX512POPCNT-LABEL: load_ctlz_poison_i512:
; AVX512POPCNT: # %bb.0:
; AVX512POPCNT-NEXT: vmovdqa64 {{.*#+}} zmm0 = [7,6,5,4,3,2,1,0]
; AVX512POPCNT-NEXT: vpermq (%rdi), %zmm0, %zmm0
@@ -4115,7 +4115,7 @@ define i32 @load_ctlz_undef_i512(ptr %p0) nounwind {
; AVX512POPCNT-NEXT: vmovd %xmm0, %eax
; AVX512POPCNT-NEXT: retq
;
-; AVX512VL-LABEL: load_ctlz_undef_i512:
+; AVX512VL-LABEL: load_ctlz_poison_i512:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa64 {{.*#+}} zmm0 = [7,6,5,4,3,2,1,0]
; AVX512VL-NEXT: vpermq (%rdi), %zmm0, %zmm0
@@ -4127,7 +4127,7 @@ define i32 @load_ctlz_undef_i512(ptr %p0) nounwind {
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
-; AVX512VLPOPCNT-LABEL: load_ctlz_undef_i512:
+; AVX512VLPOPCNT-LABEL: load_ctlz_poison_i512:
; AVX512VLPOPCNT: # %bb.0:
; AVX512VLPOPCNT-NEXT: vmovdqa64 {{.*#+}} zmm0 = [7,6,5,4,3,2,1,0]
; AVX512VLPOPCNT-NEXT: vpermq (%rdi), %zmm0, %zmm0
@@ -4144,8 +4144,8 @@ define i32 @load_ctlz_undef_i512(ptr %p0) nounwind {
ret i32 %res
}
-define i32 @vector_ctlz_undef_i512(<16 x i32> %v0) nounwind {
-; SSE-LABEL: vector_ctlz_undef_i512:
+define i32 @vector_ctlz_poison_i512(<16 x i32> %v0) nounwind {
+; SSE-LABEL: vector_ctlz_poison_i512:
; SSE: # %bb.0:
; SSE-NEXT: pextrq $1, %xmm0, %rcx
; SSE-NEXT: pextrq $1, %xmm1, %rax
@@ -4196,7 +4196,7 @@ define i32 @vector_ctlz_undef_i512(<16 x i32> %v0) nounwind {
; SSE-NEXT: # kill: def $eax killed $eax killed $rax
; SSE-NEXT: retq
;
-; AVX2-LABEL: vector_ctlz_undef_i512:
+; AVX2-LABEL: vector_ctlz_poison_i512:
; AVX2: # %bb.0:
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX2-NEXT: vpextrq $1, %xmm2, %rcx
@@ -4245,7 +4245,7 @@ define i32 @vector_ctlz_undef_i512(<16 x i32> %v0) nounwind {
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
-; AVX512F-LABEL: vector_ctlz_undef_i512:
+; AVX512F-LABEL: vector_ctlz_poison_i512:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
; AVX512F-NEXT: vpermq %zmm0, %zmm1, %zmm0
@@ -4256,7 +4256,7 @@ define i32 @vector_ctlz_undef_i512(<16 x i32> %v0) nounwind {
; AVX512F-NEXT: vmovd %xmm0, %eax
; AVX512F-NEXT: retq
;
-; AVX512POPCNT-LABEL: vector_ctlz_undef_i512:
+; AVX512POPCNT-LABEL: vector_ctlz_poison_i512:
; AVX512POPCNT: # %bb.0:
; AVX512POPCNT-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
; AVX512POPCNT-NEXT: vpermq %zmm0, %zmm1, %zmm0
@@ -4267,7 +4267,7 @@ define i32 @vector_ctlz_undef_i512(<16 x i32> %v0) nounwind {
; AVX512POPCNT-NEXT: vmovd %xmm0, %eax
; AVX512POPCNT-NEXT: retq
;
-; AVX512VL-LABEL: vector_ctlz_undef_i512:
+; AVX512VL-LABEL: vector_ctlz_poison_i512:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
; AVX512VL-NEXT: vpermq %zmm0, %zmm1, %zmm0
@@ -4279,7 +4279,7 @@ define i32 @vector_ctlz_undef_i512(<16 x i32> %v0) nounwind {
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
-; AVX512VLPOPCNT-LABEL: vector_ctlz_undef_i512:
+; AVX512VLPOPCNT-LABEL: vector_ctlz_poison_i512:
; AVX512VLPOPCNT: # %bb.0:
; AVX512VLPOPCNT-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
; AVX512VLPOPCNT-NEXT: vpermq %zmm0, %zmm1, %zmm0
@@ -4296,8 +4296,8 @@ define i32 @vector_ctlz_undef_i512(<16 x i32> %v0) nounwind {
ret i32 %res
}
-define i32 @test_ctlz_undef_i1024(i1024 %a0) nounwind {
-; SSE-LABEL: test_ctlz_undef_i1024:
+define i32 @test_ctlz_poison_i1024(i1024 %a0) nounwind {
+; SSE-LABEL: test_ctlz_poison_i1024:
; SSE: # %bb.0:
; SSE-NEXT: pushq %r14
; SSE-NEXT: pushq %rbx
@@ -4401,7 +4401,7 @@ define i32 @test_ctlz_undef_i1024(i1024 %a0) nounwind {
; SSE-NEXT: popq %r14
; SSE-NEXT: retq
;
-; AVX2-LABEL: test_ctlz_undef_i1024:
+; AVX2-LABEL: test_ctlz_poison_i1024:
; AVX2: # %bb.0:
; AVX2-NEXT: pushq %r15
; AVX2-NEXT: pushq %r14
@@ -4508,7 +4508,7 @@ define i32 @test_ctlz_undef_i1024(i1024 %a0) nounwind {
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
-; AVX512F-LABEL: test_ctlz_undef_i1024:
+; AVX512F-LABEL: test_ctlz_poison_i1024:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovdqu64 {{[0-9]+}}(%rsp), %zmm0
; AVX512F-NEXT: vmovq %rdi, %xmm1
@@ -4543,7 +4543,7 @@ define i32 @test_ctlz_undef_i1024(i1024 %a0) nounwind {
; AVX512F-NEXT: cmovel %ecx, %eax
; AVX512F-NEXT: retq
;
-; AVX512POPCNT-LABEL: test_ctlz_undef_i1024:
+; AVX512POPCNT-LABEL: test_ctlz_poison_i1024:
; AVX512POPCNT: # %bb.0:
; AVX512POPCNT-NEXT: vmovdqu64 {{[0-9]+}}(%rsp), %zmm0
; AVX512POPCNT-NEXT: vmovq %rdi, %xmm1
@@ -4578,7 +4578,7 @@ define i32 @test_ctlz_undef_i1024(i1024 %a0) nounwind {
; AVX512POPCNT-NEXT: cmovel %ecx, %eax
; AVX512POPCNT-NEXT: retq
;
-; AVX512VL-LABEL: test_ctlz_undef_i1024:
+; AVX512VL-LABEL: test_ctlz_poison_i1024:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqu64 {{[0-9]+}}(%rsp), %zmm0
; AVX512VL-NEXT: vmovq %rdi, %xmm1
@@ -4614,7 +4614,7 @@ define i32 @test_ctlz_undef_i1024(i1024 %a0) nounwind {
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
-; AVX512VLPOPCNT-LABEL: test_ctlz_undef_i1024:
+; AVX512VLPOPCNT-LABEL: test_ctlz_poison_i1024:
; AVX512VLPOPCNT: # %bb.0:
; AVX512VLPOPCNT-NEXT: vmovdqu64 {{[0-9]+}}(%rsp), %zmm0
; AVX512VLPOPCNT-NEXT: vmovq %rdi, %xmm1
@@ -4654,8 +4654,8 @@ define i32 @test_ctlz_undef_i1024(i1024 %a0) nounwind {
ret i32 %res
}
-define i32 @load_ctlz_undef_i1024(ptr %p0) nounwind {
-; SSE-LABEL: load_ctlz_undef_i1024:
+define i32 @load_ctlz_poison_i1024(ptr %p0) nounwind {
+; SSE-LABEL: load_ctlz_poison_i1024:
; SSE: # %bb.0:
; SSE-NEXT: movq 8(%rdi), %rcx
; SSE-NEXT: movq 72(%rdi), %rax
@@ -4758,7 +4758,7 @@ define i32 @load_ctlz_undef_i1024(ptr %p0) nounwind {
; SSE-NEXT: # kill: def $eax killed $eax killed $rax
; SSE-NEXT: retq
;
-; AVX2-LABEL: load_ctlz_undef_i1024:
+; AVX2-LABEL: load_ctlz_poison_i1024:
; AVX2: # %bb.0:
; AVX2-NEXT: pushq %rbx
; AVX2-NEXT: movq 16(%rdi), %rcx
@@ -4858,7 +4858,7 @@ define i32 @load_ctlz_undef_i1024(ptr %p0) nounwind {
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
-; AVX512F-LABEL: load_ctlz_undef_i1024:
+; AVX512F-LABEL: load_ctlz_poison_i1024:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovdqu64 64(%rdi), %zmm0
; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
@@ -4881,7 +4881,7 @@ define i32 @load_ctlz_undef_i1024(ptr %p0) nounwind {
; AVX512F-NEXT: cmovnel %ecx, %eax
; AVX512F-NEXT: retq
;
-; AVX512POPCNT-LABEL: load_ctlz_undef_i1024:
+; AVX512POPCNT-LABEL: load_ctlz_poison_i1024:
; AVX512POPCNT: # %bb.0:
; AVX512POPCNT-NEXT: vmovdqu64 64(%rdi), %zmm0
; AVX512POPCNT-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
@@ -4904,7 +4904,7 @@ define i32 @load_ctlz_undef_i1024(ptr %p0) nounwind {
; AVX512POPCNT-NEXT: cmovnel %ecx, %eax
; AVX512POPCNT-NEXT: retq
;
-; AVX512VL-LABEL: load_ctlz_undef_i1024:
+; AVX512VL-LABEL: load_ctlz_poison_i1024:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqu64 64(%rdi), %zmm0
; AVX512VL-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
@@ -4928,7 +4928,7 @@ define i32 @load_ctlz_undef_i1024(ptr %p0) nounwind {
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
-; AVX512VLPOPCNT-LABEL: load_ctlz_undef_i1024:
+; AVX512VLPOPCNT-LABEL: load_ctlz_poison_i1024:
; AVX512VLPOPCNT: # %bb.0:
; AVX512VLPOPCNT-NEXT: vmovdqu64 64(%rdi), %zmm0
; AVX512VLPOPCNT-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
@@ -6588,11 +6588,11 @@ define i32 @load_cttz_i1024(ptr %p0) nounwind {
}
;
-; CTTZ_ZERO_UNDEF
+; CTTZ_ZERO_POISON
;
-define i32 @test_cttz_undef_i128(i128 %a0) nounwind {
-; SSE-LABEL: test_cttz_undef_i128:
+define i32 @test_cttz_poison_i128(i128 %a0) nounwind {
+; SSE-LABEL: test_cttz_poison_i128:
; SSE: # %bb.0:
; SSE-NEXT: rep bsfq %rdi, %rcx
; SSE-NEXT: rep bsfq %rsi, %rax
@@ -6602,7 +6602,7 @@ define i32 @test_cttz_undef_i128(i128 %a0) nounwind {
; SSE-NEXT: # kill: def $eax killed $eax killed $rax
; SSE-NEXT: retq
;
-; AVX2-LABEL: test_cttz_undef_i128:
+; AVX2-LABEL: test_cttz_poison_i128:
; AVX2: # %bb.0:
; AVX2-NEXT: tzcntq %rdi, %rcx
; AVX2-NEXT: tzcntq %rsi, %rax
@@ -6612,7 +6612,7 @@ define i32 @test_cttz_undef_i128(i128 %a0) nounwind {
; AVX2-NEXT: # kill: def $eax killed $eax killed $rax
; AVX2-NEXT: retq
;
-; AVX512-LABEL: test_cttz_undef_i128:
+; AVX512-LABEL: test_cttz_poison_i128:
; AVX512: # %bb.0:
; AVX512-NEXT: tzcntq %rdi, %rcx
; AVX512-NEXT: tzcntq %rsi, %rax
@@ -6626,8 +6626,8 @@ define i32 @test_cttz_undef_i128(i128 %a0) nounwind {
ret i32 %res
}
-define i32 @load_cttz_undef_i128(ptr %p0) nounwind {
-; SSE-LABEL: load_cttz_undef_i128:
+define i32 @load_cttz_poison_i128(ptr %p0) nounwind {
+; SSE-LABEL: load_cttz_poison_i128:
; SSE: # %bb.0:
; SSE-NEXT: movq (%rdi), %rcx
; SSE-NEXT: rep bsfq %rcx, %rdx
@@ -6638,7 +6638,7 @@ define i32 @load_cttz_undef_i128(ptr %p0) nounwind {
; SSE-NEXT: # kill: def $eax killed $eax killed $rax
; SSE-NEXT: retq
;
-; AVX2-LABEL: load_cttz_undef_i128:
+; AVX2-LABEL: load_cttz_poison_i128:
; AVX2: # %bb.0:
; AVX2-NEXT: movq (%rdi), %rcx
; AVX2-NEXT: tzcntq %rcx, %rdx
@@ -6649,7 +6649,7 @@ define i32 @load_cttz_undef_i128(ptr %p0) nounwind {
; AVX2-NEXT: # kill: def $eax killed $eax killed $rax
; AVX2-NEXT: retq
;
-; AVX512-LABEL: load_cttz_undef_i128:
+; AVX512-LABEL: load_cttz_poison_i128:
; AVX512: # %bb.0:
; AVX512-NEXT: movq (%rdi), %rcx
; AVX512-NEXT: tzcntq %rcx, %rdx
@@ -6665,8 +6665,8 @@ define i32 @load_cttz_undef_i128(ptr %p0) nounwind {
ret i32 %res
}
-define i32 @vector_cttz_undef_i128(<4 x i32> %v0) nounwind {
-; SSE-LABEL: vector_cttz_undef_i128:
+define i32 @vector_cttz_poison_i128(<4 x i32> %v0) nounwind {
+; SSE-LABEL: vector_cttz_poison_i128:
; SSE: # %bb.0:
; SSE-NEXT: pextrq $1, %xmm0, %rax
; SSE-NEXT: movq %xmm0, %rcx
@@ -6678,7 +6678,7 @@ define i32 @vector_cttz_undef_i128(<4 x i32> %v0) nounwind {
; SSE-NEXT: # kill: def $eax killed $eax killed $rax
; SSE-NEXT: retq
;
-; AVX2-LABEL: vector_cttz_undef_i128:
+; AVX2-LABEL: vector_cttz_poison_i128:
; AVX2: # %bb.0:
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: vmovq %xmm0, %rcx
@@ -6690,7 +6690,7 @@ define i32 @vector_cttz_undef_i128(<4 x i32> %v0) nounwind {
; AVX2-NEXT: # kill: def $eax killed $eax killed $rax
; AVX2-NEXT: retq
;
-; AVX512-LABEL: vector_cttz_undef_i128:
+; AVX512-LABEL: vector_cttz_poison_i128:
; AVX512: # %bb.0:
; AVX512-NEXT: vpextrq $1, %xmm0, %rax
; AVX512-NEXT: vmovq %xmm0, %rcx
@@ -6707,8 +6707,8 @@ define i32 @vector_cttz_undef_i128(<4 x i32> %v0) nounwind {
ret i32 %res
}
-define i32 @test_cttz_undef_i256(i256 %a0) nounwind {
-; SSE-LABEL: test_cttz_undef_i256:
+define i32 @test_cttz_poison_i256(i256 %a0) nounwind {
+; SSE-LABEL: test_cttz_poison_i256:
; SSE: # %bb.0:
; SSE-NEXT: rep bsfq %rdi, %rax
; SSE-NEXT: rep bsfq %rsi, %r8
@@ -6726,7 +6726,7 @@ define i32 @test_cttz_undef_i256(i256 %a0) nounwind {
; SSE-NEXT: # kill: def $eax killed $eax killed $rax
; SSE-NEXT: retq
;
-; AVX2-LABEL: test_cttz_undef_i256:
+; AVX2-LABEL: test_cttz_poison_i256:
; AVX2: # %bb.0:
; AVX2-NEXT: tzcntq %rdi, %rax
; AVX2-NEXT: tzcntq %rsi, %r8
@@ -6745,7 +6745,7 @@ define i32 @test_cttz_undef_i256(i256 %a0) nounwind {
; AVX2-NEXT: # kill: def $eax killed $eax killed $rax
; AVX2-NEXT: retq
;
-; AVX512-LABEL: test_cttz_undef_i256:
+; AVX512-LABEL: test_cttz_poison_i256:
; AVX512: # %bb.0:
; AVX512-NEXT: tzcntq %rdi, %rax
; AVX512-NEXT: tzcntq %rsi, %r8
@@ -6767,8 +6767,8 @@ define i32 @test_cttz_undef_i256(i256 %a0) nounwind {
ret i32 %res
}
-define i32 @load_cttz_undef_i256(ptr %p0) nounwind {
-; SSE-LABEL: load_cttz_undef_i256:
+define i32 @load_cttz_poison_i256(ptr %p0) nounwind {
+; SSE-LABEL: load_cttz_poison_i256:
; SSE: # %bb.0:
; SSE-NEXT: movq 16(%rdi), %rcx
; SSE-NEXT: movq (%rdi), %rdx
@@ -6789,7 +6789,7 @@ define i32 @load_cttz_undef_i256(ptr %p0) nounwind {
; SSE-NEXT: # kill: def $eax killed $eax killed $rax
; SSE-NEXT: retq
;
-; AVX2-LABEL: load_cttz_undef_i256:
+; AVX2-LABEL: load_cttz_poison_i256:
; AVX2: # %bb.0:
; AVX2-NEXT: movq (%rdi), %rcx
; AVX2-NEXT: movq 8(%rdi), %rdx
@@ -6811,7 +6811,7 @@ define i32 @load_cttz_undef_i256(ptr %p0) nounwind {
; AVX2-NEXT: # kill: def $eax killed $eax killed $rax
; AVX2-NEXT: retq
;
-; AVX512F-LABEL: load_cttz_undef_i256:
+; AVX512F-LABEL: load_cttz_poison_i256:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovdqu (%rdi), %ymm0
; AVX512F-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
@@ -6827,7 +6827,7 @@ define i32 @load_cttz_undef_i256(ptr %p0) nounwind {
; AVX512F-NEXT: vmovd %xmm0, %eax
; AVX512F-NEXT: retq
;
-; AVX512POPCNT-LABEL: load_cttz_undef_i256:
+; AVX512POPCNT-LABEL: load_cttz_poison_i256:
; AVX512POPCNT: # %bb.0:
; AVX512POPCNT-NEXT: vmovdqu (%rdi), %ymm0
; AVX512POPCNT-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
@@ -6842,7 +6842,7 @@ define i32 @load_cttz_undef_i256(ptr %p0) nounwind {
; AVX512POPCNT-NEXT: vmovd %xmm0, %eax
; AVX512POPCNT-NEXT: retq
;
-; AVX512VL-LABEL: load_cttz_undef_i256:
+; AVX512VL-LABEL: load_cttz_poison_i256:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqu (%rdi), %ymm0
; AVX512VL-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
@@ -6857,7 +6857,7 @@ define i32 @load_cttz_undef_i256(ptr %p0) nounwind {
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
-; AVX512VLPOPCNT-LABEL: load_cttz_undef_i256:
+; AVX512VLPOPCNT-LABEL: load_cttz_poison_i256:
; AVX512VLPOPCNT: # %bb.0:
; AVX512VLPOPCNT-NEXT: vmovdqu (%rdi), %ymm0
; AVX512VLPOPCNT-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
@@ -6876,8 +6876,8 @@ define i32 @load_cttz_undef_i256(ptr %p0) nounwind {
ret i32 %res
}
-define i32 @vector_cttz_undef_i256(<8 x i32> %v0) nounwind {
-; SSE-LABEL: vector_cttz_undef_i256:
+define i32 @vector_cttz_poison_i256(<8 x i32> %v0) nounwind {
+; SSE-LABEL: vector_cttz_poison_i256:
; SSE: # %bb.0:
; SSE-NEXT: pextrq $1, %xmm1, %rax
; SSE-NEXT: movq %xmm1, %rcx
@@ -6899,7 +6899,7 @@ define i32 @vector_cttz_undef_i256(<8 x i32> %v0) nounwind {
; SSE-NEXT: # kill: def $eax killed $eax killed $rax
; SSE-NEXT: retq
;
-; AVX2-LABEL: vector_cttz_undef_i256:
+; AVX2-LABEL: vector_cttz_poison_i256:
; AVX2: # %bb.0:
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpextrq $1, %xmm1, %rax
@@ -6924,7 +6924,7 @@ define i32 @vector_cttz_undef_i256(<8 x i32> %v0) nounwind {
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
-; AVX512F-LABEL: vector_cttz_undef_i256:
+; AVX512F-LABEL: vector_cttz_poison_i256:
; AVX512F: # %bb.0:
; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512F-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
@@ -6940,7 +6940,7 @@ define i32 @vector_cttz_undef_i256(<8 x i32> %v0) nounwind {
; AVX512F-NEXT: vmovd %xmm0, %eax
; AVX512F-NEXT: retq
;
-; AVX512POPCNT-LABEL: vector_cttz_undef_i256:
+; AVX512POPCNT-LABEL: vector_cttz_poison_i256:
; AVX512POPCNT: # %bb.0:
; AVX512POPCNT-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512POPCNT-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
@@ -6955,7 +6955,7 @@ define i32 @vector_cttz_undef_i256(<8 x i32> %v0) nounwind {
; AVX512POPCNT-NEXT: vmovd %xmm0, %eax
; AVX512POPCNT-NEXT: retq
;
-; AVX512VL-LABEL: vector_cttz_undef_i256:
+; AVX512VL-LABEL: vector_cttz_poison_i256:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX512VL-NEXT: vpaddq %ymm1, %ymm0, %ymm1
@@ -6969,7 +6969,7 @@ define i32 @vector_cttz_undef_i256(<8 x i32> %v0) nounwind {
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
-; AVX512VLPOPCNT-LABEL: vector_cttz_undef_i256:
+; AVX512VLPOPCNT-LABEL: vector_cttz_poison_i256:
; AVX512VLPOPCNT: # %bb.0:
; AVX512VLPOPCNT-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX512VLPOPCNT-NEXT: vpaddq %ymm1, %ymm0, %ymm1
@@ -6987,8 +6987,8 @@ define i32 @vector_cttz_undef_i256(<8 x i32> %v0) nounwind {
ret i32 %res
}
-define i32 @test_cttz_undef_i512(i512 %a0) nounwind {
-; SSE-LABEL: test_cttz_undef_i512:
+define i32 @test_cttz_poison_i512(i512 %a0) nounwind {
+; SSE-LABEL: test_cttz_poison_i512:
; SSE: # %bb.0:
; SSE-NEXT: pushq %r14
; SSE-NEXT: pushq %rbx
@@ -7030,7 +7030,7 @@ define i32 @test_cttz_undef_i512(i512 %a0) nounwind {
; SSE-NEXT: popq %r14
; SSE-NEXT: retq
;
-; AVX2-LABEL: test_cttz_undef_i512:
+; AVX2-LABEL: test_cttz_poison_i512:
; AVX2: # %bb.0:
; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %rbx
@@ -7077,7 +7077,7 @@ define i32 @test_cttz_undef_i512(i512 %a0) nounwind {
; AVX2-NEXT: popq %r14
; AVX2-NEXT: retq
;
-; AVX512F-LABEL: test_cttz_undef_i512:
+; AVX512F-LABEL: test_cttz_poison_i512:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovq %rcx, %xmm0
; AVX512F-NEXT: vmovq %rdx, %xmm1
@@ -7102,7 +7102,7 @@ define i32 @test_cttz_undef_i512(i512 %a0) nounwind {
; AVX512F-NEXT: vmovd %xmm0, %eax
; AVX512F-NEXT: retq
;
-; AVX512POPCNT-LABEL: test_cttz_undef_i512:
+; AVX512POPCNT-LABEL: test_cttz_poison_i512:
; AVX512POPCNT: # %bb.0:
; AVX512POPCNT-NEXT: vmovq %rcx, %xmm0
; AVX512POPCNT-NEXT: vmovq %rdx, %xmm1
@@ -7126,7 +7126,7 @@ define i32 @test_cttz_undef_i512(i512 %a0) nounwind {
; AVX512POPCNT-NEXT: vmovd %xmm0, %eax
; AVX512POPCNT-NEXT: retq
;
-; AVX512VL-LABEL: test_cttz_undef_i512:
+; AVX512VL-LABEL: test_cttz_poison_i512:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovq %rcx, %xmm0
; AVX512VL-NEXT: vmovq %rdx, %xmm1
@@ -7152,7 +7152,7 @@ define i32 @test_cttz_undef_i512(i512 %a0) nounwind {
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
-; AVX512VLPOPCNT-LABEL: test_cttz_undef_i512:
+; AVX512VLPOPCNT-LABEL: test_cttz_poison_i512:
; AVX512VLPOPCNT: # %bb.0:
; AVX512VLPOPCNT-NEXT: vmovq %rcx, %xmm0
; AVX512VLPOPCNT-NEXT: vmovq %rdx, %xmm1
@@ -7181,8 +7181,8 @@ define i32 @test_cttz_undef_i512(i512 %a0) nounwind {
ret i32 %res
}
-define i32 @load_cttz_undef_i512(ptr %p0) nounwind {
-; SSE-LABEL: load_cttz_undef_i512:
+define i32 @load_cttz_poison_i512(ptr %p0) nounwind {
+; SSE-LABEL: load_cttz_poison_i512:
; SSE: # %bb.0:
; SSE-NEXT: pushq %rbx
; SSE-NEXT: movdqa (%rdi), %xmm0
@@ -7226,7 +7226,7 @@ define i32 @load_cttz_undef_i512(ptr %p0) nounwind {
; SSE-NEXT: popq %rbx
; SSE-NEXT: retq
;
-; AVX2-LABEL: load_cttz_undef_i512:
+; AVX2-LABEL: load_cttz_poison_i512:
; AVX2: # %bb.0:
; AVX2-NEXT: movq 40(%rdi), %rcx
; AVX2-NEXT: movq 32(%rdi), %rdx
@@ -7273,7 +7273,7 @@ define i32 @load_cttz_undef_i512(ptr %p0) nounwind {
; AVX2-NEXT: # kill: def $eax killed $eax killed $rax
; AVX2-NEXT: retq
;
-; AVX512F-LABEL: load_cttz_undef_i512:
+; AVX512F-LABEL: load_cttz_poison_i512:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0
; AVX512F-NEXT: vpternlogd {{.*#+}} zmm1 = -1
@@ -7287,7 +7287,7 @@ define i32 @load_cttz_undef_i512(ptr %p0) nounwind {
; AVX512F-NEXT: vmovd %xmm0, %eax
; AVX512F-NEXT: retq
;
-; AVX512POPCNT-LABEL: load_cttz_undef_i512:
+; AVX512POPCNT-LABEL: load_cttz_poison_i512:
; AVX512POPCNT: # %bb.0:
; AVX512POPCNT-NEXT: vmovdqu64 (%rdi), %zmm0
; AVX512POPCNT-NEXT: vpternlogd {{.*#+}} zmm1 = -1
@@ -7300,7 +7300,7 @@ define i32 @load_cttz_undef_i512(ptr %p0) nounwind {
; AVX512POPCNT-NEXT: vmovd %xmm0, %eax
; AVX512POPCNT-NEXT: retq
;
-; AVX512VL-LABEL: load_cttz_undef_i512:
+; AVX512VL-LABEL: load_cttz_poison_i512:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqu64 (%rdi), %zmm0
; AVX512VL-NEXT: vpternlogd {{.*#+}} zmm1 = -1
@@ -7315,7 +7315,7 @@ define i32 @load_cttz_undef_i512(ptr %p0) nounwind {
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
-; AVX512VLPOPCNT-LABEL: load_cttz_undef_i512:
+; AVX512VLPOPCNT-LABEL: load_cttz_poison_i512:
; AVX512VLPOPCNT: # %bb.0:
; AVX512VLPOPCNT-NEXT: vmovdqu64 (%rdi), %zmm0
; AVX512VLPOPCNT-NEXT: vpternlogd {{.*#+}} zmm1 = -1
@@ -7334,8 +7334,8 @@ define i32 @load_cttz_undef_i512(ptr %p0) nounwind {
ret i32 %res
}
-define i32 @vector_cttz_undef_i512(<16 x i32> %v0) nounwind {
-; SSE-LABEL: vector_cttz_undef_i512:
+define i32 @vector_cttz_poison_i512(<16 x i32> %v0) nounwind {
+; SSE-LABEL: vector_cttz_poison_i512:
; SSE: # %bb.0:
; SSE-NEXT: pextrq $1, %xmm3, %rax
; SSE-NEXT: pextrq $1, %xmm2, %rdx
@@ -7378,7 +7378,7 @@ define i32 @vector_cttz_undef_i512(<16 x i32> %v0) nounwind {
; SSE-NEXT: # kill: def $eax killed $eax killed $rax
; SSE-NEXT: retq
;
-; AVX2-LABEL: vector_cttz_undef_i512:
+; AVX2-LABEL: vector_cttz_poison_i512:
; AVX2: # %bb.0:
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2-NEXT: vpextrq $1, %xmm2, %rax
@@ -7427,7 +7427,7 @@ define i32 @vector_cttz_undef_i512(<16 x i32> %v0) nounwind {
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
-; AVX512F-LABEL: vector_cttz_undef_i512:
+; AVX512F-LABEL: vector_cttz_poison_i512:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpternlogd {{.*#+}} zmm1 = -1
; AVX512F-NEXT: vpaddq %zmm1, %zmm0, %zmm1
@@ -7440,7 +7440,7 @@ define i32 @vector_cttz_undef_i512(<16 x i32> %v0) nounwind {
; AVX512F-NEXT: vmovd %xmm0, %eax
; AVX512F-NEXT: retq
;
-; AVX512POPCNT-LABEL: vector_cttz_undef_i512:
+; AVX512POPCNT-LABEL: vector_cttz_poison_i512:
; AVX512POPCNT: # %bb.0:
; AVX512POPCNT-NEXT: vpternlogd {{.*#+}} zmm1 = -1
; AVX512POPCNT-NEXT: vpaddq %zmm1, %zmm0, %zmm1
@@ -7452,7 +7452,7 @@ define i32 @vector_cttz_undef_i512(<16 x i32> %v0) nounwind {
; AVX512POPCNT-NEXT: vmovd %xmm0, %eax
; AVX512POPCNT-NEXT: retq
;
-; AVX512VL-LABEL: vector_cttz_undef_i512:
+; AVX512VL-LABEL: vector_cttz_poison_i512:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpternlogd {{.*#+}} zmm1 = -1
; AVX512VL-NEXT: vpaddq %zmm1, %zmm0, %zmm1
@@ -7466,7 +7466,7 @@ define i32 @vector_cttz_undef_i512(<16 x i32> %v0) nounwind {
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
-; AVX512VLPOPCNT-LABEL: vector_cttz_undef_i512:
+; AVX512VLPOPCNT-LABEL: vector_cttz_poison_i512:
; AVX512VLPOPCNT: # %bb.0:
; AVX512VLPOPCNT-NEXT: vpternlogd {{.*#+}} zmm1 = -1
; AVX512VLPOPCNT-NEXT: vpaddq %zmm1, %zmm0, %zmm1
@@ -7484,8 +7484,8 @@ define i32 @vector_cttz_undef_i512(<16 x i32> %v0) nounwind {
ret i32 %res
}
-define i32 @test_cttz_undef_i1024(i1024 %a0) nounwind {
-; SSE-LABEL: test_cttz_undef_i1024:
+define i32 @test_cttz_poison_i1024(i1024 %a0) nounwind {
+; SSE-LABEL: test_cttz_poison_i1024:
; SSE: # %bb.0:
; SSE-NEXT: pushq %rbp
; SSE-NEXT: pushq %r15
@@ -7588,7 +7588,7 @@ define i32 @test_cttz_undef_i1024(i1024 %a0) nounwind {
; SSE-NEXT: popq %rbp
; SSE-NEXT: retq
;
-; AVX2-LABEL: test_cttz_undef_i1024:
+; AVX2-LABEL: test_cttz_poison_i1024:
; AVX2: # %bb.0:
; AVX2-NEXT: pushq %rbp
; AVX2-NEXT: pushq %r15
@@ -7707,7 +7707,7 @@ define i32 @test_cttz_undef_i1024(i1024 %a0) nounwind {
; AVX2-NEXT: popq %rbp
; AVX2-NEXT: retq
;
-; AVX512F-LABEL: test_cttz_undef_i1024:
+; AVX512F-LABEL: test_cttz_poison_i1024:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovq %rcx, %xmm0
; AVX512F-NEXT: vmovq %rdx, %xmm1
@@ -7749,7 +7749,7 @@ define i32 @test_cttz_undef_i1024(i1024 %a0) nounwind {
; AVX512F-NEXT: cmovnel %r10d, %eax
; AVX512F-NEXT: retq
;
-; AVX512POPCNT-LABEL: test_cttz_undef_i1024:
+; AVX512POPCNT-LABEL: test_cttz_poison_i1024:
; AVX512POPCNT: # %bb.0:
; AVX512POPCNT-NEXT: vmovq %rcx, %xmm0
; AVX512POPCNT-NEXT: vmovq %rdx, %xmm1
@@ -7791,7 +7791,7 @@ define i32 @test_cttz_undef_i1024(i1024 %a0) nounwind {
; AVX512POPCNT-NEXT: cmovnel %r10d, %eax
; AVX512POPCNT-NEXT: retq
;
-; AVX512VL-LABEL: test_cttz_undef_i1024:
+; AVX512VL-LABEL: test_cttz_poison_i1024:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovq %rcx, %xmm0
; AVX512VL-NEXT: vmovq %rdx, %xmm1
@@ -7834,7 +7834,7 @@ define i32 @test_cttz_undef_i1024(i1024 %a0) nounwind {
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
-; AVX512VLPOPCNT-LABEL: test_cttz_undef_i1024:
+; AVX512VLPOPCNT-LABEL: test_cttz_poison_i1024:
; AVX512VLPOPCNT: # %bb.0:
; AVX512VLPOPCNT-NEXT: vmovq %rcx, %xmm0
; AVX512VLPOPCNT-NEXT: vmovq %rdx, %xmm1
@@ -7881,8 +7881,8 @@ define i32 @test_cttz_undef_i1024(i1024 %a0) nounwind {
ret i32 %res
}
-define i32 @load_cttz_undef_i1024(ptr %p0) nounwind {
-; SSE-LABEL: load_cttz_undef_i1024:
+define i32 @load_cttz_poison_i1024(ptr %p0) nounwind {
+; SSE-LABEL: load_cttz_poison_i1024:
; SSE: # %bb.0:
; SSE-NEXT: pushq %rbx
; SSE-NEXT: movq 104(%rdi), %rcx
@@ -7971,7 +7971,7 @@ define i32 @load_cttz_undef_i1024(ptr %p0) nounwind {
; SSE-NEXT: popq %rbx
; SSE-NEXT: retq
;
-; AVX2-LABEL: load_cttz_undef_i1024:
+; AVX2-LABEL: load_cttz_poison_i1024:
; AVX2: # %bb.0:
; AVX2-NEXT: pushq %rbx
; AVX2-NEXT: movq 104(%rdi), %rcx
@@ -8071,7 +8071,7 @@ define i32 @load_cttz_undef_i1024(ptr %p0) nounwind {
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
-; AVX512F-LABEL: load_cttz_undef_i1024:
+; AVX512F-LABEL: load_cttz_poison_i1024:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0
; AVX512F-NEXT: vmovdqu64 64(%rdi), %zmm1
@@ -8097,7 +8097,7 @@ define i32 @load_cttz_undef_i1024(ptr %p0) nounwind {
; AVX512F-NEXT: cmovnel %ecx, %eax
; AVX512F-NEXT: retq
;
-; AVX512POPCNT-LABEL: load_cttz_undef_i1024:
+; AVX512POPCNT-LABEL: load_cttz_poison_i1024:
; AVX512POPCNT: # %bb.0:
; AVX512POPCNT-NEXT: vmovdqu64 (%rdi), %zmm0
; AVX512POPCNT-NEXT: vmovdqu64 64(%rdi), %zmm1
@@ -8123,7 +8123,7 @@ define i32 @load_cttz_undef_i1024(ptr %p0) nounwind {
; AVX512POPCNT-NEXT: cmovnel %ecx, %eax
; AVX512POPCNT-NEXT: retq
;
-; AVX512VL-LABEL: load_cttz_undef_i1024:
+; AVX512VL-LABEL: load_cttz_poison_i1024:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqu64 (%rdi), %zmm0
; AVX512VL-NEXT: vmovdqu64 64(%rdi), %zmm1
@@ -8150,7 +8150,7 @@ define i32 @load_cttz_undef_i1024(ptr %p0) nounwind {
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
-; AVX512VLPOPCNT-LABEL: load_cttz_undef_i1024:
+; AVX512VLPOPCNT-LABEL: load_cttz_poison_i1024:
; AVX512VLPOPCNT: # %bb.0:
; AVX512VLPOPCNT-NEXT: vmovdqu64 (%rdi), %zmm0
; AVX512VLPOPCNT-NEXT: vmovdqu64 64(%rdi), %zmm1
diff --git a/llvm/test/CodeGen/X86/freeze-unary.ll b/llvm/test/CodeGen/X86/freeze-unary.ll
index 03b003f52ffd6..56b0ceb34fe18 100644
--- a/llvm/test/CodeGen/X86/freeze-unary.ll
+++ b/llvm/test/CodeGen/X86/freeze-unary.ll
@@ -110,8 +110,8 @@ define <4 x i32> @freeze_abs_vec(<4 x i32> %a0) nounwind {
ret <4 x i32> %r
}
-define i32 @freeze_abs_undef(i32 %a0) nounwind {
-; X86-LABEL: freeze_abs_undef:
+define i32 @freeze_abs_poison(i32 %a0) nounwind {
+; X86-LABEL: freeze_abs_poison:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl %ecx, %eax
@@ -119,7 +119,7 @@ define i32 @freeze_abs_undef(i32 %a0) nounwind {
; X86-NEXT: cmovsl %ecx, %eax
; X86-NEXT: retl
;
-; X64-LABEL: freeze_abs_undef:
+; X64-LABEL: freeze_abs_poison:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
; X64-NEXT: negl %eax
@@ -131,8 +131,8 @@ define i32 @freeze_abs_undef(i32 %a0) nounwind {
ret i32 %r
}
-define <4 x i32> @freeze_abs_undef_vec(<4 x i32> %a0) nounwind {
-; X86-LABEL: freeze_abs_undef_vec:
+define <4 x i32> @freeze_abs_poison_vec(<4 x i32> %a0) nounwind {
+; X86-LABEL: freeze_abs_poison_vec:
; X86: # %bb.0:
; X86-NEXT: movdqa %xmm0, %xmm1
; X86-NEXT: psrad $31, %xmm1
@@ -140,7 +140,7 @@ define <4 x i32> @freeze_abs_undef_vec(<4 x i32> %a0) nounwind {
; X86-NEXT: psubd %xmm1, %xmm0
; X86-NEXT: retl
;
-; X64-LABEL: freeze_abs_undef_vec:
+; X64-LABEL: freeze_abs_poison_vec:
; X64: # %bb.0:
; X64-NEXT: pabsd %xmm0, %xmm0
; X64-NEXT: retq
@@ -228,8 +228,8 @@ define i32 @freeze_ctlz(i32 %a0) nounwind {
ret i32 %r
}
-define i32 @freeze_ctlz_undef(i32 %a0) nounwind {
-; X86-LABEL: freeze_ctlz_undef:
+define i32 @freeze_ctlz_poison(i32 %a0) nounwind {
+; X86-LABEL: freeze_ctlz_poison:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: bsrl %eax, %ecx
@@ -239,7 +239,7 @@ define i32 @freeze_ctlz_undef(i32 %a0) nounwind {
; X86-NEXT: cmovnel %ecx, %eax
; X86-NEXT: retl
;
-; X64-LABEL: freeze_ctlz_undef:
+; X64-LABEL: freeze_ctlz_poison:
; X64: # %bb.0:
; X64-NEXT: bsrl %edi, %ecx
; X64-NEXT: xorl $31, %ecx
@@ -254,8 +254,8 @@ define i32 @freeze_ctlz_undef(i32 %a0) nounwind {
ret i32 %r
}
-define i32 @freeze_ctlz_undef_nonzero(i32 %a0) nounwind {
-; X86-LABEL: freeze_ctlz_undef_nonzero:
+define i32 @freeze_ctlz_poison_nonzero(i32 %a0) nounwind {
+; X86-LABEL: freeze_ctlz_poison_nonzero:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: orl $1, %eax
@@ -263,7 +263,7 @@ define i32 @freeze_ctlz_undef_nonzero(i32 %a0) nounwind {
; X86-NEXT: xorl $31, %eax
; X86-NEXT: retl
;
-; X64-LABEL: freeze_ctlz_undef_nonzero:
+; X64-LABEL: freeze_ctlz_poison_nonzero:
; X64: # %bb.0:
; X64-NEXT: orl $1, %edi
; X64-NEXT: bsrl %edi, %eax
@@ -297,8 +297,8 @@ define i32 @freeze_cttz(i32 %a0) nounwind {
ret i32 %r
}
-define i32 @freeze_cttz_undef(i32 %a0) nounwind {
-; X86-LABEL: freeze_cttz_undef:
+define i32 @freeze_cttz_poison(i32 %a0) nounwind {
+; X86-LABEL: freeze_cttz_poison:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: bsfl %eax, %ecx
@@ -306,7 +306,7 @@ define i32 @freeze_cttz_undef(i32 %a0) nounwind {
; X86-NEXT: cmovnel %ecx, %eax
; X86-NEXT: retl
;
-; X64-LABEL: freeze_cttz_undef:
+; X64-LABEL: freeze_cttz_poison:
; X64: # %bb.0:
; X64-NEXT: bsfl %edi, %ecx
; X64-NEXT: movl $32, %eax
@@ -319,15 +319,15 @@ define i32 @freeze_cttz_undef(i32 %a0) nounwind {
ret i32 %r
}
-define i32 @freeze_cttz_undef_nonzero(i32 %a0) nounwind {
-; X86-LABEL: freeze_cttz_undef_nonzero:
+define i32 @freeze_cttz_poison_nonzero(i32 %a0) nounwind {
+; X86-LABEL: freeze_cttz_poison_nonzero:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: orl $1, %eax
; X86-NEXT: rep bsfl %eax, %eax
; X86-NEXT: retl
;
-; X64-LABEL: freeze_cttz_undef_nonzero:
+; X64-LABEL: freeze_cttz_poison_nonzero:
; X64: # %bb.0:
; X64-NEXT: orl $1, %edi
; X64-NEXT: rep bsfl %edi, %eax
diff --git a/llvm/test/CodeGen/X86/known-never-zero.ll b/llvm/test/CodeGen/X86/known-never-zero.ll
index 910f1375ed1ca..496b97f9e17e1 100644
--- a/llvm/test/CodeGen/X86/known-never-zero.ll
+++ b/llvm/test/CodeGen/X86/known-never-zero.ll
@@ -3,7 +3,7 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=X64
;; Use cttz to test if we properly prove never-zero. There is a very
-;; simple transform from cttz -> cttz_zero_undef if its operand is
+;; simple transform from cttz -> cttz_zero_poison if its operand is
;; known never zero.
define i32 @or_known_nonzero(i32 %x) {
diff --git a/llvm/test/CodeGen/X86/widen_bitcnt.ll b/llvm/test/CodeGen/X86/widen_bitcnt.ll
index 56001468898e4..6635d9a7030dc 100644
--- a/llvm/test/CodeGen/X86/widen_bitcnt.ll
+++ b/llvm/test/CodeGen/X86/widen_bitcnt.ll
@@ -670,11 +670,11 @@ define <8 x i32> @widen_ctlz_v2i32_v8i32(<2 x i32> %a0, <2 x i32> %a1, <2 x i32>
}
;
-; CTLZ_ZERO_UNDEF
+; CTLZ_ZERO_POISON
;
-define <4 x i32> @widen_ctlz_undef_v2i32_v4i32(<2 x i32> %a0, <2 x i32> %a1) {
-; SSE42-LABEL: widen_ctlz_undef_v2i32_v4i32:
+define <4 x i32> @widen_ctlz_poison_v2i32_v4i32(<2 x i32> %a0, <2 x i32> %a1) {
+; SSE42-LABEL: widen_ctlz_poison_v2i32_v4i32:
; SSE42: # %bb.0:
; SSE42-NEXT: movq {{.*#+}} xmm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; SSE42-NEXT: movdqa %xmm3, %xmm6
@@ -723,7 +723,7 @@ define <4 x i32> @widen_ctlz_undef_v2i32_v4i32(<2 x i32> %a0, <2 x i32> %a1) {
; SSE42-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm5[0]
; SSE42-NEXT: retq
;
-; AVX2-LABEL: widen_ctlz_undef_v2i32_v4i32:
+; AVX2-LABEL: widen_ctlz_poison_v2i32_v4i32:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovq {{.*#+}} xmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX2-NEXT: vpshufb %xmm0, %xmm2, %xmm3
@@ -765,7 +765,7 @@ define <4 x i32> @widen_ctlz_undef_v2i32_v4i32(<2 x i32> %a0, <2 x i32> %a1) {
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX2-NEXT: retq
;
-; AVX512-LABEL: widen_ctlz_undef_v2i32_v4i32:
+; AVX512-LABEL: widen_ctlz_poison_v2i32_v4i32:
; AVX512: # %bb.0:
; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512-NEXT: vplzcntd %xmm0, %xmm0
@@ -776,8 +776,8 @@ define <4 x i32> @widen_ctlz_undef_v2i32_v4i32(<2 x i32> %a0, <2 x i32> %a1) {
ret <4 x i32> %res
}
-define <8 x i32> @widen_ctlz_undef_v4i32_v8i32(<4 x i32> %a0, <4 x i32> %a1) {
-; SSE42-LABEL: widen_ctlz_undef_v4i32_v8i32:
+define <8 x i32> @widen_ctlz_poison_v4i32_v8i32(<4 x i32> %a0, <4 x i32> %a1) {
+; SSE42-LABEL: widen_ctlz_poison_v4i32_v8i32:
; SSE42: # %bb.0:
; SSE42-NEXT: movq {{.*#+}} xmm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; SSE42-NEXT: movdqa %xmm3, %xmm6
@@ -825,7 +825,7 @@ define <8 x i32> @widen_ctlz_undef_v4i32_v8i32(<4 x i32> %a0, <4 x i32> %a1) {
; SSE42-NEXT: paddd %xmm6, %xmm1
; SSE42-NEXT: retq
;
-; AVX2-LABEL: widen_ctlz_undef_v4i32_v8i32:
+; AVX2-LABEL: widen_ctlz_poison_v4i32_v8i32:
; AVX2: # %bb.0:
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
@@ -851,7 +851,7 @@ define <8 x i32> @widen_ctlz_undef_v4i32_v8i32(<4 x i32> %a0, <4 x i32> %a1) {
; AVX2-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq
;
-; AVX512-LABEL: widen_ctlz_undef_v4i32_v8i32:
+; AVX512-LABEL: widen_ctlz_poison_v4i32_v8i32:
; AVX512: # %bb.0:
; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
@@ -863,8 +863,8 @@ define <8 x i32> @widen_ctlz_undef_v4i32_v8i32(<4 x i32> %a0, <4 x i32> %a1) {
ret <8 x i32> %res
}
-define <8 x i32> @widen_ctlz_undef_v2i32_v8i32(<2 x i32> %a0, <2 x i32> %a1, <2 x i32> %a2, <2 x i32> %a3) {
-; SSE42-LABEL: widen_ctlz_undef_v2i32_v8i32:
+define <8 x i32> @widen_ctlz_poison_v2i32_v8i32(<2 x i32> %a0, <2 x i32> %a1, <2 x i32> %a2, <2 x i32> %a3) {
+; SSE42-LABEL: widen_ctlz_poison_v2i32_v8i32:
; SSE42: # %bb.0:
; SSE42-NEXT: movq {{.*#+}} xmm5 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; SSE42-NEXT: movdqa %xmm5, %xmm8
@@ -956,7 +956,7 @@ define <8 x i32> @widen_ctlz_undef_v2i32_v8i32(<2 x i32> %a0, <2 x i32> %a1, <2
; SSE42-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; SSE42-NEXT: retq
;
-; AVX2-LABEL: widen_ctlz_undef_v2i32_v8i32:
+; AVX2-LABEL: widen_ctlz_poison_v2i32_v8i32:
; AVX2: # %bb.0:
; AVX2-NEXT: # kill: def $xmm1 killed $xmm1 def $ymm1
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
@@ -1003,7 +1003,7 @@ define <8 x i32> @widen_ctlz_undef_v2i32_v8i32(<2 x i32> %a0, <2 x i32> %a1, <2
; AVX2-NEXT: vpunpcklqdq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
; AVX2-NEXT: retq
;
-; AVX512-LABEL: widen_ctlz_undef_v2i32_v8i32:
+; AVX512-LABEL: widen_ctlz_poison_v2i32_v8i32:
; AVX512: # %bb.0:
; AVX512-NEXT: # kill: def $xmm1 killed $xmm1 def $ymm1
; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
@@ -1353,11 +1353,11 @@ define <8 x i32> @widen_cttz_v2i32_v8i32(<2 x i32> %a0, <2 x i32> %a1, <2 x i32>
}
;
-; CTTZ_ZERO_UNDEF
+; CTTZ_ZERO_POISON
;
-define <4 x i32> @widen_cttz_undef_v2i32_v4i32(<2 x i32> %a0, <2 x i32> %a1) {
-; SSE42-LABEL: widen_cttz_undef_v2i32_v4i32:
+define <4 x i32> @widen_cttz_poison_v2i32_v4i32(<2 x i32> %a0, <2 x i32> %a1) {
+; SSE42-LABEL: widen_cttz_poison_v2i32_v4i32:
; SSE42: # %bb.0:
; SSE42-NEXT: pcmpeqd %xmm2, %xmm2
; SSE42-NEXT: movdqa %xmm0, %xmm3
@@ -1392,7 +1392,7 @@ define <4 x i32> @widen_cttz_undef_v2i32_v4i32(<2 x i32> %a0, <2 x i32> %a1) {
; SSE42-NEXT: packuswb %xmm1, %xmm0
; SSE42-NEXT: retq
;
-; AVX2-LABEL: widen_cttz_undef_v2i32_v4i32:
+; AVX2-LABEL: widen_cttz_poison_v2i32_v4i32:
; AVX2: # %bb.0:
; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpaddd %xmm2, %xmm0, %xmm3
@@ -1421,7 +1421,7 @@ define <4 x i32> @widen_cttz_undef_v2i32_v4i32(<2 x i32> %a0, <2 x i32> %a1) {
; AVX2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
-; AVX512VL-LABEL: widen_cttz_undef_v2i32_v4i32:
+; AVX512VL-LABEL: widen_cttz_poison_v2i32_v4i32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
; AVX512VL-NEXT: vpaddd %xmm2, %xmm0, %xmm3
@@ -1434,7 +1434,7 @@ define <4 x i32> @widen_cttz_undef_v2i32_v4i32(<2 x i32> %a0, <2 x i32> %a1) {
; AVX512VL-NEXT: vpsubd %xmm0, %xmm3, %xmm0
; AVX512VL-NEXT: retq
;
-; AVX512VPOPCNT-LABEL: widen_cttz_undef_v2i32_v4i32:
+; AVX512VPOPCNT-LABEL: widen_cttz_poison_v2i32_v4i32:
; AVX512VPOPCNT: # %bb.0:
; AVX512VPOPCNT-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
; AVX512VPOPCNT-NEXT: vpaddd %xmm2, %xmm0, %xmm3
@@ -1450,8 +1450,8 @@ define <4 x i32> @widen_cttz_undef_v2i32_v4i32(<2 x i32> %a0, <2 x i32> %a1) {
ret <4 x i32> %res
}
-define <8 x i32> @widen_cttz_undef_v4i32_v8i32(<4 x i32> %a0, <4 x i32> %a1) {
-; SSE42-LABEL: widen_cttz_undef_v4i32_v8i32:
+define <8 x i32> @widen_cttz_poison_v4i32_v8i32(<4 x i32> %a0, <4 x i32> %a1) {
+; SSE42-LABEL: widen_cttz_poison_v4i32_v8i32:
; SSE42: # %bb.0:
; SSE42-NEXT: pcmpeqd %xmm4, %xmm4
; SSE42-NEXT: movdqa %xmm0, %xmm2
@@ -1491,7 +1491,7 @@ define <8 x i32> @widen_cttz_undef_v4i32_v8i32(<4 x i32> %a0, <4 x i32> %a1) {
; SSE42-NEXT: packuswb %xmm2, %xmm1
; SSE42-NEXT: retq
;
-; AVX2-LABEL: widen_cttz_undef_v4i32_v8i32:
+; AVX2-LABEL: widen_cttz_poison_v4i32_v8i32:
; AVX2: # %bb.0:
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
@@ -1515,7 +1515,7 @@ define <8 x i32> @widen_cttz_undef_v4i32_v8i32(<4 x i32> %a0, <4 x i32> %a1) {
; AVX2-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX2-NEXT: retq
;
-; AVX512VL-LABEL: widen_cttz_undef_v4i32_v8i32:
+; AVX512VL-LABEL: widen_cttz_poison_v4i32_v8i32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX512VL-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
@@ -1527,7 +1527,7 @@ define <8 x i32> @widen_cttz_undef_v4i32_v8i32(<4 x i32> %a0, <4 x i32> %a1) {
; AVX512VL-NEXT: vpsubd %ymm0, %ymm1, %ymm0
; AVX512VL-NEXT: retq
;
-; AVX512VPOPCNT-LABEL: widen_cttz_undef_v4i32_v8i32:
+; AVX512VPOPCNT-LABEL: widen_cttz_poison_v4i32_v8i32:
; AVX512VPOPCNT: # %bb.0:
; AVX512VPOPCNT-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX512VPOPCNT-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
@@ -1542,8 +1542,8 @@ define <8 x i32> @widen_cttz_undef_v4i32_v8i32(<4 x i32> %a0, <4 x i32> %a1) {
ret <8 x i32> %res
}
-define <8 x i32> @widen_cttz_undef_v2i32_v8i32(<2 x i32> %a0, <2 x i32> %a1, <2 x i32> %a2, <2 x i32> %a3) {
-; SSE42-LABEL: widen_cttz_undef_v2i32_v8i32:
+define <8 x i32> @widen_cttz_poison_v2i32_v8i32(<2 x i32> %a0, <2 x i32> %a1, <2 x i32> %a2, <2 x i32> %a3) {
+; SSE42-LABEL: widen_cttz_poison_v2i32_v8i32:
; SSE42: # %bb.0:
; SSE42-NEXT: pcmpeqd %xmm6, %xmm6
; SSE42-NEXT: movdqa %xmm0, %xmm4
@@ -1607,7 +1607,7 @@ define <8 x i32> @widen_cttz_undef_v2i32_v8i32(<2 x i32> %a0, <2 x i32> %a1, <2
; SSE42-NEXT: packuswb %xmm2, %xmm1
; SSE42-NEXT: retq
;
-; AVX2-LABEL: widen_cttz_undef_v2i32_v8i32:
+; AVX2-LABEL: widen_cttz_poison_v2i32_v8i32:
; AVX2: # %bb.0:
; AVX2-NEXT: # kill: def $xmm1 killed $xmm1 def $ymm1
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
@@ -1641,7 +1641,7 @@ define <8 x i32> @widen_cttz_undef_v2i32_v8i32(<2 x i32> %a0, <2 x i32> %a1, <2
; AVX2-NEXT: vpackuswb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
-; AVX512VL-LABEL: widen_cttz_undef_v2i32_v8i32:
+; AVX512VL-LABEL: widen_cttz_poison_v2i32_v8i32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: # kill: def $xmm1 killed $xmm1 def $ymm1
; AVX512VL-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
@@ -1658,7 +1658,7 @@ define <8 x i32> @widen_cttz_undef_v2i32_v8i32(<2 x i32> %a0, <2 x i32> %a1, <2
; AVX512VL-NEXT: vpsubd %ymm0, %ymm1, %ymm0
; AVX512VL-NEXT: retq
;
-; AVX512VPOPCNT-LABEL: widen_cttz_undef_v2i32_v8i32:
+; AVX512VPOPCNT-LABEL: widen_cttz_poison_v2i32_v8i32:
; AVX512VPOPCNT: # %bb.0:
; AVX512VPOPCNT-NEXT: # kill: def $xmm1 killed $xmm1 def $ymm1
; AVX512VPOPCNT-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
diff --git a/llvm/test/CodeGen/Xtensa/ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/Xtensa/ctlz-cttz-ctpop.ll
index 2524a333556e2..737ab07f35a44 100644
--- a/llvm/test/CodeGen/Xtensa/ctlz-cttz-ctpop.ll
+++ b/llvm/test/CodeGen/Xtensa/ctlz-cttz-ctpop.ll
@@ -41,8 +41,8 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
ret i32 %tmp
}
-define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
-; XTENSA-LABEL: test_cttz_i32_zero_undef:
+define i32 @test_cttz_i32_zero_poison(i32 %a) nounwind {
+; XTENSA-LABEL: test_cttz_i32_zero_poison:
; XTENSA: # %bb.0:
; XTENSA-NEXT: movi a8, -1
; XTENSA-NEXT: xor a8, a2, a8
@@ -114,8 +114,8 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
ret i32 %tmp
}
-define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind {
-; XTENSA-LABEL: test_ctlz_i32_zero_undef:
+define i32 @test_ctlz_i32_zero_poison(i32 %a) nounwind {
+; XTENSA-LABEL: test_ctlz_i32_zero_poison:
; XTENSA: # %bb.0:
; XTENSA-NEXT: srli a8, a2, 1
; XTENSA-NEXT: or a8, a2, a8
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-sse4a-inseltpoison.ll b/llvm/test/Transforms/InstCombine/X86/x86-sse4a-inseltpoison.ll
index 8b92eb4c59cc5..f47ff46073d53 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-sse4a-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-sse4a-inseltpoison.ll
@@ -237,7 +237,7 @@ define <2 x i64> @test_insertqi_call_constexpr(<2 x i64> %x) {
}
; The result of this insert is the second arg, since the top 64 bits of
-; the result are poisonined, and we copy the bottom 64 bits from the
+; the result are poisoned, and we copy the bottom 64 bits from the
; second arg
define <2 x i64> @testInsert64Bits(<2 x i64> %v, <2 x i64> %i) {
; CHECK-LABEL: @testInsert64Bits(
diff --git a/llvm/test/Transforms/InstCombine/add2.ll b/llvm/test/Transforms/InstCombine/add2.ll
index 2b4ad85bfd995..565718f9665b2 100644
--- a/llvm/test/Transforms/InstCombine/add2.ll
+++ b/llvm/test/Transforms/InstCombine/add2.ll
@@ -345,7 +345,7 @@ define i16 @add_cttz(i16 %a) {
; CHECK-NEXT: [[B:%.*]] = or disjoint i16 [[CTTZ]], -8
; CHECK-NEXT: ret i16 [[B]]
;
- ; llvm.cttz.i16(..., /*is_zero_undefined=*/true) implies the value returned
+ ; llvm.cttz.i16(..., /*is_zero_poison=*/true) implies the value returned
; is in [0, 16). The range metadata indicates the value returned is in [0, 8).
; Intersecting these ranges, we know the value returned is in [0, 8).
; Therefore, InstCombine will transform
@@ -367,7 +367,7 @@ define i16 @add_cttz_2(i16 %a) {
; CHECK-NEXT: [[B:%.*]] = or disjoint i16 [[CTTZ]], -16
; CHECK-NEXT: ret i16 [[B]]
;
- ; llvm.cttz.i16(..., /*is_zero_undefined=*/true) implies the value returned
+ ; llvm.cttz.i16(..., /*is_zero_poison=*/true) implies the value returned
; is in [0, 16). The range metadata indicates the value returned is in
; [0, 32). Intersecting these ranges, we know the value returned is in
; [0, 16). Therefore, InstCombine will transform
diff --git a/llvm/test/Transforms/InstCombine/cttz.ll b/llvm/test/Transforms/InstCombine/cttz.ll
index b3291e7058896..7af67faab1d47 100644
--- a/llvm/test/Transforms/InstCombine/cttz.ll
+++ b/llvm/test/Transforms/InstCombine/cttz.ll
@@ -6,8 +6,8 @@ declare i32 @llvm.ctlz.i32(i32, i1)
declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1)
declare void @use(i32)
-define i32 @cttz_zext_zero_undef(i16 %x) {
-; CHECK-LABEL: @cttz_zext_zero_undef(
+define i32 @cttz_zext_zero_poison(i16 %x) {
+; CHECK-LABEL: @cttz_zext_zero_poison(
; CHECK-NEXT: [[TMP1:%.*]] = call range(i16 0, 17) i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 true)
; CHECK-NEXT: [[TZ:%.*]] = zext nneg i16 [[TMP1]] to i32
; CHECK-NEXT: ret i32 [[TZ]]
@@ -28,8 +28,8 @@ define i32 @cttz_zext_zero_def(i16 %x) {
ret i32 %tz
}
-define i32 @cttz_zext_zero_undef_extra_use(i16 %x) {
-; CHECK-LABEL: @cttz_zext_zero_undef_extra_use(
+define i32 @cttz_zext_zero_poison_extra_use(i16 %x) {
+; CHECK-LABEL: @cttz_zext_zero_poison_extra_use(
; CHECK-NEXT: [[Z:%.*]] = zext i16 [[X:%.*]] to i32
; CHECK-NEXT: call void @use(i32 [[Z]])
; CHECK-NEXT: [[TZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[Z]], i1 true)
@@ -41,8 +41,8 @@ define i32 @cttz_zext_zero_undef_extra_use(i16 %x) {
ret i32 %tz
}
-define <2 x i64> @cttz_zext_zero_undef_vec(<2 x i32> %x) {
-; CHECK-LABEL: @cttz_zext_zero_undef_vec(
+define <2 x i64> @cttz_zext_zero_poison_vec(<2 x i32> %x) {
+; CHECK-LABEL: @cttz_zext_zero_poison_vec(
; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 true)
; CHECK-NEXT: [[TZ:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[TZ]]
@@ -63,8 +63,8 @@ define <2 x i64> @cttz_zext_zero_def_vec(<2 x i32> %x) {
ret <2 x i64> %tz
}
-define i32 @cttz_sext_zero_undef(i16 %x) {
-; CHECK-LABEL: @cttz_sext_zero_undef(
+define i32 @cttz_sext_zero_poison(i16 %x) {
+; CHECK-LABEL: @cttz_sext_zero_poison(
; CHECK-NEXT: [[TMP1:%.*]] = call range(i16 0, 17) i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 true)
; CHECK-NEXT: [[TZ:%.*]] = zext nneg i16 [[TMP1]] to i32
; CHECK-NEXT: ret i32 [[TZ]]
@@ -85,8 +85,8 @@ define i32 @cttz_sext_zero_def(i16 %x) {
ret i32 %tz
}
-define i32 @cttz_sext_zero_undef_extra_use(i16 %x) {
-; CHECK-LABEL: @cttz_sext_zero_undef_extra_use(
+define i32 @cttz_sext_zero_poison_extra_use(i16 %x) {
+; CHECK-LABEL: @cttz_sext_zero_poison_extra_use(
; CHECK-NEXT: [[S:%.*]] = sext i16 [[X:%.*]] to i32
; CHECK-NEXT: call void @use(i32 [[S]])
; CHECK-NEXT: [[TZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[S]], i1 true)
@@ -98,8 +98,8 @@ define i32 @cttz_sext_zero_undef_extra_use(i16 %x) {
ret i32 %tz
}
-define <2 x i64> @cttz_sext_zero_undef_vec(<2 x i32> %x) {
-; CHECK-LABEL: @cttz_sext_zero_undef_vec(
+define <2 x i64> @cttz_sext_zero_poison_vec(<2 x i32> %x) {
+; CHECK-LABEL: @cttz_sext_zero_poison_vec(
; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 true)
; CHECK-NEXT: [[TZ:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[TZ]]
diff --git a/llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll b/llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll
index 0cb3aeaa14b3e..c1afdfef97a1c 100644
--- a/llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll
+++ b/llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll
@@ -3,7 +3,7 @@
; This test is to verify that the instruction combiner is able to fold
; a cttz/ctlz followed by a icmp + select into a single cttz/ctlz with
-; the 'is_zero_undef' flag cleared.
+; the 'is_zero_poison' flag cleared.
define i16 @test1(i16 %x) {
; CHECK-LABEL: @test1(
diff --git a/llvm/test/Transforms/InstCombine/umin_cttz_ctlz.ll b/llvm/test/Transforms/InstCombine/umin_cttz_ctlz.ll
index a3da6ae25ae4f..910dd9f14bc2c 100644
--- a/llvm/test/Transforms/InstCombine/umin_cttz_ctlz.ll
+++ b/llvm/test/Transforms/InstCombine/umin_cttz_ctlz.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
-define i8 @umin_cttz_i8_zero_undefined(i8 %X) {
-; CHECK-LABEL: define i8 @umin_cttz_i8_zero_undefined(
+define i8 @umin_cttz_i8_zero_poisoned(i8 %X) {
+; CHECK-LABEL: define i8 @umin_cttz_i8_zero_poisoned(
; CHECK-SAME: i8 [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[X]], 64
; CHECK-NEXT: [[RET:%.*]] = call range(i8 0, 7) i8 @llvm.cttz.i8(i8 [[TMP1]], i1 true)
@@ -25,8 +25,8 @@ define i8 @umin_cttz_i8_zero_defined(i8 %X) {
ret i8 %ret
}
-define i8 @umin_cttz_i8_commuted_zero_undefined(i8 %X) {
-; CHECK-LABEL: define i8 @umin_cttz_i8_commuted_zero_undefined(
+define i8 @umin_cttz_i8_commuted_zero_poisoned(i8 %X) {
+; CHECK-LABEL: define i8 @umin_cttz_i8_commuted_zero_poisoned(
; CHECK-SAME: i8 [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[X]], 64
; CHECK-NEXT: [[RET:%.*]] = call range(i8 0, 7) i8 @llvm.cttz.i8(i8 [[TMP1]], i1 true)
@@ -37,8 +37,8 @@ define i8 @umin_cttz_i8_commuted_zero_undefined(i8 %X) {
ret i8 %ret
}
-define i8 @umin_cttz_i8_negative_ge_bitwidth_zero_undefined(i8 %X) {
-; CHECK-LABEL: define i8 @umin_cttz_i8_negative_ge_bitwidth_zero_undefined(
+define i8 @umin_cttz_i8_negative_ge_bitwidth_zero_poisoned(i8 %X) {
+; CHECK-LABEL: define i8 @umin_cttz_i8_negative_ge_bitwidth_zero_poisoned(
; CHECK-SAME: i8 [[X:%.*]]) {
; CHECK-NEXT: [[CTTZ:%.*]] = call range(i8 0, 9) i8 @llvm.cttz.i8(i8 [[X]], i1 true)
; CHECK-NEXT: ret i8 [[CTTZ]]
@@ -48,8 +48,8 @@ define i8 @umin_cttz_i8_negative_ge_bitwidth_zero_undefined(i8 %X) {
ret i8 %ret
}
-define i16 @umin_cttz_i16_zero_undefined(i16 %X) {
-; CHECK-LABEL: define i16 @umin_cttz_i16_zero_undefined(
+define i16 @umin_cttz_i16_zero_poisoned(i16 %X) {
+; CHECK-LABEL: define i16 @umin_cttz_i16_zero_poisoned(
; CHECK-SAME: i16 [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or i16 [[X]], 64
; CHECK-NEXT: [[RET:%.*]] = call range(i16 0, 7) i16 @llvm.cttz.i16(i16 [[TMP1]], i1 true)
@@ -60,8 +60,8 @@ define i16 @umin_cttz_i16_zero_undefined(i16 %X) {
ret i16 %ret
}
-define i32 @umin_cttz_i32_zero_undefined(i32 %X) {
-; CHECK-LABEL: define i32 @umin_cttz_i32_zero_undefined(
+define i32 @umin_cttz_i32_zero_poisoned(i32 %X) {
+; CHECK-LABEL: define i32 @umin_cttz_i32_zero_poisoned(
; CHECK-SAME: i32 [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X]], 64
; CHECK-NEXT: [[RET:%.*]] = call range(i32 0, 7) i32 @llvm.cttz.i32(i32 [[TMP1]], i1 true)
@@ -72,8 +72,8 @@ define i32 @umin_cttz_i32_zero_undefined(i32 %X) {
ret i32 %ret
}
-define i64 @umin_cttz_i64_zero_undefined(i64 %X) {
-; CHECK-LABEL: define i64 @umin_cttz_i64_zero_undefined(
+define i64 @umin_cttz_i64_zero_poisoned(i64 %X) {
+; CHECK-LABEL: define i64 @umin_cttz_i64_zero_poisoned(
; CHECK-SAME: i64 [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or i64 [[X]], 64
; CHECK-NEXT: [[RET:%.*]] = call range(i64 0, 7) i64 @llvm.cttz.i64(i64 [[TMP1]], i1 true)
@@ -84,8 +84,8 @@ define i64 @umin_cttz_i64_zero_undefined(i64 %X) {
ret i64 %ret
}
-define i1 @umin_cttz_i1_zero_undefined(i1 %X) {
-; CHECK-LABEL: define i1 @umin_cttz_i1_zero_undefined(
+define i1 @umin_cttz_i1_zero_poisoned(i1 %X) {
+; CHECK-LABEL: define i1 @umin_cttz_i1_zero_poisoned(
; CHECK-SAME: i1 [[X:%.*]]) {
; CHECK-NEXT: ret i1 false
;
@@ -105,8 +105,8 @@ define i1 @umin_cttz_i1_zero_defined(i1 %X) {
ret i1 %ret
}
-define <2 x i32> @umin_cttz_2xi32_splat_zero_undefined(<2 x i32> %X) {
-; CHECK-LABEL: define <2 x i32> @umin_cttz_2xi32_splat_zero_undefined(
+define <2 x i32> @umin_cttz_2xi32_splat_zero_poisoned(<2 x i32> %X) {
+; CHECK-LABEL: define <2 x i32> @umin_cttz_2xi32_splat_zero_poisoned(
; CHECK-SAME: <2 x i32> [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[X]], splat (i32 64)
; CHECK-NEXT: [[RET:%.*]] = call range(i32 0, 7) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[TMP1]], i1 true)
@@ -117,8 +117,8 @@ define <2 x i32> @umin_cttz_2xi32_splat_zero_undefined(<2 x i32> %X) {
ret <2 x i32> %ret
}
-define <2 x i32> @umin_cttz_2xi32_splat_poison_zero_undefined(<2 x i32> %X) {
-; CHECK-LABEL: define <2 x i32> @umin_cttz_2xi32_splat_poison_zero_undefined(
+define <2 x i32> @umin_cttz_2xi32_splat_poison_zero_poisoned(<2 x i32> %X) {
+; CHECK-LABEL: define <2 x i32> @umin_cttz_2xi32_splat_poison_zero_poisoned(
; CHECK-SAME: <2 x i32> [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[X]], <i32 64, i32 poison>
; CHECK-NEXT: [[RET:%.*]] = call range(i32 0, 7) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[TMP1]], i1 true)
@@ -129,8 +129,8 @@ define <2 x i32> @umin_cttz_2xi32_splat_poison_zero_undefined(<2 x i32> %X) {
ret <2 x i32> %ret
}
-define <2 x i32> @umin_cttz_2xi32_no_splat_all_lt_bitwidth_zero_undefined(<2 x i32> %X) {
-; CHECK-LABEL: define <2 x i32> @umin_cttz_2xi32_no_splat_all_lt_bitwidth_zero_undefined(
+define <2 x i32> @umin_cttz_2xi32_no_splat_all_lt_bitwidth_zero_poisoned(<2 x i32> %X) {
+; CHECK-LABEL: define <2 x i32> @umin_cttz_2xi32_no_splat_all_lt_bitwidth_zero_poisoned(
; CHECK-SAME: <2 x i32> [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[X]], <i32 64, i32 1>
; CHECK-NEXT: [[RET:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[TMP1]], i1 true)
@@ -141,8 +141,8 @@ define <2 x i32> @umin_cttz_2xi32_no_splat_all_lt_bitwidth_zero_undefined(<2 x i
ret <2 x i32> %ret
}
-define <2 x i32> @umin_cttz_2xi32_negative_no_splat_some_lt_bitwidth_zero_undefined(<2 x i32> %X) {
-; CHECK-LABEL: define <2 x i32> @umin_cttz_2xi32_negative_no_splat_some_lt_bitwidth_zero_undefined(
+define <2 x i32> @umin_cttz_2xi32_negative_no_splat_some_lt_bitwidth_zero_poisoned(<2 x i32> %X) {
+; CHECK-LABEL: define <2 x i32> @umin_cttz_2xi32_negative_no_splat_some_lt_bitwidth_zero_poisoned(
; CHECK-SAME: <2 x i32> [[X:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X]], i1 true)
; CHECK-NEXT: [[RET1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[RET]], <2 x i32> <i32 6, i32 64>)
@@ -153,8 +153,8 @@ define <2 x i32> @umin_cttz_2xi32_negative_no_splat_some_lt_bitwidth_zero_undefi
ret <2 x i32> %ret
}
-define <2 x i32> @umin_cttz_2xi32_negative_no_splat_none_lt_bitwidth_zero_undefined(<2 x i32> %X) {
-; CHECK-LABEL: define <2 x i32> @umin_cttz_2xi32_negative_no_splat_none_lt_bitwidth_zero_undefined(
+define <2 x i32> @umin_cttz_2xi32_negative_no_splat_none_lt_bitwidth_zero_poisoned(<2 x i32> %X) {
+; CHECK-LABEL: define <2 x i32> @umin_cttz_2xi32_negative_no_splat_none_lt_bitwidth_zero_poisoned(
; CHECK-SAME: <2 x i32> [[X:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X]], i1 true)
; CHECK-NEXT: [[RET1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[RET]], <2 x i32> <i32 32, i32 64>)
@@ -191,8 +191,8 @@ define i16 @umin_cttz_i16_negative_two_uses(i16 %X) {
ret i16 %ret
}
-define i8 @umin_ctlz_i8_zero_undefined(i8 %X) {
-; CHECK-LABEL: define i8 @umin_ctlz_i8_zero_undefined(
+define i8 @umin_ctlz_i8_zero_poisoned(i8 %X) {
+; CHECK-LABEL: define i8 @umin_ctlz_i8_zero_poisoned(
; CHECK-SAME: i8 [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[X]], 2
; CHECK-NEXT: [[RET:%.*]] = call range(i8 0, 7) i8 @llvm.ctlz.i8(i8 [[TMP1]], i1 true)
@@ -215,8 +215,8 @@ define i8 @umin_ctlz_i8_zero_defined(i8 %X) {
ret i8 %ret
}
-define i8 @umin_ctlz_i8_commuted_zero_undefined(i8 %X) {
-; CHECK-LABEL: define i8 @umin_ctlz_i8_commuted_zero_undefined(
+define i8 @umin_ctlz_i8_commuted_zero_poisoned(i8 %X) {
+; CHECK-LABEL: define i8 @umin_ctlz_i8_commuted_zero_poisoned(
; CHECK-SAME: i8 [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[X]], 2
; CHECK-NEXT: [[RET:%.*]] = call range(i8 0, 7) i8 @llvm.ctlz.i8(i8 [[TMP1]], i1 true)
@@ -227,8 +227,8 @@ define i8 @umin_ctlz_i8_commuted_zero_undefined(i8 %X) {
ret i8 %ret
}
-define i8 @umin_ctlz_i8_negative_ge_bitwidth_zero_undefined(i8 %X) {
-; CHECK-LABEL: define i8 @umin_ctlz_i8_negative_ge_bitwidth_zero_undefined(
+define i8 @umin_ctlz_i8_negative_ge_bitwidth_zero_poisoned(i8 %X) {
+; CHECK-LABEL: define i8 @umin_ctlz_i8_negative_ge_bitwidth_zero_poisoned(
; CHECK-SAME: i8 [[X:%.*]]) {
; CHECK-NEXT: [[CTLZ:%.*]] = call range(i8 0, 9) i8 @llvm.ctlz.i8(i8 [[X]], i1 true)
; CHECK-NEXT: ret i8 [[CTLZ]]
@@ -238,8 +238,8 @@ define i8 @umin_ctlz_i8_negative_ge_bitwidth_zero_undefined(i8 %X) {
ret i8 %ret
}
-define i16 @umin_ctlz_i16_zero_undefined(i16 %X) {
-; CHECK-LABEL: define i16 @umin_ctlz_i16_zero_undefined(
+define i16 @umin_ctlz_i16_zero_poisoned(i16 %X) {
+; CHECK-LABEL: define i16 @umin_ctlz_i16_zero_poisoned(
; CHECK-SAME: i16 [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or i16 [[X]], 512
; CHECK-NEXT: [[RET:%.*]] = call range(i16 0, 7) i16 @llvm.ctlz.i16(i16 [[TMP1]], i1 true)
@@ -250,8 +250,8 @@ define i16 @umin_ctlz_i16_zero_undefined(i16 %X) {
ret i16 %ret
}
-define i32 @umin_ctlz_i32_zero_undefined(i32 %X) {
-; CHECK-LABEL: define i32 @umin_ctlz_i32_zero_undefined(
+define i32 @umin_ctlz_i32_zero_poisoned(i32 %X) {
+; CHECK-LABEL: define i32 @umin_ctlz_i32_zero_poisoned(
; CHECK-SAME: i32 [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X]], 33554432
; CHECK-NEXT: [[RET:%.*]] = call range(i32 0, 7) i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 true)
@@ -262,8 +262,8 @@ define i32 @umin_ctlz_i32_zero_undefined(i32 %X) {
ret i32 %ret
}
-define i64 @umin_ctlz_i64_zero_undefined(i64 %X) {
-; CHECK-LABEL: define i64 @umin_ctlz_i64_zero_undefined(
+define i64 @umin_ctlz_i64_zero_poisoned(i64 %X) {
+; CHECK-LABEL: define i64 @umin_ctlz_i64_zero_poisoned(
; CHECK-SAME: i64 [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or i64 [[X]], 144115188075855872
; CHECK-NEXT: [[RET:%.*]] = call range(i64 0, 7) i64 @llvm.ctlz.i64(i64 [[TMP1]], i1 true)
@@ -274,8 +274,8 @@ define i64 @umin_ctlz_i64_zero_undefined(i64 %X) {
ret i64 %ret
}
-define i1 @umin_ctlz_i1_zero_undefined(i1 %X) {
-; CHECK-LABEL: define i1 @umin_ctlz_i1_zero_undefined(
+define i1 @umin_ctlz_i1_zero_poisoned(i1 %X) {
+; CHECK-LABEL: define i1 @umin_ctlz_i1_zero_poisoned(
; CHECK-SAME: i1 [[X:%.*]]) {
; CHECK-NEXT: ret i1 false
;
@@ -295,8 +295,8 @@ define i1 @umin_ctlz_i1_zero_defined(i1 %X) {
ret i1 %ret
}
-define <2 x i32> @umin_ctlz_2xi32_splat_zero_undefined(<2 x i32> %X) {
-; CHECK-LABEL: define <2 x i32> @umin_ctlz_2xi32_splat_zero_undefined(
+define <2 x i32> @umin_ctlz_2xi32_splat_zero_poisoned(<2 x i32> %X) {
+; CHECK-LABEL: define <2 x i32> @umin_ctlz_2xi32_splat_zero_poisoned(
; CHECK-SAME: <2 x i32> [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[X]], splat (i32 33554432)
; CHECK-NEXT: [[RET:%.*]] = call range(i32 0, 7) <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[TMP1]], i1 true)
@@ -307,8 +307,8 @@ define <2 x i32> @umin_ctlz_2xi32_splat_zero_undefined(<2 x i32> %X) {
ret <2 x i32> %ret
}
-define <2 x i32> @umin_ctlz_2xi32_splat_poison_zero_undefined(<2 x i32> %X) {
-; CHECK-LABEL: define <2 x i32> @umin_ctlz_2xi32_splat_poison_zero_undefined(
+define <2 x i32> @umin_ctlz_2xi32_splat_poison_zero_poisoned(<2 x i32> %X) {
+; CHECK-LABEL: define <2 x i32> @umin_ctlz_2xi32_splat_poison_zero_poisoned(
; CHECK-SAME: <2 x i32> [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[X]], <i32 33554432, i32 poison>
; CHECK-NEXT: [[RET:%.*]] = call range(i32 0, 7) <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[TMP1]], i1 true)
@@ -319,8 +319,8 @@ define <2 x i32> @umin_ctlz_2xi32_splat_poison_zero_undefined(<2 x i32> %X) {
ret <2 x i32> %ret
}
-define <2 x i32> @umin_ctlz_2xi32_no_splat_all_lt_bitwidth_zero_undefined(<2 x i32> %X) {
-; CHECK-LABEL: define <2 x i32> @umin_ctlz_2xi32_no_splat_all_lt_bitwidth_zero_undefined(
+define <2 x i32> @umin_ctlz_2xi32_no_splat_all_lt_bitwidth_zero_poisoned(<2 x i32> %X) {
+; CHECK-LABEL: define <2 x i32> @umin_ctlz_2xi32_no_splat_all_lt_bitwidth_zero_poisoned(
; CHECK-SAME: <2 x i32> [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[X]], <i32 33554432, i32 -2147483648>
; CHECK-NEXT: [[RET:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[TMP1]], i1 true)
@@ -331,8 +331,8 @@ define <2 x i32> @umin_ctlz_2xi32_no_splat_all_lt_bitwidth_zero_undefined(<2 x i
ret <2 x i32> %ret
}
-define <2 x i32> @umin_ctlz_2xi32_negative_no_splat_some_lt_bitwidth_zero_undefined(<2 x i32> %X) {
-; CHECK-LABEL: define <2 x i32> @umin_ctlz_2xi32_negative_no_splat_some_lt_bitwidth_zero_undefined(
+define <2 x i32> @umin_ctlz_2xi32_negative_no_splat_some_lt_bitwidth_zero_poisoned(<2 x i32> %X) {
+; CHECK-LABEL: define <2 x i32> @umin_ctlz_2xi32_negative_no_splat_some_lt_bitwidth_zero_poisoned(
; CHECK-SAME: <2 x i32> [[X:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[X]], i1 true)
; CHECK-NEXT: [[RET1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[RET]], <2 x i32> <i32 6, i32 64>)
@@ -343,8 +343,8 @@ define <2 x i32> @umin_ctlz_2xi32_negative_no_splat_some_lt_bitwidth_zero_undefi
ret <2 x i32> %ret
}
-define <2 x i32> @umin_ctlz_2xi32_negative_no_splat_none_lt_bitwidth_zero_undefined(<2 x i32> %X) {
-; CHECK-LABEL: define <2 x i32> @umin_ctlz_2xi32_negative_no_splat_none_lt_bitwidth_zero_undefined(
+define <2 x i32> @umin_ctlz_2xi32_negative_no_splat_none_lt_bitwidth_zero_poisoned(<2 x i32> %X) {
+; CHECK-LABEL: define <2 x i32> @umin_ctlz_2xi32_negative_no_splat_none_lt_bitwidth_zero_poisoned(
; CHECK-SAME: <2 x i32> [[X:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[X]], i1 true)
; CHECK-NEXT: [[RET1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[RET]], <2 x i32> <i32 32, i32 64>)
@@ -381,8 +381,8 @@ define i16 @umin_ctlz_i16_negative_two_uses(i16 %X) {
ret i16 %ret
}
-define i32 @umin_cttz_i32_zero_undef(i32 %X, i32 %Y) {
-; CHECK-LABEL: define i32 @umin_cttz_i32_zero_undef(
+define i32 @umin_cttz_i32_zero_poison(i32 %X, i32 %Y) {
+; CHECK-LABEL: define i32 @umin_cttz_i32_zero_poison(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X]], [[Y]]
; CHECK-NEXT: [[RES:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[TMP1]], i1 false)
@@ -420,8 +420,8 @@ define i32 @umin_cttz_i32_zero_def_undef(i32 %X, i32 %Y) {
ret i32 %res
}
-define i32 @umin_ctlz_i32_zero_undef(i32 %X, i32 %Y) {
-; CHECK-LABEL: define i32 @umin_ctlz_i32_zero_undef(
+define i32 @umin_ctlz_i32_zero_poison(i32 %X, i32 %Y) {
+; CHECK-LABEL: define i32 @umin_ctlz_i32_zero_poison(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X]], [[Y]]
; CHECK-NEXT: [[RES:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false)
@@ -505,8 +505,8 @@ define i32 @neg_umin_cttz_ctlz_i32_zero_def(i32 %X, i32 %Y) {
ret i32 %res
}
-define i32 @neg_umin_cttz_ctlz_i32_zero_undef(i32 %X, i32 %Y) {
-; CHECK-LABEL: define i32 @neg_umin_cttz_ctlz_i32_zero_undef(
+define i32 @neg_umin_cttz_ctlz_i32_zero_poison(i32 %X, i32 %Y) {
+; CHECK-LABEL: define i32 @neg_umin_cttz_ctlz_i32_zero_poison(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT: [[CTTZ_X:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X]], i1 false)
; CHECK-NEXT: [[CTLZ_Y:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[Y]], i1 false)
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/ctlz.ll b/llvm/test/Transforms/SLPVectorizer/X86/ctlz.ll
index 9bf2ade3176d6..1dd7a7fc2ba17 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/ctlz.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/ctlz.ll
@@ -562,11 +562,11 @@ define void @ctlz_32i8() #0 {
}
;
-; CTLZ_ZERO_UNDEF
+; CTLZ_ZERO_POISON
;
-define void @ctlz_undef_2i64() #0 {
-; SSE-LABEL: @ctlz_undef_2i64(
+define void @ctlz_poison_2i64() #0 {
+; SSE-LABEL: @ctlz_poison_2i64(
; SSE-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 8
; SSE-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([4 x i64], ptr @src64, i32 0, i64 1), align 8
; SSE-NEXT: [[CTLZ0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[LD0]], i1 true)
@@ -575,7 +575,7 @@ define void @ctlz_undef_2i64() #0 {
; SSE-NEXT: store i64 [[CTLZ1]], ptr getelementptr inbounds ([4 x i64], ptr @dst64, i32 0, i64 1), align 8
; SSE-NEXT: ret void
;
-; AVX1-LABEL: @ctlz_undef_2i64(
+; AVX1-LABEL: @ctlz_poison_2i64(
; AVX1-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 8
; AVX1-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([4 x i64], ptr @src64, i32 0, i64 1), align 8
; AVX1-NEXT: [[CTLZ0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[LD0]], i1 true)
@@ -584,7 +584,7 @@ define void @ctlz_undef_2i64() #0 {
; AVX1-NEXT: store i64 [[CTLZ1]], ptr getelementptr inbounds ([4 x i64], ptr @dst64, i32 0, i64 1), align 8
; AVX1-NEXT: ret void
;
-; AVX2-LABEL: @ctlz_undef_2i64(
+; AVX2-LABEL: @ctlz_poison_2i64(
; AVX2-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 8
; AVX2-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([4 x i64], ptr @src64, i32 0, i64 1), align 8
; AVX2-NEXT: [[CTLZ0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[LD0]], i1 true)
@@ -593,7 +593,7 @@ define void @ctlz_undef_2i64() #0 {
; AVX2-NEXT: store i64 [[CTLZ1]], ptr getelementptr inbounds ([4 x i64], ptr @dst64, i32 0, i64 1), align 8
; AVX2-NEXT: ret void
;
-; AVX512-LABEL: @ctlz_undef_2i64(
+; AVX512-LABEL: @ctlz_poison_2i64(
; AVX512-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 8
; AVX512-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> [[TMP1]], i1 true)
; AVX512-NEXT: store <2 x i64> [[TMP2]], ptr @dst64, align 8
@@ -608,8 +608,8 @@ define void @ctlz_undef_2i64() #0 {
ret void
}
-define void @ctlz_undef_4i64() #0 {
-; SSE-LABEL: @ctlz_undef_4i64(
+define void @ctlz_poison_4i64() #0 {
+; SSE-LABEL: @ctlz_poison_4i64(
; SSE-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 4
; SSE-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([4 x i64], ptr @src64, i64 0, i64 1), align 4
; SSE-NEXT: [[LD2:%.*]] = load i64, ptr getelementptr inbounds ([4 x i64], ptr @src64, i64 0, i64 2), align 4
@@ -624,7 +624,7 @@ define void @ctlz_undef_4i64() #0 {
; SSE-NEXT: store i64 [[CTLZ3]], ptr getelementptr inbounds ([4 x i64], ptr @dst64, i64 0, i64 3), align 4
; SSE-NEXT: ret void
;
-; AVX1-LABEL: @ctlz_undef_4i64(
+; AVX1-LABEL: @ctlz_poison_4i64(
; AVX1-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 4
; AVX1-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([4 x i64], ptr @src64, i64 0, i64 1), align 4
; AVX1-NEXT: [[LD2:%.*]] = load i64, ptr getelementptr inbounds ([4 x i64], ptr @src64, i64 0, i64 2), align 4
@@ -639,7 +639,7 @@ define void @ctlz_undef_4i64() #0 {
; AVX1-NEXT: store i64 [[CTLZ3]], ptr getelementptr inbounds ([4 x i64], ptr @dst64, i64 0, i64 3), align 4
; AVX1-NEXT: ret void
;
-; AVX2-LABEL: @ctlz_undef_4i64(
+; AVX2-LABEL: @ctlz_poison_4i64(
; AVX2-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 4
; AVX2-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([4 x i64], ptr @src64, i64 0, i64 1), align 4
; AVX2-NEXT: [[LD2:%.*]] = load i64, ptr getelementptr inbounds ([4 x i64], ptr @src64, i64 0, i64 2), align 4
@@ -654,7 +654,7 @@ define void @ctlz_undef_4i64() #0 {
; AVX2-NEXT: store i64 [[CTLZ3]], ptr getelementptr inbounds ([4 x i64], ptr @dst64, i64 0, i64 3), align 4
; AVX2-NEXT: ret void
;
-; AVX512-LABEL: @ctlz_undef_4i64(
+; AVX512-LABEL: @ctlz_poison_4i64(
; AVX512-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 4
; AVX512-NEXT: [[TMP2:%.*]] = call <4 x i64> @llvm.ctlz.v4i64(<4 x i64> [[TMP1]], i1 true)
; AVX512-NEXT: store <4 x i64> [[TMP2]], ptr @dst64, align 4
@@ -675,8 +675,8 @@ define void @ctlz_undef_4i64() #0 {
ret void
}
-define void @ctlz_undef_4i32() #0 {
-; SSE-LABEL: @ctlz_undef_4i32(
+define void @ctlz_poison_4i32() #0 {
+; SSE-LABEL: @ctlz_poison_4i32(
; SSE-NEXT: [[LD0:%.*]] = load i32, ptr @src32, align 4
; SSE-NEXT: [[LD1:%.*]] = load i32, ptr getelementptr inbounds ([8 x i32], ptr @src32, i32 0, i64 1), align 4
; SSE-NEXT: [[LD2:%.*]] = load i32, ptr getelementptr inbounds ([8 x i32], ptr @src32, i32 0, i64 2), align 4
@@ -691,7 +691,7 @@ define void @ctlz_undef_4i32() #0 {
; SSE-NEXT: store i32 [[CTLZ3]], ptr getelementptr inbounds ([8 x i32], ptr @dst32, i32 0, i64 3), align 4
; SSE-NEXT: ret void
;
-; AVX1-LABEL: @ctlz_undef_4i32(
+; AVX1-LABEL: @ctlz_poison_4i32(
; AVX1-NEXT: [[LD0:%.*]] = load i32, ptr @src32, align 4
; AVX1-NEXT: [[LD1:%.*]] = load i32, ptr getelementptr inbounds ([8 x i32], ptr @src32, i32 0, i64 1), align 4
; AVX1-NEXT: [[LD2:%.*]] = load i32, ptr getelementptr inbounds ([8 x i32], ptr @src32, i32 0, i64 2), align 4
@@ -706,13 +706,13 @@ define void @ctlz_undef_4i32() #0 {
; AVX1-NEXT: store i32 [[CTLZ3]], ptr getelementptr inbounds ([8 x i32], ptr @dst32, i32 0, i64 3), align 4
; AVX1-NEXT: ret void
;
-; AVX2-LABEL: @ctlz_undef_4i32(
+; AVX2-LABEL: @ctlz_poison_4i32(
; AVX2-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 4
; AVX2-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> [[TMP1]], i1 true)
; AVX2-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
; AVX2-NEXT: ret void
;
-; AVX512-LABEL: @ctlz_undef_4i32(
+; AVX512-LABEL: @ctlz_poison_4i32(
; AVX512-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 4
; AVX512-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> [[TMP1]], i1 true)
; AVX512-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
@@ -733,8 +733,8 @@ define void @ctlz_undef_4i32() #0 {
ret void
}
-define void @ctlz_undef_8i32() #0 {
-; SSE-LABEL: @ctlz_undef_8i32(
+define void @ctlz_poison_8i32() #0 {
+; SSE-LABEL: @ctlz_poison_8i32(
; SSE-NEXT: [[LD0:%.*]] = load i32, ptr @src32, align 2
; SSE-NEXT: [[LD1:%.*]] = load i32, ptr getelementptr inbounds ([8 x i32], ptr @src32, i32 0, i64 1), align 2
; SSE-NEXT: [[LD2:%.*]] = load i32, ptr getelementptr inbounds ([8 x i32], ptr @src32, i32 0, i64 2), align 2
@@ -761,7 +761,7 @@ define void @ctlz_undef_8i32() #0 {
; SSE-NEXT: store i32 [[CTLZ7]], ptr getelementptr inbounds ([8 x i32], ptr @dst32, i32 0, i64 7), align 2
; SSE-NEXT: ret void
;
-; AVX1-LABEL: @ctlz_undef_8i32(
+; AVX1-LABEL: @ctlz_poison_8i32(
; AVX1-NEXT: [[LD0:%.*]] = load i32, ptr @src32, align 2
; AVX1-NEXT: [[LD1:%.*]] = load i32, ptr getelementptr inbounds ([8 x i32], ptr @src32, i32 0, i64 1), align 2
; AVX1-NEXT: [[LD2:%.*]] = load i32, ptr getelementptr inbounds ([8 x i32], ptr @src32, i32 0, i64 2), align 2
@@ -788,13 +788,13 @@ define void @ctlz_undef_8i32() #0 {
; AVX1-NEXT: store i32 [[CTLZ7]], ptr getelementptr inbounds ([8 x i32], ptr @dst32, i32 0, i64 7), align 2
; AVX1-NEXT: ret void
;
-; AVX2-LABEL: @ctlz_undef_8i32(
+; AVX2-LABEL: @ctlz_poison_8i32(
; AVX2-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 2
; AVX2-NEXT: [[TMP2:%.*]] = call <8 x i32> @llvm.ctlz.v8i32(<8 x i32> [[TMP1]], i1 true)
; AVX2-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 2
; AVX2-NEXT: ret void
;
-; AVX512-LABEL: @ctlz_undef_8i32(
+; AVX512-LABEL: @ctlz_poison_8i32(
; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 2
; AVX512-NEXT: [[TMP2:%.*]] = call <8 x i32> @llvm.ctlz.v8i32(<8 x i32> [[TMP1]], i1 true)
; AVX512-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 2
@@ -827,8 +827,8 @@ define void @ctlz_undef_8i32() #0 {
ret void
}
-define void @ctlz_undef_8i16() #0 {
-; CHECK-LABEL: @ctlz_undef_8i16(
+define void @ctlz_poison_8i16() #0 {
+; CHECK-LABEL: @ctlz_poison_8i16(
; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 2
; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> [[TMP1]], i1 true)
; CHECK-NEXT: store <8 x i16> [[TMP2]], ptr @dst16, align 2
@@ -861,8 +861,8 @@ define void @ctlz_undef_8i16() #0 {
ret void
}
-define void @ctlz_undef_16i16() #0 {
-; SSE-LABEL: @ctlz_undef_16i16(
+define void @ctlz_poison_16i16() #0 {
+; SSE-LABEL: @ctlz_poison_16i16(
; SSE-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 2
; SSE-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> [[TMP1]], i1 true)
; SSE-NEXT: store <8 x i16> [[TMP2]], ptr @dst16, align 2
@@ -871,7 +871,7 @@ define void @ctlz_undef_16i16() #0 {
; SSE-NEXT: store <8 x i16> [[TMP4]], ptr getelementptr inbounds ([16 x i16], ptr @dst16, i16 0, i64 8), align 2
; SSE-NEXT: ret void
;
-; AVX-LABEL: @ctlz_undef_16i16(
+; AVX-LABEL: @ctlz_poison_16i16(
; AVX-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @src16, align 2
; AVX-NEXT: [[TMP2:%.*]] = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> [[TMP1]], i1 true)
; AVX-NEXT: store <16 x i16> [[TMP2]], ptr @dst16, align 2
@@ -928,8 +928,8 @@ define void @ctlz_undef_16i16() #0 {
ret void
}
-define void @ctlz_undef_16i8() #0 {
-; CHECK-LABEL: @ctlz_undef_16i8(
+define void @ctlz_poison_16i8() #0 {
+; CHECK-LABEL: @ctlz_poison_16i8(
; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @src8, align 1
; CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> [[TMP1]], i1 true)
; CHECK-NEXT: store <16 x i8> [[TMP2]], ptr @dst8, align 1
@@ -986,8 +986,8 @@ define void @ctlz_undef_16i8() #0 {
ret void
}
-define void @ctlz_undef_32i8() #0 {
-; SSE-LABEL: @ctlz_undef_32i8(
+define void @ctlz_poison_32i8() #0 {
+; SSE-LABEL: @ctlz_poison_32i8(
; SSE-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @src8, align 1
; SSE-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> [[TMP1]], i1 true)
; SSE-NEXT: store <16 x i8> [[TMP2]], ptr @dst8, align 1
@@ -996,7 +996,7 @@ define void @ctlz_undef_32i8() #0 {
; SSE-NEXT: store <16 x i8> [[TMP4]], ptr getelementptr inbounds ([32 x i8], ptr @dst8, i8 0, i64 16), align 1
; SSE-NEXT: ret void
;
-; AVX-LABEL: @ctlz_undef_32i8(
+; AVX-LABEL: @ctlz_poison_32i8(
; AVX-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @src8, align 1
; AVX-NEXT: [[TMP2:%.*]] = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> [[TMP1]], i1 true)
; AVX-NEXT: store <32 x i8> [[TMP2]], ptr @dst8, align 1
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/cttz.ll b/llvm/test/Transforms/SLPVectorizer/X86/cttz.ll
index 896be6f2fe213..688e22eb64fd3 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/cttz.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/cttz.ll
@@ -553,11 +553,11 @@ define void @cttz_32i8() #0 {
}
;
-; CTTZ_ZERO_UNDEF
+; CTTZ_ZERO_POISON
;
-define void @cttz_undef_2i64() #0 {
-; SSE-LABEL: @cttz_undef_2i64(
+define void @cttz_poison_2i64() #0 {
+; SSE-LABEL: @cttz_poison_2i64(
; SSE-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 8
; SSE-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([4 x i64], ptr @src64, i32 0, i64 1), align 8
; SSE-NEXT: [[CTTZ0:%.*]] = call i64 @llvm.cttz.i64(i64 [[LD0]], i1 true)
@@ -566,7 +566,7 @@ define void @cttz_undef_2i64() #0 {
; SSE-NEXT: store i64 [[CTTZ1]], ptr getelementptr inbounds ([4 x i64], ptr @dst64, i32 0, i64 1), align 8
; SSE-NEXT: ret void
;
-; AVX1-LABEL: @cttz_undef_2i64(
+; AVX1-LABEL: @cttz_poison_2i64(
; AVX1-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 8
; AVX1-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([4 x i64], ptr @src64, i32 0, i64 1), align 8
; AVX1-NEXT: [[CTTZ0:%.*]] = call i64 @llvm.cttz.i64(i64 [[LD0]], i1 true)
@@ -575,7 +575,7 @@ define void @cttz_undef_2i64() #0 {
; AVX1-NEXT: store i64 [[CTTZ1]], ptr getelementptr inbounds ([4 x i64], ptr @dst64, i32 0, i64 1), align 8
; AVX1-NEXT: ret void
;
-; AVX2-LABEL: @cttz_undef_2i64(
+; AVX2-LABEL: @cttz_poison_2i64(
; AVX2-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 8
; AVX2-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([4 x i64], ptr @src64, i32 0, i64 1), align 8
; AVX2-NEXT: [[CTTZ0:%.*]] = call i64 @llvm.cttz.i64(i64 [[LD0]], i1 true)
@@ -584,7 +584,7 @@ define void @cttz_undef_2i64() #0 {
; AVX2-NEXT: store i64 [[CTTZ1]], ptr getelementptr inbounds ([4 x i64], ptr @dst64, i32 0, i64 1), align 8
; AVX2-NEXT: ret void
;
-; AVX512-LABEL: @cttz_undef_2i64(
+; AVX512-LABEL: @cttz_poison_2i64(
; AVX512-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 8
; AVX512-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[TMP1]], i1 true)
; AVX512-NEXT: store <2 x i64> [[TMP2]], ptr @dst64, align 8
@@ -599,8 +599,8 @@ define void @cttz_undef_2i64() #0 {
ret void
}
-define void @cttz_undef_4i64() #0 {
-; SSE-LABEL: @cttz_undef_4i64(
+define void @cttz_poison_4i64() #0 {
+; SSE-LABEL: @cttz_poison_4i64(
; SSE-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 4
; SSE-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([4 x i64], ptr @src64, i64 0, i64 1), align 4
; SSE-NEXT: [[LD2:%.*]] = load i64, ptr getelementptr inbounds ([4 x i64], ptr @src64, i64 0, i64 2), align 4
@@ -615,7 +615,7 @@ define void @cttz_undef_4i64() #0 {
; SSE-NEXT: store i64 [[CTTZ3]], ptr getelementptr inbounds ([4 x i64], ptr @dst64, i64 0, i64 3), align 4
; SSE-NEXT: ret void
;
-; AVX1-LABEL: @cttz_undef_4i64(
+; AVX1-LABEL: @cttz_poison_4i64(
; AVX1-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 4
; AVX1-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([4 x i64], ptr @src64, i64 0, i64 1), align 4
; AVX1-NEXT: [[LD2:%.*]] = load i64, ptr getelementptr inbounds ([4 x i64], ptr @src64, i64 0, i64 2), align 4
@@ -630,13 +630,13 @@ define void @cttz_undef_4i64() #0 {
; AVX1-NEXT: store i64 [[CTTZ3]], ptr getelementptr inbounds ([4 x i64], ptr @dst64, i64 0, i64 3), align 4
; AVX1-NEXT: ret void
;
-; AVX2-LABEL: @cttz_undef_4i64(
+; AVX2-LABEL: @cttz_poison_4i64(
; AVX2-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 4
; AVX2-NEXT: [[TMP2:%.*]] = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> [[TMP1]], i1 true)
; AVX2-NEXT: store <4 x i64> [[TMP2]], ptr @dst64, align 4
; AVX2-NEXT: ret void
;
-; AVX512-LABEL: @cttz_undef_4i64(
+; AVX512-LABEL: @cttz_poison_4i64(
; AVX512-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 4
; AVX512-NEXT: [[TMP2:%.*]] = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> [[TMP1]], i1 true)
; AVX512-NEXT: store <4 x i64> [[TMP2]], ptr @dst64, align 4
@@ -657,8 +657,8 @@ define void @cttz_undef_4i64() #0 {
ret void
}
-define void @cttz_undef_4i32() #0 {
-; SSE-LABEL: @cttz_undef_4i32(
+define void @cttz_poison_4i32() #0 {
+; SSE-LABEL: @cttz_poison_4i32(
; SSE-NEXT: [[LD0:%.*]] = load i32, ptr @src32, align 4
; SSE-NEXT: [[LD1:%.*]] = load i32, ptr getelementptr inbounds ([8 x i32], ptr @src32, i32 0, i64 1), align 4
; SSE-NEXT: [[LD2:%.*]] = load i32, ptr getelementptr inbounds ([8 x i32], ptr @src32, i32 0, i64 2), align 4
@@ -673,7 +673,7 @@ define void @cttz_undef_4i32() #0 {
; SSE-NEXT: store i32 [[CTTZ3]], ptr getelementptr inbounds ([8 x i32], ptr @dst32, i32 0, i64 3), align 4
; SSE-NEXT: ret void
;
-; AVX1-LABEL: @cttz_undef_4i32(
+; AVX1-LABEL: @cttz_poison_4i32(
; AVX1-NEXT: [[LD0:%.*]] = load i32, ptr @src32, align 4
; AVX1-NEXT: [[LD1:%.*]] = load i32, ptr getelementptr inbounds ([8 x i32], ptr @src32, i32 0, i64 1), align 4
; AVX1-NEXT: [[LD2:%.*]] = load i32, ptr getelementptr inbounds ([8 x i32], ptr @src32, i32 0, i64 2), align 4
@@ -688,13 +688,13 @@ define void @cttz_undef_4i32() #0 {
; AVX1-NEXT: store i32 [[CTTZ3]], ptr getelementptr inbounds ([8 x i32], ptr @dst32, i32 0, i64 3), align 4
; AVX1-NEXT: ret void
;
-; AVX2-LABEL: @cttz_undef_4i32(
+; AVX2-LABEL: @cttz_poison_4i32(
; AVX2-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 4
; AVX2-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> [[TMP1]], i1 true)
; AVX2-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
; AVX2-NEXT: ret void
;
-; AVX512-LABEL: @cttz_undef_4i32(
+; AVX512-LABEL: @cttz_poison_4i32(
; AVX512-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 4
; AVX512-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> [[TMP1]], i1 true)
; AVX512-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
@@ -715,8 +715,8 @@ define void @cttz_undef_4i32() #0 {
ret void
}
-define void @cttz_undef_8i32() #0 {
-; SSE-LABEL: @cttz_undef_8i32(
+define void @cttz_poison_8i32() #0 {
+; SSE-LABEL: @cttz_poison_8i32(
; SSE-NEXT: [[LD0:%.*]] = load i32, ptr @src32, align 2
; SSE-NEXT: [[LD1:%.*]] = load i32, ptr getelementptr inbounds ([8 x i32], ptr @src32, i32 0, i64 1), align 2
; SSE-NEXT: [[LD2:%.*]] = load i32, ptr getelementptr inbounds ([8 x i32], ptr @src32, i32 0, i64 2), align 2
@@ -743,7 +743,7 @@ define void @cttz_undef_8i32() #0 {
; SSE-NEXT: store i32 [[CTTZ7]], ptr getelementptr inbounds ([8 x i32], ptr @dst32, i32 0, i64 7), align 2
; SSE-NEXT: ret void
;
-; AVX1-LABEL: @cttz_undef_8i32(
+; AVX1-LABEL: @cttz_poison_8i32(
; AVX1-NEXT: [[LD0:%.*]] = load i32, ptr @src32, align 2
; AVX1-NEXT: [[LD1:%.*]] = load i32, ptr getelementptr inbounds ([8 x i32], ptr @src32, i32 0, i64 1), align 2
; AVX1-NEXT: [[LD2:%.*]] = load i32, ptr getelementptr inbounds ([8 x i32], ptr @src32, i32 0, i64 2), align 2
@@ -770,13 +770,13 @@ define void @cttz_undef_8i32() #0 {
; AVX1-NEXT: store i32 [[CTTZ7]], ptr getelementptr inbounds ([8 x i32], ptr @dst32, i32 0, i64 7), align 2
; AVX1-NEXT: ret void
;
-; AVX2-LABEL: @cttz_undef_8i32(
+; AVX2-LABEL: @cttz_poison_8i32(
; AVX2-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 2
; AVX2-NEXT: [[TMP2:%.*]] = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> [[TMP1]], i1 true)
; AVX2-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 2
; AVX2-NEXT: ret void
;
-; AVX512-LABEL: @cttz_undef_8i32(
+; AVX512-LABEL: @cttz_poison_8i32(
; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 2
; AVX512-NEXT: [[TMP2:%.*]] = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> [[TMP1]], i1 true)
; AVX512-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 2
@@ -809,8 +809,8 @@ define void @cttz_undef_8i32() #0 {
ret void
}
-define void @cttz_undef_8i16() #0 {
-; CHECK-LABEL: @cttz_undef_8i16(
+define void @cttz_poison_8i16() #0 {
+; CHECK-LABEL: @cttz_poison_8i16(
; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 2
; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> [[TMP1]], i1 true)
; CHECK-NEXT: store <8 x i16> [[TMP2]], ptr @dst16, align 2
@@ -843,8 +843,8 @@ define void @cttz_undef_8i16() #0 {
ret void
}
-define void @cttz_undef_16i16() #0 {
-; SSE-LABEL: @cttz_undef_16i16(
+define void @cttz_poison_16i16() #0 {
+; SSE-LABEL: @cttz_poison_16i16(
; SSE-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 2
; SSE-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> [[TMP1]], i1 true)
; SSE-NEXT: store <8 x i16> [[TMP2]], ptr @dst16, align 2
@@ -853,7 +853,7 @@ define void @cttz_undef_16i16() #0 {
; SSE-NEXT: store <8 x i16> [[TMP4]], ptr getelementptr inbounds ([16 x i16], ptr @dst16, i16 0, i64 8), align 2
; SSE-NEXT: ret void
;
-; AVX-LABEL: @cttz_undef_16i16(
+; AVX-LABEL: @cttz_poison_16i16(
; AVX-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @src16, align 2
; AVX-NEXT: [[TMP2:%.*]] = call <16 x i16> @llvm.cttz.v16i16(<16 x i16> [[TMP1]], i1 true)
; AVX-NEXT: store <16 x i16> [[TMP2]], ptr @dst16, align 2
@@ -910,8 +910,8 @@ define void @cttz_undef_16i16() #0 {
ret void
}
-define void @cttz_undef_16i8() #0 {
-; CHECK-LABEL: @cttz_undef_16i8(
+define void @cttz_poison_16i8() #0 {
+; CHECK-LABEL: @cttz_poison_16i8(
; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @src8, align 1
; CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> [[TMP1]], i1 true)
; CHECK-NEXT: store <16 x i8> [[TMP2]], ptr @dst8, align 1
@@ -968,8 +968,8 @@ define void @cttz_undef_16i8() #0 {
ret void
}
-define void @cttz_undef_32i8() #0 {
-; SSE-LABEL: @cttz_undef_32i8(
+define void @cttz_poison_32i8() #0 {
+; SSE-LABEL: @cttz_poison_32i8(
; SSE-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @src8, align 1
; SSE-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> [[TMP1]], i1 true)
; SSE-NEXT: store <16 x i8> [[TMP2]], ptr @dst8, align 1
@@ -978,7 +978,7 @@ define void @cttz_undef_32i8() #0 {
; SSE-NEXT: store <16 x i8> [[TMP4]], ptr getelementptr inbounds ([32 x i8], ptr @dst8, i8 0, i64 16), align 1
; SSE-NEXT: ret void
;
-; AVX-LABEL: @cttz_undef_32i8(
+; AVX-LABEL: @cttz_poison_32i8(
; AVX-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @src8, align 1
; AVX-NEXT: [[TMP2:%.*]] = call <32 x i8> @llvm.cttz.v32i8(<32 x i8> [[TMP1]], i1 true)
; AVX-NEXT: store <32 x i8> [[TMP2]], ptr @dst8, align 1
diff --git a/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp b/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
index cef2c59e26fb5..809d8880faaed 100644
--- a/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
@@ -180,8 +180,8 @@ TEST_F(AArch64GISelMITest, LowerRotatesVector) {
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
}
-// Test CTTZ expansion when CTTZ_ZERO_UNDEF is legal or custom,
-// in which case it becomes CTTZ_ZERO_UNDEF with select.
+// Test CTTZ expansion when CTTZ_ZERO_POISON is legal or custom,
+// in which case it becomes CTTZ_ZERO_POISON with select.
TEST_F(AArch64GISelMITest, LowerBitCountingCTTZ0) {
setUp();
if (!TM)
@@ -189,7 +189,7 @@ TEST_F(AArch64GISelMITest, LowerBitCountingCTTZ0) {
// Declare your legalization info
DefineLegalizerInfo(A, {
- getActionDefinitionsBuilder(G_CTTZ_ZERO_UNDEF).legalFor({{s32, s64}});
+ getActionDefinitionsBuilder(G_CTTZ_ZERO_POISON).legalFor({{s32, s64}});
});
// Build Instr
auto MIBCTTZ =
@@ -202,7 +202,7 @@ TEST_F(AArch64GISelMITest, LowerBitCountingCTTZ0) {
Helper.lower(*MIBCTTZ, 0, LLT::scalar(64)));
auto CheckStr = R"(
- CHECK: [[CZU:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF %0
+ CHECK: [[CZU:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON %0
CHECK: [[ZERO:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
CHECK: [[CMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), %0:_(s64), [[ZERO]]
CHECK: [[SIXTY4:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
@@ -274,7 +274,7 @@ TEST_F(AArch64GISelMITest, NarrowScalarCTLZ) {
CHECK: [[CTLZ_LO:%[0-9]+]]:_(s32) = G_CTLZ [[UNMERGE_LO]]:_(s32)
CHECK: [[THIRTYTWO:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTLZ_LO]]:_, [[THIRTYTWO]]:_
- CHECK: [[CTLZ_HI:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[UNMERGE_HI]]:_(s32)
+ CHECK: [[CTLZ_HI:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_POISON [[UNMERGE_HI]]:_(s32)
CHECK: %{{[0-9]+}}:_(s32) = G_SELECT [[CMP]]:_(i1), [[ADD]]:_, [[CTLZ_HI]]:_
)";
@@ -309,7 +309,7 @@ TEST_F(AArch64GISelMITest, NarrowScalarCTTZ) {
CHECK: [[CTTZ_HI:%[0-9]+]]:_(s32) = G_CTTZ [[UNMERGE_HI]]:_(s32)
CHECK: [[THIRTYTWO:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTTZ_HI]]:_, [[THIRTYTWO]]:_
- CHECK: [[CTTZ_LO:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UNMERGE_LO]]:_(s32)
+ CHECK: [[CTTZ_LO:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[UNMERGE_LO]]:_(s32)
CHECK: %{{[0-9]+}}:_(s32) = G_SELECT [[CMP]]:_(s1), [[ADD]]:_, [[CTTZ_LO]]:_
)";
@@ -419,7 +419,7 @@ TEST_F(AArch64GISelMITest, WidenBitCountingCTPOP2) {
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
}
-// CTTZ_ZERO_UNDEF expansion in terms of CTTZ
+// CTTZ_ZERO_POISON expansion in terms of CTTZ
TEST_F(AArch64GISelMITest, LowerBitCountingCTTZ3) {
setUp();
if (!TM)
@@ -430,7 +430,7 @@ TEST_F(AArch64GISelMITest, LowerBitCountingCTTZ3) {
getActionDefinitionsBuilder(G_CTTZ).legalFor({{s64, s64}});
});
// Build
- auto MIBCTTZ = B.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
+ auto MIBCTTZ = B.buildInstr(TargetOpcode::G_CTTZ_ZERO_POISON,
{LLT::scalar(64)}, {Copies[0]});
AInfo Info(MF->getSubtarget());
DummyGISelObserver Observer;
@@ -446,7 +446,7 @@ TEST_F(AArch64GISelMITest, LowerBitCountingCTTZ3) {
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
}
-// CTLZ expansion in terms of CTLZ_ZERO_UNDEF
+// CTLZ expansion in terms of CTLZ_ZERO_POISON
TEST_F(AArch64GISelMITest, LowerBitCountingCTLZ0) {
setUp();
if (!TM)
@@ -454,7 +454,7 @@ TEST_F(AArch64GISelMITest, LowerBitCountingCTLZ0) {
// Declare your legalization info
DefineLegalizerInfo(A, {
- getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF).legalFor({{s64, s64}});
+ getActionDefinitionsBuilder(G_CTLZ_ZERO_POISON).legalFor({{s64, s64}});
});
// Build
auto MIBCTLZ =
@@ -466,7 +466,7 @@ TEST_F(AArch64GISelMITest, LowerBitCountingCTLZ0) {
LegalizerHelper::LegalizeResult::Legalized);
auto CheckStr = R"(
- CHECK: [[CZU:%[0-9]+]]:_(s64) = G_CTLZ_ZERO_UNDEF %0
+ CHECK: [[CZU:%[0-9]+]]:_(s64) = G_CTLZ_ZERO_POISON %0
CHECK: [[ZERO:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
CHECK: [[CMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), %0:_(s64), [[ZERO]]
CHECK: [[SIXTY4:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
@@ -477,7 +477,7 @@ TEST_F(AArch64GISelMITest, LowerBitCountingCTLZ0) {
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
}
-// CTLZ expansion in terms of CTLZ_ZERO_UNDEF if the latter is a libcall
+// CTLZ expansion in terms of CTLZ_ZERO_POISON if the latter is a libcall
TEST_F(AArch64GISelMITest, LowerBitCountingCTLZLibcall) {
setUp();
if (!TM)
@@ -485,7 +485,7 @@ TEST_F(AArch64GISelMITest, LowerBitCountingCTLZLibcall) {
// Declare your legalization info
DefineLegalizerInfo(A, {
- getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF).libcallFor({{s32, s64}});
+ getActionDefinitionsBuilder(G_CTLZ_ZERO_POISON).libcallFor({{s32, s64}});
});
// Build
auto MIBCTLZ =
@@ -497,7 +497,7 @@ TEST_F(AArch64GISelMITest, LowerBitCountingCTLZLibcall) {
Helper.lower(*MIBCTLZ, 0, LLT::scalar(32)));
auto CheckStr = R"(
- CHECK: [[CZU:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF %0
+ CHECK: [[CZU:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_POISON %0
CHECK: [[ZERO:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
CHECK: [[CMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), %0:_(s64), [[ZERO]]
CHECK: [[THIRTY2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
@@ -584,15 +584,15 @@ TEST_F(AArch64GISelMITest, WidenBitCountingCTLZ) {
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
}
-// CTLZ_ZERO_UNDEF widening.
-TEST_F(AArch64GISelMITest, WidenBitCountingCTLZZeroUndef) {
+// CTLZ_ZERO_POISON widening.
+TEST_F(AArch64GISelMITest, WidenBitCountingCTLZZeroPoison) {
setUp();
if (!TM)
GTEST_SKIP();
// Declare your legalization info
DefineLegalizerInfo(A, {
- getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF).legalFor({{s16, s16}});
+ getActionDefinitionsBuilder(G_CTLZ_ZERO_POISON).legalFor({{s16, s16}});
});
// Build
// Trunc it to s8.
@@ -600,7 +600,7 @@ TEST_F(AArch64GISelMITest, WidenBitCountingCTLZZeroUndef) {
LLT s16{LLT::scalar(16)};
auto MIBTrunc = B.buildTrunc(s8, Copies[0]);
auto MIBCTLZ_ZU =
- B.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {s8}, {MIBTrunc});
+ B.buildInstr(TargetOpcode::G_CTLZ_ZERO_POISON, {s8}, {MIBTrunc});
AInfo Info(MF->getSubtarget());
DummyGISelObserver Observer;
LegalizerHelper Helper(*MF, Info, Observer, B);
@@ -612,7 +612,7 @@ TEST_F(AArch64GISelMITest, WidenBitCountingCTLZZeroUndef) {
CHECK: [[Zext:%[0-9]+]]:_(s16) = G_ANYEXT [[Trunc]]
CHECK: [[Cst8:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
CHECK: [[Shl:%[0-9]+]]:_(s16) = G_SHL [[Zext]]:_, [[Cst8]]:_
- CHECK: [[CtlzZu:%[0-9]+]]:_(s16) = G_CTLZ_ZERO_UNDEF [[Shl]]
+ CHECK: [[CtlzZu:%[0-9]+]]:_(s16) = G_CTLZ_ZERO_POISON [[Shl]]
CHECK: [[Trunc:%[0-9]+]]:_(s8) = G_TRUNC [[CtlzZu]]
)";
@@ -653,33 +653,33 @@ TEST_F(AArch64GISelMITest, WidenBitCountingCTPOP) {
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
}
-// CTTZ_ZERO_UNDEF widening.
-TEST_F(AArch64GISelMITest, WidenBitCountingCTTZ_ZERO_UNDEF) {
+// CTTZ_ZERO_POISON widening.
+TEST_F(AArch64GISelMITest, WidenBitCountingCTTZ_ZERO_POISON) {
setUp();
if (!TM)
GTEST_SKIP();
// Declare your legalization info
DefineLegalizerInfo(A, {
- getActionDefinitionsBuilder(G_CTTZ_ZERO_UNDEF).legalFor({{s16, s16}});
+ getActionDefinitionsBuilder(G_CTTZ_ZERO_POISON).legalFor({{s16, s16}});
});
// Build
// Trunc it to s8.
LLT s8{LLT::scalar(8)};
LLT s16{LLT::scalar(16)};
auto MIBTrunc = B.buildTrunc(s8, Copies[0]);
- auto MIBCTTZ_ZERO_UNDEF =
- B.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {s8}, {MIBTrunc});
+ auto MIBCTTZ_ZERO_POISON =
+ B.buildInstr(TargetOpcode::G_CTTZ_ZERO_POISON, {s8}, {MIBTrunc});
AInfo Info(MF->getSubtarget());
DummyGISelObserver Observer;
LegalizerHelper Helper(*MF, Info, Observer, B);
- EXPECT_TRUE(Helper.widenScalar(*MIBCTTZ_ZERO_UNDEF, 1, s16) ==
+ EXPECT_TRUE(Helper.widenScalar(*MIBCTTZ_ZERO_POISON, 1, s16) ==
LegalizerHelper::LegalizeResult::Legalized);
auto CheckStr = R"(
CHECK: [[Trunc:%[0-9]+]]:_(s8) = G_TRUNC
CHECK: [[AnyExt:%[0-9]+]]:_(s16) = G_ANYEXT [[Trunc]]
- CHECK: [[CttzZu:%[0-9]+]]:_(s16) = G_CTTZ_ZERO_UNDEF [[AnyExt]]
+ CHECK: [[CttzZu:%[0-9]+]]:_(s16) = G_CTTZ_ZERO_POISON [[AnyExt]]
CHECK: [[Trunc:%[0-9]+]]:_(s8) = G_TRUNC [[CttzZu]]
)";
@@ -714,7 +714,7 @@ TEST_F(AArch64GISelMITest, WidenBitCountingCTTZ) {
CHECK: [[AnyExt:%[0-9]+]]:_(s16) = G_ANYEXT [[Trunc]]
CHECK: [[Cst:%[0-9]+]]:_(s16) = G_CONSTANT i16 256
CHECK: [[Or:%[0-9]+]]:_(s16) = G_OR [[AnyExt]]:_, [[Cst]]
- CHECK: [[Cttz:%[0-9]+]]:_(s16) = G_CTTZ_ZERO_UNDEF [[Or]]
+ CHECK: [[Cttz:%[0-9]+]]:_(s16) = G_CTTZ_ZERO_POISON [[Or]]
CHECK: [[Trunc:%[0-9]+]]:_(s8) = G_TRUNC [[Cttz]]
)";
@@ -2310,14 +2310,14 @@ TEST_F(AArch64GISelMITest, LibcallURem) {
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
}
-TEST_F(AArch64GISelMITest, LibcallCtlzZeroUndef) {
+TEST_F(AArch64GISelMITest, LibcallCtlzZeroPoison) {
setUp();
if (!TM)
GTEST_SKIP();
// Declare your legalization info
DefineLegalizerInfo(A, {
- getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
+ getActionDefinitionsBuilder(G_CTLZ_ZERO_POISON)
.libcallFor({{s32, s32}, {s64, s64}, {s128, s128}});
});
@@ -2328,11 +2328,11 @@ TEST_F(AArch64GISelMITest, LibcallCtlzZeroUndef) {
auto MIBExt = B.buildAnyExt(S128, Copies[0]);
auto MIBCtlz32 =
- B.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {S32}, {MIBTrunc});
+ B.buildInstr(TargetOpcode::G_CTLZ_ZERO_POISON, {S32}, {MIBTrunc});
auto MIBCtlz64 =
- B.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {S64}, {Copies[0]});
+ B.buildInstr(TargetOpcode::G_CTLZ_ZERO_POISON, {S64}, {Copies[0]});
auto MIBCtlz128 =
- B.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {S128}, {MIBExt});
+ B.buildInstr(TargetOpcode::G_CTLZ_ZERO_POISON, {S128}, {MIBExt});
AInfo Info(MF->getSubtarget());
DummyGISelObserver Observer;
diff --git a/llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp b/llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp
index caff8ed761ab2..a9e3c81eceb2b 100644
--- a/llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp
@@ -222,18 +222,18 @@ TEST_F(AArch64GISelMITest, BuildBitCounts) {
B.buildCTPOP(S32, Copies[0]);
B.buildCTLZ(S32, Copies[0]);
- B.buildCTLZ_ZERO_UNDEF(S32, Copies[1]);
+ B.buildCTLZ_ZERO_POISON(S32, Copies[1]);
B.buildCTTZ(S32, Copies[0]);
- B.buildCTTZ_ZERO_UNDEF(S32, Copies[1]);
+ B.buildCTTZ_ZERO_POISON(S32, Copies[1]);
auto CheckStr = R"(
; CHECK: [[COPY0:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[COPY0]]:_
; CHECK: [[CTLZ0:%[0-9]+]]:_(s32) = G_CTLZ [[COPY0]]:_
- ; CHECK: [[CTLZ_UNDEF0:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY1]]:_
+ ; CHECK: [[CTLZ_POISON0:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_POISON [[COPY1]]:_
; CHECK: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[COPY0]]:_
- ; CHECK: [[CTTZ_UNDEF0:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY1]]:_
+ ; CHECK: [[CTTZ_POISON0:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_POISON [[COPY1]]:_
)";
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
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