[llvm] [ARM] Enable switch cond settings to SimplifyCFGOptions (PR #196675)
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Fri May 8 20:54:57 PDT 2026
https://github.com/LumioseSil updated https://github.com/llvm/llvm-project/pull/196675
>From 4e511756059b57d6e8dd68ce53167b09e6b4ca96 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Fri, 8 May 2026 21:26:30 -0400
Subject: [PATCH] [ARM] Enable switch cond settings to SimplifyCFGOptions
---
llvm/lib/Target/ARM/ARMTargetMachine.cpp | 7 ++-
.../CodeGen/Thumb2/bti-indirect-branches.ll | 51 ++++---------------
llvm/test/DebugInfo/ARM/partial-subreg.ll | 2 +-
llvm/test/MC/ARM/data-in-code.ll | 9 ++++
4 files changed, 25 insertions(+), 44 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 0de6f3d16eff4..d117a5fd354fb 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -365,7 +365,12 @@ void ARMPassConfig::addIRPasses() {
// ldrex/strex loops to simplify this, but it needs tidying up.
if (TM->getOptLevel() != CodeGenOptLevel::None && EnableAtomicTidy)
addPass(createCFGSimplificationPass(
- SimplifyCFGOptions().hoistCommonInsts(true).sinkCommonInsts(true),
+ SimplifyCFGOptions()
+ .forwardSwitchCondToPhi(true)
+ .convertSwitchRangeToICmp(true)
+ .convertSwitchToLookupTable(true)
+ .hoistCommonInsts(true)
+ .sinkCommonInsts(true),
[this](const Function &F) {
const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
diff --git a/llvm/test/CodeGen/Thumb2/bti-indirect-branches.ll b/llvm/test/CodeGen/Thumb2/bti-indirect-branches.ll
index 8e570f0e91a08..980ba2c140134 100644
--- a/llvm/test/CodeGen/Thumb2/bti-indirect-branches.ll
+++ b/llvm/test/CodeGen/Thumb2/bti-indirect-branches.ll
@@ -5,31 +5,15 @@ define internal i32 @table_switch(i32 %x) "branch-target-enforcement" {
; CHECK-LABEL: table_switch:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: bti
-; CHECK-NEXT: subs r1, r0, #1
-; CHECK-NEXT: cmp r1, #3
-; CHECK-NEXT: bhi .LBB0_6
-; CHECK-NEXT: @ %bb.1: @ %entry
-; CHECK-NEXT: .LCPI0_0:
-; CHECK-NEXT: tbb [pc, r1]
-; CHECK-NEXT: @ %bb.2:
-; CHECK-NEXT: .LJTI0_0:
-; CHECK-NEXT: .byte (.LBB0_7-(.LCPI0_0+4))/2
-; CHECK-NEXT: .byte (.LBB0_3-(.LCPI0_0+4))/2
-; CHECK-NEXT: .byte (.LBB0_4-(.LCPI0_0+4))/2
-; CHECK-NEXT: .byte (.LBB0_5-(.LCPI0_0+4))/2
-; CHECK-NEXT: .p2align 1
-; CHECK-NEXT: .LBB0_3: @ %bb2
-; CHECK-NEXT: movs r0, #2
-; CHECK-NEXT: bx lr
-; CHECK-NEXT: .LBB0_4: @ %bb3
-; CHECK-NEXT: movs r0, #3
-; CHECK-NEXT: bx lr
-; CHECK-NEXT: .LBB0_5: @ %bb4
-; CHECK-NEXT: movs r0, #5
-; CHECK-NEXT: bx lr
-; CHECK-NEXT: .LBB0_6: @ %sw.epilog
-; CHECK-NEXT: movs r0, #0
-; CHECK-NEXT: .LBB0_7: @ %return
+; CHECK-NEXT: subs r0, #1
+; CHECK-NEXT: cmp r0, #3
+; CHECK-NEXT: itt hi
+; CHECK-NEXT: movhi r0, #0
+; CHECK-NEXT: bxhi lr
+; CHECK-NEXT: .LBB0_1: @ %switch.lookup
+; CHECK-NEXT: movw r1, :lower16:.Lswitch.table.table_switch
+; CHECK-NEXT: movt r1, :upper16:.Lswitch.table.table_switch
+; CHECK-NEXT: ldr.w r0, [r1, r0, lsl #2]
; CHECK-NEXT: bx lr
entry:
switch i32 %x, label %sw.epilog [
@@ -93,23 +77,6 @@ declare void @consume_exception(ptr)
declare i32 @__gxx_personality_v0(...)
define internal i32 @exception_handling(i32 %0) "branch-target-enforcement" personality ptr @__gxx_personality_v0 {
-; CHECK-LABEL: exception_handling:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: bti
-; CHECK-NEXT: .save {r7, lr}
-; CHECK-NEXT: push {r7, lr}
-; CHECK-NEXT: .Ltmp0:
-; CHECK-NEXT: bl may_throw
-; CHECK-NEXT: .Ltmp1:
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: movs r0, #0
-; CHECK-NEXT: pop {r7, pc}
-; CHECK-NEXT: .LBB2_2:
-; CHECK-NEXT: .Ltmp2:
-; CHECK-NEXT: bti
-; CHECK-NEXT: bl consume_exception
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: pop {r7, pc}
entry:
invoke void @may_throw()
to label %return unwind label %lpad
diff --git a/llvm/test/DebugInfo/ARM/partial-subreg.ll b/llvm/test/DebugInfo/ARM/partial-subreg.ll
index ac1bfafde9949..c6d43de89256c 100644
--- a/llvm/test/DebugInfo/ARM/partial-subreg.ll
+++ b/llvm/test/DebugInfo/ARM/partial-subreg.ll
@@ -9,7 +9,7 @@
; CHECK: DW_AT_name {{.*}}"subscript.get"
; CHECK: DW_TAG_formal_parameter
; CHECK-NEXT: DW_AT_location [DW_FORM_sec_offset] ({{.*}}
-; CHECK-NEXT: [0x{{.*}}, 0x{{.*}}): DW_OP_regx D16, DW_OP_piece 0x8, DW_OP_regx D17, DW_OP_piece 0x4
+; CHECK-NEXT: [0x{{.*}}, 0x{{.*}}): DW_OP_piece 0xc, DW_OP_regx D16, DW_OP_piece 0x8, DW_OP_regx D17, DW_OP_piece 0x4
source_filename = "simd.ll"
target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
diff --git a/llvm/test/MC/ARM/data-in-code.ll b/llvm/test/MC/ARM/data-in-code.ll
index b755c3bb5cad4..b0e5b4d95c868 100644
--- a/llvm/test/MC/ARM/data-in-code.ll
+++ b/llvm/test/MC/ARM/data-in-code.ll
@@ -9,6 +9,11 @@
;; Ensure that if a jump table is generated that it has Mapping Symbols
;; marking the data-in-code region.
+declare void @sink0()
+declare void @sink1()
+declare void @sink2()
+declare void @sink3()
+
define void @foo(ptr %ptr, i32 %b) nounwind ssp {
%tmp = load i32, ptr %ptr, align 4
switch i32 %tmp, label %exit [
@@ -18,15 +23,19 @@ define void @foo(ptr %ptr, i32 %b) nounwind ssp {
i32 3, label %bb3
]
bb0:
+ call void @sink0()
store i32 %b, ptr %ptr, align 4
br label %exit
bb1:
+ call void @sink1()
store i32 1, ptr %ptr, align 4
br label %exit
bb2:
+ call void @sink2()
store i32 2, ptr %ptr, align 4
br label %exit
bb3:
+ call void @sink3()
store i32 4, ptr %ptr, align 4
br label %exit
exit:
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