[llvm] Reapply "[MC][TableGen] Expand Opcode field of MCInstrDesc" (#180321) (PR #180954)

[Shilei Tian via llvm-commits]

shiltian wrote:

> For amdgpu, this is ok because it only uses pseudo instructions for matcher tables and opcode enum is sorted so that pseudo instructions always come first.

Well, this is not always true. For example, in `llvm/lib/Target/AMDGPU/VOP1Instructions.td`, we have:

```
foreach vt = Reg32Types.types in {
  def : MovDPP8Pattern<isGFX10Only, V_MOV_B32_dpp8_gfx10, vt>;
  def : MovDPP8Pattern<isGFX11Only, V_MOV_B32_dpp8_gfx11, vt>;
  def : MovDPP8Pattern<isGFX12Only, V_MOV_B32_dpp8_gfx12, vt>;
}
```

which directly matches to real instructions.

I'm now trying to increase the matcher table as well, so I wonder what the OOM issue was when increasing the opcode in matcher table to 32-bit.

CC @arsenm @rampitec @jayfoad 

https://github.com/llvm/llvm-project/pull/180954