[llvm] [InstCombine] Fold binop into multi-use select when one select arm and the other operand are constant (PR #196583)
Iris Shi via llvm-commits
llvm-commits at lists.llvm.org
Sat May 9 00:13:10 PDT 2026
https://github.com/el-ev updated https://github.com/llvm/llvm-project/pull/196583
>From a7aebec901daf187e905dc4c89c45876391787c9 Mon Sep 17 00:00:00 2001
From: Iris Shi <0.0 at owo.li>
Date: Sat, 9 May 2026 00:15:21 +0800
Subject: [PATCH 1/3] pre-commit tests
1
---
.../fold-multi-use-select-packed-constants.ll | 263 ++++++++++++++++++
1 file changed, 263 insertions(+)
create mode 100644 llvm/test/Transforms/InstCombine/fold-multi-use-select-packed-constants.ll
diff --git a/llvm/test/Transforms/InstCombine/fold-multi-use-select-packed-constants.ll b/llvm/test/Transforms/InstCombine/fold-multi-use-select-packed-constants.ll
new file mode 100644
index 0000000000000..5055444939969
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/fold-multi-use-select-packed-constants.ll
@@ -0,0 +1,263 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+define noundef i32 @rust_155985(i32 noundef %n, i1 noundef zeroext %b) {
+; CHECK-LABEL: @rust_155985(
+; CHECK-NEXT: start:
+; CHECK-NEXT: [[EQ:%.*]] = icmp eq i32 [[N:%.*]], 0
+; CHECK-NEXT: [[INNER:%.*]] = select i1 [[EQ]], i64 4294967297, i64 8589934593
+; CHECK-NEXT: [[OUTER:%.*]] = select i1 [[B:%.*]], i64 0, i64 [[INNER]]
+; CHECK-NEXT: [[TAG:%.*]] = trunc i64 [[OUTER]] to i1
+; CHECK-NEXT: [[SHIFT:%.*]] = lshr i64 [[OUTER]], 32
+; CHECK-NEXT: [[PAYLOAD:%.*]] = trunc nuw nsw i64 [[SHIFT]] to i32
+; CHECK-NEXT: [[FINAL:%.*]] = select i1 [[TAG]], i32 [[PAYLOAD]], i32 0
+; CHECK-NEXT: ret i32 [[FINAL]]
+;
+start:
+ %eq = icmp eq i32 %n, 0
+ ; Err(X::_1) -> 0x00000001_00000001, Err(X::_2) -> 0x00000002_00000001
+ %inner = select i1 %eq, i64 4294967297, i64 8589934593
+ ; Ok(()) -> 0
+ %outer = select i1 %b, i64 0, i64 %inner
+ %tag = trunc i64 %outer to i1
+ %shift = lshr i64 %outer, 32
+ %payload = trunc i64 %shift to i32
+ %final = select i1 %tag, i32 %payload, i32 0
+ ret i32 %final
+}
+
+define i32 @lshr_through_multi_use_nested_select(i1 %c1, i1 %c2, ptr %sink) {
+; CHECK-LABEL: @lshr_through_multi_use_nested_select(
+; CHECK-NEXT: [[INNER:%.*]] = select i1 [[C1:%.*]], i64 4294967297, i64 8589934593
+; CHECK-NEXT: [[OUTER:%.*]] = select i1 [[C2:%.*]], i64 0, i64 [[INNER]]
+; CHECK-NEXT: store i64 [[OUTER]], ptr [[SINK:%.*]], align 4
+; CHECK-NEXT: [[S:%.*]] = lshr i64 [[OUTER]], 32
+; CHECK-NEXT: [[T:%.*]] = trunc nuw nsw i64 [[S]] to i32
+; CHECK-NEXT: ret i32 [[T]]
+;
+ %inner = select i1 %c1, i64 4294967297, i64 8589934593
+ %outer = select i1 %c2, i64 0, i64 %inner
+ store i64 %outer, ptr %sink
+ %s = lshr i64 %outer, 32
+ %t = trunc i64 %s to i32
+ ret i32 %t
+}
+
+define i64 @and_through_multi_use_nested_select(i1 %c1, i1 %c2, ptr %sink) {
+; CHECK-LABEL: @and_through_multi_use_nested_select(
+; CHECK-NEXT: [[INNER:%.*]] = select i1 [[C1:%.*]], i64 4294967297, i64 8589934595
+; CHECK-NEXT: [[OUTER:%.*]] = select i1 [[C2:%.*]], i64 0, i64 [[INNER]]
+; CHECK-NEXT: store i64 [[OUTER]], ptr [[SINK:%.*]], align 4
+; CHECK-NEXT: [[M:%.*]] = and i64 [[OUTER]], 3
+; CHECK-NEXT: ret i64 [[M]]
+;
+ %inner = select i1 %c1, i64 4294967297, i64 8589934595
+ %outer = select i1 %c2, i64 0, i64 %inner
+ store i64 %outer, ptr %sink
+ %m = and i64 %outer, 4294967295
+ ret i64 %m
+}
+
+define i64 @or_through_multi_use_nested_select(i1 %c1, i1 %c2, ptr %sink) {
+; CHECK-LABEL: @or_through_multi_use_nested_select(
+; CHECK-NEXT: [[INNER:%.*]] = select i1 [[C1:%.*]], i64 10, i64 20
+; CHECK-NEXT: [[OUTER:%.*]] = select i1 [[C2:%.*]], i64 0, i64 [[INNER]]
+; CHECK-NEXT: store i64 [[OUTER]], ptr [[SINK:%.*]], align 4
+; CHECK-NEXT: [[M:%.*]] = or i64 [[OUTER]], 3
+; CHECK-NEXT: ret i64 [[M]]
+;
+ %inner = select i1 %c1, i64 10, i64 20
+ %outer = select i1 %c2, i64 0, i64 %inner
+ store i64 %outer, ptr %sink
+ %m = or i64 %outer, 3
+ ret i64 %m
+}
+
+define i64 @add_through_multi_use_nested_select(i1 %c1, i1 %c2, ptr %sink) {
+; CHECK-LABEL: @add_through_multi_use_nested_select(
+; CHECK-NEXT: [[INNER:%.*]] = select i1 [[C1:%.*]], i64 100, i64 200
+; CHECK-NEXT: [[OUTER:%.*]] = select i1 [[C2:%.*]], i64 0, i64 [[INNER]]
+; CHECK-NEXT: store i64 [[OUTER]], ptr [[SINK:%.*]], align 4
+; CHECK-NEXT: [[M:%.*]] = add nuw nsw i64 [[OUTER]], 42
+; CHECK-NEXT: ret i64 [[M]]
+;
+ %inner = select i1 %c1, i64 100, i64 200
+ %outer = select i1 %c2, i64 0, i64 %inner
+ store i64 %outer, ptr %sink
+ %m = add i64 %outer, 42
+ ret i64 %m
+}
+
+define i32 @lshr_const_on_true_arm(i1 %c1, i1 %c2, ptr %sink) {
+; CHECK-LABEL: @lshr_const_on_true_arm(
+; CHECK-NEXT: [[INNER:%.*]] = select i1 [[C1:%.*]], i64 4294967297, i64 8589934593
+; CHECK-NEXT: [[OUTER:%.*]] = select i1 [[C2:%.*]], i64 [[INNER]], i64 0
+; CHECK-NEXT: store i64 [[OUTER]], ptr [[SINK:%.*]], align 4
+; CHECK-NEXT: [[S:%.*]] = lshr i64 [[OUTER]], 32
+; CHECK-NEXT: [[T:%.*]] = trunc nuw nsw i64 [[S]] to i32
+; CHECK-NEXT: ret i32 [[T]]
+;
+ %inner = select i1 %c1, i64 4294967297, i64 8589934593
+ %outer = select i1 %c2, i64 %inner, i64 0
+ store i64 %outer, ptr %sink
+ %s = lshr i64 %outer, 32
+ %t = trunc i64 %s to i32
+ ret i32 %t
+}
+
+define i64 @binop_both_arms_constant_multi_use(i1 %c, ptr %sink) {
+; CHECK-LABEL: @binop_both_arms_constant_multi_use(
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C:%.*]], i64 100, i64 200
+; CHECK-NEXT: store i64 [[SEL]], ptr [[SINK:%.*]], align 4
+; CHECK-NEXT: [[M:%.*]] = add nuw nsw i64 [[SEL]], 5
+; CHECK-NEXT: ret i64 [[M]]
+;
+ %sel = select i1 %c, i64 100, i64 200
+ store i64 %sel, ptr %sink
+ %m = add i64 %sel, 5
+ ret i64 %m
+}
+
+define i64 @nested3_select(i1 %c1, i1 %c2, i1 %c3, ptr %sink) {
+; CHECK-LABEL: @nested3_select(
+; CHECK-NEXT: [[S1:%.*]] = select i1 [[C1:%.*]], i64 10, i64 20
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[C3:%.*]], i1 true, i1 [[C2:%.*]]
+; CHECK-NEXT: [[S3:%.*]] = select i1 [[TMP1]], i64 0, i64 [[S1]]
+; CHECK-NEXT: store i64 [[S3]], ptr [[SINK:%.*]], align 4
+; CHECK-NEXT: ret i64 [[S3]]
+;
+ %s1 = select i1 %c1, i64 10, i64 20
+ %s2 = select i1 %c2, i64 0, i64 %s1
+ %s3 = select i1 %c3, i64 0, i64 %s2
+ store i64 %s3, ptr %sink
+ %m = and i64 %s3, 255
+ ret i64 %m
+}
+
+; Negative: binop other operand is not a constant
+define i64 @neg_binop_other_operand_not_const(i1 %c1, i1 %c2, i64 %x, ptr %sink) {
+; CHECK-LABEL: @neg_binop_other_operand_not_const(
+; CHECK-NEXT: [[INNER:%.*]] = select i1 [[C1:%.*]], i64 100, i64 200
+; CHECK-NEXT: [[OUTER:%.*]] = select i1 [[C2:%.*]], i64 0, i64 [[INNER]]
+; CHECK-NEXT: store i64 [[OUTER]], ptr [[SINK:%.*]], align 4
+; CHECK-NEXT: [[M:%.*]] = add i64 [[OUTER]], [[X:%.*]]
+; CHECK-NEXT: ret i64 [[M]]
+;
+ %inner = select i1 %c1, i64 100, i64 200
+ %outer = select i1 %c2, i64 0, i64 %inner
+ store i64 %outer, ptr %sink
+ %m = add i64 %outer, %x
+ ret i64 %m
+}
+
+; Negative: neither arm of the multi-use select is a constant
+define i64 @neg_no_const_arm(i1 %c, i64 %x, i64 %y, ptr %sink) {
+; CHECK-LABEL: @neg_no_const_arm(
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C:%.*]], i64 [[X:%.*]], i64 [[Y:%.*]]
+; CHECK-NEXT: store i64 [[SEL]], ptr [[SINK:%.*]], align 4
+; CHECK-NEXT: [[M:%.*]] = add i64 [[SEL]], 42
+; CHECK-NEXT: ret i64 [[M]]
+;
+ %sel = select i1 %c, i64 %x, i64 %y
+ store i64 %sel, ptr %sink
+ %m = add i64 %sel, 42
+ ret i64 %m
+}
+
+; Negative: variable arm of outer select is not a const-select
+define i64 @neg_variable_arm_not_select(i1 %c, i64 %x, ptr %sink) {
+; CHECK-LABEL: @neg_variable_arm_not_select(
+; CHECK-NEXT: [[OUTER:%.*]] = select i1 [[C:%.*]], i64 0, i64 [[X:%.*]]
+; CHECK-NEXT: store i64 [[OUTER]], ptr [[SINK:%.*]], align 4
+; CHECK-NEXT: [[M:%.*]] = add i64 [[OUTER]], 42
+; CHECK-NEXT: ret i64 [[M]]
+;
+ %outer = select i1 %c, i64 0, i64 %x
+ store i64 %outer, ptr %sink
+ %m = add i64 %outer, 42
+ ret i64 %m
+}
+
+define <2 x i64> @vec_binop_both_arms_constant_multi_use(i1 %c, ptr %sink) {
+; CHECK-LABEL: @vec_binop_both_arms_constant_multi_use(
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C:%.*]], <2 x i64> <i64 100, i64 200>, <2 x i64> <i64 300, i64 400>
+; CHECK-NEXT: store <2 x i64> [[SEL]], ptr [[SINK:%.*]], align 16
+; CHECK-NEXT: [[M:%.*]] = add nuw nsw <2 x i64> [[SEL]], <i64 5, i64 10>
+; CHECK-NEXT: ret <2 x i64> [[M]]
+;
+ %sel = select i1 %c, <2 x i64> <i64 100, i64 200>, <2 x i64> <i64 300, i64 400>
+ store <2 x i64> %sel, ptr %sink
+ %m = add <2 x i64> %sel, <i64 5, i64 10>
+ ret <2 x i64> %m
+}
+
+define <2 x i32> @vec_lshr_through_multi_use_nested_select(i1 %c1, i1 %c2, ptr %sink) {
+; CHECK-LABEL: @vec_lshr_through_multi_use_nested_select(
+; CHECK-NEXT: [[INNER:%.*]] = select i1 [[C1:%.*]], <2 x i64> <i64 4294967297, i64 8589934593>, <2 x i64> <i64 12884901889, i64 17179869185>
+; CHECK-NEXT: [[OUTER:%.*]] = select i1 [[C2:%.*]], <2 x i64> zeroinitializer, <2 x i64> [[INNER]]
+; CHECK-NEXT: store <2 x i64> [[OUTER]], ptr [[SINK:%.*]], align 16
+; CHECK-NEXT: [[S:%.*]] = lshr <2 x i64> [[OUTER]], splat (i64 32)
+; CHECK-NEXT: [[T:%.*]] = trunc nuw nsw <2 x i64> [[S]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[T]]
+;
+ %inner = select i1 %c1, <2 x i64> <i64 4294967297, i64 8589934593>, <2 x i64> <i64 12884901889, i64 17179869185>
+ %outer = select i1 %c2, <2 x i64> zeroinitializer, <2 x i64> %inner
+ store <2 x i64> %outer, ptr %sink
+ %s = lshr <2 x i64> %outer, <i64 32, i64 32>
+ %t = trunc <2 x i64> %s to <2 x i32>
+ ret <2 x i32> %t
+}
+
+define <2 x i64> @vec_or_through_multi_use_both_const(i1 %c, ptr %sink) {
+; CHECK-LABEL: @vec_or_through_multi_use_both_const(
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C:%.*]], <2 x i64> <i64 10, i64 20>, <2 x i64> <i64 30, i64 40>
+; CHECK-NEXT: store <2 x i64> [[SEL]], ptr [[SINK:%.*]], align 16
+; CHECK-NEXT: [[M:%.*]] = or <2 x i64> [[SEL]], splat (i64 3)
+; CHECK-NEXT: ret <2 x i64> [[M]]
+;
+ %sel = select i1 %c, <2 x i64> <i64 10, i64 20>, <2 x i64> <i64 30, i64 40>
+ store <2 x i64> %sel, ptr %sink
+ %m = or <2 x i64> %sel, <i64 3, i64 3>
+ ret <2 x i64> %m
+}
+
+define <2 x i64> @vec_splat_cond_both_const(<2 x i1> %c, ptr %sink) {
+; CHECK-LABEL: @vec_splat_cond_both_const(
+; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[C:%.*]], <2 x i64> <i64 100, i64 200>, <2 x i64> <i64 300, i64 400>
+; CHECK-NEXT: store <2 x i64> [[SEL]], ptr [[SINK:%.*]], align 16
+; CHECK-NEXT: [[M:%.*]] = add nuw nsw <2 x i64> [[SEL]], <i64 5, i64 10>
+; CHECK-NEXT: ret <2 x i64> [[M]]
+;
+ %sel = select <2 x i1> %c, <2 x i64> <i64 100, i64 200>, <2 x i64> <i64 300, i64 400>
+ store <2 x i64> %sel, ptr %sink
+ %m = add <2 x i64> %sel, <i64 5, i64 10>
+ ret <2 x i64> %m
+}
+
+; Negative: no constant arm
+define <2 x i64> @vec_neg_no_const_arm(i1 %c, <2 x i64> %x, <2 x i64> %y, ptr %sink) {
+; CHECK-LABEL: @vec_neg_no_const_arm(
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C:%.*]], <2 x i64> [[X:%.*]], <2 x i64> [[Y:%.*]]
+; CHECK-NEXT: store <2 x i64> [[SEL]], ptr [[SINK:%.*]], align 16
+; CHECK-NEXT: [[M:%.*]] = add <2 x i64> [[SEL]], splat (i64 42)
+; CHECK-NEXT: ret <2 x i64> [[M]]
+;
+ %sel = select i1 %c, <2 x i64> %x, <2 x i64> %y
+ store <2 x i64> %sel, ptr %sink
+ %m = add <2 x i64> %sel, <i64 42, i64 42>
+ ret <2 x i64> %m
+}
+
+; Negative: variable arm not a const-select
+define <2 x i64> @vec_neg_variable_arm_not_select(i1 %c, <2 x i64> %x, ptr %sink) {
+; CHECK-LABEL: @vec_neg_variable_arm_not_select(
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C:%.*]], <2 x i64> zeroinitializer, <2 x i64> [[X:%.*]]
+; CHECK-NEXT: store <2 x i64> [[SEL]], ptr [[SINK:%.*]], align 16
+; CHECK-NEXT: [[M:%.*]] = add <2 x i64> [[SEL]], splat (i64 42)
+; CHECK-NEXT: ret <2 x i64> [[M]]
+;
+ %sel = select i1 %c, <2 x i64> zeroinitializer, <2 x i64> %x
+ store <2 x i64> %sel, ptr %sink
+ %m = add <2 x i64> %sel, <i64 42, i64 42>
+ ret <2 x i64> %m
+}
>From 0da8649b9400f1d1ef2a811a0312255833003bc6 Mon Sep 17 00:00:00 2001
From: Iris Shi <0.0 at owo.li>
Date: Sat, 9 May 2026 00:42:27 +0800
Subject: [PATCH 2/3] [InstCombine] Fold binop into multi-use select when one
select arm and the other operand are constant
---
.../InstCombine/InstructionCombining.cpp | 23 ++++-
.../AMDGPU/amdgpu-simplify-libcall-pow.ll | 96 +++++++++----------
.../Transforms/InstCombine/binop-select.ll | 2 +-
.../Transforms/InstCombine/extractelement.ll | 5 +-
.../fold-multi-use-select-packed-constants.ll | 8 +-
llvm/test/Transforms/InstCombine/pr72433.ll | 9 +-
llvm/test/Transforms/InstCombine/pr80597.ll | 9 +-
7 files changed, 77 insertions(+), 75 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
index a09f881e06595..3fea8caa1f7c5 100644
--- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
@@ -2309,8 +2309,27 @@ Instruction *InstCombinerImpl::foldBinopWithPhiOperands(BinaryOperator &BO) {
Instruction *InstCombinerImpl::foldBinOpIntoSelectOrPhi(BinaryOperator &I) {
auto TryFoldOperand = [&](unsigned OpIdx,
bool IsOtherParamConst) -> Instruction * {
- if (auto *Sel = dyn_cast<SelectInst>(I.getOperand(OpIdx)))
- return FoldOpIntoSelect(I, Sel, false, !IsOtherParamConst);
+ if (auto *Sel = dyn_cast<SelectInst>(I.getOperand(OpIdx))) {
+ // Fold binop(select(c, C, x), C2) => select(c, C3, binop(x, C2))
+ // when one arm and the other operand are both constants, even if
+ // the select has multiple uses. Also allow the non-constant arm
+ // to be a both-constant select when the binop feeds a cast.
+ bool MultiUse = false;
+ if (IsOtherParamConst && !Sel->hasOneUser()) {
+ Value *TV = Sel->getTrueValue(), *FV = Sel->getFalseValue();
+ if (isa<Constant>(TV) && isa<Constant>(FV)) {
+ MultiUse = true;
+ } else if (I.hasOneUse() && isa<CastInst>(*I.user_begin())) {
+ auto IsConstSel = [](Value *V) {
+ return match(V, m_Select(m_Value(), m_Constant(), m_Constant()));
+ };
+ MultiUse = (isa<Constant>(TV) && IsConstSel(FV)) ||
+ (isa<Constant>(FV) && IsConstSel(TV));
+ }
+ }
+ return FoldOpIntoSelect(I, Sel, /*FoldWithMultiUse=*/MultiUse,
+ !IsOtherParamConst);
+ }
if (auto *PN = dyn_cast<PHINode>(I.getOperand(OpIdx)))
return foldOpIntoPhi(I, PN);
return nullptr;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
index a553bb10ff29d..1b96932dc8115 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
@@ -1323,7 +1323,7 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_0.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP7]])
; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <2 x float> [[TMP9]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> <float 0.000000e+00, float -0.000000e+00>
; NOPRELINK-NEXT: [[TMP12:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP11]])
; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une <2 x float> [[TMP12]], [[TMP11]]
; NOPRELINK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP10]], [[TMP13]]
@@ -1384,7 +1384,7 @@ define float @test_pow_afn_f32_0.5(float %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP1]], float 5.000000e-01, float 2.500000e-01
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
@@ -1427,7 +1427,7 @@ define float @test_pow_afn_f32_neg0.5(float %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP1]], float 5.000000e-01, float -2.500000e-01
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
@@ -1472,7 +1472,7 @@ define <2 x float> @test_pow_afn_v2f32_0.5(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> splat (float 2.500000e-01)
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -1515,7 +1515,7 @@ define <2 x float> @test_pow_afn_v2f32_neg0.5(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> splat (float -2.500000e-01)
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -1560,7 +1560,7 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_0.5(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> <float 2.500000e-01, float -2.500000e-01>
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -1605,7 +1605,7 @@ define <3 x float> @test_pow_afn_v3f32_0.5_splat_undef(<3 x float> %x, <3 x floa
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <3 x float> @llvm.exp2.v3f32(<3 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <3 x float> @llvm.trunc.v3f32(<3 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <3 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <3 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <3 x i1> [[TMP1]], <3 x float> splat (float 5.000000e-01), <3 x float> <float 2.500000e-01, float poison, float 2.500000e-01>
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <3 x float> @llvm.trunc.v3f32(<3 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <3 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <3 x i1> [[TMP8]], [[TMP11]]
@@ -1648,7 +1648,7 @@ define <3 x float> @test_pow_afn_v3f32_neg0.5_splat_undef(<3 x float> %x, <3 x f
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <3 x float> @llvm.exp2.v3f32(<3 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <3 x float> @llvm.trunc.v3f32(<3 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <3 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <3 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <3 x i1> [[TMP1]], <3 x float> splat (float 5.000000e-01), <3 x float> <float -2.500000e-01, float poison, float -2.500000e-01>
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <3 x float> @llvm.trunc.v3f32(<3 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <3 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <3 x i1> [[TMP8]], [[TMP11]]
@@ -1731,7 +1731,7 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_1.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> <float 5.000000e-01, float -5.000000e-01>
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -1805,7 +1805,7 @@ define float @test_pow_afn_f32_neg2.0(float %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP1]], float 5.000000e-01, float -1.000000e+00
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
@@ -1860,7 +1860,7 @@ define <2 x float> @test_pow_afn_v2f32_neg2.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> splat (float -1.000000e+00)
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -1905,7 +1905,7 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_2.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> <float 1.000000e+00, float -1.000000e+00>
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -1950,7 +1950,7 @@ define float @test_pow_afn_f32_3.0(float %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP1]], float 5.000000e-01, float 1.500000e+00
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
@@ -1993,7 +1993,7 @@ define float @test_pow_afn_f32_neg3.0(float %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP1]], float 5.000000e-01, float -1.500000e+00
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
@@ -2038,7 +2038,7 @@ define <2 x float> @test_pow_afn_v2f32_3.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> splat (float 1.500000e+00)
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -2081,7 +2081,7 @@ define <2 x float> @test_pow_afn_v2f32_neg3.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> splat (float -1.500000e+00)
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -2126,7 +2126,7 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_3.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> <float 1.500000e+00, float -1.500000e+00>
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -2171,7 +2171,7 @@ define float @test_pow_afn_f32_3.99(float %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP1]], float 5.000000e-01, float 1.995000e+00
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
@@ -2214,7 +2214,7 @@ define float @test_pow_afn_f32_neg3.99(float %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP1]], float 5.000000e-01, float -1.995000e+00
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
@@ -2259,7 +2259,7 @@ define <2 x float> @test_pow_afn_v2f32_3.99(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> splat (float 1.995000e+00)
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -2302,7 +2302,7 @@ define <2 x float> @test_pow_afn_v2f32_neg3.99(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> splat (float -1.995000e+00)
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -2347,7 +2347,7 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_3.99(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> <float 1.995000e+00, float -1.995000e+00>
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -2392,7 +2392,7 @@ define float @test_pow_afn_f32_8.0(float %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP1]], float 5.000000e-01, float 4.000000e+00
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
@@ -2435,7 +2435,7 @@ define float @test_pow_afn_f32_neg8.0(float %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP1]], float 5.000000e-01, float -4.000000e+00
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
@@ -2480,7 +2480,7 @@ define <2 x float> @test_pow_afn_v2f32_8.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> splat (float 4.000000e+00)
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -2523,7 +2523,7 @@ define <2 x float> @test_pow_afn_v2f32_neg8.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> splat (float -4.000000e+00)
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -2568,7 +2568,7 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_8.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> <float 4.000000e+00, float -4.000000e+00>
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -2613,7 +2613,7 @@ define float @test_pow_afn_f32_12.0(float %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP1]], float 5.000000e-01, float 6.000000e+00
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
@@ -2656,7 +2656,7 @@ define float @test_pow_afn_f32_neg12.0(float %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP1]], float 5.000000e-01, float -6.000000e+00
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
@@ -2701,7 +2701,7 @@ define <2 x float> @test_pow_afn_v2f32_12.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> splat (float 6.000000e+00)
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -2744,7 +2744,7 @@ define <2 x float> @test_pow_afn_v2f32_neg12.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> splat (float -6.000000e+00)
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -2789,7 +2789,7 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_12.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> <float 6.000000e+00, float -6.000000e+00>
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -2834,7 +2834,7 @@ define float @test_pow_afn_f32_13.0(float %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP1]], float 5.000000e-01, float 6.500000e+00
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
@@ -2877,7 +2877,7 @@ define float @test_pow_afn_f32_neg13.0(float %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP1]], float 5.000000e-01, float -6.500000e+00
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
@@ -2922,7 +2922,7 @@ define <2 x float> @test_pow_afn_v2f32_13.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> splat (float 6.500000e+00)
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -2965,7 +2965,7 @@ define <2 x float> @test_pow_afn_v2f32_neg13.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> splat (float -6.500000e+00)
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -3010,7 +3010,7 @@ define <2 x float> @test_pow_afn_v2f32_13.0_15.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> <float 6.500000e+00, float 7.500000e+00>
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -3053,7 +3053,7 @@ define <2 x float> @test_pow_afn_v2f32_13.0_14.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> <float 6.500000e+00, float 7.000000e+00>
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -3096,7 +3096,7 @@ define <2 x float> @test_pow_afn_v2f32_14.0_16.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> <float 7.000000e+00, float 8.000000e+00>
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -3139,7 +3139,7 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_13.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> <float 6.500000e+00, float -6.500000e+00>
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -3184,7 +3184,7 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_13.0_minus_14.0(<2 x float> %x
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> <float -6.500000e+00, float -7.000000e+00>
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -4254,7 +4254,7 @@ define float @test_pow_afn_f32__y_3(float %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP1]], float 5.000000e-01, float 1.500000e+00
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
@@ -4308,7 +4308,7 @@ define float @test_pow_afn_f32__y_4(float %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP1]], float 5.000000e-01, float 2.000000e+00
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
@@ -4362,7 +4362,7 @@ define float @test_pow_afn_f32_nnan_ninf__y_4_5(float %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call nnan ninf afn float @llvm.trunc.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp nnan ninf afn oeq float [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan ninf afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP1]], float 5.000000e-01, float 2.250000e+00
; NOPRELINK-NEXT: [[TMP10:%.*]] = call nnan ninf afn float @llvm.trunc.f32(float [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp nnan ninf afn une float [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
@@ -4400,7 +4400,7 @@ define float @test_pow_afn_f32__y_5(float %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP1]], float 5.000000e-01, float 2.500000e+00
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
@@ -4455,7 +4455,7 @@ define float @test_pow_afn_f32__y_neg5(float %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP1]], float 5.000000e-01, float -2.500000e+00
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
@@ -4557,7 +4557,7 @@ define <2 x float> @test_pow_afn_v2f32_nnan_ninf__y_4_5(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> splat (float 2.250000e+00)
; NOPRELINK-NEXT: [[TMP10:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp nnan ninf afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
@@ -4595,7 +4595,7 @@ define <2 x float> @test_pow_afn_v2f32_nnan_ninf__y_4_5_undef(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x float> splat (float 5.000000e-01), <2 x float> <float 2.250000e+00, float poison>
; NOPRELINK-NEXT: [[TMP10:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp nnan ninf afn une <2 x float> [[TMP10]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
diff --git a/llvm/test/Transforms/InstCombine/binop-select.ll b/llvm/test/Transforms/InstCombine/binop-select.ll
index 3265ea54a831e..3efeba83d12ef 100644
--- a/llvm/test/Transforms/InstCombine/binop-select.ll
+++ b/llvm/test/Transforms/InstCombine/binop-select.ll
@@ -274,7 +274,7 @@ define i32 @and_sel_op0_use(i1 %b) {
; CHECK-LABEL: @and_sel_op0_use(
; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], i32 25, i32 0
; CHECK-NEXT: call void @use(i32 [[S]])
-; CHECK-NEXT: [[R:%.*]] = and i32 [[S]], 1
+; CHECK-NEXT: [[R:%.*]] = zext i1 [[B]] to i32
; CHECK-NEXT: ret i32 [[R]]
;
%s = select i1 %b, i32 25, i32 0
diff --git a/llvm/test/Transforms/InstCombine/extractelement.ll b/llvm/test/Transforms/InstCombine/extractelement.ll
index 04a35e19fb0bb..6a5a1ab7e98a2 100644
--- a/llvm/test/Transforms/InstCombine/extractelement.ll
+++ b/llvm/test/Transforms/InstCombine/extractelement.ll
@@ -799,10 +799,7 @@ define i32 @extelt_vecselect_const_operand_vector(<3 x i1> %c) {
define i32 @extelt_select_const_operand_extractelt_use(i1 %c) {
; ANY-LABEL: @extelt_select_const_operand_extractelt_use(
-; ANY-NEXT: [[E:%.*]] = select i1 [[C:%.*]], i32 4, i32 7
-; ANY-NEXT: [[M:%.*]] = shl nuw nsw i32 [[E]], 1
-; ANY-NEXT: [[M_2:%.*]] = shl nuw nsw i32 [[E]], 2
-; ANY-NEXT: [[R:%.*]] = mul nuw nsw i32 [[M]], [[M_2]]
+; ANY-NEXT: [[R:%.*]] = select i1 [[C:%.*]], i32 128, i32 392
; ANY-NEXT: ret i32 [[R]]
;
%s = select i1 %c, <3 x i32> <i32 2, i32 3, i32 4>, <3 x i32> <i32 5, i32 6, i32 7>
diff --git a/llvm/test/Transforms/InstCombine/fold-multi-use-select-packed-constants.ll b/llvm/test/Transforms/InstCombine/fold-multi-use-select-packed-constants.ll
index 5055444939969..bbac2d9757abc 100644
--- a/llvm/test/Transforms/InstCombine/fold-multi-use-select-packed-constants.ll
+++ b/llvm/test/Transforms/InstCombine/fold-multi-use-select-packed-constants.ll
@@ -5,12 +5,8 @@ define noundef i32 @rust_155985(i32 noundef %n, i1 noundef zeroext %b) {
; CHECK-LABEL: @rust_155985(
; CHECK-NEXT: start:
; CHECK-NEXT: [[EQ:%.*]] = icmp eq i32 [[N:%.*]], 0
-; CHECK-NEXT: [[INNER:%.*]] = select i1 [[EQ]], i64 4294967297, i64 8589934593
-; CHECK-NEXT: [[OUTER:%.*]] = select i1 [[B:%.*]], i64 0, i64 [[INNER]]
-; CHECK-NEXT: [[TAG:%.*]] = trunc i64 [[OUTER]] to i1
-; CHECK-NEXT: [[SHIFT:%.*]] = lshr i64 [[OUTER]], 32
-; CHECK-NEXT: [[PAYLOAD:%.*]] = trunc nuw nsw i64 [[SHIFT]] to i32
-; CHECK-NEXT: [[FINAL:%.*]] = select i1 [[TAG]], i32 [[PAYLOAD]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = select i1 [[EQ]], i32 1, i32 2
+; CHECK-NEXT: [[FINAL:%.*]] = select i1 [[B:%.*]], i32 0, i32 [[TMP0]]
; CHECK-NEXT: ret i32 [[FINAL]]
;
start:
diff --git a/llvm/test/Transforms/InstCombine/pr72433.ll b/llvm/test/Transforms/InstCombine/pr72433.ll
index c6e74582a13d3..b5eafb7fed86f 100644
--- a/llvm/test/Transforms/InstCombine/pr72433.ll
+++ b/llvm/test/Transforms/InstCombine/pr72433.ll
@@ -5,13 +5,8 @@ define i32 @widget(i32 %arg, i32 %arg1) {
; CHECK-LABEL: define i32 @widget(
; CHECK-SAME: i32 [[ARG:%.*]], i32 [[ARG1:%.*]]) {
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[ICMP:%.*]] = icmp ne i32 [[ARG]], 0
-; CHECK-NEXT: [[TMP0:%.*]] = zext i1 [[ICMP]] to i32
-; CHECK-NEXT: [[MUL:%.*]] = shl nuw nsw i32 20, [[TMP0]]
-; CHECK-NEXT: [[XOR:%.*]] = zext i1 [[ICMP]] to i32
-; CHECK-NEXT: [[ADD9:%.*]] = or disjoint i32 [[MUL]], [[XOR]]
-; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[ICMP]] to i32
-; CHECK-NEXT: [[MUL2:%.*]] = shl nuw nsw i32 [[ADD9]], [[TMP1]]
+; CHECK-NEXT: [[ICMP_NOT:%.*]] = icmp eq i32 [[ARG]], 0
+; CHECK-NEXT: [[MUL2:%.*]] = select i1 [[ICMP_NOT]], i32 20, i32 82
; CHECK-NEXT: ret i32 [[MUL2]]
;
bb:
diff --git a/llvm/test/Transforms/InstCombine/pr80597.ll b/llvm/test/Transforms/InstCombine/pr80597.ll
index 148da056486f9..bf536b9ecd133 100644
--- a/llvm/test/Transforms/InstCombine/pr80597.ll
+++ b/llvm/test/Transforms/InstCombine/pr80597.ll
@@ -5,14 +5,9 @@ define i64 @pr80597(i1 %cond) {
; CHECK-LABEL: define i64 @pr80597(
; CHECK-SAME: i1 [[COND:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[ADD:%.*]] = select i1 [[COND]], i64 0, i64 -12884901888
-; CHECK-NEXT: [[SEXT1:%.*]] = add nsw i64 [[ADD]], 8836839514384105472
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[SEXT1]], -34359738368
-; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK-NEXT: br i1 true, label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
; CHECK: if.else:
-; CHECK-NEXT: [[SEXT2:%.*]] = ashr exact i64 [[ADD]], 1
-; CHECK-NEXT: [[ASHR:%.*]] = or disjoint i64 [[SEXT2]], 4418419761487020032
-; CHECK-NEXT: ret i64 [[ASHR]]
+; CHECK-NEXT: ret i64 poison
; CHECK: if.then:
; CHECK-NEXT: ret i64 0
;
>From 102ac8554f9c6d50992356526a9180bcb98ccc18 Mon Sep 17 00:00:00 2001
From: Iris Shi <0.0 at owo.li>
Date: Sat, 9 May 2026 15:02:21 +0800
Subject: [PATCH 3/3] address review comments
Co-Authored-By: arsenm <arsenm2 at gmail.com>
---
.../InstCombine/InstructionCombining.cpp | 14 +++++--------
.../fold-multi-use-select-packed-constants.ll | 20 +++++++++----------
2 files changed, 15 insertions(+), 19 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
index 3fea8caa1f7c5..8dd8295d34375 100644
--- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
@@ -2316,16 +2316,12 @@ Instruction *InstCombinerImpl::foldBinOpIntoSelectOrPhi(BinaryOperator &I) {
// to be a both-constant select when the binop feeds a cast.
bool MultiUse = false;
if (IsOtherParamConst && !Sel->hasOneUser()) {
- Value *TV = Sel->getTrueValue(), *FV = Sel->getFalseValue();
- if (isa<Constant>(TV) && isa<Constant>(FV)) {
+ if (match(Sel, m_Select(m_Value(), m_Constant(), m_Constant())))
MultiUse = true;
- } else if (I.hasOneUse() && isa<CastInst>(*I.user_begin())) {
- auto IsConstSel = [](Value *V) {
- return match(V, m_Select(m_Value(), m_Constant(), m_Constant()));
- };
- MultiUse = (isa<Constant>(TV) && IsConstSel(FV)) ||
- (isa<Constant>(FV) && IsConstSel(TV));
- }
+ else if (I.hasOneUse() && isa<CastInst>(*I.user_begin()))
+ MultiUse = match(
+ Sel, m_c_Select(m_Constant(),
+ m_Select(m_Value(), m_Constant(), m_Constant())));
}
return FoldOpIntoSelect(I, Sel, /*FoldWithMultiUse=*/MultiUse,
!IsOtherParamConst);
diff --git a/llvm/test/Transforms/InstCombine/fold-multi-use-select-packed-constants.ll b/llvm/test/Transforms/InstCombine/fold-multi-use-select-packed-constants.ll
index bbac2d9757abc..3cc06f041524d 100644
--- a/llvm/test/Transforms/InstCombine/fold-multi-use-select-packed-constants.ll
+++ b/llvm/test/Transforms/InstCombine/fold-multi-use-select-packed-constants.ll
@@ -27,8 +27,8 @@ define i32 @lshr_through_multi_use_nested_select(i1 %c1, i1 %c2, ptr %sink) {
; CHECK-NEXT: [[INNER:%.*]] = select i1 [[C1:%.*]], i64 4294967297, i64 8589934593
; CHECK-NEXT: [[OUTER:%.*]] = select i1 [[C2:%.*]], i64 0, i64 [[INNER]]
; CHECK-NEXT: store i64 [[OUTER]], ptr [[SINK:%.*]], align 4
-; CHECK-NEXT: [[S:%.*]] = lshr i64 [[OUTER]], 32
-; CHECK-NEXT: [[T:%.*]] = trunc nuw nsw i64 [[S]] to i32
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[C1]], i32 1, i32 2
+; CHECK-NEXT: [[T:%.*]] = select i1 [[C2]], i32 0, i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[T]]
;
%inner = select i1 %c1, i64 4294967297, i64 8589934593
@@ -89,8 +89,8 @@ define i32 @lshr_const_on_true_arm(i1 %c1, i1 %c2, ptr %sink) {
; CHECK-NEXT: [[INNER:%.*]] = select i1 [[C1:%.*]], i64 4294967297, i64 8589934593
; CHECK-NEXT: [[OUTER:%.*]] = select i1 [[C2:%.*]], i64 [[INNER]], i64 0
; CHECK-NEXT: store i64 [[OUTER]], ptr [[SINK:%.*]], align 4
-; CHECK-NEXT: [[S:%.*]] = lshr i64 [[OUTER]], 32
-; CHECK-NEXT: [[T:%.*]] = trunc nuw nsw i64 [[S]] to i32
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[C1]], i32 1, i32 2
+; CHECK-NEXT: [[T:%.*]] = select i1 [[C2]], i32 [[TMP1]], i32 0
; CHECK-NEXT: ret i32 [[T]]
;
%inner = select i1 %c1, i64 4294967297, i64 8589934593
@@ -105,7 +105,7 @@ define i64 @binop_both_arms_constant_multi_use(i1 %c, ptr %sink) {
; CHECK-LABEL: @binop_both_arms_constant_multi_use(
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C:%.*]], i64 100, i64 200
; CHECK-NEXT: store i64 [[SEL]], ptr [[SINK:%.*]], align 4
-; CHECK-NEXT: [[M:%.*]] = add nuw nsw i64 [[SEL]], 5
+; CHECK-NEXT: [[M:%.*]] = select i1 [[C]], i64 105, i64 205
; CHECK-NEXT: ret i64 [[M]]
;
%sel = select i1 %c, i64 100, i64 200
@@ -178,7 +178,7 @@ define <2 x i64> @vec_binop_both_arms_constant_multi_use(i1 %c, ptr %sink) {
; CHECK-LABEL: @vec_binop_both_arms_constant_multi_use(
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C:%.*]], <2 x i64> <i64 100, i64 200>, <2 x i64> <i64 300, i64 400>
; CHECK-NEXT: store <2 x i64> [[SEL]], ptr [[SINK:%.*]], align 16
-; CHECK-NEXT: [[M:%.*]] = add nuw nsw <2 x i64> [[SEL]], <i64 5, i64 10>
+; CHECK-NEXT: [[M:%.*]] = select i1 [[C]], <2 x i64> <i64 105, i64 210>, <2 x i64> <i64 305, i64 410>
; CHECK-NEXT: ret <2 x i64> [[M]]
;
%sel = select i1 %c, <2 x i64> <i64 100, i64 200>, <2 x i64> <i64 300, i64 400>
@@ -192,8 +192,8 @@ define <2 x i32> @vec_lshr_through_multi_use_nested_select(i1 %c1, i1 %c2, ptr %
; CHECK-NEXT: [[INNER:%.*]] = select i1 [[C1:%.*]], <2 x i64> <i64 4294967297, i64 8589934593>, <2 x i64> <i64 12884901889, i64 17179869185>
; CHECK-NEXT: [[OUTER:%.*]] = select i1 [[C2:%.*]], <2 x i64> zeroinitializer, <2 x i64> [[INNER]]
; CHECK-NEXT: store <2 x i64> [[OUTER]], ptr [[SINK:%.*]], align 16
-; CHECK-NEXT: [[S:%.*]] = lshr <2 x i64> [[OUTER]], splat (i64 32)
-; CHECK-NEXT: [[T:%.*]] = trunc nuw nsw <2 x i64> [[S]] to <2 x i32>
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[C1]], <2 x i32> <i32 1, i32 2>, <2 x i32> <i32 3, i32 4>
+; CHECK-NEXT: [[T:%.*]] = select i1 [[C2]], <2 x i32> zeroinitializer, <2 x i32> [[TMP1]]
; CHECK-NEXT: ret <2 x i32> [[T]]
;
%inner = select i1 %c1, <2 x i64> <i64 4294967297, i64 8589934593>, <2 x i64> <i64 12884901889, i64 17179869185>
@@ -208,7 +208,7 @@ define <2 x i64> @vec_or_through_multi_use_both_const(i1 %c, ptr %sink) {
; CHECK-LABEL: @vec_or_through_multi_use_both_const(
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C:%.*]], <2 x i64> <i64 10, i64 20>, <2 x i64> <i64 30, i64 40>
; CHECK-NEXT: store <2 x i64> [[SEL]], ptr [[SINK:%.*]], align 16
-; CHECK-NEXT: [[M:%.*]] = or <2 x i64> [[SEL]], splat (i64 3)
+; CHECK-NEXT: [[M:%.*]] = select i1 [[C]], <2 x i64> <i64 11, i64 23>, <2 x i64> <i64 31, i64 43>
; CHECK-NEXT: ret <2 x i64> [[M]]
;
%sel = select i1 %c, <2 x i64> <i64 10, i64 20>, <2 x i64> <i64 30, i64 40>
@@ -221,7 +221,7 @@ define <2 x i64> @vec_splat_cond_both_const(<2 x i1> %c, ptr %sink) {
; CHECK-LABEL: @vec_splat_cond_both_const(
; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[C:%.*]], <2 x i64> <i64 100, i64 200>, <2 x i64> <i64 300, i64 400>
; CHECK-NEXT: store <2 x i64> [[SEL]], ptr [[SINK:%.*]], align 16
-; CHECK-NEXT: [[M:%.*]] = add nuw nsw <2 x i64> [[SEL]], <i64 5, i64 10>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[C]], <2 x i64> <i64 105, i64 210>, <2 x i64> <i64 305, i64 410>
; CHECK-NEXT: ret <2 x i64> [[M]]
;
%sel = select <2 x i1> %c, <2 x i64> <i64 100, i64 200>, <2 x i64> <i64 300, i64 400>
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