[llvm] [CodeGen][AMDGPU] Move boilerplate unit test code to base class (NFC) (PR #196547)
via llvm-commits
llvm-commits at lists.llvm.org
Fri May 8 07:52:24 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Lucas Ramirez (lucas-rami)
<details>
<summary>Changes</summary>
This adds the `CodeGenTestBase` class to handle boilerplate code for codegen unit tests and makes use of it wherever possible, in particular in AMDGPU unit tests.
Furthermore, this makes all AMDGPU unit tests rely on GoogleTest's API for "run once per test-suite" code, instead of re-implementing that behavior using a `std::once` flag. As a consequence all TEST(...) become TEST_F().
---
Patch is 23.64 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/196547.diff
12 Files Affected:
- (added) llvm/unittests/CodeGen/CodeGenTestBase.h (+91)
- (modified) llvm/unittests/CodeGen/MachineDomTreeUpdaterTest.cpp (+5-72)
- (modified) llvm/unittests/CodeGen/RematerializerTest.cpp (+7-72)
- (modified) llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp (+11-18)
- (modified) llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.h (+19-4)
- (modified) llvm/unittests/Target/AMDGPU/CMakeLists.txt (+1)
- (modified) llvm/unittests/Target/AMDGPU/CSETest.cpp (+1-1)
- (modified) llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp (+2-2)
- (modified) llvm/unittests/Target/AMDGPU/ExecMayBeModifiedBeforeAnyUse.cpp (+1-1)
- (modified) llvm/unittests/Target/AMDGPU/LiveRegUnits.cpp (+9-43)
- (modified) llvm/unittests/Target/AMDGPU/PALMetadata.cpp (+3-18)
- (modified) llvm/unittests/Target/AMDGPU/UniformityAnalysisTest.cpp (+2-18)
``````````diff
diff --git a/llvm/unittests/CodeGen/CodeGenTestBase.h b/llvm/unittests/CodeGen/CodeGenTestBase.h
new file mode 100644
index 0000000000000..0a3117779fc36
--- /dev/null
+++ b/llvm/unittests/CodeGen/CodeGenTestBase.h
@@ -0,0 +1,91 @@
+//===--- CodeGenTestBase.h - Utilities for codegen unit tests ---*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_UNITTESTS_CODEGEN_CODEGENTESTBASE_H
+#define LLVM_UNITTESTS_CODEGEN_CODEGENTESTBASE_H
+
+#include "llvm/Analysis/CGSCCPassManager.h"
+#include "llvm/Analysis/LoopAnalysisManager.h"
+#include "llvm/CodeGen/MIRParser/MIRParser.h"
+#include "llvm/CodeGen/MachineFunctionAnalysis.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/MachinePassManager.h"
+#include "llvm/IR/Module.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Passes/PassBuilder.h"
+#include "llvm/Target/TargetMachine.h"
+#include "gtest/gtest.h"
+
+namespace llvm {
+
+/// Boilerplate set-up for codegen tests. Sets up all analyses managers for a
+/// given target and creates a module from an MIR string.
+class CodeGenTestBase : public testing::Test {
+public:
+ LLVMContext Context;
+ std::unique_ptr<TargetMachine> TM;
+ std::unique_ptr<MachineModuleInfo> MMI;
+ std::unique_ptr<MIRParser> MIR;
+ std::unique_ptr<Module> Mod;
+
+ LoopAnalysisManager LAM;
+ MachineFunctionAnalysisManager MFAM;
+ FunctionAnalysisManager FAM;
+ CGSCCAnalysisManager CGAM;
+ ModuleAnalysisManager MAM;
+
+ MachineFunction &getMF(StringRef FuncName) {
+ return FAM.getResult<MachineFunctionAnalysis>(*Mod->getFunction(FuncName))
+ .getMF();
+ }
+
+protected:
+ /// Sets up the target machine and analyses managers.
+ void setUpImpl(StringRef Triple, StringRef CPU, StringRef FS) {
+ llvm::Triple TT(Triple);
+ std::string Error;
+ const Target *T = TargetRegistry::lookupTarget("", TT, Error);
+ if (!T)
+ GTEST_SKIP();
+ TargetOptions Options;
+ TM.reset(T->createTargetMachine(TT, CPU, FS, Options, std::nullopt));
+ if (!TM)
+ GTEST_SKIP();
+ MMI = std::make_unique<MachineModuleInfo>(TM.get());
+
+ PassBuilder PB(TM.get());
+ PB.registerModuleAnalyses(MAM);
+ PB.registerCGSCCAnalyses(CGAM);
+ PB.registerFunctionAnalyses(FAM);
+ PB.registerLoopAnalyses(LAM);
+ PB.registerMachineFunctionAnalyses(MFAM);
+ PB.crossRegisterProxies(LAM, FAM, CGAM, MAM, &MFAM);
+ MAM.registerPass([&] { return MachineModuleAnalysis(*MMI); });
+ }
+
+ /// Parses \p MIRCode into a module. Returns whether parsing was successful.
+ bool parseMIR(StringRef MIRCode) {
+ SMDiagnostic Diagnostic;
+ std::unique_ptr<MemoryBuffer> MBuffer = MemoryBuffer::getMemBuffer(MIRCode);
+ MIR = createMIRParser(std::move(MBuffer), Context);
+ if (!MIR)
+ return false;
+
+ Mod = MIR->parseIRModule();
+ Mod->setDataLayout(TM->createDataLayout());
+ if (MIR->parseMachineFunctions(*Mod, MAM)) {
+ Mod.reset();
+ return false;
+ }
+ return true;
+ }
+};
+
+} // namespace llvm
+
+#endif // LLVM_UNITTESTS_CODEGEN_CODEGENTESTBASE_H
diff --git a/llvm/unittests/CodeGen/MachineDomTreeUpdaterTest.cpp b/llvm/unittests/CodeGen/MachineDomTreeUpdaterTest.cpp
index 85fdba0b3a9f7..c32565d875cdb 100644
--- a/llvm/unittests/CodeGen/MachineDomTreeUpdaterTest.cpp
+++ b/llvm/unittests/CodeGen/MachineDomTreeUpdaterTest.cpp
@@ -7,88 +7,23 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineDomTreeUpdater.h"
-#include "llvm/Analysis/CGSCCPassManager.h"
-#include "llvm/Analysis/LoopAnalysisManager.h"
+#include "CodeGenTestBase.h"
#include "llvm/CodeGen/MIRParser/MIRParser.h"
-#include "llvm/CodeGen/MachineFunctionAnalysis.h"
-#include "llvm/CodeGen/MachineModuleInfo.h"
-#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachinePostDominators.h"
-#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/TargetLowering.h"
-#include "llvm/IR/Module.h"
-#include "llvm/MC/TargetRegistry.h"
#include "llvm/Passes/PassBuilder.h"
-#include "llvm/Support/SourceMgr.h"
#include "llvm/Support/TargetSelect.h"
-#include "llvm/Target/TargetMachine.h"
#include "gtest/gtest.h"
using namespace llvm;
-class MachineDomTreeUpdaterTest : public testing::Test {
+class MachineDomTreeUpdaterTest : public CodeGenTestBase {
public:
- LLVMContext Context;
- std::unique_ptr<TargetMachine> TM;
- std::unique_ptr<Module> M;
- std::unique_ptr<MachineModuleInfo> MMI;
- std::unique_ptr<MIRParser> MIR;
-
- LoopAnalysisManager LAM;
- MachineFunctionAnalysisManager MFAM;
- FunctionAnalysisManager FAM;
- CGSCCAnalysisManager CGAM;
- ModuleAnalysisManager MAM;
-
- ModulePassManager MPM;
- FunctionPassManager FPM;
- MachineFunctionPassManager MFPM;
-
static void SetUpTestCase() {
InitializeAllTargets();
InitializeAllTargetMCs();
}
- void SetUp() override {
- Triple TargetTriple("x86_64-unknown-linux-gnu");
- std::string Error;
- const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error);
- if (!T)
- GTEST_SKIP();
- TargetOptions Options;
- TM = std::unique_ptr<TargetMachine>(
- T->createTargetMachine(TargetTriple, "", "", Options, std::nullopt));
- if (!TM)
- GTEST_SKIP();
- MMI = std::make_unique<MachineModuleInfo>(TM.get());
-
- PassBuilder PB(TM.get());
- PB.registerModuleAnalyses(MAM);
- PB.registerCGSCCAnalyses(CGAM);
- PB.registerFunctionAnalyses(FAM);
- PB.registerLoopAnalyses(LAM);
- PB.registerMachineFunctionAnalyses(MFAM);
- PB.crossRegisterProxies(LAM, FAM, CGAM, MAM, &MFAM);
- MAM.registerPass([&] { return MachineModuleAnalysis(*MMI); });
- }
-
- bool parseMIR(StringRef MIRCode) {
- SMDiagnostic Diagnostic;
- std::unique_ptr<MemoryBuffer> MBuffer = MemoryBuffer::getMemBuffer(MIRCode);
- MIR = createMIRParser(std::move(MBuffer), Context);
- if (!MIR)
- return false;
-
- M = MIR->parseIRModule();
- M->setDataLayout(TM->createDataLayout());
-
- if (MIR->parseMachineFunctions(*M, MAM)) {
- M.reset();
- return false;
- }
-
- return true;
- }
+ void SetUp() override { setUpImpl("x86_64-unknown-linux-gnu", "", ""); }
};
TEST_F(MachineDomTreeUpdaterTest, EagerUpdateBasicOperations) {
@@ -150,8 +85,7 @@ body: |
ASSERT_TRUE(parseMIR(MIRString));
- auto &MF =
- FAM.getResult<MachineFunctionAnalysis>(*M->getFunction("f0")).getMF();
+ MachineFunction &MF = getMF("f0");
MachineDominatorTree DT(MF);
MachinePostDominatorTree PDT(MF);
@@ -240,8 +174,7 @@ body: |
ASSERT_TRUE(parseMIR(MIRString));
- auto &MF =
- FAM.getResult<MachineFunctionAnalysis>(*M->getFunction("f0")).getMF();
+ MachineFunction &MF = getMF("f0");
MachineDominatorTree DT(MF);
MachinePostDominatorTree PDT(MF);
diff --git a/llvm/unittests/CodeGen/RematerializerTest.cpp b/llvm/unittests/CodeGen/RematerializerTest.cpp
index 00316aa5f72be..bcb8b8caf8f25 100644
--- a/llvm/unittests/CodeGen/RematerializerTest.cpp
+++ b/llvm/unittests/CodeGen/RematerializerTest.cpp
@@ -7,96 +7,31 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/Rematerializer.h"
-#include "llvm/Analysis/CGSCCPassManager.h"
-#include "llvm/Analysis/LoopAnalysisManager.h"
-#include "llvm/CodeGen/MIRParser/MIRParser.h"
-#include "llvm/CodeGen/MachineDomTreeUpdater.h"
-#include "llvm/CodeGen/MachineFunctionAnalysis.h"
-#include "llvm/CodeGen/MachineModuleInfo.h"
-#include "llvm/CodeGen/MachinePassManager.h"
-#include "llvm/CodeGen/MachinePostDominators.h"
-#include "llvm/CodeGen/MachineScheduler.h"
-#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/TargetLowering.h"
-#include "llvm/IR/Module.h"
-#include "llvm/MC/TargetRegistry.h"
-#include "llvm/Passes/PassBuilder.h"
-#include "llvm/Support/SourceMgr.h"
+#include "CodeGenTestBase.h"
+#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/Support/TargetSelect.h"
-#include "llvm/Target/TargetMachine.h"
-#include "gtest/gtest.h"
-#include <memory>
using namespace llvm;
using RegisterIdx = Rematerializer::RegisterIdx;
-class RematerializerTest : public testing::Test {
+class RematerializerTest : public CodeGenTestBase {
public:
- LLVMContext Context;
- std::unique_ptr<TargetMachine> TM;
- std::unique_ptr<Module> M;
- std::unique_ptr<MachineModuleInfo> MMI;
-
- std::unique_ptr<MIRParser> MIR;
std::unique_ptr<SmallVector<Rematerializer::RegionBoundaries>> Regions;
std::unique_ptr<Rematerializer> Remater;
- MachineFunction *MF;
-
- LoopAnalysisManager LAM;
- MachineFunctionAnalysisManager MFAM;
- FunctionAnalysisManager FAM;
- CGSCCAnalysisManager CGAM;
-
- ModulePassManager MPM;
- FunctionPassManager FPM;
- MachineFunctionPassManager MFPM;
- ModuleAnalysisManager MAM;
+ MachineFunction* MF;
static void SetUpTestCase() {
InitializeAllTargets();
InitializeAllTargetMCs();
}
- void SetUp() override {
- Triple TargetTriple("amdgcn--");
- std::string Error;
- const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error);
- if (!T)
- GTEST_SKIP();
- TargetOptions Options;
- TM = std::unique_ptr<TargetMachine>(T->createTargetMachine(
- TargetTriple, "gfx950", "", Options, std::nullopt));
- if (!TM)
- GTEST_SKIP();
- MMI = std::make_unique<MachineModuleInfo>(TM.get());
-
- PassBuilder PB(TM.get());
- PB.registerModuleAnalyses(MAM);
- PB.registerCGSCCAnalyses(CGAM);
- PB.registerFunctionAnalyses(FAM);
- PB.registerLoopAnalyses(LAM);
- PB.registerMachineFunctionAnalyses(MFAM);
- PB.crossRegisterProxies(LAM, FAM, CGAM, MAM, &MFAM);
- MAM.registerPass([&] { return MachineModuleAnalysis(*MMI); });
- }
+ void SetUp() override { setUpImpl("amdgcn--", "gfx950", ""); }
bool parseMIRAndInit(StringRef MIRCode, StringRef FunName) {
- SMDiagnostic Diagnostic;
- std::unique_ptr<MemoryBuffer> MBuffer = MemoryBuffer::getMemBuffer(MIRCode);
- MIR = createMIRParser(std::move(MBuffer), Context);
- if (!MIR)
+ if (!parseMIR(MIRCode))
return false;
- M = MIR->parseIRModule();
- M->setDataLayout(TM->createDataLayout());
-
- if (MIR->parseMachineFunctions(*M, MAM)) {
- M.reset();
- return false;
- }
-
- MF = &FAM.getResult<MachineFunctionAnalysis>(*M->getFunction(FunName))
- .getMF();
+ MF = &CodeGenTestBase::getMF(FunName);
LiveIntervals &LIS = MFAM.getResult<LiveIntervalsAnalysis>(*MF);
// Create regions for the rematerializer. Both MBBs and terminator MIs
diff --git a/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp b/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
index 81982d0217f71..9f4d6bad96ee8 100644
--- a/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
+++ b/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
@@ -7,6 +7,7 @@
//===----------------------------------------------------------------------===//
#include "AMDGPUUnitTests.h"
+#include "AMDGPUGenSubtargetInfo.inc"
#include "AMDGPUTargetMachine.h"
#include "GCNSubtarget.h"
#include "llvm/MC/TargetRegistry.h"
@@ -14,24 +15,16 @@
#include "llvm/TargetParser/TargetParser.h"
#include "gtest/gtest.h"
-#include "AMDGPUGenSubtargetInfo.inc"
-
using namespace llvm;
-std::once_flag flag;
-
-void InitializeAMDGPUTarget() {
- std::call_once(flag, []() {
- LLVMInitializeAMDGPUTargetInfo();
- LLVMInitializeAMDGPUTarget();
- LLVMInitializeAMDGPUTargetMC();
- });
+void initializeAMDGPUTarget() {
+ LLVMInitializeAMDGPUTargetInfo();
+ LLVMInitializeAMDGPUTarget();
+ LLVMInitializeAMDGPUTargetMC();
}
-std::unique_ptr<const GCNTargetMachine>
-llvm::createAMDGPUTargetMachine(std::string TStr, StringRef CPU, StringRef FS) {
- InitializeAMDGPUTarget();
-
+std::unique_ptr<GCNTargetMachine>
+createAMDGPUTargetMachine(std::string TStr, StringRef CPU, StringRef FS) {
Triple TT(TStr);
std::string Error;
const Target *T = TargetRegistry::lookupTarget(TT, Error);
@@ -180,7 +173,7 @@ static void testDynamicVGPRLimits(StringRef CPUName, StringRef FS,
testWithBlockSize(32);
}
-TEST(AMDGPU, TestVGPRLimitsPerOccupancy) {
+TEST_F(AMDGPUTestBase, TestVGPRLimitsPerOccupancy) {
auto test = [](std::stringstream &OS, unsigned Occ, const GCNSubtarget &ST,
unsigned DynamicVGPRBlockSize) {
unsigned MaxVGPRNum = ST.getAddressableNumVGPRs(DynamicVGPRBlockSize);
@@ -240,7 +233,7 @@ static void testAbsoluteLimits(StringRef CPUName, StringRef FS,
EXPECT_EQ(12u, Range.second) << CPUName << ' ' << FS;
}
-TEST(AMDGPU, TestOccupancyAbsoluteLimits) {
+TEST_F(AMDGPUTestBase, TestOccupancyAbsoluteLimits) {
// CPUName, Features, DynamicVGPRBlockSize; Expected MinOcc, MaxOcc, MaxVGPRs
testAbsoluteLimits("gfx1200", "+wavefrontsize32", 0, 1, 16, 256);
testAbsoluteLimits("gfx1200", "+wavefrontsize32", 16, 1, 16, 128);
@@ -251,7 +244,7 @@ static const char *printSubReg(const TargetRegisterInfo &TRI, unsigned SubReg) {
return SubReg ? TRI.getSubRegIndexName(SubReg) : "<none>";
}
-TEST(AMDGPU, TestReverseComposeSubRegIndices) {
+TEST_F(AMDGPUTestBase, TestReverseComposeSubRegIndices) {
auto TM = createAMDGPUTargetMachine("amdgcn-amd-", "gfx900", "");
if (!TM)
return;
@@ -327,7 +320,7 @@ TEST(AMDGPU, TestReverseComposeSubRegIndices) {
}
}
-TEST(AMDGPU, TestGetNamedOperandIdx) {
+TEST_F(AMDGPUTestBase, TestGetNamedOperandIdx) {
std::unique_ptr<const GCNTargetMachine> TM =
createAMDGPUTargetMachine("amdgcn-amd-", "gfx900", "");
if (!TM)
diff --git a/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.h b/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.h
index ccd2e32527042..466dd56d373b8 100644
--- a/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.h
+++ b/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.h
@@ -9,17 +9,32 @@
#ifndef LLVM_UNITTESTS_TARGET_AMDGPU_AMDGPUUNITTESTS_H
#define LLVM_UNITTESTS_TARGET_AMDGPU_AMDGPUUNITTESTS_H
+#include "AMDGPUGenSubtargetInfo.inc"
+#include "AMDGPUTargetMachine.h"
+#include "CodeGenTestBase.h"
+#include "GCNSubtarget.h"
#include <memory>
#include <string>
namespace llvm {
-
class GCNTargetMachine;
class StringRef;
+} // end namespace llvm
-std::unique_ptr<const GCNTargetMachine>
-createAMDGPUTargetMachine(std::string TStr, StringRef CPU, StringRef FS);
+void initializeAMDGPUTarget();
-} // end namespace llvm
+std::unique_ptr<llvm::GCNTargetMachine>
+createAMDGPUTargetMachine(std::string TStr, llvm::StringRef CPU,
+ llvm::StringRef FS);
+
+class AMDGPUTestBase : public testing::Test {
+public:
+ static void SetUpTestSuite() { initializeAMDGPUTarget(); }
+};
+
+class AMDGPUCodeGenTestBase : public llvm::CodeGenTestBase {
+public:
+ static void SetUpTestSuite() { initializeAMDGPUTarget(); }
+};
#endif // LLVM_UNITTESTS_TARGET_AMDGPU_AMDGPUUNITTESTS_H
diff --git a/llvm/unittests/Target/AMDGPU/CMakeLists.txt b/llvm/unittests/Target/AMDGPU/CMakeLists.txt
index 7760f694933c2..2425556ebe33f 100644
--- a/llvm/unittests/Target/AMDGPU/CMakeLists.txt
+++ b/llvm/unittests/Target/AMDGPU/CMakeLists.txt
@@ -1,6 +1,7 @@
include_directories(
${PROJECT_SOURCE_DIR}/lib/Target/AMDGPU
${PROJECT_BINARY_DIR}/lib/Target/AMDGPU
+ ${PROJECT_SOURCE_DIR}/unittests/CodeGen
)
set(LLVM_LINK_COMPONENTS
diff --git a/llvm/unittests/Target/AMDGPU/CSETest.cpp b/llvm/unittests/Target/AMDGPU/CSETest.cpp
index ff44ff184234c..382f23906e92d 100644
--- a/llvm/unittests/Target/AMDGPU/CSETest.cpp
+++ b/llvm/unittests/Target/AMDGPU/CSETest.cpp
@@ -15,7 +15,7 @@
using namespace llvm;
-TEST(AMDGPU, TestCSEForRegisterClassOrBankAndLLT) {
+TEST_F(AMDGPUTestBase, TestCSEForRegisterClassOrBankAndLLT) {
auto TM = createAMDGPUTargetMachine("amdgcn-amd-", "gfx1100", "");
if (!TM)
GTEST_SKIP();
diff --git a/llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp b/llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
index 68a6b96997223..ec8ed7f15b35a 100644
--- a/llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
+++ b/llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
@@ -12,7 +12,7 @@
using namespace llvm;
-TEST(AMDGPU, TestWave64DwarfRegMapping) {
+TEST_F(AMDGPUTestBase, TestWave64DwarfRegMapping) {
for (auto Triple :
{"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {
auto TM = createAMDGPUTargetMachine(Triple, "gfx1010", "+wavefrontsize64");
@@ -52,7 +52,7 @@ TEST(AMDGPU, TestWave64DwarfRegMapping) {
}
}
-TEST(AMDGPU, TestWave32DwarfRegMapping) {
+TEST_F(AMDGPUTestBase, TestWave32DwarfRegMapping) {
for (auto Triple :
{"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {
auto TM = createAMDGPUTargetMachine(Triple, "gfx1010", "+wavefrontsize32");
diff --git a/llvm/unittests/Target/AMDGPU/ExecMayBeModifiedBeforeAnyUse.cpp b/llvm/unittests/Target/AMDGPU/ExecMayBeModifiedBeforeAnyUse.cpp
index 5ac4edae5f0df..8034bf6561d86 100644
--- a/llvm/unittests/Target/AMDGPU/ExecMayBeModifiedBeforeAnyUse.cpp
+++ b/llvm/unittests/Target/AMDGPU/ExecMayBeModifiedBeforeAnyUse.cpp
@@ -13,7 +13,7 @@
using namespace llvm;
-TEST(AMDGPU, ExecMayBeModifiedBeforeAnyUse) {
+TEST_F(AMDGPUTestBase, ExecMayBeModifiedBeforeAnyUse) {
auto TM = createAMDGPUTargetMachine("amdgcn-amd-", "gfx906", "");
if (!TM)
GTEST_SKIP();
diff --git a/llvm/unittests/Target/AMDGPU/LiveRegUnits.cpp b/llvm/unittests/Target/AMDGPU/LiveRegUnits.cpp
index 95266dc853bfd..ec3d465891467 100644
--- a/llvm/unittests/Target/AMDGPU/LiveRegUnits.cpp
+++ b/llvm/unittests/Target/AMDGPU/LiveRegUnits.cpp
@@ -6,52 +6,22 @@
//
//===----------------------------------------------------------------------===//
-#include "AMDGPUTargetMachine.h"
#include "AMDGPUUnitTests.h"
#include "GCNSubtarget.h"
#include "llvm/CodeGen/MIRParser/MIRParser.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
-#include "llvm/MC/TargetRegistry.h"
-#include "llvm/Support/SourceMgr.h"
-#include "llvm/Support/TargetSelect.h"
-#include "llvm/TargetParser/TargetParser.h"
#include "gtest/gtest.h"
#include "AMDGPUGenSubtargetInfo.inc"
using namespace llvm;
-// FIXME: Consolidate parseMIR and other common helpers (this one is copied from
-// unittests/MIR/MachineMetadata.cpp).
-std::unique_ptr<Module> parseMIR(LLVMContext &Context, const TargetMachine &TM,
- StringRef MIRCode, const char *FnName,
- MachineModuleInfo &MMI) {
- SMDiagnostic Diagnostic;
- std::unique_ptr<MemoryBuffer> MBuffer = MemoryBuffer::getMemBuffer(MIRCode);
- auto MIR = createMIRParser(std::move(MBuffer), Context);
- if (!MIR)
- return nullptr;
-
- std::unique_ptr<Module> Mod = MIR->parseIRModule();
- if (!Mod)
- return nullptr;
-
- Mod->setDataLayout(TM.createDataLayout());
-
- if (MIR->parseMachineFunctions(*Mod, MMI)) {
- return nullptr;
- }
-
- return Mod;
-}
-
-TEST(AMDGPULiveRegUnits, TestVGPRBlockLoadStore) {
- auto TM = createAMDGPUTargetMachine("amdgcn-amd-", "gfx1200", "");
- ASSERT_TRUE(TM) << "No target machine";
-
- GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
- std::string(TM->getTargetFeatureString()), *TM);
+class LiveRegUnitsTest : public AMDGPUCodeGenTestBase {
+public:
+ void SetUp() override { setUpImpl("amdgcn-amd-", "gfx1200", ""); }
+};
+TEST_F(LiveRegUnitsTest, TestVGPRBlockLoadStore) {
// Add a very simple MIR snippet that saves and restores a block of VGPRs. The
// body of the function, represented by a S_NOP, clobbers one CSR (v42) and
// one caller-saved register (v49), and reads one CSR (v61) and one
@@ -76,17 +46,13 @@ body: |
...
)MIR";
- LLVMContext Context;
- MachineModuleInfo MMI(TM.get());
- auto M = parseMIR(Context, *TM, MIRString, "vgpr-block-insts", MMI);
-
- auto *MF = MMI.getMachineFunction(*M->getFunction("vgpr-block-insts"));
- auto *MBB = MF->getBlockNumbered(0);
-
+ ASSERT_TRUE(parseMIR(MIRString));
+ MachineFunction &MF = getMF("vgpr-block-insts");
+ auto *MBB = MF.getBlockNumbered(0);
auto MIt = --MBB->instr_end();
LiveRegUnits LiveUnits;
- LiveUnits.init(*ST.getRegisterInfo());
+ LiveUnits.init(*MF.getSubtarget<GCNSubtarget>().getRegisterInfo());
...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/196547
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