[llvm] [LoongArch][NFC] Add tests for vector extend sitofp/uitofp (PR #196465)
via llvm-commits
llvm-commits at lists.llvm.org
Fri May 8 01:12:48 PDT 2026
https://github.com/lrzlin updated https://github.com/llvm/llvm-project/pull/196465
>From caf52ac56b07585db763b7badbb3a97eea97efab Mon Sep 17 00:00:00 2001
From: Lin Runze <linrunze at loongson.cn>
Date: Fri, 8 May 2026 12:05:40 +0800
Subject: [PATCH 1/2] [LoongArch][NFC] Add tests for vector extend
sitofp/uitofp
---
.../LoongArch/lasx/ir-instruction/sitofp.ll | 217 ++++++++++++++++
.../LoongArch/lasx/ir-instruction/uitofp.ll | 93 +++++++
.../LoongArch/lsx/ir-instruction/sitofp.ll | 242 ++++++++++++++++++
.../LoongArch/lsx/ir-instruction/uitofp.ll | 92 +++++++
4 files changed, 644 insertions(+)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll
index 3673f594094be..3c08d885999d3 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll
@@ -56,3 +56,220 @@ define void @sitofp_v4i32_v4f64(ptr %res, ptr %in){
store <4 x double> %v1, ptr %res
ret void
}
+
+define <2 x float> @sitofp_v2i32_v2f32(<2 x i32> %a) {
+; CHECK-LABEL: sitofp_v2i32_v2f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vffint.s.w $vr0, $vr0
+; CHECK-NEXT: ret
+ %cvt = sitofp <2 x i32> %a to <2 x float>
+ ret <2 x float> %cvt
+}
+
+define <2 x double> @sitofp_v4i32_v2f64(<4 x i32> %a) {
+; CHECK-LABEL: sitofp_v4i32_v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $vr0 killed $vr0 def $xr0
+; CHECK-NEXT: vext2xv.d.w $xr0, $xr0
+; CHECK-NEXT: xvffint.d.l $xr0, $xr0
+; CHECK-NEXT: # kill: def $vr0 killed $vr0 killed $xr0
+; CHECK-NEXT: ret
+ %cvt = sitofp <4 x i32> %a to <4 x double>
+ %shuf = shufflevector <4 x double> %cvt, <4 x double> undef, <2 x i32> <i32 0, i32 1>
+ ret <2 x double> %shuf
+}
+
+define <2 x double> @sitofp_v2i16_v2f64(<8 x i16> %a) {
+; CHECK-LABEL: sitofp_v2i16_v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: ret
+ %shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
+ %cvt = sitofp <2 x i16> %shuf to <2 x double>
+ ret <2 x double> %cvt
+}
+
+define <2 x double> @sitofp_v8i16_v2f64(<8 x i16> %a) {
+; CHECK-LABEL: sitofp_v8i16_v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr1, $vr0, 16
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %cvt = sitofp <8 x i16> %a to <8 x double>
+ %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <2 x i32> <i32 0, i32 1>
+ ret <2 x double> %shuf
+}
+
+define <2 x double> @sitofp_v2i8_v2f64(<16 x i8> %a) {
+; CHECK-LABEL: sitofp_v2i8_v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: ret
+ %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
+ %cvt = sitofp <2 x i8> %shuf to <2 x double>
+ ret <2 x double> %cvt
+}
+
+define <2 x double> @sitofp_v16i8_v2f64(<16 x i8> %a) {
+; CHECK-LABEL: sitofp_v16i8_v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr1, $vr0, 16
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %cvt = sitofp <16 x i8> %a to <16 x double>
+ %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <2 x i32> <i32 0, i32 1>
+ ret <2 x double> %shuf
+}
+
+define <4 x double> @sitofp_v4i64_v4f64(<4 x i64> %a) {
+; CHECK-LABEL: sitofp_v4i64_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xvffint.d.l $xr0, $xr0
+; CHECK-NEXT: ret
+ %cvt = sitofp <4 x i64> %a to <4 x double>
+ ret <4 x double> %cvt
+}
+
+define <4 x double> @sitofp_v4i16_v4f64(<8 x i16> %a) {
+; CHECK-LABEL: sitofp_v4i16_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 2
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa2, $a0
+; CHECK-NEXT: ffint.d.w $fa2, $fa2
+; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: xvpermi.q $xr0, $xr2, 2
+; CHECK-NEXT: ret
+ %shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %cvt = sitofp <4 x i16> %shuf to <4 x double>
+ ret <4 x double> %cvt
+}
+
+define <4 x double> @sitofp_v8i16_v4f64(<8 x i16> %a) {
+; CHECK-LABEL: sitofp_v8i16_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 2
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa2, $a0
+; CHECK-NEXT: ffint.d.w $fa2, $fa2
+; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: xvpermi.q $xr0, $xr2, 2
+; CHECK-NEXT: ret
+ %cvt = sitofp <8 x i16> %a to <8 x double>
+ %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x double> %shuf
+}
+
+define <4 x double> @sitofp_v4i8_v4f64(<16 x i8> %a) {
+; CHECK-LABEL: sitofp_v4i8_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa2, $a0
+; CHECK-NEXT: ffint.d.w $fa2, $fa2
+; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: xvpermi.q $xr0, $xr2, 2
+; CHECK-NEXT: ret
+ %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %cvt = sitofp <4 x i8> %shuf to <4 x double>
+ ret <4 x double> %cvt
+}
+
+define <4 x double> @sitofp_v16i8_v4f64(<16 x i8> %a) {
+; CHECK-LABEL: sitofp_v16i8_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa2, $a0
+; CHECK-NEXT: ffint.d.w $fa2, $fa2
+; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: xvpermi.q $xr0, $xr2, 2
+; CHECK-NEXT: ret
+ %cvt = sitofp <16 x i8> %a to <16 x double>
+ %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x double> %shuf
+}
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll
index 6e417032acff5..363a16ab1d6f2 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll
@@ -56,3 +56,96 @@ define void @uitofp_v4i32_v4f64(ptr %res, ptr %in){
store <4 x double> %v1, ptr %res
ret void
}
+
+define <2 x double> @uitofp_v2i8_v2f64(<16 x i8> %a) {
+; CHECK-LABEL: uitofp_v2i8_v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: ret
+ %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
+ %cvt = uitofp <2 x i8> %shuf to <2 x double>
+ ret <2 x double> %cvt
+}
+
+define <2 x double> @uitofp_v16i8_v2f64(<16 x i8> %a) {
+; CHECK-LABEL: uitofp_v16i8_v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr1, $vr0, 16
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %cvt = uitofp <16 x i8> %a to <16 x double>
+ %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <2 x i32> <i32 0, i32 1>
+ ret <2 x double> %shuf
+}
+
+define <4 x double> @uitofp_v4i8_v4f64(<16 x i8> %a) {
+; CHECK-LABEL: uitofp_v4i8_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa2, $a0
+; CHECK-NEXT: ffint.d.w $fa2, $fa2
+; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: xvpermi.q $xr0, $xr2, 2
+; CHECK-NEXT: ret
+ %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %cvt = uitofp <4 x i8> %shuf to <4 x double>
+ ret <4 x double> %cvt
+}
+
+define <4 x double> @uitofp_v16i8_v4f64(<16 x i8> %a) {
+; CHECK-LABEL: uitofp_v16i8_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa2, $a0
+; CHECK-NEXT: ffint.d.w $fa2, $fa2
+; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: xvpermi.q $xr0, $xr2, 2
+; CHECK-NEXT: ret
+ %cvt = uitofp <16 x i8> %a to <16 x double>
+ %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x double> %shuf
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll
index 37eb9e7e8dc49..04425493ca4fe 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll
@@ -27,3 +27,245 @@ define void @sitofp_v2i64_v2f64(ptr %res, ptr %in){
store <2 x double> %v1, ptr %res
ret void
}
+
+define <4 x double> @sitofp_v4i64_v4f64(<4 x i64> %a) {
+; CHECK-LABEL: sitofp_v4i64_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vffint.d.l $vr0, $vr0
+; CHECK-NEXT: vffint.d.l $vr1, $vr1
+; CHECK-NEXT: ret
+ %cvt = sitofp <4 x i64> %a to <4 x double>
+ ret <4 x double> %cvt
+}
+
+define <4 x double> @sitofp_v4i32_v4f64(<4 x i32> %a) {
+; CHECK-LABEL: sitofp_v4i32_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 1
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 0
+; CHECK-NEXT: movgr2fr.w $fa2, $a0
+; CHECK-NEXT: ffint.d.w $fa2, $fa2
+; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
+; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 3
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa3, $fa1
+; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 2
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa0
+; CHECK-NEXT: vextrins.d $vr1, $vr3, 16
+; CHECK-NEXT: vori.b $vr0, $vr2, 0
+; CHECK-NEXT: ret
+ %cvt = sitofp <4 x i32> %a to <4 x double>
+ ret <4 x double> %cvt
+}
+
+define <2 x float> @sitofp_v2i32_v2f32(<2 x i32> %a) {
+; CHECK-LABEL: sitofp_v2i32_v2f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vffint.s.w $vr0, $vr0
+; CHECK-NEXT: ret
+ %cvt = sitofp <2 x i32> %a to <2 x float>
+ ret <2 x float> %cvt
+}
+
+define <2 x double> @sitofp_v4i32_v2f64(<4 x i32> %a) {
+; CHECK-LABEL: sitofp_v4i32_v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 1
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 0
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: ret
+ %cvt = sitofp <4 x i32> %a to <4 x double>
+ %shuf = shufflevector <4 x double> %cvt, <4 x double> undef, <2 x i32> <i32 0, i32 1>
+ ret <2 x double> %shuf
+}
+
+define <2 x double> @sitofp_v2i16_v2f64(<8 x i16> %a) {
+; CHECK-LABEL: sitofp_v2i16_v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: ret
+ %shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
+ %cvt = sitofp <2 x i16> %shuf to <2 x double>
+ ret <2 x double> %cvt
+}
+
+define <2 x double> @sitofp_v8i16_v2f64(<8 x i16> %a) {
+; CHECK-LABEL: sitofp_v8i16_v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: ret
+ %cvt = sitofp <8 x i16> %a to <8 x double>
+ %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <2 x i32> <i32 0, i32 1>
+ ret <2 x double> %shuf
+}
+
+define <2 x double> @sitofp_v2i8_v2f64(<16 x i8> %a) {
+; CHECK-LABEL: sitofp_v2i8_v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: ret
+ %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
+ %cvt = sitofp <2 x i8> %shuf to <2 x double>
+ ret <2 x double> %cvt
+}
+
+define <2 x double> @sitofp_v16i8_v2f64(<16 x i8> %a) {
+; CHECK-LABEL: sitofp_v16i8_v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: ret
+ %cvt = sitofp <16 x i8> %a to <16 x double>
+ %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <2 x i32> <i32 0, i32 1>
+ ret <2 x double> %shuf
+}
+
+define <4 x double> @sitofp_v4i16_v4f64(<8 x i16> %a) {
+; CHECK-LABEL: sitofp_v4i16_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa2, $a0
+; CHECK-NEXT: ffint.d.w $fa2, $fa2
+; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa3, $fa1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 2
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa0
+; CHECK-NEXT: vextrins.d $vr1, $vr3, 16
+; CHECK-NEXT: vori.b $vr0, $vr2, 0
+; CHECK-NEXT: ret
+ %shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %cvt = sitofp <4 x i16> %shuf to <4 x double>
+ ret <4 x double> %cvt
+}
+
+define <4 x double> @sitofp_v8i16_v4f64(<8 x i16> %a) {
+; CHECK-LABEL: sitofp_v8i16_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa2, $a0
+; CHECK-NEXT: ffint.d.w $fa2, $fa2
+; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa3, $fa1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 2
+; CHECK-NEXT: ext.w.h $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa0
+; CHECK-NEXT: vextrins.d $vr1, $vr3, 16
+; CHECK-NEXT: vori.b $vr0, $vr2, 0
+; CHECK-NEXT: ret
+ %cvt = sitofp <8 x i16> %a to <8 x double>
+ %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x double> %shuf
+}
+
+define <4 x double> @sitofp_v4i8_v4f64(<16 x i8> %a) {
+; CHECK-LABEL: sitofp_v4i8_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa2, $a0
+; CHECK-NEXT: ffint.d.w $fa2, $fa2
+; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa3, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa0
+; CHECK-NEXT: vextrins.d $vr1, $vr3, 16
+; CHECK-NEXT: vori.b $vr0, $vr2, 0
+; CHECK-NEXT: ret
+ %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %cvt = sitofp <4 x i8> %shuf to <4 x double>
+ ret <4 x double> %cvt
+}
+
+define <4 x double> @sitofp_v16i8_v4f64(<16 x i8> %a) {
+; CHECK-LABEL: sitofp_v16i8_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa2, $a0
+; CHECK-NEXT: ffint.d.w $fa2, $fa2
+; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa3, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
+; CHECK-NEXT: ext.w.b $a0, $a0
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa0
+; CHECK-NEXT: vextrins.d $vr1, $vr3, 16
+; CHECK-NEXT: vori.b $vr0, $vr2, 0
+; CHECK-NEXT: ret
+ %cvt = sitofp <16 x i8> %a to <16 x double>
+ %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x double> %shuf
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll
index 3ae1119435eff..dc93938834bfb 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll
@@ -27,3 +27,95 @@ define void @uitofp_v2i64_v2f64(ptr %res, ptr %in){
store <2 x double> %v1, ptr %res
ret void
}
+
+define <2 x double> @uitofp_v2i8_v2f64(<16 x i8> %a) {
+; CHECK-LABEL: uitofp_v2i8_v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: ret
+ %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
+ %cvt = uitofp <2 x i8> %shuf to <2 x double>
+ ret <2 x double> %cvt
+}
+
+define <2 x double> @uitofp_v16i8_v2f64(<16 x i8> %a) {
+; CHECK-LABEL: uitofp_v16i8_v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: ret
+ %cvt = uitofp <16 x i8> %a to <16 x double>
+ %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <2 x i32> <i32 0, i32 1>
+ ret <2 x double> %shuf
+}
+
+define <4 x double> @uitofp_v4i8_v4f64(<16 x i8> %a) {
+; CHECK-LABEL: uitofp_v4i8_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa2, $a0
+; CHECK-NEXT: ffint.d.w $fa2, $fa2
+; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa3, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa0
+; CHECK-NEXT: vextrins.d $vr1, $vr3, 16
+; CHECK-NEXT: vori.b $vr0, $vr2, 0
+; CHECK-NEXT: ret
+ %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %cvt = uitofp <4 x i8> %shuf to <4 x double>
+ ret <4 x double> %cvt
+}
+
+define <4 x double> @uitofp_v16i8_v4f64(<16 x i8> %a) {
+; CHECK-LABEL: uitofp_v16i8_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa2, $a0
+; CHECK-NEXT: ffint.d.w $fa2, $fa2
+; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa1, $a0
+; CHECK-NEXT: ffint.d.w $fa3, $fa1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
+; CHECK-NEXT: andi $a0, $a0, 255
+; CHECK-NEXT: movgr2fr.w $fa0, $a0
+; CHECK-NEXT: ffint.d.w $fa1, $fa0
+; CHECK-NEXT: vextrins.d $vr1, $vr3, 16
+; CHECK-NEXT: vori.b $vr0, $vr2, 0
+; CHECK-NEXT: ret
+ %cvt = uitofp <16 x i8> %a to <16 x double>
+ %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x double> %shuf
+}
>From e74ce396c9334f76a510ed89c572ccc27ab7b221 Mon Sep 17 00:00:00 2001
From: Lin Runze <linrunze at loongson.cn>
Date: Fri, 8 May 2026 12:11:58 +0800
Subject: [PATCH 2/2] [LoongArch] Use vector extend for sitofp/uitofp
---
.../LoongArch/LoongArchISelLowering.cpp | 50 +++++
.../LoongArch/lasx/ir-instruction/sitofp.ll | 164 ++++----------
.../LoongArch/lasx/ir-instruction/uitofp.ll | 82 ++-----
.../LoongArch/lsx/ir-instruction/sitofp.ll | 211 ++++++------------
.../LoongArch/lsx/ir-instruction/uitofp.ll | 88 +++-----
5 files changed, 209 insertions(+), 386 deletions(-)
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index e3bdf2b993036..9840fe109d84e 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -498,6 +498,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
// Set DAG combine for LA32 and LA64.
if (Subtarget.hasBasicF()) {
setTargetDAGCombine(ISD::SINT_TO_FP);
+ setTargetDAGCombine(ISD::UINT_TO_FP);
}
setTargetDAGCombine(ISD::AND);
@@ -7749,6 +7750,25 @@ static SDValue performSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
SDLoc DL(N);
EVT VT = N->getValueType(0);
+ // Sign-extend src to avoid scalarization.
+ if (VT.isVector()) {
+ SDValue Src = N->getOperand(0);
+ EVT SrcVT = Src.getValueType();
+
+ unsigned DstElts = VT.getVectorNumElements();
+ unsigned SrcEltBits = SrcVT.getScalarSizeInBits();
+ unsigned DstEltBits = VT.getScalarSizeInBits();
+
+ if (SrcEltBits >= DstEltBits)
+ return SDValue();
+
+ MVT WidenEltVT = MVT::getIntegerVT(DstEltBits);
+ MVT WidenSrcVT = MVT::getVectorVT(WidenEltVT, DstElts);
+
+ SDValue Extend = DAG.getNode(ISD::SIGN_EXTEND, DL, WidenSrcVT, Src);
+ return DAG.getNode(ISD::SINT_TO_FP, DL, VT, Extend);
+ }
+
if (VT != MVT::f32 && VT != MVT::f64)
return SDValue();
if (VT == MVT::f32 && !Subtarget.hasBasicF())
@@ -7782,6 +7802,34 @@ static SDValue performSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
return SDValue();
}
+static SDValue performUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
+ TargetLowering::DAGCombinerInfo &DCI,
+ const LoongArchSubtarget &Subtarget) {
+ SDLoc DL(N);
+ EVT VT = N->getValueType(0);
+
+ // Zero-extend src to avoid scalarization.
+ if (VT.isVector()) {
+ SDValue Src = N->getOperand(0);
+ EVT SrcVT = Src.getValueType();
+
+ unsigned DstElts = VT.getVectorNumElements();
+ unsigned SrcEltBits = SrcVT.getScalarSizeInBits();
+ unsigned DstEltBits = VT.getScalarSizeInBits();
+
+ if (SrcEltBits >= DstEltBits)
+ return SDValue();
+
+ MVT WidenEltVT = MVT::getIntegerVT(DstEltBits);
+ MVT WidenSrcVT = MVT::getVectorVT(WidenEltVT, DstElts);
+
+ SDValue Extend = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenSrcVT, Src);
+ return DAG.getNode(ISD::UINT_TO_FP, DL, VT, Extend);
+ }
+
+ return SDValue();
+}
+
// Try to widen AND, OR and XOR nodes to VT in order to remove casts around
// logical operations, like in the example below.
// or (and (truncate x, truncate y)),
@@ -8067,6 +8115,8 @@ SDValue LoongArchTargetLowering::PerformDAGCombine(SDNode *N,
return performEXTENDCombine(N, DAG, DCI, Subtarget);
case ISD::SINT_TO_FP:
return performSINT_TO_FPCombine(N, DAG, DCI, Subtarget);
+ case ISD::UINT_TO_FP:
+ return performUINT_TO_FPCombine(N, DAG, DCI, Subtarget);
case LoongArchISD::BITREV_W:
return performBITREV_WCombine(N, DAG, DCI, Subtarget);
case LoongArchISD::BR_CC:
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll
index 3c08d885999d3..5e3261a22c404 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll
@@ -75,24 +75,18 @@ define <2 x double> @sitofp_v4i32_v2f64(<4 x i32> %a) {
; CHECK-NEXT: # kill: def $vr0 killed $vr0 killed $xr0
; CHECK-NEXT: ret
%cvt = sitofp <4 x i32> %a to <4 x double>
- %shuf = shufflevector <4 x double> %cvt, <4 x double> undef, <2 x i32> <i32 0, i32 1>
+ %shuf = shufflevector <4 x double> %cvt, <4 x double> poison, <2 x i32> <i32 0, i32 1>
ret <2 x double> %shuf
}
define <2 x double> @sitofp_v2i16_v2f64(<8 x i16> %a) {
; CHECK-LABEL: sitofp_v2i16_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa0, $fa0
-; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: # kill: def $vr0 killed $vr0 def $xr0
+; CHECK-NEXT: vext2xv.d.h $xr0, $xr0
+; CHECK-NEXT: vffint.d.l $vr0, $vr0
; CHECK-NEXT: ret
- %shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
+ %shuf = shufflevector <8 x i16> %a, <8 x i16> poison, <2 x i32> <i32 0, i32 1>
%cvt = sitofp <2 x i16> %shuf to <2 x double>
ret <2 x double> %cvt
}
@@ -100,36 +94,25 @@ define <2 x double> @sitofp_v2i16_v2f64(<8 x i16> %a) {
define <2 x double> @sitofp_v8i16_v2f64(<8 x i16> %a) {
; CHECK-LABEL: sitofp_v8i16_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa0, $fa0
-; CHECK-NEXT: vextrins.d $vr1, $vr0, 16
-; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: # kill: def $vr0 killed $vr0 def $xr0
+; CHECK-NEXT: vext2xv.w.h $xr0, $xr0
+; CHECK-NEXT: vext2xv.d.w $xr0, $xr0
+; CHECK-NEXT: xvffint.d.l $xr0, $xr0
+; CHECK-NEXT: # kill: def $vr0 killed $vr0 killed $xr0
; CHECK-NEXT: ret
%cvt = sitofp <8 x i16> %a to <8 x double>
- %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <2 x i32> <i32 0, i32 1>
+ %shuf = shufflevector <8 x double> %cvt, <8 x double> poison, <2 x i32> <i32 0, i32 1>
ret <2 x double> %shuf
}
define <2 x double> @sitofp_v2i8_v2f64(<16 x i8> %a) {
; CHECK-LABEL: sitofp_v2i8_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa0, $fa0
-; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: # kill: def $vr0 killed $vr0 def $xr0
+; CHECK-NEXT: vext2xv.d.b $xr0, $xr0
+; CHECK-NEXT: vffint.d.l $vr0, $vr0
; CHECK-NEXT: ret
- %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
+ %shuf = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 0, i32 1>
%cvt = sitofp <2 x i8> %shuf to <2 x double>
ret <2 x double> %cvt
}
@@ -137,19 +120,15 @@ define <2 x double> @sitofp_v2i8_v2f64(<16 x i8> %a) {
define <2 x double> @sitofp_v16i8_v2f64(<16 x i8> %a) {
; CHECK-LABEL: sitofp_v16i8_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa0, $fa0
-; CHECK-NEXT: vextrins.d $vr1, $vr0, 16
-; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: # kill: def $vr0 killed $vr0 def $xr0
+; CHECK-NEXT: vext2xv.h.b $xr0, $xr0
+; CHECK-NEXT: vext2xv.w.h $xr0, $xr0
+; CHECK-NEXT: vext2xv.d.w $xr0, $xr0
+; CHECK-NEXT: xvffint.d.l $xr0, $xr0
+; CHECK-NEXT: # kill: def $vr0 killed $vr0 killed $xr0
; CHECK-NEXT: ret
%cvt = sitofp <16 x i8> %a to <16 x double>
- %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <2 x i32> <i32 0, i32 1>
+ %shuf = shufflevector <16 x double> %cvt, <16 x double> poison, <2 x i32> <i32 0, i32 1>
ret <2 x double> %shuf
}
@@ -165,27 +144,11 @@ define <4 x double> @sitofp_v4i64_v4f64(<4 x i64> %a) {
define <4 x double> @sitofp_v4i16_v4f64(<8 x i16> %a) {
; CHECK-LABEL: sitofp_v4i16_v4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 2
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa2, $a0
-; CHECK-NEXT: ffint.d.w $fa2, $fa2
-; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa0, $fa0
-; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
-; CHECK-NEXT: xvpermi.q $xr0, $xr2, 2
+; CHECK-NEXT: # kill: def $vr0 killed $vr0 def $xr0
+; CHECK-NEXT: vext2xv.d.h $xr0, $xr0
+; CHECK-NEXT: xvffint.d.l $xr0, $xr0
; CHECK-NEXT: ret
- %shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %shuf = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%cvt = sitofp <4 x i16> %shuf to <4 x double>
ret <4 x double> %cvt
}
@@ -193,55 +156,24 @@ define <4 x double> @sitofp_v4i16_v4f64(<8 x i16> %a) {
define <4 x double> @sitofp_v8i16_v4f64(<8 x i16> %a) {
; CHECK-LABEL: sitofp_v8i16_v4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 2
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa2, $a0
-; CHECK-NEXT: ffint.d.w $fa2, $fa2
-; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa0, $fa0
-; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
-; CHECK-NEXT: xvpermi.q $xr0, $xr2, 2
+; CHECK-NEXT: # kill: def $vr0 killed $vr0 def $xr0
+; CHECK-NEXT: vext2xv.w.h $xr0, $xr0
+; CHECK-NEXT: vext2xv.d.w $xr0, $xr0
+; CHECK-NEXT: xvffint.d.l $xr0, $xr0
; CHECK-NEXT: ret
%cvt = sitofp <8 x i16> %a to <8 x double>
- %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %shuf = shufflevector <8 x double> %cvt, <8 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x double> %shuf
}
define <4 x double> @sitofp_v4i8_v4f64(<16 x i8> %a) {
; CHECK-LABEL: sitofp_v4i8_v4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa2, $a0
-; CHECK-NEXT: ffint.d.w $fa2, $fa2
-; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa0, $fa0
-; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
-; CHECK-NEXT: xvpermi.q $xr0, $xr2, 2
+; CHECK-NEXT: # kill: def $vr0 killed $vr0 def $xr0
+; CHECK-NEXT: vext2xv.d.b $xr0, $xr0
+; CHECK-NEXT: xvffint.d.l $xr0, $xr0
; CHECK-NEXT: ret
- %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %shuf = shufflevector <16 x i8> %a, <16 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%cvt = sitofp <4 x i8> %shuf to <4 x double>
ret <4 x double> %cvt
}
@@ -249,27 +181,13 @@ define <4 x double> @sitofp_v4i8_v4f64(<16 x i8> %a) {
define <4 x double> @sitofp_v16i8_v4f64(<16 x i8> %a) {
; CHECK-LABEL: sitofp_v16i8_v4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa2, $a0
-; CHECK-NEXT: ffint.d.w $fa2, $fa2
-; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa0, $fa0
-; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
-; CHECK-NEXT: xvpermi.q $xr0, $xr2, 2
+; CHECK-NEXT: # kill: def $vr0 killed $vr0 def $xr0
+; CHECK-NEXT: vext2xv.h.b $xr0, $xr0
+; CHECK-NEXT: vext2xv.w.h $xr0, $xr0
+; CHECK-NEXT: vext2xv.d.w $xr0, $xr0
+; CHECK-NEXT: xvffint.d.l $xr0, $xr0
; CHECK-NEXT: ret
%cvt = sitofp <16 x i8> %a to <16 x double>
- %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %shuf = shufflevector <16 x double> %cvt, <16 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x double> %shuf
}
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll
index 363a16ab1d6f2..8d5ec3f64ebcf 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll
@@ -60,17 +60,11 @@ define void @uitofp_v4i32_v4f64(ptr %res, ptr %in){
define <2 x double> @uitofp_v2i8_v2f64(<16 x i8> %a) {
; CHECK-LABEL: uitofp_v2i8_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa0, $fa0
-; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: # kill: def $vr0 killed $vr0 def $xr0
+; CHECK-NEXT: vext2xv.du.bu $xr0, $xr0
+; CHECK-NEXT: vffint.d.lu $vr0, $vr0
; CHECK-NEXT: ret
- %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
+ %shuf = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 0, i32 1>
%cvt = uitofp <2 x i8> %shuf to <2 x double>
ret <2 x double> %cvt
}
@@ -78,46 +72,26 @@ define <2 x double> @uitofp_v2i8_v2f64(<16 x i8> %a) {
define <2 x double> @uitofp_v16i8_v2f64(<16 x i8> %a) {
; CHECK-LABEL: uitofp_v16i8_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa0, $fa0
-; CHECK-NEXT: vextrins.d $vr1, $vr0, 16
-; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: # kill: def $vr0 killed $vr0 def $xr0
+; CHECK-NEXT: vext2xv.hu.bu $xr0, $xr0
+; CHECK-NEXT: vext2xv.wu.hu $xr0, $xr0
+; CHECK-NEXT: vext2xv.du.wu $xr0, $xr0
+; CHECK-NEXT: xvffint.d.lu $xr0, $xr0
+; CHECK-NEXT: # kill: def $vr0 killed $vr0 killed $xr0
; CHECK-NEXT: ret
%cvt = uitofp <16 x i8> %a to <16 x double>
- %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <2 x i32> <i32 0, i32 1>
+ %shuf = shufflevector <16 x double> %cvt, <16 x double> poison, <2 x i32> <i32 0, i32 1>
ret <2 x double> %shuf
}
define <4 x double> @uitofp_v4i8_v4f64(<16 x i8> %a) {
; CHECK-LABEL: uitofp_v4i8_v4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa2, $a0
-; CHECK-NEXT: ffint.d.w $fa2, $fa2
-; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa0, $fa0
-; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
-; CHECK-NEXT: xvpermi.q $xr0, $xr2, 2
+; CHECK-NEXT: # kill: def $vr0 killed $vr0 def $xr0
+; CHECK-NEXT: vext2xv.du.bu $xr0, $xr0
+; CHECK-NEXT: xvffint.d.lu $xr0, $xr0
; CHECK-NEXT: ret
- %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %shuf = shufflevector <16 x i8> %a, <16 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%cvt = uitofp <4 x i8> %shuf to <4 x double>
ret <4 x double> %cvt
}
@@ -125,27 +99,13 @@ define <4 x double> @uitofp_v4i8_v4f64(<16 x i8> %a) {
define <4 x double> @uitofp_v16i8_v4f64(<16 x i8> %a) {
; CHECK-LABEL: uitofp_v16i8_v4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa2, $a0
-; CHECK-NEXT: ffint.d.w $fa2, $fa2
-; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa0, $fa0
-; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
-; CHECK-NEXT: xvpermi.q $xr0, $xr2, 2
+; CHECK-NEXT: # kill: def $vr0 killed $vr0 def $xr0
+; CHECK-NEXT: vext2xv.hu.bu $xr0, $xr0
+; CHECK-NEXT: vext2xv.wu.hu $xr0, $xr0
+; CHECK-NEXT: vext2xv.du.wu $xr0, $xr0
+; CHECK-NEXT: xvffint.d.lu $xr0, $xr0
; CHECK-NEXT: ret
%cvt = uitofp <16 x i8> %a to <16 x double>
- %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %shuf = shufflevector <16 x double> %cvt, <16 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x double> %shuf
}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll
index 04425493ca4fe..18a3bcd70b465 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll
@@ -41,20 +41,11 @@ define <4 x double> @sitofp_v4i64_v4f64(<4 x i64> %a) {
define <4 x double> @sitofp_v4i32_v4f64(<4 x i32> %a) {
; CHECK-LABEL: sitofp_v4i32_v4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 1
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 0
-; CHECK-NEXT: movgr2fr.w $fa2, $a0
-; CHECK-NEXT: ffint.d.w $fa2, $fa2
-; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
-; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 3
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa3, $fa1
-; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 2
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa0
-; CHECK-NEXT: vextrins.d $vr1, $vr3, 16
+; CHECK-NEXT: vslti.w $vr1, $vr0, 0
+; CHECK-NEXT: vilvl.w $vr2, $vr1, $vr0
+; CHECK-NEXT: vffint.d.l $vr2, $vr2
+; CHECK-NEXT: vilvh.w $vr0, $vr1, $vr0
+; CHECK-NEXT: vffint.d.l $vr1, $vr0
; CHECK-NEXT: vori.b $vr0, $vr2, 0
; CHECK-NEXT: ret
%cvt = sitofp <4 x i32> %a to <4 x double>
@@ -73,33 +64,24 @@ define <2 x float> @sitofp_v2i32_v2f32(<2 x i32> %a) {
define <2 x double> @sitofp_v4i32_v2f64(<4 x i32> %a) {
; CHECK-LABEL: sitofp_v4i32_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 1
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 0
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa0, $fa0
-; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: vslti.w $vr1, $vr0, 0
+; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr0
+; CHECK-NEXT: vffint.d.l $vr0, $vr0
; CHECK-NEXT: ret
%cvt = sitofp <4 x i32> %a to <4 x double>
- %shuf = shufflevector <4 x double> %cvt, <4 x double> undef, <2 x i32> <i32 0, i32 1>
+ %shuf = shufflevector <4 x double> %cvt, <4 x double> poison, <2 x i32> <i32 0, i32 1>
ret <2 x double> %shuf
}
define <2 x double> @sitofp_v2i16_v2f64(<8 x i16> %a) {
; CHECK-LABEL: sitofp_v2i16_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa0, $fa0
-; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: vextrins.h $vr0, $vr0, 65
+; CHECK-NEXT: vslli.d $vr0, $vr0, 48
+; CHECK-NEXT: vsrai.d $vr0, $vr0, 48
+; CHECK-NEXT: vffint.d.l $vr0, $vr0
; CHECK-NEXT: ret
- %shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
+ %shuf = shufflevector <8 x i16> %a, <8 x i16> poison, <2 x i32> <i32 0, i32 1>
%cvt = sitofp <2 x i16> %shuf to <2 x double>
ret <2 x double> %cvt
}
@@ -107,35 +89,26 @@ define <2 x double> @sitofp_v2i16_v2f64(<8 x i16> %a) {
define <2 x double> @sitofp_v8i16_v2f64(<8 x i16> %a) {
; CHECK-LABEL: sitofp_v8i16_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa0, $fa0
-; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: vslti.h $vr1, $vr0, 0
+; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0
+; CHECK-NEXT: vslti.w $vr1, $vr0, 0
+; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr0
+; CHECK-NEXT: vffint.d.l $vr0, $vr0
; CHECK-NEXT: ret
%cvt = sitofp <8 x i16> %a to <8 x double>
- %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <2 x i32> <i32 0, i32 1>
+ %shuf = shufflevector <8 x double> %cvt, <8 x double> poison, <2 x i32> <i32 0, i32 1>
ret <2 x double> %shuf
}
define <2 x double> @sitofp_v2i8_v2f64(<16 x i8> %a) {
; CHECK-LABEL: sitofp_v2i8_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa0, $fa0
-; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: vextrins.b $vr0, $vr0, 129
+; CHECK-NEXT: vslli.d $vr0, $vr0, 56
+; CHECK-NEXT: vsrai.d $vr0, $vr0, 56
+; CHECK-NEXT: vffint.d.l $vr0, $vr0
; CHECK-NEXT: ret
- %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
+ %shuf = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 0, i32 1>
%cvt = sitofp <2 x i8> %shuf to <2 x double>
ret <2 x double> %cvt
}
@@ -143,45 +116,31 @@ define <2 x double> @sitofp_v2i8_v2f64(<16 x i8> %a) {
define <2 x double> @sitofp_v16i8_v2f64(<16 x i8> %a) {
; CHECK-LABEL: sitofp_v16i8_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa0, $fa0
-; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: vslti.b $vr1, $vr0, 0
+; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr0
+; CHECK-NEXT: vslti.h $vr1, $vr0, 0
+; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0
+; CHECK-NEXT: vslti.w $vr1, $vr0, 0
+; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr0
+; CHECK-NEXT: vffint.d.l $vr0, $vr0
; CHECK-NEXT: ret
%cvt = sitofp <16 x i8> %a to <16 x double>
- %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <2 x i32> <i32 0, i32 1>
+ %shuf = shufflevector <16 x double> %cvt, <16 x double> poison, <2 x i32> <i32 0, i32 1>
ret <2 x double> %shuf
}
define <4 x double> @sitofp_v4i16_v4f64(<8 x i16> %a) {
; CHECK-LABEL: sitofp_v4i16_v4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa2, $a0
-; CHECK-NEXT: ffint.d.w $fa2, $fa2
-; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa3, $fa1
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 2
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa0
-; CHECK-NEXT: vextrins.d $vr1, $vr3, 16
-; CHECK-NEXT: vori.b $vr0, $vr2, 0
+; CHECK-NEXT: vslti.h $vr1, $vr0, 0
+; CHECK-NEXT: vilvl.h $vr1, $vr1, $vr0
+; CHECK-NEXT: vslti.w $vr2, $vr1, 0
+; CHECK-NEXT: vilvl.w $vr0, $vr2, $vr1
+; CHECK-NEXT: vffint.d.l $vr0, $vr0
+; CHECK-NEXT: vilvh.w $vr1, $vr2, $vr1
+; CHECK-NEXT: vffint.d.l $vr1, $vr1
; CHECK-NEXT: ret
- %shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %shuf = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%cvt = sitofp <4 x i16> %shuf to <4 x double>
ret <4 x double> %cvt
}
@@ -189,55 +148,33 @@ define <4 x double> @sitofp_v4i16_v4f64(<8 x i16> %a) {
define <4 x double> @sitofp_v8i16_v4f64(<8 x i16> %a) {
; CHECK-LABEL: sitofp_v8i16_v4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa2, $a0
-; CHECK-NEXT: ffint.d.w $fa2, $fa2
-; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa3, $fa1
-; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 2
-; CHECK-NEXT: ext.w.h $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa0
-; CHECK-NEXT: vextrins.d $vr1, $vr3, 16
-; CHECK-NEXT: vori.b $vr0, $vr2, 0
+; CHECK-NEXT: vslti.h $vr1, $vr0, 0
+; CHECK-NEXT: vilvl.h $vr1, $vr1, $vr0
+; CHECK-NEXT: vslti.w $vr2, $vr1, 0
+; CHECK-NEXT: vilvl.w $vr0, $vr2, $vr1
+; CHECK-NEXT: vffint.d.l $vr0, $vr0
+; CHECK-NEXT: vilvh.w $vr1, $vr2, $vr1
+; CHECK-NEXT: vffint.d.l $vr1, $vr1
; CHECK-NEXT: ret
%cvt = sitofp <8 x i16> %a to <8 x double>
- %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %shuf = shufflevector <8 x double> %cvt, <8 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x double> %shuf
}
define <4 x double> @sitofp_v4i8_v4f64(<16 x i8> %a) {
; CHECK-LABEL: sitofp_v4i8_v4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa2, $a0
-; CHECK-NEXT: ffint.d.w $fa2, $fa2
-; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa3, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa0
-; CHECK-NEXT: vextrins.d $vr1, $vr3, 16
-; CHECK-NEXT: vori.b $vr0, $vr2, 0
+; CHECK-NEXT: vilvl.b $vr0, $vr0, $vr0
+; CHECK-NEXT: vilvl.h $vr0, $vr0, $vr0
+; CHECK-NEXT: vslli.w $vr0, $vr0, 24
+; CHECK-NEXT: vsrai.w $vr1, $vr0, 24
+; CHECK-NEXT: vslti.w $vr2, $vr1, 0
+; CHECK-NEXT: vilvl.w $vr0, $vr2, $vr1
+; CHECK-NEXT: vffint.d.l $vr0, $vr0
+; CHECK-NEXT: vilvh.w $vr1, $vr2, $vr1
+; CHECK-NEXT: vffint.d.l $vr1, $vr1
; CHECK-NEXT: ret
- %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %shuf = shufflevector <16 x i8> %a, <16 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%cvt = sitofp <4 x i8> %shuf to <4 x double>
ret <4 x double> %cvt
}
@@ -245,27 +182,17 @@ define <4 x double> @sitofp_v4i8_v4f64(<16 x i8> %a) {
define <4 x double> @sitofp_v16i8_v4f64(<16 x i8> %a) {
; CHECK-LABEL: sitofp_v16i8_v4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa2, $a0
-; CHECK-NEXT: ffint.d.w $fa2, $fa2
-; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa3, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
-; CHECK-NEXT: ext.w.b $a0, $a0
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa0
-; CHECK-NEXT: vextrins.d $vr1, $vr3, 16
-; CHECK-NEXT: vori.b $vr0, $vr2, 0
+; CHECK-NEXT: vslti.b $vr1, $vr0, 0
+; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr0
+; CHECK-NEXT: vslti.h $vr1, $vr0, 0
+; CHECK-NEXT: vilvl.h $vr1, $vr1, $vr0
+; CHECK-NEXT: vslti.w $vr2, $vr1, 0
+; CHECK-NEXT: vilvl.w $vr0, $vr2, $vr1
+; CHECK-NEXT: vffint.d.l $vr0, $vr0
+; CHECK-NEXT: vilvh.w $vr1, $vr2, $vr1
+; CHECK-NEXT: vffint.d.l $vr1, $vr1
; CHECK-NEXT: ret
%cvt = sitofp <16 x i8> %a to <16 x double>
- %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %shuf = shufflevector <16 x double> %cvt, <16 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x double> %shuf
}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll
index dc93938834bfb..6d7a1b1554563 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll
@@ -31,17 +31,13 @@ define void @uitofp_v2i64_v2f64(ptr %res, ptr %in){
define <2 x double> @uitofp_v2i8_v2f64(<16 x i8> %a) {
; CHECK-LABEL: uitofp_v2i8_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa0, $fa0
-; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: vrepli.b $vr1, 0
+; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr0
+; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0
+; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr0
+; CHECK-NEXT: vffint.d.lu $vr0, $vr0
; CHECK-NEXT: ret
- %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
+ %shuf = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 0, i32 1>
%cvt = uitofp <2 x i8> %shuf to <2 x double>
ret <2 x double> %cvt
}
@@ -49,45 +45,29 @@ define <2 x double> @uitofp_v2i8_v2f64(<16 x i8> %a) {
define <2 x double> @uitofp_v16i8_v2f64(<16 x i8> %a) {
; CHECK-LABEL: uitofp_v16i8_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa0, $fa0
-; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: vrepli.b $vr1, 0
+; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr0
+; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0
+; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr0
+; CHECK-NEXT: vffint.d.lu $vr0, $vr0
; CHECK-NEXT: ret
%cvt = uitofp <16 x i8> %a to <16 x double>
- %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <2 x i32> <i32 0, i32 1>
+ %shuf = shufflevector <16 x double> %cvt, <16 x double> poison, <2 x i32> <i32 0, i32 1>
ret <2 x double> %shuf
}
define <4 x double> @uitofp_v4i8_v4f64(<16 x i8> %a) {
; CHECK-LABEL: uitofp_v4i8_v4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa2, $a0
-; CHECK-NEXT: ffint.d.w $fa2, $fa2
-; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa3, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa0
-; CHECK-NEXT: vextrins.d $vr1, $vr3, 16
-; CHECK-NEXT: vori.b $vr0, $vr2, 0
+; CHECK-NEXT: vrepli.b $vr1, 0
+; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr0
+; CHECK-NEXT: vilvl.h $vr2, $vr1, $vr0
+; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr2
+; CHECK-NEXT: vffint.d.lu $vr0, $vr0
+; CHECK-NEXT: vilvh.w $vr1, $vr1, $vr2
+; CHECK-NEXT: vffint.d.lu $vr1, $vr1
; CHECK-NEXT: ret
- %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %shuf = shufflevector <16 x i8> %a, <16 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%cvt = uitofp <4 x i8> %shuf to <4 x double>
ret <4 x double> %cvt
}
@@ -95,27 +75,15 @@ define <4 x double> @uitofp_v4i8_v4f64(<16 x i8> %a) {
define <4 x double> @uitofp_v16i8_v4f64(<16 x i8> %a) {
; CHECK-LABEL: uitofp_v16i8_v4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa2, $a0
-; CHECK-NEXT: ffint.d.w $fa2, $fa2
-; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa1, $a0
-; CHECK-NEXT: ffint.d.w $fa3, $fa1
-; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
-; CHECK-NEXT: andi $a0, $a0, 255
-; CHECK-NEXT: movgr2fr.w $fa0, $a0
-; CHECK-NEXT: ffint.d.w $fa1, $fa0
-; CHECK-NEXT: vextrins.d $vr1, $vr3, 16
-; CHECK-NEXT: vori.b $vr0, $vr2, 0
+; CHECK-NEXT: vrepli.b $vr1, 0
+; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr0
+; CHECK-NEXT: vilvl.h $vr2, $vr1, $vr0
+; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr2
+; CHECK-NEXT: vffint.d.lu $vr0, $vr0
+; CHECK-NEXT: vilvh.w $vr1, $vr1, $vr2
+; CHECK-NEXT: vffint.d.lu $vr1, $vr1
; CHECK-NEXT: ret
%cvt = uitofp <16 x i8> %a to <16 x double>
- %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %shuf = shufflevector <16 x double> %cvt, <16 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x double> %shuf
}
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