[llvm] AMDGPU/GlobalISel: Switch to extended LLTs (PR #196522)
via llvm-commits
llvm-commits at lists.llvm.org
Fri May 8 05:53:13 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Petar Avramovic (petar-avramovic)
<details>
<summary>Changes</summary>
Switch is required to be able to translate bfloat.
After the switch most of the codegen patterns now require explicit
type on register to match instead of LLT::scalar.
So we can still use LLT::scalar for type checks but new instructions
created during lowerings/combines need to use propper extended LLT.
inst select test sources fully switched to i32/f32 so patterns can match
for legalizer and regbanklegalize left as is (should probably be switched
as well)
New functionality worth noting is f16 and bitcast lowering to i32
f16 = g_bitcast i16
->
i32 = g_anyext i16
f16 = g_trunc i32
f16 = trunc i32 is legal
---
Patch is 22.33 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/196522.diff
591 Files Affected:
- (modified) llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h (+13-1)
- (modified) llvm/include/llvm/CodeGen/MachineFunction.h (+9-6)
- (modified) llvm/include/llvm/Target/GlobalISel/Combine.td (+5-1)
- (modified) llvm/lib/CodeGen/GlobalISel/CallLowering.cpp (+2-2)
- (modified) llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp (+24-4)
- (modified) llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (+85-28)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp (+18-9)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp (+4-4)
- (modified) llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (+497-428)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp (+113-91)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h (+4)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp (+17-3)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h (+1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (+39-39)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+1)
- (modified) llvm/lib/Target/AMDGPU/CMakeLists.txt (+4-4)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir (+17)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir (+1-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir (+1-2)
- (modified) llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll (+20-16)
- (modified) llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll (+229-182)
- (modified) llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll (+19-15)
- (modified) llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll (+182-141)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-concat-vectors.mir (+11-10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-cse-leaves-dead-cast.mir (+41-40)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir (+20-20)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir (+242-234)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir (+9-9)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll (+4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll (+3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll (+16-16)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll (+16-16)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll (+14-14)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir (+30-30)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll (+26-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll (+66-66)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll (+43-43)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll (+363-275)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f32.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f64.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.v2f16.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll (+59-39)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.mir (+15-15)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll (+4-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll (+176-108)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll (+64-48)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll (+179-159)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll (+1633-1376)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll (+30-22)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll (+615-615)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.v2i65.ll (+9-9)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll (+53-45)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll (+23-22)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll (+48-48)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll (+26-26)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir (+21-21)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir (+20-20)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir (+26-26)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir (+26-26)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir (+66-66)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir (+94-94)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir (+81-81)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir (+42-42)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir (+197-167)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir (+25-21)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir (+18-18)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir (+49-49)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir (+125-125)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-undef.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir (+32-32)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-undef.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir (+121-121)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir (+114-122)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir (+63-63)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir (+86-86)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir (+77-77)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir (+38-38)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir (+16-16)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir (+28-31)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir (+399-366)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus-fake16.mir (+176-148)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus.mir (+176-176)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir (+272-232)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir (+33-36)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir (+18-18)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s64.mir (+11-11)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir (+78-66)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir (+36-30)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir (+50-50)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir (+11-11)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir (+50-50)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir (+11-11)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir (+50-50)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir (+11-11)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir (+50-50)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir (+11-11)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir (+89-89)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir (+22-22)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir (+276-288)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir (+30-30)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir (+35-35)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir (+45-45)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir (+128-128)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir (+16-16)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.s16.mir (+19-19)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir (+99-99)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir (+137-107)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir (+79-61)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir (+195-195)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir (+292-292)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-old-legalization.mir (+315-305)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir (+369-339)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir (+77-53)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir (+111-111)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir (+173-173)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir (+197-167)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir (+25-21)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir (+78-78)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir (+25-25)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir (+21-21)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir (+15-15)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir (+45-45)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir (+40-40)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir (+45-45)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir (+40-40)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir (+27-27)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pseudo-scalar-transcendental.mir (+48-48)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop1.mir (+83-83)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop2.mir (+95-95)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir (+116-116)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir (+34-34)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sextload-local.mir (+15-15)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir (+157-157)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir (+25-21)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir (+22-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax-64.mir (+9-9)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin-64.mir (+9-9)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir (+54-54)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-local.mir (+99-79)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir (+227-227)
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- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir (+9-9)
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- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll (+80-80)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll (+39-39)
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- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-metadata.ll (+4-4)
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- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll (+6-6)
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- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll (+186-186)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll (+744-744)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/known-fpclass-phi.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-abs.mir (+56-56)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir (+100-100)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir (+71-71)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.workitem.id.mir (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir (+61-61)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir (+79-77)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir (+381-378)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir (+578-549)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir (+9-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir (+41-41)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir (+8-7)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir (+171-164)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctls.mir (+36-35)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir (+19-19)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir (+14-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir (+15-15)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-divrem.mir (+13-13)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir (+224-218)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir (+133-133)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir (+51-51)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir (+139-139)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir (+63-63)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir (+121-100)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
index d8d7ccc0bd7a7..a0df1fd4096a0 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
@@ -74,6 +74,9 @@ class LegalizationArtifactCombiner {
if (MRI.getType(DstReg) == MRI.getType(TruncSrc))
replaceRegOrBuildCopy(DstReg, TruncSrc, MRI, Builder, UpdatedDefs,
Observer);
+ else if (MRI.getType(DstReg).getSizeInBits() ==
+ MRI.getType(TruncSrc).getSizeInBits())
+ Builder.buildBitcast(DstReg, TruncSrc);
else
Builder.buildAnyExtOrTrunc(DstReg, TruncSrc);
UpdatedDefs.push_back(DstReg);
@@ -1062,7 +1065,16 @@ class LegalizationArtifactCombiner {
}
MIB.setInstrAndDebugLoc(MI);
- MIB.buildMergeLikeInstr(Dst, ConcatSources);
+ if (ConcatSources.size() == 1) {
+ if (MRI.getType(Dst) == MRI.getType(ConcatSources[0]))
+ replaceRegOrBuildCopy(Dst, ConcatSources[0], MRI, MIB, UpdatedDefs,
+ Observer);
+ else {
+ MIB.buildBitcast(Dst, ConcatSources[0]);
+ UpdatedDefs.push_back(Dst);
+ }
+ } else
+ MIB.buildMergeLikeInstr(Dst, ConcatSources);
DeadInsts.push_back(&MI);
return true;
}
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index d620ae5137eba..5e34eab8c57e7 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -1158,12 +1158,15 @@ class LLVM_ABI MachineFunction {
int64_t Offset, LLT Ty);
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
int64_t Offset, LocationSize Size) {
- return getMachineMemOperand(
- MMO, Offset,
- !Size.isPrecise() ? LLT()
- : Size.isScalable()
- ? LLT::scalable_vector(1, 8 * Size.getValue().getKnownMinValue())
- : LLT::scalar(8 * Size.getValue().getKnownMinValue()));
+ if (!Size.isPrecise())
+ return getMachineMemOperand(MMO, Offset, LLT());
+
+ unsigned SizeInBits = 8 * Size.getValue().getKnownMinValue();
+ LLT Ty = Size.isScalable() ? LLT::scalable_vector(1, SizeInBits)
+ : MMO->getType().isPointerOrPointerVector()
+ ? LLT::scalar(SizeInBits)
+ : MMO->getType().changeElementSize(SizeInBits);
+ return getMachineMemOperand(MMO, Offset, Ty);
}
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
int64_t Offset, uint64_t Size) {
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 2091554304771..383eaf197effe 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -1623,7 +1623,11 @@ def sub_add_reg: GICombineRule <
def bitcast_bitcast_fold : GICombineRule<
(defs root:$dst),
(match (G_BITCAST $dst, $src1):$op, (G_BITCAST $src1, $src0),
- [{ return MRI.getType(${src0}.getReg()) == MRI.getType(${dst}.getReg()); }]),
+ [{ LLT Src0Ty = MRI.getType(${src0}.getReg());
+ LLT DstTy = MRI.getType(${dst}.getReg());
+ return Src0Ty == DstTy &&
+ (!Src0Ty.isScalar() || (Src0Ty.isInteger() == DstTy.isInteger() &&
+ Src0Ty.isFloat() == DstTy.isFloat())); }]),
(apply [{ Helper.replaceSingleDefInstWithReg(*${op}, ${src0}.getReg()); }])>;
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index 16549c1047213..b651801f27bc5 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -421,7 +421,7 @@ void CallLowering::buildCopyFromRegs(MachineIRBuilder &B,
// Sometimes pointers are passed zero extended.
LLT OrigTy = MRI.getType(OrigRegs[0]);
if (OrigTy.isPointer()) {
- LLT IntPtrTy = LLT::scalar(OrigTy.getSizeInBits());
+ LLT IntPtrTy = LLT::integer(OrigTy.getSizeInBits());
B.buildIntToPtr(OrigRegs[0], B.buildTrunc(IntPtrTy, SrcReg));
return;
}
@@ -1338,7 +1338,7 @@ Register CallLowering::ValueHandler::extendRegister(Register ValReg,
if (ValRegTy.isPointer()) {
// The x32 ABI wants to zero extend 32-bit pointers to 64-bit registers, so
// we have to cast to do the extension.
- LLT IntPtrTy = LLT::scalar(ValRegTy.getSizeInBits());
+ LLT IntPtrTy = LLT::integer(ValRegTy.getSizeInBits());
ValReg = MIRBuilder.buildPtrToInt(IntPtrTy, ValReg).getReg(0);
}
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index c58fb84a3890e..35b05c581d956 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -190,9 +190,24 @@ void CombinerHelper::replaceRegWith(MachineRegisterInfo &MRI, Register FromReg,
Register ToReg) const {
Observer.changingAllUsesOfReg(MRI, FromReg);
- if (MRI.constrainRegAttrs(ToReg, FromReg))
+ if (MRI.constrainRegAttrs(ToReg, FromReg)) {
+ // Notify about ToReg's def so CSE re-hashes it after constrainRegAttrs
+ // may have changed its type in MRI.
+ MachineInstr *ToRegDef = ToReg.isVirtual() ? MRI.getUniqueVRegDef(ToReg) : nullptr;
+ if (ToRegDef)
+ Observer.changingInstr(*ToRegDef);
+ // Notify the observer about each use instruction that is about to have its
+ // operand changed, so that CSE info can invalidate and re-hash them.
+ SmallVector<MachineInstr *, 4> UseInstrs;
+ for (MachineOperand &UseMO : MRI.use_nodbg_operands(FromReg))
+ if (!is_contained(UseInstrs, UseMO.getParent()))
+ UseInstrs.push_back(UseMO.getParent());
+ for (MachineInstr *UseMI : UseInstrs)
+ Observer.changingInstr(*UseMI);
MRI.replaceRegWith(FromReg, ToReg);
- else
+ if (ToRegDef)
+ Observer.changedInstr(*ToRegDef);
+ } else
Builder.buildCopy(FromReg, ToReg);
Observer.finishedChangingAllUsesOfReg();
@@ -2360,7 +2375,12 @@ void CombinerHelper::applyCombineUnmergeConstant(
unsigned NumElems = MI.getNumOperands() - 1;
for (unsigned Idx = 0; Idx < NumElems; ++Idx) {
Register DstReg = MI.getOperand(Idx).getReg();
- Builder.buildConstant(DstReg, Csts[Idx]);
+ LLT DstTy = MRI.getType(DstReg);
+ if (DstTy.isFloat())
+ Builder.buildFConstant(DstReg,
+ APFloat(getFltSemanticForLLT(DstTy), Csts[Idx]));
+ else
+ Builder.buildConstant(DstReg, Csts[Idx]);
}
MI.eraseFromParent();
@@ -2496,7 +2516,7 @@ void CombinerHelper::applyCombineShiftToUnmerge(
unsigned HalfSize = Size / 2;
assert(ShiftVal >= HalfSize);
- LLT HalfTy = LLT::scalar(HalfSize);
+ LLT HalfTy = Ty.isInteger() ? LLT::integer(HalfSize) : LLT::scalar(HalfSize);
auto Unmerge = Builder.buildUnmerge(HalfTy, SrcReg);
unsigned NarrowShiftAmt = ShiftVal - HalfSize;
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 71cda8a480dd7..aaefb31345eab 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -1595,7 +1595,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
unsigned LeftoverBits = TotalSize - NumParts * NarrowSize;
SmallVector<Register, 1> LeftoverRegs;
if (LeftoverBits != 0) {
- LeftoverTy = LLT::scalar(LeftoverBits);
+ LeftoverTy = LLT::integer(LeftoverBits);
auto K = MIRBuilder.buildConstant(
LeftoverTy,
Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits));
@@ -2144,7 +2144,9 @@ Register LegalizerHelper::coerceToScalar(Register Val) {
return Val;
const DataLayout &DL = MIRBuilder.getDataLayout();
- LLT NewTy = LLT::scalar(Ty.getSizeInBits());
+ LLT EltTy = Ty.getScalarType();
+ LLT NewTy = EltTy.isFloat() ? EltTy.changeElementSize(Ty.getSizeInBits())
+ : LLT::integer(Ty.getSizeInBits());
if (Ty.isPointer()) {
if (DL.isNonIntegralAddressSpace(Ty.getAddressSpace()))
return Register();
@@ -2292,11 +2294,11 @@ LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
// %10:_(s12) = G_MERGE_VALUES %8, %9
const int GCD = std::gcd(SrcSize, WideSize);
- LLT GCDTy = LLT::scalar(GCD);
+ LLT GCDTy = WideTy.changeElementSize(GCD);
SmallVector<Register, 8> NewMergeRegs;
SmallVector<Register, 8> Unmerges;
- LLT WideDstTy = LLT::scalar(NumMerge * WideSize);
+ LLT WideDstTy = WideTy.changeElementSize(NumMerge * WideSize);
// Decompose the original operands if they don't evenly divide.
for (const MachineOperand &MO : llvm::drop_begin(MI.operands())) {
@@ -2487,7 +2489,7 @@ LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
return UnableToLegalize;
- LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits());
+ LLT SrcAsIntTy = LLT::integer(SrcTy.getSizeInBits());
Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src);
SrcTy = SrcAsIntTy;
}
@@ -2755,6 +2757,38 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
switch (Opcode) {
default:
return UnableToLegalize;
+ case TargetOpcode::G_BITCAST: {
+ if (TypeIdx != 0)
+ return UnableToLegalize;
+ LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
+ if (!SrcTy.isScalar())
+ return UnableToLegalize;
+ LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
+ // If src and dst have the same size, widening both to WideTy produces a
+ // same-type bitcast. Replace with COPY so the widened instruction is valid.
+ if (SrcTy.getSizeInBits() == DstTy.getSizeInBits()) {
+ Observer.changingInstr(MI);
+ MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::COPY));
+ widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
+ widenScalarDst(MI, WideTy, 0);
+ Observer.changedInstr(MI);
+ return Legalized;
+ }
+ // If src and dst would both become WideTy, the bitcast becomes a no-op.
+ // Replace it with G_ANYEXT of the source instead.
+ if (SrcTy.getSizeInBits() == WideTy.getSizeInBits()) {
+ Observer.changingInstr(MI);
+ MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::G_ANYEXT));
+ widenScalarDst(MI, WideTy, 0);
+ Observer.changedInstr(MI);
+ return Legalized;
+ }
+ Observer.changingInstr(MI);
+ widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
+ widenScalarDst(MI, WideTy, 0);
+ Observer.changedInstr(MI);
+ return Legalized;
+ }
case TargetOpcode::G_ATOMICRMW_XCHG:
case TargetOpcode::G_ATOMICRMW_ADD:
case TargetOpcode::G_ATOMICRMW_SUB:
@@ -7359,7 +7393,8 @@ LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
Register SegReg = SrcRegs[i];
if (ExtractOffset != 0 || SegSize != NarrowSize) {
// A genuine extract is needed.
- SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
+ SegReg = MRI.createGenericVirtualRegister(
+ MRI.getType(OpReg).changeElementSize(SegSize));
MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
}
@@ -7437,7 +7472,7 @@ LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
Register SegReg = OpReg;
if (ExtractOffset != 0 || SegSize != OpSize) {
// A genuine extract is needed.
- SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
+ SegReg = MRI.createGenericVirtualRegister(LLT::integer(SegSize));
MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
}
@@ -7449,7 +7484,7 @@ LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
uint64_t WideSize = DstRegs.size() * NarrowSize;
Register DstReg = MI.getOperand(0).getReg();
if (WideSize > RegTy.getSizeInBits()) {
- Register MergeReg = MRI.createGenericVirtualRegister(LLT::scalar(WideSize));
+ Register MergeReg = MRI.createGenericVirtualRegister(LLT::integer(WideSize));
MIRBuilder.buildMergeLikeInstr(MergeReg, DstRegs);
MIRBuilder.buildTrunc(DstReg, MergeReg);
} else
@@ -8242,8 +8277,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerRotate(MachineInstr &MI) {
LegalizerHelper::LegalizeResult
LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
auto [Dst, Src] = MI.getFirst2Regs();
- const LLT S64 = LLT::scalar(64);
- const LLT S32 = LLT::scalar(32);
+ const LLT S64 = LLT::integer(64);
+ const LLT S32 = LLT::integer(32);
const LLT S1 = LLT::scalar(1);
assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32);
@@ -8300,8 +8335,8 @@ LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
LegalizerHelper::LegalizeResult
LegalizerHelper::lowerU64ToF32WithSITOFP(MachineInstr &MI) {
auto [Dst, Src] = MI.getFirst2Regs();
- const LLT S64 = LLT::scalar(64);
- const LLT S32 = LLT::scalar(32);
+ const LLT S64 = LLT::integer(64);
+ const LLT S32 = LLT::integer(32);
const LLT S1 = LLT::scalar(1);
assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32);
@@ -8335,8 +8370,8 @@ LegalizerHelper::lowerU64ToF32WithSITOFP(MachineInstr &MI) {
LegalizerHelper::LegalizeResult
LegalizerHelper::lowerU64ToF64BitFloatOps(MachineInstr &MI) {
auto [Dst, Src] = MI.getFirst2Regs();
- const LLT S64 = LLT::scalar(64);
- const LLT S32 = LLT::scalar(32);
+ const LLT S64 = LLT::integer(64);
+ const LLT S32 = LLT::integer(32);
assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S64);
@@ -8463,8 +8498,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerSITOFP(MachineInstr &MI) {
LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOUI(MachineInstr &MI) {
auto [Dst, DstTy, Src, SrcTy] = MI.getFirst2RegLLTs();
- const LLT S64 = LLT::scalar(64);
- const LLT S32 = LLT::scalar(32);
+ const LLT S64 = LLT::integer(64);
+ const LLT S32 = LLT::integer(32);
if (SrcTy != S64 && SrcTy != S32)
return UnableToLegalize;
@@ -8503,8 +8538,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOUI(MachineInstr &MI) {
LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOSI(MachineInstr &MI) {
auto [Dst, DstTy, Src, SrcTy] = MI.getFirst2RegLLTs();
- const LLT S64 = LLT::scalar(64);
- const LLT S32 = LLT::scalar(32);
+ const LLT S64 = LLT::integer(64);
+ const LLT S32 = LLT::integer(32);
// FIXME: Only f32 to i64 conversions are supported.
if (SrcTy.getScalarType() != S32 || DstTy.getScalarType() != S64)
@@ -8705,7 +8740,7 @@ LegalizerHelper::lowerFPExtAndTruncMem(MachineInstr &MI) {
LegalizerHelper::LegalizeResult
LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
const LLT S1 = LLT::scalar(1);
- const LLT S32 = LLT::scalar(32);
+ const LLT S32 = LLT::integer(32);
auto [Dst, Src] = MI.getFirst2Regs();
assert(MRI.getType(Dst).getScalarType() == LLT::float16() &&
@@ -8716,7 +8751,7 @@ LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
if (MI.getFlag(MachineInstr::FmAfn)) {
unsigned Flags = MI.getFlags();
- auto Src32 = MIRBuilder.buildFPTrunc(S32, Src, Flags);
+ auto Src32 = MIRBuilder.buildFPTrunc(LLT::float32(), Src, Flags);
MIRBuilder.buildFPTrunc(Dst, Src32, Flags);
MI.eraseFromParent();
return Legalized;
@@ -9246,7 +9281,9 @@ LegalizerHelper::lowerMergeValues(MachineInstr &MI) {
auto [DstReg, DstTy, Src0Reg, Src0Ty] = MI.getFirst2RegLLTs();
unsigned PartSize = Src0Ty.getSizeInBits();
- LLT WideTy = LLT::scalar(DstTy.getSizeInBits());
+ LLT WideTy = DstTy.isPointer() ? LLT::scalar(DstTy.getSizeInBits())
+ : DstTy.isScalar() ? DstTy
+ : LLT::integer(DstTy.getSizeInBits());
Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0);
for (unsigned I = 2; I != NumOps; ++I) {
@@ -9272,6 +9309,8 @@ LegalizerHelper::lowerMergeValues(MachineInstr &MI) {
}
MIRBuilder.buildIntToPtr(DstReg, ResultReg);
+ } else if (WideTy != DstTy) {
+ MIRBuilder.buildBitcast(DstReg, ResultReg);
}
MI.eraseFromParent();
@@ -9292,16 +9331,34 @@ LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) {
return UnableToLegalize;
// Expand scalarizing unmerge as bitcast to integer and shift.
- LLT IntTy = MRI.getType(SrcReg);
+ LLT SrcTy = MRI.getType(SrcReg);
+ LLT IntTy = LLT::integer(SrcTy.getSizeInBits());
+ LLT IntDstTy = LLT::integer(DstTy.getSizeInBits());
- MIRBuilder.buildTrunc(Dst0Reg, SrcReg);
+ // Bitcast source to integer if needed (e.g. coerceToScalar on <2 x f16> gives f32).
+ Register IntSrcReg = SrcReg;
+ if (!SrcTy.isInteger())
+ IntSrcReg = MIRBuilder.buildBitcast(IntTy, SrcReg).getReg(0);
const unsigned DstSize = DstTy.getSizeInBits();
+
+ // Build a destination value: truncate integer bits, then bitcast to DstTy if float.
+ auto buildDst = [&](Register Dst, Register Src) {
+ if (!DstTy.isFloat())
+ MIRBuilder.buildTrunc(Dst, Src);
+ else {
+ auto Trunc = MIRBuilder.buildTrunc(IntDstTy, Src);
+ MIRBuilder.buildBitcast(Dst, Trunc);
+ }
+ };
+
+ buildDst(Dst0Reg, IntSrcReg);
+
unsigned Offset = DstSize;
for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) {
auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset);
- auto Shift = MIRBuilder.buildLShr(IntTy, SrcReg, ShiftAmt);
- MIRBuilder.buildTrunc(MI.getOperand(I), Shift);
+ auto Shift = MIRBuilder.buildLShr(IntTy, IntSrcReg, ShiftAmt);
+ buildDst(MI.getOperand(I).getReg(), Shift.getReg(0));
}
MI.eraseFromParent();
@@ -9631,14 +9688,14 @@ LegalizerHelper::lowerExtract(MachineInstr &MI) {
(SrcTy.isVector() && DstTy == SrcTy.getElementType()))) {
LLT SrcIntTy = SrcTy;
if (!SrcTy.isScalar()) {
- SrcIntTy = LLT::scalar(SrcTy.getSizeInBits());
+ SrcIntTy = LLT::integer(SrcTy.getSizeInBits());
SrcReg = MIRBuilder.buildCast(SrcIntTy, SrcReg).getReg(0);
}
Register ResultReg = DstReg;
if (DstTy.isPointer())
ResultReg =
- MRI.createGenericVirtualRegister(LLT::scalar(DstTy.getSizeInBits()));
+ MRI.createGenericVirtualRegister(LLT::integer(DstTy.getSizeInBits()));
if (Offset == 0)
MIRBuilder.buildTrunc(ResultReg, SrcReg);
@@ -10623,7 +10680,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerVAArg(MachineInstr &MI) {
auto VAList = MIRBuilder.buildLoad(PtrTy, ListPtr, *PtrLoadMMO).getReg(0);
const Align A(MI.getOperand(2).getImm());
- LLT PtrTyAsScalarTy = LLT::scalar(PtrTy.getSizeInBits());
+ LLT PtrTyAsScalarTy = LLT::integer(PtrTy.getSizeInBits());
if (A > TLI.getMinStackArgumentAlignment()) {
Register AlignAmt =
MIRBuilder.buildConstant(PtrTyAsScalarTy, A.value() - 1).getReg(0);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index 9ae28a6528dc5..b9b488a5d2d9d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -36,7 +36,7 @@ static Register extendRegisterMin32(CallLowering::ValueHandler &Handler,
if (VA.getLocVT().getSizeInBits() < 32) {
// 16-bit types are reported as legal for 32-bit registers. We need to
// extend and do a 32-bit copy to avoid the verifier complaining about it.
- return Handler.MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0);
+ return Handler.MIRBuilder.buildAnyExt(LLT::integer(32), ValVReg).getReg(0);
}
return Handler.extendRegister(ValVReg, VA);
@@ -73,7 +73,7 @@ struct AMDGPUOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
= static_cast<const SIRegisterInfo *>(MRI.getTargetRegisterInfo());
if (TRI->isSGPRReg(MRI, PhysReg)) {
LLT Ty = MRI.getType(ExtReg);
- LLT S32 = LLT::scalar(32);
+ LLT S32 = LLT::integer(32);
if (Ty != S32) {
// FIXME: We should probably support readfirstlane intrinsics with all
// legal 32-bit types.
@@ -123,7 +123,7 @@ struct AMDGPUIncomingArgHandler : public CallLowering::In...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/196522
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