[llvm] [llvm][RISCV] Optimize fcopysign for fixed vectors (PR #193802)
Brandon Wu via llvm-commits
llvm-commits at lists.llvm.org
Thu May 7 23:52:38 PDT 2026
https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/193802
>From e7c8ba8e5c4b4f84c97061ac6965c6518234a719 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Thu, 23 Apr 2026 23:16:54 +0800
Subject: [PATCH 01/10] pre commit test
---
.../rvv/fixed-vectors-vcopysign-sdnode.ll | 2403 ++++++++++++++++-
1 file changed, 2374 insertions(+), 29 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-sdnode.ll
index 9cfed6a659c64..dcbb653a3b7ea 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-sdnode.ll
@@ -1,56 +1,2401 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfa \
-; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfa \
-; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+experimental-zvfbfa \
+; RUN: -target-abi=ilp32d -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFA,ZVFHMIN32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+experimental-zvfbfa \
+; RUN: -target-abi=lp64d -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFA,ZVFHMIN64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin -target-abi=ilp32d \
+; RUN: -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFHMIN32,ZVFBFMIN32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin -target-abi=lp64d \
+; RUN: -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFHMIN64,ZVFBFMIN64
define <2 x bfloat> @copysign_v2bf16(<2 x bfloat> %vm, <2 x bfloat> %vs) {
-; CHECK-LABEL: copysign_v2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
-; CHECK-NEXT: vfsgnj.vv v8, v8, v9
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: copysign_v2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v9
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: copysign_v2bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v9, v9, a0
+; ZVFBFMIN-NEXT: addi a0, a0, -1
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a0
+; ZVFBFMIN-NEXT: vor.vv v8, v8, v9
+; ZVFBFMIN-NEXT: ret
%r = call <2 x bfloat> @llvm.copysign.v2bf16(<2 x bfloat> %vm, <2 x bfloat> %vs)
ret <2 x bfloat> %r
}
define <4 x bfloat> @copysign_v4bf16(<4 x bfloat> %vm, <4 x bfloat> %vs) {
-; CHECK-LABEL: copysign_v4bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
-; CHECK-NEXT: vfsgnj.vv v8, v8, v9
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: copysign_v4bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v9
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: copysign_v4bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v9, v9, a0
+; ZVFBFMIN-NEXT: addi a0, a0, -1
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a0
+; ZVFBFMIN-NEXT: vor.vv v8, v8, v9
+; ZVFBFMIN-NEXT: ret
%r = call <4 x bfloat> @llvm.copysign.v4bf16(<4 x bfloat> %vm, <4 x bfloat> %vs)
ret <4 x bfloat> %r
}
define <8 x bfloat> @copysign_v8bf16(<8 x bfloat> %vm, <8 x bfloat> %vs) {
-; CHECK-LABEL: copysign_v8bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16alt, m1, ta, ma
-; CHECK-NEXT: vfsgnj.vv v8, v8, v9
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: copysign_v8bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 8, e16alt, m1, ta, ma
+; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v9
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: copysign_v8bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v9, v9, a0
+; ZVFBFMIN-NEXT: addi a0, a0, -1
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a0
+; ZVFBFMIN-NEXT: vor.vv v8, v8, v9
+; ZVFBFMIN-NEXT: ret
%r = call <8 x bfloat> @llvm.copysign.v8bf16(<8 x bfloat> %vm, <8 x bfloat> %vs)
ret <8 x bfloat> %r
}
define <16 x bfloat> @copysign_v16bf16(<16 x bfloat> %vm, <16 x bfloat> %vs) {
-; CHECK-LABEL: copysign_v16bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e16alt, m2, ta, ma
-; CHECK-NEXT: vfsgnj.vv v8, v8, v10
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: copysign_v16bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 16, e16alt, m2, ta, ma
+; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v10
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: copysign_v16bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v10, v10, a0
+; ZVFBFMIN-NEXT: addi a0, a0, -1
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a0
+; ZVFBFMIN-NEXT: vor.vv v8, v8, v10
+; ZVFBFMIN-NEXT: ret
%r = call <16 x bfloat> @llvm.copysign.v16bf16(<16 x bfloat> %vm, <16 x bfloat> %vs)
ret <16 x bfloat> %r
}
define <32 x bfloat> @copysign_v32bf32(<32 x bfloat> %vm, <32 x bfloat> %vs) {
-; CHECK-LABEL: copysign_v32bf32:
+; ZVFBFA-LABEL: copysign_v32bf32:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: li a0, 32
+; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v12
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: copysign_v32bf32:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: li a0, 32
+; ZVFBFMIN-NEXT: lui a1, 8
+; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v12, v12, a1
+; ZVFBFMIN-NEXT: addi a1, a1, -1
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a1
+; ZVFBFMIN-NEXT: vor.vv v8, v8, v12
+; ZVFBFMIN-NEXT: ret
+ %r = call <32 x bfloat> @llvm.copysign.v32bf32(<32 x bfloat> %vm, <32 x bfloat> %vs)
+ ret <32 x bfloat> %r
+}
+
+define <64 x bfloat> @copysign_v64bf16(<64 x bfloat> %vm, <64 x bfloat> %vs) {
+; ZVFBFA-LABEL: copysign_v64bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: li a0, 64
+; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma
+; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v16
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN32-LABEL: copysign_v64bf16:
+; ZVFBFMIN32: # %bb.0:
+; ZVFBFMIN32-NEXT: addi sp, sp, -656
+; ZVFBFMIN32-NEXT: .cfi_def_cfa_offset 656
+; ZVFBFMIN32-NEXT: sw ra, 652(sp) # 4-byte Folded Spill
+; ZVFBFMIN32-NEXT: sw s0, 648(sp) # 4-byte Folded Spill
+; ZVFBFMIN32-NEXT: sw s1, 644(sp) # 4-byte Folded Spill
+; ZVFBFMIN32-NEXT: sw s2, 640(sp) # 4-byte Folded Spill
+; ZVFBFMIN32-NEXT: sw s3, 636(sp) # 4-byte Folded Spill
+; ZVFBFMIN32-NEXT: sw s4, 632(sp) # 4-byte Folded Spill
+; ZVFBFMIN32-NEXT: sw s5, 628(sp) # 4-byte Folded Spill
+; ZVFBFMIN32-NEXT: sw s6, 624(sp) # 4-byte Folded Spill
+; ZVFBFMIN32-NEXT: sw s7, 620(sp) # 4-byte Folded Spill
+; ZVFBFMIN32-NEXT: sw s8, 616(sp) # 4-byte Folded Spill
+; ZVFBFMIN32-NEXT: sw s9, 612(sp) # 4-byte Folded Spill
+; ZVFBFMIN32-NEXT: sw s10, 608(sp) # 4-byte Folded Spill
+; ZVFBFMIN32-NEXT: sw s11, 604(sp) # 4-byte Folded Spill
+; ZVFBFMIN32-NEXT: .cfi_offset ra, -4
+; ZVFBFMIN32-NEXT: .cfi_offset s0, -8
+; ZVFBFMIN32-NEXT: .cfi_offset s1, -12
+; ZVFBFMIN32-NEXT: .cfi_offset s2, -16
+; ZVFBFMIN32-NEXT: .cfi_offset s3, -20
+; ZVFBFMIN32-NEXT: .cfi_offset s4, -24
+; ZVFBFMIN32-NEXT: .cfi_offset s5, -28
+; ZVFBFMIN32-NEXT: .cfi_offset s6, -32
+; ZVFBFMIN32-NEXT: .cfi_offset s7, -36
+; ZVFBFMIN32-NEXT: .cfi_offset s8, -40
+; ZVFBFMIN32-NEXT: .cfi_offset s9, -44
+; ZVFBFMIN32-NEXT: .cfi_offset s10, -48
+; ZVFBFMIN32-NEXT: .cfi_offset s11, -52
+; ZVFBFMIN32-NEXT: addi s0, sp, 656
+; ZVFBFMIN32-NEXT: .cfi_def_cfa s0, 0
+; ZVFBFMIN32-NEXT: csrr a0, vlenb
+; ZVFBFMIN32-NEXT: slli a1, a0, 3
+; ZVFBFMIN32-NEXT: sub a0, a1, a0
+; ZVFBFMIN32-NEXT: sub sp, sp, a0
+; ZVFBFMIN32-NEXT: andi sp, sp, -128
+; ZVFBFMIN32-NEXT: li a0, 64
+; ZVFBFMIN32-NEXT: addi a2, sp, 256
+; ZVFBFMIN32-NEXT: addi a4, sp, 128
+; ZVFBFMIN32-NEXT: lui a1, 8
+; ZVFBFMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFBFMIN32-NEXT: vmv.x.s a3, v16
+; ZVFBFMIN32-NEXT: vslidedown.vi v24, v16, 7
+; ZVFBFMIN32-NEXT: csrr a5, vlenb
+; ZVFBFMIN32-NEXT: slli a6, a5, 2
+; ZVFBFMIN32-NEXT: add a5, a6, a5
+; ZVFBFMIN32-NEXT: add a5, sp, a5
+; ZVFBFMIN32-NEXT: addi a5, a5, 592
+; ZVFBFMIN32-NEXT: vs1r.v v24, (a5) # vscale x 8-byte Folded Spill
+; ZVFBFMIN32-NEXT: vslidedown.vi v24, v16, 6
+; ZVFBFMIN32-NEXT: csrr a5, vlenb
+; ZVFBFMIN32-NEXT: slli a5, a5, 2
+; ZVFBFMIN32-NEXT: add a5, sp, a5
+; ZVFBFMIN32-NEXT: addi a5, a5, 592
+; ZVFBFMIN32-NEXT: vs1r.v v24, (a5) # vscale x 8-byte Folded Spill
+; ZVFBFMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFMIN32-NEXT: vse16.v v16, (a2)
+; ZVFBFMIN32-NEXT: vse16.v v8, (a4)
+; ZVFBFMIN32-NEXT: lhu a4, 382(sp)
+; ZVFBFMIN32-NEXT: lhu a5, 254(sp)
+; ZVFBFMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFBFMIN32-NEXT: vslidedown.vi v10, v16, 5
+; ZVFBFMIN32-NEXT: csrr a2, vlenb
+; ZVFBFMIN32-NEXT: add a2, sp, a2
+; ZVFBFMIN32-NEXT: addi a2, a2, 592
+; ZVFBFMIN32-NEXT: vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
+; ZVFBFMIN32-NEXT: addi a2, a1, -1
+; ZVFBFMIN32-NEXT: and a4, a4, a1
+; ZVFBFMIN32-NEXT: and a5, a5, a2
+; ZVFBFMIN32-NEXT: or a4, a5, a4
+; ZVFBFMIN32-NEXT: sh a4, 510(sp)
+; ZVFBFMIN32-NEXT: lhu a4, 380(sp)
+; ZVFBFMIN32-NEXT: lhu a5, 252(sp)
+; ZVFBFMIN32-NEXT: vslidedown.vi v10, v16, 4
+; ZVFBFMIN32-NEXT: addi a6, sp, 592
+; ZVFBFMIN32-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
+; ZVFBFMIN32-NEXT: vslidedown.vi v10, v16, 3
+; ZVFBFMIN32-NEXT: csrr a6, vlenb
+; ZVFBFMIN32-NEXT: slli a6, a6, 1
+; ZVFBFMIN32-NEXT: mv a7, a6
+; ZVFBFMIN32-NEXT: slli a6, a6, 1
+; ZVFBFMIN32-NEXT: add a6, a6, a7
+; ZVFBFMIN32-NEXT: add a6, sp, a6
+; ZVFBFMIN32-NEXT: addi a6, a6, 592
+; ZVFBFMIN32-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
+; ZVFBFMIN32-NEXT: and a4, a4, a1
+; ZVFBFMIN32-NEXT: and a5, a5, a2
+; ZVFBFMIN32-NEXT: or a4, a5, a4
+; ZVFBFMIN32-NEXT: sh a4, 508(sp)
+; ZVFBFMIN32-NEXT: lhu a4, 378(sp)
+; ZVFBFMIN32-NEXT: lhu a5, 250(sp)
+; ZVFBFMIN32-NEXT: vslidedown.vi v10, v16, 2
+; ZVFBFMIN32-NEXT: csrr a6, vlenb
+; ZVFBFMIN32-NEXT: slli a7, a6, 1
+; ZVFBFMIN32-NEXT: add a6, a7, a6
+; ZVFBFMIN32-NEXT: add a6, sp, a6
+; ZVFBFMIN32-NEXT: addi a6, a6, 592
+; ZVFBFMIN32-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
+; ZVFBFMIN32-NEXT: vslidedown.vi v10, v16, 1
+; ZVFBFMIN32-NEXT: csrr a6, vlenb
+; ZVFBFMIN32-NEXT: slli a6, a6, 1
+; ZVFBFMIN32-NEXT: add a6, sp, a6
+; ZVFBFMIN32-NEXT: addi a6, a6, 592
+; ZVFBFMIN32-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
+; ZVFBFMIN32-NEXT: and a4, a4, a1
+; ZVFBFMIN32-NEXT: and a5, a5, a2
+; ZVFBFMIN32-NEXT: or a4, a5, a4
+; ZVFBFMIN32-NEXT: sh a4, 506(sp)
+; ZVFBFMIN32-NEXT: lhu a4, 376(sp)
+; ZVFBFMIN32-NEXT: lhu a5, 248(sp)
+; ZVFBFMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFBFMIN32-NEXT: vslidedown.vi v26, v16, 15
+; ZVFBFMIN32-NEXT: vslidedown.vi v28, v16, 14
+; ZVFBFMIN32-NEXT: and a4, a4, a1
+; ZVFBFMIN32-NEXT: and a5, a5, a2
+; ZVFBFMIN32-NEXT: or a4, a5, a4
+; ZVFBFMIN32-NEXT: sh a4, 504(sp)
+; ZVFBFMIN32-NEXT: lhu a4, 374(sp)
+; ZVFBFMIN32-NEXT: lhu a5, 246(sp)
+; ZVFBFMIN32-NEXT: vslidedown.vi v30, v16, 13
+; ZVFBFMIN32-NEXT: vslidedown.vi v6, v16, 12
+; ZVFBFMIN32-NEXT: and a4, a4, a1
+; ZVFBFMIN32-NEXT: and a5, a5, a2
+; ZVFBFMIN32-NEXT: or a4, a5, a4
+; ZVFBFMIN32-NEXT: sh a4, 502(sp)
+; ZVFBFMIN32-NEXT: lhu a4, 372(sp)
+; ZVFBFMIN32-NEXT: lhu a5, 244(sp)
+; ZVFBFMIN32-NEXT: vslidedown.vi v20, v16, 11
+; ZVFBFMIN32-NEXT: vslidedown.vi v18, v16, 10
+; ZVFBFMIN32-NEXT: vslidedown.vi v2, v16, 9
+; ZVFBFMIN32-NEXT: vslidedown.vi v0, v16, 8
+; ZVFBFMIN32-NEXT: and a4, a4, a1
+; ZVFBFMIN32-NEXT: and a5, a5, a2
+; ZVFBFMIN32-NEXT: or a4, a5, a4
+; ZVFBFMIN32-NEXT: sh a4, 500(sp)
+; ZVFBFMIN32-NEXT: lhu a4, 370(sp)
+; ZVFBFMIN32-NEXT: lhu a5, 242(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s t3, v8
+; ZVFBFMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFBFMIN32-NEXT: vslidedown.vi v7, v8, 7
+; ZVFBFMIN32-NEXT: and a4, a4, a1
+; ZVFBFMIN32-NEXT: and a5, a5, a2
+; ZVFBFMIN32-NEXT: or a4, a5, a4
+; ZVFBFMIN32-NEXT: sh a4, 498(sp)
+; ZVFBFMIN32-NEXT: lhu a4, 368(sp)
+; ZVFBFMIN32-NEXT: lhu a5, 240(sp)
+; ZVFBFMIN32-NEXT: vslidedown.vi v3, v8, 6
+; ZVFBFMIN32-NEXT: vslidedown.vi v27, v8, 5
+; ZVFBFMIN32-NEXT: vslidedown.vi v21, v8, 4
+; ZVFBFMIN32-NEXT: vslidedown.vi v19, v8, 3
+; ZVFBFMIN32-NEXT: vslidedown.vi v31, v8, 2
+; ZVFBFMIN32-NEXT: vslidedown.vi v29, v8, 1
+; ZVFBFMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFBFMIN32-NEXT: vslidedown.vi v10, v8, 15
+; ZVFBFMIN32-NEXT: vslidedown.vi v12, v8, 14
+; ZVFBFMIN32-NEXT: vslidedown.vi v14, v8, 13
+; ZVFBFMIN32-NEXT: vslidedown.vi v24, v8, 12
+; ZVFBFMIN32-NEXT: vslidedown.vi v22, v8, 11
+; ZVFBFMIN32-NEXT: vslidedown.vi v16, v8, 10
+; ZVFBFMIN32-NEXT: vslidedown.vi v4, v8, 9
+; ZVFBFMIN32-NEXT: vslidedown.vi v8, v8, 8
+; ZVFBFMIN32-NEXT: and a4, a4, a1
+; ZVFBFMIN32-NEXT: and a5, a5, a2
+; ZVFBFMIN32-NEXT: or a4, a5, a4
+; ZVFBFMIN32-NEXT: sh a4, 496(sp)
+; ZVFBFMIN32-NEXT: lhu a4, 366(sp)
+; ZVFBFMIN32-NEXT: lhu a5, 238(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s t1, v26
+; ZVFBFMIN32-NEXT: vmv.x.s t2, v10
+; ZVFBFMIN32-NEXT: and a4, a4, a1
+; ZVFBFMIN32-NEXT: and a5, a5, a2
+; ZVFBFMIN32-NEXT: or a4, a5, a4
+; ZVFBFMIN32-NEXT: sh a4, 494(sp)
+; ZVFBFMIN32-NEXT: lhu a4, 364(sp)
+; ZVFBFMIN32-NEXT: lhu a5, 236(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s t0, v28
+; ZVFBFMIN32-NEXT: vmv.x.s a7, v12
+; ZVFBFMIN32-NEXT: and a4, a4, a1
+; ZVFBFMIN32-NEXT: and a5, a5, a2
+; ZVFBFMIN32-NEXT: or a4, a5, a4
+; ZVFBFMIN32-NEXT: sh a4, 492(sp)
+; ZVFBFMIN32-NEXT: lhu a4, 362(sp)
+; ZVFBFMIN32-NEXT: lhu t4, 234(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s a6, v30
+; ZVFBFMIN32-NEXT: vmv.x.s a5, v14
+; ZVFBFMIN32-NEXT: and a4, a4, a1
+; ZVFBFMIN32-NEXT: and t4, t4, a2
+; ZVFBFMIN32-NEXT: or a4, t4, a4
+; ZVFBFMIN32-NEXT: sh a4, 490(sp)
+; ZVFBFMIN32-NEXT: lhu t4, 360(sp)
+; ZVFBFMIN32-NEXT: lhu t5, 232(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s a4, v6
+; ZVFBFMIN32-NEXT: csrr t6, vlenb
+; ZVFBFMIN32-NEXT: slli s1, t6, 2
+; ZVFBFMIN32-NEXT: add t6, s1, t6
+; ZVFBFMIN32-NEXT: add t6, sp, t6
+; ZVFBFMIN32-NEXT: lh s6, 592(t6) # 8-byte Folded Reload
+; ZVFBFMIN32-NEXT: and t4, t4, a1
+; ZVFBFMIN32-NEXT: and t5, t5, a2
+; ZVFBFMIN32-NEXT: or t4, t5, t4
+; ZVFBFMIN32-NEXT: sh t4, 488(sp)
+; ZVFBFMIN32-NEXT: lhu t5, 358(sp)
+; ZVFBFMIN32-NEXT: lhu t6, 230(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s s7, v7
+; ZVFBFMIN32-NEXT: csrr t4, vlenb
+; ZVFBFMIN32-NEXT: slli t4, t4, 2
+; ZVFBFMIN32-NEXT: add t4, sp, t4
+; ZVFBFMIN32-NEXT: lh t4, 592(t4) # 8-byte Folded Reload
+; ZVFBFMIN32-NEXT: and t5, t5, a1
+; ZVFBFMIN32-NEXT: and t6, t6, a2
+; ZVFBFMIN32-NEXT: or t5, t6, t5
+; ZVFBFMIN32-NEXT: sh t5, 486(sp)
+; ZVFBFMIN32-NEXT: lhu t5, 356(sp)
+; ZVFBFMIN32-NEXT: lhu s1, 228(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s s4, v3
+; ZVFBFMIN32-NEXT: csrr t6, vlenb
+; ZVFBFMIN32-NEXT: add t6, sp, t6
+; ZVFBFMIN32-NEXT: lh t6, 592(t6) # 8-byte Folded Reload
+; ZVFBFMIN32-NEXT: and t5, t5, a1
+; ZVFBFMIN32-NEXT: and s1, s1, a2
+; ZVFBFMIN32-NEXT: or t5, s1, t5
+; ZVFBFMIN32-NEXT: sh t5, 484(sp)
+; ZVFBFMIN32-NEXT: lhu s2, 354(sp)
+; ZVFBFMIN32-NEXT: lhu s3, 226(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s s1, v27
+; ZVFBFMIN32-NEXT: lh t5, 592(sp) # 8-byte Folded Reload
+; ZVFBFMIN32-NEXT: and s2, s2, a1
+; ZVFBFMIN32-NEXT: and s3, s3, a2
+; ZVFBFMIN32-NEXT: or s2, s3, s2
+; ZVFBFMIN32-NEXT: sh s2, 482(sp)
+; ZVFBFMIN32-NEXT: lhu s2, 352(sp)
+; ZVFBFMIN32-NEXT: lhu s3, 224(sp)
+; ZVFBFMIN32-NEXT: and a3, a3, a1
+; ZVFBFMIN32-NEXT: and t3, t3, a2
+; ZVFBFMIN32-NEXT: and s2, s2, a1
+; ZVFBFMIN32-NEXT: and s3, s3, a2
+; ZVFBFMIN32-NEXT: or s2, s3, s2
+; ZVFBFMIN32-NEXT: sh s2, 480(sp)
+; ZVFBFMIN32-NEXT: lhu s2, 350(sp)
+; ZVFBFMIN32-NEXT: lhu s3, 222(sp)
+; ZVFBFMIN32-NEXT: or a3, t3, a3
+; ZVFBFMIN32-NEXT: sh a3, 384(sp)
+; ZVFBFMIN32-NEXT: and a3, s2, a1
+; ZVFBFMIN32-NEXT: and t3, s3, a2
+; ZVFBFMIN32-NEXT: or a3, t3, a3
+; ZVFBFMIN32-NEXT: sh a3, 478(sp)
+; ZVFBFMIN32-NEXT: lhu a3, 348(sp)
+; ZVFBFMIN32-NEXT: lhu t3, 220(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s s10, v21
+; ZVFBFMIN32-NEXT: csrr s2, vlenb
+; ZVFBFMIN32-NEXT: slli s2, s2, 1
+; ZVFBFMIN32-NEXT: mv s3, s2
+; ZVFBFMIN32-NEXT: slli s2, s2, 1
+; ZVFBFMIN32-NEXT: add s2, s2, s3
+; ZVFBFMIN32-NEXT: add s2, sp, s2
+; ZVFBFMIN32-NEXT: lh s8, 592(s2) # 8-byte Folded Reload
+; ZVFBFMIN32-NEXT: and a3, a3, a1
+; ZVFBFMIN32-NEXT: and t3, t3, a2
+; ZVFBFMIN32-NEXT: or a3, t3, a3
+; ZVFBFMIN32-NEXT: sh a3, 476(sp)
+; ZVFBFMIN32-NEXT: lhu a3, 346(sp)
+; ZVFBFMIN32-NEXT: lhu t3, 218(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s s9, v19
+; ZVFBFMIN32-NEXT: csrr s2, vlenb
+; ZVFBFMIN32-NEXT: slli s3, s2, 1
+; ZVFBFMIN32-NEXT: add s2, s3, s2
+; ZVFBFMIN32-NEXT: add s2, sp, s2
+; ZVFBFMIN32-NEXT: lh s3, 592(s2) # 8-byte Folded Reload
+; ZVFBFMIN32-NEXT: and a3, a3, a1
+; ZVFBFMIN32-NEXT: and t3, t3, a2
+; ZVFBFMIN32-NEXT: or a3, t3, a3
+; ZVFBFMIN32-NEXT: sh a3, 474(sp)
+; ZVFBFMIN32-NEXT: lhu t3, 344(sp)
+; ZVFBFMIN32-NEXT: lhu s2, 216(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s s5, v31
+; ZVFBFMIN32-NEXT: csrr a3, vlenb
+; ZVFBFMIN32-NEXT: slli a3, a3, 1
+; ZVFBFMIN32-NEXT: add a3, sp, a3
+; ZVFBFMIN32-NEXT: lh a3, 592(a3) # 8-byte Folded Reload
+; ZVFBFMIN32-NEXT: and t3, t3, a1
+; ZVFBFMIN32-NEXT: and s2, s2, a2
+; ZVFBFMIN32-NEXT: or t3, s2, t3
+; ZVFBFMIN32-NEXT: sh t3, 472(sp)
+; ZVFBFMIN32-NEXT: lhu t3, 342(sp)
+; ZVFBFMIN32-NEXT: lhu s11, 214(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s s2, v29
+; ZVFBFMIN32-NEXT: and s6, s6, a1
+; ZVFBFMIN32-NEXT: and t3, t3, a1
+; ZVFBFMIN32-NEXT: and s11, s11, a2
+; ZVFBFMIN32-NEXT: or t3, s11, t3
+; ZVFBFMIN32-NEXT: sh t3, 470(sp)
+; ZVFBFMIN32-NEXT: lhu s11, 340(sp)
+; ZVFBFMIN32-NEXT: lhu ra, 212(sp)
+; ZVFBFMIN32-NEXT: and t3, s7, a2
+; ZVFBFMIN32-NEXT: or t3, t3, s6
+; ZVFBFMIN32-NEXT: and s6, s11, a1
+; ZVFBFMIN32-NEXT: and s7, ra, a2
+; ZVFBFMIN32-NEXT: or s6, s7, s6
+; ZVFBFMIN32-NEXT: sh s6, 468(sp)
+; ZVFBFMIN32-NEXT: lhu s6, 338(sp)
+; ZVFBFMIN32-NEXT: lhu s7, 210(sp)
+; ZVFBFMIN32-NEXT: and t4, t4, a1
+; ZVFBFMIN32-NEXT: and s4, s4, a2
+; ZVFBFMIN32-NEXT: and s6, s6, a1
+; ZVFBFMIN32-NEXT: and s7, s7, a2
+; ZVFBFMIN32-NEXT: or s6, s7, s6
+; ZVFBFMIN32-NEXT: sh s6, 466(sp)
+; ZVFBFMIN32-NEXT: lhu s6, 336(sp)
+; ZVFBFMIN32-NEXT: lhu s7, 208(sp)
+; ZVFBFMIN32-NEXT: or t4, s4, t4
+; ZVFBFMIN32-NEXT: and t6, t6, a1
+; ZVFBFMIN32-NEXT: and s4, s6, a1
+; ZVFBFMIN32-NEXT: and s6, s7, a2
+; ZVFBFMIN32-NEXT: or s4, s6, s4
+; ZVFBFMIN32-NEXT: sh s4, 464(sp)
+; ZVFBFMIN32-NEXT: lhu s4, 334(sp)
+; ZVFBFMIN32-NEXT: lhu s6, 206(sp)
+; ZVFBFMIN32-NEXT: and s1, s1, a2
+; ZVFBFMIN32-NEXT: or t6, s1, t6
+; ZVFBFMIN32-NEXT: and s1, s4, a1
+; ZVFBFMIN32-NEXT: and s4, s6, a2
+; ZVFBFMIN32-NEXT: or s1, s4, s1
+; ZVFBFMIN32-NEXT: sh s1, 462(sp)
+; ZVFBFMIN32-NEXT: lhu s1, 332(sp)
+; ZVFBFMIN32-NEXT: lhu s4, 204(sp)
+; ZVFBFMIN32-NEXT: and t5, t5, a1
+; ZVFBFMIN32-NEXT: and s6, s10, a2
+; ZVFBFMIN32-NEXT: and s1, s1, a1
+; ZVFBFMIN32-NEXT: and s4, s4, a2
+; ZVFBFMIN32-NEXT: or s1, s4, s1
+; ZVFBFMIN32-NEXT: sh s1, 460(sp)
+; ZVFBFMIN32-NEXT: lhu s1, 330(sp)
+; ZVFBFMIN32-NEXT: lhu s4, 202(sp)
+; ZVFBFMIN32-NEXT: or t5, s6, t5
+; ZVFBFMIN32-NEXT: and s6, s8, a1
+; ZVFBFMIN32-NEXT: and s1, s1, a1
+; ZVFBFMIN32-NEXT: and s4, s4, a2
+; ZVFBFMIN32-NEXT: or s1, s4, s1
+; ZVFBFMIN32-NEXT: sh s1, 458(sp)
+; ZVFBFMIN32-NEXT: lhu s1, 328(sp)
+; ZVFBFMIN32-NEXT: lhu s4, 200(sp)
+; ZVFBFMIN32-NEXT: and s7, s9, a2
+; ZVFBFMIN32-NEXT: or s6, s7, s6
+; ZVFBFMIN32-NEXT: and s1, s1, a1
+; ZVFBFMIN32-NEXT: and s4, s4, a2
+; ZVFBFMIN32-NEXT: or s1, s4, s1
+; ZVFBFMIN32-NEXT: sh s1, 456(sp)
+; ZVFBFMIN32-NEXT: lhu s1, 326(sp)
+; ZVFBFMIN32-NEXT: lhu s4, 198(sp)
+; ZVFBFMIN32-NEXT: and s3, s3, a1
+; ZVFBFMIN32-NEXT: and s5, s5, a2
+; ZVFBFMIN32-NEXT: and s1, s1, a1
+; ZVFBFMIN32-NEXT: and s4, s4, a2
+; ZVFBFMIN32-NEXT: or s1, s4, s1
+; ZVFBFMIN32-NEXT: sh s1, 454(sp)
+; ZVFBFMIN32-NEXT: lhu s1, 324(sp)
+; ZVFBFMIN32-NEXT: lhu s4, 196(sp)
+; ZVFBFMIN32-NEXT: or s3, s5, s3
+; ZVFBFMIN32-NEXT: and a3, a3, a1
+; ZVFBFMIN32-NEXT: and s1, s1, a1
+; ZVFBFMIN32-NEXT: and s4, s4, a2
+; ZVFBFMIN32-NEXT: or s1, s4, s1
+; ZVFBFMIN32-NEXT: sh s1, 452(sp)
+; ZVFBFMIN32-NEXT: lhu s1, 322(sp)
+; ZVFBFMIN32-NEXT: lhu s4, 194(sp)
+; ZVFBFMIN32-NEXT: and s2, s2, a2
+; ZVFBFMIN32-NEXT: or s2, s2, a3
+; ZVFBFMIN32-NEXT: and s1, s1, a1
+; ZVFBFMIN32-NEXT: and a3, s4, a2
+; ZVFBFMIN32-NEXT: or a3, a3, s1
+; ZVFBFMIN32-NEXT: sh a3, 450(sp)
+; ZVFBFMIN32-NEXT: lhu a3, 320(sp)
+; ZVFBFMIN32-NEXT: lhu s1, 192(sp)
+; ZVFBFMIN32-NEXT: and t1, t1, a1
+; ZVFBFMIN32-NEXT: and t2, t2, a2
+; ZVFBFMIN32-NEXT: and a3, a3, a1
+; ZVFBFMIN32-NEXT: and s1, s1, a2
+; ZVFBFMIN32-NEXT: or a3, s1, a3
+; ZVFBFMIN32-NEXT: sh a3, 448(sp)
+; ZVFBFMIN32-NEXT: lhu s1, 318(sp)
+; ZVFBFMIN32-NEXT: lhu s4, 190(sp)
+; ZVFBFMIN32-NEXT: or a3, t2, t1
+; ZVFBFMIN32-NEXT: vmv.x.s t2, v24
+; ZVFBFMIN32-NEXT: and s1, s1, a1
+; ZVFBFMIN32-NEXT: and t1, s4, a2
+; ZVFBFMIN32-NEXT: or t1, t1, s1
+; ZVFBFMIN32-NEXT: sh t1, 446(sp)
+; ZVFBFMIN32-NEXT: lhu t1, 316(sp)
+; ZVFBFMIN32-NEXT: lhu s1, 188(sp)
+; ZVFBFMIN32-NEXT: sh s2, 386(sp)
+; ZVFBFMIN32-NEXT: sh s3, 388(sp)
+; ZVFBFMIN32-NEXT: sh s6, 390(sp)
+; ZVFBFMIN32-NEXT: sh t5, 392(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s t5, v20
+; ZVFBFMIN32-NEXT: and t1, t1, a1
+; ZVFBFMIN32-NEXT: and s1, s1, a2
+; ZVFBFMIN32-NEXT: or s1, s1, t1
+; ZVFBFMIN32-NEXT: vmv.x.s t1, v22
+; ZVFBFMIN32-NEXT: and t0, t0, a1
+; ZVFBFMIN32-NEXT: sh t6, 394(sp)
+; ZVFBFMIN32-NEXT: sh t4, 396(sp)
+; ZVFBFMIN32-NEXT: sh t3, 398(sp)
+; ZVFBFMIN32-NEXT: sh s1, 444(sp)
+; ZVFBFMIN32-NEXT: lhu t3, 314(sp)
+; ZVFBFMIN32-NEXT: lhu t4, 186(sp)
+; ZVFBFMIN32-NEXT: and a7, a7, a2
+; ZVFBFMIN32-NEXT: or a7, a7, t0
+; ZVFBFMIN32-NEXT: and t0, t3, a1
+; ZVFBFMIN32-NEXT: and t3, t4, a2
+; ZVFBFMIN32-NEXT: or t0, t3, t0
+; ZVFBFMIN32-NEXT: sh t0, 442(sp)
+; ZVFBFMIN32-NEXT: lhu t0, 312(sp)
+; ZVFBFMIN32-NEXT: lhu t3, 184(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s t4, v18
+; ZVFBFMIN32-NEXT: and a6, a6, a1
+; ZVFBFMIN32-NEXT: and t0, t0, a1
+; ZVFBFMIN32-NEXT: and t3, t3, a2
+; ZVFBFMIN32-NEXT: or t0, t3, t0
+; ZVFBFMIN32-NEXT: sh t0, 440(sp)
+; ZVFBFMIN32-NEXT: lhu t0, 310(sp)
+; ZVFBFMIN32-NEXT: lhu t3, 182(sp)
+; ZVFBFMIN32-NEXT: and a5, a5, a2
+; ZVFBFMIN32-NEXT: or a5, a5, a6
+; ZVFBFMIN32-NEXT: and a6, t0, a1
+; ZVFBFMIN32-NEXT: and t0, t3, a2
+; ZVFBFMIN32-NEXT: or a6, t0, a6
+; ZVFBFMIN32-NEXT: sh a6, 438(sp)
+; ZVFBFMIN32-NEXT: lhu a6, 308(sp)
+; ZVFBFMIN32-NEXT: lhu t0, 180(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s t3, v16
+; ZVFBFMIN32-NEXT: and a4, a4, a1
+; ZVFBFMIN32-NEXT: and a6, a6, a1
+; ZVFBFMIN32-NEXT: and t0, t0, a2
+; ZVFBFMIN32-NEXT: or a6, t0, a6
+; ZVFBFMIN32-NEXT: sh a6, 436(sp)
+; ZVFBFMIN32-NEXT: lhu a6, 306(sp)
+; ZVFBFMIN32-NEXT: lhu t0, 178(sp)
+; ZVFBFMIN32-NEXT: and t2, t2, a2
+; ZVFBFMIN32-NEXT: or a4, t2, a4
+; ZVFBFMIN32-NEXT: and a6, a6, a1
+; ZVFBFMIN32-NEXT: and t0, t0, a2
+; ZVFBFMIN32-NEXT: or a6, t0, a6
+; ZVFBFMIN32-NEXT: sh a6, 434(sp)
+; ZVFBFMIN32-NEXT: lhu a6, 304(sp)
+; ZVFBFMIN32-NEXT: lhu t0, 176(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s t2, v2
+; ZVFBFMIN32-NEXT: and t5, t5, a1
+; ZVFBFMIN32-NEXT: and a6, a6, a1
+; ZVFBFMIN32-NEXT: and t0, t0, a2
+; ZVFBFMIN32-NEXT: or a6, t0, a6
+; ZVFBFMIN32-NEXT: sh a6, 432(sp)
+; ZVFBFMIN32-NEXT: lhu t0, 302(sp)
+; ZVFBFMIN32-NEXT: lhu t6, 174(sp)
+; ZVFBFMIN32-NEXT: and a6, t1, a2
+; ZVFBFMIN32-NEXT: or a6, a6, t5
+; ZVFBFMIN32-NEXT: and t0, t0, a1
+; ZVFBFMIN32-NEXT: and t1, t6, a2
+; ZVFBFMIN32-NEXT: or t0, t1, t0
+; ZVFBFMIN32-NEXT: sh t0, 430(sp)
+; ZVFBFMIN32-NEXT: lhu t0, 300(sp)
+; ZVFBFMIN32-NEXT: lhu t1, 172(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s t5, v4
+; ZVFBFMIN32-NEXT: and t4, t4, a1
+; ZVFBFMIN32-NEXT: and t0, t0, a1
+; ZVFBFMIN32-NEXT: and t1, t1, a2
+; ZVFBFMIN32-NEXT: or t0, t1, t0
+; ZVFBFMIN32-NEXT: sh t0, 428(sp)
+; ZVFBFMIN32-NEXT: lhu t0, 298(sp)
+; ZVFBFMIN32-NEXT: lhu t1, 170(sp)
+; ZVFBFMIN32-NEXT: and t3, t3, a2
+; ZVFBFMIN32-NEXT: or t3, t3, t4
+; ZVFBFMIN32-NEXT: and t0, t0, a1
+; ZVFBFMIN32-NEXT: and t1, t1, a2
+; ZVFBFMIN32-NEXT: or t0, t1, t0
+; ZVFBFMIN32-NEXT: sh t0, 426(sp)
+; ZVFBFMIN32-NEXT: lhu t0, 296(sp)
+; ZVFBFMIN32-NEXT: lhu t1, 168(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s t4, v0
+; ZVFBFMIN32-NEXT: and t2, t2, a1
+; ZVFBFMIN32-NEXT: and t0, t0, a1
+; ZVFBFMIN32-NEXT: and t1, t1, a2
+; ZVFBFMIN32-NEXT: or t0, t1, t0
+; ZVFBFMIN32-NEXT: sh t0, 424(sp)
+; ZVFBFMIN32-NEXT: lhu t0, 294(sp)
+; ZVFBFMIN32-NEXT: lhu t1, 166(sp)
+; ZVFBFMIN32-NEXT: and t5, t5, a2
+; ZVFBFMIN32-NEXT: or t2, t5, t2
+; ZVFBFMIN32-NEXT: and t0, t0, a1
+; ZVFBFMIN32-NEXT: and t1, t1, a2
+; ZVFBFMIN32-NEXT: or t0, t1, t0
+; ZVFBFMIN32-NEXT: sh t0, 422(sp)
+; ZVFBFMIN32-NEXT: lhu t0, 292(sp)
+; ZVFBFMIN32-NEXT: lhu t1, 164(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s t5, v8
+; ZVFBFMIN32-NEXT: and t4, t4, a1
+; ZVFBFMIN32-NEXT: and t0, t0, a1
+; ZVFBFMIN32-NEXT: and t1, t1, a2
+; ZVFBFMIN32-NEXT: or t0, t1, t0
+; ZVFBFMIN32-NEXT: sh t0, 420(sp)
+; ZVFBFMIN32-NEXT: lhu t0, 290(sp)
+; ZVFBFMIN32-NEXT: lhu t1, 162(sp)
+; ZVFBFMIN32-NEXT: and t5, t5, a2
+; ZVFBFMIN32-NEXT: or t4, t5, t4
+; ZVFBFMIN32-NEXT: and t0, t0, a1
+; ZVFBFMIN32-NEXT: and t1, t1, a2
+; ZVFBFMIN32-NEXT: or t0, t1, t0
+; ZVFBFMIN32-NEXT: sh t0, 418(sp)
+; ZVFBFMIN32-NEXT: lhu t0, 288(sp)
+; ZVFBFMIN32-NEXT: lhu t1, 160(sp)
+; ZVFBFMIN32-NEXT: sh a4, 408(sp)
+; ZVFBFMIN32-NEXT: sh a5, 410(sp)
+; ZVFBFMIN32-NEXT: sh a7, 412(sp)
+; ZVFBFMIN32-NEXT: sh a3, 414(sp)
+; ZVFBFMIN32-NEXT: sh t4, 400(sp)
+; ZVFBFMIN32-NEXT: sh t2, 402(sp)
+; ZVFBFMIN32-NEXT: sh t3, 404(sp)
+; ZVFBFMIN32-NEXT: sh a6, 406(sp)
+; ZVFBFMIN32-NEXT: and a1, t0, a1
+; ZVFBFMIN32-NEXT: and a2, t1, a2
+; ZVFBFMIN32-NEXT: or a1, a2, a1
+; ZVFBFMIN32-NEXT: sh a1, 416(sp)
+; ZVFBFMIN32-NEXT: addi a1, sp, 384
+; ZVFBFMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFMIN32-NEXT: vle16.v v8, (a1)
+; ZVFBFMIN32-NEXT: addi sp, s0, -656
+; ZVFBFMIN32-NEXT: .cfi_def_cfa sp, 656
+; ZVFBFMIN32-NEXT: lw ra, 652(sp) # 4-byte Folded Reload
+; ZVFBFMIN32-NEXT: lw s0, 648(sp) # 4-byte Folded Reload
+; ZVFBFMIN32-NEXT: lw s1, 644(sp) # 4-byte Folded Reload
+; ZVFBFMIN32-NEXT: lw s2, 640(sp) # 4-byte Folded Reload
+; ZVFBFMIN32-NEXT: lw s3, 636(sp) # 4-byte Folded Reload
+; ZVFBFMIN32-NEXT: lw s4, 632(sp) # 4-byte Folded Reload
+; ZVFBFMIN32-NEXT: lw s5, 628(sp) # 4-byte Folded Reload
+; ZVFBFMIN32-NEXT: lw s6, 624(sp) # 4-byte Folded Reload
+; ZVFBFMIN32-NEXT: lw s7, 620(sp) # 4-byte Folded Reload
+; ZVFBFMIN32-NEXT: lw s8, 616(sp) # 4-byte Folded Reload
+; ZVFBFMIN32-NEXT: lw s9, 612(sp) # 4-byte Folded Reload
+; ZVFBFMIN32-NEXT: lw s10, 608(sp) # 4-byte Folded Reload
+; ZVFBFMIN32-NEXT: lw s11, 604(sp) # 4-byte Folded Reload
+; ZVFBFMIN32-NEXT: .cfi_restore ra
+; ZVFBFMIN32-NEXT: .cfi_restore s0
+; ZVFBFMIN32-NEXT: .cfi_restore s1
+; ZVFBFMIN32-NEXT: .cfi_restore s2
+; ZVFBFMIN32-NEXT: .cfi_restore s3
+; ZVFBFMIN32-NEXT: .cfi_restore s4
+; ZVFBFMIN32-NEXT: .cfi_restore s5
+; ZVFBFMIN32-NEXT: .cfi_restore s6
+; ZVFBFMIN32-NEXT: .cfi_restore s7
+; ZVFBFMIN32-NEXT: .cfi_restore s8
+; ZVFBFMIN32-NEXT: .cfi_restore s9
+; ZVFBFMIN32-NEXT: .cfi_restore s10
+; ZVFBFMIN32-NEXT: .cfi_restore s11
+; ZVFBFMIN32-NEXT: addi sp, sp, 656
+; ZVFBFMIN32-NEXT: .cfi_def_cfa_offset 0
+; ZVFBFMIN32-NEXT: ret
+;
+; ZVFBFMIN64-LABEL: copysign_v64bf16:
+; ZVFBFMIN64: # %bb.0:
+; ZVFBFMIN64-NEXT: addi sp, sp, -656
+; ZVFBFMIN64-NEXT: .cfi_def_cfa_offset 656
+; ZVFBFMIN64-NEXT: sd ra, 648(sp) # 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: sd s0, 640(sp) # 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: sd s1, 632(sp) # 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: sd s2, 624(sp) # 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: sd s3, 616(sp) # 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: sd s4, 608(sp) # 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: sd s5, 600(sp) # 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: sd s6, 592(sp) # 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: sd s7, 584(sp) # 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: sd s8, 576(sp) # 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: sd s9, 568(sp) # 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: sd s10, 560(sp) # 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: sd s11, 552(sp) # 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: .cfi_offset ra, -8
+; ZVFBFMIN64-NEXT: .cfi_offset s0, -16
+; ZVFBFMIN64-NEXT: .cfi_offset s1, -24
+; ZVFBFMIN64-NEXT: .cfi_offset s2, -32
+; ZVFBFMIN64-NEXT: .cfi_offset s3, -40
+; ZVFBFMIN64-NEXT: .cfi_offset s4, -48
+; ZVFBFMIN64-NEXT: .cfi_offset s5, -56
+; ZVFBFMIN64-NEXT: .cfi_offset s6, -64
+; ZVFBFMIN64-NEXT: .cfi_offset s7, -72
+; ZVFBFMIN64-NEXT: .cfi_offset s8, -80
+; ZVFBFMIN64-NEXT: .cfi_offset s9, -88
+; ZVFBFMIN64-NEXT: .cfi_offset s10, -96
+; ZVFBFMIN64-NEXT: .cfi_offset s11, -104
+; ZVFBFMIN64-NEXT: addi s0, sp, 656
+; ZVFBFMIN64-NEXT: .cfi_def_cfa s0, 0
+; ZVFBFMIN64-NEXT: csrr a0, vlenb
+; ZVFBFMIN64-NEXT: slli a1, a0, 3
+; ZVFBFMIN64-NEXT: sub a0, a1, a0
+; ZVFBFMIN64-NEXT: sub sp, sp, a0
+; ZVFBFMIN64-NEXT: andi sp, sp, -128
+; ZVFBFMIN64-NEXT: li a0, 64
+; ZVFBFMIN64-NEXT: addi a2, sp, 256
+; ZVFBFMIN64-NEXT: addi a4, sp, 128
+; ZVFBFMIN64-NEXT: lui a1, 8
+; ZVFBFMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFBFMIN64-NEXT: vmv.x.s a3, v16
+; ZVFBFMIN64-NEXT: vslidedown.vi v24, v16, 7
+; ZVFBFMIN64-NEXT: csrr a5, vlenb
+; ZVFBFMIN64-NEXT: slli a6, a5, 2
+; ZVFBFMIN64-NEXT: add a5, a6, a5
+; ZVFBFMIN64-NEXT: add a5, sp, a5
+; ZVFBFMIN64-NEXT: addi a5, a5, 544
+; ZVFBFMIN64-NEXT: vs1r.v v24, (a5) # vscale x 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: vslidedown.vi v24, v16, 6
+; ZVFBFMIN64-NEXT: csrr a5, vlenb
+; ZVFBFMIN64-NEXT: slli a5, a5, 2
+; ZVFBFMIN64-NEXT: add a5, sp, a5
+; ZVFBFMIN64-NEXT: addi a5, a5, 544
+; ZVFBFMIN64-NEXT: vs1r.v v24, (a5) # vscale x 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFMIN64-NEXT: vse16.v v16, (a2)
+; ZVFBFMIN64-NEXT: vse16.v v8, (a4)
+; ZVFBFMIN64-NEXT: lhu a4, 382(sp)
+; ZVFBFMIN64-NEXT: lhu a5, 254(sp)
+; ZVFBFMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFBFMIN64-NEXT: vslidedown.vi v10, v16, 5
+; ZVFBFMIN64-NEXT: csrr a2, vlenb
+; ZVFBFMIN64-NEXT: add a2, sp, a2
+; ZVFBFMIN64-NEXT: addi a2, a2, 544
+; ZVFBFMIN64-NEXT: vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: addi a2, a1, -1
+; ZVFBFMIN64-NEXT: and a4, a4, a1
+; ZVFBFMIN64-NEXT: and a5, a5, a2
+; ZVFBFMIN64-NEXT: or a4, a5, a4
+; ZVFBFMIN64-NEXT: sh a4, 510(sp)
+; ZVFBFMIN64-NEXT: lhu a4, 380(sp)
+; ZVFBFMIN64-NEXT: lhu a5, 252(sp)
+; ZVFBFMIN64-NEXT: vslidedown.vi v10, v16, 4
+; ZVFBFMIN64-NEXT: addi a6, sp, 544
+; ZVFBFMIN64-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: vslidedown.vi v10, v16, 3
+; ZVFBFMIN64-NEXT: csrr a6, vlenb
+; ZVFBFMIN64-NEXT: slli a6, a6, 1
+; ZVFBFMIN64-NEXT: mv a7, a6
+; ZVFBFMIN64-NEXT: slli a6, a6, 1
+; ZVFBFMIN64-NEXT: add a6, a6, a7
+; ZVFBFMIN64-NEXT: add a6, sp, a6
+; ZVFBFMIN64-NEXT: addi a6, a6, 544
+; ZVFBFMIN64-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: and a4, a4, a1
+; ZVFBFMIN64-NEXT: and a5, a5, a2
+; ZVFBFMIN64-NEXT: or a4, a5, a4
+; ZVFBFMIN64-NEXT: sh a4, 508(sp)
+; ZVFBFMIN64-NEXT: lhu a4, 378(sp)
+; ZVFBFMIN64-NEXT: lhu a5, 250(sp)
+; ZVFBFMIN64-NEXT: vslidedown.vi v10, v16, 2
+; ZVFBFMIN64-NEXT: csrr a6, vlenb
+; ZVFBFMIN64-NEXT: slli a7, a6, 1
+; ZVFBFMIN64-NEXT: add a6, a7, a6
+; ZVFBFMIN64-NEXT: add a6, sp, a6
+; ZVFBFMIN64-NEXT: addi a6, a6, 544
+; ZVFBFMIN64-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: vslidedown.vi v10, v16, 1
+; ZVFBFMIN64-NEXT: csrr a6, vlenb
+; ZVFBFMIN64-NEXT: slli a6, a6, 1
+; ZVFBFMIN64-NEXT: add a6, sp, a6
+; ZVFBFMIN64-NEXT: addi a6, a6, 544
+; ZVFBFMIN64-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: and a4, a4, a1
+; ZVFBFMIN64-NEXT: and a5, a5, a2
+; ZVFBFMIN64-NEXT: or a4, a5, a4
+; ZVFBFMIN64-NEXT: sh a4, 506(sp)
+; ZVFBFMIN64-NEXT: lhu a4, 376(sp)
+; ZVFBFMIN64-NEXT: lhu a5, 248(sp)
+; ZVFBFMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFBFMIN64-NEXT: vslidedown.vi v26, v16, 15
+; ZVFBFMIN64-NEXT: vslidedown.vi v28, v16, 14
+; ZVFBFMIN64-NEXT: and a4, a4, a1
+; ZVFBFMIN64-NEXT: and a5, a5, a2
+; ZVFBFMIN64-NEXT: or a4, a5, a4
+; ZVFBFMIN64-NEXT: sh a4, 504(sp)
+; ZVFBFMIN64-NEXT: lhu a4, 374(sp)
+; ZVFBFMIN64-NEXT: lhu a5, 246(sp)
+; ZVFBFMIN64-NEXT: vslidedown.vi v30, v16, 13
+; ZVFBFMIN64-NEXT: vslidedown.vi v6, v16, 12
+; ZVFBFMIN64-NEXT: and a4, a4, a1
+; ZVFBFMIN64-NEXT: and a5, a5, a2
+; ZVFBFMIN64-NEXT: or a4, a5, a4
+; ZVFBFMIN64-NEXT: sh a4, 502(sp)
+; ZVFBFMIN64-NEXT: lhu a4, 372(sp)
+; ZVFBFMIN64-NEXT: lhu a5, 244(sp)
+; ZVFBFMIN64-NEXT: vslidedown.vi v20, v16, 11
+; ZVFBFMIN64-NEXT: vslidedown.vi v18, v16, 10
+; ZVFBFMIN64-NEXT: vslidedown.vi v2, v16, 9
+; ZVFBFMIN64-NEXT: vslidedown.vi v0, v16, 8
+; ZVFBFMIN64-NEXT: and a4, a4, a1
+; ZVFBFMIN64-NEXT: and a5, a5, a2
+; ZVFBFMIN64-NEXT: or a4, a5, a4
+; ZVFBFMIN64-NEXT: sh a4, 500(sp)
+; ZVFBFMIN64-NEXT: lhu a4, 370(sp)
+; ZVFBFMIN64-NEXT: lhu a5, 242(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s t3, v8
+; ZVFBFMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFBFMIN64-NEXT: vslidedown.vi v7, v8, 7
+; ZVFBFMIN64-NEXT: and a4, a4, a1
+; ZVFBFMIN64-NEXT: and a5, a5, a2
+; ZVFBFMIN64-NEXT: or a4, a5, a4
+; ZVFBFMIN64-NEXT: sh a4, 498(sp)
+; ZVFBFMIN64-NEXT: lhu a4, 368(sp)
+; ZVFBFMIN64-NEXT: lhu a5, 240(sp)
+; ZVFBFMIN64-NEXT: vslidedown.vi v3, v8, 6
+; ZVFBFMIN64-NEXT: vslidedown.vi v27, v8, 5
+; ZVFBFMIN64-NEXT: vslidedown.vi v21, v8, 4
+; ZVFBFMIN64-NEXT: vslidedown.vi v19, v8, 3
+; ZVFBFMIN64-NEXT: vslidedown.vi v31, v8, 2
+; ZVFBFMIN64-NEXT: vslidedown.vi v29, v8, 1
+; ZVFBFMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFBFMIN64-NEXT: vslidedown.vi v10, v8, 15
+; ZVFBFMIN64-NEXT: vslidedown.vi v12, v8, 14
+; ZVFBFMIN64-NEXT: vslidedown.vi v14, v8, 13
+; ZVFBFMIN64-NEXT: vslidedown.vi v24, v8, 12
+; ZVFBFMIN64-NEXT: vslidedown.vi v22, v8, 11
+; ZVFBFMIN64-NEXT: vslidedown.vi v16, v8, 10
+; ZVFBFMIN64-NEXT: vslidedown.vi v4, v8, 9
+; ZVFBFMIN64-NEXT: vslidedown.vi v8, v8, 8
+; ZVFBFMIN64-NEXT: and a4, a4, a1
+; ZVFBFMIN64-NEXT: and a5, a5, a2
+; ZVFBFMIN64-NEXT: or a4, a5, a4
+; ZVFBFMIN64-NEXT: sh a4, 496(sp)
+; ZVFBFMIN64-NEXT: lhu a4, 366(sp)
+; ZVFBFMIN64-NEXT: lhu a5, 238(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s t1, v26
+; ZVFBFMIN64-NEXT: vmv.x.s t2, v10
+; ZVFBFMIN64-NEXT: and a4, a4, a1
+; ZVFBFMIN64-NEXT: and a5, a5, a2
+; ZVFBFMIN64-NEXT: or a4, a5, a4
+; ZVFBFMIN64-NEXT: sh a4, 494(sp)
+; ZVFBFMIN64-NEXT: lhu a4, 364(sp)
+; ZVFBFMIN64-NEXT: lhu a5, 236(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s t0, v28
+; ZVFBFMIN64-NEXT: vmv.x.s a7, v12
+; ZVFBFMIN64-NEXT: and a4, a4, a1
+; ZVFBFMIN64-NEXT: and a5, a5, a2
+; ZVFBFMIN64-NEXT: or a4, a5, a4
+; ZVFBFMIN64-NEXT: sh a4, 492(sp)
+; ZVFBFMIN64-NEXT: lhu a4, 362(sp)
+; ZVFBFMIN64-NEXT: lhu t4, 234(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s a6, v30
+; ZVFBFMIN64-NEXT: vmv.x.s a5, v14
+; ZVFBFMIN64-NEXT: and a4, a4, a1
+; ZVFBFMIN64-NEXT: and t4, t4, a2
+; ZVFBFMIN64-NEXT: or a4, t4, a4
+; ZVFBFMIN64-NEXT: sh a4, 490(sp)
+; ZVFBFMIN64-NEXT: lhu t4, 360(sp)
+; ZVFBFMIN64-NEXT: lhu t5, 232(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s a4, v6
+; ZVFBFMIN64-NEXT: csrr t6, vlenb
+; ZVFBFMIN64-NEXT: slli s1, t6, 2
+; ZVFBFMIN64-NEXT: add t6, s1, t6
+; ZVFBFMIN64-NEXT: add t6, sp, t6
+; ZVFBFMIN64-NEXT: lh s6, 544(t6) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: and t4, t4, a1
+; ZVFBFMIN64-NEXT: and t5, t5, a2
+; ZVFBFMIN64-NEXT: or t4, t5, t4
+; ZVFBFMIN64-NEXT: sh t4, 488(sp)
+; ZVFBFMIN64-NEXT: lhu t5, 358(sp)
+; ZVFBFMIN64-NEXT: lhu t6, 230(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s s7, v7
+; ZVFBFMIN64-NEXT: csrr t4, vlenb
+; ZVFBFMIN64-NEXT: slli t4, t4, 2
+; ZVFBFMIN64-NEXT: add t4, sp, t4
+; ZVFBFMIN64-NEXT: lh t4, 544(t4) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: and t5, t5, a1
+; ZVFBFMIN64-NEXT: and t6, t6, a2
+; ZVFBFMIN64-NEXT: or t5, t6, t5
+; ZVFBFMIN64-NEXT: sh t5, 486(sp)
+; ZVFBFMIN64-NEXT: lhu t5, 356(sp)
+; ZVFBFMIN64-NEXT: lhu s1, 228(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s s4, v3
+; ZVFBFMIN64-NEXT: csrr t6, vlenb
+; ZVFBFMIN64-NEXT: add t6, sp, t6
+; ZVFBFMIN64-NEXT: lh t6, 544(t6) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: and t5, t5, a1
+; ZVFBFMIN64-NEXT: and s1, s1, a2
+; ZVFBFMIN64-NEXT: or t5, s1, t5
+; ZVFBFMIN64-NEXT: sh t5, 484(sp)
+; ZVFBFMIN64-NEXT: lhu s2, 354(sp)
+; ZVFBFMIN64-NEXT: lhu s3, 226(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s s1, v27
+; ZVFBFMIN64-NEXT: lh t5, 544(sp) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: and s2, s2, a1
+; ZVFBFMIN64-NEXT: and s3, s3, a2
+; ZVFBFMIN64-NEXT: or s2, s3, s2
+; ZVFBFMIN64-NEXT: sh s2, 482(sp)
+; ZVFBFMIN64-NEXT: lhu s2, 352(sp)
+; ZVFBFMIN64-NEXT: lhu s3, 224(sp)
+; ZVFBFMIN64-NEXT: and a3, a3, a1
+; ZVFBFMIN64-NEXT: and t3, t3, a2
+; ZVFBFMIN64-NEXT: and s2, s2, a1
+; ZVFBFMIN64-NEXT: and s3, s3, a2
+; ZVFBFMIN64-NEXT: or s2, s3, s2
+; ZVFBFMIN64-NEXT: sh s2, 480(sp)
+; ZVFBFMIN64-NEXT: lhu s2, 350(sp)
+; ZVFBFMIN64-NEXT: lhu s3, 222(sp)
+; ZVFBFMIN64-NEXT: or a3, t3, a3
+; ZVFBFMIN64-NEXT: sh a3, 384(sp)
+; ZVFBFMIN64-NEXT: and a3, s2, a1
+; ZVFBFMIN64-NEXT: and t3, s3, a2
+; ZVFBFMIN64-NEXT: or a3, t3, a3
+; ZVFBFMIN64-NEXT: sh a3, 478(sp)
+; ZVFBFMIN64-NEXT: lhu a3, 348(sp)
+; ZVFBFMIN64-NEXT: lhu t3, 220(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s s10, v21
+; ZVFBFMIN64-NEXT: csrr s2, vlenb
+; ZVFBFMIN64-NEXT: slli s2, s2, 1
+; ZVFBFMIN64-NEXT: mv s3, s2
+; ZVFBFMIN64-NEXT: slli s2, s2, 1
+; ZVFBFMIN64-NEXT: add s2, s2, s3
+; ZVFBFMIN64-NEXT: add s2, sp, s2
+; ZVFBFMIN64-NEXT: lh s8, 544(s2) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: and a3, a3, a1
+; ZVFBFMIN64-NEXT: and t3, t3, a2
+; ZVFBFMIN64-NEXT: or a3, t3, a3
+; ZVFBFMIN64-NEXT: sh a3, 476(sp)
+; ZVFBFMIN64-NEXT: lhu a3, 346(sp)
+; ZVFBFMIN64-NEXT: lhu t3, 218(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s s9, v19
+; ZVFBFMIN64-NEXT: csrr s2, vlenb
+; ZVFBFMIN64-NEXT: slli s3, s2, 1
+; ZVFBFMIN64-NEXT: add s2, s3, s2
+; ZVFBFMIN64-NEXT: add s2, sp, s2
+; ZVFBFMIN64-NEXT: lh s3, 544(s2) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: and a3, a3, a1
+; ZVFBFMIN64-NEXT: and t3, t3, a2
+; ZVFBFMIN64-NEXT: or a3, t3, a3
+; ZVFBFMIN64-NEXT: sh a3, 474(sp)
+; ZVFBFMIN64-NEXT: lhu t3, 344(sp)
+; ZVFBFMIN64-NEXT: lhu s2, 216(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s s5, v31
+; ZVFBFMIN64-NEXT: csrr a3, vlenb
+; ZVFBFMIN64-NEXT: slli a3, a3, 1
+; ZVFBFMIN64-NEXT: add a3, sp, a3
+; ZVFBFMIN64-NEXT: lh a3, 544(a3) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: and t3, t3, a1
+; ZVFBFMIN64-NEXT: and s2, s2, a2
+; ZVFBFMIN64-NEXT: or t3, s2, t3
+; ZVFBFMIN64-NEXT: sh t3, 472(sp)
+; ZVFBFMIN64-NEXT: lhu t3, 342(sp)
+; ZVFBFMIN64-NEXT: lhu s11, 214(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s s2, v29
+; ZVFBFMIN64-NEXT: and s6, s6, a1
+; ZVFBFMIN64-NEXT: and t3, t3, a1
+; ZVFBFMIN64-NEXT: and s11, s11, a2
+; ZVFBFMIN64-NEXT: or t3, s11, t3
+; ZVFBFMIN64-NEXT: sh t3, 470(sp)
+; ZVFBFMIN64-NEXT: lhu s11, 340(sp)
+; ZVFBFMIN64-NEXT: lhu ra, 212(sp)
+; ZVFBFMIN64-NEXT: and t3, s7, a2
+; ZVFBFMIN64-NEXT: or t3, t3, s6
+; ZVFBFMIN64-NEXT: and s6, s11, a1
+; ZVFBFMIN64-NEXT: and s7, ra, a2
+; ZVFBFMIN64-NEXT: or s6, s7, s6
+; ZVFBFMIN64-NEXT: sh s6, 468(sp)
+; ZVFBFMIN64-NEXT: lhu s6, 338(sp)
+; ZVFBFMIN64-NEXT: lhu s7, 210(sp)
+; ZVFBFMIN64-NEXT: and t4, t4, a1
+; ZVFBFMIN64-NEXT: and s4, s4, a2
+; ZVFBFMIN64-NEXT: and s6, s6, a1
+; ZVFBFMIN64-NEXT: and s7, s7, a2
+; ZVFBFMIN64-NEXT: or s6, s7, s6
+; ZVFBFMIN64-NEXT: sh s6, 466(sp)
+; ZVFBFMIN64-NEXT: lhu s6, 336(sp)
+; ZVFBFMIN64-NEXT: lhu s7, 208(sp)
+; ZVFBFMIN64-NEXT: or t4, s4, t4
+; ZVFBFMIN64-NEXT: and t6, t6, a1
+; ZVFBFMIN64-NEXT: and s4, s6, a1
+; ZVFBFMIN64-NEXT: and s6, s7, a2
+; ZVFBFMIN64-NEXT: or s4, s6, s4
+; ZVFBFMIN64-NEXT: sh s4, 464(sp)
+; ZVFBFMIN64-NEXT: lhu s4, 334(sp)
+; ZVFBFMIN64-NEXT: lhu s6, 206(sp)
+; ZVFBFMIN64-NEXT: and s1, s1, a2
+; ZVFBFMIN64-NEXT: or t6, s1, t6
+; ZVFBFMIN64-NEXT: and s1, s4, a1
+; ZVFBFMIN64-NEXT: and s4, s6, a2
+; ZVFBFMIN64-NEXT: or s1, s4, s1
+; ZVFBFMIN64-NEXT: sh s1, 462(sp)
+; ZVFBFMIN64-NEXT: lhu s1, 332(sp)
+; ZVFBFMIN64-NEXT: lhu s4, 204(sp)
+; ZVFBFMIN64-NEXT: and t5, t5, a1
+; ZVFBFMIN64-NEXT: and s6, s10, a2
+; ZVFBFMIN64-NEXT: and s1, s1, a1
+; ZVFBFMIN64-NEXT: and s4, s4, a2
+; ZVFBFMIN64-NEXT: or s1, s4, s1
+; ZVFBFMIN64-NEXT: sh s1, 460(sp)
+; ZVFBFMIN64-NEXT: lhu s1, 330(sp)
+; ZVFBFMIN64-NEXT: lhu s4, 202(sp)
+; ZVFBFMIN64-NEXT: or t5, s6, t5
+; ZVFBFMIN64-NEXT: and s6, s8, a1
+; ZVFBFMIN64-NEXT: and s1, s1, a1
+; ZVFBFMIN64-NEXT: and s4, s4, a2
+; ZVFBFMIN64-NEXT: or s1, s4, s1
+; ZVFBFMIN64-NEXT: sh s1, 458(sp)
+; ZVFBFMIN64-NEXT: lhu s1, 328(sp)
+; ZVFBFMIN64-NEXT: lhu s4, 200(sp)
+; ZVFBFMIN64-NEXT: and s7, s9, a2
+; ZVFBFMIN64-NEXT: or s6, s7, s6
+; ZVFBFMIN64-NEXT: and s1, s1, a1
+; ZVFBFMIN64-NEXT: and s4, s4, a2
+; ZVFBFMIN64-NEXT: or s1, s4, s1
+; ZVFBFMIN64-NEXT: sh s1, 456(sp)
+; ZVFBFMIN64-NEXT: lhu s1, 326(sp)
+; ZVFBFMIN64-NEXT: lhu s4, 198(sp)
+; ZVFBFMIN64-NEXT: and s3, s3, a1
+; ZVFBFMIN64-NEXT: and s5, s5, a2
+; ZVFBFMIN64-NEXT: and s1, s1, a1
+; ZVFBFMIN64-NEXT: and s4, s4, a2
+; ZVFBFMIN64-NEXT: or s1, s4, s1
+; ZVFBFMIN64-NEXT: sh s1, 454(sp)
+; ZVFBFMIN64-NEXT: lhu s1, 324(sp)
+; ZVFBFMIN64-NEXT: lhu s4, 196(sp)
+; ZVFBFMIN64-NEXT: or s3, s5, s3
+; ZVFBFMIN64-NEXT: and a3, a3, a1
+; ZVFBFMIN64-NEXT: and s1, s1, a1
+; ZVFBFMIN64-NEXT: and s4, s4, a2
+; ZVFBFMIN64-NEXT: or s1, s4, s1
+; ZVFBFMIN64-NEXT: sh s1, 452(sp)
+; ZVFBFMIN64-NEXT: lhu s1, 322(sp)
+; ZVFBFMIN64-NEXT: lhu s4, 194(sp)
+; ZVFBFMIN64-NEXT: and s2, s2, a2
+; ZVFBFMIN64-NEXT: or s2, s2, a3
+; ZVFBFMIN64-NEXT: and s1, s1, a1
+; ZVFBFMIN64-NEXT: and a3, s4, a2
+; ZVFBFMIN64-NEXT: or a3, a3, s1
+; ZVFBFMIN64-NEXT: sh a3, 450(sp)
+; ZVFBFMIN64-NEXT: lhu a3, 320(sp)
+; ZVFBFMIN64-NEXT: lhu s1, 192(sp)
+; ZVFBFMIN64-NEXT: and t1, t1, a1
+; ZVFBFMIN64-NEXT: and t2, t2, a2
+; ZVFBFMIN64-NEXT: and a3, a3, a1
+; ZVFBFMIN64-NEXT: and s1, s1, a2
+; ZVFBFMIN64-NEXT: or a3, s1, a3
+; ZVFBFMIN64-NEXT: sh a3, 448(sp)
+; ZVFBFMIN64-NEXT: lhu s1, 318(sp)
+; ZVFBFMIN64-NEXT: lhu s4, 190(sp)
+; ZVFBFMIN64-NEXT: or a3, t2, t1
+; ZVFBFMIN64-NEXT: vmv.x.s t2, v24
+; ZVFBFMIN64-NEXT: and s1, s1, a1
+; ZVFBFMIN64-NEXT: and t1, s4, a2
+; ZVFBFMIN64-NEXT: or t1, t1, s1
+; ZVFBFMIN64-NEXT: sh t1, 446(sp)
+; ZVFBFMIN64-NEXT: lhu t1, 316(sp)
+; ZVFBFMIN64-NEXT: lhu s1, 188(sp)
+; ZVFBFMIN64-NEXT: sh s2, 386(sp)
+; ZVFBFMIN64-NEXT: sh s3, 388(sp)
+; ZVFBFMIN64-NEXT: sh s6, 390(sp)
+; ZVFBFMIN64-NEXT: sh t5, 392(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s t5, v20
+; ZVFBFMIN64-NEXT: and t1, t1, a1
+; ZVFBFMIN64-NEXT: and s1, s1, a2
+; ZVFBFMIN64-NEXT: or s1, s1, t1
+; ZVFBFMIN64-NEXT: vmv.x.s t1, v22
+; ZVFBFMIN64-NEXT: and t0, t0, a1
+; ZVFBFMIN64-NEXT: sh t6, 394(sp)
+; ZVFBFMIN64-NEXT: sh t4, 396(sp)
+; ZVFBFMIN64-NEXT: sh t3, 398(sp)
+; ZVFBFMIN64-NEXT: sh s1, 444(sp)
+; ZVFBFMIN64-NEXT: lhu t3, 314(sp)
+; ZVFBFMIN64-NEXT: lhu t4, 186(sp)
+; ZVFBFMIN64-NEXT: and a7, a7, a2
+; ZVFBFMIN64-NEXT: or a7, a7, t0
+; ZVFBFMIN64-NEXT: and t0, t3, a1
+; ZVFBFMIN64-NEXT: and t3, t4, a2
+; ZVFBFMIN64-NEXT: or t0, t3, t0
+; ZVFBFMIN64-NEXT: sh t0, 442(sp)
+; ZVFBFMIN64-NEXT: lhu t0, 312(sp)
+; ZVFBFMIN64-NEXT: lhu t3, 184(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s t4, v18
+; ZVFBFMIN64-NEXT: and a6, a6, a1
+; ZVFBFMIN64-NEXT: and t0, t0, a1
+; ZVFBFMIN64-NEXT: and t3, t3, a2
+; ZVFBFMIN64-NEXT: or t0, t3, t0
+; ZVFBFMIN64-NEXT: sh t0, 440(sp)
+; ZVFBFMIN64-NEXT: lhu t0, 310(sp)
+; ZVFBFMIN64-NEXT: lhu t3, 182(sp)
+; ZVFBFMIN64-NEXT: and a5, a5, a2
+; ZVFBFMIN64-NEXT: or a5, a5, a6
+; ZVFBFMIN64-NEXT: and a6, t0, a1
+; ZVFBFMIN64-NEXT: and t0, t3, a2
+; ZVFBFMIN64-NEXT: or a6, t0, a6
+; ZVFBFMIN64-NEXT: sh a6, 438(sp)
+; ZVFBFMIN64-NEXT: lhu a6, 308(sp)
+; ZVFBFMIN64-NEXT: lhu t0, 180(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s t3, v16
+; ZVFBFMIN64-NEXT: and a4, a4, a1
+; ZVFBFMIN64-NEXT: and a6, a6, a1
+; ZVFBFMIN64-NEXT: and t0, t0, a2
+; ZVFBFMIN64-NEXT: or a6, t0, a6
+; ZVFBFMIN64-NEXT: sh a6, 436(sp)
+; ZVFBFMIN64-NEXT: lhu a6, 306(sp)
+; ZVFBFMIN64-NEXT: lhu t0, 178(sp)
+; ZVFBFMIN64-NEXT: and t2, t2, a2
+; ZVFBFMIN64-NEXT: or a4, t2, a4
+; ZVFBFMIN64-NEXT: and a6, a6, a1
+; ZVFBFMIN64-NEXT: and t0, t0, a2
+; ZVFBFMIN64-NEXT: or a6, t0, a6
+; ZVFBFMIN64-NEXT: sh a6, 434(sp)
+; ZVFBFMIN64-NEXT: lhu a6, 304(sp)
+; ZVFBFMIN64-NEXT: lhu t0, 176(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s t2, v2
+; ZVFBFMIN64-NEXT: and t5, t5, a1
+; ZVFBFMIN64-NEXT: and a6, a6, a1
+; ZVFBFMIN64-NEXT: and t0, t0, a2
+; ZVFBFMIN64-NEXT: or a6, t0, a6
+; ZVFBFMIN64-NEXT: sh a6, 432(sp)
+; ZVFBFMIN64-NEXT: lhu t0, 302(sp)
+; ZVFBFMIN64-NEXT: lhu t6, 174(sp)
+; ZVFBFMIN64-NEXT: and a6, t1, a2
+; ZVFBFMIN64-NEXT: or a6, a6, t5
+; ZVFBFMIN64-NEXT: and t0, t0, a1
+; ZVFBFMIN64-NEXT: and t1, t6, a2
+; ZVFBFMIN64-NEXT: or t0, t1, t0
+; ZVFBFMIN64-NEXT: sh t0, 430(sp)
+; ZVFBFMIN64-NEXT: lhu t0, 300(sp)
+; ZVFBFMIN64-NEXT: lhu t1, 172(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s t5, v4
+; ZVFBFMIN64-NEXT: and t4, t4, a1
+; ZVFBFMIN64-NEXT: and t0, t0, a1
+; ZVFBFMIN64-NEXT: and t1, t1, a2
+; ZVFBFMIN64-NEXT: or t0, t1, t0
+; ZVFBFMIN64-NEXT: sh t0, 428(sp)
+; ZVFBFMIN64-NEXT: lhu t0, 298(sp)
+; ZVFBFMIN64-NEXT: lhu t1, 170(sp)
+; ZVFBFMIN64-NEXT: and t3, t3, a2
+; ZVFBFMIN64-NEXT: or t3, t3, t4
+; ZVFBFMIN64-NEXT: and t0, t0, a1
+; ZVFBFMIN64-NEXT: and t1, t1, a2
+; ZVFBFMIN64-NEXT: or t0, t1, t0
+; ZVFBFMIN64-NEXT: sh t0, 426(sp)
+; ZVFBFMIN64-NEXT: lhu t0, 296(sp)
+; ZVFBFMIN64-NEXT: lhu t1, 168(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s t4, v0
+; ZVFBFMIN64-NEXT: and t2, t2, a1
+; ZVFBFMIN64-NEXT: and t0, t0, a1
+; ZVFBFMIN64-NEXT: and t1, t1, a2
+; ZVFBFMIN64-NEXT: or t0, t1, t0
+; ZVFBFMIN64-NEXT: sh t0, 424(sp)
+; ZVFBFMIN64-NEXT: lhu t0, 294(sp)
+; ZVFBFMIN64-NEXT: lhu t1, 166(sp)
+; ZVFBFMIN64-NEXT: and t5, t5, a2
+; ZVFBFMIN64-NEXT: or t2, t5, t2
+; ZVFBFMIN64-NEXT: and t0, t0, a1
+; ZVFBFMIN64-NEXT: and t1, t1, a2
+; ZVFBFMIN64-NEXT: or t0, t1, t0
+; ZVFBFMIN64-NEXT: sh t0, 422(sp)
+; ZVFBFMIN64-NEXT: lhu t0, 292(sp)
+; ZVFBFMIN64-NEXT: lhu t1, 164(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s t5, v8
+; ZVFBFMIN64-NEXT: and t4, t4, a1
+; ZVFBFMIN64-NEXT: and t0, t0, a1
+; ZVFBFMIN64-NEXT: and t1, t1, a2
+; ZVFBFMIN64-NEXT: or t0, t1, t0
+; ZVFBFMIN64-NEXT: sh t0, 420(sp)
+; ZVFBFMIN64-NEXT: lhu t0, 290(sp)
+; ZVFBFMIN64-NEXT: lhu t1, 162(sp)
+; ZVFBFMIN64-NEXT: and t5, t5, a2
+; ZVFBFMIN64-NEXT: or t4, t5, t4
+; ZVFBFMIN64-NEXT: and t0, t0, a1
+; ZVFBFMIN64-NEXT: and t1, t1, a2
+; ZVFBFMIN64-NEXT: or t0, t1, t0
+; ZVFBFMIN64-NEXT: sh t0, 418(sp)
+; ZVFBFMIN64-NEXT: lhu t0, 288(sp)
+; ZVFBFMIN64-NEXT: lhu t1, 160(sp)
+; ZVFBFMIN64-NEXT: sh a4, 408(sp)
+; ZVFBFMIN64-NEXT: sh a5, 410(sp)
+; ZVFBFMIN64-NEXT: sh a7, 412(sp)
+; ZVFBFMIN64-NEXT: sh a3, 414(sp)
+; ZVFBFMIN64-NEXT: sh t4, 400(sp)
+; ZVFBFMIN64-NEXT: sh t2, 402(sp)
+; ZVFBFMIN64-NEXT: sh t3, 404(sp)
+; ZVFBFMIN64-NEXT: sh a6, 406(sp)
+; ZVFBFMIN64-NEXT: and a1, t0, a1
+; ZVFBFMIN64-NEXT: and a2, t1, a2
+; ZVFBFMIN64-NEXT: or a1, a2, a1
+; ZVFBFMIN64-NEXT: sh a1, 416(sp)
+; ZVFBFMIN64-NEXT: addi a1, sp, 384
+; ZVFBFMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFMIN64-NEXT: vle16.v v8, (a1)
+; ZVFBFMIN64-NEXT: addi sp, s0, -656
+; ZVFBFMIN64-NEXT: .cfi_def_cfa sp, 656
+; ZVFBFMIN64-NEXT: ld ra, 648(sp) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: ld s0, 640(sp) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: ld s1, 632(sp) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: ld s2, 624(sp) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: ld s3, 616(sp) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: ld s4, 608(sp) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: ld s5, 600(sp) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: ld s6, 592(sp) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: ld s7, 584(sp) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: ld s8, 576(sp) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: ld s9, 568(sp) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: ld s10, 560(sp) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: ld s11, 552(sp) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: .cfi_restore ra
+; ZVFBFMIN64-NEXT: .cfi_restore s0
+; ZVFBFMIN64-NEXT: .cfi_restore s1
+; ZVFBFMIN64-NEXT: .cfi_restore s2
+; ZVFBFMIN64-NEXT: .cfi_restore s3
+; ZVFBFMIN64-NEXT: .cfi_restore s4
+; ZVFBFMIN64-NEXT: .cfi_restore s5
+; ZVFBFMIN64-NEXT: .cfi_restore s6
+; ZVFBFMIN64-NEXT: .cfi_restore s7
+; ZVFBFMIN64-NEXT: .cfi_restore s8
+; ZVFBFMIN64-NEXT: .cfi_restore s9
+; ZVFBFMIN64-NEXT: .cfi_restore s10
+; ZVFBFMIN64-NEXT: .cfi_restore s11
+; ZVFBFMIN64-NEXT: addi sp, sp, 656
+; ZVFBFMIN64-NEXT: .cfi_def_cfa_offset 0
+; ZVFBFMIN64-NEXT: ret
+ %r = call <64 x bfloat> @llvm.copysign.v64bf16(<64 x bfloat> %vm, <64 x bfloat> %vs)
+ ret <64 x bfloat> %r
+}
+
+define <2 x half> @copysign_v2f16(<2 x half> %vm, <2 x half> %vs) {
+; CHECK-LABEL: copysign_v2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 8
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vor.vv v8, v8, v9
+; CHECK-NEXT: ret
+ %r = call <2 x half> @llvm.copysign.v2f16(<2 x half> %vm, <2 x half> %vs)
+ ret <2 x half> %r
+}
+
+define <8 x half> @copysign_v8f16(<8 x half> %vm, <8 x half> %vs) {
+; CHECK-LABEL: copysign_v8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 8
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vor.vv v8, v8, v9
+; CHECK-NEXT: ret
+ %r = call <8 x half> @llvm.copysign.v8f16(<8 x half> %vm, <8 x half> %vs)
+ ret <8 x half> %r
+}
+
+define <32 x half> @copysign_v32f16(<32 x half> %vm, <32 x half> %vs) {
+; CHECK-LABEL: copysign_v32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma
-; CHECK-NEXT: vfsgnj.vv v8, v8, v12
+; CHECK-NEXT: lui a1, 8
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: vand.vx v12, v12, a1
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: vand.vx v8, v8, a1
+; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: ret
- %r = call <32 x bfloat> @llvm.copysign.v32bf32(<32 x bfloat> %vm, <32 x bfloat> %vs)
- ret <32 x bfloat> %r
+ %r = call <32 x half> @llvm.copysign.v32f16(<32 x half> %vm, <32 x half> %vs)
+ ret <32 x half> %r
+}
+
+define <64 x half> @copysign_v64f16(<64 x half> %vm, <64 x half> %vs) {
+; ZVFHMIN32-LABEL: copysign_v64f16:
+; ZVFHMIN32: # %bb.0:
+; ZVFHMIN32-NEXT: addi sp, sp, -656
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 656
+; ZVFHMIN32-NEXT: sw ra, 652(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s0, 648(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s1, 644(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s2, 640(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s3, 636(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s4, 632(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s5, 628(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s6, 624(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s7, 620(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s8, 616(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s9, 612(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s10, 608(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s11, 604(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: .cfi_offset ra, -4
+; ZVFHMIN32-NEXT: .cfi_offset s0, -8
+; ZVFHMIN32-NEXT: .cfi_offset s1, -12
+; ZVFHMIN32-NEXT: .cfi_offset s2, -16
+; ZVFHMIN32-NEXT: .cfi_offset s3, -20
+; ZVFHMIN32-NEXT: .cfi_offset s4, -24
+; ZVFHMIN32-NEXT: .cfi_offset s5, -28
+; ZVFHMIN32-NEXT: .cfi_offset s6, -32
+; ZVFHMIN32-NEXT: .cfi_offset s7, -36
+; ZVFHMIN32-NEXT: .cfi_offset s8, -40
+; ZVFHMIN32-NEXT: .cfi_offset s9, -44
+; ZVFHMIN32-NEXT: .cfi_offset s10, -48
+; ZVFHMIN32-NEXT: .cfi_offset s11, -52
+; ZVFHMIN32-NEXT: addi s0, sp, 656
+; ZVFHMIN32-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN32-NEXT: csrr a0, vlenb
+; ZVFHMIN32-NEXT: slli a1, a0, 3
+; ZVFHMIN32-NEXT: sub a0, a1, a0
+; ZVFHMIN32-NEXT: sub sp, sp, a0
+; ZVFHMIN32-NEXT: andi sp, sp, -128
+; ZVFHMIN32-NEXT: li a0, 64
+; ZVFHMIN32-NEXT: addi a2, sp, 256
+; ZVFHMIN32-NEXT: addi a4, sp, 128
+; ZVFHMIN32-NEXT: lui a1, 8
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN32-NEXT: vmv.x.s a3, v16
+; ZVFHMIN32-NEXT: vslidedown.vi v24, v16, 7
+; ZVFHMIN32-NEXT: csrr a5, vlenb
+; ZVFHMIN32-NEXT: slli a6, a5, 2
+; ZVFHMIN32-NEXT: add a5, a6, a5
+; ZVFHMIN32-NEXT: add a5, sp, a5
+; ZVFHMIN32-NEXT: addi a5, a5, 592
+; ZVFHMIN32-NEXT: vs1r.v v24, (a5) # vscale x 8-byte Folded Spill
+; ZVFHMIN32-NEXT: vslidedown.vi v24, v16, 6
+; ZVFHMIN32-NEXT: csrr a5, vlenb
+; ZVFHMIN32-NEXT: slli a5, a5, 2
+; ZVFHMIN32-NEXT: add a5, sp, a5
+; ZVFHMIN32-NEXT: addi a5, a5, 592
+; ZVFHMIN32-NEXT: vs1r.v v24, (a5) # vscale x 8-byte Folded Spill
+; ZVFHMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN32-NEXT: vse16.v v16, (a2)
+; ZVFHMIN32-NEXT: vse16.v v8, (a4)
+; ZVFHMIN32-NEXT: lhu a4, 382(sp)
+; ZVFHMIN32-NEXT: lhu a5, 254(sp)
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v16, 5
+; ZVFHMIN32-NEXT: csrr a2, vlenb
+; ZVFHMIN32-NEXT: add a2, sp, a2
+; ZVFHMIN32-NEXT: addi a2, a2, 592
+; ZVFHMIN32-NEXT: vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
+; ZVFHMIN32-NEXT: addi a2, a1, -1
+; ZVFHMIN32-NEXT: and a4, a4, a1
+; ZVFHMIN32-NEXT: and a5, a5, a2
+; ZVFHMIN32-NEXT: or a4, a5, a4
+; ZVFHMIN32-NEXT: sh a4, 510(sp)
+; ZVFHMIN32-NEXT: lhu a4, 380(sp)
+; ZVFHMIN32-NEXT: lhu a5, 252(sp)
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v16, 4
+; ZVFHMIN32-NEXT: addi a6, sp, 592
+; ZVFHMIN32-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v16, 3
+; ZVFHMIN32-NEXT: csrr a6, vlenb
+; ZVFHMIN32-NEXT: slli a6, a6, 1
+; ZVFHMIN32-NEXT: mv a7, a6
+; ZVFHMIN32-NEXT: slli a6, a6, 1
+; ZVFHMIN32-NEXT: add a6, a6, a7
+; ZVFHMIN32-NEXT: add a6, sp, a6
+; ZVFHMIN32-NEXT: addi a6, a6, 592
+; ZVFHMIN32-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
+; ZVFHMIN32-NEXT: and a4, a4, a1
+; ZVFHMIN32-NEXT: and a5, a5, a2
+; ZVFHMIN32-NEXT: or a4, a5, a4
+; ZVFHMIN32-NEXT: sh a4, 508(sp)
+; ZVFHMIN32-NEXT: lhu a4, 378(sp)
+; ZVFHMIN32-NEXT: lhu a5, 250(sp)
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v16, 2
+; ZVFHMIN32-NEXT: csrr a6, vlenb
+; ZVFHMIN32-NEXT: slli a7, a6, 1
+; ZVFHMIN32-NEXT: add a6, a7, a6
+; ZVFHMIN32-NEXT: add a6, sp, a6
+; ZVFHMIN32-NEXT: addi a6, a6, 592
+; ZVFHMIN32-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v16, 1
+; ZVFHMIN32-NEXT: csrr a6, vlenb
+; ZVFHMIN32-NEXT: slli a6, a6, 1
+; ZVFHMIN32-NEXT: add a6, sp, a6
+; ZVFHMIN32-NEXT: addi a6, a6, 592
+; ZVFHMIN32-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
+; ZVFHMIN32-NEXT: and a4, a4, a1
+; ZVFHMIN32-NEXT: and a5, a5, a2
+; ZVFHMIN32-NEXT: or a4, a5, a4
+; ZVFHMIN32-NEXT: sh a4, 506(sp)
+; ZVFHMIN32-NEXT: lhu a4, 376(sp)
+; ZVFHMIN32-NEXT: lhu a5, 248(sp)
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v26, v16, 15
+; ZVFHMIN32-NEXT: vslidedown.vi v28, v16, 14
+; ZVFHMIN32-NEXT: and a4, a4, a1
+; ZVFHMIN32-NEXT: and a5, a5, a2
+; ZVFHMIN32-NEXT: or a4, a5, a4
+; ZVFHMIN32-NEXT: sh a4, 504(sp)
+; ZVFHMIN32-NEXT: lhu a4, 374(sp)
+; ZVFHMIN32-NEXT: lhu a5, 246(sp)
+; ZVFHMIN32-NEXT: vslidedown.vi v30, v16, 13
+; ZVFHMIN32-NEXT: vslidedown.vi v6, v16, 12
+; ZVFHMIN32-NEXT: and a4, a4, a1
+; ZVFHMIN32-NEXT: and a5, a5, a2
+; ZVFHMIN32-NEXT: or a4, a5, a4
+; ZVFHMIN32-NEXT: sh a4, 502(sp)
+; ZVFHMIN32-NEXT: lhu a4, 372(sp)
+; ZVFHMIN32-NEXT: lhu a5, 244(sp)
+; ZVFHMIN32-NEXT: vslidedown.vi v20, v16, 11
+; ZVFHMIN32-NEXT: vslidedown.vi v18, v16, 10
+; ZVFHMIN32-NEXT: vslidedown.vi v2, v16, 9
+; ZVFHMIN32-NEXT: vslidedown.vi v0, v16, 8
+; ZVFHMIN32-NEXT: and a4, a4, a1
+; ZVFHMIN32-NEXT: and a5, a5, a2
+; ZVFHMIN32-NEXT: or a4, a5, a4
+; ZVFHMIN32-NEXT: sh a4, 500(sp)
+; ZVFHMIN32-NEXT: lhu a4, 370(sp)
+; ZVFHMIN32-NEXT: lhu a5, 242(sp)
+; ZVFHMIN32-NEXT: vmv.x.s t3, v8
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v7, v8, 7
+; ZVFHMIN32-NEXT: and a4, a4, a1
+; ZVFHMIN32-NEXT: and a5, a5, a2
+; ZVFHMIN32-NEXT: or a4, a5, a4
+; ZVFHMIN32-NEXT: sh a4, 498(sp)
+; ZVFHMIN32-NEXT: lhu a4, 368(sp)
+; ZVFHMIN32-NEXT: lhu a5, 240(sp)
+; ZVFHMIN32-NEXT: vslidedown.vi v3, v8, 6
+; ZVFHMIN32-NEXT: vslidedown.vi v27, v8, 5
+; ZVFHMIN32-NEXT: vslidedown.vi v21, v8, 4
+; ZVFHMIN32-NEXT: vslidedown.vi v19, v8, 3
+; ZVFHMIN32-NEXT: vslidedown.vi v31, v8, 2
+; ZVFHMIN32-NEXT: vslidedown.vi v29, v8, 1
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 15
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 14
+; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 13
+; ZVFHMIN32-NEXT: vslidedown.vi v24, v8, 12
+; ZVFHMIN32-NEXT: vslidedown.vi v22, v8, 11
+; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 10
+; ZVFHMIN32-NEXT: vslidedown.vi v4, v8, 9
+; ZVFHMIN32-NEXT: vslidedown.vi v8, v8, 8
+; ZVFHMIN32-NEXT: and a4, a4, a1
+; ZVFHMIN32-NEXT: and a5, a5, a2
+; ZVFHMIN32-NEXT: or a4, a5, a4
+; ZVFHMIN32-NEXT: sh a4, 496(sp)
+; ZVFHMIN32-NEXT: lhu a4, 366(sp)
+; ZVFHMIN32-NEXT: lhu a5, 238(sp)
+; ZVFHMIN32-NEXT: vmv.x.s t1, v26
+; ZVFHMIN32-NEXT: vmv.x.s t2, v10
+; ZVFHMIN32-NEXT: and a4, a4, a1
+; ZVFHMIN32-NEXT: and a5, a5, a2
+; ZVFHMIN32-NEXT: or a4, a5, a4
+; ZVFHMIN32-NEXT: sh a4, 494(sp)
+; ZVFHMIN32-NEXT: lhu a4, 364(sp)
+; ZVFHMIN32-NEXT: lhu a5, 236(sp)
+; ZVFHMIN32-NEXT: vmv.x.s t0, v28
+; ZVFHMIN32-NEXT: vmv.x.s a7, v12
+; ZVFHMIN32-NEXT: and a4, a4, a1
+; ZVFHMIN32-NEXT: and a5, a5, a2
+; ZVFHMIN32-NEXT: or a4, a5, a4
+; ZVFHMIN32-NEXT: sh a4, 492(sp)
+; ZVFHMIN32-NEXT: lhu a4, 362(sp)
+; ZVFHMIN32-NEXT: lhu t4, 234(sp)
+; ZVFHMIN32-NEXT: vmv.x.s a6, v30
+; ZVFHMIN32-NEXT: vmv.x.s a5, v14
+; ZVFHMIN32-NEXT: and a4, a4, a1
+; ZVFHMIN32-NEXT: and t4, t4, a2
+; ZVFHMIN32-NEXT: or a4, t4, a4
+; ZVFHMIN32-NEXT: sh a4, 490(sp)
+; ZVFHMIN32-NEXT: lhu t4, 360(sp)
+; ZVFHMIN32-NEXT: lhu t5, 232(sp)
+; ZVFHMIN32-NEXT: vmv.x.s a4, v6
+; ZVFHMIN32-NEXT: csrr t6, vlenb
+; ZVFHMIN32-NEXT: slli s1, t6, 2
+; ZVFHMIN32-NEXT: add t6, s1, t6
+; ZVFHMIN32-NEXT: add t6, sp, t6
+; ZVFHMIN32-NEXT: lh s6, 592(t6) # 8-byte Folded Reload
+; ZVFHMIN32-NEXT: and t4, t4, a1
+; ZVFHMIN32-NEXT: and t5, t5, a2
+; ZVFHMIN32-NEXT: or t4, t5, t4
+; ZVFHMIN32-NEXT: sh t4, 488(sp)
+; ZVFHMIN32-NEXT: lhu t5, 358(sp)
+; ZVFHMIN32-NEXT: lhu t6, 230(sp)
+; ZVFHMIN32-NEXT: vmv.x.s s7, v7
+; ZVFHMIN32-NEXT: csrr t4, vlenb
+; ZVFHMIN32-NEXT: slli t4, t4, 2
+; ZVFHMIN32-NEXT: add t4, sp, t4
+; ZVFHMIN32-NEXT: lh t4, 592(t4) # 8-byte Folded Reload
+; ZVFHMIN32-NEXT: and t5, t5, a1
+; ZVFHMIN32-NEXT: and t6, t6, a2
+; ZVFHMIN32-NEXT: or t5, t6, t5
+; ZVFHMIN32-NEXT: sh t5, 486(sp)
+; ZVFHMIN32-NEXT: lhu t5, 356(sp)
+; ZVFHMIN32-NEXT: lhu s1, 228(sp)
+; ZVFHMIN32-NEXT: vmv.x.s s4, v3
+; ZVFHMIN32-NEXT: csrr t6, vlenb
+; ZVFHMIN32-NEXT: add t6, sp, t6
+; ZVFHMIN32-NEXT: lh t6, 592(t6) # 8-byte Folded Reload
+; ZVFHMIN32-NEXT: and t5, t5, a1
+; ZVFHMIN32-NEXT: and s1, s1, a2
+; ZVFHMIN32-NEXT: or t5, s1, t5
+; ZVFHMIN32-NEXT: sh t5, 484(sp)
+; ZVFHMIN32-NEXT: lhu s2, 354(sp)
+; ZVFHMIN32-NEXT: lhu s3, 226(sp)
+; ZVFHMIN32-NEXT: vmv.x.s s1, v27
+; ZVFHMIN32-NEXT: lh t5, 592(sp) # 8-byte Folded Reload
+; ZVFHMIN32-NEXT: and s2, s2, a1
+; ZVFHMIN32-NEXT: and s3, s3, a2
+; ZVFHMIN32-NEXT: or s2, s3, s2
+; ZVFHMIN32-NEXT: sh s2, 482(sp)
+; ZVFHMIN32-NEXT: lhu s2, 352(sp)
+; ZVFHMIN32-NEXT: lhu s3, 224(sp)
+; ZVFHMIN32-NEXT: and a3, a3, a1
+; ZVFHMIN32-NEXT: and t3, t3, a2
+; ZVFHMIN32-NEXT: and s2, s2, a1
+; ZVFHMIN32-NEXT: and s3, s3, a2
+; ZVFHMIN32-NEXT: or s2, s3, s2
+; ZVFHMIN32-NEXT: sh s2, 480(sp)
+; ZVFHMIN32-NEXT: lhu s2, 350(sp)
+; ZVFHMIN32-NEXT: lhu s3, 222(sp)
+; ZVFHMIN32-NEXT: or a3, t3, a3
+; ZVFHMIN32-NEXT: sh a3, 384(sp)
+; ZVFHMIN32-NEXT: and a3, s2, a1
+; ZVFHMIN32-NEXT: and t3, s3, a2
+; ZVFHMIN32-NEXT: or a3, t3, a3
+; ZVFHMIN32-NEXT: sh a3, 478(sp)
+; ZVFHMIN32-NEXT: lhu a3, 348(sp)
+; ZVFHMIN32-NEXT: lhu t3, 220(sp)
+; ZVFHMIN32-NEXT: vmv.x.s s10, v21
+; ZVFHMIN32-NEXT: csrr s2, vlenb
+; ZVFHMIN32-NEXT: slli s2, s2, 1
+; ZVFHMIN32-NEXT: mv s3, s2
+; ZVFHMIN32-NEXT: slli s2, s2, 1
+; ZVFHMIN32-NEXT: add s2, s2, s3
+; ZVFHMIN32-NEXT: add s2, sp, s2
+; ZVFHMIN32-NEXT: lh s8, 592(s2) # 8-byte Folded Reload
+; ZVFHMIN32-NEXT: and a3, a3, a1
+; ZVFHMIN32-NEXT: and t3, t3, a2
+; ZVFHMIN32-NEXT: or a3, t3, a3
+; ZVFHMIN32-NEXT: sh a3, 476(sp)
+; ZVFHMIN32-NEXT: lhu a3, 346(sp)
+; ZVFHMIN32-NEXT: lhu t3, 218(sp)
+; ZVFHMIN32-NEXT: vmv.x.s s9, v19
+; ZVFHMIN32-NEXT: csrr s2, vlenb
+; ZVFHMIN32-NEXT: slli s3, s2, 1
+; ZVFHMIN32-NEXT: add s2, s3, s2
+; ZVFHMIN32-NEXT: add s2, sp, s2
+; ZVFHMIN32-NEXT: lh s3, 592(s2) # 8-byte Folded Reload
+; ZVFHMIN32-NEXT: and a3, a3, a1
+; ZVFHMIN32-NEXT: and t3, t3, a2
+; ZVFHMIN32-NEXT: or a3, t3, a3
+; ZVFHMIN32-NEXT: sh a3, 474(sp)
+; ZVFHMIN32-NEXT: lhu t3, 344(sp)
+; ZVFHMIN32-NEXT: lhu s2, 216(sp)
+; ZVFHMIN32-NEXT: vmv.x.s s5, v31
+; ZVFHMIN32-NEXT: csrr a3, vlenb
+; ZVFHMIN32-NEXT: slli a3, a3, 1
+; ZVFHMIN32-NEXT: add a3, sp, a3
+; ZVFHMIN32-NEXT: lh a3, 592(a3) # 8-byte Folded Reload
+; ZVFHMIN32-NEXT: and t3, t3, a1
+; ZVFHMIN32-NEXT: and s2, s2, a2
+; ZVFHMIN32-NEXT: or t3, s2, t3
+; ZVFHMIN32-NEXT: sh t3, 472(sp)
+; ZVFHMIN32-NEXT: lhu t3, 342(sp)
+; ZVFHMIN32-NEXT: lhu s11, 214(sp)
+; ZVFHMIN32-NEXT: vmv.x.s s2, v29
+; ZVFHMIN32-NEXT: and s6, s6, a1
+; ZVFHMIN32-NEXT: and t3, t3, a1
+; ZVFHMIN32-NEXT: and s11, s11, a2
+; ZVFHMIN32-NEXT: or t3, s11, t3
+; ZVFHMIN32-NEXT: sh t3, 470(sp)
+; ZVFHMIN32-NEXT: lhu s11, 340(sp)
+; ZVFHMIN32-NEXT: lhu ra, 212(sp)
+; ZVFHMIN32-NEXT: and t3, s7, a2
+; ZVFHMIN32-NEXT: or t3, t3, s6
+; ZVFHMIN32-NEXT: and s6, s11, a1
+; ZVFHMIN32-NEXT: and s7, ra, a2
+; ZVFHMIN32-NEXT: or s6, s7, s6
+; ZVFHMIN32-NEXT: sh s6, 468(sp)
+; ZVFHMIN32-NEXT: lhu s6, 338(sp)
+; ZVFHMIN32-NEXT: lhu s7, 210(sp)
+; ZVFHMIN32-NEXT: and t4, t4, a1
+; ZVFHMIN32-NEXT: and s4, s4, a2
+; ZVFHMIN32-NEXT: and s6, s6, a1
+; ZVFHMIN32-NEXT: and s7, s7, a2
+; ZVFHMIN32-NEXT: or s6, s7, s6
+; ZVFHMIN32-NEXT: sh s6, 466(sp)
+; ZVFHMIN32-NEXT: lhu s6, 336(sp)
+; ZVFHMIN32-NEXT: lhu s7, 208(sp)
+; ZVFHMIN32-NEXT: or t4, s4, t4
+; ZVFHMIN32-NEXT: and t6, t6, a1
+; ZVFHMIN32-NEXT: and s4, s6, a1
+; ZVFHMIN32-NEXT: and s6, s7, a2
+; ZVFHMIN32-NEXT: or s4, s6, s4
+; ZVFHMIN32-NEXT: sh s4, 464(sp)
+; ZVFHMIN32-NEXT: lhu s4, 334(sp)
+; ZVFHMIN32-NEXT: lhu s6, 206(sp)
+; ZVFHMIN32-NEXT: and s1, s1, a2
+; ZVFHMIN32-NEXT: or t6, s1, t6
+; ZVFHMIN32-NEXT: and s1, s4, a1
+; ZVFHMIN32-NEXT: and s4, s6, a2
+; ZVFHMIN32-NEXT: or s1, s4, s1
+; ZVFHMIN32-NEXT: sh s1, 462(sp)
+; ZVFHMIN32-NEXT: lhu s1, 332(sp)
+; ZVFHMIN32-NEXT: lhu s4, 204(sp)
+; ZVFHMIN32-NEXT: and t5, t5, a1
+; ZVFHMIN32-NEXT: and s6, s10, a2
+; ZVFHMIN32-NEXT: and s1, s1, a1
+; ZVFHMIN32-NEXT: and s4, s4, a2
+; ZVFHMIN32-NEXT: or s1, s4, s1
+; ZVFHMIN32-NEXT: sh s1, 460(sp)
+; ZVFHMIN32-NEXT: lhu s1, 330(sp)
+; ZVFHMIN32-NEXT: lhu s4, 202(sp)
+; ZVFHMIN32-NEXT: or t5, s6, t5
+; ZVFHMIN32-NEXT: and s6, s8, a1
+; ZVFHMIN32-NEXT: and s1, s1, a1
+; ZVFHMIN32-NEXT: and s4, s4, a2
+; ZVFHMIN32-NEXT: or s1, s4, s1
+; ZVFHMIN32-NEXT: sh s1, 458(sp)
+; ZVFHMIN32-NEXT: lhu s1, 328(sp)
+; ZVFHMIN32-NEXT: lhu s4, 200(sp)
+; ZVFHMIN32-NEXT: and s7, s9, a2
+; ZVFHMIN32-NEXT: or s6, s7, s6
+; ZVFHMIN32-NEXT: and s1, s1, a1
+; ZVFHMIN32-NEXT: and s4, s4, a2
+; ZVFHMIN32-NEXT: or s1, s4, s1
+; ZVFHMIN32-NEXT: sh s1, 456(sp)
+; ZVFHMIN32-NEXT: lhu s1, 326(sp)
+; ZVFHMIN32-NEXT: lhu s4, 198(sp)
+; ZVFHMIN32-NEXT: and s3, s3, a1
+; ZVFHMIN32-NEXT: and s5, s5, a2
+; ZVFHMIN32-NEXT: and s1, s1, a1
+; ZVFHMIN32-NEXT: and s4, s4, a2
+; ZVFHMIN32-NEXT: or s1, s4, s1
+; ZVFHMIN32-NEXT: sh s1, 454(sp)
+; ZVFHMIN32-NEXT: lhu s1, 324(sp)
+; ZVFHMIN32-NEXT: lhu s4, 196(sp)
+; ZVFHMIN32-NEXT: or s3, s5, s3
+; ZVFHMIN32-NEXT: and a3, a3, a1
+; ZVFHMIN32-NEXT: and s1, s1, a1
+; ZVFHMIN32-NEXT: and s4, s4, a2
+; ZVFHMIN32-NEXT: or s1, s4, s1
+; ZVFHMIN32-NEXT: sh s1, 452(sp)
+; ZVFHMIN32-NEXT: lhu s1, 322(sp)
+; ZVFHMIN32-NEXT: lhu s4, 194(sp)
+; ZVFHMIN32-NEXT: and s2, s2, a2
+; ZVFHMIN32-NEXT: or s2, s2, a3
+; ZVFHMIN32-NEXT: and s1, s1, a1
+; ZVFHMIN32-NEXT: and a3, s4, a2
+; ZVFHMIN32-NEXT: or a3, a3, s1
+; ZVFHMIN32-NEXT: sh a3, 450(sp)
+; ZVFHMIN32-NEXT: lhu a3, 320(sp)
+; ZVFHMIN32-NEXT: lhu s1, 192(sp)
+; ZVFHMIN32-NEXT: and t1, t1, a1
+; ZVFHMIN32-NEXT: and t2, t2, a2
+; ZVFHMIN32-NEXT: and a3, a3, a1
+; ZVFHMIN32-NEXT: and s1, s1, a2
+; ZVFHMIN32-NEXT: or a3, s1, a3
+; ZVFHMIN32-NEXT: sh a3, 448(sp)
+; ZVFHMIN32-NEXT: lhu s1, 318(sp)
+; ZVFHMIN32-NEXT: lhu s4, 190(sp)
+; ZVFHMIN32-NEXT: or a3, t2, t1
+; ZVFHMIN32-NEXT: vmv.x.s t2, v24
+; ZVFHMIN32-NEXT: and s1, s1, a1
+; ZVFHMIN32-NEXT: and t1, s4, a2
+; ZVFHMIN32-NEXT: or t1, t1, s1
+; ZVFHMIN32-NEXT: sh t1, 446(sp)
+; ZVFHMIN32-NEXT: lhu t1, 316(sp)
+; ZVFHMIN32-NEXT: lhu s1, 188(sp)
+; ZVFHMIN32-NEXT: sh s2, 386(sp)
+; ZVFHMIN32-NEXT: sh s3, 388(sp)
+; ZVFHMIN32-NEXT: sh s6, 390(sp)
+; ZVFHMIN32-NEXT: sh t5, 392(sp)
+; ZVFHMIN32-NEXT: vmv.x.s t5, v20
+; ZVFHMIN32-NEXT: and t1, t1, a1
+; ZVFHMIN32-NEXT: and s1, s1, a2
+; ZVFHMIN32-NEXT: or s1, s1, t1
+; ZVFHMIN32-NEXT: vmv.x.s t1, v22
+; ZVFHMIN32-NEXT: and t0, t0, a1
+; ZVFHMIN32-NEXT: sh t6, 394(sp)
+; ZVFHMIN32-NEXT: sh t4, 396(sp)
+; ZVFHMIN32-NEXT: sh t3, 398(sp)
+; ZVFHMIN32-NEXT: sh s1, 444(sp)
+; ZVFHMIN32-NEXT: lhu t3, 314(sp)
+; ZVFHMIN32-NEXT: lhu t4, 186(sp)
+; ZVFHMIN32-NEXT: and a7, a7, a2
+; ZVFHMIN32-NEXT: or a7, a7, t0
+; ZVFHMIN32-NEXT: and t0, t3, a1
+; ZVFHMIN32-NEXT: and t3, t4, a2
+; ZVFHMIN32-NEXT: or t0, t3, t0
+; ZVFHMIN32-NEXT: sh t0, 442(sp)
+; ZVFHMIN32-NEXT: lhu t0, 312(sp)
+; ZVFHMIN32-NEXT: lhu t3, 184(sp)
+; ZVFHMIN32-NEXT: vmv.x.s t4, v18
+; ZVFHMIN32-NEXT: and a6, a6, a1
+; ZVFHMIN32-NEXT: and t0, t0, a1
+; ZVFHMIN32-NEXT: and t3, t3, a2
+; ZVFHMIN32-NEXT: or t0, t3, t0
+; ZVFHMIN32-NEXT: sh t0, 440(sp)
+; ZVFHMIN32-NEXT: lhu t0, 310(sp)
+; ZVFHMIN32-NEXT: lhu t3, 182(sp)
+; ZVFHMIN32-NEXT: and a5, a5, a2
+; ZVFHMIN32-NEXT: or a5, a5, a6
+; ZVFHMIN32-NEXT: and a6, t0, a1
+; ZVFHMIN32-NEXT: and t0, t3, a2
+; ZVFHMIN32-NEXT: or a6, t0, a6
+; ZVFHMIN32-NEXT: sh a6, 438(sp)
+; ZVFHMIN32-NEXT: lhu a6, 308(sp)
+; ZVFHMIN32-NEXT: lhu t0, 180(sp)
+; ZVFHMIN32-NEXT: vmv.x.s t3, v16
+; ZVFHMIN32-NEXT: and a4, a4, a1
+; ZVFHMIN32-NEXT: and a6, a6, a1
+; ZVFHMIN32-NEXT: and t0, t0, a2
+; ZVFHMIN32-NEXT: or a6, t0, a6
+; ZVFHMIN32-NEXT: sh a6, 436(sp)
+; ZVFHMIN32-NEXT: lhu a6, 306(sp)
+; ZVFHMIN32-NEXT: lhu t0, 178(sp)
+; ZVFHMIN32-NEXT: and t2, t2, a2
+; ZVFHMIN32-NEXT: or a4, t2, a4
+; ZVFHMIN32-NEXT: and a6, a6, a1
+; ZVFHMIN32-NEXT: and t0, t0, a2
+; ZVFHMIN32-NEXT: or a6, t0, a6
+; ZVFHMIN32-NEXT: sh a6, 434(sp)
+; ZVFHMIN32-NEXT: lhu a6, 304(sp)
+; ZVFHMIN32-NEXT: lhu t0, 176(sp)
+; ZVFHMIN32-NEXT: vmv.x.s t2, v2
+; ZVFHMIN32-NEXT: and t5, t5, a1
+; ZVFHMIN32-NEXT: and a6, a6, a1
+; ZVFHMIN32-NEXT: and t0, t0, a2
+; ZVFHMIN32-NEXT: or a6, t0, a6
+; ZVFHMIN32-NEXT: sh a6, 432(sp)
+; ZVFHMIN32-NEXT: lhu t0, 302(sp)
+; ZVFHMIN32-NEXT: lhu t6, 174(sp)
+; ZVFHMIN32-NEXT: and a6, t1, a2
+; ZVFHMIN32-NEXT: or a6, a6, t5
+; ZVFHMIN32-NEXT: and t0, t0, a1
+; ZVFHMIN32-NEXT: and t1, t6, a2
+; ZVFHMIN32-NEXT: or t0, t1, t0
+; ZVFHMIN32-NEXT: sh t0, 430(sp)
+; ZVFHMIN32-NEXT: lhu t0, 300(sp)
+; ZVFHMIN32-NEXT: lhu t1, 172(sp)
+; ZVFHMIN32-NEXT: vmv.x.s t5, v4
+; ZVFHMIN32-NEXT: and t4, t4, a1
+; ZVFHMIN32-NEXT: and t0, t0, a1
+; ZVFHMIN32-NEXT: and t1, t1, a2
+; ZVFHMIN32-NEXT: or t0, t1, t0
+; ZVFHMIN32-NEXT: sh t0, 428(sp)
+; ZVFHMIN32-NEXT: lhu t0, 298(sp)
+; ZVFHMIN32-NEXT: lhu t1, 170(sp)
+; ZVFHMIN32-NEXT: and t3, t3, a2
+; ZVFHMIN32-NEXT: or t3, t3, t4
+; ZVFHMIN32-NEXT: and t0, t0, a1
+; ZVFHMIN32-NEXT: and t1, t1, a2
+; ZVFHMIN32-NEXT: or t0, t1, t0
+; ZVFHMIN32-NEXT: sh t0, 426(sp)
+; ZVFHMIN32-NEXT: lhu t0, 296(sp)
+; ZVFHMIN32-NEXT: lhu t1, 168(sp)
+; ZVFHMIN32-NEXT: vmv.x.s t4, v0
+; ZVFHMIN32-NEXT: and t2, t2, a1
+; ZVFHMIN32-NEXT: and t0, t0, a1
+; ZVFHMIN32-NEXT: and t1, t1, a2
+; ZVFHMIN32-NEXT: or t0, t1, t0
+; ZVFHMIN32-NEXT: sh t0, 424(sp)
+; ZVFHMIN32-NEXT: lhu t0, 294(sp)
+; ZVFHMIN32-NEXT: lhu t1, 166(sp)
+; ZVFHMIN32-NEXT: and t5, t5, a2
+; ZVFHMIN32-NEXT: or t2, t5, t2
+; ZVFHMIN32-NEXT: and t0, t0, a1
+; ZVFHMIN32-NEXT: and t1, t1, a2
+; ZVFHMIN32-NEXT: or t0, t1, t0
+; ZVFHMIN32-NEXT: sh t0, 422(sp)
+; ZVFHMIN32-NEXT: lhu t0, 292(sp)
+; ZVFHMIN32-NEXT: lhu t1, 164(sp)
+; ZVFHMIN32-NEXT: vmv.x.s t5, v8
+; ZVFHMIN32-NEXT: and t4, t4, a1
+; ZVFHMIN32-NEXT: and t0, t0, a1
+; ZVFHMIN32-NEXT: and t1, t1, a2
+; ZVFHMIN32-NEXT: or t0, t1, t0
+; ZVFHMIN32-NEXT: sh t0, 420(sp)
+; ZVFHMIN32-NEXT: lhu t0, 290(sp)
+; ZVFHMIN32-NEXT: lhu t1, 162(sp)
+; ZVFHMIN32-NEXT: and t5, t5, a2
+; ZVFHMIN32-NEXT: or t4, t5, t4
+; ZVFHMIN32-NEXT: and t0, t0, a1
+; ZVFHMIN32-NEXT: and t1, t1, a2
+; ZVFHMIN32-NEXT: or t0, t1, t0
+; ZVFHMIN32-NEXT: sh t0, 418(sp)
+; ZVFHMIN32-NEXT: lhu t0, 288(sp)
+; ZVFHMIN32-NEXT: lhu t1, 160(sp)
+; ZVFHMIN32-NEXT: sh a4, 408(sp)
+; ZVFHMIN32-NEXT: sh a5, 410(sp)
+; ZVFHMIN32-NEXT: sh a7, 412(sp)
+; ZVFHMIN32-NEXT: sh a3, 414(sp)
+; ZVFHMIN32-NEXT: sh t4, 400(sp)
+; ZVFHMIN32-NEXT: sh t2, 402(sp)
+; ZVFHMIN32-NEXT: sh t3, 404(sp)
+; ZVFHMIN32-NEXT: sh a6, 406(sp)
+; ZVFHMIN32-NEXT: and a1, t0, a1
+; ZVFHMIN32-NEXT: and a2, t1, a2
+; ZVFHMIN32-NEXT: or a1, a2, a1
+; ZVFHMIN32-NEXT: sh a1, 416(sp)
+; ZVFHMIN32-NEXT: addi a1, sp, 384
+; ZVFHMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN32-NEXT: vle16.v v8, (a1)
+; ZVFHMIN32-NEXT: addi sp, s0, -656
+; ZVFHMIN32-NEXT: .cfi_def_cfa sp, 656
+; ZVFHMIN32-NEXT: lw ra, 652(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s0, 648(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s1, 644(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s2, 640(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s3, 636(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s4, 632(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s5, 628(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s6, 624(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s7, 620(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s8, 616(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s9, 612(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s10, 608(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s11, 604(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: .cfi_restore ra
+; ZVFHMIN32-NEXT: .cfi_restore s0
+; ZVFHMIN32-NEXT: .cfi_restore s1
+; ZVFHMIN32-NEXT: .cfi_restore s2
+; ZVFHMIN32-NEXT: .cfi_restore s3
+; ZVFHMIN32-NEXT: .cfi_restore s4
+; ZVFHMIN32-NEXT: .cfi_restore s5
+; ZVFHMIN32-NEXT: .cfi_restore s6
+; ZVFHMIN32-NEXT: .cfi_restore s7
+; ZVFHMIN32-NEXT: .cfi_restore s8
+; ZVFHMIN32-NEXT: .cfi_restore s9
+; ZVFHMIN32-NEXT: .cfi_restore s10
+; ZVFHMIN32-NEXT: .cfi_restore s11
+; ZVFHMIN32-NEXT: addi sp, sp, 656
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN32-NEXT: ret
+;
+; ZVFHMIN64-LABEL: copysign_v64f16:
+; ZVFHMIN64: # %bb.0:
+; ZVFHMIN64-NEXT: addi sp, sp, -656
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 656
+; ZVFHMIN64-NEXT: sd ra, 648(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s0, 640(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s1, 632(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s2, 624(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s3, 616(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s4, 608(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s5, 600(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s6, 592(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s7, 584(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s8, 576(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s9, 568(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s10, 560(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s11, 552(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: .cfi_offset ra, -8
+; ZVFHMIN64-NEXT: .cfi_offset s0, -16
+; ZVFHMIN64-NEXT: .cfi_offset s1, -24
+; ZVFHMIN64-NEXT: .cfi_offset s2, -32
+; ZVFHMIN64-NEXT: .cfi_offset s3, -40
+; ZVFHMIN64-NEXT: .cfi_offset s4, -48
+; ZVFHMIN64-NEXT: .cfi_offset s5, -56
+; ZVFHMIN64-NEXT: .cfi_offset s6, -64
+; ZVFHMIN64-NEXT: .cfi_offset s7, -72
+; ZVFHMIN64-NEXT: .cfi_offset s8, -80
+; ZVFHMIN64-NEXT: .cfi_offset s9, -88
+; ZVFHMIN64-NEXT: .cfi_offset s10, -96
+; ZVFHMIN64-NEXT: .cfi_offset s11, -104
+; ZVFHMIN64-NEXT: addi s0, sp, 656
+; ZVFHMIN64-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN64-NEXT: csrr a0, vlenb
+; ZVFHMIN64-NEXT: slli a1, a0, 3
+; ZVFHMIN64-NEXT: sub a0, a1, a0
+; ZVFHMIN64-NEXT: sub sp, sp, a0
+; ZVFHMIN64-NEXT: andi sp, sp, -128
+; ZVFHMIN64-NEXT: li a0, 64
+; ZVFHMIN64-NEXT: addi a2, sp, 256
+; ZVFHMIN64-NEXT: addi a4, sp, 128
+; ZVFHMIN64-NEXT: lui a1, 8
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN64-NEXT: vmv.x.s a3, v16
+; ZVFHMIN64-NEXT: vslidedown.vi v24, v16, 7
+; ZVFHMIN64-NEXT: csrr a5, vlenb
+; ZVFHMIN64-NEXT: slli a6, a5, 2
+; ZVFHMIN64-NEXT: add a5, a6, a5
+; ZVFHMIN64-NEXT: add a5, sp, a5
+; ZVFHMIN64-NEXT: addi a5, a5, 544
+; ZVFHMIN64-NEXT: vs1r.v v24, (a5) # vscale x 8-byte Folded Spill
+; ZVFHMIN64-NEXT: vslidedown.vi v24, v16, 6
+; ZVFHMIN64-NEXT: csrr a5, vlenb
+; ZVFHMIN64-NEXT: slli a5, a5, 2
+; ZVFHMIN64-NEXT: add a5, sp, a5
+; ZVFHMIN64-NEXT: addi a5, a5, 544
+; ZVFHMIN64-NEXT: vs1r.v v24, (a5) # vscale x 8-byte Folded Spill
+; ZVFHMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN64-NEXT: vse16.v v16, (a2)
+; ZVFHMIN64-NEXT: vse16.v v8, (a4)
+; ZVFHMIN64-NEXT: lhu a4, 382(sp)
+; ZVFHMIN64-NEXT: lhu a5, 254(sp)
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v16, 5
+; ZVFHMIN64-NEXT: csrr a2, vlenb
+; ZVFHMIN64-NEXT: add a2, sp, a2
+; ZVFHMIN64-NEXT: addi a2, a2, 544
+; ZVFHMIN64-NEXT: vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
+; ZVFHMIN64-NEXT: addi a2, a1, -1
+; ZVFHMIN64-NEXT: and a4, a4, a1
+; ZVFHMIN64-NEXT: and a5, a5, a2
+; ZVFHMIN64-NEXT: or a4, a5, a4
+; ZVFHMIN64-NEXT: sh a4, 510(sp)
+; ZVFHMIN64-NEXT: lhu a4, 380(sp)
+; ZVFHMIN64-NEXT: lhu a5, 252(sp)
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v16, 4
+; ZVFHMIN64-NEXT: addi a6, sp, 544
+; ZVFHMIN64-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v16, 3
+; ZVFHMIN64-NEXT: csrr a6, vlenb
+; ZVFHMIN64-NEXT: slli a6, a6, 1
+; ZVFHMIN64-NEXT: mv a7, a6
+; ZVFHMIN64-NEXT: slli a6, a6, 1
+; ZVFHMIN64-NEXT: add a6, a6, a7
+; ZVFHMIN64-NEXT: add a6, sp, a6
+; ZVFHMIN64-NEXT: addi a6, a6, 544
+; ZVFHMIN64-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
+; ZVFHMIN64-NEXT: and a4, a4, a1
+; ZVFHMIN64-NEXT: and a5, a5, a2
+; ZVFHMIN64-NEXT: or a4, a5, a4
+; ZVFHMIN64-NEXT: sh a4, 508(sp)
+; ZVFHMIN64-NEXT: lhu a4, 378(sp)
+; ZVFHMIN64-NEXT: lhu a5, 250(sp)
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v16, 2
+; ZVFHMIN64-NEXT: csrr a6, vlenb
+; ZVFHMIN64-NEXT: slli a7, a6, 1
+; ZVFHMIN64-NEXT: add a6, a7, a6
+; ZVFHMIN64-NEXT: add a6, sp, a6
+; ZVFHMIN64-NEXT: addi a6, a6, 544
+; ZVFHMIN64-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v16, 1
+; ZVFHMIN64-NEXT: csrr a6, vlenb
+; ZVFHMIN64-NEXT: slli a6, a6, 1
+; ZVFHMIN64-NEXT: add a6, sp, a6
+; ZVFHMIN64-NEXT: addi a6, a6, 544
+; ZVFHMIN64-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
+; ZVFHMIN64-NEXT: and a4, a4, a1
+; ZVFHMIN64-NEXT: and a5, a5, a2
+; ZVFHMIN64-NEXT: or a4, a5, a4
+; ZVFHMIN64-NEXT: sh a4, 506(sp)
+; ZVFHMIN64-NEXT: lhu a4, 376(sp)
+; ZVFHMIN64-NEXT: lhu a5, 248(sp)
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v26, v16, 15
+; ZVFHMIN64-NEXT: vslidedown.vi v28, v16, 14
+; ZVFHMIN64-NEXT: and a4, a4, a1
+; ZVFHMIN64-NEXT: and a5, a5, a2
+; ZVFHMIN64-NEXT: or a4, a5, a4
+; ZVFHMIN64-NEXT: sh a4, 504(sp)
+; ZVFHMIN64-NEXT: lhu a4, 374(sp)
+; ZVFHMIN64-NEXT: lhu a5, 246(sp)
+; ZVFHMIN64-NEXT: vslidedown.vi v30, v16, 13
+; ZVFHMIN64-NEXT: vslidedown.vi v6, v16, 12
+; ZVFHMIN64-NEXT: and a4, a4, a1
+; ZVFHMIN64-NEXT: and a5, a5, a2
+; ZVFHMIN64-NEXT: or a4, a5, a4
+; ZVFHMIN64-NEXT: sh a4, 502(sp)
+; ZVFHMIN64-NEXT: lhu a4, 372(sp)
+; ZVFHMIN64-NEXT: lhu a5, 244(sp)
+; ZVFHMIN64-NEXT: vslidedown.vi v20, v16, 11
+; ZVFHMIN64-NEXT: vslidedown.vi v18, v16, 10
+; ZVFHMIN64-NEXT: vslidedown.vi v2, v16, 9
+; ZVFHMIN64-NEXT: vslidedown.vi v0, v16, 8
+; ZVFHMIN64-NEXT: and a4, a4, a1
+; ZVFHMIN64-NEXT: and a5, a5, a2
+; ZVFHMIN64-NEXT: or a4, a5, a4
+; ZVFHMIN64-NEXT: sh a4, 500(sp)
+; ZVFHMIN64-NEXT: lhu a4, 370(sp)
+; ZVFHMIN64-NEXT: lhu a5, 242(sp)
+; ZVFHMIN64-NEXT: vmv.x.s t3, v8
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v7, v8, 7
+; ZVFHMIN64-NEXT: and a4, a4, a1
+; ZVFHMIN64-NEXT: and a5, a5, a2
+; ZVFHMIN64-NEXT: or a4, a5, a4
+; ZVFHMIN64-NEXT: sh a4, 498(sp)
+; ZVFHMIN64-NEXT: lhu a4, 368(sp)
+; ZVFHMIN64-NEXT: lhu a5, 240(sp)
+; ZVFHMIN64-NEXT: vslidedown.vi v3, v8, 6
+; ZVFHMIN64-NEXT: vslidedown.vi v27, v8, 5
+; ZVFHMIN64-NEXT: vslidedown.vi v21, v8, 4
+; ZVFHMIN64-NEXT: vslidedown.vi v19, v8, 3
+; ZVFHMIN64-NEXT: vslidedown.vi v31, v8, 2
+; ZVFHMIN64-NEXT: vslidedown.vi v29, v8, 1
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 15
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 14
+; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 13
+; ZVFHMIN64-NEXT: vslidedown.vi v24, v8, 12
+; ZVFHMIN64-NEXT: vslidedown.vi v22, v8, 11
+; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 10
+; ZVFHMIN64-NEXT: vslidedown.vi v4, v8, 9
+; ZVFHMIN64-NEXT: vslidedown.vi v8, v8, 8
+; ZVFHMIN64-NEXT: and a4, a4, a1
+; ZVFHMIN64-NEXT: and a5, a5, a2
+; ZVFHMIN64-NEXT: or a4, a5, a4
+; ZVFHMIN64-NEXT: sh a4, 496(sp)
+; ZVFHMIN64-NEXT: lhu a4, 366(sp)
+; ZVFHMIN64-NEXT: lhu a5, 238(sp)
+; ZVFHMIN64-NEXT: vmv.x.s t1, v26
+; ZVFHMIN64-NEXT: vmv.x.s t2, v10
+; ZVFHMIN64-NEXT: and a4, a4, a1
+; ZVFHMIN64-NEXT: and a5, a5, a2
+; ZVFHMIN64-NEXT: or a4, a5, a4
+; ZVFHMIN64-NEXT: sh a4, 494(sp)
+; ZVFHMIN64-NEXT: lhu a4, 364(sp)
+; ZVFHMIN64-NEXT: lhu a5, 236(sp)
+; ZVFHMIN64-NEXT: vmv.x.s t0, v28
+; ZVFHMIN64-NEXT: vmv.x.s a7, v12
+; ZVFHMIN64-NEXT: and a4, a4, a1
+; ZVFHMIN64-NEXT: and a5, a5, a2
+; ZVFHMIN64-NEXT: or a4, a5, a4
+; ZVFHMIN64-NEXT: sh a4, 492(sp)
+; ZVFHMIN64-NEXT: lhu a4, 362(sp)
+; ZVFHMIN64-NEXT: lhu t4, 234(sp)
+; ZVFHMIN64-NEXT: vmv.x.s a6, v30
+; ZVFHMIN64-NEXT: vmv.x.s a5, v14
+; ZVFHMIN64-NEXT: and a4, a4, a1
+; ZVFHMIN64-NEXT: and t4, t4, a2
+; ZVFHMIN64-NEXT: or a4, t4, a4
+; ZVFHMIN64-NEXT: sh a4, 490(sp)
+; ZVFHMIN64-NEXT: lhu t4, 360(sp)
+; ZVFHMIN64-NEXT: lhu t5, 232(sp)
+; ZVFHMIN64-NEXT: vmv.x.s a4, v6
+; ZVFHMIN64-NEXT: csrr t6, vlenb
+; ZVFHMIN64-NEXT: slli s1, t6, 2
+; ZVFHMIN64-NEXT: add t6, s1, t6
+; ZVFHMIN64-NEXT: add t6, sp, t6
+; ZVFHMIN64-NEXT: lh s6, 544(t6) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: and t4, t4, a1
+; ZVFHMIN64-NEXT: and t5, t5, a2
+; ZVFHMIN64-NEXT: or t4, t5, t4
+; ZVFHMIN64-NEXT: sh t4, 488(sp)
+; ZVFHMIN64-NEXT: lhu t5, 358(sp)
+; ZVFHMIN64-NEXT: lhu t6, 230(sp)
+; ZVFHMIN64-NEXT: vmv.x.s s7, v7
+; ZVFHMIN64-NEXT: csrr t4, vlenb
+; ZVFHMIN64-NEXT: slli t4, t4, 2
+; ZVFHMIN64-NEXT: add t4, sp, t4
+; ZVFHMIN64-NEXT: lh t4, 544(t4) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: and t5, t5, a1
+; ZVFHMIN64-NEXT: and t6, t6, a2
+; ZVFHMIN64-NEXT: or t5, t6, t5
+; ZVFHMIN64-NEXT: sh t5, 486(sp)
+; ZVFHMIN64-NEXT: lhu t5, 356(sp)
+; ZVFHMIN64-NEXT: lhu s1, 228(sp)
+; ZVFHMIN64-NEXT: vmv.x.s s4, v3
+; ZVFHMIN64-NEXT: csrr t6, vlenb
+; ZVFHMIN64-NEXT: add t6, sp, t6
+; ZVFHMIN64-NEXT: lh t6, 544(t6) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: and t5, t5, a1
+; ZVFHMIN64-NEXT: and s1, s1, a2
+; ZVFHMIN64-NEXT: or t5, s1, t5
+; ZVFHMIN64-NEXT: sh t5, 484(sp)
+; ZVFHMIN64-NEXT: lhu s2, 354(sp)
+; ZVFHMIN64-NEXT: lhu s3, 226(sp)
+; ZVFHMIN64-NEXT: vmv.x.s s1, v27
+; ZVFHMIN64-NEXT: lh t5, 544(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: and s2, s2, a1
+; ZVFHMIN64-NEXT: and s3, s3, a2
+; ZVFHMIN64-NEXT: or s2, s3, s2
+; ZVFHMIN64-NEXT: sh s2, 482(sp)
+; ZVFHMIN64-NEXT: lhu s2, 352(sp)
+; ZVFHMIN64-NEXT: lhu s3, 224(sp)
+; ZVFHMIN64-NEXT: and a3, a3, a1
+; ZVFHMIN64-NEXT: and t3, t3, a2
+; ZVFHMIN64-NEXT: and s2, s2, a1
+; ZVFHMIN64-NEXT: and s3, s3, a2
+; ZVFHMIN64-NEXT: or s2, s3, s2
+; ZVFHMIN64-NEXT: sh s2, 480(sp)
+; ZVFHMIN64-NEXT: lhu s2, 350(sp)
+; ZVFHMIN64-NEXT: lhu s3, 222(sp)
+; ZVFHMIN64-NEXT: or a3, t3, a3
+; ZVFHMIN64-NEXT: sh a3, 384(sp)
+; ZVFHMIN64-NEXT: and a3, s2, a1
+; ZVFHMIN64-NEXT: and t3, s3, a2
+; ZVFHMIN64-NEXT: or a3, t3, a3
+; ZVFHMIN64-NEXT: sh a3, 478(sp)
+; ZVFHMIN64-NEXT: lhu a3, 348(sp)
+; ZVFHMIN64-NEXT: lhu t3, 220(sp)
+; ZVFHMIN64-NEXT: vmv.x.s s10, v21
+; ZVFHMIN64-NEXT: csrr s2, vlenb
+; ZVFHMIN64-NEXT: slli s2, s2, 1
+; ZVFHMIN64-NEXT: mv s3, s2
+; ZVFHMIN64-NEXT: slli s2, s2, 1
+; ZVFHMIN64-NEXT: add s2, s2, s3
+; ZVFHMIN64-NEXT: add s2, sp, s2
+; ZVFHMIN64-NEXT: lh s8, 544(s2) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: and a3, a3, a1
+; ZVFHMIN64-NEXT: and t3, t3, a2
+; ZVFHMIN64-NEXT: or a3, t3, a3
+; ZVFHMIN64-NEXT: sh a3, 476(sp)
+; ZVFHMIN64-NEXT: lhu a3, 346(sp)
+; ZVFHMIN64-NEXT: lhu t3, 218(sp)
+; ZVFHMIN64-NEXT: vmv.x.s s9, v19
+; ZVFHMIN64-NEXT: csrr s2, vlenb
+; ZVFHMIN64-NEXT: slli s3, s2, 1
+; ZVFHMIN64-NEXT: add s2, s3, s2
+; ZVFHMIN64-NEXT: add s2, sp, s2
+; ZVFHMIN64-NEXT: lh s3, 544(s2) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: and a3, a3, a1
+; ZVFHMIN64-NEXT: and t3, t3, a2
+; ZVFHMIN64-NEXT: or a3, t3, a3
+; ZVFHMIN64-NEXT: sh a3, 474(sp)
+; ZVFHMIN64-NEXT: lhu t3, 344(sp)
+; ZVFHMIN64-NEXT: lhu s2, 216(sp)
+; ZVFHMIN64-NEXT: vmv.x.s s5, v31
+; ZVFHMIN64-NEXT: csrr a3, vlenb
+; ZVFHMIN64-NEXT: slli a3, a3, 1
+; ZVFHMIN64-NEXT: add a3, sp, a3
+; ZVFHMIN64-NEXT: lh a3, 544(a3) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: and t3, t3, a1
+; ZVFHMIN64-NEXT: and s2, s2, a2
+; ZVFHMIN64-NEXT: or t3, s2, t3
+; ZVFHMIN64-NEXT: sh t3, 472(sp)
+; ZVFHMIN64-NEXT: lhu t3, 342(sp)
+; ZVFHMIN64-NEXT: lhu s11, 214(sp)
+; ZVFHMIN64-NEXT: vmv.x.s s2, v29
+; ZVFHMIN64-NEXT: and s6, s6, a1
+; ZVFHMIN64-NEXT: and t3, t3, a1
+; ZVFHMIN64-NEXT: and s11, s11, a2
+; ZVFHMIN64-NEXT: or t3, s11, t3
+; ZVFHMIN64-NEXT: sh t3, 470(sp)
+; ZVFHMIN64-NEXT: lhu s11, 340(sp)
+; ZVFHMIN64-NEXT: lhu ra, 212(sp)
+; ZVFHMIN64-NEXT: and t3, s7, a2
+; ZVFHMIN64-NEXT: or t3, t3, s6
+; ZVFHMIN64-NEXT: and s6, s11, a1
+; ZVFHMIN64-NEXT: and s7, ra, a2
+; ZVFHMIN64-NEXT: or s6, s7, s6
+; ZVFHMIN64-NEXT: sh s6, 468(sp)
+; ZVFHMIN64-NEXT: lhu s6, 338(sp)
+; ZVFHMIN64-NEXT: lhu s7, 210(sp)
+; ZVFHMIN64-NEXT: and t4, t4, a1
+; ZVFHMIN64-NEXT: and s4, s4, a2
+; ZVFHMIN64-NEXT: and s6, s6, a1
+; ZVFHMIN64-NEXT: and s7, s7, a2
+; ZVFHMIN64-NEXT: or s6, s7, s6
+; ZVFHMIN64-NEXT: sh s6, 466(sp)
+; ZVFHMIN64-NEXT: lhu s6, 336(sp)
+; ZVFHMIN64-NEXT: lhu s7, 208(sp)
+; ZVFHMIN64-NEXT: or t4, s4, t4
+; ZVFHMIN64-NEXT: and t6, t6, a1
+; ZVFHMIN64-NEXT: and s4, s6, a1
+; ZVFHMIN64-NEXT: and s6, s7, a2
+; ZVFHMIN64-NEXT: or s4, s6, s4
+; ZVFHMIN64-NEXT: sh s4, 464(sp)
+; ZVFHMIN64-NEXT: lhu s4, 334(sp)
+; ZVFHMIN64-NEXT: lhu s6, 206(sp)
+; ZVFHMIN64-NEXT: and s1, s1, a2
+; ZVFHMIN64-NEXT: or t6, s1, t6
+; ZVFHMIN64-NEXT: and s1, s4, a1
+; ZVFHMIN64-NEXT: and s4, s6, a2
+; ZVFHMIN64-NEXT: or s1, s4, s1
+; ZVFHMIN64-NEXT: sh s1, 462(sp)
+; ZVFHMIN64-NEXT: lhu s1, 332(sp)
+; ZVFHMIN64-NEXT: lhu s4, 204(sp)
+; ZVFHMIN64-NEXT: and t5, t5, a1
+; ZVFHMIN64-NEXT: and s6, s10, a2
+; ZVFHMIN64-NEXT: and s1, s1, a1
+; ZVFHMIN64-NEXT: and s4, s4, a2
+; ZVFHMIN64-NEXT: or s1, s4, s1
+; ZVFHMIN64-NEXT: sh s1, 460(sp)
+; ZVFHMIN64-NEXT: lhu s1, 330(sp)
+; ZVFHMIN64-NEXT: lhu s4, 202(sp)
+; ZVFHMIN64-NEXT: or t5, s6, t5
+; ZVFHMIN64-NEXT: and s6, s8, a1
+; ZVFHMIN64-NEXT: and s1, s1, a1
+; ZVFHMIN64-NEXT: and s4, s4, a2
+; ZVFHMIN64-NEXT: or s1, s4, s1
+; ZVFHMIN64-NEXT: sh s1, 458(sp)
+; ZVFHMIN64-NEXT: lhu s1, 328(sp)
+; ZVFHMIN64-NEXT: lhu s4, 200(sp)
+; ZVFHMIN64-NEXT: and s7, s9, a2
+; ZVFHMIN64-NEXT: or s6, s7, s6
+; ZVFHMIN64-NEXT: and s1, s1, a1
+; ZVFHMIN64-NEXT: and s4, s4, a2
+; ZVFHMIN64-NEXT: or s1, s4, s1
+; ZVFHMIN64-NEXT: sh s1, 456(sp)
+; ZVFHMIN64-NEXT: lhu s1, 326(sp)
+; ZVFHMIN64-NEXT: lhu s4, 198(sp)
+; ZVFHMIN64-NEXT: and s3, s3, a1
+; ZVFHMIN64-NEXT: and s5, s5, a2
+; ZVFHMIN64-NEXT: and s1, s1, a1
+; ZVFHMIN64-NEXT: and s4, s4, a2
+; ZVFHMIN64-NEXT: or s1, s4, s1
+; ZVFHMIN64-NEXT: sh s1, 454(sp)
+; ZVFHMIN64-NEXT: lhu s1, 324(sp)
+; ZVFHMIN64-NEXT: lhu s4, 196(sp)
+; ZVFHMIN64-NEXT: or s3, s5, s3
+; ZVFHMIN64-NEXT: and a3, a3, a1
+; ZVFHMIN64-NEXT: and s1, s1, a1
+; ZVFHMIN64-NEXT: and s4, s4, a2
+; ZVFHMIN64-NEXT: or s1, s4, s1
+; ZVFHMIN64-NEXT: sh s1, 452(sp)
+; ZVFHMIN64-NEXT: lhu s1, 322(sp)
+; ZVFHMIN64-NEXT: lhu s4, 194(sp)
+; ZVFHMIN64-NEXT: and s2, s2, a2
+; ZVFHMIN64-NEXT: or s2, s2, a3
+; ZVFHMIN64-NEXT: and s1, s1, a1
+; ZVFHMIN64-NEXT: and a3, s4, a2
+; ZVFHMIN64-NEXT: or a3, a3, s1
+; ZVFHMIN64-NEXT: sh a3, 450(sp)
+; ZVFHMIN64-NEXT: lhu a3, 320(sp)
+; ZVFHMIN64-NEXT: lhu s1, 192(sp)
+; ZVFHMIN64-NEXT: and t1, t1, a1
+; ZVFHMIN64-NEXT: and t2, t2, a2
+; ZVFHMIN64-NEXT: and a3, a3, a1
+; ZVFHMIN64-NEXT: and s1, s1, a2
+; ZVFHMIN64-NEXT: or a3, s1, a3
+; ZVFHMIN64-NEXT: sh a3, 448(sp)
+; ZVFHMIN64-NEXT: lhu s1, 318(sp)
+; ZVFHMIN64-NEXT: lhu s4, 190(sp)
+; ZVFHMIN64-NEXT: or a3, t2, t1
+; ZVFHMIN64-NEXT: vmv.x.s t2, v24
+; ZVFHMIN64-NEXT: and s1, s1, a1
+; ZVFHMIN64-NEXT: and t1, s4, a2
+; ZVFHMIN64-NEXT: or t1, t1, s1
+; ZVFHMIN64-NEXT: sh t1, 446(sp)
+; ZVFHMIN64-NEXT: lhu t1, 316(sp)
+; ZVFHMIN64-NEXT: lhu s1, 188(sp)
+; ZVFHMIN64-NEXT: sh s2, 386(sp)
+; ZVFHMIN64-NEXT: sh s3, 388(sp)
+; ZVFHMIN64-NEXT: sh s6, 390(sp)
+; ZVFHMIN64-NEXT: sh t5, 392(sp)
+; ZVFHMIN64-NEXT: vmv.x.s t5, v20
+; ZVFHMIN64-NEXT: and t1, t1, a1
+; ZVFHMIN64-NEXT: and s1, s1, a2
+; ZVFHMIN64-NEXT: or s1, s1, t1
+; ZVFHMIN64-NEXT: vmv.x.s t1, v22
+; ZVFHMIN64-NEXT: and t0, t0, a1
+; ZVFHMIN64-NEXT: sh t6, 394(sp)
+; ZVFHMIN64-NEXT: sh t4, 396(sp)
+; ZVFHMIN64-NEXT: sh t3, 398(sp)
+; ZVFHMIN64-NEXT: sh s1, 444(sp)
+; ZVFHMIN64-NEXT: lhu t3, 314(sp)
+; ZVFHMIN64-NEXT: lhu t4, 186(sp)
+; ZVFHMIN64-NEXT: and a7, a7, a2
+; ZVFHMIN64-NEXT: or a7, a7, t0
+; ZVFHMIN64-NEXT: and t0, t3, a1
+; ZVFHMIN64-NEXT: and t3, t4, a2
+; ZVFHMIN64-NEXT: or t0, t3, t0
+; ZVFHMIN64-NEXT: sh t0, 442(sp)
+; ZVFHMIN64-NEXT: lhu t0, 312(sp)
+; ZVFHMIN64-NEXT: lhu t3, 184(sp)
+; ZVFHMIN64-NEXT: vmv.x.s t4, v18
+; ZVFHMIN64-NEXT: and a6, a6, a1
+; ZVFHMIN64-NEXT: and t0, t0, a1
+; ZVFHMIN64-NEXT: and t3, t3, a2
+; ZVFHMIN64-NEXT: or t0, t3, t0
+; ZVFHMIN64-NEXT: sh t0, 440(sp)
+; ZVFHMIN64-NEXT: lhu t0, 310(sp)
+; ZVFHMIN64-NEXT: lhu t3, 182(sp)
+; ZVFHMIN64-NEXT: and a5, a5, a2
+; ZVFHMIN64-NEXT: or a5, a5, a6
+; ZVFHMIN64-NEXT: and a6, t0, a1
+; ZVFHMIN64-NEXT: and t0, t3, a2
+; ZVFHMIN64-NEXT: or a6, t0, a6
+; ZVFHMIN64-NEXT: sh a6, 438(sp)
+; ZVFHMIN64-NEXT: lhu a6, 308(sp)
+; ZVFHMIN64-NEXT: lhu t0, 180(sp)
+; ZVFHMIN64-NEXT: vmv.x.s t3, v16
+; ZVFHMIN64-NEXT: and a4, a4, a1
+; ZVFHMIN64-NEXT: and a6, a6, a1
+; ZVFHMIN64-NEXT: and t0, t0, a2
+; ZVFHMIN64-NEXT: or a6, t0, a6
+; ZVFHMIN64-NEXT: sh a6, 436(sp)
+; ZVFHMIN64-NEXT: lhu a6, 306(sp)
+; ZVFHMIN64-NEXT: lhu t0, 178(sp)
+; ZVFHMIN64-NEXT: and t2, t2, a2
+; ZVFHMIN64-NEXT: or a4, t2, a4
+; ZVFHMIN64-NEXT: and a6, a6, a1
+; ZVFHMIN64-NEXT: and t0, t0, a2
+; ZVFHMIN64-NEXT: or a6, t0, a6
+; ZVFHMIN64-NEXT: sh a6, 434(sp)
+; ZVFHMIN64-NEXT: lhu a6, 304(sp)
+; ZVFHMIN64-NEXT: lhu t0, 176(sp)
+; ZVFHMIN64-NEXT: vmv.x.s t2, v2
+; ZVFHMIN64-NEXT: and t5, t5, a1
+; ZVFHMIN64-NEXT: and a6, a6, a1
+; ZVFHMIN64-NEXT: and t0, t0, a2
+; ZVFHMIN64-NEXT: or a6, t0, a6
+; ZVFHMIN64-NEXT: sh a6, 432(sp)
+; ZVFHMIN64-NEXT: lhu t0, 302(sp)
+; ZVFHMIN64-NEXT: lhu t6, 174(sp)
+; ZVFHMIN64-NEXT: and a6, t1, a2
+; ZVFHMIN64-NEXT: or a6, a6, t5
+; ZVFHMIN64-NEXT: and t0, t0, a1
+; ZVFHMIN64-NEXT: and t1, t6, a2
+; ZVFHMIN64-NEXT: or t0, t1, t0
+; ZVFHMIN64-NEXT: sh t0, 430(sp)
+; ZVFHMIN64-NEXT: lhu t0, 300(sp)
+; ZVFHMIN64-NEXT: lhu t1, 172(sp)
+; ZVFHMIN64-NEXT: vmv.x.s t5, v4
+; ZVFHMIN64-NEXT: and t4, t4, a1
+; ZVFHMIN64-NEXT: and t0, t0, a1
+; ZVFHMIN64-NEXT: and t1, t1, a2
+; ZVFHMIN64-NEXT: or t0, t1, t0
+; ZVFHMIN64-NEXT: sh t0, 428(sp)
+; ZVFHMIN64-NEXT: lhu t0, 298(sp)
+; ZVFHMIN64-NEXT: lhu t1, 170(sp)
+; ZVFHMIN64-NEXT: and t3, t3, a2
+; ZVFHMIN64-NEXT: or t3, t3, t4
+; ZVFHMIN64-NEXT: and t0, t0, a1
+; ZVFHMIN64-NEXT: and t1, t1, a2
+; ZVFHMIN64-NEXT: or t0, t1, t0
+; ZVFHMIN64-NEXT: sh t0, 426(sp)
+; ZVFHMIN64-NEXT: lhu t0, 296(sp)
+; ZVFHMIN64-NEXT: lhu t1, 168(sp)
+; ZVFHMIN64-NEXT: vmv.x.s t4, v0
+; ZVFHMIN64-NEXT: and t2, t2, a1
+; ZVFHMIN64-NEXT: and t0, t0, a1
+; ZVFHMIN64-NEXT: and t1, t1, a2
+; ZVFHMIN64-NEXT: or t0, t1, t0
+; ZVFHMIN64-NEXT: sh t0, 424(sp)
+; ZVFHMIN64-NEXT: lhu t0, 294(sp)
+; ZVFHMIN64-NEXT: lhu t1, 166(sp)
+; ZVFHMIN64-NEXT: and t5, t5, a2
+; ZVFHMIN64-NEXT: or t2, t5, t2
+; ZVFHMIN64-NEXT: and t0, t0, a1
+; ZVFHMIN64-NEXT: and t1, t1, a2
+; ZVFHMIN64-NEXT: or t0, t1, t0
+; ZVFHMIN64-NEXT: sh t0, 422(sp)
+; ZVFHMIN64-NEXT: lhu t0, 292(sp)
+; ZVFHMIN64-NEXT: lhu t1, 164(sp)
+; ZVFHMIN64-NEXT: vmv.x.s t5, v8
+; ZVFHMIN64-NEXT: and t4, t4, a1
+; ZVFHMIN64-NEXT: and t0, t0, a1
+; ZVFHMIN64-NEXT: and t1, t1, a2
+; ZVFHMIN64-NEXT: or t0, t1, t0
+; ZVFHMIN64-NEXT: sh t0, 420(sp)
+; ZVFHMIN64-NEXT: lhu t0, 290(sp)
+; ZVFHMIN64-NEXT: lhu t1, 162(sp)
+; ZVFHMIN64-NEXT: and t5, t5, a2
+; ZVFHMIN64-NEXT: or t4, t5, t4
+; ZVFHMIN64-NEXT: and t0, t0, a1
+; ZVFHMIN64-NEXT: and t1, t1, a2
+; ZVFHMIN64-NEXT: or t0, t1, t0
+; ZVFHMIN64-NEXT: sh t0, 418(sp)
+; ZVFHMIN64-NEXT: lhu t0, 288(sp)
+; ZVFHMIN64-NEXT: lhu t1, 160(sp)
+; ZVFHMIN64-NEXT: sh a4, 408(sp)
+; ZVFHMIN64-NEXT: sh a5, 410(sp)
+; ZVFHMIN64-NEXT: sh a7, 412(sp)
+; ZVFHMIN64-NEXT: sh a3, 414(sp)
+; ZVFHMIN64-NEXT: sh t4, 400(sp)
+; ZVFHMIN64-NEXT: sh t2, 402(sp)
+; ZVFHMIN64-NEXT: sh t3, 404(sp)
+; ZVFHMIN64-NEXT: sh a6, 406(sp)
+; ZVFHMIN64-NEXT: and a1, t0, a1
+; ZVFHMIN64-NEXT: and a2, t1, a2
+; ZVFHMIN64-NEXT: or a1, a2, a1
+; ZVFHMIN64-NEXT: sh a1, 416(sp)
+; ZVFHMIN64-NEXT: addi a1, sp, 384
+; ZVFHMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN64-NEXT: vle16.v v8, (a1)
+; ZVFHMIN64-NEXT: addi sp, s0, -656
+; ZVFHMIN64-NEXT: .cfi_def_cfa sp, 656
+; ZVFHMIN64-NEXT: ld ra, 648(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s0, 640(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s1, 632(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s2, 624(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s3, 616(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s4, 608(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s5, 600(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s6, 592(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s7, 584(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s8, 576(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s9, 568(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s10, 560(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s11, 552(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: .cfi_restore ra
+; ZVFHMIN64-NEXT: .cfi_restore s0
+; ZVFHMIN64-NEXT: .cfi_restore s1
+; ZVFHMIN64-NEXT: .cfi_restore s2
+; ZVFHMIN64-NEXT: .cfi_restore s3
+; ZVFHMIN64-NEXT: .cfi_restore s4
+; ZVFHMIN64-NEXT: .cfi_restore s5
+; ZVFHMIN64-NEXT: .cfi_restore s6
+; ZVFHMIN64-NEXT: .cfi_restore s7
+; ZVFHMIN64-NEXT: .cfi_restore s8
+; ZVFHMIN64-NEXT: .cfi_restore s9
+; ZVFHMIN64-NEXT: .cfi_restore s10
+; ZVFHMIN64-NEXT: .cfi_restore s11
+; ZVFHMIN64-NEXT: addi sp, sp, 656
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN64-NEXT: ret
+ %r = call <64 x half> @llvm.copysign.v64f16(<64 x half> %vm, <64 x half> %vs)
+ ret <64 x half> %r
}
>From 8833fb60788801eeed4e109e427a07f27cd04edd Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Thu, 23 Apr 2026 23:24:44 +0800
Subject: [PATCH 02/10] [llvm][RISCV] Optimize fcopysign for fixed vectors
vsgnj is not available on zvfhmin or zvfbfmin, it's expected to expand
to integer operations instead of unrolling to scalar operations.
General expandFCOPYSIGN already handles that in most of cases except for
fixed vector types that are not promotable, we need to handle them manually same
as what expandFCOPYSIGN does.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 34 +-
.../rvv/fixed-vectors-vcopysign-sdnode.ll | 2254 +----------------
2 files changed, 56 insertions(+), 2232 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4d5013c709e23..d0e8dfc0e3259 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1679,7 +1679,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
}
setOperationAction(ISD::FNEG, VT, Expand);
setOperationAction(ISD::FABS, VT, Expand);
- setOperationAction(ISD::FCOPYSIGN, VT, Expand);
+ setOperationAction(ISD::FCOPYSIGN, VT, Custom);
MVT F32VecVT = MVT::getVectorVT(MVT::f32, VT.getVectorElementCount());
// Don't promote f16 vector operations to f32 if f32 vector type is
// not legal.
@@ -1709,6 +1709,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ZvfbfaOps, VT, Custom);
setOperationAction(ZvfbfaVPOps, VT, Custom);
setCondCodeAction(VFPCCToExpand, VT, Expand);
+ } else {
+ setOperationAction(ISD::FCOPYSIGN, VT, Custom);
}
setOperationAction(
{ISD::VP_MERGE, ISD::VP_SELECT, ISD::VSELECT, ISD::SELECT}, VT,
@@ -7490,6 +7492,28 @@ static SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG,
return DAG.getNode(RISCVISD::FMV_H_X, DL, VT, CopiedSign);
}
+static SDValue expandVectorFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
+ SDLoc DL(Op);
+ MVT VT = Op.getSimpleValueType();
+ MVT IntVT = VT.changeVectorElementTypeToInteger();
+
+ SDValue Mag = DAG.getNode(ISD::BITCAST, DL, IntVT, Op.getOperand(0));
+ SDValue Sign = DAG.getNode(ISD::BITCAST, DL, IntVT, Op.getOperand(1));
+
+ SDValue SignMask = DAG.getConstant(
+ APInt::getSignMask(IntVT.getScalarSizeInBits()), DL, IntVT);
+ SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, Sign, SignMask);
+
+ SDValue ClearSignMask = DAG.getConstant(
+ APInt::getSignedMaxValue(IntVT.getScalarSizeInBits()), DL, IntVT);
+ SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, Mag, ClearSignMask);
+
+ SDValue CopiedSign = DAG.getNode(ISD::OR, DL, IntVT, ClearedSign, SignBit,
+ SDNodeFlags::Disjoint);
+
+ return DAG.getNode(ISD::BITCAST, DL, VT, CopiedSign);
+}
+
/// Get a RISC-V target specified VL op for a given SDNode.
static unsigned getRISCVVLOp(SDValue Op) {
#define OP_CASE(NODE) \
@@ -8951,12 +8975,18 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
SDValue CLMUL = DAG.getNode(ISD::CLMUL, DL, I64VecVT, Op0, Op1);
return DAG.getNode(ISD::TRUNCATE, DL, VT, CLMUL);
}
- case ISD::FCOPYSIGN:
+ case ISD::FCOPYSIGN: {
if (Op.getValueType() == MVT::f16 || Op.getValueType() == MVT::bf16)
return lowerFCOPYSIGN(Op, DAG, Subtarget);
+ MVT EltVT = Op.getSimpleValueType().getVectorElementType();
+ // zvfhmin f16 and zvfbfmin bf16 vectors have no native vfsgnj
+ if ((EltVT == MVT::f16 && !Subtarget.hasVInstructionsF16()) ||
+ (EltVT == MVT::bf16 && !Subtarget.hasVInstructionsBF16()))
+ return expandVectorFCOPYSIGN(Op, DAG);
if (isPromotedOpNeedingSplit(Op, Subtarget, *this))
return SplitVectorOp(Op, DAG);
return lowerToScalableOp(Op, DAG);
+ }
case ISD::STRICT_FADD:
case ISD::STRICT_FSUB:
case ISD::STRICT_FMUL:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-sdnode.ll
index dcbb653a3b7ea..0df4eabe89917 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-sdnode.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+experimental-zvfbfa \
; RUN: -target-abi=ilp32d -verify-machineinstrs < %s \
-; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFA,ZVFHMIN32
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFA
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+experimental-zvfbfa \
; RUN: -target-abi=lp64d -verify-machineinstrs < %s \
-; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFA,ZVFHMIN64
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFA
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s \
-; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFHMIN32,ZVFBFMIN32
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s \
-; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFHMIN64,ZVFBFMIN64
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN
define <2 x bfloat> @copysign_v2bf16(<2 x bfloat> %vm, <2 x bfloat> %vs) {
; ZVFBFA-LABEL: copysign_v2bf16:
@@ -122,1119 +122,16 @@ define <64 x bfloat> @copysign_v64bf16(<64 x bfloat> %vm, <64 x bfloat> %vs) {
; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v16
; ZVFBFA-NEXT: ret
;
-; ZVFBFMIN32-LABEL: copysign_v64bf16:
-; ZVFBFMIN32: # %bb.0:
-; ZVFBFMIN32-NEXT: addi sp, sp, -656
-; ZVFBFMIN32-NEXT: .cfi_def_cfa_offset 656
-; ZVFBFMIN32-NEXT: sw ra, 652(sp) # 4-byte Folded Spill
-; ZVFBFMIN32-NEXT: sw s0, 648(sp) # 4-byte Folded Spill
-; ZVFBFMIN32-NEXT: sw s1, 644(sp) # 4-byte Folded Spill
-; ZVFBFMIN32-NEXT: sw s2, 640(sp) # 4-byte Folded Spill
-; ZVFBFMIN32-NEXT: sw s3, 636(sp) # 4-byte Folded Spill
-; ZVFBFMIN32-NEXT: sw s4, 632(sp) # 4-byte Folded Spill
-; ZVFBFMIN32-NEXT: sw s5, 628(sp) # 4-byte Folded Spill
-; ZVFBFMIN32-NEXT: sw s6, 624(sp) # 4-byte Folded Spill
-; ZVFBFMIN32-NEXT: sw s7, 620(sp) # 4-byte Folded Spill
-; ZVFBFMIN32-NEXT: sw s8, 616(sp) # 4-byte Folded Spill
-; ZVFBFMIN32-NEXT: sw s9, 612(sp) # 4-byte Folded Spill
-; ZVFBFMIN32-NEXT: sw s10, 608(sp) # 4-byte Folded Spill
-; ZVFBFMIN32-NEXT: sw s11, 604(sp) # 4-byte Folded Spill
-; ZVFBFMIN32-NEXT: .cfi_offset ra, -4
-; ZVFBFMIN32-NEXT: .cfi_offset s0, -8
-; ZVFBFMIN32-NEXT: .cfi_offset s1, -12
-; ZVFBFMIN32-NEXT: .cfi_offset s2, -16
-; ZVFBFMIN32-NEXT: .cfi_offset s3, -20
-; ZVFBFMIN32-NEXT: .cfi_offset s4, -24
-; ZVFBFMIN32-NEXT: .cfi_offset s5, -28
-; ZVFBFMIN32-NEXT: .cfi_offset s6, -32
-; ZVFBFMIN32-NEXT: .cfi_offset s7, -36
-; ZVFBFMIN32-NEXT: .cfi_offset s8, -40
-; ZVFBFMIN32-NEXT: .cfi_offset s9, -44
-; ZVFBFMIN32-NEXT: .cfi_offset s10, -48
-; ZVFBFMIN32-NEXT: .cfi_offset s11, -52
-; ZVFBFMIN32-NEXT: addi s0, sp, 656
-; ZVFBFMIN32-NEXT: .cfi_def_cfa s0, 0
-; ZVFBFMIN32-NEXT: csrr a0, vlenb
-; ZVFBFMIN32-NEXT: slli a1, a0, 3
-; ZVFBFMIN32-NEXT: sub a0, a1, a0
-; ZVFBFMIN32-NEXT: sub sp, sp, a0
-; ZVFBFMIN32-NEXT: andi sp, sp, -128
-; ZVFBFMIN32-NEXT: li a0, 64
-; ZVFBFMIN32-NEXT: addi a2, sp, 256
-; ZVFBFMIN32-NEXT: addi a4, sp, 128
-; ZVFBFMIN32-NEXT: lui a1, 8
-; ZVFBFMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFBFMIN32-NEXT: vmv.x.s a3, v16
-; ZVFBFMIN32-NEXT: vslidedown.vi v24, v16, 7
-; ZVFBFMIN32-NEXT: csrr a5, vlenb
-; ZVFBFMIN32-NEXT: slli a6, a5, 2
-; ZVFBFMIN32-NEXT: add a5, a6, a5
-; ZVFBFMIN32-NEXT: add a5, sp, a5
-; ZVFBFMIN32-NEXT: addi a5, a5, 592
-; ZVFBFMIN32-NEXT: vs1r.v v24, (a5) # vscale x 8-byte Folded Spill
-; ZVFBFMIN32-NEXT: vslidedown.vi v24, v16, 6
-; ZVFBFMIN32-NEXT: csrr a5, vlenb
-; ZVFBFMIN32-NEXT: slli a5, a5, 2
-; ZVFBFMIN32-NEXT: add a5, sp, a5
-; ZVFBFMIN32-NEXT: addi a5, a5, 592
-; ZVFBFMIN32-NEXT: vs1r.v v24, (a5) # vscale x 8-byte Folded Spill
-; ZVFBFMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFBFMIN32-NEXT: vse16.v v16, (a2)
-; ZVFBFMIN32-NEXT: vse16.v v8, (a4)
-; ZVFBFMIN32-NEXT: lhu a4, 382(sp)
-; ZVFBFMIN32-NEXT: lhu a5, 254(sp)
-; ZVFBFMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFBFMIN32-NEXT: vslidedown.vi v10, v16, 5
-; ZVFBFMIN32-NEXT: csrr a2, vlenb
-; ZVFBFMIN32-NEXT: add a2, sp, a2
-; ZVFBFMIN32-NEXT: addi a2, a2, 592
-; ZVFBFMIN32-NEXT: vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
-; ZVFBFMIN32-NEXT: addi a2, a1, -1
-; ZVFBFMIN32-NEXT: and a4, a4, a1
-; ZVFBFMIN32-NEXT: and a5, a5, a2
-; ZVFBFMIN32-NEXT: or a4, a5, a4
-; ZVFBFMIN32-NEXT: sh a4, 510(sp)
-; ZVFBFMIN32-NEXT: lhu a4, 380(sp)
-; ZVFBFMIN32-NEXT: lhu a5, 252(sp)
-; ZVFBFMIN32-NEXT: vslidedown.vi v10, v16, 4
-; ZVFBFMIN32-NEXT: addi a6, sp, 592
-; ZVFBFMIN32-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
-; ZVFBFMIN32-NEXT: vslidedown.vi v10, v16, 3
-; ZVFBFMIN32-NEXT: csrr a6, vlenb
-; ZVFBFMIN32-NEXT: slli a6, a6, 1
-; ZVFBFMIN32-NEXT: mv a7, a6
-; ZVFBFMIN32-NEXT: slli a6, a6, 1
-; ZVFBFMIN32-NEXT: add a6, a6, a7
-; ZVFBFMIN32-NEXT: add a6, sp, a6
-; ZVFBFMIN32-NEXT: addi a6, a6, 592
-; ZVFBFMIN32-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
-; ZVFBFMIN32-NEXT: and a4, a4, a1
-; ZVFBFMIN32-NEXT: and a5, a5, a2
-; ZVFBFMIN32-NEXT: or a4, a5, a4
-; ZVFBFMIN32-NEXT: sh a4, 508(sp)
-; ZVFBFMIN32-NEXT: lhu a4, 378(sp)
-; ZVFBFMIN32-NEXT: lhu a5, 250(sp)
-; ZVFBFMIN32-NEXT: vslidedown.vi v10, v16, 2
-; ZVFBFMIN32-NEXT: csrr a6, vlenb
-; ZVFBFMIN32-NEXT: slli a7, a6, 1
-; ZVFBFMIN32-NEXT: add a6, a7, a6
-; ZVFBFMIN32-NEXT: add a6, sp, a6
-; ZVFBFMIN32-NEXT: addi a6, a6, 592
-; ZVFBFMIN32-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
-; ZVFBFMIN32-NEXT: vslidedown.vi v10, v16, 1
-; ZVFBFMIN32-NEXT: csrr a6, vlenb
-; ZVFBFMIN32-NEXT: slli a6, a6, 1
-; ZVFBFMIN32-NEXT: add a6, sp, a6
-; ZVFBFMIN32-NEXT: addi a6, a6, 592
-; ZVFBFMIN32-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
-; ZVFBFMIN32-NEXT: and a4, a4, a1
-; ZVFBFMIN32-NEXT: and a5, a5, a2
-; ZVFBFMIN32-NEXT: or a4, a5, a4
-; ZVFBFMIN32-NEXT: sh a4, 506(sp)
-; ZVFBFMIN32-NEXT: lhu a4, 376(sp)
-; ZVFBFMIN32-NEXT: lhu a5, 248(sp)
-; ZVFBFMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; ZVFBFMIN32-NEXT: vslidedown.vi v26, v16, 15
-; ZVFBFMIN32-NEXT: vslidedown.vi v28, v16, 14
-; ZVFBFMIN32-NEXT: and a4, a4, a1
-; ZVFBFMIN32-NEXT: and a5, a5, a2
-; ZVFBFMIN32-NEXT: or a4, a5, a4
-; ZVFBFMIN32-NEXT: sh a4, 504(sp)
-; ZVFBFMIN32-NEXT: lhu a4, 374(sp)
-; ZVFBFMIN32-NEXT: lhu a5, 246(sp)
-; ZVFBFMIN32-NEXT: vslidedown.vi v30, v16, 13
-; ZVFBFMIN32-NEXT: vslidedown.vi v6, v16, 12
-; ZVFBFMIN32-NEXT: and a4, a4, a1
-; ZVFBFMIN32-NEXT: and a5, a5, a2
-; ZVFBFMIN32-NEXT: or a4, a5, a4
-; ZVFBFMIN32-NEXT: sh a4, 502(sp)
-; ZVFBFMIN32-NEXT: lhu a4, 372(sp)
-; ZVFBFMIN32-NEXT: lhu a5, 244(sp)
-; ZVFBFMIN32-NEXT: vslidedown.vi v20, v16, 11
-; ZVFBFMIN32-NEXT: vslidedown.vi v18, v16, 10
-; ZVFBFMIN32-NEXT: vslidedown.vi v2, v16, 9
-; ZVFBFMIN32-NEXT: vslidedown.vi v0, v16, 8
-; ZVFBFMIN32-NEXT: and a4, a4, a1
-; ZVFBFMIN32-NEXT: and a5, a5, a2
-; ZVFBFMIN32-NEXT: or a4, a5, a4
-; ZVFBFMIN32-NEXT: sh a4, 500(sp)
-; ZVFBFMIN32-NEXT: lhu a4, 370(sp)
-; ZVFBFMIN32-NEXT: lhu a5, 242(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s t3, v8
-; ZVFBFMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFBFMIN32-NEXT: vslidedown.vi v7, v8, 7
-; ZVFBFMIN32-NEXT: and a4, a4, a1
-; ZVFBFMIN32-NEXT: and a5, a5, a2
-; ZVFBFMIN32-NEXT: or a4, a5, a4
-; ZVFBFMIN32-NEXT: sh a4, 498(sp)
-; ZVFBFMIN32-NEXT: lhu a4, 368(sp)
-; ZVFBFMIN32-NEXT: lhu a5, 240(sp)
-; ZVFBFMIN32-NEXT: vslidedown.vi v3, v8, 6
-; ZVFBFMIN32-NEXT: vslidedown.vi v27, v8, 5
-; ZVFBFMIN32-NEXT: vslidedown.vi v21, v8, 4
-; ZVFBFMIN32-NEXT: vslidedown.vi v19, v8, 3
-; ZVFBFMIN32-NEXT: vslidedown.vi v31, v8, 2
-; ZVFBFMIN32-NEXT: vslidedown.vi v29, v8, 1
-; ZVFBFMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; ZVFBFMIN32-NEXT: vslidedown.vi v10, v8, 15
-; ZVFBFMIN32-NEXT: vslidedown.vi v12, v8, 14
-; ZVFBFMIN32-NEXT: vslidedown.vi v14, v8, 13
-; ZVFBFMIN32-NEXT: vslidedown.vi v24, v8, 12
-; ZVFBFMIN32-NEXT: vslidedown.vi v22, v8, 11
-; ZVFBFMIN32-NEXT: vslidedown.vi v16, v8, 10
-; ZVFBFMIN32-NEXT: vslidedown.vi v4, v8, 9
-; ZVFBFMIN32-NEXT: vslidedown.vi v8, v8, 8
-; ZVFBFMIN32-NEXT: and a4, a4, a1
-; ZVFBFMIN32-NEXT: and a5, a5, a2
-; ZVFBFMIN32-NEXT: or a4, a5, a4
-; ZVFBFMIN32-NEXT: sh a4, 496(sp)
-; ZVFBFMIN32-NEXT: lhu a4, 366(sp)
-; ZVFBFMIN32-NEXT: lhu a5, 238(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s t1, v26
-; ZVFBFMIN32-NEXT: vmv.x.s t2, v10
-; ZVFBFMIN32-NEXT: and a4, a4, a1
-; ZVFBFMIN32-NEXT: and a5, a5, a2
-; ZVFBFMIN32-NEXT: or a4, a5, a4
-; ZVFBFMIN32-NEXT: sh a4, 494(sp)
-; ZVFBFMIN32-NEXT: lhu a4, 364(sp)
-; ZVFBFMIN32-NEXT: lhu a5, 236(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s t0, v28
-; ZVFBFMIN32-NEXT: vmv.x.s a7, v12
-; ZVFBFMIN32-NEXT: and a4, a4, a1
-; ZVFBFMIN32-NEXT: and a5, a5, a2
-; ZVFBFMIN32-NEXT: or a4, a5, a4
-; ZVFBFMIN32-NEXT: sh a4, 492(sp)
-; ZVFBFMIN32-NEXT: lhu a4, 362(sp)
-; ZVFBFMIN32-NEXT: lhu t4, 234(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s a6, v30
-; ZVFBFMIN32-NEXT: vmv.x.s a5, v14
-; ZVFBFMIN32-NEXT: and a4, a4, a1
-; ZVFBFMIN32-NEXT: and t4, t4, a2
-; ZVFBFMIN32-NEXT: or a4, t4, a4
-; ZVFBFMIN32-NEXT: sh a4, 490(sp)
-; ZVFBFMIN32-NEXT: lhu t4, 360(sp)
-; ZVFBFMIN32-NEXT: lhu t5, 232(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s a4, v6
-; ZVFBFMIN32-NEXT: csrr t6, vlenb
-; ZVFBFMIN32-NEXT: slli s1, t6, 2
-; ZVFBFMIN32-NEXT: add t6, s1, t6
-; ZVFBFMIN32-NEXT: add t6, sp, t6
-; ZVFBFMIN32-NEXT: lh s6, 592(t6) # 8-byte Folded Reload
-; ZVFBFMIN32-NEXT: and t4, t4, a1
-; ZVFBFMIN32-NEXT: and t5, t5, a2
-; ZVFBFMIN32-NEXT: or t4, t5, t4
-; ZVFBFMIN32-NEXT: sh t4, 488(sp)
-; ZVFBFMIN32-NEXT: lhu t5, 358(sp)
-; ZVFBFMIN32-NEXT: lhu t6, 230(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s s7, v7
-; ZVFBFMIN32-NEXT: csrr t4, vlenb
-; ZVFBFMIN32-NEXT: slli t4, t4, 2
-; ZVFBFMIN32-NEXT: add t4, sp, t4
-; ZVFBFMIN32-NEXT: lh t4, 592(t4) # 8-byte Folded Reload
-; ZVFBFMIN32-NEXT: and t5, t5, a1
-; ZVFBFMIN32-NEXT: and t6, t6, a2
-; ZVFBFMIN32-NEXT: or t5, t6, t5
-; ZVFBFMIN32-NEXT: sh t5, 486(sp)
-; ZVFBFMIN32-NEXT: lhu t5, 356(sp)
-; ZVFBFMIN32-NEXT: lhu s1, 228(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s s4, v3
-; ZVFBFMIN32-NEXT: csrr t6, vlenb
-; ZVFBFMIN32-NEXT: add t6, sp, t6
-; ZVFBFMIN32-NEXT: lh t6, 592(t6) # 8-byte Folded Reload
-; ZVFBFMIN32-NEXT: and t5, t5, a1
-; ZVFBFMIN32-NEXT: and s1, s1, a2
-; ZVFBFMIN32-NEXT: or t5, s1, t5
-; ZVFBFMIN32-NEXT: sh t5, 484(sp)
-; ZVFBFMIN32-NEXT: lhu s2, 354(sp)
-; ZVFBFMIN32-NEXT: lhu s3, 226(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s s1, v27
-; ZVFBFMIN32-NEXT: lh t5, 592(sp) # 8-byte Folded Reload
-; ZVFBFMIN32-NEXT: and s2, s2, a1
-; ZVFBFMIN32-NEXT: and s3, s3, a2
-; ZVFBFMIN32-NEXT: or s2, s3, s2
-; ZVFBFMIN32-NEXT: sh s2, 482(sp)
-; ZVFBFMIN32-NEXT: lhu s2, 352(sp)
-; ZVFBFMIN32-NEXT: lhu s3, 224(sp)
-; ZVFBFMIN32-NEXT: and a3, a3, a1
-; ZVFBFMIN32-NEXT: and t3, t3, a2
-; ZVFBFMIN32-NEXT: and s2, s2, a1
-; ZVFBFMIN32-NEXT: and s3, s3, a2
-; ZVFBFMIN32-NEXT: or s2, s3, s2
-; ZVFBFMIN32-NEXT: sh s2, 480(sp)
-; ZVFBFMIN32-NEXT: lhu s2, 350(sp)
-; ZVFBFMIN32-NEXT: lhu s3, 222(sp)
-; ZVFBFMIN32-NEXT: or a3, t3, a3
-; ZVFBFMIN32-NEXT: sh a3, 384(sp)
-; ZVFBFMIN32-NEXT: and a3, s2, a1
-; ZVFBFMIN32-NEXT: and t3, s3, a2
-; ZVFBFMIN32-NEXT: or a3, t3, a3
-; ZVFBFMIN32-NEXT: sh a3, 478(sp)
-; ZVFBFMIN32-NEXT: lhu a3, 348(sp)
-; ZVFBFMIN32-NEXT: lhu t3, 220(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s s10, v21
-; ZVFBFMIN32-NEXT: csrr s2, vlenb
-; ZVFBFMIN32-NEXT: slli s2, s2, 1
-; ZVFBFMIN32-NEXT: mv s3, s2
-; ZVFBFMIN32-NEXT: slli s2, s2, 1
-; ZVFBFMIN32-NEXT: add s2, s2, s3
-; ZVFBFMIN32-NEXT: add s2, sp, s2
-; ZVFBFMIN32-NEXT: lh s8, 592(s2) # 8-byte Folded Reload
-; ZVFBFMIN32-NEXT: and a3, a3, a1
-; ZVFBFMIN32-NEXT: and t3, t3, a2
-; ZVFBFMIN32-NEXT: or a3, t3, a3
-; ZVFBFMIN32-NEXT: sh a3, 476(sp)
-; ZVFBFMIN32-NEXT: lhu a3, 346(sp)
-; ZVFBFMIN32-NEXT: lhu t3, 218(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s s9, v19
-; ZVFBFMIN32-NEXT: csrr s2, vlenb
-; ZVFBFMIN32-NEXT: slli s3, s2, 1
-; ZVFBFMIN32-NEXT: add s2, s3, s2
-; ZVFBFMIN32-NEXT: add s2, sp, s2
-; ZVFBFMIN32-NEXT: lh s3, 592(s2) # 8-byte Folded Reload
-; ZVFBFMIN32-NEXT: and a3, a3, a1
-; ZVFBFMIN32-NEXT: and t3, t3, a2
-; ZVFBFMIN32-NEXT: or a3, t3, a3
-; ZVFBFMIN32-NEXT: sh a3, 474(sp)
-; ZVFBFMIN32-NEXT: lhu t3, 344(sp)
-; ZVFBFMIN32-NEXT: lhu s2, 216(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s s5, v31
-; ZVFBFMIN32-NEXT: csrr a3, vlenb
-; ZVFBFMIN32-NEXT: slli a3, a3, 1
-; ZVFBFMIN32-NEXT: add a3, sp, a3
-; ZVFBFMIN32-NEXT: lh a3, 592(a3) # 8-byte Folded Reload
-; ZVFBFMIN32-NEXT: and t3, t3, a1
-; ZVFBFMIN32-NEXT: and s2, s2, a2
-; ZVFBFMIN32-NEXT: or t3, s2, t3
-; ZVFBFMIN32-NEXT: sh t3, 472(sp)
-; ZVFBFMIN32-NEXT: lhu t3, 342(sp)
-; ZVFBFMIN32-NEXT: lhu s11, 214(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s s2, v29
-; ZVFBFMIN32-NEXT: and s6, s6, a1
-; ZVFBFMIN32-NEXT: and t3, t3, a1
-; ZVFBFMIN32-NEXT: and s11, s11, a2
-; ZVFBFMIN32-NEXT: or t3, s11, t3
-; ZVFBFMIN32-NEXT: sh t3, 470(sp)
-; ZVFBFMIN32-NEXT: lhu s11, 340(sp)
-; ZVFBFMIN32-NEXT: lhu ra, 212(sp)
-; ZVFBFMIN32-NEXT: and t3, s7, a2
-; ZVFBFMIN32-NEXT: or t3, t3, s6
-; ZVFBFMIN32-NEXT: and s6, s11, a1
-; ZVFBFMIN32-NEXT: and s7, ra, a2
-; ZVFBFMIN32-NEXT: or s6, s7, s6
-; ZVFBFMIN32-NEXT: sh s6, 468(sp)
-; ZVFBFMIN32-NEXT: lhu s6, 338(sp)
-; ZVFBFMIN32-NEXT: lhu s7, 210(sp)
-; ZVFBFMIN32-NEXT: and t4, t4, a1
-; ZVFBFMIN32-NEXT: and s4, s4, a2
-; ZVFBFMIN32-NEXT: and s6, s6, a1
-; ZVFBFMIN32-NEXT: and s7, s7, a2
-; ZVFBFMIN32-NEXT: or s6, s7, s6
-; ZVFBFMIN32-NEXT: sh s6, 466(sp)
-; ZVFBFMIN32-NEXT: lhu s6, 336(sp)
-; ZVFBFMIN32-NEXT: lhu s7, 208(sp)
-; ZVFBFMIN32-NEXT: or t4, s4, t4
-; ZVFBFMIN32-NEXT: and t6, t6, a1
-; ZVFBFMIN32-NEXT: and s4, s6, a1
-; ZVFBFMIN32-NEXT: and s6, s7, a2
-; ZVFBFMIN32-NEXT: or s4, s6, s4
-; ZVFBFMIN32-NEXT: sh s4, 464(sp)
-; ZVFBFMIN32-NEXT: lhu s4, 334(sp)
-; ZVFBFMIN32-NEXT: lhu s6, 206(sp)
-; ZVFBFMIN32-NEXT: and s1, s1, a2
-; ZVFBFMIN32-NEXT: or t6, s1, t6
-; ZVFBFMIN32-NEXT: and s1, s4, a1
-; ZVFBFMIN32-NEXT: and s4, s6, a2
-; ZVFBFMIN32-NEXT: or s1, s4, s1
-; ZVFBFMIN32-NEXT: sh s1, 462(sp)
-; ZVFBFMIN32-NEXT: lhu s1, 332(sp)
-; ZVFBFMIN32-NEXT: lhu s4, 204(sp)
-; ZVFBFMIN32-NEXT: and t5, t5, a1
-; ZVFBFMIN32-NEXT: and s6, s10, a2
-; ZVFBFMIN32-NEXT: and s1, s1, a1
-; ZVFBFMIN32-NEXT: and s4, s4, a2
-; ZVFBFMIN32-NEXT: or s1, s4, s1
-; ZVFBFMIN32-NEXT: sh s1, 460(sp)
-; ZVFBFMIN32-NEXT: lhu s1, 330(sp)
-; ZVFBFMIN32-NEXT: lhu s4, 202(sp)
-; ZVFBFMIN32-NEXT: or t5, s6, t5
-; ZVFBFMIN32-NEXT: and s6, s8, a1
-; ZVFBFMIN32-NEXT: and s1, s1, a1
-; ZVFBFMIN32-NEXT: and s4, s4, a2
-; ZVFBFMIN32-NEXT: or s1, s4, s1
-; ZVFBFMIN32-NEXT: sh s1, 458(sp)
-; ZVFBFMIN32-NEXT: lhu s1, 328(sp)
-; ZVFBFMIN32-NEXT: lhu s4, 200(sp)
-; ZVFBFMIN32-NEXT: and s7, s9, a2
-; ZVFBFMIN32-NEXT: or s6, s7, s6
-; ZVFBFMIN32-NEXT: and s1, s1, a1
-; ZVFBFMIN32-NEXT: and s4, s4, a2
-; ZVFBFMIN32-NEXT: or s1, s4, s1
-; ZVFBFMIN32-NEXT: sh s1, 456(sp)
-; ZVFBFMIN32-NEXT: lhu s1, 326(sp)
-; ZVFBFMIN32-NEXT: lhu s4, 198(sp)
-; ZVFBFMIN32-NEXT: and s3, s3, a1
-; ZVFBFMIN32-NEXT: and s5, s5, a2
-; ZVFBFMIN32-NEXT: and s1, s1, a1
-; ZVFBFMIN32-NEXT: and s4, s4, a2
-; ZVFBFMIN32-NEXT: or s1, s4, s1
-; ZVFBFMIN32-NEXT: sh s1, 454(sp)
-; ZVFBFMIN32-NEXT: lhu s1, 324(sp)
-; ZVFBFMIN32-NEXT: lhu s4, 196(sp)
-; ZVFBFMIN32-NEXT: or s3, s5, s3
-; ZVFBFMIN32-NEXT: and a3, a3, a1
-; ZVFBFMIN32-NEXT: and s1, s1, a1
-; ZVFBFMIN32-NEXT: and s4, s4, a2
-; ZVFBFMIN32-NEXT: or s1, s4, s1
-; ZVFBFMIN32-NEXT: sh s1, 452(sp)
-; ZVFBFMIN32-NEXT: lhu s1, 322(sp)
-; ZVFBFMIN32-NEXT: lhu s4, 194(sp)
-; ZVFBFMIN32-NEXT: and s2, s2, a2
-; ZVFBFMIN32-NEXT: or s2, s2, a3
-; ZVFBFMIN32-NEXT: and s1, s1, a1
-; ZVFBFMIN32-NEXT: and a3, s4, a2
-; ZVFBFMIN32-NEXT: or a3, a3, s1
-; ZVFBFMIN32-NEXT: sh a3, 450(sp)
-; ZVFBFMIN32-NEXT: lhu a3, 320(sp)
-; ZVFBFMIN32-NEXT: lhu s1, 192(sp)
-; ZVFBFMIN32-NEXT: and t1, t1, a1
-; ZVFBFMIN32-NEXT: and t2, t2, a2
-; ZVFBFMIN32-NEXT: and a3, a3, a1
-; ZVFBFMIN32-NEXT: and s1, s1, a2
-; ZVFBFMIN32-NEXT: or a3, s1, a3
-; ZVFBFMIN32-NEXT: sh a3, 448(sp)
-; ZVFBFMIN32-NEXT: lhu s1, 318(sp)
-; ZVFBFMIN32-NEXT: lhu s4, 190(sp)
-; ZVFBFMIN32-NEXT: or a3, t2, t1
-; ZVFBFMIN32-NEXT: vmv.x.s t2, v24
-; ZVFBFMIN32-NEXT: and s1, s1, a1
-; ZVFBFMIN32-NEXT: and t1, s4, a2
-; ZVFBFMIN32-NEXT: or t1, t1, s1
-; ZVFBFMIN32-NEXT: sh t1, 446(sp)
-; ZVFBFMIN32-NEXT: lhu t1, 316(sp)
-; ZVFBFMIN32-NEXT: lhu s1, 188(sp)
-; ZVFBFMIN32-NEXT: sh s2, 386(sp)
-; ZVFBFMIN32-NEXT: sh s3, 388(sp)
-; ZVFBFMIN32-NEXT: sh s6, 390(sp)
-; ZVFBFMIN32-NEXT: sh t5, 392(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s t5, v20
-; ZVFBFMIN32-NEXT: and t1, t1, a1
-; ZVFBFMIN32-NEXT: and s1, s1, a2
-; ZVFBFMIN32-NEXT: or s1, s1, t1
-; ZVFBFMIN32-NEXT: vmv.x.s t1, v22
-; ZVFBFMIN32-NEXT: and t0, t0, a1
-; ZVFBFMIN32-NEXT: sh t6, 394(sp)
-; ZVFBFMIN32-NEXT: sh t4, 396(sp)
-; ZVFBFMIN32-NEXT: sh t3, 398(sp)
-; ZVFBFMIN32-NEXT: sh s1, 444(sp)
-; ZVFBFMIN32-NEXT: lhu t3, 314(sp)
-; ZVFBFMIN32-NEXT: lhu t4, 186(sp)
-; ZVFBFMIN32-NEXT: and a7, a7, a2
-; ZVFBFMIN32-NEXT: or a7, a7, t0
-; ZVFBFMIN32-NEXT: and t0, t3, a1
-; ZVFBFMIN32-NEXT: and t3, t4, a2
-; ZVFBFMIN32-NEXT: or t0, t3, t0
-; ZVFBFMIN32-NEXT: sh t0, 442(sp)
-; ZVFBFMIN32-NEXT: lhu t0, 312(sp)
-; ZVFBFMIN32-NEXT: lhu t3, 184(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s t4, v18
-; ZVFBFMIN32-NEXT: and a6, a6, a1
-; ZVFBFMIN32-NEXT: and t0, t0, a1
-; ZVFBFMIN32-NEXT: and t3, t3, a2
-; ZVFBFMIN32-NEXT: or t0, t3, t0
-; ZVFBFMIN32-NEXT: sh t0, 440(sp)
-; ZVFBFMIN32-NEXT: lhu t0, 310(sp)
-; ZVFBFMIN32-NEXT: lhu t3, 182(sp)
-; ZVFBFMIN32-NEXT: and a5, a5, a2
-; ZVFBFMIN32-NEXT: or a5, a5, a6
-; ZVFBFMIN32-NEXT: and a6, t0, a1
-; ZVFBFMIN32-NEXT: and t0, t3, a2
-; ZVFBFMIN32-NEXT: or a6, t0, a6
-; ZVFBFMIN32-NEXT: sh a6, 438(sp)
-; ZVFBFMIN32-NEXT: lhu a6, 308(sp)
-; ZVFBFMIN32-NEXT: lhu t0, 180(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s t3, v16
-; ZVFBFMIN32-NEXT: and a4, a4, a1
-; ZVFBFMIN32-NEXT: and a6, a6, a1
-; ZVFBFMIN32-NEXT: and t0, t0, a2
-; ZVFBFMIN32-NEXT: or a6, t0, a6
-; ZVFBFMIN32-NEXT: sh a6, 436(sp)
-; ZVFBFMIN32-NEXT: lhu a6, 306(sp)
-; ZVFBFMIN32-NEXT: lhu t0, 178(sp)
-; ZVFBFMIN32-NEXT: and t2, t2, a2
-; ZVFBFMIN32-NEXT: or a4, t2, a4
-; ZVFBFMIN32-NEXT: and a6, a6, a1
-; ZVFBFMIN32-NEXT: and t0, t0, a2
-; ZVFBFMIN32-NEXT: or a6, t0, a6
-; ZVFBFMIN32-NEXT: sh a6, 434(sp)
-; ZVFBFMIN32-NEXT: lhu a6, 304(sp)
-; ZVFBFMIN32-NEXT: lhu t0, 176(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s t2, v2
-; ZVFBFMIN32-NEXT: and t5, t5, a1
-; ZVFBFMIN32-NEXT: and a6, a6, a1
-; ZVFBFMIN32-NEXT: and t0, t0, a2
-; ZVFBFMIN32-NEXT: or a6, t0, a6
-; ZVFBFMIN32-NEXT: sh a6, 432(sp)
-; ZVFBFMIN32-NEXT: lhu t0, 302(sp)
-; ZVFBFMIN32-NEXT: lhu t6, 174(sp)
-; ZVFBFMIN32-NEXT: and a6, t1, a2
-; ZVFBFMIN32-NEXT: or a6, a6, t5
-; ZVFBFMIN32-NEXT: and t0, t0, a1
-; ZVFBFMIN32-NEXT: and t1, t6, a2
-; ZVFBFMIN32-NEXT: or t0, t1, t0
-; ZVFBFMIN32-NEXT: sh t0, 430(sp)
-; ZVFBFMIN32-NEXT: lhu t0, 300(sp)
-; ZVFBFMIN32-NEXT: lhu t1, 172(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s t5, v4
-; ZVFBFMIN32-NEXT: and t4, t4, a1
-; ZVFBFMIN32-NEXT: and t0, t0, a1
-; ZVFBFMIN32-NEXT: and t1, t1, a2
-; ZVFBFMIN32-NEXT: or t0, t1, t0
-; ZVFBFMIN32-NEXT: sh t0, 428(sp)
-; ZVFBFMIN32-NEXT: lhu t0, 298(sp)
-; ZVFBFMIN32-NEXT: lhu t1, 170(sp)
-; ZVFBFMIN32-NEXT: and t3, t3, a2
-; ZVFBFMIN32-NEXT: or t3, t3, t4
-; ZVFBFMIN32-NEXT: and t0, t0, a1
-; ZVFBFMIN32-NEXT: and t1, t1, a2
-; ZVFBFMIN32-NEXT: or t0, t1, t0
-; ZVFBFMIN32-NEXT: sh t0, 426(sp)
-; ZVFBFMIN32-NEXT: lhu t0, 296(sp)
-; ZVFBFMIN32-NEXT: lhu t1, 168(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s t4, v0
-; ZVFBFMIN32-NEXT: and t2, t2, a1
-; ZVFBFMIN32-NEXT: and t0, t0, a1
-; ZVFBFMIN32-NEXT: and t1, t1, a2
-; ZVFBFMIN32-NEXT: or t0, t1, t0
-; ZVFBFMIN32-NEXT: sh t0, 424(sp)
-; ZVFBFMIN32-NEXT: lhu t0, 294(sp)
-; ZVFBFMIN32-NEXT: lhu t1, 166(sp)
-; ZVFBFMIN32-NEXT: and t5, t5, a2
-; ZVFBFMIN32-NEXT: or t2, t5, t2
-; ZVFBFMIN32-NEXT: and t0, t0, a1
-; ZVFBFMIN32-NEXT: and t1, t1, a2
-; ZVFBFMIN32-NEXT: or t0, t1, t0
-; ZVFBFMIN32-NEXT: sh t0, 422(sp)
-; ZVFBFMIN32-NEXT: lhu t0, 292(sp)
-; ZVFBFMIN32-NEXT: lhu t1, 164(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s t5, v8
-; ZVFBFMIN32-NEXT: and t4, t4, a1
-; ZVFBFMIN32-NEXT: and t0, t0, a1
-; ZVFBFMIN32-NEXT: and t1, t1, a2
-; ZVFBFMIN32-NEXT: or t0, t1, t0
-; ZVFBFMIN32-NEXT: sh t0, 420(sp)
-; ZVFBFMIN32-NEXT: lhu t0, 290(sp)
-; ZVFBFMIN32-NEXT: lhu t1, 162(sp)
-; ZVFBFMIN32-NEXT: and t5, t5, a2
-; ZVFBFMIN32-NEXT: or t4, t5, t4
-; ZVFBFMIN32-NEXT: and t0, t0, a1
-; ZVFBFMIN32-NEXT: and t1, t1, a2
-; ZVFBFMIN32-NEXT: or t0, t1, t0
-; ZVFBFMIN32-NEXT: sh t0, 418(sp)
-; ZVFBFMIN32-NEXT: lhu t0, 288(sp)
-; ZVFBFMIN32-NEXT: lhu t1, 160(sp)
-; ZVFBFMIN32-NEXT: sh a4, 408(sp)
-; ZVFBFMIN32-NEXT: sh a5, 410(sp)
-; ZVFBFMIN32-NEXT: sh a7, 412(sp)
-; ZVFBFMIN32-NEXT: sh a3, 414(sp)
-; ZVFBFMIN32-NEXT: sh t4, 400(sp)
-; ZVFBFMIN32-NEXT: sh t2, 402(sp)
-; ZVFBFMIN32-NEXT: sh t3, 404(sp)
-; ZVFBFMIN32-NEXT: sh a6, 406(sp)
-; ZVFBFMIN32-NEXT: and a1, t0, a1
-; ZVFBFMIN32-NEXT: and a2, t1, a2
-; ZVFBFMIN32-NEXT: or a1, a2, a1
-; ZVFBFMIN32-NEXT: sh a1, 416(sp)
-; ZVFBFMIN32-NEXT: addi a1, sp, 384
-; ZVFBFMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFBFMIN32-NEXT: vle16.v v8, (a1)
-; ZVFBFMIN32-NEXT: addi sp, s0, -656
-; ZVFBFMIN32-NEXT: .cfi_def_cfa sp, 656
-; ZVFBFMIN32-NEXT: lw ra, 652(sp) # 4-byte Folded Reload
-; ZVFBFMIN32-NEXT: lw s0, 648(sp) # 4-byte Folded Reload
-; ZVFBFMIN32-NEXT: lw s1, 644(sp) # 4-byte Folded Reload
-; ZVFBFMIN32-NEXT: lw s2, 640(sp) # 4-byte Folded Reload
-; ZVFBFMIN32-NEXT: lw s3, 636(sp) # 4-byte Folded Reload
-; ZVFBFMIN32-NEXT: lw s4, 632(sp) # 4-byte Folded Reload
-; ZVFBFMIN32-NEXT: lw s5, 628(sp) # 4-byte Folded Reload
-; ZVFBFMIN32-NEXT: lw s6, 624(sp) # 4-byte Folded Reload
-; ZVFBFMIN32-NEXT: lw s7, 620(sp) # 4-byte Folded Reload
-; ZVFBFMIN32-NEXT: lw s8, 616(sp) # 4-byte Folded Reload
-; ZVFBFMIN32-NEXT: lw s9, 612(sp) # 4-byte Folded Reload
-; ZVFBFMIN32-NEXT: lw s10, 608(sp) # 4-byte Folded Reload
-; ZVFBFMIN32-NEXT: lw s11, 604(sp) # 4-byte Folded Reload
-; ZVFBFMIN32-NEXT: .cfi_restore ra
-; ZVFBFMIN32-NEXT: .cfi_restore s0
-; ZVFBFMIN32-NEXT: .cfi_restore s1
-; ZVFBFMIN32-NEXT: .cfi_restore s2
-; ZVFBFMIN32-NEXT: .cfi_restore s3
-; ZVFBFMIN32-NEXT: .cfi_restore s4
-; ZVFBFMIN32-NEXT: .cfi_restore s5
-; ZVFBFMIN32-NEXT: .cfi_restore s6
-; ZVFBFMIN32-NEXT: .cfi_restore s7
-; ZVFBFMIN32-NEXT: .cfi_restore s8
-; ZVFBFMIN32-NEXT: .cfi_restore s9
-; ZVFBFMIN32-NEXT: .cfi_restore s10
-; ZVFBFMIN32-NEXT: .cfi_restore s11
-; ZVFBFMIN32-NEXT: addi sp, sp, 656
-; ZVFBFMIN32-NEXT: .cfi_def_cfa_offset 0
-; ZVFBFMIN32-NEXT: ret
-;
-; ZVFBFMIN64-LABEL: copysign_v64bf16:
-; ZVFBFMIN64: # %bb.0:
-; ZVFBFMIN64-NEXT: addi sp, sp, -656
-; ZVFBFMIN64-NEXT: .cfi_def_cfa_offset 656
-; ZVFBFMIN64-NEXT: sd ra, 648(sp) # 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: sd s0, 640(sp) # 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: sd s1, 632(sp) # 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: sd s2, 624(sp) # 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: sd s3, 616(sp) # 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: sd s4, 608(sp) # 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: sd s5, 600(sp) # 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: sd s6, 592(sp) # 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: sd s7, 584(sp) # 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: sd s8, 576(sp) # 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: sd s9, 568(sp) # 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: sd s10, 560(sp) # 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: sd s11, 552(sp) # 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: .cfi_offset ra, -8
-; ZVFBFMIN64-NEXT: .cfi_offset s0, -16
-; ZVFBFMIN64-NEXT: .cfi_offset s1, -24
-; ZVFBFMIN64-NEXT: .cfi_offset s2, -32
-; ZVFBFMIN64-NEXT: .cfi_offset s3, -40
-; ZVFBFMIN64-NEXT: .cfi_offset s4, -48
-; ZVFBFMIN64-NEXT: .cfi_offset s5, -56
-; ZVFBFMIN64-NEXT: .cfi_offset s6, -64
-; ZVFBFMIN64-NEXT: .cfi_offset s7, -72
-; ZVFBFMIN64-NEXT: .cfi_offset s8, -80
-; ZVFBFMIN64-NEXT: .cfi_offset s9, -88
-; ZVFBFMIN64-NEXT: .cfi_offset s10, -96
-; ZVFBFMIN64-NEXT: .cfi_offset s11, -104
-; ZVFBFMIN64-NEXT: addi s0, sp, 656
-; ZVFBFMIN64-NEXT: .cfi_def_cfa s0, 0
-; ZVFBFMIN64-NEXT: csrr a0, vlenb
-; ZVFBFMIN64-NEXT: slli a1, a0, 3
-; ZVFBFMIN64-NEXT: sub a0, a1, a0
-; ZVFBFMIN64-NEXT: sub sp, sp, a0
-; ZVFBFMIN64-NEXT: andi sp, sp, -128
-; ZVFBFMIN64-NEXT: li a0, 64
-; ZVFBFMIN64-NEXT: addi a2, sp, 256
-; ZVFBFMIN64-NEXT: addi a4, sp, 128
-; ZVFBFMIN64-NEXT: lui a1, 8
-; ZVFBFMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFBFMIN64-NEXT: vmv.x.s a3, v16
-; ZVFBFMIN64-NEXT: vslidedown.vi v24, v16, 7
-; ZVFBFMIN64-NEXT: csrr a5, vlenb
-; ZVFBFMIN64-NEXT: slli a6, a5, 2
-; ZVFBFMIN64-NEXT: add a5, a6, a5
-; ZVFBFMIN64-NEXT: add a5, sp, a5
-; ZVFBFMIN64-NEXT: addi a5, a5, 544
-; ZVFBFMIN64-NEXT: vs1r.v v24, (a5) # vscale x 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: vslidedown.vi v24, v16, 6
-; ZVFBFMIN64-NEXT: csrr a5, vlenb
-; ZVFBFMIN64-NEXT: slli a5, a5, 2
-; ZVFBFMIN64-NEXT: add a5, sp, a5
-; ZVFBFMIN64-NEXT: addi a5, a5, 544
-; ZVFBFMIN64-NEXT: vs1r.v v24, (a5) # vscale x 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFBFMIN64-NEXT: vse16.v v16, (a2)
-; ZVFBFMIN64-NEXT: vse16.v v8, (a4)
-; ZVFBFMIN64-NEXT: lhu a4, 382(sp)
-; ZVFBFMIN64-NEXT: lhu a5, 254(sp)
-; ZVFBFMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFBFMIN64-NEXT: vslidedown.vi v10, v16, 5
-; ZVFBFMIN64-NEXT: csrr a2, vlenb
-; ZVFBFMIN64-NEXT: add a2, sp, a2
-; ZVFBFMIN64-NEXT: addi a2, a2, 544
-; ZVFBFMIN64-NEXT: vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: addi a2, a1, -1
-; ZVFBFMIN64-NEXT: and a4, a4, a1
-; ZVFBFMIN64-NEXT: and a5, a5, a2
-; ZVFBFMIN64-NEXT: or a4, a5, a4
-; ZVFBFMIN64-NEXT: sh a4, 510(sp)
-; ZVFBFMIN64-NEXT: lhu a4, 380(sp)
-; ZVFBFMIN64-NEXT: lhu a5, 252(sp)
-; ZVFBFMIN64-NEXT: vslidedown.vi v10, v16, 4
-; ZVFBFMIN64-NEXT: addi a6, sp, 544
-; ZVFBFMIN64-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: vslidedown.vi v10, v16, 3
-; ZVFBFMIN64-NEXT: csrr a6, vlenb
-; ZVFBFMIN64-NEXT: slli a6, a6, 1
-; ZVFBFMIN64-NEXT: mv a7, a6
-; ZVFBFMIN64-NEXT: slli a6, a6, 1
-; ZVFBFMIN64-NEXT: add a6, a6, a7
-; ZVFBFMIN64-NEXT: add a6, sp, a6
-; ZVFBFMIN64-NEXT: addi a6, a6, 544
-; ZVFBFMIN64-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: and a4, a4, a1
-; ZVFBFMIN64-NEXT: and a5, a5, a2
-; ZVFBFMIN64-NEXT: or a4, a5, a4
-; ZVFBFMIN64-NEXT: sh a4, 508(sp)
-; ZVFBFMIN64-NEXT: lhu a4, 378(sp)
-; ZVFBFMIN64-NEXT: lhu a5, 250(sp)
-; ZVFBFMIN64-NEXT: vslidedown.vi v10, v16, 2
-; ZVFBFMIN64-NEXT: csrr a6, vlenb
-; ZVFBFMIN64-NEXT: slli a7, a6, 1
-; ZVFBFMIN64-NEXT: add a6, a7, a6
-; ZVFBFMIN64-NEXT: add a6, sp, a6
-; ZVFBFMIN64-NEXT: addi a6, a6, 544
-; ZVFBFMIN64-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: vslidedown.vi v10, v16, 1
-; ZVFBFMIN64-NEXT: csrr a6, vlenb
-; ZVFBFMIN64-NEXT: slli a6, a6, 1
-; ZVFBFMIN64-NEXT: add a6, sp, a6
-; ZVFBFMIN64-NEXT: addi a6, a6, 544
-; ZVFBFMIN64-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: and a4, a4, a1
-; ZVFBFMIN64-NEXT: and a5, a5, a2
-; ZVFBFMIN64-NEXT: or a4, a5, a4
-; ZVFBFMIN64-NEXT: sh a4, 506(sp)
-; ZVFBFMIN64-NEXT: lhu a4, 376(sp)
-; ZVFBFMIN64-NEXT: lhu a5, 248(sp)
-; ZVFBFMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; ZVFBFMIN64-NEXT: vslidedown.vi v26, v16, 15
-; ZVFBFMIN64-NEXT: vslidedown.vi v28, v16, 14
-; ZVFBFMIN64-NEXT: and a4, a4, a1
-; ZVFBFMIN64-NEXT: and a5, a5, a2
-; ZVFBFMIN64-NEXT: or a4, a5, a4
-; ZVFBFMIN64-NEXT: sh a4, 504(sp)
-; ZVFBFMIN64-NEXT: lhu a4, 374(sp)
-; ZVFBFMIN64-NEXT: lhu a5, 246(sp)
-; ZVFBFMIN64-NEXT: vslidedown.vi v30, v16, 13
-; ZVFBFMIN64-NEXT: vslidedown.vi v6, v16, 12
-; ZVFBFMIN64-NEXT: and a4, a4, a1
-; ZVFBFMIN64-NEXT: and a5, a5, a2
-; ZVFBFMIN64-NEXT: or a4, a5, a4
-; ZVFBFMIN64-NEXT: sh a4, 502(sp)
-; ZVFBFMIN64-NEXT: lhu a4, 372(sp)
-; ZVFBFMIN64-NEXT: lhu a5, 244(sp)
-; ZVFBFMIN64-NEXT: vslidedown.vi v20, v16, 11
-; ZVFBFMIN64-NEXT: vslidedown.vi v18, v16, 10
-; ZVFBFMIN64-NEXT: vslidedown.vi v2, v16, 9
-; ZVFBFMIN64-NEXT: vslidedown.vi v0, v16, 8
-; ZVFBFMIN64-NEXT: and a4, a4, a1
-; ZVFBFMIN64-NEXT: and a5, a5, a2
-; ZVFBFMIN64-NEXT: or a4, a5, a4
-; ZVFBFMIN64-NEXT: sh a4, 500(sp)
-; ZVFBFMIN64-NEXT: lhu a4, 370(sp)
-; ZVFBFMIN64-NEXT: lhu a5, 242(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s t3, v8
-; ZVFBFMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFBFMIN64-NEXT: vslidedown.vi v7, v8, 7
-; ZVFBFMIN64-NEXT: and a4, a4, a1
-; ZVFBFMIN64-NEXT: and a5, a5, a2
-; ZVFBFMIN64-NEXT: or a4, a5, a4
-; ZVFBFMIN64-NEXT: sh a4, 498(sp)
-; ZVFBFMIN64-NEXT: lhu a4, 368(sp)
-; ZVFBFMIN64-NEXT: lhu a5, 240(sp)
-; ZVFBFMIN64-NEXT: vslidedown.vi v3, v8, 6
-; ZVFBFMIN64-NEXT: vslidedown.vi v27, v8, 5
-; ZVFBFMIN64-NEXT: vslidedown.vi v21, v8, 4
-; ZVFBFMIN64-NEXT: vslidedown.vi v19, v8, 3
-; ZVFBFMIN64-NEXT: vslidedown.vi v31, v8, 2
-; ZVFBFMIN64-NEXT: vslidedown.vi v29, v8, 1
-; ZVFBFMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; ZVFBFMIN64-NEXT: vslidedown.vi v10, v8, 15
-; ZVFBFMIN64-NEXT: vslidedown.vi v12, v8, 14
-; ZVFBFMIN64-NEXT: vslidedown.vi v14, v8, 13
-; ZVFBFMIN64-NEXT: vslidedown.vi v24, v8, 12
-; ZVFBFMIN64-NEXT: vslidedown.vi v22, v8, 11
-; ZVFBFMIN64-NEXT: vslidedown.vi v16, v8, 10
-; ZVFBFMIN64-NEXT: vslidedown.vi v4, v8, 9
-; ZVFBFMIN64-NEXT: vslidedown.vi v8, v8, 8
-; ZVFBFMIN64-NEXT: and a4, a4, a1
-; ZVFBFMIN64-NEXT: and a5, a5, a2
-; ZVFBFMIN64-NEXT: or a4, a5, a4
-; ZVFBFMIN64-NEXT: sh a4, 496(sp)
-; ZVFBFMIN64-NEXT: lhu a4, 366(sp)
-; ZVFBFMIN64-NEXT: lhu a5, 238(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s t1, v26
-; ZVFBFMIN64-NEXT: vmv.x.s t2, v10
-; ZVFBFMIN64-NEXT: and a4, a4, a1
-; ZVFBFMIN64-NEXT: and a5, a5, a2
-; ZVFBFMIN64-NEXT: or a4, a5, a4
-; ZVFBFMIN64-NEXT: sh a4, 494(sp)
-; ZVFBFMIN64-NEXT: lhu a4, 364(sp)
-; ZVFBFMIN64-NEXT: lhu a5, 236(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s t0, v28
-; ZVFBFMIN64-NEXT: vmv.x.s a7, v12
-; ZVFBFMIN64-NEXT: and a4, a4, a1
-; ZVFBFMIN64-NEXT: and a5, a5, a2
-; ZVFBFMIN64-NEXT: or a4, a5, a4
-; ZVFBFMIN64-NEXT: sh a4, 492(sp)
-; ZVFBFMIN64-NEXT: lhu a4, 362(sp)
-; ZVFBFMIN64-NEXT: lhu t4, 234(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s a6, v30
-; ZVFBFMIN64-NEXT: vmv.x.s a5, v14
-; ZVFBFMIN64-NEXT: and a4, a4, a1
-; ZVFBFMIN64-NEXT: and t4, t4, a2
-; ZVFBFMIN64-NEXT: or a4, t4, a4
-; ZVFBFMIN64-NEXT: sh a4, 490(sp)
-; ZVFBFMIN64-NEXT: lhu t4, 360(sp)
-; ZVFBFMIN64-NEXT: lhu t5, 232(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s a4, v6
-; ZVFBFMIN64-NEXT: csrr t6, vlenb
-; ZVFBFMIN64-NEXT: slli s1, t6, 2
-; ZVFBFMIN64-NEXT: add t6, s1, t6
-; ZVFBFMIN64-NEXT: add t6, sp, t6
-; ZVFBFMIN64-NEXT: lh s6, 544(t6) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: and t4, t4, a1
-; ZVFBFMIN64-NEXT: and t5, t5, a2
-; ZVFBFMIN64-NEXT: or t4, t5, t4
-; ZVFBFMIN64-NEXT: sh t4, 488(sp)
-; ZVFBFMIN64-NEXT: lhu t5, 358(sp)
-; ZVFBFMIN64-NEXT: lhu t6, 230(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s s7, v7
-; ZVFBFMIN64-NEXT: csrr t4, vlenb
-; ZVFBFMIN64-NEXT: slli t4, t4, 2
-; ZVFBFMIN64-NEXT: add t4, sp, t4
-; ZVFBFMIN64-NEXT: lh t4, 544(t4) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: and t5, t5, a1
-; ZVFBFMIN64-NEXT: and t6, t6, a2
-; ZVFBFMIN64-NEXT: or t5, t6, t5
-; ZVFBFMIN64-NEXT: sh t5, 486(sp)
-; ZVFBFMIN64-NEXT: lhu t5, 356(sp)
-; ZVFBFMIN64-NEXT: lhu s1, 228(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s s4, v3
-; ZVFBFMIN64-NEXT: csrr t6, vlenb
-; ZVFBFMIN64-NEXT: add t6, sp, t6
-; ZVFBFMIN64-NEXT: lh t6, 544(t6) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: and t5, t5, a1
-; ZVFBFMIN64-NEXT: and s1, s1, a2
-; ZVFBFMIN64-NEXT: or t5, s1, t5
-; ZVFBFMIN64-NEXT: sh t5, 484(sp)
-; ZVFBFMIN64-NEXT: lhu s2, 354(sp)
-; ZVFBFMIN64-NEXT: lhu s3, 226(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s s1, v27
-; ZVFBFMIN64-NEXT: lh t5, 544(sp) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: and s2, s2, a1
-; ZVFBFMIN64-NEXT: and s3, s3, a2
-; ZVFBFMIN64-NEXT: or s2, s3, s2
-; ZVFBFMIN64-NEXT: sh s2, 482(sp)
-; ZVFBFMIN64-NEXT: lhu s2, 352(sp)
-; ZVFBFMIN64-NEXT: lhu s3, 224(sp)
-; ZVFBFMIN64-NEXT: and a3, a3, a1
-; ZVFBFMIN64-NEXT: and t3, t3, a2
-; ZVFBFMIN64-NEXT: and s2, s2, a1
-; ZVFBFMIN64-NEXT: and s3, s3, a2
-; ZVFBFMIN64-NEXT: or s2, s3, s2
-; ZVFBFMIN64-NEXT: sh s2, 480(sp)
-; ZVFBFMIN64-NEXT: lhu s2, 350(sp)
-; ZVFBFMIN64-NEXT: lhu s3, 222(sp)
-; ZVFBFMIN64-NEXT: or a3, t3, a3
-; ZVFBFMIN64-NEXT: sh a3, 384(sp)
-; ZVFBFMIN64-NEXT: and a3, s2, a1
-; ZVFBFMIN64-NEXT: and t3, s3, a2
-; ZVFBFMIN64-NEXT: or a3, t3, a3
-; ZVFBFMIN64-NEXT: sh a3, 478(sp)
-; ZVFBFMIN64-NEXT: lhu a3, 348(sp)
-; ZVFBFMIN64-NEXT: lhu t3, 220(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s s10, v21
-; ZVFBFMIN64-NEXT: csrr s2, vlenb
-; ZVFBFMIN64-NEXT: slli s2, s2, 1
-; ZVFBFMIN64-NEXT: mv s3, s2
-; ZVFBFMIN64-NEXT: slli s2, s2, 1
-; ZVFBFMIN64-NEXT: add s2, s2, s3
-; ZVFBFMIN64-NEXT: add s2, sp, s2
-; ZVFBFMIN64-NEXT: lh s8, 544(s2) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: and a3, a3, a1
-; ZVFBFMIN64-NEXT: and t3, t3, a2
-; ZVFBFMIN64-NEXT: or a3, t3, a3
-; ZVFBFMIN64-NEXT: sh a3, 476(sp)
-; ZVFBFMIN64-NEXT: lhu a3, 346(sp)
-; ZVFBFMIN64-NEXT: lhu t3, 218(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s s9, v19
-; ZVFBFMIN64-NEXT: csrr s2, vlenb
-; ZVFBFMIN64-NEXT: slli s3, s2, 1
-; ZVFBFMIN64-NEXT: add s2, s3, s2
-; ZVFBFMIN64-NEXT: add s2, sp, s2
-; ZVFBFMIN64-NEXT: lh s3, 544(s2) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: and a3, a3, a1
-; ZVFBFMIN64-NEXT: and t3, t3, a2
-; ZVFBFMIN64-NEXT: or a3, t3, a3
-; ZVFBFMIN64-NEXT: sh a3, 474(sp)
-; ZVFBFMIN64-NEXT: lhu t3, 344(sp)
-; ZVFBFMIN64-NEXT: lhu s2, 216(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s s5, v31
-; ZVFBFMIN64-NEXT: csrr a3, vlenb
-; ZVFBFMIN64-NEXT: slli a3, a3, 1
-; ZVFBFMIN64-NEXT: add a3, sp, a3
-; ZVFBFMIN64-NEXT: lh a3, 544(a3) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: and t3, t3, a1
-; ZVFBFMIN64-NEXT: and s2, s2, a2
-; ZVFBFMIN64-NEXT: or t3, s2, t3
-; ZVFBFMIN64-NEXT: sh t3, 472(sp)
-; ZVFBFMIN64-NEXT: lhu t3, 342(sp)
-; ZVFBFMIN64-NEXT: lhu s11, 214(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s s2, v29
-; ZVFBFMIN64-NEXT: and s6, s6, a1
-; ZVFBFMIN64-NEXT: and t3, t3, a1
-; ZVFBFMIN64-NEXT: and s11, s11, a2
-; ZVFBFMIN64-NEXT: or t3, s11, t3
-; ZVFBFMIN64-NEXT: sh t3, 470(sp)
-; ZVFBFMIN64-NEXT: lhu s11, 340(sp)
-; ZVFBFMIN64-NEXT: lhu ra, 212(sp)
-; ZVFBFMIN64-NEXT: and t3, s7, a2
-; ZVFBFMIN64-NEXT: or t3, t3, s6
-; ZVFBFMIN64-NEXT: and s6, s11, a1
-; ZVFBFMIN64-NEXT: and s7, ra, a2
-; ZVFBFMIN64-NEXT: or s6, s7, s6
-; ZVFBFMIN64-NEXT: sh s6, 468(sp)
-; ZVFBFMIN64-NEXT: lhu s6, 338(sp)
-; ZVFBFMIN64-NEXT: lhu s7, 210(sp)
-; ZVFBFMIN64-NEXT: and t4, t4, a1
-; ZVFBFMIN64-NEXT: and s4, s4, a2
-; ZVFBFMIN64-NEXT: and s6, s6, a1
-; ZVFBFMIN64-NEXT: and s7, s7, a2
-; ZVFBFMIN64-NEXT: or s6, s7, s6
-; ZVFBFMIN64-NEXT: sh s6, 466(sp)
-; ZVFBFMIN64-NEXT: lhu s6, 336(sp)
-; ZVFBFMIN64-NEXT: lhu s7, 208(sp)
-; ZVFBFMIN64-NEXT: or t4, s4, t4
-; ZVFBFMIN64-NEXT: and t6, t6, a1
-; ZVFBFMIN64-NEXT: and s4, s6, a1
-; ZVFBFMIN64-NEXT: and s6, s7, a2
-; ZVFBFMIN64-NEXT: or s4, s6, s4
-; ZVFBFMIN64-NEXT: sh s4, 464(sp)
-; ZVFBFMIN64-NEXT: lhu s4, 334(sp)
-; ZVFBFMIN64-NEXT: lhu s6, 206(sp)
-; ZVFBFMIN64-NEXT: and s1, s1, a2
-; ZVFBFMIN64-NEXT: or t6, s1, t6
-; ZVFBFMIN64-NEXT: and s1, s4, a1
-; ZVFBFMIN64-NEXT: and s4, s6, a2
-; ZVFBFMIN64-NEXT: or s1, s4, s1
-; ZVFBFMIN64-NEXT: sh s1, 462(sp)
-; ZVFBFMIN64-NEXT: lhu s1, 332(sp)
-; ZVFBFMIN64-NEXT: lhu s4, 204(sp)
-; ZVFBFMIN64-NEXT: and t5, t5, a1
-; ZVFBFMIN64-NEXT: and s6, s10, a2
-; ZVFBFMIN64-NEXT: and s1, s1, a1
-; ZVFBFMIN64-NEXT: and s4, s4, a2
-; ZVFBFMIN64-NEXT: or s1, s4, s1
-; ZVFBFMIN64-NEXT: sh s1, 460(sp)
-; ZVFBFMIN64-NEXT: lhu s1, 330(sp)
-; ZVFBFMIN64-NEXT: lhu s4, 202(sp)
-; ZVFBFMIN64-NEXT: or t5, s6, t5
-; ZVFBFMIN64-NEXT: and s6, s8, a1
-; ZVFBFMIN64-NEXT: and s1, s1, a1
-; ZVFBFMIN64-NEXT: and s4, s4, a2
-; ZVFBFMIN64-NEXT: or s1, s4, s1
-; ZVFBFMIN64-NEXT: sh s1, 458(sp)
-; ZVFBFMIN64-NEXT: lhu s1, 328(sp)
-; ZVFBFMIN64-NEXT: lhu s4, 200(sp)
-; ZVFBFMIN64-NEXT: and s7, s9, a2
-; ZVFBFMIN64-NEXT: or s6, s7, s6
-; ZVFBFMIN64-NEXT: and s1, s1, a1
-; ZVFBFMIN64-NEXT: and s4, s4, a2
-; ZVFBFMIN64-NEXT: or s1, s4, s1
-; ZVFBFMIN64-NEXT: sh s1, 456(sp)
-; ZVFBFMIN64-NEXT: lhu s1, 326(sp)
-; ZVFBFMIN64-NEXT: lhu s4, 198(sp)
-; ZVFBFMIN64-NEXT: and s3, s3, a1
-; ZVFBFMIN64-NEXT: and s5, s5, a2
-; ZVFBFMIN64-NEXT: and s1, s1, a1
-; ZVFBFMIN64-NEXT: and s4, s4, a2
-; ZVFBFMIN64-NEXT: or s1, s4, s1
-; ZVFBFMIN64-NEXT: sh s1, 454(sp)
-; ZVFBFMIN64-NEXT: lhu s1, 324(sp)
-; ZVFBFMIN64-NEXT: lhu s4, 196(sp)
-; ZVFBFMIN64-NEXT: or s3, s5, s3
-; ZVFBFMIN64-NEXT: and a3, a3, a1
-; ZVFBFMIN64-NEXT: and s1, s1, a1
-; ZVFBFMIN64-NEXT: and s4, s4, a2
-; ZVFBFMIN64-NEXT: or s1, s4, s1
-; ZVFBFMIN64-NEXT: sh s1, 452(sp)
-; ZVFBFMIN64-NEXT: lhu s1, 322(sp)
-; ZVFBFMIN64-NEXT: lhu s4, 194(sp)
-; ZVFBFMIN64-NEXT: and s2, s2, a2
-; ZVFBFMIN64-NEXT: or s2, s2, a3
-; ZVFBFMIN64-NEXT: and s1, s1, a1
-; ZVFBFMIN64-NEXT: and a3, s4, a2
-; ZVFBFMIN64-NEXT: or a3, a3, s1
-; ZVFBFMIN64-NEXT: sh a3, 450(sp)
-; ZVFBFMIN64-NEXT: lhu a3, 320(sp)
-; ZVFBFMIN64-NEXT: lhu s1, 192(sp)
-; ZVFBFMIN64-NEXT: and t1, t1, a1
-; ZVFBFMIN64-NEXT: and t2, t2, a2
-; ZVFBFMIN64-NEXT: and a3, a3, a1
-; ZVFBFMIN64-NEXT: and s1, s1, a2
-; ZVFBFMIN64-NEXT: or a3, s1, a3
-; ZVFBFMIN64-NEXT: sh a3, 448(sp)
-; ZVFBFMIN64-NEXT: lhu s1, 318(sp)
-; ZVFBFMIN64-NEXT: lhu s4, 190(sp)
-; ZVFBFMIN64-NEXT: or a3, t2, t1
-; ZVFBFMIN64-NEXT: vmv.x.s t2, v24
-; ZVFBFMIN64-NEXT: and s1, s1, a1
-; ZVFBFMIN64-NEXT: and t1, s4, a2
-; ZVFBFMIN64-NEXT: or t1, t1, s1
-; ZVFBFMIN64-NEXT: sh t1, 446(sp)
-; ZVFBFMIN64-NEXT: lhu t1, 316(sp)
-; ZVFBFMIN64-NEXT: lhu s1, 188(sp)
-; ZVFBFMIN64-NEXT: sh s2, 386(sp)
-; ZVFBFMIN64-NEXT: sh s3, 388(sp)
-; ZVFBFMIN64-NEXT: sh s6, 390(sp)
-; ZVFBFMIN64-NEXT: sh t5, 392(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s t5, v20
-; ZVFBFMIN64-NEXT: and t1, t1, a1
-; ZVFBFMIN64-NEXT: and s1, s1, a2
-; ZVFBFMIN64-NEXT: or s1, s1, t1
-; ZVFBFMIN64-NEXT: vmv.x.s t1, v22
-; ZVFBFMIN64-NEXT: and t0, t0, a1
-; ZVFBFMIN64-NEXT: sh t6, 394(sp)
-; ZVFBFMIN64-NEXT: sh t4, 396(sp)
-; ZVFBFMIN64-NEXT: sh t3, 398(sp)
-; ZVFBFMIN64-NEXT: sh s1, 444(sp)
-; ZVFBFMIN64-NEXT: lhu t3, 314(sp)
-; ZVFBFMIN64-NEXT: lhu t4, 186(sp)
-; ZVFBFMIN64-NEXT: and a7, a7, a2
-; ZVFBFMIN64-NEXT: or a7, a7, t0
-; ZVFBFMIN64-NEXT: and t0, t3, a1
-; ZVFBFMIN64-NEXT: and t3, t4, a2
-; ZVFBFMIN64-NEXT: or t0, t3, t0
-; ZVFBFMIN64-NEXT: sh t0, 442(sp)
-; ZVFBFMIN64-NEXT: lhu t0, 312(sp)
-; ZVFBFMIN64-NEXT: lhu t3, 184(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s t4, v18
-; ZVFBFMIN64-NEXT: and a6, a6, a1
-; ZVFBFMIN64-NEXT: and t0, t0, a1
-; ZVFBFMIN64-NEXT: and t3, t3, a2
-; ZVFBFMIN64-NEXT: or t0, t3, t0
-; ZVFBFMIN64-NEXT: sh t0, 440(sp)
-; ZVFBFMIN64-NEXT: lhu t0, 310(sp)
-; ZVFBFMIN64-NEXT: lhu t3, 182(sp)
-; ZVFBFMIN64-NEXT: and a5, a5, a2
-; ZVFBFMIN64-NEXT: or a5, a5, a6
-; ZVFBFMIN64-NEXT: and a6, t0, a1
-; ZVFBFMIN64-NEXT: and t0, t3, a2
-; ZVFBFMIN64-NEXT: or a6, t0, a6
-; ZVFBFMIN64-NEXT: sh a6, 438(sp)
-; ZVFBFMIN64-NEXT: lhu a6, 308(sp)
-; ZVFBFMIN64-NEXT: lhu t0, 180(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s t3, v16
-; ZVFBFMIN64-NEXT: and a4, a4, a1
-; ZVFBFMIN64-NEXT: and a6, a6, a1
-; ZVFBFMIN64-NEXT: and t0, t0, a2
-; ZVFBFMIN64-NEXT: or a6, t0, a6
-; ZVFBFMIN64-NEXT: sh a6, 436(sp)
-; ZVFBFMIN64-NEXT: lhu a6, 306(sp)
-; ZVFBFMIN64-NEXT: lhu t0, 178(sp)
-; ZVFBFMIN64-NEXT: and t2, t2, a2
-; ZVFBFMIN64-NEXT: or a4, t2, a4
-; ZVFBFMIN64-NEXT: and a6, a6, a1
-; ZVFBFMIN64-NEXT: and t0, t0, a2
-; ZVFBFMIN64-NEXT: or a6, t0, a6
-; ZVFBFMIN64-NEXT: sh a6, 434(sp)
-; ZVFBFMIN64-NEXT: lhu a6, 304(sp)
-; ZVFBFMIN64-NEXT: lhu t0, 176(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s t2, v2
-; ZVFBFMIN64-NEXT: and t5, t5, a1
-; ZVFBFMIN64-NEXT: and a6, a6, a1
-; ZVFBFMIN64-NEXT: and t0, t0, a2
-; ZVFBFMIN64-NEXT: or a6, t0, a6
-; ZVFBFMIN64-NEXT: sh a6, 432(sp)
-; ZVFBFMIN64-NEXT: lhu t0, 302(sp)
-; ZVFBFMIN64-NEXT: lhu t6, 174(sp)
-; ZVFBFMIN64-NEXT: and a6, t1, a2
-; ZVFBFMIN64-NEXT: or a6, a6, t5
-; ZVFBFMIN64-NEXT: and t0, t0, a1
-; ZVFBFMIN64-NEXT: and t1, t6, a2
-; ZVFBFMIN64-NEXT: or t0, t1, t0
-; ZVFBFMIN64-NEXT: sh t0, 430(sp)
-; ZVFBFMIN64-NEXT: lhu t0, 300(sp)
-; ZVFBFMIN64-NEXT: lhu t1, 172(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s t5, v4
-; ZVFBFMIN64-NEXT: and t4, t4, a1
-; ZVFBFMIN64-NEXT: and t0, t0, a1
-; ZVFBFMIN64-NEXT: and t1, t1, a2
-; ZVFBFMIN64-NEXT: or t0, t1, t0
-; ZVFBFMIN64-NEXT: sh t0, 428(sp)
-; ZVFBFMIN64-NEXT: lhu t0, 298(sp)
-; ZVFBFMIN64-NEXT: lhu t1, 170(sp)
-; ZVFBFMIN64-NEXT: and t3, t3, a2
-; ZVFBFMIN64-NEXT: or t3, t3, t4
-; ZVFBFMIN64-NEXT: and t0, t0, a1
-; ZVFBFMIN64-NEXT: and t1, t1, a2
-; ZVFBFMIN64-NEXT: or t0, t1, t0
-; ZVFBFMIN64-NEXT: sh t0, 426(sp)
-; ZVFBFMIN64-NEXT: lhu t0, 296(sp)
-; ZVFBFMIN64-NEXT: lhu t1, 168(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s t4, v0
-; ZVFBFMIN64-NEXT: and t2, t2, a1
-; ZVFBFMIN64-NEXT: and t0, t0, a1
-; ZVFBFMIN64-NEXT: and t1, t1, a2
-; ZVFBFMIN64-NEXT: or t0, t1, t0
-; ZVFBFMIN64-NEXT: sh t0, 424(sp)
-; ZVFBFMIN64-NEXT: lhu t0, 294(sp)
-; ZVFBFMIN64-NEXT: lhu t1, 166(sp)
-; ZVFBFMIN64-NEXT: and t5, t5, a2
-; ZVFBFMIN64-NEXT: or t2, t5, t2
-; ZVFBFMIN64-NEXT: and t0, t0, a1
-; ZVFBFMIN64-NEXT: and t1, t1, a2
-; ZVFBFMIN64-NEXT: or t0, t1, t0
-; ZVFBFMIN64-NEXT: sh t0, 422(sp)
-; ZVFBFMIN64-NEXT: lhu t0, 292(sp)
-; ZVFBFMIN64-NEXT: lhu t1, 164(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s t5, v8
-; ZVFBFMIN64-NEXT: and t4, t4, a1
-; ZVFBFMIN64-NEXT: and t0, t0, a1
-; ZVFBFMIN64-NEXT: and t1, t1, a2
-; ZVFBFMIN64-NEXT: or t0, t1, t0
-; ZVFBFMIN64-NEXT: sh t0, 420(sp)
-; ZVFBFMIN64-NEXT: lhu t0, 290(sp)
-; ZVFBFMIN64-NEXT: lhu t1, 162(sp)
-; ZVFBFMIN64-NEXT: and t5, t5, a2
-; ZVFBFMIN64-NEXT: or t4, t5, t4
-; ZVFBFMIN64-NEXT: and t0, t0, a1
-; ZVFBFMIN64-NEXT: and t1, t1, a2
-; ZVFBFMIN64-NEXT: or t0, t1, t0
-; ZVFBFMIN64-NEXT: sh t0, 418(sp)
-; ZVFBFMIN64-NEXT: lhu t0, 288(sp)
-; ZVFBFMIN64-NEXT: lhu t1, 160(sp)
-; ZVFBFMIN64-NEXT: sh a4, 408(sp)
-; ZVFBFMIN64-NEXT: sh a5, 410(sp)
-; ZVFBFMIN64-NEXT: sh a7, 412(sp)
-; ZVFBFMIN64-NEXT: sh a3, 414(sp)
-; ZVFBFMIN64-NEXT: sh t4, 400(sp)
-; ZVFBFMIN64-NEXT: sh t2, 402(sp)
-; ZVFBFMIN64-NEXT: sh t3, 404(sp)
-; ZVFBFMIN64-NEXT: sh a6, 406(sp)
-; ZVFBFMIN64-NEXT: and a1, t0, a1
-; ZVFBFMIN64-NEXT: and a2, t1, a2
-; ZVFBFMIN64-NEXT: or a1, a2, a1
-; ZVFBFMIN64-NEXT: sh a1, 416(sp)
-; ZVFBFMIN64-NEXT: addi a1, sp, 384
-; ZVFBFMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFBFMIN64-NEXT: vle16.v v8, (a1)
-; ZVFBFMIN64-NEXT: addi sp, s0, -656
-; ZVFBFMIN64-NEXT: .cfi_def_cfa sp, 656
-; ZVFBFMIN64-NEXT: ld ra, 648(sp) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: ld s0, 640(sp) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: ld s1, 632(sp) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: ld s2, 624(sp) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: ld s3, 616(sp) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: ld s4, 608(sp) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: ld s5, 600(sp) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: ld s6, 592(sp) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: ld s7, 584(sp) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: ld s8, 576(sp) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: ld s9, 568(sp) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: ld s10, 560(sp) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: ld s11, 552(sp) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: .cfi_restore ra
-; ZVFBFMIN64-NEXT: .cfi_restore s0
-; ZVFBFMIN64-NEXT: .cfi_restore s1
-; ZVFBFMIN64-NEXT: .cfi_restore s2
-; ZVFBFMIN64-NEXT: .cfi_restore s3
-; ZVFBFMIN64-NEXT: .cfi_restore s4
-; ZVFBFMIN64-NEXT: .cfi_restore s5
-; ZVFBFMIN64-NEXT: .cfi_restore s6
-; ZVFBFMIN64-NEXT: .cfi_restore s7
-; ZVFBFMIN64-NEXT: .cfi_restore s8
-; ZVFBFMIN64-NEXT: .cfi_restore s9
-; ZVFBFMIN64-NEXT: .cfi_restore s10
-; ZVFBFMIN64-NEXT: .cfi_restore s11
-; ZVFBFMIN64-NEXT: addi sp, sp, 656
-; ZVFBFMIN64-NEXT: .cfi_def_cfa_offset 0
-; ZVFBFMIN64-NEXT: ret
+; ZVFBFMIN-LABEL: copysign_v64bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: li a0, 64
+; ZVFBFMIN-NEXT: lui a1, 8
+; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v16, v16, a1
+; ZVFBFMIN-NEXT: addi a1, a1, -1
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a1
+; ZVFBFMIN-NEXT: vor.vv v8, v8, v16
+; ZVFBFMIN-NEXT: ret
%r = call <64 x bfloat> @llvm.copysign.v64bf16(<64 x bfloat> %vm, <64 x bfloat> %vs)
ret <64 x bfloat> %r
}
@@ -1283,1119 +180,16 @@ define <32 x half> @copysign_v32f16(<32 x half> %vm, <32 x half> %vs) {
}
define <64 x half> @copysign_v64f16(<64 x half> %vm, <64 x half> %vs) {
-; ZVFHMIN32-LABEL: copysign_v64f16:
-; ZVFHMIN32: # %bb.0:
-; ZVFHMIN32-NEXT: addi sp, sp, -656
-; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 656
-; ZVFHMIN32-NEXT: sw ra, 652(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT: sw s0, 648(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT: sw s1, 644(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT: sw s2, 640(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT: sw s3, 636(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT: sw s4, 632(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT: sw s5, 628(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT: sw s6, 624(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT: sw s7, 620(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT: sw s8, 616(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT: sw s9, 612(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT: sw s10, 608(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT: sw s11, 604(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT: .cfi_offset ra, -4
-; ZVFHMIN32-NEXT: .cfi_offset s0, -8
-; ZVFHMIN32-NEXT: .cfi_offset s1, -12
-; ZVFHMIN32-NEXT: .cfi_offset s2, -16
-; ZVFHMIN32-NEXT: .cfi_offset s3, -20
-; ZVFHMIN32-NEXT: .cfi_offset s4, -24
-; ZVFHMIN32-NEXT: .cfi_offset s5, -28
-; ZVFHMIN32-NEXT: .cfi_offset s6, -32
-; ZVFHMIN32-NEXT: .cfi_offset s7, -36
-; ZVFHMIN32-NEXT: .cfi_offset s8, -40
-; ZVFHMIN32-NEXT: .cfi_offset s9, -44
-; ZVFHMIN32-NEXT: .cfi_offset s10, -48
-; ZVFHMIN32-NEXT: .cfi_offset s11, -52
-; ZVFHMIN32-NEXT: addi s0, sp, 656
-; ZVFHMIN32-NEXT: .cfi_def_cfa s0, 0
-; ZVFHMIN32-NEXT: csrr a0, vlenb
-; ZVFHMIN32-NEXT: slli a1, a0, 3
-; ZVFHMIN32-NEXT: sub a0, a1, a0
-; ZVFHMIN32-NEXT: sub sp, sp, a0
-; ZVFHMIN32-NEXT: andi sp, sp, -128
-; ZVFHMIN32-NEXT: li a0, 64
-; ZVFHMIN32-NEXT: addi a2, sp, 256
-; ZVFHMIN32-NEXT: addi a4, sp, 128
-; ZVFHMIN32-NEXT: lui a1, 8
-; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN32-NEXT: vmv.x.s a3, v16
-; ZVFHMIN32-NEXT: vslidedown.vi v24, v16, 7
-; ZVFHMIN32-NEXT: csrr a5, vlenb
-; ZVFHMIN32-NEXT: slli a6, a5, 2
-; ZVFHMIN32-NEXT: add a5, a6, a5
-; ZVFHMIN32-NEXT: add a5, sp, a5
-; ZVFHMIN32-NEXT: addi a5, a5, 592
-; ZVFHMIN32-NEXT: vs1r.v v24, (a5) # vscale x 8-byte Folded Spill
-; ZVFHMIN32-NEXT: vslidedown.vi v24, v16, 6
-; ZVFHMIN32-NEXT: csrr a5, vlenb
-; ZVFHMIN32-NEXT: slli a5, a5, 2
-; ZVFHMIN32-NEXT: add a5, sp, a5
-; ZVFHMIN32-NEXT: addi a5, a5, 592
-; ZVFHMIN32-NEXT: vs1r.v v24, (a5) # vscale x 8-byte Folded Spill
-; ZVFHMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN32-NEXT: vse16.v v16, (a2)
-; ZVFHMIN32-NEXT: vse16.v v8, (a4)
-; ZVFHMIN32-NEXT: lhu a4, 382(sp)
-; ZVFHMIN32-NEXT: lhu a5, 254(sp)
-; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN32-NEXT: vslidedown.vi v10, v16, 5
-; ZVFHMIN32-NEXT: csrr a2, vlenb
-; ZVFHMIN32-NEXT: add a2, sp, a2
-; ZVFHMIN32-NEXT: addi a2, a2, 592
-; ZVFHMIN32-NEXT: vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN32-NEXT: addi a2, a1, -1
-; ZVFHMIN32-NEXT: and a4, a4, a1
-; ZVFHMIN32-NEXT: and a5, a5, a2
-; ZVFHMIN32-NEXT: or a4, a5, a4
-; ZVFHMIN32-NEXT: sh a4, 510(sp)
-; ZVFHMIN32-NEXT: lhu a4, 380(sp)
-; ZVFHMIN32-NEXT: lhu a5, 252(sp)
-; ZVFHMIN32-NEXT: vslidedown.vi v10, v16, 4
-; ZVFHMIN32-NEXT: addi a6, sp, 592
-; ZVFHMIN32-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
-; ZVFHMIN32-NEXT: vslidedown.vi v10, v16, 3
-; ZVFHMIN32-NEXT: csrr a6, vlenb
-; ZVFHMIN32-NEXT: slli a6, a6, 1
-; ZVFHMIN32-NEXT: mv a7, a6
-; ZVFHMIN32-NEXT: slli a6, a6, 1
-; ZVFHMIN32-NEXT: add a6, a6, a7
-; ZVFHMIN32-NEXT: add a6, sp, a6
-; ZVFHMIN32-NEXT: addi a6, a6, 592
-; ZVFHMIN32-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
-; ZVFHMIN32-NEXT: and a4, a4, a1
-; ZVFHMIN32-NEXT: and a5, a5, a2
-; ZVFHMIN32-NEXT: or a4, a5, a4
-; ZVFHMIN32-NEXT: sh a4, 508(sp)
-; ZVFHMIN32-NEXT: lhu a4, 378(sp)
-; ZVFHMIN32-NEXT: lhu a5, 250(sp)
-; ZVFHMIN32-NEXT: vslidedown.vi v10, v16, 2
-; ZVFHMIN32-NEXT: csrr a6, vlenb
-; ZVFHMIN32-NEXT: slli a7, a6, 1
-; ZVFHMIN32-NEXT: add a6, a7, a6
-; ZVFHMIN32-NEXT: add a6, sp, a6
-; ZVFHMIN32-NEXT: addi a6, a6, 592
-; ZVFHMIN32-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
-; ZVFHMIN32-NEXT: vslidedown.vi v10, v16, 1
-; ZVFHMIN32-NEXT: csrr a6, vlenb
-; ZVFHMIN32-NEXT: slli a6, a6, 1
-; ZVFHMIN32-NEXT: add a6, sp, a6
-; ZVFHMIN32-NEXT: addi a6, a6, 592
-; ZVFHMIN32-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
-; ZVFHMIN32-NEXT: and a4, a4, a1
-; ZVFHMIN32-NEXT: and a5, a5, a2
-; ZVFHMIN32-NEXT: or a4, a5, a4
-; ZVFHMIN32-NEXT: sh a4, 506(sp)
-; ZVFHMIN32-NEXT: lhu a4, 376(sp)
-; ZVFHMIN32-NEXT: lhu a5, 248(sp)
-; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; ZVFHMIN32-NEXT: vslidedown.vi v26, v16, 15
-; ZVFHMIN32-NEXT: vslidedown.vi v28, v16, 14
-; ZVFHMIN32-NEXT: and a4, a4, a1
-; ZVFHMIN32-NEXT: and a5, a5, a2
-; ZVFHMIN32-NEXT: or a4, a5, a4
-; ZVFHMIN32-NEXT: sh a4, 504(sp)
-; ZVFHMIN32-NEXT: lhu a4, 374(sp)
-; ZVFHMIN32-NEXT: lhu a5, 246(sp)
-; ZVFHMIN32-NEXT: vslidedown.vi v30, v16, 13
-; ZVFHMIN32-NEXT: vslidedown.vi v6, v16, 12
-; ZVFHMIN32-NEXT: and a4, a4, a1
-; ZVFHMIN32-NEXT: and a5, a5, a2
-; ZVFHMIN32-NEXT: or a4, a5, a4
-; ZVFHMIN32-NEXT: sh a4, 502(sp)
-; ZVFHMIN32-NEXT: lhu a4, 372(sp)
-; ZVFHMIN32-NEXT: lhu a5, 244(sp)
-; ZVFHMIN32-NEXT: vslidedown.vi v20, v16, 11
-; ZVFHMIN32-NEXT: vslidedown.vi v18, v16, 10
-; ZVFHMIN32-NEXT: vslidedown.vi v2, v16, 9
-; ZVFHMIN32-NEXT: vslidedown.vi v0, v16, 8
-; ZVFHMIN32-NEXT: and a4, a4, a1
-; ZVFHMIN32-NEXT: and a5, a5, a2
-; ZVFHMIN32-NEXT: or a4, a5, a4
-; ZVFHMIN32-NEXT: sh a4, 500(sp)
-; ZVFHMIN32-NEXT: lhu a4, 370(sp)
-; ZVFHMIN32-NEXT: lhu a5, 242(sp)
-; ZVFHMIN32-NEXT: vmv.x.s t3, v8
-; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN32-NEXT: vslidedown.vi v7, v8, 7
-; ZVFHMIN32-NEXT: and a4, a4, a1
-; ZVFHMIN32-NEXT: and a5, a5, a2
-; ZVFHMIN32-NEXT: or a4, a5, a4
-; ZVFHMIN32-NEXT: sh a4, 498(sp)
-; ZVFHMIN32-NEXT: lhu a4, 368(sp)
-; ZVFHMIN32-NEXT: lhu a5, 240(sp)
-; ZVFHMIN32-NEXT: vslidedown.vi v3, v8, 6
-; ZVFHMIN32-NEXT: vslidedown.vi v27, v8, 5
-; ZVFHMIN32-NEXT: vslidedown.vi v21, v8, 4
-; ZVFHMIN32-NEXT: vslidedown.vi v19, v8, 3
-; ZVFHMIN32-NEXT: vslidedown.vi v31, v8, 2
-; ZVFHMIN32-NEXT: vslidedown.vi v29, v8, 1
-; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 15
-; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 14
-; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 13
-; ZVFHMIN32-NEXT: vslidedown.vi v24, v8, 12
-; ZVFHMIN32-NEXT: vslidedown.vi v22, v8, 11
-; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 10
-; ZVFHMIN32-NEXT: vslidedown.vi v4, v8, 9
-; ZVFHMIN32-NEXT: vslidedown.vi v8, v8, 8
-; ZVFHMIN32-NEXT: and a4, a4, a1
-; ZVFHMIN32-NEXT: and a5, a5, a2
-; ZVFHMIN32-NEXT: or a4, a5, a4
-; ZVFHMIN32-NEXT: sh a4, 496(sp)
-; ZVFHMIN32-NEXT: lhu a4, 366(sp)
-; ZVFHMIN32-NEXT: lhu a5, 238(sp)
-; ZVFHMIN32-NEXT: vmv.x.s t1, v26
-; ZVFHMIN32-NEXT: vmv.x.s t2, v10
-; ZVFHMIN32-NEXT: and a4, a4, a1
-; ZVFHMIN32-NEXT: and a5, a5, a2
-; ZVFHMIN32-NEXT: or a4, a5, a4
-; ZVFHMIN32-NEXT: sh a4, 494(sp)
-; ZVFHMIN32-NEXT: lhu a4, 364(sp)
-; ZVFHMIN32-NEXT: lhu a5, 236(sp)
-; ZVFHMIN32-NEXT: vmv.x.s t0, v28
-; ZVFHMIN32-NEXT: vmv.x.s a7, v12
-; ZVFHMIN32-NEXT: and a4, a4, a1
-; ZVFHMIN32-NEXT: and a5, a5, a2
-; ZVFHMIN32-NEXT: or a4, a5, a4
-; ZVFHMIN32-NEXT: sh a4, 492(sp)
-; ZVFHMIN32-NEXT: lhu a4, 362(sp)
-; ZVFHMIN32-NEXT: lhu t4, 234(sp)
-; ZVFHMIN32-NEXT: vmv.x.s a6, v30
-; ZVFHMIN32-NEXT: vmv.x.s a5, v14
-; ZVFHMIN32-NEXT: and a4, a4, a1
-; ZVFHMIN32-NEXT: and t4, t4, a2
-; ZVFHMIN32-NEXT: or a4, t4, a4
-; ZVFHMIN32-NEXT: sh a4, 490(sp)
-; ZVFHMIN32-NEXT: lhu t4, 360(sp)
-; ZVFHMIN32-NEXT: lhu t5, 232(sp)
-; ZVFHMIN32-NEXT: vmv.x.s a4, v6
-; ZVFHMIN32-NEXT: csrr t6, vlenb
-; ZVFHMIN32-NEXT: slli s1, t6, 2
-; ZVFHMIN32-NEXT: add t6, s1, t6
-; ZVFHMIN32-NEXT: add t6, sp, t6
-; ZVFHMIN32-NEXT: lh s6, 592(t6) # 8-byte Folded Reload
-; ZVFHMIN32-NEXT: and t4, t4, a1
-; ZVFHMIN32-NEXT: and t5, t5, a2
-; ZVFHMIN32-NEXT: or t4, t5, t4
-; ZVFHMIN32-NEXT: sh t4, 488(sp)
-; ZVFHMIN32-NEXT: lhu t5, 358(sp)
-; ZVFHMIN32-NEXT: lhu t6, 230(sp)
-; ZVFHMIN32-NEXT: vmv.x.s s7, v7
-; ZVFHMIN32-NEXT: csrr t4, vlenb
-; ZVFHMIN32-NEXT: slli t4, t4, 2
-; ZVFHMIN32-NEXT: add t4, sp, t4
-; ZVFHMIN32-NEXT: lh t4, 592(t4) # 8-byte Folded Reload
-; ZVFHMIN32-NEXT: and t5, t5, a1
-; ZVFHMIN32-NEXT: and t6, t6, a2
-; ZVFHMIN32-NEXT: or t5, t6, t5
-; ZVFHMIN32-NEXT: sh t5, 486(sp)
-; ZVFHMIN32-NEXT: lhu t5, 356(sp)
-; ZVFHMIN32-NEXT: lhu s1, 228(sp)
-; ZVFHMIN32-NEXT: vmv.x.s s4, v3
-; ZVFHMIN32-NEXT: csrr t6, vlenb
-; ZVFHMIN32-NEXT: add t6, sp, t6
-; ZVFHMIN32-NEXT: lh t6, 592(t6) # 8-byte Folded Reload
-; ZVFHMIN32-NEXT: and t5, t5, a1
-; ZVFHMIN32-NEXT: and s1, s1, a2
-; ZVFHMIN32-NEXT: or t5, s1, t5
-; ZVFHMIN32-NEXT: sh t5, 484(sp)
-; ZVFHMIN32-NEXT: lhu s2, 354(sp)
-; ZVFHMIN32-NEXT: lhu s3, 226(sp)
-; ZVFHMIN32-NEXT: vmv.x.s s1, v27
-; ZVFHMIN32-NEXT: lh t5, 592(sp) # 8-byte Folded Reload
-; ZVFHMIN32-NEXT: and s2, s2, a1
-; ZVFHMIN32-NEXT: and s3, s3, a2
-; ZVFHMIN32-NEXT: or s2, s3, s2
-; ZVFHMIN32-NEXT: sh s2, 482(sp)
-; ZVFHMIN32-NEXT: lhu s2, 352(sp)
-; ZVFHMIN32-NEXT: lhu s3, 224(sp)
-; ZVFHMIN32-NEXT: and a3, a3, a1
-; ZVFHMIN32-NEXT: and t3, t3, a2
-; ZVFHMIN32-NEXT: and s2, s2, a1
-; ZVFHMIN32-NEXT: and s3, s3, a2
-; ZVFHMIN32-NEXT: or s2, s3, s2
-; ZVFHMIN32-NEXT: sh s2, 480(sp)
-; ZVFHMIN32-NEXT: lhu s2, 350(sp)
-; ZVFHMIN32-NEXT: lhu s3, 222(sp)
-; ZVFHMIN32-NEXT: or a3, t3, a3
-; ZVFHMIN32-NEXT: sh a3, 384(sp)
-; ZVFHMIN32-NEXT: and a3, s2, a1
-; ZVFHMIN32-NEXT: and t3, s3, a2
-; ZVFHMIN32-NEXT: or a3, t3, a3
-; ZVFHMIN32-NEXT: sh a3, 478(sp)
-; ZVFHMIN32-NEXT: lhu a3, 348(sp)
-; ZVFHMIN32-NEXT: lhu t3, 220(sp)
-; ZVFHMIN32-NEXT: vmv.x.s s10, v21
-; ZVFHMIN32-NEXT: csrr s2, vlenb
-; ZVFHMIN32-NEXT: slli s2, s2, 1
-; ZVFHMIN32-NEXT: mv s3, s2
-; ZVFHMIN32-NEXT: slli s2, s2, 1
-; ZVFHMIN32-NEXT: add s2, s2, s3
-; ZVFHMIN32-NEXT: add s2, sp, s2
-; ZVFHMIN32-NEXT: lh s8, 592(s2) # 8-byte Folded Reload
-; ZVFHMIN32-NEXT: and a3, a3, a1
-; ZVFHMIN32-NEXT: and t3, t3, a2
-; ZVFHMIN32-NEXT: or a3, t3, a3
-; ZVFHMIN32-NEXT: sh a3, 476(sp)
-; ZVFHMIN32-NEXT: lhu a3, 346(sp)
-; ZVFHMIN32-NEXT: lhu t3, 218(sp)
-; ZVFHMIN32-NEXT: vmv.x.s s9, v19
-; ZVFHMIN32-NEXT: csrr s2, vlenb
-; ZVFHMIN32-NEXT: slli s3, s2, 1
-; ZVFHMIN32-NEXT: add s2, s3, s2
-; ZVFHMIN32-NEXT: add s2, sp, s2
-; ZVFHMIN32-NEXT: lh s3, 592(s2) # 8-byte Folded Reload
-; ZVFHMIN32-NEXT: and a3, a3, a1
-; ZVFHMIN32-NEXT: and t3, t3, a2
-; ZVFHMIN32-NEXT: or a3, t3, a3
-; ZVFHMIN32-NEXT: sh a3, 474(sp)
-; ZVFHMIN32-NEXT: lhu t3, 344(sp)
-; ZVFHMIN32-NEXT: lhu s2, 216(sp)
-; ZVFHMIN32-NEXT: vmv.x.s s5, v31
-; ZVFHMIN32-NEXT: csrr a3, vlenb
-; ZVFHMIN32-NEXT: slli a3, a3, 1
-; ZVFHMIN32-NEXT: add a3, sp, a3
-; ZVFHMIN32-NEXT: lh a3, 592(a3) # 8-byte Folded Reload
-; ZVFHMIN32-NEXT: and t3, t3, a1
-; ZVFHMIN32-NEXT: and s2, s2, a2
-; ZVFHMIN32-NEXT: or t3, s2, t3
-; ZVFHMIN32-NEXT: sh t3, 472(sp)
-; ZVFHMIN32-NEXT: lhu t3, 342(sp)
-; ZVFHMIN32-NEXT: lhu s11, 214(sp)
-; ZVFHMIN32-NEXT: vmv.x.s s2, v29
-; ZVFHMIN32-NEXT: and s6, s6, a1
-; ZVFHMIN32-NEXT: and t3, t3, a1
-; ZVFHMIN32-NEXT: and s11, s11, a2
-; ZVFHMIN32-NEXT: or t3, s11, t3
-; ZVFHMIN32-NEXT: sh t3, 470(sp)
-; ZVFHMIN32-NEXT: lhu s11, 340(sp)
-; ZVFHMIN32-NEXT: lhu ra, 212(sp)
-; ZVFHMIN32-NEXT: and t3, s7, a2
-; ZVFHMIN32-NEXT: or t3, t3, s6
-; ZVFHMIN32-NEXT: and s6, s11, a1
-; ZVFHMIN32-NEXT: and s7, ra, a2
-; ZVFHMIN32-NEXT: or s6, s7, s6
-; ZVFHMIN32-NEXT: sh s6, 468(sp)
-; ZVFHMIN32-NEXT: lhu s6, 338(sp)
-; ZVFHMIN32-NEXT: lhu s7, 210(sp)
-; ZVFHMIN32-NEXT: and t4, t4, a1
-; ZVFHMIN32-NEXT: and s4, s4, a2
-; ZVFHMIN32-NEXT: and s6, s6, a1
-; ZVFHMIN32-NEXT: and s7, s7, a2
-; ZVFHMIN32-NEXT: or s6, s7, s6
-; ZVFHMIN32-NEXT: sh s6, 466(sp)
-; ZVFHMIN32-NEXT: lhu s6, 336(sp)
-; ZVFHMIN32-NEXT: lhu s7, 208(sp)
-; ZVFHMIN32-NEXT: or t4, s4, t4
-; ZVFHMIN32-NEXT: and t6, t6, a1
-; ZVFHMIN32-NEXT: and s4, s6, a1
-; ZVFHMIN32-NEXT: and s6, s7, a2
-; ZVFHMIN32-NEXT: or s4, s6, s4
-; ZVFHMIN32-NEXT: sh s4, 464(sp)
-; ZVFHMIN32-NEXT: lhu s4, 334(sp)
-; ZVFHMIN32-NEXT: lhu s6, 206(sp)
-; ZVFHMIN32-NEXT: and s1, s1, a2
-; ZVFHMIN32-NEXT: or t6, s1, t6
-; ZVFHMIN32-NEXT: and s1, s4, a1
-; ZVFHMIN32-NEXT: and s4, s6, a2
-; ZVFHMIN32-NEXT: or s1, s4, s1
-; ZVFHMIN32-NEXT: sh s1, 462(sp)
-; ZVFHMIN32-NEXT: lhu s1, 332(sp)
-; ZVFHMIN32-NEXT: lhu s4, 204(sp)
-; ZVFHMIN32-NEXT: and t5, t5, a1
-; ZVFHMIN32-NEXT: and s6, s10, a2
-; ZVFHMIN32-NEXT: and s1, s1, a1
-; ZVFHMIN32-NEXT: and s4, s4, a2
-; ZVFHMIN32-NEXT: or s1, s4, s1
-; ZVFHMIN32-NEXT: sh s1, 460(sp)
-; ZVFHMIN32-NEXT: lhu s1, 330(sp)
-; ZVFHMIN32-NEXT: lhu s4, 202(sp)
-; ZVFHMIN32-NEXT: or t5, s6, t5
-; ZVFHMIN32-NEXT: and s6, s8, a1
-; ZVFHMIN32-NEXT: and s1, s1, a1
-; ZVFHMIN32-NEXT: and s4, s4, a2
-; ZVFHMIN32-NEXT: or s1, s4, s1
-; ZVFHMIN32-NEXT: sh s1, 458(sp)
-; ZVFHMIN32-NEXT: lhu s1, 328(sp)
-; ZVFHMIN32-NEXT: lhu s4, 200(sp)
-; ZVFHMIN32-NEXT: and s7, s9, a2
-; ZVFHMIN32-NEXT: or s6, s7, s6
-; ZVFHMIN32-NEXT: and s1, s1, a1
-; ZVFHMIN32-NEXT: and s4, s4, a2
-; ZVFHMIN32-NEXT: or s1, s4, s1
-; ZVFHMIN32-NEXT: sh s1, 456(sp)
-; ZVFHMIN32-NEXT: lhu s1, 326(sp)
-; ZVFHMIN32-NEXT: lhu s4, 198(sp)
-; ZVFHMIN32-NEXT: and s3, s3, a1
-; ZVFHMIN32-NEXT: and s5, s5, a2
-; ZVFHMIN32-NEXT: and s1, s1, a1
-; ZVFHMIN32-NEXT: and s4, s4, a2
-; ZVFHMIN32-NEXT: or s1, s4, s1
-; ZVFHMIN32-NEXT: sh s1, 454(sp)
-; ZVFHMIN32-NEXT: lhu s1, 324(sp)
-; ZVFHMIN32-NEXT: lhu s4, 196(sp)
-; ZVFHMIN32-NEXT: or s3, s5, s3
-; ZVFHMIN32-NEXT: and a3, a3, a1
-; ZVFHMIN32-NEXT: and s1, s1, a1
-; ZVFHMIN32-NEXT: and s4, s4, a2
-; ZVFHMIN32-NEXT: or s1, s4, s1
-; ZVFHMIN32-NEXT: sh s1, 452(sp)
-; ZVFHMIN32-NEXT: lhu s1, 322(sp)
-; ZVFHMIN32-NEXT: lhu s4, 194(sp)
-; ZVFHMIN32-NEXT: and s2, s2, a2
-; ZVFHMIN32-NEXT: or s2, s2, a3
-; ZVFHMIN32-NEXT: and s1, s1, a1
-; ZVFHMIN32-NEXT: and a3, s4, a2
-; ZVFHMIN32-NEXT: or a3, a3, s1
-; ZVFHMIN32-NEXT: sh a3, 450(sp)
-; ZVFHMIN32-NEXT: lhu a3, 320(sp)
-; ZVFHMIN32-NEXT: lhu s1, 192(sp)
-; ZVFHMIN32-NEXT: and t1, t1, a1
-; ZVFHMIN32-NEXT: and t2, t2, a2
-; ZVFHMIN32-NEXT: and a3, a3, a1
-; ZVFHMIN32-NEXT: and s1, s1, a2
-; ZVFHMIN32-NEXT: or a3, s1, a3
-; ZVFHMIN32-NEXT: sh a3, 448(sp)
-; ZVFHMIN32-NEXT: lhu s1, 318(sp)
-; ZVFHMIN32-NEXT: lhu s4, 190(sp)
-; ZVFHMIN32-NEXT: or a3, t2, t1
-; ZVFHMIN32-NEXT: vmv.x.s t2, v24
-; ZVFHMIN32-NEXT: and s1, s1, a1
-; ZVFHMIN32-NEXT: and t1, s4, a2
-; ZVFHMIN32-NEXT: or t1, t1, s1
-; ZVFHMIN32-NEXT: sh t1, 446(sp)
-; ZVFHMIN32-NEXT: lhu t1, 316(sp)
-; ZVFHMIN32-NEXT: lhu s1, 188(sp)
-; ZVFHMIN32-NEXT: sh s2, 386(sp)
-; ZVFHMIN32-NEXT: sh s3, 388(sp)
-; ZVFHMIN32-NEXT: sh s6, 390(sp)
-; ZVFHMIN32-NEXT: sh t5, 392(sp)
-; ZVFHMIN32-NEXT: vmv.x.s t5, v20
-; ZVFHMIN32-NEXT: and t1, t1, a1
-; ZVFHMIN32-NEXT: and s1, s1, a2
-; ZVFHMIN32-NEXT: or s1, s1, t1
-; ZVFHMIN32-NEXT: vmv.x.s t1, v22
-; ZVFHMIN32-NEXT: and t0, t0, a1
-; ZVFHMIN32-NEXT: sh t6, 394(sp)
-; ZVFHMIN32-NEXT: sh t4, 396(sp)
-; ZVFHMIN32-NEXT: sh t3, 398(sp)
-; ZVFHMIN32-NEXT: sh s1, 444(sp)
-; ZVFHMIN32-NEXT: lhu t3, 314(sp)
-; ZVFHMIN32-NEXT: lhu t4, 186(sp)
-; ZVFHMIN32-NEXT: and a7, a7, a2
-; ZVFHMIN32-NEXT: or a7, a7, t0
-; ZVFHMIN32-NEXT: and t0, t3, a1
-; ZVFHMIN32-NEXT: and t3, t4, a2
-; ZVFHMIN32-NEXT: or t0, t3, t0
-; ZVFHMIN32-NEXT: sh t0, 442(sp)
-; ZVFHMIN32-NEXT: lhu t0, 312(sp)
-; ZVFHMIN32-NEXT: lhu t3, 184(sp)
-; ZVFHMIN32-NEXT: vmv.x.s t4, v18
-; ZVFHMIN32-NEXT: and a6, a6, a1
-; ZVFHMIN32-NEXT: and t0, t0, a1
-; ZVFHMIN32-NEXT: and t3, t3, a2
-; ZVFHMIN32-NEXT: or t0, t3, t0
-; ZVFHMIN32-NEXT: sh t0, 440(sp)
-; ZVFHMIN32-NEXT: lhu t0, 310(sp)
-; ZVFHMIN32-NEXT: lhu t3, 182(sp)
-; ZVFHMIN32-NEXT: and a5, a5, a2
-; ZVFHMIN32-NEXT: or a5, a5, a6
-; ZVFHMIN32-NEXT: and a6, t0, a1
-; ZVFHMIN32-NEXT: and t0, t3, a2
-; ZVFHMIN32-NEXT: or a6, t0, a6
-; ZVFHMIN32-NEXT: sh a6, 438(sp)
-; ZVFHMIN32-NEXT: lhu a6, 308(sp)
-; ZVFHMIN32-NEXT: lhu t0, 180(sp)
-; ZVFHMIN32-NEXT: vmv.x.s t3, v16
-; ZVFHMIN32-NEXT: and a4, a4, a1
-; ZVFHMIN32-NEXT: and a6, a6, a1
-; ZVFHMIN32-NEXT: and t0, t0, a2
-; ZVFHMIN32-NEXT: or a6, t0, a6
-; ZVFHMIN32-NEXT: sh a6, 436(sp)
-; ZVFHMIN32-NEXT: lhu a6, 306(sp)
-; ZVFHMIN32-NEXT: lhu t0, 178(sp)
-; ZVFHMIN32-NEXT: and t2, t2, a2
-; ZVFHMIN32-NEXT: or a4, t2, a4
-; ZVFHMIN32-NEXT: and a6, a6, a1
-; ZVFHMIN32-NEXT: and t0, t0, a2
-; ZVFHMIN32-NEXT: or a6, t0, a6
-; ZVFHMIN32-NEXT: sh a6, 434(sp)
-; ZVFHMIN32-NEXT: lhu a6, 304(sp)
-; ZVFHMIN32-NEXT: lhu t0, 176(sp)
-; ZVFHMIN32-NEXT: vmv.x.s t2, v2
-; ZVFHMIN32-NEXT: and t5, t5, a1
-; ZVFHMIN32-NEXT: and a6, a6, a1
-; ZVFHMIN32-NEXT: and t0, t0, a2
-; ZVFHMIN32-NEXT: or a6, t0, a6
-; ZVFHMIN32-NEXT: sh a6, 432(sp)
-; ZVFHMIN32-NEXT: lhu t0, 302(sp)
-; ZVFHMIN32-NEXT: lhu t6, 174(sp)
-; ZVFHMIN32-NEXT: and a6, t1, a2
-; ZVFHMIN32-NEXT: or a6, a6, t5
-; ZVFHMIN32-NEXT: and t0, t0, a1
-; ZVFHMIN32-NEXT: and t1, t6, a2
-; ZVFHMIN32-NEXT: or t0, t1, t0
-; ZVFHMIN32-NEXT: sh t0, 430(sp)
-; ZVFHMIN32-NEXT: lhu t0, 300(sp)
-; ZVFHMIN32-NEXT: lhu t1, 172(sp)
-; ZVFHMIN32-NEXT: vmv.x.s t5, v4
-; ZVFHMIN32-NEXT: and t4, t4, a1
-; ZVFHMIN32-NEXT: and t0, t0, a1
-; ZVFHMIN32-NEXT: and t1, t1, a2
-; ZVFHMIN32-NEXT: or t0, t1, t0
-; ZVFHMIN32-NEXT: sh t0, 428(sp)
-; ZVFHMIN32-NEXT: lhu t0, 298(sp)
-; ZVFHMIN32-NEXT: lhu t1, 170(sp)
-; ZVFHMIN32-NEXT: and t3, t3, a2
-; ZVFHMIN32-NEXT: or t3, t3, t4
-; ZVFHMIN32-NEXT: and t0, t0, a1
-; ZVFHMIN32-NEXT: and t1, t1, a2
-; ZVFHMIN32-NEXT: or t0, t1, t0
-; ZVFHMIN32-NEXT: sh t0, 426(sp)
-; ZVFHMIN32-NEXT: lhu t0, 296(sp)
-; ZVFHMIN32-NEXT: lhu t1, 168(sp)
-; ZVFHMIN32-NEXT: vmv.x.s t4, v0
-; ZVFHMIN32-NEXT: and t2, t2, a1
-; ZVFHMIN32-NEXT: and t0, t0, a1
-; ZVFHMIN32-NEXT: and t1, t1, a2
-; ZVFHMIN32-NEXT: or t0, t1, t0
-; ZVFHMIN32-NEXT: sh t0, 424(sp)
-; ZVFHMIN32-NEXT: lhu t0, 294(sp)
-; ZVFHMIN32-NEXT: lhu t1, 166(sp)
-; ZVFHMIN32-NEXT: and t5, t5, a2
-; ZVFHMIN32-NEXT: or t2, t5, t2
-; ZVFHMIN32-NEXT: and t0, t0, a1
-; ZVFHMIN32-NEXT: and t1, t1, a2
-; ZVFHMIN32-NEXT: or t0, t1, t0
-; ZVFHMIN32-NEXT: sh t0, 422(sp)
-; ZVFHMIN32-NEXT: lhu t0, 292(sp)
-; ZVFHMIN32-NEXT: lhu t1, 164(sp)
-; ZVFHMIN32-NEXT: vmv.x.s t5, v8
-; ZVFHMIN32-NEXT: and t4, t4, a1
-; ZVFHMIN32-NEXT: and t0, t0, a1
-; ZVFHMIN32-NEXT: and t1, t1, a2
-; ZVFHMIN32-NEXT: or t0, t1, t0
-; ZVFHMIN32-NEXT: sh t0, 420(sp)
-; ZVFHMIN32-NEXT: lhu t0, 290(sp)
-; ZVFHMIN32-NEXT: lhu t1, 162(sp)
-; ZVFHMIN32-NEXT: and t5, t5, a2
-; ZVFHMIN32-NEXT: or t4, t5, t4
-; ZVFHMIN32-NEXT: and t0, t0, a1
-; ZVFHMIN32-NEXT: and t1, t1, a2
-; ZVFHMIN32-NEXT: or t0, t1, t0
-; ZVFHMIN32-NEXT: sh t0, 418(sp)
-; ZVFHMIN32-NEXT: lhu t0, 288(sp)
-; ZVFHMIN32-NEXT: lhu t1, 160(sp)
-; ZVFHMIN32-NEXT: sh a4, 408(sp)
-; ZVFHMIN32-NEXT: sh a5, 410(sp)
-; ZVFHMIN32-NEXT: sh a7, 412(sp)
-; ZVFHMIN32-NEXT: sh a3, 414(sp)
-; ZVFHMIN32-NEXT: sh t4, 400(sp)
-; ZVFHMIN32-NEXT: sh t2, 402(sp)
-; ZVFHMIN32-NEXT: sh t3, 404(sp)
-; ZVFHMIN32-NEXT: sh a6, 406(sp)
-; ZVFHMIN32-NEXT: and a1, t0, a1
-; ZVFHMIN32-NEXT: and a2, t1, a2
-; ZVFHMIN32-NEXT: or a1, a2, a1
-; ZVFHMIN32-NEXT: sh a1, 416(sp)
-; ZVFHMIN32-NEXT: addi a1, sp, 384
-; ZVFHMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN32-NEXT: vle16.v v8, (a1)
-; ZVFHMIN32-NEXT: addi sp, s0, -656
-; ZVFHMIN32-NEXT: .cfi_def_cfa sp, 656
-; ZVFHMIN32-NEXT: lw ra, 652(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT: lw s0, 648(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT: lw s1, 644(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT: lw s2, 640(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT: lw s3, 636(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT: lw s4, 632(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT: lw s5, 628(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT: lw s6, 624(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT: lw s7, 620(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT: lw s8, 616(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT: lw s9, 612(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT: lw s10, 608(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT: lw s11, 604(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT: .cfi_restore ra
-; ZVFHMIN32-NEXT: .cfi_restore s0
-; ZVFHMIN32-NEXT: .cfi_restore s1
-; ZVFHMIN32-NEXT: .cfi_restore s2
-; ZVFHMIN32-NEXT: .cfi_restore s3
-; ZVFHMIN32-NEXT: .cfi_restore s4
-; ZVFHMIN32-NEXT: .cfi_restore s5
-; ZVFHMIN32-NEXT: .cfi_restore s6
-; ZVFHMIN32-NEXT: .cfi_restore s7
-; ZVFHMIN32-NEXT: .cfi_restore s8
-; ZVFHMIN32-NEXT: .cfi_restore s9
-; ZVFHMIN32-NEXT: .cfi_restore s10
-; ZVFHMIN32-NEXT: .cfi_restore s11
-; ZVFHMIN32-NEXT: addi sp, sp, 656
-; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 0
-; ZVFHMIN32-NEXT: ret
-;
-; ZVFHMIN64-LABEL: copysign_v64f16:
-; ZVFHMIN64: # %bb.0:
-; ZVFHMIN64-NEXT: addi sp, sp, -656
-; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 656
-; ZVFHMIN64-NEXT: sd ra, 648(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT: sd s0, 640(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT: sd s1, 632(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT: sd s2, 624(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT: sd s3, 616(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT: sd s4, 608(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT: sd s5, 600(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT: sd s6, 592(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT: sd s7, 584(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT: sd s8, 576(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT: sd s9, 568(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT: sd s10, 560(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT: sd s11, 552(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT: .cfi_offset ra, -8
-; ZVFHMIN64-NEXT: .cfi_offset s0, -16
-; ZVFHMIN64-NEXT: .cfi_offset s1, -24
-; ZVFHMIN64-NEXT: .cfi_offset s2, -32
-; ZVFHMIN64-NEXT: .cfi_offset s3, -40
-; ZVFHMIN64-NEXT: .cfi_offset s4, -48
-; ZVFHMIN64-NEXT: .cfi_offset s5, -56
-; ZVFHMIN64-NEXT: .cfi_offset s6, -64
-; ZVFHMIN64-NEXT: .cfi_offset s7, -72
-; ZVFHMIN64-NEXT: .cfi_offset s8, -80
-; ZVFHMIN64-NEXT: .cfi_offset s9, -88
-; ZVFHMIN64-NEXT: .cfi_offset s10, -96
-; ZVFHMIN64-NEXT: .cfi_offset s11, -104
-; ZVFHMIN64-NEXT: addi s0, sp, 656
-; ZVFHMIN64-NEXT: .cfi_def_cfa s0, 0
-; ZVFHMIN64-NEXT: csrr a0, vlenb
-; ZVFHMIN64-NEXT: slli a1, a0, 3
-; ZVFHMIN64-NEXT: sub a0, a1, a0
-; ZVFHMIN64-NEXT: sub sp, sp, a0
-; ZVFHMIN64-NEXT: andi sp, sp, -128
-; ZVFHMIN64-NEXT: li a0, 64
-; ZVFHMIN64-NEXT: addi a2, sp, 256
-; ZVFHMIN64-NEXT: addi a4, sp, 128
-; ZVFHMIN64-NEXT: lui a1, 8
-; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN64-NEXT: vmv.x.s a3, v16
-; ZVFHMIN64-NEXT: vslidedown.vi v24, v16, 7
-; ZVFHMIN64-NEXT: csrr a5, vlenb
-; ZVFHMIN64-NEXT: slli a6, a5, 2
-; ZVFHMIN64-NEXT: add a5, a6, a5
-; ZVFHMIN64-NEXT: add a5, sp, a5
-; ZVFHMIN64-NEXT: addi a5, a5, 544
-; ZVFHMIN64-NEXT: vs1r.v v24, (a5) # vscale x 8-byte Folded Spill
-; ZVFHMIN64-NEXT: vslidedown.vi v24, v16, 6
-; ZVFHMIN64-NEXT: csrr a5, vlenb
-; ZVFHMIN64-NEXT: slli a5, a5, 2
-; ZVFHMIN64-NEXT: add a5, sp, a5
-; ZVFHMIN64-NEXT: addi a5, a5, 544
-; ZVFHMIN64-NEXT: vs1r.v v24, (a5) # vscale x 8-byte Folded Spill
-; ZVFHMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN64-NEXT: vse16.v v16, (a2)
-; ZVFHMIN64-NEXT: vse16.v v8, (a4)
-; ZVFHMIN64-NEXT: lhu a4, 382(sp)
-; ZVFHMIN64-NEXT: lhu a5, 254(sp)
-; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN64-NEXT: vslidedown.vi v10, v16, 5
-; ZVFHMIN64-NEXT: csrr a2, vlenb
-; ZVFHMIN64-NEXT: add a2, sp, a2
-; ZVFHMIN64-NEXT: addi a2, a2, 544
-; ZVFHMIN64-NEXT: vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN64-NEXT: addi a2, a1, -1
-; ZVFHMIN64-NEXT: and a4, a4, a1
-; ZVFHMIN64-NEXT: and a5, a5, a2
-; ZVFHMIN64-NEXT: or a4, a5, a4
-; ZVFHMIN64-NEXT: sh a4, 510(sp)
-; ZVFHMIN64-NEXT: lhu a4, 380(sp)
-; ZVFHMIN64-NEXT: lhu a5, 252(sp)
-; ZVFHMIN64-NEXT: vslidedown.vi v10, v16, 4
-; ZVFHMIN64-NEXT: addi a6, sp, 544
-; ZVFHMIN64-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
-; ZVFHMIN64-NEXT: vslidedown.vi v10, v16, 3
-; ZVFHMIN64-NEXT: csrr a6, vlenb
-; ZVFHMIN64-NEXT: slli a6, a6, 1
-; ZVFHMIN64-NEXT: mv a7, a6
-; ZVFHMIN64-NEXT: slli a6, a6, 1
-; ZVFHMIN64-NEXT: add a6, a6, a7
-; ZVFHMIN64-NEXT: add a6, sp, a6
-; ZVFHMIN64-NEXT: addi a6, a6, 544
-; ZVFHMIN64-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
-; ZVFHMIN64-NEXT: and a4, a4, a1
-; ZVFHMIN64-NEXT: and a5, a5, a2
-; ZVFHMIN64-NEXT: or a4, a5, a4
-; ZVFHMIN64-NEXT: sh a4, 508(sp)
-; ZVFHMIN64-NEXT: lhu a4, 378(sp)
-; ZVFHMIN64-NEXT: lhu a5, 250(sp)
-; ZVFHMIN64-NEXT: vslidedown.vi v10, v16, 2
-; ZVFHMIN64-NEXT: csrr a6, vlenb
-; ZVFHMIN64-NEXT: slli a7, a6, 1
-; ZVFHMIN64-NEXT: add a6, a7, a6
-; ZVFHMIN64-NEXT: add a6, sp, a6
-; ZVFHMIN64-NEXT: addi a6, a6, 544
-; ZVFHMIN64-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
-; ZVFHMIN64-NEXT: vslidedown.vi v10, v16, 1
-; ZVFHMIN64-NEXT: csrr a6, vlenb
-; ZVFHMIN64-NEXT: slli a6, a6, 1
-; ZVFHMIN64-NEXT: add a6, sp, a6
-; ZVFHMIN64-NEXT: addi a6, a6, 544
-; ZVFHMIN64-NEXT: vs1r.v v10, (a6) # vscale x 8-byte Folded Spill
-; ZVFHMIN64-NEXT: and a4, a4, a1
-; ZVFHMIN64-NEXT: and a5, a5, a2
-; ZVFHMIN64-NEXT: or a4, a5, a4
-; ZVFHMIN64-NEXT: sh a4, 506(sp)
-; ZVFHMIN64-NEXT: lhu a4, 376(sp)
-; ZVFHMIN64-NEXT: lhu a5, 248(sp)
-; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; ZVFHMIN64-NEXT: vslidedown.vi v26, v16, 15
-; ZVFHMIN64-NEXT: vslidedown.vi v28, v16, 14
-; ZVFHMIN64-NEXT: and a4, a4, a1
-; ZVFHMIN64-NEXT: and a5, a5, a2
-; ZVFHMIN64-NEXT: or a4, a5, a4
-; ZVFHMIN64-NEXT: sh a4, 504(sp)
-; ZVFHMIN64-NEXT: lhu a4, 374(sp)
-; ZVFHMIN64-NEXT: lhu a5, 246(sp)
-; ZVFHMIN64-NEXT: vslidedown.vi v30, v16, 13
-; ZVFHMIN64-NEXT: vslidedown.vi v6, v16, 12
-; ZVFHMIN64-NEXT: and a4, a4, a1
-; ZVFHMIN64-NEXT: and a5, a5, a2
-; ZVFHMIN64-NEXT: or a4, a5, a4
-; ZVFHMIN64-NEXT: sh a4, 502(sp)
-; ZVFHMIN64-NEXT: lhu a4, 372(sp)
-; ZVFHMIN64-NEXT: lhu a5, 244(sp)
-; ZVFHMIN64-NEXT: vslidedown.vi v20, v16, 11
-; ZVFHMIN64-NEXT: vslidedown.vi v18, v16, 10
-; ZVFHMIN64-NEXT: vslidedown.vi v2, v16, 9
-; ZVFHMIN64-NEXT: vslidedown.vi v0, v16, 8
-; ZVFHMIN64-NEXT: and a4, a4, a1
-; ZVFHMIN64-NEXT: and a5, a5, a2
-; ZVFHMIN64-NEXT: or a4, a5, a4
-; ZVFHMIN64-NEXT: sh a4, 500(sp)
-; ZVFHMIN64-NEXT: lhu a4, 370(sp)
-; ZVFHMIN64-NEXT: lhu a5, 242(sp)
-; ZVFHMIN64-NEXT: vmv.x.s t3, v8
-; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN64-NEXT: vslidedown.vi v7, v8, 7
-; ZVFHMIN64-NEXT: and a4, a4, a1
-; ZVFHMIN64-NEXT: and a5, a5, a2
-; ZVFHMIN64-NEXT: or a4, a5, a4
-; ZVFHMIN64-NEXT: sh a4, 498(sp)
-; ZVFHMIN64-NEXT: lhu a4, 368(sp)
-; ZVFHMIN64-NEXT: lhu a5, 240(sp)
-; ZVFHMIN64-NEXT: vslidedown.vi v3, v8, 6
-; ZVFHMIN64-NEXT: vslidedown.vi v27, v8, 5
-; ZVFHMIN64-NEXT: vslidedown.vi v21, v8, 4
-; ZVFHMIN64-NEXT: vslidedown.vi v19, v8, 3
-; ZVFHMIN64-NEXT: vslidedown.vi v31, v8, 2
-; ZVFHMIN64-NEXT: vslidedown.vi v29, v8, 1
-; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 15
-; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 14
-; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 13
-; ZVFHMIN64-NEXT: vslidedown.vi v24, v8, 12
-; ZVFHMIN64-NEXT: vslidedown.vi v22, v8, 11
-; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 10
-; ZVFHMIN64-NEXT: vslidedown.vi v4, v8, 9
-; ZVFHMIN64-NEXT: vslidedown.vi v8, v8, 8
-; ZVFHMIN64-NEXT: and a4, a4, a1
-; ZVFHMIN64-NEXT: and a5, a5, a2
-; ZVFHMIN64-NEXT: or a4, a5, a4
-; ZVFHMIN64-NEXT: sh a4, 496(sp)
-; ZVFHMIN64-NEXT: lhu a4, 366(sp)
-; ZVFHMIN64-NEXT: lhu a5, 238(sp)
-; ZVFHMIN64-NEXT: vmv.x.s t1, v26
-; ZVFHMIN64-NEXT: vmv.x.s t2, v10
-; ZVFHMIN64-NEXT: and a4, a4, a1
-; ZVFHMIN64-NEXT: and a5, a5, a2
-; ZVFHMIN64-NEXT: or a4, a5, a4
-; ZVFHMIN64-NEXT: sh a4, 494(sp)
-; ZVFHMIN64-NEXT: lhu a4, 364(sp)
-; ZVFHMIN64-NEXT: lhu a5, 236(sp)
-; ZVFHMIN64-NEXT: vmv.x.s t0, v28
-; ZVFHMIN64-NEXT: vmv.x.s a7, v12
-; ZVFHMIN64-NEXT: and a4, a4, a1
-; ZVFHMIN64-NEXT: and a5, a5, a2
-; ZVFHMIN64-NEXT: or a4, a5, a4
-; ZVFHMIN64-NEXT: sh a4, 492(sp)
-; ZVFHMIN64-NEXT: lhu a4, 362(sp)
-; ZVFHMIN64-NEXT: lhu t4, 234(sp)
-; ZVFHMIN64-NEXT: vmv.x.s a6, v30
-; ZVFHMIN64-NEXT: vmv.x.s a5, v14
-; ZVFHMIN64-NEXT: and a4, a4, a1
-; ZVFHMIN64-NEXT: and t4, t4, a2
-; ZVFHMIN64-NEXT: or a4, t4, a4
-; ZVFHMIN64-NEXT: sh a4, 490(sp)
-; ZVFHMIN64-NEXT: lhu t4, 360(sp)
-; ZVFHMIN64-NEXT: lhu t5, 232(sp)
-; ZVFHMIN64-NEXT: vmv.x.s a4, v6
-; ZVFHMIN64-NEXT: csrr t6, vlenb
-; ZVFHMIN64-NEXT: slli s1, t6, 2
-; ZVFHMIN64-NEXT: add t6, s1, t6
-; ZVFHMIN64-NEXT: add t6, sp, t6
-; ZVFHMIN64-NEXT: lh s6, 544(t6) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: and t4, t4, a1
-; ZVFHMIN64-NEXT: and t5, t5, a2
-; ZVFHMIN64-NEXT: or t4, t5, t4
-; ZVFHMIN64-NEXT: sh t4, 488(sp)
-; ZVFHMIN64-NEXT: lhu t5, 358(sp)
-; ZVFHMIN64-NEXT: lhu t6, 230(sp)
-; ZVFHMIN64-NEXT: vmv.x.s s7, v7
-; ZVFHMIN64-NEXT: csrr t4, vlenb
-; ZVFHMIN64-NEXT: slli t4, t4, 2
-; ZVFHMIN64-NEXT: add t4, sp, t4
-; ZVFHMIN64-NEXT: lh t4, 544(t4) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: and t5, t5, a1
-; ZVFHMIN64-NEXT: and t6, t6, a2
-; ZVFHMIN64-NEXT: or t5, t6, t5
-; ZVFHMIN64-NEXT: sh t5, 486(sp)
-; ZVFHMIN64-NEXT: lhu t5, 356(sp)
-; ZVFHMIN64-NEXT: lhu s1, 228(sp)
-; ZVFHMIN64-NEXT: vmv.x.s s4, v3
-; ZVFHMIN64-NEXT: csrr t6, vlenb
-; ZVFHMIN64-NEXT: add t6, sp, t6
-; ZVFHMIN64-NEXT: lh t6, 544(t6) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: and t5, t5, a1
-; ZVFHMIN64-NEXT: and s1, s1, a2
-; ZVFHMIN64-NEXT: or t5, s1, t5
-; ZVFHMIN64-NEXT: sh t5, 484(sp)
-; ZVFHMIN64-NEXT: lhu s2, 354(sp)
-; ZVFHMIN64-NEXT: lhu s3, 226(sp)
-; ZVFHMIN64-NEXT: vmv.x.s s1, v27
-; ZVFHMIN64-NEXT: lh t5, 544(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: and s2, s2, a1
-; ZVFHMIN64-NEXT: and s3, s3, a2
-; ZVFHMIN64-NEXT: or s2, s3, s2
-; ZVFHMIN64-NEXT: sh s2, 482(sp)
-; ZVFHMIN64-NEXT: lhu s2, 352(sp)
-; ZVFHMIN64-NEXT: lhu s3, 224(sp)
-; ZVFHMIN64-NEXT: and a3, a3, a1
-; ZVFHMIN64-NEXT: and t3, t3, a2
-; ZVFHMIN64-NEXT: and s2, s2, a1
-; ZVFHMIN64-NEXT: and s3, s3, a2
-; ZVFHMIN64-NEXT: or s2, s3, s2
-; ZVFHMIN64-NEXT: sh s2, 480(sp)
-; ZVFHMIN64-NEXT: lhu s2, 350(sp)
-; ZVFHMIN64-NEXT: lhu s3, 222(sp)
-; ZVFHMIN64-NEXT: or a3, t3, a3
-; ZVFHMIN64-NEXT: sh a3, 384(sp)
-; ZVFHMIN64-NEXT: and a3, s2, a1
-; ZVFHMIN64-NEXT: and t3, s3, a2
-; ZVFHMIN64-NEXT: or a3, t3, a3
-; ZVFHMIN64-NEXT: sh a3, 478(sp)
-; ZVFHMIN64-NEXT: lhu a3, 348(sp)
-; ZVFHMIN64-NEXT: lhu t3, 220(sp)
-; ZVFHMIN64-NEXT: vmv.x.s s10, v21
-; ZVFHMIN64-NEXT: csrr s2, vlenb
-; ZVFHMIN64-NEXT: slli s2, s2, 1
-; ZVFHMIN64-NEXT: mv s3, s2
-; ZVFHMIN64-NEXT: slli s2, s2, 1
-; ZVFHMIN64-NEXT: add s2, s2, s3
-; ZVFHMIN64-NEXT: add s2, sp, s2
-; ZVFHMIN64-NEXT: lh s8, 544(s2) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: and a3, a3, a1
-; ZVFHMIN64-NEXT: and t3, t3, a2
-; ZVFHMIN64-NEXT: or a3, t3, a3
-; ZVFHMIN64-NEXT: sh a3, 476(sp)
-; ZVFHMIN64-NEXT: lhu a3, 346(sp)
-; ZVFHMIN64-NEXT: lhu t3, 218(sp)
-; ZVFHMIN64-NEXT: vmv.x.s s9, v19
-; ZVFHMIN64-NEXT: csrr s2, vlenb
-; ZVFHMIN64-NEXT: slli s3, s2, 1
-; ZVFHMIN64-NEXT: add s2, s3, s2
-; ZVFHMIN64-NEXT: add s2, sp, s2
-; ZVFHMIN64-NEXT: lh s3, 544(s2) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: and a3, a3, a1
-; ZVFHMIN64-NEXT: and t3, t3, a2
-; ZVFHMIN64-NEXT: or a3, t3, a3
-; ZVFHMIN64-NEXT: sh a3, 474(sp)
-; ZVFHMIN64-NEXT: lhu t3, 344(sp)
-; ZVFHMIN64-NEXT: lhu s2, 216(sp)
-; ZVFHMIN64-NEXT: vmv.x.s s5, v31
-; ZVFHMIN64-NEXT: csrr a3, vlenb
-; ZVFHMIN64-NEXT: slli a3, a3, 1
-; ZVFHMIN64-NEXT: add a3, sp, a3
-; ZVFHMIN64-NEXT: lh a3, 544(a3) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: and t3, t3, a1
-; ZVFHMIN64-NEXT: and s2, s2, a2
-; ZVFHMIN64-NEXT: or t3, s2, t3
-; ZVFHMIN64-NEXT: sh t3, 472(sp)
-; ZVFHMIN64-NEXT: lhu t3, 342(sp)
-; ZVFHMIN64-NEXT: lhu s11, 214(sp)
-; ZVFHMIN64-NEXT: vmv.x.s s2, v29
-; ZVFHMIN64-NEXT: and s6, s6, a1
-; ZVFHMIN64-NEXT: and t3, t3, a1
-; ZVFHMIN64-NEXT: and s11, s11, a2
-; ZVFHMIN64-NEXT: or t3, s11, t3
-; ZVFHMIN64-NEXT: sh t3, 470(sp)
-; ZVFHMIN64-NEXT: lhu s11, 340(sp)
-; ZVFHMIN64-NEXT: lhu ra, 212(sp)
-; ZVFHMIN64-NEXT: and t3, s7, a2
-; ZVFHMIN64-NEXT: or t3, t3, s6
-; ZVFHMIN64-NEXT: and s6, s11, a1
-; ZVFHMIN64-NEXT: and s7, ra, a2
-; ZVFHMIN64-NEXT: or s6, s7, s6
-; ZVFHMIN64-NEXT: sh s6, 468(sp)
-; ZVFHMIN64-NEXT: lhu s6, 338(sp)
-; ZVFHMIN64-NEXT: lhu s7, 210(sp)
-; ZVFHMIN64-NEXT: and t4, t4, a1
-; ZVFHMIN64-NEXT: and s4, s4, a2
-; ZVFHMIN64-NEXT: and s6, s6, a1
-; ZVFHMIN64-NEXT: and s7, s7, a2
-; ZVFHMIN64-NEXT: or s6, s7, s6
-; ZVFHMIN64-NEXT: sh s6, 466(sp)
-; ZVFHMIN64-NEXT: lhu s6, 336(sp)
-; ZVFHMIN64-NEXT: lhu s7, 208(sp)
-; ZVFHMIN64-NEXT: or t4, s4, t4
-; ZVFHMIN64-NEXT: and t6, t6, a1
-; ZVFHMIN64-NEXT: and s4, s6, a1
-; ZVFHMIN64-NEXT: and s6, s7, a2
-; ZVFHMIN64-NEXT: or s4, s6, s4
-; ZVFHMIN64-NEXT: sh s4, 464(sp)
-; ZVFHMIN64-NEXT: lhu s4, 334(sp)
-; ZVFHMIN64-NEXT: lhu s6, 206(sp)
-; ZVFHMIN64-NEXT: and s1, s1, a2
-; ZVFHMIN64-NEXT: or t6, s1, t6
-; ZVFHMIN64-NEXT: and s1, s4, a1
-; ZVFHMIN64-NEXT: and s4, s6, a2
-; ZVFHMIN64-NEXT: or s1, s4, s1
-; ZVFHMIN64-NEXT: sh s1, 462(sp)
-; ZVFHMIN64-NEXT: lhu s1, 332(sp)
-; ZVFHMIN64-NEXT: lhu s4, 204(sp)
-; ZVFHMIN64-NEXT: and t5, t5, a1
-; ZVFHMIN64-NEXT: and s6, s10, a2
-; ZVFHMIN64-NEXT: and s1, s1, a1
-; ZVFHMIN64-NEXT: and s4, s4, a2
-; ZVFHMIN64-NEXT: or s1, s4, s1
-; ZVFHMIN64-NEXT: sh s1, 460(sp)
-; ZVFHMIN64-NEXT: lhu s1, 330(sp)
-; ZVFHMIN64-NEXT: lhu s4, 202(sp)
-; ZVFHMIN64-NEXT: or t5, s6, t5
-; ZVFHMIN64-NEXT: and s6, s8, a1
-; ZVFHMIN64-NEXT: and s1, s1, a1
-; ZVFHMIN64-NEXT: and s4, s4, a2
-; ZVFHMIN64-NEXT: or s1, s4, s1
-; ZVFHMIN64-NEXT: sh s1, 458(sp)
-; ZVFHMIN64-NEXT: lhu s1, 328(sp)
-; ZVFHMIN64-NEXT: lhu s4, 200(sp)
-; ZVFHMIN64-NEXT: and s7, s9, a2
-; ZVFHMIN64-NEXT: or s6, s7, s6
-; ZVFHMIN64-NEXT: and s1, s1, a1
-; ZVFHMIN64-NEXT: and s4, s4, a2
-; ZVFHMIN64-NEXT: or s1, s4, s1
-; ZVFHMIN64-NEXT: sh s1, 456(sp)
-; ZVFHMIN64-NEXT: lhu s1, 326(sp)
-; ZVFHMIN64-NEXT: lhu s4, 198(sp)
-; ZVFHMIN64-NEXT: and s3, s3, a1
-; ZVFHMIN64-NEXT: and s5, s5, a2
-; ZVFHMIN64-NEXT: and s1, s1, a1
-; ZVFHMIN64-NEXT: and s4, s4, a2
-; ZVFHMIN64-NEXT: or s1, s4, s1
-; ZVFHMIN64-NEXT: sh s1, 454(sp)
-; ZVFHMIN64-NEXT: lhu s1, 324(sp)
-; ZVFHMIN64-NEXT: lhu s4, 196(sp)
-; ZVFHMIN64-NEXT: or s3, s5, s3
-; ZVFHMIN64-NEXT: and a3, a3, a1
-; ZVFHMIN64-NEXT: and s1, s1, a1
-; ZVFHMIN64-NEXT: and s4, s4, a2
-; ZVFHMIN64-NEXT: or s1, s4, s1
-; ZVFHMIN64-NEXT: sh s1, 452(sp)
-; ZVFHMIN64-NEXT: lhu s1, 322(sp)
-; ZVFHMIN64-NEXT: lhu s4, 194(sp)
-; ZVFHMIN64-NEXT: and s2, s2, a2
-; ZVFHMIN64-NEXT: or s2, s2, a3
-; ZVFHMIN64-NEXT: and s1, s1, a1
-; ZVFHMIN64-NEXT: and a3, s4, a2
-; ZVFHMIN64-NEXT: or a3, a3, s1
-; ZVFHMIN64-NEXT: sh a3, 450(sp)
-; ZVFHMIN64-NEXT: lhu a3, 320(sp)
-; ZVFHMIN64-NEXT: lhu s1, 192(sp)
-; ZVFHMIN64-NEXT: and t1, t1, a1
-; ZVFHMIN64-NEXT: and t2, t2, a2
-; ZVFHMIN64-NEXT: and a3, a3, a1
-; ZVFHMIN64-NEXT: and s1, s1, a2
-; ZVFHMIN64-NEXT: or a3, s1, a3
-; ZVFHMIN64-NEXT: sh a3, 448(sp)
-; ZVFHMIN64-NEXT: lhu s1, 318(sp)
-; ZVFHMIN64-NEXT: lhu s4, 190(sp)
-; ZVFHMIN64-NEXT: or a3, t2, t1
-; ZVFHMIN64-NEXT: vmv.x.s t2, v24
-; ZVFHMIN64-NEXT: and s1, s1, a1
-; ZVFHMIN64-NEXT: and t1, s4, a2
-; ZVFHMIN64-NEXT: or t1, t1, s1
-; ZVFHMIN64-NEXT: sh t1, 446(sp)
-; ZVFHMIN64-NEXT: lhu t1, 316(sp)
-; ZVFHMIN64-NEXT: lhu s1, 188(sp)
-; ZVFHMIN64-NEXT: sh s2, 386(sp)
-; ZVFHMIN64-NEXT: sh s3, 388(sp)
-; ZVFHMIN64-NEXT: sh s6, 390(sp)
-; ZVFHMIN64-NEXT: sh t5, 392(sp)
-; ZVFHMIN64-NEXT: vmv.x.s t5, v20
-; ZVFHMIN64-NEXT: and t1, t1, a1
-; ZVFHMIN64-NEXT: and s1, s1, a2
-; ZVFHMIN64-NEXT: or s1, s1, t1
-; ZVFHMIN64-NEXT: vmv.x.s t1, v22
-; ZVFHMIN64-NEXT: and t0, t0, a1
-; ZVFHMIN64-NEXT: sh t6, 394(sp)
-; ZVFHMIN64-NEXT: sh t4, 396(sp)
-; ZVFHMIN64-NEXT: sh t3, 398(sp)
-; ZVFHMIN64-NEXT: sh s1, 444(sp)
-; ZVFHMIN64-NEXT: lhu t3, 314(sp)
-; ZVFHMIN64-NEXT: lhu t4, 186(sp)
-; ZVFHMIN64-NEXT: and a7, a7, a2
-; ZVFHMIN64-NEXT: or a7, a7, t0
-; ZVFHMIN64-NEXT: and t0, t3, a1
-; ZVFHMIN64-NEXT: and t3, t4, a2
-; ZVFHMIN64-NEXT: or t0, t3, t0
-; ZVFHMIN64-NEXT: sh t0, 442(sp)
-; ZVFHMIN64-NEXT: lhu t0, 312(sp)
-; ZVFHMIN64-NEXT: lhu t3, 184(sp)
-; ZVFHMIN64-NEXT: vmv.x.s t4, v18
-; ZVFHMIN64-NEXT: and a6, a6, a1
-; ZVFHMIN64-NEXT: and t0, t0, a1
-; ZVFHMIN64-NEXT: and t3, t3, a2
-; ZVFHMIN64-NEXT: or t0, t3, t0
-; ZVFHMIN64-NEXT: sh t0, 440(sp)
-; ZVFHMIN64-NEXT: lhu t0, 310(sp)
-; ZVFHMIN64-NEXT: lhu t3, 182(sp)
-; ZVFHMIN64-NEXT: and a5, a5, a2
-; ZVFHMIN64-NEXT: or a5, a5, a6
-; ZVFHMIN64-NEXT: and a6, t0, a1
-; ZVFHMIN64-NEXT: and t0, t3, a2
-; ZVFHMIN64-NEXT: or a6, t0, a6
-; ZVFHMIN64-NEXT: sh a6, 438(sp)
-; ZVFHMIN64-NEXT: lhu a6, 308(sp)
-; ZVFHMIN64-NEXT: lhu t0, 180(sp)
-; ZVFHMIN64-NEXT: vmv.x.s t3, v16
-; ZVFHMIN64-NEXT: and a4, a4, a1
-; ZVFHMIN64-NEXT: and a6, a6, a1
-; ZVFHMIN64-NEXT: and t0, t0, a2
-; ZVFHMIN64-NEXT: or a6, t0, a6
-; ZVFHMIN64-NEXT: sh a6, 436(sp)
-; ZVFHMIN64-NEXT: lhu a6, 306(sp)
-; ZVFHMIN64-NEXT: lhu t0, 178(sp)
-; ZVFHMIN64-NEXT: and t2, t2, a2
-; ZVFHMIN64-NEXT: or a4, t2, a4
-; ZVFHMIN64-NEXT: and a6, a6, a1
-; ZVFHMIN64-NEXT: and t0, t0, a2
-; ZVFHMIN64-NEXT: or a6, t0, a6
-; ZVFHMIN64-NEXT: sh a6, 434(sp)
-; ZVFHMIN64-NEXT: lhu a6, 304(sp)
-; ZVFHMIN64-NEXT: lhu t0, 176(sp)
-; ZVFHMIN64-NEXT: vmv.x.s t2, v2
-; ZVFHMIN64-NEXT: and t5, t5, a1
-; ZVFHMIN64-NEXT: and a6, a6, a1
-; ZVFHMIN64-NEXT: and t0, t0, a2
-; ZVFHMIN64-NEXT: or a6, t0, a6
-; ZVFHMIN64-NEXT: sh a6, 432(sp)
-; ZVFHMIN64-NEXT: lhu t0, 302(sp)
-; ZVFHMIN64-NEXT: lhu t6, 174(sp)
-; ZVFHMIN64-NEXT: and a6, t1, a2
-; ZVFHMIN64-NEXT: or a6, a6, t5
-; ZVFHMIN64-NEXT: and t0, t0, a1
-; ZVFHMIN64-NEXT: and t1, t6, a2
-; ZVFHMIN64-NEXT: or t0, t1, t0
-; ZVFHMIN64-NEXT: sh t0, 430(sp)
-; ZVFHMIN64-NEXT: lhu t0, 300(sp)
-; ZVFHMIN64-NEXT: lhu t1, 172(sp)
-; ZVFHMIN64-NEXT: vmv.x.s t5, v4
-; ZVFHMIN64-NEXT: and t4, t4, a1
-; ZVFHMIN64-NEXT: and t0, t0, a1
-; ZVFHMIN64-NEXT: and t1, t1, a2
-; ZVFHMIN64-NEXT: or t0, t1, t0
-; ZVFHMIN64-NEXT: sh t0, 428(sp)
-; ZVFHMIN64-NEXT: lhu t0, 298(sp)
-; ZVFHMIN64-NEXT: lhu t1, 170(sp)
-; ZVFHMIN64-NEXT: and t3, t3, a2
-; ZVFHMIN64-NEXT: or t3, t3, t4
-; ZVFHMIN64-NEXT: and t0, t0, a1
-; ZVFHMIN64-NEXT: and t1, t1, a2
-; ZVFHMIN64-NEXT: or t0, t1, t0
-; ZVFHMIN64-NEXT: sh t0, 426(sp)
-; ZVFHMIN64-NEXT: lhu t0, 296(sp)
-; ZVFHMIN64-NEXT: lhu t1, 168(sp)
-; ZVFHMIN64-NEXT: vmv.x.s t4, v0
-; ZVFHMIN64-NEXT: and t2, t2, a1
-; ZVFHMIN64-NEXT: and t0, t0, a1
-; ZVFHMIN64-NEXT: and t1, t1, a2
-; ZVFHMIN64-NEXT: or t0, t1, t0
-; ZVFHMIN64-NEXT: sh t0, 424(sp)
-; ZVFHMIN64-NEXT: lhu t0, 294(sp)
-; ZVFHMIN64-NEXT: lhu t1, 166(sp)
-; ZVFHMIN64-NEXT: and t5, t5, a2
-; ZVFHMIN64-NEXT: or t2, t5, t2
-; ZVFHMIN64-NEXT: and t0, t0, a1
-; ZVFHMIN64-NEXT: and t1, t1, a2
-; ZVFHMIN64-NEXT: or t0, t1, t0
-; ZVFHMIN64-NEXT: sh t0, 422(sp)
-; ZVFHMIN64-NEXT: lhu t0, 292(sp)
-; ZVFHMIN64-NEXT: lhu t1, 164(sp)
-; ZVFHMIN64-NEXT: vmv.x.s t5, v8
-; ZVFHMIN64-NEXT: and t4, t4, a1
-; ZVFHMIN64-NEXT: and t0, t0, a1
-; ZVFHMIN64-NEXT: and t1, t1, a2
-; ZVFHMIN64-NEXT: or t0, t1, t0
-; ZVFHMIN64-NEXT: sh t0, 420(sp)
-; ZVFHMIN64-NEXT: lhu t0, 290(sp)
-; ZVFHMIN64-NEXT: lhu t1, 162(sp)
-; ZVFHMIN64-NEXT: and t5, t5, a2
-; ZVFHMIN64-NEXT: or t4, t5, t4
-; ZVFHMIN64-NEXT: and t0, t0, a1
-; ZVFHMIN64-NEXT: and t1, t1, a2
-; ZVFHMIN64-NEXT: or t0, t1, t0
-; ZVFHMIN64-NEXT: sh t0, 418(sp)
-; ZVFHMIN64-NEXT: lhu t0, 288(sp)
-; ZVFHMIN64-NEXT: lhu t1, 160(sp)
-; ZVFHMIN64-NEXT: sh a4, 408(sp)
-; ZVFHMIN64-NEXT: sh a5, 410(sp)
-; ZVFHMIN64-NEXT: sh a7, 412(sp)
-; ZVFHMIN64-NEXT: sh a3, 414(sp)
-; ZVFHMIN64-NEXT: sh t4, 400(sp)
-; ZVFHMIN64-NEXT: sh t2, 402(sp)
-; ZVFHMIN64-NEXT: sh t3, 404(sp)
-; ZVFHMIN64-NEXT: sh a6, 406(sp)
-; ZVFHMIN64-NEXT: and a1, t0, a1
-; ZVFHMIN64-NEXT: and a2, t1, a2
-; ZVFHMIN64-NEXT: or a1, a2, a1
-; ZVFHMIN64-NEXT: sh a1, 416(sp)
-; ZVFHMIN64-NEXT: addi a1, sp, 384
-; ZVFHMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN64-NEXT: vle16.v v8, (a1)
-; ZVFHMIN64-NEXT: addi sp, s0, -656
-; ZVFHMIN64-NEXT: .cfi_def_cfa sp, 656
-; ZVFHMIN64-NEXT: ld ra, 648(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: ld s0, 640(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: ld s1, 632(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: ld s2, 624(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: ld s3, 616(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: ld s4, 608(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: ld s5, 600(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: ld s6, 592(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: ld s7, 584(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: ld s8, 576(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: ld s9, 568(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: ld s10, 560(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: ld s11, 552(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: .cfi_restore ra
-; ZVFHMIN64-NEXT: .cfi_restore s0
-; ZVFHMIN64-NEXT: .cfi_restore s1
-; ZVFHMIN64-NEXT: .cfi_restore s2
-; ZVFHMIN64-NEXT: .cfi_restore s3
-; ZVFHMIN64-NEXT: .cfi_restore s4
-; ZVFHMIN64-NEXT: .cfi_restore s5
-; ZVFHMIN64-NEXT: .cfi_restore s6
-; ZVFHMIN64-NEXT: .cfi_restore s7
-; ZVFHMIN64-NEXT: .cfi_restore s8
-; ZVFHMIN64-NEXT: .cfi_restore s9
-; ZVFHMIN64-NEXT: .cfi_restore s10
-; ZVFHMIN64-NEXT: .cfi_restore s11
-; ZVFHMIN64-NEXT: addi sp, sp, 656
-; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 0
-; ZVFHMIN64-NEXT: ret
+; CHECK-LABEL: copysign_v64f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 64
+; CHECK-NEXT: lui a1, 8
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: vand.vx v16, v16, a1
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: vand.vx v8, v8, a1
+; CHECK-NEXT: vor.vv v8, v8, v16
+; CHECK-NEXT: ret
%r = call <64 x half> @llvm.copysign.v64f16(<64 x half> %vm, <64 x half> %vs)
ret <64 x half> %r
}
>From 47f9aafa747ef34e3db0a9948e7ca31d85718055 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Fri, 24 Apr 2026 14:59:39 +0800
Subject: [PATCH 03/10] fixup! improve heuristic check
---
.../SelectionDAG/LegalizeVectorOps.cpp | 21 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 34 +--
llvm/test/CodeGen/NVPTX/f16x2-instructions.ll | 205 ++++++------------
llvm/test/CodeGen/Thumb2/mve-fmath.ll | 166 ++++----------
4 files changed, 118 insertions(+), 308 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index ccad9354fc820..2c8783aef369b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -2136,10 +2136,23 @@ SDValue VectorLegalizer::ExpandFCOPYSIGN(SDNode *Node) {
!TLI.isOperationLegalOrCustom(ISD::OR, IntVT))
return SDValue();
- // FIXME: The FSUB check is here to force unrolling v1f64 vectors on AArch64.
- if (!TLI.isOperationLegalOrCustomOrPromote(ISD::FSUB, VT) &&
- !VT.isScalableVector())
- return SDValue();
+ // Heuristic check to determine whether vector should be expanded to integer
+ // operations or unroll to scalar operations.
+ // 1. Scalable vector is never unrolled.
+ // 2. Fixed vectors is unrolled if one of following is true:
+ // a. Vector only has 1 element and target know how to handle scalar
+ // FOPYSIGN(either legal or custom expand).
+ // b. Vector has more than 1 elements and target supports scalar
+ // FCOPYSIGN natively and vector length <= 3(2 AND + 1 OR).
+ if (VT.isFixedLengthVector()) {
+ EVT EltVT = VT.getScalarType();
+ if ((VT.getVectorNumElements() == 1 &&
+ TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, EltVT)) ||
+ (VT.getVectorNumElements() < 4 &&
+ TLI.isOperationLegal(ISD::FCOPYSIGN, EltVT) &&
+ TLI.isExtractVecEltCheap(VT, 0)))
+ return SDValue();
+ }
SDLoc DL(Node);
SDValue Mag = DAG.getNode(ISD::BITCAST, DL, IntVT, Node->getOperand(0));
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d0e8dfc0e3259..4d5013c709e23 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1679,7 +1679,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
}
setOperationAction(ISD::FNEG, VT, Expand);
setOperationAction(ISD::FABS, VT, Expand);
- setOperationAction(ISD::FCOPYSIGN, VT, Custom);
+ setOperationAction(ISD::FCOPYSIGN, VT, Expand);
MVT F32VecVT = MVT::getVectorVT(MVT::f32, VT.getVectorElementCount());
// Don't promote f16 vector operations to f32 if f32 vector type is
// not legal.
@@ -1709,8 +1709,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ZvfbfaOps, VT, Custom);
setOperationAction(ZvfbfaVPOps, VT, Custom);
setCondCodeAction(VFPCCToExpand, VT, Expand);
- } else {
- setOperationAction(ISD::FCOPYSIGN, VT, Custom);
}
setOperationAction(
{ISD::VP_MERGE, ISD::VP_SELECT, ISD::VSELECT, ISD::SELECT}, VT,
@@ -7492,28 +7490,6 @@ static SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG,
return DAG.getNode(RISCVISD::FMV_H_X, DL, VT, CopiedSign);
}
-static SDValue expandVectorFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
- SDLoc DL(Op);
- MVT VT = Op.getSimpleValueType();
- MVT IntVT = VT.changeVectorElementTypeToInteger();
-
- SDValue Mag = DAG.getNode(ISD::BITCAST, DL, IntVT, Op.getOperand(0));
- SDValue Sign = DAG.getNode(ISD::BITCAST, DL, IntVT, Op.getOperand(1));
-
- SDValue SignMask = DAG.getConstant(
- APInt::getSignMask(IntVT.getScalarSizeInBits()), DL, IntVT);
- SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, Sign, SignMask);
-
- SDValue ClearSignMask = DAG.getConstant(
- APInt::getSignedMaxValue(IntVT.getScalarSizeInBits()), DL, IntVT);
- SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, Mag, ClearSignMask);
-
- SDValue CopiedSign = DAG.getNode(ISD::OR, DL, IntVT, ClearedSign, SignBit,
- SDNodeFlags::Disjoint);
-
- return DAG.getNode(ISD::BITCAST, DL, VT, CopiedSign);
-}
-
/// Get a RISC-V target specified VL op for a given SDNode.
static unsigned getRISCVVLOp(SDValue Op) {
#define OP_CASE(NODE) \
@@ -8975,18 +8951,12 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
SDValue CLMUL = DAG.getNode(ISD::CLMUL, DL, I64VecVT, Op0, Op1);
return DAG.getNode(ISD::TRUNCATE, DL, VT, CLMUL);
}
- case ISD::FCOPYSIGN: {
+ case ISD::FCOPYSIGN:
if (Op.getValueType() == MVT::f16 || Op.getValueType() == MVT::bf16)
return lowerFCOPYSIGN(Op, DAG, Subtarget);
- MVT EltVT = Op.getSimpleValueType().getVectorElementType();
- // zvfhmin f16 and zvfbfmin bf16 vectors have no native vfsgnj
- if ((EltVT == MVT::f16 && !Subtarget.hasVInstructionsF16()) ||
- (EltVT == MVT::bf16 && !Subtarget.hasVInstructionsBF16()))
- return expandVectorFCOPYSIGN(Op, DAG);
if (isPromotedOpNeedingSplit(Op, Subtarget, *this))
return SplitVectorOp(Op, DAG);
return lowerToScalableOp(Op, DAG);
- }
case ISD::STRICT_FADD:
case ISD::STRICT_FSUB:
case ISD::STRICT_FMUL:
diff --git a/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll b/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
index 3ebaf68d4a15f..5bb6b2bff0c49 100644
--- a/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
@@ -1878,167 +1878,84 @@ define <2 x half> @test_maxnum(<2 x half> %a, <2 x half> %b) #0 {
}
define <2 x half> @test_copysign(<2 x half> %a, <2 x half> %b) #0 {
-; CHECK-F16-LABEL: test_copysign(
-; CHECK-F16: {
-; CHECK-F16-NEXT: .reg .b32 %r<6>;
-; CHECK-F16-EMPTY:
-; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_copysign_param_1];
-; CHECK-F16-NEXT: ld.param.b32 %r1, [test_copysign_param_0];
-; CHECK-F16-NEXT: and.b32 %r3, %r2, -2147450880;
-; CHECK-F16-NEXT: and.b32 %r4, %r1, 2147450879;
-; CHECK-F16-NEXT: or.b32 %r5, %r4, %r3;
-; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r5;
-; CHECK-F16-NEXT: ret;
-;
-; CHECK-NOF16-LABEL: test_copysign(
-; CHECK-NOF16: {
-; CHECK-NOF16-NEXT: .reg .b16 %rs<11>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
-; CHECK-NOF16-EMPTY:
-; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_copysign_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_copysign_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NOF16-NEXT: and.b16 %rs3, %rs2, -32768;
-; CHECK-NOF16-NEXT: mov.b32 {%rs4, %rs5}, %r1;
-; CHECK-NOF16-NEXT: and.b16 %rs6, %rs5, 32767;
-; CHECK-NOF16-NEXT: or.b16 %rs7, %rs6, %rs3;
-; CHECK-NOF16-NEXT: and.b16 %rs8, %rs1, -32768;
-; CHECK-NOF16-NEXT: and.b16 %rs9, %rs4, 32767;
-; CHECK-NOF16-NEXT: or.b16 %rs10, %rs9, %rs8;
-; CHECK-NOF16-NEXT: st.param.v2.b16 [func_retval0], {%rs10, %rs7};
-; CHECK-NOF16-NEXT: ret;
+; CHECK-LABEL: test_copysign(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<6>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r2, [test_copysign_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_copysign_param_0];
+; CHECK-NEXT: and.b32 %r3, %r2, -2147450880;
+; CHECK-NEXT: and.b32 %r4, %r1, 2147450879;
+; CHECK-NEXT: or.b32 %r5, %r4, %r3;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r5;
+; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.copysign.f16(<2 x half> %a, <2 x half> %b)
ret <2 x half> %r
}
define <2 x half> @test_copysign_f32(<2 x half> %a, <2 x float> %b) #0 {
-; CHECK-F16-LABEL: test_copysign_f32(
-; CHECK-F16: {
-; CHECK-F16-NEXT: .reg .b16 %rs<3>;
-; CHECK-F16-NEXT: .reg .b32 %r<8>;
-; CHECK-F16-EMPTY:
-; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.v2.b32 {%r2, %r3}, [test_copysign_f32_param_1];
-; CHECK-F16-NEXT: ld.param.b32 %r1, [test_copysign_f32_param_0];
-; CHECK-F16-NEXT: cvt.rn.f16.f32 %rs1, %r3;
-; CHECK-F16-NEXT: cvt.rn.f16.f32 %rs2, %r2;
-; CHECK-F16-NEXT: mov.b32 %r4, {%rs2, %rs1};
-; CHECK-F16-NEXT: and.b32 %r5, %r4, -2147450880;
-; CHECK-F16-NEXT: and.b32 %r6, %r1, 2147450879;
-; CHECK-F16-NEXT: or.b32 %r7, %r6, %r5;
-; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r7;
-; CHECK-F16-NEXT: ret;
-;
-; CHECK-NOF16-LABEL: test_copysign_f32(
-; CHECK-NOF16: {
-; CHECK-NOF16-NEXT: .reg .b16 %rs<9>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<6>;
-; CHECK-NOF16-EMPTY:
-; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.v2.b32 {%r2, %r3}, [test_copysign_f32_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_copysign_f32_param_0];
-; CHECK-NOF16-NEXT: and.b32 %r4, %r3, -2147483648;
-; CHECK-NOF16-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r4; }
-; CHECK-NOF16-NEXT: mov.b32 {%rs2, %rs3}, %r1;
-; CHECK-NOF16-NEXT: and.b16 %rs4, %rs3, 32767;
-; CHECK-NOF16-NEXT: or.b16 %rs5, %rs4, %rs1;
-; CHECK-NOF16-NEXT: and.b32 %r5, %r2, -2147483648;
-; CHECK-NOF16-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs6}, %r5; }
-; CHECK-NOF16-NEXT: and.b16 %rs7, %rs2, 32767;
-; CHECK-NOF16-NEXT: or.b16 %rs8, %rs7, %rs6;
-; CHECK-NOF16-NEXT: st.param.v2.b16 [func_retval0], {%rs8, %rs5};
-; CHECK-NOF16-NEXT: ret;
+; CHECK-LABEL: test_copysign_f32(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<8>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.v2.b32 {%r2, %r3}, [test_copysign_f32_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_copysign_f32_param_0];
+; CHECK-NEXT: cvt.rn.f16.f32 %rs1, %r3;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs2, %r2;
+; CHECK-NEXT: mov.b32 %r4, {%rs2, %rs1};
+; CHECK-NEXT: and.b32 %r5, %r4, -2147450880;
+; CHECK-NEXT: and.b32 %r6, %r1, 2147450879;
+; CHECK-NEXT: or.b32 %r7, %r6, %r5;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-NEXT: ret;
%tb = fptrunc <2 x float> %b to <2 x half>
%r = call <2 x half> @llvm.copysign.f16(<2 x half> %a, <2 x half> %tb)
ret <2 x half> %r
}
define <2 x half> @test_copysign_f64(<2 x half> %a, <2 x double> %b) #0 {
-; CHECK-F16-LABEL: test_copysign_f64(
-; CHECK-F16: {
-; CHECK-F16-NEXT: .reg .b16 %rs<3>;
-; CHECK-F16-NEXT: .reg .b32 %r<6>;
-; CHECK-F16-NEXT: .reg .b64 %rd<3>;
-; CHECK-F16-EMPTY:
-; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_copysign_f64_param_1];
-; CHECK-F16-NEXT: ld.param.b32 %r1, [test_copysign_f64_param_0];
-; CHECK-F16-NEXT: cvt.rn.f16.f64 %rs1, %rd2;
-; CHECK-F16-NEXT: cvt.rn.f16.f64 %rs2, %rd1;
-; CHECK-F16-NEXT: mov.b32 %r2, {%rs2, %rs1};
-; CHECK-F16-NEXT: and.b32 %r3, %r2, -2147450880;
-; CHECK-F16-NEXT: and.b32 %r4, %r1, 2147450879;
-; CHECK-F16-NEXT: or.b32 %r5, %r4, %r3;
-; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r5;
-; CHECK-F16-NEXT: ret;
-;
-; CHECK-NOF16-LABEL: test_copysign_f64(
-; CHECK-NOF16: {
-; CHECK-NOF16-NEXT: .reg .b16 %rs<9>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<2>;
-; CHECK-NOF16-NEXT: .reg .b64 %rd<7>;
-; CHECK-NOF16-EMPTY:
-; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_copysign_f64_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_copysign_f64_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NOF16-NEXT: and.b16 %rs3, %rs2, 32767;
-; CHECK-NOF16-NEXT: and.b64 %rd3, %rd2, -9223372036854775808;
-; CHECK-NOF16-NEXT: shr.u64 %rd4, %rd3, 48;
-; CHECK-NOF16-NEXT: cvt.u16.u64 %rs4, %rd4;
-; CHECK-NOF16-NEXT: or.b16 %rs5, %rs3, %rs4;
-; CHECK-NOF16-NEXT: and.b16 %rs6, %rs1, 32767;
-; CHECK-NOF16-NEXT: and.b64 %rd5, %rd1, -9223372036854775808;
-; CHECK-NOF16-NEXT: shr.u64 %rd6, %rd5, 48;
-; CHECK-NOF16-NEXT: cvt.u16.u64 %rs7, %rd6;
-; CHECK-NOF16-NEXT: or.b16 %rs8, %rs6, %rs7;
-; CHECK-NOF16-NEXT: st.param.v2.b16 [func_retval0], {%rs8, %rs5};
-; CHECK-NOF16-NEXT: ret;
+; CHECK-LABEL: test_copysign_f64(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<6>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_copysign_f64_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_copysign_f64_param_0];
+; CHECK-NEXT: cvt.rn.f16.f64 %rs1, %rd2;
+; CHECK-NEXT: cvt.rn.f16.f64 %rs2, %rd1;
+; CHECK-NEXT: mov.b32 %r2, {%rs2, %rs1};
+; CHECK-NEXT: and.b32 %r3, %r2, -2147450880;
+; CHECK-NEXT: and.b32 %r4, %r1, 2147450879;
+; CHECK-NEXT: or.b32 %r5, %r4, %r3;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r5;
+; CHECK-NEXT: ret;
%tb = fptrunc <2 x double> %b to <2 x half>
%r = call <2 x half> @llvm.copysign.f16(<2 x half> %a, <2 x half> %tb)
ret <2 x half> %r
}
define <2 x float> @test_copysign_extended(<2 x half> %a, <2 x half> %b) #0 {
-; CHECK-F16-LABEL: test_copysign_extended(
-; CHECK-F16: {
-; CHECK-F16-NEXT: .reg .b16 %rs<3>;
-; CHECK-F16-NEXT: .reg .b32 %r<8>;
-; CHECK-F16-EMPTY:
-; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_copysign_extended_param_1];
-; CHECK-F16-NEXT: ld.param.b32 %r1, [test_copysign_extended_param_0];
-; CHECK-F16-NEXT: and.b32 %r3, %r2, -2147450880;
-; CHECK-F16-NEXT: and.b32 %r4, %r1, 2147450879;
-; CHECK-F16-NEXT: or.b32 %r5, %r4, %r3;
-; CHECK-F16-NEXT: mov.b32 {%rs1, %rs2}, %r5;
-; CHECK-F16-NEXT: cvt.f32.f16 %r6, %rs2;
-; CHECK-F16-NEXT: cvt.f32.f16 %r7, %rs1;
-; CHECK-F16-NEXT: st.param.v2.b32 [func_retval0], {%r7, %r6};
-; CHECK-F16-NEXT: ret;
-;
-; CHECK-NOF16-LABEL: test_copysign_extended(
-; CHECK-NOF16: {
-; CHECK-NOF16-NEXT: .reg .b16 %rs<11>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
-; CHECK-NOF16-EMPTY:
-; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_copysign_extended_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_copysign_extended_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NOF16-NEXT: and.b16 %rs3, %rs1, -32768;
-; CHECK-NOF16-NEXT: mov.b32 {%rs4, %rs5}, %r1;
-; CHECK-NOF16-NEXT: and.b16 %rs6, %rs4, 32767;
-; CHECK-NOF16-NEXT: or.b16 %rs7, %rs6, %rs3;
-; CHECK-NOF16-NEXT: and.b16 %rs8, %rs2, -32768;
-; CHECK-NOF16-NEXT: and.b16 %rs9, %rs5, 32767;
-; CHECK-NOF16-NEXT: or.b16 %rs10, %rs9, %rs8;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs10;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs7;
-; CHECK-NOF16-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
-; CHECK-NOF16-NEXT: ret;
+; CHECK-LABEL: test_copysign_extended(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<8>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r2, [test_copysign_extended_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_copysign_extended_param_0];
+; CHECK-NEXT: and.b32 %r3, %r2, -2147450880;
+; CHECK-NEXT: and.b32 %r4, %r1, 2147450879;
+; CHECK-NEXT: or.b32 %r5, %r4, %r3;
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r5;
+; CHECK-NEXT: cvt.f32.f16 %r6, %rs2;
+; CHECK-NEXT: cvt.f32.f16 %r7, %rs1;
+; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r7, %r6};
+; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.copysign.f16(<2 x half> %a, <2 x half> %b)
%xr = fpext <2 x half> %r to <2 x float>
ret <2 x float> %xr
diff --git a/llvm/test/CodeGen/Thumb2/mve-fmath.ll b/llvm/test/CodeGen/Thumb2/mve-fmath.ll
index ad8921d2f7b02..7da8b746c0ce3 100644
--- a/llvm/test/CodeGen/Thumb2/mve-fmath.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-fmath.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,FULLFP16
-; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,MVEFP
-; RUN: llc -early-live-intervals -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,FULLFP16
-; RUN: llc -early-live-intervals -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,MVEFP
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -early-live-intervals -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -early-live-intervals -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK
define arm_aapcs_vfpcc <4 x float> @sqrt_float32_t(<4 x float> %src) {
; CHECK-LABEL: sqrt_float32_t:
@@ -1091,123 +1091,26 @@ entry:
}
define arm_aapcs_vfpcc <4 x float> @copysign_float32_t(<4 x float> %src1, <4 x float> %src2) {
-; FULLFP16-LABEL: copysign_float32_t:
-; FULLFP16: @ %bb.0: @ %entry
-; FULLFP16-NEXT: .save {r4, r5, r7, lr}
-; FULLFP16-NEXT: push {r4, r5, r7, lr}
-; FULLFP16-NEXT: vmov r12, r1, d2
-; FULLFP16-NEXT: vmov r2, lr, d3
-; FULLFP16-NEXT: vmov r3, r0, d0
-; FULLFP16-NEXT: vmov r4, r5, d1
-; FULLFP16-NEXT: lsrs r1, r1, #31
-; FULLFP16-NEXT: bfi r0, r1, #31, #1
-; FULLFP16-NEXT: lsrs r1, r2, #31
-; FULLFP16-NEXT: bfi r4, r1, #31, #1
-; FULLFP16-NEXT: lsr.w r1, lr, #31
-; FULLFP16-NEXT: bfi r5, r1, #31, #1
-; FULLFP16-NEXT: lsr.w r1, r12, #31
-; FULLFP16-NEXT: bfi r3, r1, #31, #1
-; FULLFP16-NEXT: vmov s2, r4
-; FULLFP16-NEXT: vmov s3, r5
-; FULLFP16-NEXT: vmov s1, r0
-; FULLFP16-NEXT: vmov s0, r3
-; FULLFP16-NEXT: pop {r4, r5, r7, pc}
-;
-; MVEFP-LABEL: copysign_float32_t:
-; MVEFP: @ %bb.0: @ %entry
-; MVEFP-NEXT: vmov.i32 q2, #0x80000000
-; MVEFP-NEXT: vbic.i32 q0, #0x80000000
-; MVEFP-NEXT: vand q1, q1, q2
-; MVEFP-NEXT: vorr q0, q0, q1
-; MVEFP-NEXT: bx lr
+; CHECK-LABEL: copysign_float32_t:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.i32 q2, #0x80000000
+; CHECK-NEXT: vbic.i32 q0, #0x80000000
+; CHECK-NEXT: vand q1, q1, q2
+; CHECK-NEXT: vorr q0, q0, q1
+; CHECK-NEXT: bx lr
entry:
%0 = call fast <4 x float> @llvm.copysign.v4f32(<4 x float> %src1, <4 x float> %src2)
ret <4 x float> %0
}
define arm_aapcs_vfpcc <8 x half> @copysign_float16_t(<8 x half> %src1, <8 x half> %src2) {
-; FULLFP16-LABEL: copysign_float16_t:
-; FULLFP16: @ %bb.0: @ %entry
-; FULLFP16-NEXT: .pad #32
-; FULLFP16-NEXT: sub sp, #32
-; FULLFP16-NEXT: vmovx.f16 s8, s4
-; FULLFP16-NEXT: vstr.16 s8, [sp, #24]
-; FULLFP16-NEXT: vstr.16 s4, [sp, #28]
-; FULLFP16-NEXT: vmovx.f16 s4, s5
-; FULLFP16-NEXT: vstr.16 s4, [sp, #16]
-; FULLFP16-NEXT: vmovx.f16 s4, s6
-; FULLFP16-NEXT: vstr.16 s5, [sp, #20]
-; FULLFP16-NEXT: vstr.16 s4, [sp, #8]
-; FULLFP16-NEXT: vmovx.f16 s4, s7
-; FULLFP16-NEXT: vstr.16 s6, [sp, #12]
-; FULLFP16-NEXT: vstr.16 s4, [sp]
-; FULLFP16-NEXT: vstr.16 s7, [sp, #4]
-; FULLFP16-NEXT: ldrb.w r0, [sp, #25]
-; FULLFP16-NEXT: vmovx.f16 s4, s0
-; FULLFP16-NEXT: vabs.f16 s4, s4
-; FULLFP16-NEXT: vneg.f16 s6, s4
-; FULLFP16-NEXT: lsls r0, r0, #24
-; FULLFP16-NEXT: it pl
-; FULLFP16-NEXT: vmovpl.f32 s6, s4
-; FULLFP16-NEXT: ldrb.w r0, [sp, #29]
-; FULLFP16-NEXT: vabs.f16 s4, s0
-; FULLFP16-NEXT: vneg.f16 s0, s4
-; FULLFP16-NEXT: lsls r0, r0, #24
-; FULLFP16-NEXT: it pl
-; FULLFP16-NEXT: vmovpl.f32 s0, s4
-; FULLFP16-NEXT: ldrb.w r0, [sp, #17]
-; FULLFP16-NEXT: vmovx.f16 s4, s1
-; FULLFP16-NEXT: vabs.f16 s4, s4
-; FULLFP16-NEXT: vins.f16 s0, s6
-; FULLFP16-NEXT: vneg.f16 s6, s4
-; FULLFP16-NEXT: lsls r0, r0, #24
-; FULLFP16-NEXT: it pl
-; FULLFP16-NEXT: vmovpl.f32 s6, s4
-; FULLFP16-NEXT: ldrb.w r0, [sp, #21]
-; FULLFP16-NEXT: vabs.f16 s4, s1
-; FULLFP16-NEXT: vneg.f16 s1, s4
-; FULLFP16-NEXT: lsls r0, r0, #24
-; FULLFP16-NEXT: it pl
-; FULLFP16-NEXT: vmovpl.f32 s1, s4
-; FULLFP16-NEXT: ldrb.w r0, [sp, #9]
-; FULLFP16-NEXT: vmovx.f16 s4, s2
-; FULLFP16-NEXT: vabs.f16 s4, s4
-; FULLFP16-NEXT: vins.f16 s1, s6
-; FULLFP16-NEXT: vneg.f16 s6, s4
-; FULLFP16-NEXT: lsls r0, r0, #24
-; FULLFP16-NEXT: it pl
-; FULLFP16-NEXT: vmovpl.f32 s6, s4
-; FULLFP16-NEXT: ldrb.w r0, [sp, #13]
-; FULLFP16-NEXT: vabs.f16 s4, s2
-; FULLFP16-NEXT: vneg.f16 s2, s4
-; FULLFP16-NEXT: lsls r0, r0, #24
-; FULLFP16-NEXT: it pl
-; FULLFP16-NEXT: vmovpl.f32 s2, s4
-; FULLFP16-NEXT: ldrb.w r0, [sp, #1]
-; FULLFP16-NEXT: vmovx.f16 s4, s3
-; FULLFP16-NEXT: vabs.f16 s4, s4
-; FULLFP16-NEXT: vins.f16 s2, s6
-; FULLFP16-NEXT: vneg.f16 s6, s4
-; FULLFP16-NEXT: lsls r0, r0, #24
-; FULLFP16-NEXT: it pl
-; FULLFP16-NEXT: vmovpl.f32 s6, s4
-; FULLFP16-NEXT: ldrb.w r0, [sp, #5]
-; FULLFP16-NEXT: vabs.f16 s4, s3
-; FULLFP16-NEXT: vneg.f16 s3, s4
-; FULLFP16-NEXT: lsls r0, r0, #24
-; FULLFP16-NEXT: it pl
-; FULLFP16-NEXT: vmovpl.f32 s3, s4
-; FULLFP16-NEXT: vins.f16 s3, s6
-; FULLFP16-NEXT: add sp, #32
-; FULLFP16-NEXT: bx lr
-;
-; MVEFP-LABEL: copysign_float16_t:
-; MVEFP: @ %bb.0: @ %entry
-; MVEFP-NEXT: vmov.i16 q2, #0x8000
-; MVEFP-NEXT: vbic.i16 q0, #0x8000
-; MVEFP-NEXT: vand q1, q1, q2
-; MVEFP-NEXT: vorr q0, q0, q1
-; MVEFP-NEXT: bx lr
+; CHECK-LABEL: copysign_float16_t:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.i16 q2, #0x8000
+; CHECK-NEXT: vbic.i16 q0, #0x8000
+; CHECK-NEXT: vand q1, q1, q2
+; CHECK-NEXT: vorr q0, q0, q1
+; CHECK-NEXT: bx lr
entry:
%0 = call fast <8 x half> @llvm.copysign.v8f16(<8 x half> %src1, <8 x half> %src2)
ret <8 x half> %0
@@ -1216,19 +1119,26 @@ entry:
define arm_aapcs_vfpcc <2 x double> @copysign_float64_t(<2 x double> %src1, <2 x double> %src2) {
; CHECK-LABEL: copysign_float64_t:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r7, lr}
-; CHECK-NEXT: push {r7, lr}
-; CHECK-NEXT: vmov r0, r1, d3
-; CHECK-NEXT: vmov r0, lr, d2
-; CHECK-NEXT: vmov r0, r3, d1
-; CHECK-NEXT: vmov r12, r2, d0
-; CHECK-NEXT: lsrs r1, r1, #31
-; CHECK-NEXT: bfi r3, r1, #31, #1
-; CHECK-NEXT: lsr.w r1, lr, #31
-; CHECK-NEXT: bfi r2, r1, #31, #1
-; CHECK-NEXT: vmov d1, r0, r3
-; CHECK-NEXT: vmov d0, r12, r2
-; CHECK-NEXT: pop {r7, pc}
+; CHECK-NEXT: adr r1, .LCPI32_1
+; CHECK-NEXT: adr r0, .LCPI32_0
+; CHECK-NEXT: vldrw.u32 q2, [r1]
+; CHECK-NEXT: vand q1, q1, q2
+; CHECK-NEXT: vldrw.u32 q2, [r0]
+; CHECK-NEXT: vand q0, q0, q2
+; CHECK-NEXT: vorr q0, q0, q1
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI32_0:
+; CHECK-NEXT: .long 4294967295 @ 0xffffffff
+; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
+; CHECK-NEXT: .long 4294967295 @ 0xffffffff
+; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
+; CHECK-NEXT: .LCPI32_1:
+; CHECK-NEXT: .long 0 @ 0x0
+; CHECK-NEXT: .long 2147483648 @ 0x80000000
+; CHECK-NEXT: .long 0 @ 0x0
+; CHECK-NEXT: .long 2147483648 @ 0x80000000
entry:
%0 = call fast <2 x double> @llvm.copysign.v2f64(<2 x double> %src1, <2 x double> %src2)
ret <2 x double> %0
>From 71cb33fbba242db30e5e70a39083358f429797cc Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Sat, 25 Apr 2026 21:09:52 +0800
Subject: [PATCH 04/10] fixup! grammar and getVectorElementType
---
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 2c8783aef369b..fc020830f0eab 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -2137,15 +2137,15 @@ SDValue VectorLegalizer::ExpandFCOPYSIGN(SDNode *Node) {
return SDValue();
// Heuristic check to determine whether vector should be expanded to integer
- // operations or unroll to scalar operations.
+ // operations or unrolled to scalar operations.
// 1. Scalable vector is never unrolled.
- // 2. Fixed vectors is unrolled if one of following is true:
- // a. Vector only has 1 element and target know how to handle scalar
+ // 2. Fixed vector is unrolled if one of followings is true:
+ // a. Vector only has 1 element and target knows how to handle scalar
// FOPYSIGN(either legal or custom expand).
- // b. Vector has more than 1 elements and target supports scalar
+ // b. Vector has more than 1 element and target supports scalar
// FCOPYSIGN natively and vector length <= 3(2 AND + 1 OR).
if (VT.isFixedLengthVector()) {
- EVT EltVT = VT.getScalarType();
+ EVT EltVT = VT.getVectorElementType();
if ((VT.getVectorNumElements() == 1 &&
TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, EltVT)) ||
(VT.getVectorNumElements() < 4 &&
>From 0af3ba88a8a53102e995fcfe18616b5c0bb8c17a Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Sat, 25 Apr 2026 21:26:19 +0800
Subject: [PATCH 05/10] fixup! relax unroll
---
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index fc020830f0eab..eddb04f9f9268 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -2141,13 +2141,13 @@ SDValue VectorLegalizer::ExpandFCOPYSIGN(SDNode *Node) {
// 1. Scalable vector is never unrolled.
// 2. Fixed vector is unrolled if one of followings is true:
// a. Vector only has 1 element and target knows how to handle scalar
- // FOPYSIGN(either legal or custom expand).
+ // FOPYSIGN(either legal or custom expand or promote).
// b. Vector has more than 1 element and target supports scalar
// FCOPYSIGN natively and vector length <= 3(2 AND + 1 OR).
if (VT.isFixedLengthVector()) {
EVT EltVT = VT.getVectorElementType();
if ((VT.getVectorNumElements() == 1 &&
- TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, EltVT)) ||
+ TLI.isOperationLegalOrCustomOrPromote(ISD::FCOPYSIGN, EltVT)) ||
(VT.getVectorNumElements() < 4 &&
TLI.isOperationLegal(ISD::FCOPYSIGN, EltVT) &&
TLI.isExtractVecEltCheap(VT, 0)))
>From 0738f208207244c1b8de72e6ba36b3337b4166cc Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Wed, 29 Apr 2026 16:54:24 +0800
Subject: [PATCH 06/10] fixup! revise heuristic
---
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index eddb04f9f9268..2812003aea6e4 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -2143,12 +2143,13 @@ SDValue VectorLegalizer::ExpandFCOPYSIGN(SDNode *Node) {
// a. Vector only has 1 element and target knows how to handle scalar
// FOPYSIGN(either legal or custom expand or promote).
// b. Vector has more than 1 element and target supports scalar
- // FCOPYSIGN natively and vector length <= 3(2 AND + 1 OR).
+ // FCOPYSIGN natively and vector length <= 6(2 AND + 1 OR + 2 LUI + 1
+ // ADDI).
if (VT.isFixedLengthVector()) {
EVT EltVT = VT.getVectorElementType();
if ((VT.getVectorNumElements() == 1 &&
TLI.isOperationLegalOrCustomOrPromote(ISD::FCOPYSIGN, EltVT)) ||
- (VT.getVectorNumElements() < 4 &&
+ (VT.getVectorNumElements() < 7 &&
TLI.isOperationLegal(ISD::FCOPYSIGN, EltVT) &&
TLI.isExtractVecEltCheap(VT, 0)))
return SDValue();
>From d86cfff49f93117bae949c49477c659373d156b8 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Wed, 29 Apr 2026 17:03:44 +0800
Subject: [PATCH 07/10] fixup! revise heuristic
---
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 2812003aea6e4..c406314627503 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -2141,15 +2141,15 @@ SDValue VectorLegalizer::ExpandFCOPYSIGN(SDNode *Node) {
// 1. Scalable vector is never unrolled.
// 2. Fixed vector is unrolled if one of followings is true:
// a. Vector only has 1 element and target knows how to handle scalar
- // FOPYSIGN(either legal or custom expand or promote).
+ // FCOPYSIGN(either legal or custom expand or promote).
// b. Vector has more than 1 element and target supports scalar
- // FCOPYSIGN natively and vector length <= 6(2 AND + 1 OR + 2 LUI + 1
+ // FCOPYSIGN natively and vector length <= 5(2 AND + 1 OR + 1 LUI + 1
// ADDI).
if (VT.isFixedLengthVector()) {
EVT EltVT = VT.getVectorElementType();
if ((VT.getVectorNumElements() == 1 &&
TLI.isOperationLegalOrCustomOrPromote(ISD::FCOPYSIGN, EltVT)) ||
- (VT.getVectorNumElements() < 7 &&
+ (VT.getVectorNumElements() < 6 &&
TLI.isOperationLegal(ISD::FCOPYSIGN, EltVT) &&
TLI.isExtractVecEltCheap(VT, 0)))
return SDValue();
>From e46e5991501901deb9ca3847308c0932c2402a08 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Wed, 29 Apr 2026 17:27:05 +0800
Subject: [PATCH 08/10] fixup! revise heuristic
---
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index c406314627503..aa2339c4307ba 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -2143,8 +2143,9 @@ SDValue VectorLegalizer::ExpandFCOPYSIGN(SDNode *Node) {
// a. Vector only has 1 element and target knows how to handle scalar
// FCOPYSIGN(either legal or custom expand or promote).
// b. Vector has more than 1 element and target supports scalar
- // FCOPYSIGN natively and vector length <= 5(2 AND + 1 OR + 1 LUI + 1
- // ADDI).
+ // FCOPYSIGN natively and vector length <= 5(2 AND + 1 OR + 2 CONST).
+ // FIXME: Scalar construction instruction count varies in every architecture,
+ // here we assume 1 instruction for now.
if (VT.isFixedLengthVector()) {
EVT EltVT = VT.getVectorElementType();
if ((VT.getVectorNumElements() == 1 &&
>From fc573fe16b321695e0cd0755636b17d895adf32d Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Fri, 8 May 2026 14:41:20 +0800
Subject: [PATCH 09/10] fixup! update check
---
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index aa2339c4307ba..b3536e9e7d51f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -2152,7 +2152,7 @@ SDValue VectorLegalizer::ExpandFCOPYSIGN(SDNode *Node) {
TLI.isOperationLegalOrCustomOrPromote(ISD::FCOPYSIGN, EltVT)) ||
(VT.getVectorNumElements() < 6 &&
TLI.isOperationLegal(ISD::FCOPYSIGN, EltVT) &&
- TLI.isExtractVecEltCheap(VT, 0)))
+ TLI.isExtractVecEltCheap(VT, 0) && TLI.isExtractVecEltCheap(VT, 1)))
return SDValue();
}
>From 3c46915dcce127d63f66d19663329aac16908d55 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Fri, 8 May 2026 14:52:17 +0800
Subject: [PATCH 10/10] fixup! update check
---
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index b3536e9e7d51f..df86a163a247f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -2148,11 +2148,12 @@ SDValue VectorLegalizer::ExpandFCOPYSIGN(SDNode *Node) {
// here we assume 1 instruction for now.
if (VT.isFixedLengthVector()) {
EVT EltVT = VT.getVectorElementType();
- if ((VT.getVectorNumElements() == 1 &&
+ unsigned NumElts = VT.getVectorNumElements();
+ if ((NumElts == 1 &&
TLI.isOperationLegalOrCustomOrPromote(ISD::FCOPYSIGN, EltVT)) ||
- (VT.getVectorNumElements() < 6 &&
- TLI.isOperationLegal(ISD::FCOPYSIGN, EltVT) &&
- TLI.isExtractVecEltCheap(VT, 0) && TLI.isExtractVecEltCheap(VT, 1)))
+ (NumElts < 6 && TLI.isOperationLegal(ISD::FCOPYSIGN, EltVT) &&
+ TLI.isExtractVecEltCheap(VT, 0) &&
+ (NumElts == 1 || TLI.isExtractVecEltCheap(VT, 1))))
return SDValue();
}
More information about the llvm-commits
mailing list