[llvm] [WIP][DAG] visitFREEZE - always allow freezing multiple operands (PR #152107)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri May 8 03:22:41 PDT 2026
https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/152107
>From 5f4ac12959a45756999fd2255c3617820e04f397 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Tue, 5 Aug 2025 10:31:10 +0100
Subject: [PATCH] [WIP][DAG] visitFREEZE - always allow freezing multiple
operands
Remove the limited freeze multiple operand handling, always freeze all operands and rely on later visitFREEZE calls to merge frozen/unfrozen versions of each node to prevent infinite loops.
This also removes the special handling of frozen SRA/SRL nodes as most of the regressions are related
Fixes #149798
Fixes #150204
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 102 +-
llvm/test/CodeGen/AArch64/div-i256.ll | 64 +-
llvm/test/CodeGen/AArch64/icmp-ult-eq-fold.ll | 32 +-
llvm/test/CodeGen/AArch64/neon-dotreduce.ll | 851 +-
llvm/test/CodeGen/AMDGPU/bf16-conversions.ll | 4 +-
.../test/CodeGen/AMDGPU/carryout-selection.ll | 51 +-
llvm/test/CodeGen/AMDGPU/clmul.ll | 1616 +--
.../AMDGPU/divergence-driven-trunc-to-i1.ll | 9 +-
llvm/test/CodeGen/AMDGPU/fract-match.ll | 22 +-
llvm/test/CodeGen/AMDGPU/srem64.ll | 242 +-
.../test/CodeGen/AMDGPU/vector-reduce-smax.ll | 12 +-
.../test/CodeGen/AMDGPU/vector-reduce-smin.ll | 12 +-
.../test/CodeGen/AMDGPU/vector-reduce-umax.ll | 12 +-
.../test/CodeGen/AMDGPU/vector-reduce-umin.ll | 12 +-
llvm/test/CodeGen/NVPTX/i128.ll | 180 +-
llvm/test/CodeGen/RISCV/abds.ll | 104 +-
llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll | 72 +-
llvm/test/CodeGen/RISCV/clmul.ll | 948 +-
llvm/test/CodeGen/RISCV/clmulh.ll | 9687 +++++++++--------
llvm/test/CodeGen/RISCV/clmulr.ll | 9455 ++++++++--------
llvm/test/CodeGen/RISCV/idiv_large.ll | 346 +-
llvm/test/CodeGen/RISCV/rv64xtheadbb.ll | 12 +-
llvm/test/CodeGen/RISCV/rv64zbb.ll | 12 +-
.../RISCV/wide-scalar-shift-legalization.ll | 1901 ++--
llvm/test/CodeGen/SystemZ/pr60413.ll | 36 +-
llvm/test/CodeGen/X86/abds-neg.ll | 92 +-
llvm/test/CodeGen/X86/avg.ll | 156 +-
llvm/test/CodeGen/X86/bit-manip-i256.ll | 622 +-
llvm/test/CodeGen/X86/bit-manip-i512.ll | 832 +-
llvm/test/CodeGen/X86/clmul-vector.ll | 260 +-
llvm/test/CodeGen/X86/combine-add.ll | 4 +-
llvm/test/CodeGen/X86/div_i129_v_pow2k.ll | 16 +-
llvm/test/CodeGen/X86/freeze-binary.ll | 60 +-
llvm/test/CodeGen/X86/freeze-unary.ll | 2 +
llvm/test/CodeGen/X86/freeze-vector.ll | 24 +-
llvm/test/CodeGen/X86/freeze.ll | 17 +-
llvm/test/CodeGen/X86/midpoint-int-vec-512.ll | 126 +-
llvm/test/CodeGen/X86/pr120906.ll | 21 +-
.../test/CodeGen/X86/setcc-non-simple-type.ll | 4 +-
llvm/test/CodeGen/X86/shift-i128.ll | 10 +-
llvm/test/CodeGen/X86/shift-i512.ll | 137 +-
.../test/CodeGen/X86/vector-compare-all_of.ll | 29 +-
.../test/CodeGen/X86/vector-compare-any_of.ll | 20 +-
llvm/test/CodeGen/X86/vector-fshr-128.ll | 196 +-
llvm/test/CodeGen/X86/vector-fshr-256.ll | 60 +-
llvm/test/CodeGen/X86/vector-fshr-512.ll | 52 +-
.../CodeGen/X86/vector-shuffle-combining.ll | 18 +-
llvm/test/CodeGen/X86/vector-trunc-packus.ll | 262 +-
llvm/test/CodeGen/X86/vshift-6.ll | 3 +-
...ad-of-small-alloca-with-zero-upper-half.ll | 220 +-
.../CodeGen/X86/widen-load-of-small-alloca.ll | 220 +-
.../zero_extend_vector_inreg_of_broadcast.ll | 10 +-
52 files changed, 14531 insertions(+), 14736 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 15577af91ff03..a78b9d238fe3e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -17808,11 +17808,16 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {
if (SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT))
return CombineLD;
- // int_vt (bitcast (vec_vt (scalar_to_vector elt_vt:x)))
- // => int_vt (any_extend elt_vt:x)
- if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && VT.isScalarInteger()) {
+ if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
SDValue SrcScalar = N0.getOperand(0);
- if (SrcScalar.getValueType().isScalarInteger())
+
+ // remove scalar_to_vector if src/dst sizes match.
+ if (SrcScalar.getValueSizeInBits() == VT.getSizeInBits())
+ return DAG.getBitcast(VT, SrcScalar);
+
+ // int_vt (bitcast (vec_vt (scalar_to_vector elt_vt:x)))
+ // => int_vt (any_extend elt_vt:x)
+ if (VT.isScalarInteger() && SrcScalar.getValueType().isScalarInteger())
return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, SrcScalar);
}
@@ -17887,12 +17892,6 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
return FrozenN0;
}
- // We currently avoid folding freeze over SRA/SRL, due to the problems seen
- // with (freeze (assert ext)) blocking simplifications of SRA/SRL. See for
- // example https://reviews.llvm.org/D136529#4120959.
- if (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)
- return SDValue();
-
// Fold freeze(op(x, ...)) -> op(freeze(x), ...).
// Try to push freeze through instructions that propagate but don't produce
// poison as far as possible. If an operand of freeze follows three
@@ -17905,19 +17904,6 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
N0->getNumValues() != 1 || !N0->hasOneUse())
return SDValue();
- // TOOD: we should always allow multiple operands, however this increases the
- // likelihood of infinite loops due to the ReplaceAllUsesOfValueWith call
- // below causing later nodes that share frozen operands to fold again and no
- // longer being able to confirm other operands are not poison due to recursion
- // depth limits on isGuaranteedNotToBeUndefOrPoison.
- bool AllowMultipleMaybePoisonOperands =
- N0.getOpcode() == ISD::SELECT_CC || N0.getOpcode() == ISD::SETCC ||
- N0.getOpcode() == ISD::BUILD_VECTOR ||
- N0.getOpcode() == ISD::INSERT_SUBVECTOR ||
- N0.getOpcode() == ISD::BUILD_PAIR ||
- N0.getOpcode() == ISD::VECTOR_SHUFFLE ||
- N0.getOpcode() == ISD::CONCAT_VECTORS || N0.getOpcode() == ISD::FMUL;
-
// Avoid turning a BUILD_VECTOR that can be recognized as "all zeros", "all
// ones" or "constant" into something that depends on FrozenUndef. We can
// instead pick undef values to keep those properties, while at the same time
@@ -17938,75 +17924,13 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
}
}
- SmallSet<SDValue, 8> MaybePoisonOperands;
- SmallVector<unsigned, 8> MaybePoisonOperandNumbers;
- for (auto [OpNo, Op] : enumerate(N0->ops())) {
- if (DAG.isGuaranteedNotToBeUndefOrPoison(Op,
- UndefPoisonKind::UndefOrPoison))
- continue;
- bool HadMaybePoisonOperands = !MaybePoisonOperands.empty();
- bool IsNewMaybePoisonOperand = MaybePoisonOperands.insert(Op).second;
- if (IsNewMaybePoisonOperand)
- MaybePoisonOperandNumbers.push_back(OpNo);
- if (!HadMaybePoisonOperands)
- continue;
- if (IsNewMaybePoisonOperand && !AllowMultipleMaybePoisonOperands) {
- // Multiple maybe-poison ops when not allowed - bail out.
- return SDValue();
- }
- }
- // NOTE: the whole op may be not guaranteed to not be undef or poison because
- // it could create undef or poison due to it's poison-generating flags.
- // So not finding any maybe-poison operands is fine.
-
- for (unsigned OpNo : MaybePoisonOperandNumbers) {
- // N0 can mutate during iteration, so make sure to refetch the maybe poison
- // operands via the operand numbers. The typical scenario is that we have
- // something like this
- // t262: i32 = freeze t181
- // t150: i32 = ctlz_zero_undef t262
- // t184: i32 = ctlz_zero_undef t181
- // t268: i32 = select_cc t181, Constant:i32<0>, t184, t186, setne:ch
- // When freezing the t181 operand we get t262 back, and then the
- // ReplaceAllUsesOfValueWith call will not only replace t181 by t262, but
- // also recursively replace t184 by t150.
- SDValue MaybePoisonOperand = N->getOperand(0).getOperand(OpNo);
- // Don't replace every single UNDEF everywhere with frozen UNDEF, though.
- if (MaybePoisonOperand.isUndef())
- continue;
- // First, freeze each offending operand.
- SDValue FrozenMaybePoisonOperand = DAG.getFreeze(MaybePoisonOperand);
- // Then, change all other uses of unfrozen operand to use frozen operand.
- DAG.ReplaceAllUsesOfValueWith(MaybePoisonOperand, FrozenMaybePoisonOperand);
- if (FrozenMaybePoisonOperand.getOpcode() == ISD::FREEZE &&
- FrozenMaybePoisonOperand.getOperand(0) == FrozenMaybePoisonOperand) {
- // But, that also updated the use in the freeze we just created, thus
- // creating a cycle in a DAG. Let's undo that by mutating the freeze.
- DAG.UpdateNodeOperands(FrozenMaybePoisonOperand.getNode(),
- MaybePoisonOperand);
- }
-
- // This node has been merged with another.
- if (N->getOpcode() == ISD::DELETED_NODE)
- return SDValue(N, 0);
- }
-
- assert(N->getOpcode() != ISD::DELETED_NODE && "Node was deleted!");
-
- // The whole node may have been updated, so the value we were holding
- // may no longer be valid. Re-fetch the operand we're `freeze`ing.
- N0 = N->getOperand(0);
+ // Collect and freeze all operands.
+ SmallVector<SDValue> Ops(N0->ops());
+ for (auto &Op : Ops)
+ Op = DAG.getFreeze(Op);
// Finally, recreate the node, it's operands were updated to use
// frozen operands, so we just need to use it's "original" operands.
- SmallVector<SDValue> Ops(N0->ops());
- // TODO: ISD::UNDEF and ISD::POISON should get separate handling, but best
- // leave for a future patch.
- for (SDValue &Op : Ops) {
- if (Op.isUndef())
- Op = DAG.getFreeze(Op);
- }
-
SDLoc DL(N0);
// Special case handling for ShuffleVectorSDNode nodes.
diff --git a/llvm/test/CodeGen/AArch64/div-i256.ll b/llvm/test/CodeGen/AArch64/div-i256.ll
index 48ac1963f465a..bfb13d917e40c 100644
--- a/llvm/test/CodeGen/AArch64/div-i256.ll
+++ b/llvm/test/CodeGen/AArch64/div-i256.ll
@@ -214,17 +214,17 @@ define i256 @sdiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: sbcs x15, x9, x12
; CHECK-NEXT: eor x9, x3, x12
; CHECK-NEXT: clz x16, x14
-; CHECK-NEXT: sbcs x18, x8, x12
-; CHECK-NEXT: clz x17, x15
+; CHECK-NEXT: sbcs x17, x8, x12
+; CHECK-NEXT: clz x0, x15
; CHECK-NEXT: add x16, x16, #64
-; CHECK-NEXT: sbc x0, x9, x12
+; CHECK-NEXT: sbc x18, x9, x12
; CHECK-NEXT: subs x8, x10, x13
; CHECK-NEXT: eor x10, x6, x13
; CHECK-NEXT: sbcs x9, x11, x13
; CHECK-NEXT: eor x11, x7, x13
-; CHECK-NEXT: orr x1, x14, x18
+; CHECK-NEXT: orr x1, x14, x17
; CHECK-NEXT: sbcs x10, x10, x13
-; CHECK-NEXT: orr x4, x15, x0
+; CHECK-NEXT: orr x4, x15, x18
; CHECK-NEXT: clz x5, x8
; CHECK-NEXT: sbc x11, x11, x13
; CHECK-NEXT: orr x2, x8, x10
@@ -244,41 +244,41 @@ define i256 @sdiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: cmp x11, #0
; CHECK-NEXT: csel x1, x1, x3, ne
; CHECK-NEXT: cmp x9, #0
-; CHECK-NEXT: clz x3, x18
+; CHECK-NEXT: clz x3, x17
; CHECK-NEXT: csel x2, x2, x5, ne
; CHECK-NEXT: cmp x6, #0
; CHECK-NEXT: add x3, x3, #64
; CHECK-NEXT: add x2, x2, #128
-; CHECK-NEXT: clz x5, x0
+; CHECK-NEXT: clz x5, x18
; CHECK-NEXT: csel x1, x1, x2, ne
-; CHECK-NEXT: cmp x0, #0
+; CHECK-NEXT: cmp x18, #0
; CHECK-NEXT: csel x2, x5, x3, ne
; CHECK-NEXT: cmp x15, #0
-; CHECK-NEXT: orr x3, x18, x0
-; CHECK-NEXT: csel x16, x17, x16, ne
+; CHECK-NEXT: orr x3, x17, x18
+; CHECK-NEXT: csel x16, x0, x16, ne
; CHECK-NEXT: cmp x3, #0
; CHECK-NEXT: mov w3, #255 // =0xff
; CHECK-NEXT: add x16, x16, #128
; CHECK-NEXT: csel x16, x2, x16, ne
; CHECK-NEXT: subs x2, x1, x16
; CHECK-NEXT: ngcs x16, xzr
-; CHECK-NEXT: ngcs x17, xzr
+; CHECK-NEXT: ngcs x0, xzr
; CHECK-NEXT: ngc x1, xzr
; CHECK-NEXT: cmp x3, x2
; CHECK-NEXT: ngcs xzr, x16
-; CHECK-NEXT: ngcs xzr, x17
+; CHECK-NEXT: ngcs xzr, x0
; CHECK-NEXT: ngcs xzr, x1
; CHECK-NEXT: csinc w5, w4, wzr, hs
; CHECK-NEXT: cmp w5, #0
-; CHECK-NEXT: csel x13, xzr, x0, ne
-; CHECK-NEXT: csel x4, xzr, x18, ne
+; CHECK-NEXT: csel x13, xzr, x18, ne
+; CHECK-NEXT: csel x4, xzr, x17, ne
; CHECK-NEXT: csel x7, xzr, x15, ne
; CHECK-NEXT: csel x3, xzr, x14, ne
; CHECK-NEXT: tbnz w5, #0, .LBB1_6
; CHECK-NEXT: // %bb.1: // %_udiv-special-cases
; CHECK-NEXT: eor x5, x2, #0xff
; CHECK-NEXT: orr x6, x16, x1
-; CHECK-NEXT: orr x5, x5, x17
+; CHECK-NEXT: orr x5, x5, x0
; CHECK-NEXT: orr x5, x5, x6
; CHECK-NEXT: cbz x5, .LBB1_6
; CHECK-NEXT: // %bb.2: // %udiv-bb1
@@ -288,7 +288,7 @@ define i256 @sdiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: add x4, sp, #64
; CHECK-NEXT: sub x3, x13, x2
; CHECK-NEXT: add x4, x4, #32
-; CHECK-NEXT: stp x0, x29, [sp, #120] // 8-byte Folded Spill
+; CHECK-NEXT: stp x18, x29, [sp, #120] // 8-byte Folded Spill
; CHECK-NEXT: lsr x13, x3, #3
; CHECK-NEXT: stp x28, x27, [sp, #144] // 16-byte Folded Spill
; CHECK-NEXT: stp x26, x25, [sp, #160] // 16-byte Folded Spill
@@ -303,8 +303,8 @@ define i256 @sdiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: stp x14, x15, [sp, #96]
; CHECK-NEXT: mvn w20, w3
; CHECK-NEXT: eor x19, x19, #0x3f
-; CHECK-NEXT: str x18, [sp, #112]
-; CHECK-NEXT: adcs x17, x17, xzr
+; CHECK-NEXT: str x17, [sp, #112]
+; CHECK-NEXT: adcs x0, x0, xzr
; CHECK-NEXT: stp q0, q0, [sp, #64]
; CHECK-NEXT: ldp x2, x6, [x4, #8]
; CHECK-NEXT: ldr x7, [x4]
@@ -334,29 +334,29 @@ define i256 @sdiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: mov x19, xzr
; CHECK-NEXT: mov x20, xzr
; CHECK-NEXT: and x14, x21, #0x18
-; CHECK-NEXT: stp x18, x0, [sp, #16]
-; CHECK-NEXT: and x18, x13, #0x3f
+; CHECK-NEXT: stp x17, x18, [sp, #16]
+; CHECK-NEXT: and x17, x13, #0x3f
; CHECK-NEXT: add x14, x15, x14
-; CHECK-NEXT: eor x18, x18, #0x3f
+; CHECK-NEXT: eor x17, x17, #0x3f
; CHECK-NEXT: mvn w21, w13
-; CHECK-NEXT: ldp x15, x0, [x14, #16]
+; CHECK-NEXT: ldp x15, x18, [x14, #16]
; CHECK-NEXT: mov x7, xzr
; CHECK-NEXT: ldp x25, x22, [x14]
; CHECK-NEXT: subs x14, x8, #1
-; CHECK-NEXT: lsl x23, x0, #1
+; CHECK-NEXT: lsl x23, x18, #1
; CHECK-NEXT: lsl x24, x15, #1
; CHECK-NEXT: lsr x26, x15, x13
; CHECK-NEXT: lsl x27, x22, #1
; CHECK-NEXT: mov x15, #-1 // =0xffffffffffffffff
; CHECK-NEXT: lsr x28, x25, x13
-; CHECK-NEXT: lsl x23, x23, x18
+; CHECK-NEXT: lsl x23, x23, x17
; CHECK-NEXT: lsl x21, x24, x21
; CHECK-NEXT: lsr x24, x22, x13
-; CHECK-NEXT: lsl x27, x27, x18
-; CHECK-NEXT: adcs x18, x9, x15
+; CHECK-NEXT: lsl x27, x27, x17
+; CHECK-NEXT: adcs x17, x9, x15
; CHECK-NEXT: orr x22, x23, x26
-; CHECK-NEXT: lsr x23, x0, x13
-; CHECK-NEXT: adcs x0, x10, x15
+; CHECK-NEXT: lsr x23, x18, x13
+; CHECK-NEXT: adcs x18, x10, x15
; CHECK-NEXT: orr x25, x24, x21
; CHECK-NEXT: orr x24, x27, x28
; CHECK-NEXT: adc x21, x11, x15
@@ -369,10 +369,10 @@ define i256 @sdiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: extr x5, x5, x3, #63
; CHECK-NEXT: extr x3, x3, x2, #63
; CHECK-NEXT: cmp x14, x26
-; CHECK-NEXT: sbcs xzr, x18, x27
+; CHECK-NEXT: sbcs xzr, x17, x27
; CHECK-NEXT: orr x3, x20, x3
; CHECK-NEXT: orr x5, x7, x5
-; CHECK-NEXT: sbcs xzr, x0, x28
+; CHECK-NEXT: sbcs xzr, x18, x28
; CHECK-NEXT: mov x7, xzr
; CHECK-NEXT: sbc x22, x21, x23
; CHECK-NEXT: asr x29, x22, #63
@@ -389,10 +389,10 @@ define i256 @sdiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: adcs x16, x16, x15
; CHECK-NEXT: orr x1, x6, x1, lsl #1
; CHECK-NEXT: and x6, x29, #0x1
-; CHECK-NEXT: adcs x17, x17, x15
+; CHECK-NEXT: adcs x0, x0, x15
; CHECK-NEXT: orr x2, x19, x26
; CHECK-NEXT: adc x4, x4, x15
-; CHECK-NEXT: orr x20, x13, x17
+; CHECK-NEXT: orr x20, x13, x0
; CHECK-NEXT: orr x19, x16, x4
; CHECK-NEXT: orr x26, x20, x19
; CHECK-NEXT: mov x19, xzr
diff --git a/llvm/test/CodeGen/AArch64/icmp-ult-eq-fold.ll b/llvm/test/CodeGen/AArch64/icmp-ult-eq-fold.ll
index 8297fa2d4e3f9..78d23b4aed25f 100644
--- a/llvm/test/CodeGen/AArch64/icmp-ult-eq-fold.ll
+++ b/llvm/test/CodeGen/AArch64/icmp-ult-eq-fold.ll
@@ -205,9 +205,8 @@ define i1 @test_disjoint3(i1 %0, i32 %1, i32 %2) {
; CHECK-LABEL: test_disjoint3:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, #1 // =0x1
-; CHECK-NEXT: orr w9, w2, #0x800000
; CHECK-NEXT: lsl w8, w8, w1
-; CHECK-NEXT: tst w9, w8
+; CHECK-NEXT: tst w2, w8
; CHECK-NEXT: cset w8, mi
; CHECK-NEXT: orr w8, w0, w8
; CHECK-NEXT: and w0, w8, #0x1
@@ -227,9 +226,8 @@ define i1 @test_disjoint4(i1 %0, i32 %1, i32 %2) {
; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: orr w9, w2, #0x800000
; CHECK-NEXT: lsl w8, w8, w1
-; CHECK-NEXT: and w8, w9, w8
-; CHECK-NEXT: cmp w8, #1
-; CHECK-NEXT: cset w8, lt
+; CHECK-NEXT: tst w9, w8
+; CHECK-NEXT: cset w8, le
; CHECK-NEXT: orr w8, w0, w8
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
@@ -248,9 +246,8 @@ define i1 @test_disjoint_inverse_4(i1 %0, i32 %1, i32 %2) {
; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: orr w9, w2, #0x800000
; CHECK-NEXT: lsl w8, w8, w1
-; CHECK-NEXT: bic w8, w9, w8
-; CHECK-NEXT: cmp w8, #1
-; CHECK-NEXT: cset w8, lt
+; CHECK-NEXT: bics wzr, w9, w8
+; CHECK-NEXT: cset w8, le
; CHECK-NEXT: orr w8, w0, w8
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
@@ -310,9 +307,8 @@ define i1 @test_disjoint3_inverse(i1 %0, i32 %1, i32 %2) {
; CHECK-LABEL: test_disjoint3_inverse:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, #1 // =0x1
-; CHECK-NEXT: orr w9, w2, #0x800000
; CHECK-NEXT: lsl w8, w8, w1
-; CHECK-NEXT: bics wzr, w9, w8
+; CHECK-NEXT: bics wzr, w2, w8
; CHECK-NEXT: cset w8, mi
; CHECK-NEXT: orr w8, w0, w8
; CHECK-NEXT: and w0, w8, #0x1
@@ -371,9 +367,8 @@ define i1 @test_disjoint3_64(i1 %0, i64 %1, i64 %2) {
; CHECK-LABEL: test_disjoint3_64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, #1 // =0x1
-; CHECK-NEXT: orr x9, x2, #0x80000000000000
; CHECK-NEXT: lsl x8, x8, x1
-; CHECK-NEXT: tst x9, x8
+; CHECK-NEXT: tst x2, x8
; CHECK-NEXT: cset w8, mi
; CHECK-NEXT: orr w8, w0, w8
; CHECK-NEXT: and w0, w8, #0x1
@@ -393,9 +388,8 @@ define i1 @test_disjoint4_64(i1 %0, i64 %1, i64 %2) {
; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: orr x9, x2, #0x80000000000000
; CHECK-NEXT: lsl x8, x8, x1
-; CHECK-NEXT: and x8, x9, x8
-; CHECK-NEXT: cmp x8, #1
-; CHECK-NEXT: cset w8, lt
+; CHECK-NEXT: tst x9, x8
+; CHECK-NEXT: cset w8, le
; CHECK-NEXT: orr w8, w0, w8
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
@@ -414,9 +408,8 @@ define i1 @test_disjoint_inverse_4_64(i1 %0, i64 %1, i64 %2) {
; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: orr x9, x2, #0x80000000000000
; CHECK-NEXT: lsl x8, x8, x1
-; CHECK-NEXT: bic x8, x9, x8
-; CHECK-NEXT: cmp x8, #1
-; CHECK-NEXT: cset w8, lt
+; CHECK-NEXT: bics xzr, x9, x8
+; CHECK-NEXT: cset w8, le
; CHECK-NEXT: orr w8, w0, w8
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
@@ -476,9 +469,8 @@ define i1 @test_disjoint3_inverse_64(i1 %0, i64 %1, i64 %2) {
; CHECK-LABEL: test_disjoint3_inverse_64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, #1 // =0x1
-; CHECK-NEXT: orr x9, x2, #0x80000000000000
; CHECK-NEXT: lsl x8, x8, x1
-; CHECK-NEXT: bics xzr, x9, x8
+; CHECK-NEXT: bics xzr, x2, x8
; CHECK-NEXT: cset w8, mi
; CHECK-NEXT: orr w8, w0, w8
; CHECK-NEXT: and w0, w8, #0x1
diff --git a/llvm/test/CodeGen/AArch64/neon-dotreduce.ll b/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
index 8854d8ab80798..17dd4d5d203bc 100644
--- a/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+++ b/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
@@ -445,9 +445,8 @@ entry:
define i32 @test_udot_v5i8_nomla(ptr nocapture readonly %a1) {
; CHECK-SD-LABEL: test_udot_v5i8_nomla:
; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ldr x8, [x0]
+; CHECK-SD-NEXT: ldr d0, [x0]
; CHECK-SD-NEXT: movi v1.2d, #0000000000000000
-; CHECK-SD-NEXT: fmov d0, x8
; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-SD-NEXT: ushll2 v2.4s, v0.8h, #0
; CHECK-SD-NEXT: mov v1.s[0], v2.s[0]
@@ -2351,20 +2350,20 @@ define i32 @test_udot_v25i8(ptr nocapture readonly %a, ptr nocapture readonly %b
; CHECK-SD-LABEL: test_udot_v25i8:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: ldp q3, q0, [x1]
-; CHECK-SD-NEXT: movi v5.2d, #0000000000000000
; CHECK-SD-NEXT: ldp q2, q1, [x0]
; CHECK-SD-NEXT: umull2 v4.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT: umull v5.8h, v3.8b, v2.8b
; CHECK-SD-NEXT: umull v0.8h, v0.8b, v1.8b
-; CHECK-SD-NEXT: umull v1.8h, v3.8b, v2.8b
+; CHECK-SD-NEXT: movi v1.2d, #0000000000000000
; CHECK-SD-NEXT: umull2 v2.8h, v3.16b, v2.16b
; CHECK-SD-NEXT: ushll v3.4s, v4.4h, #0
-; CHECK-SD-NEXT: uaddl2 v4.4s, v1.8h, v0.8h
-; CHECK-SD-NEXT: uaddl v0.4s, v1.4h, v0.4h
-; CHECK-SD-NEXT: mov v5.s[0], v3.s[0]
-; CHECK-SD-NEXT: uaddw2 v1.4s, v4.4s, v2.8h
+; CHECK-SD-NEXT: uaddl2 v4.4s, v5.8h, v0.8h
+; CHECK-SD-NEXT: uaddl v0.4s, v5.4h, v0.4h
+; CHECK-SD-NEXT: mov v1.s[0], v3.s[0]
+; CHECK-SD-NEXT: uaddw2 v3.4s, v4.4s, v2.8h
+; CHECK-SD-NEXT: add v0.4s, v0.4s, v3.4s
+; CHECK-SD-NEXT: uaddw v1.4s, v1.4s, v2.4h
; CHECK-SD-NEXT: add v0.4s, v0.4s, v1.4s
-; CHECK-SD-NEXT: uaddw v2.4s, v5.4s, v2.4h
-; CHECK-SD-NEXT: add v0.4s, v0.4s, v2.4s
; CHECK-SD-NEXT: addv s0, v0.4s
; CHECK-SD-NEXT: fmov w8, s0
; CHECK-SD-NEXT: add w0, w8, w2
@@ -2781,20 +2780,20 @@ define i32 @test_sdot_v25i8(ptr nocapture readonly %a, ptr nocapture readonly %b
; CHECK-SD-LABEL: test_sdot_v25i8:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: ldp q3, q0, [x1]
-; CHECK-SD-NEXT: movi v5.2d, #0000000000000000
; CHECK-SD-NEXT: ldp q2, q1, [x0]
; CHECK-SD-NEXT: smull2 v4.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT: smull v5.8h, v3.8b, v2.8b
; CHECK-SD-NEXT: smull v0.8h, v0.8b, v1.8b
-; CHECK-SD-NEXT: smull v1.8h, v3.8b, v2.8b
+; CHECK-SD-NEXT: movi v1.2d, #0000000000000000
; CHECK-SD-NEXT: smull2 v2.8h, v3.16b, v2.16b
; CHECK-SD-NEXT: sshll v3.4s, v4.4h, #0
-; CHECK-SD-NEXT: saddl2 v4.4s, v1.8h, v0.8h
-; CHECK-SD-NEXT: saddl v0.4s, v1.4h, v0.4h
-; CHECK-SD-NEXT: mov v5.s[0], v3.s[0]
-; CHECK-SD-NEXT: saddw2 v1.4s, v4.4s, v2.8h
+; CHECK-SD-NEXT: saddl2 v4.4s, v5.8h, v0.8h
+; CHECK-SD-NEXT: saddl v0.4s, v5.4h, v0.4h
+; CHECK-SD-NEXT: mov v1.s[0], v3.s[0]
+; CHECK-SD-NEXT: saddw2 v3.4s, v4.4s, v2.8h
+; CHECK-SD-NEXT: add v0.4s, v0.4s, v3.4s
+; CHECK-SD-NEXT: saddw v1.4s, v1.4s, v2.4h
; CHECK-SD-NEXT: add v0.4s, v0.4s, v1.4s
-; CHECK-SD-NEXT: saddw v2.4s, v5.4s, v2.4h
-; CHECK-SD-NEXT: add v0.4s, v0.4s, v2.4s
; CHECK-SD-NEXT: addv s0, v0.4s
; CHECK-SD-NEXT: fmov w8, s0
; CHECK-SD-NEXT: add w0, w8, w2
@@ -3115,202 +3114,210 @@ define i32 @test_sdot_v25i8_double(<25 x i8> %a, <25 x i8> %b, <25 x i8> %c, <25
; CHECK-SD-NEXT: .cfi_offset w29, -16
; CHECK-SD-NEXT: ldr b0, [sp, #216]
; CHECK-SD-NEXT: add x8, sp, #224
+; CHECK-SD-NEXT: add x9, sp, #232
; CHECK-SD-NEXT: ldr b1, [sp, #16]
-; CHECK-SD-NEXT: ldr b2, [sp, #280]
-; CHECK-SD-NEXT: add x9, sp, #240
-; CHECK-SD-NEXT: ldr b4, [sp, #80]
+; CHECK-SD-NEXT: ldrb w10, [sp, #288]
+; CHECK-SD-NEXT: ldrb w11, [sp, #80]
; CHECK-SD-NEXT: ld1 { v0.b }[1], [x8]
; CHECK-SD-NEXT: add x8, sp, #24
-; CHECK-SD-NEXT: add x10, sp, #48
+; CHECK-SD-NEXT: ldr b2, [sp, #152]
; CHECK-SD-NEXT: ld1 { v1.b }[1], [x8]
-; CHECK-SD-NEXT: add x8, sp, #232
-; CHECK-SD-NEXT: add x11, sp, #96
-; CHECK-SD-NEXT: ldr b5, [sp, #152]
-; CHECK-SD-NEXT: add x12, sp, #168
+; CHECK-SD-NEXT: add x8, sp, #160
+; CHECK-SD-NEXT: fmov s5, w11
+; CHECK-SD-NEXT: ld1 { v2.b }[1], [x8]
+; CHECK-SD-NEXT: ldrb w8, [sp, #88]
; CHECK-SD-NEXT: ldr b6, [sp, #616]
-; CHECK-SD-NEXT: ld1 { v0.b }[2], [x8]
-; CHECK-SD-NEXT: add x8, sp, #32
+; CHECK-SD-NEXT: ld1 { v0.b }[2], [x9]
+; CHECK-SD-NEXT: ldrb w9, [sp, #280]
; CHECK-SD-NEXT: fmov s3, w0
-; CHECK-SD-NEXT: ld1 { v1.b }[2], [x8]
-; CHECK-SD-NEXT: add x8, sp, #288
-; CHECK-SD-NEXT: ldr b7, [sp, #416]
-; CHECK-SD-NEXT: ld1 { v2.b }[1], [x8]
-; CHECK-SD-NEXT: add x8, sp, #40
-; CHECK-SD-NEXT: ldr b22, [sp, #744]
+; CHECK-SD-NEXT: mov v5.b[1], w8
+; CHECK-SD-NEXT: add x8, sp, #168
+; CHECK-SD-NEXT: ldrb w11, [sp, #136]
+; CHECK-SD-NEXT: fmov s4, w9
+; CHECK-SD-NEXT: add x9, sp, #240
+; CHECK-SD-NEXT: ld1 { v2.b }[2], [x8]
; CHECK-SD-NEXT: ld1 { v0.b }[3], [x9]
-; CHECK-SD-NEXT: add x9, sp, #248
+; CHECK-SD-NEXT: ldrb w9, [sp, #296]
+; CHECK-SD-NEXT: ldrb w8, [sp, #96]
+; CHECK-SD-NEXT: ldr b17, [sp, #552]
; CHECK-SD-NEXT: mov v3.b[1], w1
-; CHECK-SD-NEXT: ld1 { v1.b }[3], [x8]
-; CHECK-SD-NEXT: add x8, sp, #88
-; CHECK-SD-NEXT: ldr b23, [sp, #544]
-; CHECK-SD-NEXT: ld1 { v4.b }[1], [x8]
-; CHECK-SD-NEXT: add x8, sp, #256
-; CHECK-SD-NEXT: ldr b19, [sp, #680]
-; CHECK-SD-NEXT: ld1 { v0.b }[4], [x9]
-; CHECK-SD-NEXT: add x9, sp, #296
-; CHECK-SD-NEXT: ldr b20, [sp, #480]
-; CHECK-SD-NEXT: ld1 { v1.b }[4], [x10]
-; CHECK-SD-NEXT: ld1 { v2.b }[2], [x9]
-; CHECK-SD-NEXT: add x10, sp, #160
-; CHECK-SD-NEXT: ld1 { v4.b }[2], [x11]
-; CHECK-SD-NEXT: add x11, sp, #304
-; CHECK-SD-NEXT: ld1 { v5.b }[1], [x10]
-; CHECK-SD-NEXT: ld1 { v0.b }[5], [x8]
-; CHECK-SD-NEXT: add x8, sp, #56
-; CHECK-SD-NEXT: add x10, sp, #264
-; CHECK-SD-NEXT: ld1 { v1.b }[5], [x8]
-; CHECK-SD-NEXT: add x8, sp, #64
-; CHECK-SD-NEXT: ld1 { v2.b }[3], [x11]
-; CHECK-SD-NEXT: add x9, sp, #272
-; CHECK-SD-NEXT: ld1 { v5.b }[2], [x12]
-; CHECK-SD-NEXT: add x11, sp, #72
-; CHECK-SD-NEXT: ld1 { v0.b }[6], [x10]
-; CHECK-SD-NEXT: add x10, sp, #312
+; CHECK-SD-NEXT: ldr b19, [sp, #416]
+; CHECK-SD-NEXT: mov v4.b[1], w10
+; CHECK-SD-NEXT: add x10, sp, #32
+; CHECK-SD-NEXT: mov v5.b[2], w8
+; CHECK-SD-NEXT: ld1 { v1.b }[2], [x10]
+; CHECK-SD-NEXT: add x8, sp, #176
+; CHECK-SD-NEXT: add x10, sp, #248
+; CHECK-SD-NEXT: ld1 { v2.b }[3], [x8]
+; CHECK-SD-NEXT: ldrb w8, [sp, #104]
+; CHECK-SD-NEXT: ld1 { v0.b }[4], [x10]
+; CHECK-SD-NEXT: add x10, sp, #256
+; CHECK-SD-NEXT: ldr b21, [sp, #352]
; CHECK-SD-NEXT: mov v3.b[2], w2
-; CHECK-SD-NEXT: ld1 { v1.b }[6], [x8]
-; CHECK-SD-NEXT: add x8, sp, #104
-; CHECK-SD-NEXT: ld1 { v2.b }[4], [x10]
-; CHECK-SD-NEXT: ld1 { v4.b }[3], [x8]
-; CHECK-SD-NEXT: add x8, sp, #112
-; CHECK-SD-NEXT: add x10, sp, #128
-; CHECK-SD-NEXT: ld1 { v0.b }[7], [x9]
-; CHECK-SD-NEXT: add x9, sp, #320
-; CHECK-SD-NEXT: ldr b21, [sp, #552]
-; CHECK-SD-NEXT: ld1 { v2.b }[5], [x9]
-; CHECK-SD-NEXT: add x9, sp, #176
-; CHECK-SD-NEXT: ld1 { v1.b }[7], [x11]
-; CHECK-SD-NEXT: ld1 { v4.b }[4], [x8]
-; CHECK-SD-NEXT: add x8, sp, #624
-; CHECK-SD-NEXT: ld1 { v5.b }[3], [x9]
-; CHECK-SD-NEXT: ld1 { v6.b }[1], [x8]
-; CHECK-SD-NEXT: add x8, sp, #120
-; CHECK-SD-NEXT: add x9, sp, #328
-; CHECK-SD-NEXT: ld1 { v2.b }[6], [x9]
-; CHECK-SD-NEXT: add x9, sp, #184
-; CHECK-SD-NEXT: add x11, sp, #192
-; CHECK-SD-NEXT: ld1 { v4.b }[5], [x8]
-; CHECK-SD-NEXT: add x8, sp, #632
-; CHECK-SD-NEXT: ld1 { v5.b }[4], [x9]
-; CHECK-SD-NEXT: ld1 { v6.b }[2], [x8]
-; CHECK-SD-NEXT: add x9, sp, #640
-; CHECK-SD-NEXT: add x8, sp, #336
-; CHECK-SD-NEXT: ld1 { v2.b }[7], [x8]
-; CHECK-SD-NEXT: add x8, sp, #656
-; CHECK-SD-NEXT: smull v23.8h, v23.8b, v22.8b
-; CHECK-SD-NEXT: ld1 { v5.b }[5], [x11]
-; CHECK-SD-NEXT: add x11, sp, #648
-; CHECK-SD-NEXT: ld1 { v4.b }[6], [x10]
-; CHECK-SD-NEXT: ld1 { v6.b }[3], [x9]
-; CHECK-SD-NEXT: add x9, sp, #200
-; CHECK-SD-NEXT: add x10, sp, #136
-; CHECK-SD-NEXT: ldr b22, [sp, #352]
-; CHECK-SD-NEXT: add x12, sp, #360
+; CHECK-SD-NEXT: mov v4.b[2], w9
+; CHECK-SD-NEXT: add x9, sp, #40
+; CHECK-SD-NEXT: mov v5.b[3], w8
+; CHECK-SD-NEXT: ld1 { v1.b }[3], [x9]
+; CHECK-SD-NEXT: ldrb w9, [sp, #304]
+; CHECK-SD-NEXT: add x8, sp, #184
+; CHECK-SD-NEXT: ld1 { v2.b }[4], [x8]
+; CHECK-SD-NEXT: ldrb w8, [sp, #112]
+; CHECK-SD-NEXT: ld1 { v0.b }[5], [x10]
+; CHECK-SD-NEXT: add x10, sp, #264
; CHECK-SD-NEXT: mov v3.b[3], w3
-; CHECK-SD-NEXT: ld1 { v5.b }[6], [x9]
-; CHECK-SD-NEXT: add x9, sp, #208
-; CHECK-SD-NEXT: ld1 { v4.b }[7], [x10]
-; CHECK-SD-NEXT: ld1 { v6.b }[4], [x11]
-; CHECK-SD-NEXT: add x11, sp, #424
-; CHECK-SD-NEXT: add x10, sp, #488
-; CHECK-SD-NEXT: ld1 { v7.b }[1], [x11]
-; CHECK-SD-NEXT: add x11, sp, #560
-; CHECK-SD-NEXT: ld1 { v20.b }[1], [x10]
-; CHECK-SD-NEXT: ld1 { v5.b }[7], [x9]
-; CHECK-SD-NEXT: add x9, sp, #440
-; CHECK-SD-NEXT: ld1 { v21.b }[1], [x11]
-; CHECK-SD-NEXT: ld1 { v6.b }[5], [x8]
-; CHECK-SD-NEXT: add x8, sp, #432
-; CHECK-SD-NEXT: ld1 { v22.b }[1], [x12]
-; CHECK-SD-NEXT: ld1 { v7.b }[2], [x8]
-; CHECK-SD-NEXT: add x11, sp, #496
-; CHECK-SD-NEXT: add x12, sp, #568
-; CHECK-SD-NEXT: add x13, sp, #368
-; CHECK-SD-NEXT: ld1 { v20.b }[2], [x11]
-; CHECK-SD-NEXT: ld1 { v21.b }[2], [x12]
-; CHECK-SD-NEXT: ld1 { v22.b }[2], [x13]
-; CHECK-SD-NEXT: add x10, sp, #448
+; CHECK-SD-NEXT: ldrb w12, [sp, #144]
+; CHECK-SD-NEXT: mov v4.b[3], w9
+; CHECK-SD-NEXT: add x9, sp, #48
+; CHECK-SD-NEXT: mov v5.b[4], w8
+; CHECK-SD-NEXT: ld1 { v1.b }[4], [x9]
+; CHECK-SD-NEXT: ldrb w9, [sp, #312]
+; CHECK-SD-NEXT: add x8, sp, #192
+; CHECK-SD-NEXT: ld1 { v0.b }[6], [x10]
+; CHECK-SD-NEXT: ld1 { v2.b }[5], [x8]
+; CHECK-SD-NEXT: ldrb w8, [sp, #120]
+; CHECK-SD-NEXT: add x10, sp, #272
; CHECK-SD-NEXT: mov v3.b[4], w4
-; CHECK-SD-NEXT: ld1 { v7.b }[3], [x9]
-; CHECK-SD-NEXT: add x9, sp, #688
-; CHECK-SD-NEXT: add x11, sp, #576
-; CHECK-SD-NEXT: ld1 { v19.b }[1], [x9]
-; CHECK-SD-NEXT: add x9, sp, #696
-; CHECK-SD-NEXT: add x12, sp, #376
-; CHECK-SD-NEXT: ld1 { v21.b }[3], [x11]
-; CHECK-SD-NEXT: ld1 { v22.b }[3], [x12]
-; CHECK-SD-NEXT: add x11, sp, #512
-; CHECK-SD-NEXT: ld1 { v7.b }[4], [x10]
-; CHECK-SD-NEXT: add x10, sp, #504
-; CHECK-SD-NEXT: add x12, sp, #584
-; CHECK-SD-NEXT: ld1 { v19.b }[2], [x9]
-; CHECK-SD-NEXT: add x9, sp, #704
-; CHECK-SD-NEXT: ld1 { v20.b }[3], [x10]
-; CHECK-SD-NEXT: add x13, sp, #384
+; CHECK-SD-NEXT: fmov s16, w12
+; CHECK-SD-NEXT: mov v4.b[4], w9
+; CHECK-SD-NEXT: add x9, sp, #56
+; CHECK-SD-NEXT: mov v5.b[5], w8
+; CHECK-SD-NEXT: ld1 { v1.b }[5], [x9]
+; CHECK-SD-NEXT: ldrb w9, [sp, #320]
+; CHECK-SD-NEXT: ld1 { v0.b }[7], [x10]
+; CHECK-SD-NEXT: add x8, sp, #200
+; CHECK-SD-NEXT: add x10, sp, #72
+; CHECK-SD-NEXT: movi v23.2d, #0000000000000000
+; CHECK-SD-NEXT: ld1 { v2.b }[6], [x8]
+; CHECK-SD-NEXT: ldrb w8, [sp, #128]
; CHECK-SD-NEXT: mov v3.b[5], w5
-; CHECK-SD-NEXT: ld1 { v21.b }[4], [x12]
-; CHECK-SD-NEXT: ld1 { v22.b }[4], [x13]
-; CHECK-SD-NEXT: add x10, sp, #456
-; CHECK-SD-NEXT: ldr b16, [sp, #344]
-; CHECK-SD-NEXT: ld1 { v19.b }[3], [x9]
-; CHECK-SD-NEXT: add x9, sp, #712
-; CHECK-SD-NEXT: ld1 { v20.b }[4], [x11]
-; CHECK-SD-NEXT: ldr b17, [sp, #144]
-; CHECK-SD-NEXT: ld1 { v7.b }[5], [x10]
-; CHECK-SD-NEXT: add x10, sp, #520
-; CHECK-SD-NEXT: add x11, sp, #592
-; CHECK-SD-NEXT: add x12, sp, #392
+; CHECK-SD-NEXT: mov v4.b[5], w9
+; CHECK-SD-NEXT: add x9, sp, #64
+; CHECK-SD-NEXT: ld1 { v1.b }[6], [x9]
+; CHECK-SD-NEXT: ldrb w9, [sp, #328]
+; CHECK-SD-NEXT: mov v5.b[6], w8
+; CHECK-SD-NEXT: add x8, sp, #208
+; CHECK-SD-NEXT: ld1 { v2.b }[7], [x8]
+; CHECK-SD-NEXT: ldrb w8, [sp, #488]
; CHECK-SD-NEXT: mov v3.b[6], w6
-; CHECK-SD-NEXT: ld1 { v19.b }[4], [x9]
-; CHECK-SD-NEXT: add x9, sp, #720
-; CHECK-SD-NEXT: ld1 { v20.b }[5], [x10]
-; CHECK-SD-NEXT: ld1 { v21.b }[5], [x11]
-; CHECK-SD-NEXT: ld1 { v22.b }[5], [x12]
-; CHECK-SD-NEXT: smull v16.8h, v17.8b, v16.8b
-; CHECK-SD-NEXT: add x8, sp, #664
-; CHECK-SD-NEXT: add x10, sp, #464
-; CHECK-SD-NEXT: add x11, sp, #528
-; CHECK-SD-NEXT: ld1 { v19.b }[5], [x9]
-; CHECK-SD-NEXT: add x9, sp, #728
-; CHECK-SD-NEXT: add x12, sp, #600
-; CHECK-SD-NEXT: add x13, sp, #400
-; CHECK-SD-NEXT: ld1 { v6.b }[6], [x8]
-; CHECK-SD-NEXT: ld1 { v20.b }[6], [x11]
-; CHECK-SD-NEXT: ld1 { v21.b }[6], [x12]
-; CHECK-SD-NEXT: ld1 { v22.b }[6], [x13]
-; CHECK-SD-NEXT: ld1 { v7.b }[6], [x10]
-; CHECK-SD-NEXT: ld1 { v19.b }[6], [x9]
-; CHECK-SD-NEXT: add x9, sp, #736
+; CHECK-SD-NEXT: mov v4.b[6], w9
+; CHECK-SD-NEXT: ld1 { v1.b }[7], [x10]
+; CHECK-SD-NEXT: add x10, sp, #624
+; CHECK-SD-NEXT: ldrb w9, [sp, #336]
+; CHECK-SD-NEXT: ld1 { v6.b }[1], [x10]
+; CHECK-SD-NEXT: ldrb w10, [sp, #344]
+; CHECK-SD-NEXT: mov v5.b[7], w11
+; CHECK-SD-NEXT: add x11, sp, #640
+; CHECK-SD-NEXT: fmov s7, w10
+; CHECK-SD-NEXT: ldrb w10, [sp, #480]
; CHECK-SD-NEXT: mov v3.b[7], w7
-; CHECK-SD-NEXT: sshll v18.4s, v16.4h, #0
-; CHECK-SD-NEXT: movi v16.2d, #0000000000000000
-; CHECK-SD-NEXT: movi v17.2d, #0000000000000000
+; CHECK-SD-NEXT: mov v4.b[7], w9
+; CHECK-SD-NEXT: add x9, sp, #632
+; CHECK-SD-NEXT: smull v0.8h, v1.8b, v0.8b
+; CHECK-SD-NEXT: ld1 { v6.b }[2], [x9]
+; CHECK-SD-NEXT: ldrb w9, [sp, #680]
+; CHECK-SD-NEXT: fmov s20, w10
+; CHECK-SD-NEXT: ldrb w10, [sp, #696]
+; CHECK-SD-NEXT: smull v7.8h, v16.8b, v7.8b
+; CHECK-SD-NEXT: fmov s18, w9
+; CHECK-SD-NEXT: ldrb w9, [sp, #496]
+; CHECK-SD-NEXT: smull v1.8h, v3.8b, v2.8b
+; CHECK-SD-NEXT: ld1 { v6.b }[3], [x11]
+; CHECK-SD-NEXT: add x11, sp, #560
+; CHECK-SD-NEXT: mov v20.b[1], w8
+; CHECK-SD-NEXT: ld1 { v17.b }[1], [x11]
+; CHECK-SD-NEXT: ldrb w11, [sp, #688]
+; CHECK-SD-NEXT: add x8, sp, #424
+; CHECK-SD-NEXT: ld1 { v19.b }[1], [x8]
+; CHECK-SD-NEXT: add x8, sp, #360
+; CHECK-SD-NEXT: sshll v7.4s, v7.4h, #0
+; CHECK-SD-NEXT: mov v18.b[1], w11
+; CHECK-SD-NEXT: add x11, sp, #568
+; CHECK-SD-NEXT: ld1 { v21.b }[1], [x8]
+; CHECK-SD-NEXT: ldrb w8, [sp, #704]
+; CHECK-SD-NEXT: mov v20.b[2], w9
+; CHECK-SD-NEXT: ld1 { v17.b }[2], [x11]
+; CHECK-SD-NEXT: ldrb w11, [sp, #504]
+; CHECK-SD-NEXT: add x9, sp, #432
+; CHECK-SD-NEXT: smull v2.8h, v5.8b, v4.8b
+; CHECK-SD-NEXT: ld1 { v19.b }[2], [x9]
+; CHECK-SD-NEXT: add x9, sp, #368
+; CHECK-SD-NEXT: mov v23.s[0], v7.s[0]
+; CHECK-SD-NEXT: mov v18.b[2], w10
+; CHECK-SD-NEXT: add x10, sp, #648
+; CHECK-SD-NEXT: ld1 { v21.b }[2], [x9]
+; CHECK-SD-NEXT: ld1 { v6.b }[4], [x10]
+; CHECK-SD-NEXT: add x10, sp, #576
+; CHECK-SD-NEXT: ldrb w9, [sp, #712]
+; CHECK-SD-NEXT: ld1 { v17.b }[3], [x10]
+; CHECK-SD-NEXT: mov v20.b[3], w11
+; CHECK-SD-NEXT: ldrb w10, [sp, #512]
+; CHECK-SD-NEXT: add x11, sp, #584
+; CHECK-SD-NEXT: mov v18.b[3], w8
+; CHECK-SD-NEXT: add x8, sp, #656
+; CHECK-SD-NEXT: ld1 { v6.b }[5], [x8]
+; CHECK-SD-NEXT: add x8, sp, #440
+; CHECK-SD-NEXT: ld1 { v17.b }[4], [x11]
+; CHECK-SD-NEXT: ld1 { v19.b }[3], [x8]
+; CHECK-SD-NEXT: add x8, sp, #376
+; CHECK-SD-NEXT: mov v20.b[4], w10
+; CHECK-SD-NEXT: ld1 { v21.b }[3], [x8]
+; CHECK-SD-NEXT: ldrb w8, [sp, #720]
+; CHECK-SD-NEXT: add x10, sp, #592
+; CHECK-SD-NEXT: mov v18.b[4], w9
+; CHECK-SD-NEXT: add x9, sp, #664
+; CHECK-SD-NEXT: ldrb w11, [sp, #520]
+; CHECK-SD-NEXT: ld1 { v6.b }[6], [x9]
+; CHECK-SD-NEXT: add x9, sp, #448
+; CHECK-SD-NEXT: ld1 { v17.b }[5], [x10]
+; CHECK-SD-NEXT: ld1 { v19.b }[4], [x9]
+; CHECK-SD-NEXT: add x9, sp, #384
+; CHECK-SD-NEXT: mov v20.b[5], w11
+; CHECK-SD-NEXT: ld1 { v21.b }[4], [x9]
+; CHECK-SD-NEXT: add x11, sp, #600
+; CHECK-SD-NEXT: ldrb w10, [sp, #528]
+; CHECK-SD-NEXT: mov v18.b[5], w8
; CHECK-SD-NEXT: add x8, sp, #672
-; CHECK-SD-NEXT: add x10, sp, #472
-; CHECK-SD-NEXT: add x11, sp, #608
-; CHECK-SD-NEXT: ld1 { v19.b }[7], [x9]
-; CHECK-SD-NEXT: add x9, sp, #536
-; CHECK-SD-NEXT: add x12, sp, #408
-; CHECK-SD-NEXT: ld1 { v20.b }[7], [x9]
-; CHECK-SD-NEXT: ld1 { v21.b }[7], [x11]
-; CHECK-SD-NEXT: ld1 { v22.b }[7], [x12]
+; CHECK-SD-NEXT: ld1 { v17.b }[6], [x11]
; CHECK-SD-NEXT: ld1 { v6.b }[7], [x8]
-; CHECK-SD-NEXT: ld1 { v7.b }[7], [x10]
-; CHECK-SD-NEXT: sshll v23.4s, v23.4h, #0
-; CHECK-SD-NEXT: smull v0.8h, v1.8b, v0.8b
-; CHECK-SD-NEXT: smull v1.8h, v4.8b, v2.8b
-; CHECK-SD-NEXT: smull v2.8h, v3.8b, v5.8b
-; CHECK-SD-NEXT: smull v3.8h, v20.8b, v19.8b
-; CHECK-SD-NEXT: smull v4.8h, v22.8b, v21.8b
-; CHECK-SD-NEXT: mov v17.s[0], v18.s[0]
-; CHECK-SD-NEXT: smull v5.8h, v7.8b, v6.8b
-; CHECK-SD-NEXT: mov v16.s[0], v23.s[0]
-; CHECK-SD-NEXT: saddl2 v6.4s, v2.8h, v1.8h
-; CHECK-SD-NEXT: saddl v1.4s, v2.4h, v1.4h
-; CHECK-SD-NEXT: saddl2 v2.4s, v4.8h, v3.8h
-; CHECK-SD-NEXT: saddl v3.4s, v4.4h, v3.4h
-; CHECK-SD-NEXT: saddw v4.4s, v17.4s, v0.4h
-; CHECK-SD-NEXT: saddw v7.4s, v16.4s, v5.4h
+; CHECK-SD-NEXT: add x8, sp, #456
+; CHECK-SD-NEXT: ldrb w11, [sp, #544]
+; CHECK-SD-NEXT: ld1 { v19.b }[5], [x8]
+; CHECK-SD-NEXT: add x8, sp, #392
+; CHECK-SD-NEXT: ldrb w9, [sp, #728]
+; CHECK-SD-NEXT: ld1 { v21.b }[5], [x8]
+; CHECK-SD-NEXT: ldrb w8, [sp, #744]
+; CHECK-SD-NEXT: fmov s22, w11
+; CHECK-SD-NEXT: mov v18.b[6], w9
+; CHECK-SD-NEXT: mov v20.b[6], w10
+; CHECK-SD-NEXT: add x11, sp, #400
+; CHECK-SD-NEXT: fmov s16, w8
+; CHECK-SD-NEXT: add x8, sp, #464
+; CHECK-SD-NEXT: ldrb w9, [sp, #536]
+; CHECK-SD-NEXT: ld1 { v21.b }[6], [x11]
+; CHECK-SD-NEXT: ldrb w10, [sp, #736]
+; CHECK-SD-NEXT: ld1 { v19.b }[6], [x8]
+; CHECK-SD-NEXT: add x8, sp, #408
+; CHECK-SD-NEXT: add x11, sp, #608
+; CHECK-SD-NEXT: smull v16.8h, v22.8b, v16.8b
+; CHECK-SD-NEXT: mov v18.b[7], w10
+; CHECK-SD-NEXT: movi v22.2d, #0000000000000000
+; CHECK-SD-NEXT: mov v20.b[7], w9
+; CHECK-SD-NEXT: ld1 { v21.b }[7], [x8]
+; CHECK-SD-NEXT: add x8, sp, #472
+; CHECK-SD-NEXT: ld1 { v17.b }[7], [x11]
+; CHECK-SD-NEXT: ld1 { v19.b }[7], [x8]
+; CHECK-SD-NEXT: sshll v16.4s, v16.4h, #0
+; CHECK-SD-NEXT: smull v3.8h, v21.8b, v17.8b
+; CHECK-SD-NEXT: smull v4.8h, v20.8b, v18.8b
+; CHECK-SD-NEXT: smull v5.8h, v19.8b, v6.8b
+; CHECK-SD-NEXT: saddl2 v6.4s, v1.8h, v2.8h
+; CHECK-SD-NEXT: saddl v1.4s, v1.4h, v2.4h
+; CHECK-SD-NEXT: mov v22.s[0], v16.s[0]
+; CHECK-SD-NEXT: saddl2 v2.4s, v3.8h, v4.8h
+; CHECK-SD-NEXT: saddl v3.4s, v3.4h, v4.4h
+; CHECK-SD-NEXT: saddw v4.4s, v23.4s, v0.4h
; CHECK-SD-NEXT: saddw2 v0.4s, v6.4s, v0.8h
+; CHECK-SD-NEXT: saddw v7.4s, v22.4s, v5.4h
; CHECK-SD-NEXT: add v1.4s, v1.4s, v4.4s
; CHECK-SD-NEXT: saddw2 v2.4s, v2.4s, v5.8h
; CHECK-SD-NEXT: add v3.4s, v3.4s, v7.4s
@@ -5557,267 +5564,271 @@ define i32 @test_sdot_v33i8_double(<33 x i8> %a, <33 x i8> %b, <33 x i8> %c, <33
; CHECK-SD-NEXT: ldr b0, [sp, #344]
; CHECK-SD-NEXT: add x8, sp, #352
; CHECK-SD-NEXT: ldr b1, [sp, #80]
-; CHECK-SD-NEXT: ldr b2, [sp, #216]
-; CHECK-SD-NEXT: add x9, sp, #96
-; CHECK-SD-NEXT: add x10, sp, #104
+; CHECK-SD-NEXT: add x9, sp, #88
+; CHECK-SD-NEXT: add x12, sp, #368
+; CHECK-SD-NEXT: add x13, sp, #376
; CHECK-SD-NEXT: ld1 { v0.b }[1], [x8]
-; CHECK-SD-NEXT: add x8, sp, #88
-; CHECK-SD-NEXT: ldr b4, [sp, #408]
-; CHECK-SD-NEXT: ld1 { v1.b }[1], [x8]
; CHECK-SD-NEXT: add x8, sp, #360
-; CHECK-SD-NEXT: add x12, sp, #248
-; CHECK-SD-NEXT: add x13, sp, #432
-; CHECK-SD-NEXT: add x11, sp, #384
-; CHECK-SD-NEXT: ldr b5, [sp, #144]
+; CHECK-SD-NEXT: ld1 { v1.b }[1], [x9]
+; CHECK-SD-NEXT: add x9, sp, #96
+; CHECK-SD-NEXT: add x14, sp, #104
+; CHECK-SD-NEXT: ldr b3, [sp, #216]
+; CHECK-SD-NEXT: add x16, sp, #112
+; CHECK-SD-NEXT: ldr b4, [sp, #408]
+; CHECK-SD-NEXT: add x15, sp, #392
; CHECK-SD-NEXT: ld1 { v0.b }[2], [x8]
-; CHECK-SD-NEXT: add x8, sp, #224
-; CHECK-SD-NEXT: ldr b6, [sp, #280]
-; CHECK-SD-NEXT: ld1 { v2.b }[1], [x8]
; CHECK-SD-NEXT: ld1 { v1.b }[2], [x9]
-; CHECK-SD-NEXT: add x8, sp, #368
-; CHECK-SD-NEXT: add x9, sp, #232
+; CHECK-SD-NEXT: ldr b5, [sp, #144]
+; CHECK-SD-NEXT: ldr b6, [sp, #280]
; CHECK-SD-NEXT: ldr b16, [sp, #744]
; CHECK-SD-NEXT: ldr b17, [sp, #480]
-; CHECK-SD-NEXT: ld1 { v0.b }[3], [x8]
-; CHECK-SD-NEXT: add x8, sp, #376
; CHECK-SD-NEXT: ldr b18, [sp, #936]
-; CHECK-SD-NEXT: ld1 { v2.b }[2], [x9]
-; CHECK-SD-NEXT: ld1 { v1.b }[3], [x10]
-; CHECK-SD-NEXT: add x9, sp, #240
-; CHECK-SD-NEXT: add x10, sp, #392
; CHECK-SD-NEXT: ldr b19, [sp, #672]
; CHECK-SD-NEXT: ldr b7, [sp, #16]
-; CHECK-SD-NEXT: ld1 { v0.b }[4], [x8]
-; CHECK-SD-NEXT: add x8, sp, #112
-; CHECK-SD-NEXT: ldr b21, [sp, #1000]
-; CHECK-SD-NEXT: ld1 { v2.b }[3], [x9]
-; CHECK-SD-NEXT: ld1 { v1.b }[4], [x8]
-; CHECK-SD-NEXT: add x8, sp, #416
-; CHECK-SD-NEXT: ld1 { v4.b }[1], [x8]
-; CHECK-SD-NEXT: add x8, sp, #120
-; CHECK-SD-NEXT: add x9, sp, #400
-; CHECK-SD-NEXT: ld1 { v0.b }[5], [x11]
-; CHECK-SD-NEXT: add x11, sp, #128
-; CHECK-SD-NEXT: ldr b22, [sp, #736]
-; CHECK-SD-NEXT: ld1 { v2.b }[4], [x12]
-; CHECK-SD-NEXT: add x12, sp, #424
-; CHECK-SD-NEXT: ld1 { v1.b }[5], [x8]
-; CHECK-SD-NEXT: ld1 { v4.b }[2], [x12]
-; CHECK-SD-NEXT: add x12, sp, #152
-; CHECK-SD-NEXT: add x8, sp, #136
-; CHECK-SD-NEXT: ld1 { v5.b }[1], [x12]
-; CHECK-SD-NEXT: add x12, sp, #440
-; CHECK-SD-NEXT: ld1 { v0.b }[6], [x10]
-; CHECK-SD-NEXT: ld1 { v1.b }[6], [x11]
-; CHECK-SD-NEXT: add x11, sp, #288
-; CHECK-SD-NEXT: add x10, sp, #256
+; CHECK-SD-NEXT: ld1 { v0.b }[3], [x12]
+; CHECK-SD-NEXT: ld1 { v1.b }[3], [x14]
+; CHECK-SD-NEXT: add x12, sp, #384
+; CHECK-SD-NEXT: add x14, sp, #224
+; CHECK-SD-NEXT: ldrb w10, [sp, #736]
+; CHECK-SD-NEXT: ldrb w11, [sp, #1000]
+; CHECK-SD-NEXT: ld1 { v3.b }[1], [x14]
+; CHECK-SD-NEXT: add x14, sp, #128
+; CHECK-SD-NEXT: fmov s2, w0
+; CHECK-SD-NEXT: ld1 { v0.b }[4], [x13]
+; CHECK-SD-NEXT: ld1 { v1.b }[4], [x16]
+; CHECK-SD-NEXT: add x13, sp, #416
+; CHECK-SD-NEXT: add x16, sp, #120
+; CHECK-SD-NEXT: ld1 { v4.b }[1], [x13]
+; CHECK-SD-NEXT: add x13, sp, #400
+; CHECK-SD-NEXT: fmov s20, w11
+; CHECK-SD-NEXT: fmov s21, w10
+; CHECK-SD-NEXT: ldrb w8, [sp, #208]
+; CHECK-SD-NEXT: ld1 { v0.b }[5], [x12]
+; CHECK-SD-NEXT: add x12, sp, #232
+; CHECK-SD-NEXT: ld1 { v1.b }[5], [x16]
+; CHECK-SD-NEXT: ld1 { v3.b }[2], [x12]
+; CHECK-SD-NEXT: add x16, sp, #240
+; CHECK-SD-NEXT: add x12, sp, #136
+; CHECK-SD-NEXT: ldrb w9, [sp, #472]
+; CHECK-SD-NEXT: add x11, sp, #536
+; CHECK-SD-NEXT: smull v21.8h, v21.8b, v20.8b
+; CHECK-SD-NEXT: ld1 { v0.b }[6], [x15]
+; CHECK-SD-NEXT: add x15, sp, #152
+; CHECK-SD-NEXT: ld1 { v1.b }[6], [x14]
+; CHECK-SD-NEXT: ld1 { v5.b }[1], [x15]
+; CHECK-SD-NEXT: add x15, sp, #424
+; CHECK-SD-NEXT: ld1 { v3.b }[3], [x16]
+; CHECK-SD-NEXT: ld1 { v4.b }[2], [x15]
+; CHECK-SD-NEXT: add x15, sp, #288
+; CHECK-SD-NEXT: add x14, sp, #160
+; CHECK-SD-NEXT: ld1 { v6.b }[1], [x15]
+; CHECK-SD-NEXT: ld1 { v0.b }[7], [x13]
+; CHECK-SD-NEXT: add x13, sp, #432
+; CHECK-SD-NEXT: ld1 { v5.b }[2], [x14]
+; CHECK-SD-NEXT: add x15, sp, #248
+; CHECK-SD-NEXT: add x14, sp, #440
; CHECK-SD-NEXT: ld1 { v4.b }[3], [x13]
-; CHECK-SD-NEXT: ld1 { v6.b }[1], [x11]
-; CHECK-SD-NEXT: add x11, sp, #296
-; CHECK-SD-NEXT: ld1 { v0.b }[7], [x9]
-; CHECK-SD-NEXT: add x9, sp, #160
-; CHECK-SD-NEXT: ld1 { v2.b }[5], [x10]
-; CHECK-SD-NEXT: ld1 { v5.b }[2], [x9]
-; CHECK-SD-NEXT: add x10, sp, #168
-; CHECK-SD-NEXT: ld1 { v1.b }[7], [x8]
-; CHECK-SD-NEXT: ld1 { v4.b }[4], [x12]
-; CHECK-SD-NEXT: add x12, sp, #448
-; CHECK-SD-NEXT: ld1 { v6.b }[2], [x11]
-; CHECK-SD-NEXT: add x11, sp, #304
-; CHECK-SD-NEXT: add x8, sp, #464
-; CHECK-SD-NEXT: add x13, sp, #768
-; CHECK-SD-NEXT: ld1 { v5.b }[3], [x10]
-; CHECK-SD-NEXT: add x10, sp, #176
-; CHECK-SD-NEXT: add x9, sp, #264
-; CHECK-SD-NEXT: ld1 { v4.b }[5], [x12]
-; CHECK-SD-NEXT: add x12, sp, #456
-; CHECK-SD-NEXT: ld1 { v6.b }[3], [x11]
-; CHECK-SD-NEXT: add x11, sp, #760
-; CHECK-SD-NEXT: ld1 { v2.b }[6], [x9]
-; CHECK-SD-NEXT: add x9, sp, #272
-; CHECK-SD-NEXT: ld1 { v5.b }[4], [x10]
-; CHECK-SD-NEXT: add x10, sp, #312
-; CHECK-SD-NEXT: fmov s3, w0
-; CHECK-SD-NEXT: ld1 { v4.b }[6], [x12]
-; CHECK-SD-NEXT: ld1 { v6.b }[4], [x10]
-; CHECK-SD-NEXT: add x10, sp, #320
-; CHECK-SD-NEXT: add x12, sp, #680
-; CHECK-SD-NEXT: ld1 { v2.b }[7], [x9]
-; CHECK-SD-NEXT: add x9, sp, #184
-; CHECK-SD-NEXT: ld1 { v19.b }[1], [x12]
-; CHECK-SD-NEXT: add x12, sp, #776
-; CHECK-SD-NEXT: ld1 { v5.b }[5], [x9]
-; CHECK-SD-NEXT: ld1 { v4.b }[7], [x8]
-; CHECK-SD-NEXT: add x8, sp, #752
-; CHECK-SD-NEXT: ld1 { v6.b }[5], [x10]
-; CHECK-SD-NEXT: ld1 { v16.b }[1], [x8]
-; CHECK-SD-NEXT: add x10, sp, #24
-; CHECK-SD-NEXT: smull v22.8h, v22.8b, v21.8b
-; CHECK-SD-NEXT: ld1 { v7.b }[1], [x10]
-; CHECK-SD-NEXT: add x10, sp, #496
-; CHECK-SD-NEXT: mov v3.b[1], w1
-; CHECK-SD-NEXT: add x9, sp, #192
-; CHECK-SD-NEXT: ldr b20, [sp, #472]
-; CHECK-SD-NEXT: ldr b23, [sp, #208]
-; CHECK-SD-NEXT: ld1 { v16.b }[2], [x11]
-; CHECK-SD-NEXT: add x11, sp, #488
-; CHECK-SD-NEXT: ld1 { v5.b }[6], [x9]
-; CHECK-SD-NEXT: ld1 { v17.b }[1], [x11]
-; CHECK-SD-NEXT: add x11, sp, #944
-; CHECK-SD-NEXT: add x9, sp, #328
-; CHECK-SD-NEXT: ld1 { v18.b }[1], [x11]
-; CHECK-SD-NEXT: add x11, sp, #688
-; CHECK-SD-NEXT: ld1 { v6.b }[6], [x9]
-; CHECK-SD-NEXT: ld1 { v16.b }[3], [x13]
-; CHECK-SD-NEXT: ld1 { v19.b }[2], [x11]
-; CHECK-SD-NEXT: add x11, sp, #504
-; CHECK-SD-NEXT: ld1 { v17.b }[2], [x10]
-; CHECK-SD-NEXT: add x10, sp, #952
-; CHECK-SD-NEXT: add x13, sp, #784
-; CHECK-SD-NEXT: ld1 { v18.b }[2], [x10]
-; CHECK-SD-NEXT: add x10, sp, #32
-; CHECK-SD-NEXT: add x9, sp, #40
-; CHECK-SD-NEXT: ld1 { v16.b }[4], [x12]
-; CHECK-SD-NEXT: add x12, sp, #696
-; CHECK-SD-NEXT: ld1 { v7.b }[2], [x10]
-; CHECK-SD-NEXT: ld1 { v17.b }[3], [x11]
-; CHECK-SD-NEXT: add x11, sp, #960
-; CHECK-SD-NEXT: ld1 { v19.b }[3], [x12]
-; CHECK-SD-NEXT: ld1 { v18.b }[3], [x11]
-; CHECK-SD-NEXT: add x10, sp, #512
-; CHECK-SD-NEXT: add x11, sp, #704
-; CHECK-SD-NEXT: ld1 { v16.b }[5], [x13]
-; CHECK-SD-NEXT: add x12, sp, #792
-; CHECK-SD-NEXT: sshll v24.4s, v22.4h, #0
-; CHECK-SD-NEXT: ld1 { v17.b }[4], [x10]
-; CHECK-SD-NEXT: add x10, sp, #968
-; CHECK-SD-NEXT: ld1 { v19.b }[4], [x11]
-; CHECK-SD-NEXT: ld1 { v18.b }[4], [x10]
-; CHECK-SD-NEXT: add x10, sp, #520
-; CHECK-SD-NEXT: add x11, sp, #976
-; CHECK-SD-NEXT: ld1 { v16.b }[6], [x12]
-; CHECK-SD-NEXT: add x12, sp, #712
-; CHECK-SD-NEXT: smull v20.8h, v23.8b, v20.8b
-; CHECK-SD-NEXT: ld1 { v17.b }[5], [x10]
-; CHECK-SD-NEXT: ld1 { v19.b }[5], [x12]
-; CHECK-SD-NEXT: add x12, sp, #720
-; CHECK-SD-NEXT: ld1 { v18.b }[5], [x11]
-; CHECK-SD-NEXT: add x11, sp, #528
-; CHECK-SD-NEXT: add x10, sp, #800
-; CHECK-SD-NEXT: ld1 { v16.b }[7], [x10]
-; CHECK-SD-NEXT: add x10, sp, #536
+; CHECK-SD-NEXT: ld1 { v3.b }[4], [x15]
+; CHECK-SD-NEXT: add x13, sp, #296
+; CHECK-SD-NEXT: add x15, sp, #168
+; CHECK-SD-NEXT: ld1 { v6.b }[2], [x13]
+; CHECK-SD-NEXT: add x13, sp, #256
+; CHECK-SD-NEXT: ld1 { v5.b }[3], [x15]
+; CHECK-SD-NEXT: add x16, sp, #176
+; CHECK-SD-NEXT: add x15, sp, #448
+; CHECK-SD-NEXT: ld1 { v4.b }[4], [x14]
+; CHECK-SD-NEXT: ld1 { v3.b }[5], [x13]
+; CHECK-SD-NEXT: add x14, sp, #304
+; CHECK-SD-NEXT: ld1 { v6.b }[3], [x14]
+; CHECK-SD-NEXT: add x13, sp, #264
+; CHECK-SD-NEXT: ld1 { v1.b }[7], [x12]
+; CHECK-SD-NEXT: ld1 { v5.b }[4], [x16]
+; CHECK-SD-NEXT: add x12, sp, #312
+; CHECK-SD-NEXT: add x14, sp, #184
+; CHECK-SD-NEXT: ld1 { v4.b }[5], [x15]
+; CHECK-SD-NEXT: ld1 { v3.b }[6], [x13]
+; CHECK-SD-NEXT: add x13, sp, #456
+; CHECK-SD-NEXT: ld1 { v6.b }[4], [x12]
+; CHECK-SD-NEXT: add x12, sp, #272
+; CHECK-SD-NEXT: add x15, sp, #496
+; CHECK-SD-NEXT: ld1 { v5.b }[5], [x14]
+; CHECK-SD-NEXT: add x14, sp, #192
+; CHECK-SD-NEXT: add x16, sp, #504
+; CHECK-SD-NEXT: ld1 { v4.b }[6], [x13]
+; CHECK-SD-NEXT: ld1 { v3.b }[7], [x12]
+; CHECK-SD-NEXT: add x12, sp, #320
+; CHECK-SD-NEXT: ld1 { v6.b }[5], [x12]
+; CHECK-SD-NEXT: add x13, sp, #464
+; CHECK-SD-NEXT: fmov s22, w9
+; CHECK-SD-NEXT: ld1 { v5.b }[6], [x14]
+; CHECK-SD-NEXT: add x14, sp, #752
+; CHECK-SD-NEXT: fmov s23, w8
+; CHECK-SD-NEXT: ld1 { v16.b }[1], [x14]
+; CHECK-SD-NEXT: ld1 { v4.b }[7], [x13]
+; CHECK-SD-NEXT: add x13, sp, #328
+; CHECK-SD-NEXT: ld1 { v6.b }[6], [x13]
+; CHECK-SD-NEXT: add x13, sp, #760
+; CHECK-SD-NEXT: add x14, sp, #488
+; CHECK-SD-NEXT: ld1 { v17.b }[1], [x14]
+; CHECK-SD-NEXT: add x14, sp, #680
+; CHECK-SD-NEXT: mov v2.b[1], w1
+; CHECK-SD-NEXT: ld1 { v16.b }[2], [x13]
+; CHECK-SD-NEXT: add x13, sp, #944
+; CHECK-SD-NEXT: ld1 { v19.b }[1], [x14]
+; CHECK-SD-NEXT: ld1 { v18.b }[1], [x13]
+; CHECK-SD-NEXT: add x14, sp, #768
+; CHECK-SD-NEXT: add x13, sp, #24
+; CHECK-SD-NEXT: ld1 { v17.b }[2], [x15]
+; CHECK-SD-NEXT: add x15, sp, #688
+; CHECK-SD-NEXT: ld1 { v7.b }[1], [x13]
+; CHECK-SD-NEXT: ld1 { v16.b }[3], [x14]
+; CHECK-SD-NEXT: add x14, sp, #952
+; CHECK-SD-NEXT: ld1 { v19.b }[2], [x15]
+; CHECK-SD-NEXT: ld1 { v18.b }[2], [x14]
+; CHECK-SD-NEXT: add x13, sp, #776
+; CHECK-SD-NEXT: add x14, sp, #696
+; CHECK-SD-NEXT: ld1 { v17.b }[3], [x16]
+; CHECK-SD-NEXT: add x15, sp, #512
+; CHECK-SD-NEXT: add x16, sp, #520
+; CHECK-SD-NEXT: ld1 { v16.b }[4], [x13]
+; CHECK-SD-NEXT: add x13, sp, #960
+; CHECK-SD-NEXT: ld1 { v19.b }[3], [x14]
+; CHECK-SD-NEXT: ld1 { v18.b }[3], [x13]
+; CHECK-SD-NEXT: add x14, sp, #784
+; CHECK-SD-NEXT: add x13, sp, #32
+; CHECK-SD-NEXT: ld1 { v17.b }[4], [x15]
+; CHECK-SD-NEXT: add x15, sp, #704
+; CHECK-SD-NEXT: ld1 { v7.b }[2], [x13]
+; CHECK-SD-NEXT: ld1 { v16.b }[5], [x14]
+; CHECK-SD-NEXT: add x14, sp, #968
+; CHECK-SD-NEXT: ld1 { v19.b }[4], [x15]
+; CHECK-SD-NEXT: ld1 { v18.b }[4], [x14]
+; CHECK-SD-NEXT: add x13, sp, #792
+; CHECK-SD-NEXT: add x14, sp, #712
+; CHECK-SD-NEXT: ld1 { v17.b }[5], [x16]
+; CHECK-SD-NEXT: add x15, sp, #528
+; CHECK-SD-NEXT: add x10, sp, #40
+; CHECK-SD-NEXT: ld1 { v16.b }[6], [x13]
+; CHECK-SD-NEXT: add x13, sp, #976
+; CHECK-SD-NEXT: ld1 { v19.b }[5], [x14]
+; CHECK-SD-NEXT: ld1 { v18.b }[5], [x13]
+; CHECK-SD-NEXT: add x14, sp, #984
+; CHECK-SD-NEXT: add x13, sp, #800
+; CHECK-SD-NEXT: ld1 { v17.b }[6], [x15]
+; CHECK-SD-NEXT: add x15, sp, #720
+; CHECK-SD-NEXT: sshll v24.4s, v21.4h, #0
+; CHECK-SD-NEXT: ld1 { v19.b }[6], [x15]
+; CHECK-SD-NEXT: ld1 { v16.b }[7], [x13]
+; CHECK-SD-NEXT: add x13, sp, #992
+; CHECK-SD-NEXT: ld1 { v18.b }[6], [x14]
+; CHECK-SD-NEXT: add x14, sp, #728
+; CHECK-SD-NEXT: ld1 { v7.b }[3], [x10]
+; CHECK-SD-NEXT: ld1 { v17.b }[7], [x11]
+; CHECK-SD-NEXT: smull v21.8h, v23.8b, v22.8b
; CHECK-SD-NEXT: ldr b22, [sp, #872]
-; CHECK-SD-NEXT: ld1 { v17.b }[6], [x11]
-; CHECK-SD-NEXT: add x11, sp, #984
-; CHECK-SD-NEXT: ld1 { v19.b }[6], [x12]
-; CHECK-SD-NEXT: ld1 { v18.b }[6], [x11]
-; CHECK-SD-NEXT: add x11, sp, #992
-; CHECK-SD-NEXT: add x12, sp, #728
+; CHECK-SD-NEXT: ld1 { v19.b }[7], [x14]
; CHECK-SD-NEXT: ldr b23, [sp, #608]
-; CHECK-SD-NEXT: ld1 { v7.b }[3], [x9]
-; CHECK-SD-NEXT: add x9, sp, #880
-; CHECK-SD-NEXT: ld1 { v17.b }[7], [x10]
-; CHECK-SD-NEXT: ld1 { v19.b }[7], [x12]
-; CHECK-SD-NEXT: add x10, sp, #816
-; CHECK-SD-NEXT: ld1 { v18.b }[7], [x11]
-; CHECK-SD-NEXT: add x11, sp, #552
-; CHECK-SD-NEXT: add x12, sp, #616
-; CHECK-SD-NEXT: mov v3.b[2], w2
-; CHECK-SD-NEXT: ld1 { v22.b }[1], [x9]
-; CHECK-SD-NEXT: ld1 { v23.b }[1], [x12]
+; CHECK-SD-NEXT: add x9, sp, #816
+; CHECK-SD-NEXT: ld1 { v18.b }[7], [x13]
+; CHECK-SD-NEXT: add x10, sp, #552
+; CHECK-SD-NEXT: add x8, sp, #880
; CHECK-SD-NEXT: smull v16.8h, v17.8b, v16.8b
-; CHECK-SD-NEXT: add x12, sp, #560
-; CHECK-SD-NEXT: add x9, sp, #888
+; CHECK-SD-NEXT: add x11, sp, #616
+; CHECK-SD-NEXT: mov v2.b[2], w2
+; CHECK-SD-NEXT: ld1 { v22.b }[1], [x8]
+; CHECK-SD-NEXT: ld1 { v23.b }[1], [x11]
+; CHECK-SD-NEXT: add x11, sp, #560
; CHECK-SD-NEXT: smull v17.8h, v19.8b, v18.8b
; CHECK-SD-NEXT: ldr b18, [sp, #808]
; CHECK-SD-NEXT: ldr b19, [sp, #544]
+; CHECK-SD-NEXT: add x8, sp, #888
; CHECK-SD-NEXT: add x13, sp, #624
-; CHECK-SD-NEXT: ld1 { v22.b }[2], [x9]
-; CHECK-SD-NEXT: add x9, sp, #896
-; CHECK-SD-NEXT: ld1 { v18.b }[1], [x10]
-; CHECK-SD-NEXT: ld1 { v19.b }[1], [x11]
-; CHECK-SD-NEXT: add x11, sp, #824
-; CHECK-SD-NEXT: add x10, sp, #48
+; CHECK-SD-NEXT: movi v20.2d, #0000000000000000
+; CHECK-SD-NEXT: ld1 { v18.b }[1], [x9]
+; CHECK-SD-NEXT: ld1 { v19.b }[1], [x10]
+; CHECK-SD-NEXT: add x10, sp, #824
+; CHECK-SD-NEXT: add x9, sp, #48
+; CHECK-SD-NEXT: ld1 { v22.b }[2], [x8]
; CHECK-SD-NEXT: ld1 { v23.b }[2], [x13]
-; CHECK-SD-NEXT: mov v3.b[3], w3
-; CHECK-SD-NEXT: ld1 { v7.b }[4], [x10]
-; CHECK-SD-NEXT: add x10, sp, #832
-; CHECK-SD-NEXT: ld1 { v22.b }[3], [x9]
-; CHECK-SD-NEXT: ld1 { v18.b }[2], [x11]
-; CHECK-SD-NEXT: ld1 { v19.b }[2], [x12]
-; CHECK-SD-NEXT: add x11, sp, #568
-; CHECK-SD-NEXT: add x12, sp, #632
-; CHECK-SD-NEXT: add x9, sp, #904
+; CHECK-SD-NEXT: mov v2.b[3], w3
+; CHECK-SD-NEXT: ld1 { v7.b }[4], [x9]
+; CHECK-SD-NEXT: add x9, sp, #832
+; CHECK-SD-NEXT: ld1 { v18.b }[2], [x10]
+; CHECK-SD-NEXT: ld1 { v19.b }[2], [x11]
+; CHECK-SD-NEXT: add x10, sp, #568
+; CHECK-SD-NEXT: add x8, sp, #896
+; CHECK-SD-NEXT: add x11, sp, #632
; CHECK-SD-NEXT: add x13, sp, #640
-; CHECK-SD-NEXT: ld1 { v23.b }[3], [x12]
-; CHECK-SD-NEXT: add x12, sp, #576
-; CHECK-SD-NEXT: mov v3.b[4], w4
-; CHECK-SD-NEXT: ld1 { v18.b }[3], [x10]
-; CHECK-SD-NEXT: ld1 { v19.b }[3], [x11]
-; CHECK-SD-NEXT: add x11, sp, #840
-; CHECK-SD-NEXT: add x10, sp, #56
-; CHECK-SD-NEXT: ld1 { v22.b }[4], [x9]
-; CHECK-SD-NEXT: add x9, sp, #912
+; CHECK-SD-NEXT: ld1 { v22.b }[3], [x8]
+; CHECK-SD-NEXT: ld1 { v23.b }[3], [x11]
+; CHECK-SD-NEXT: add x11, sp, #576
+; CHECK-SD-NEXT: ld1 { v18.b }[3], [x9]
+; CHECK-SD-NEXT: ld1 { v19.b }[3], [x10]
+; CHECK-SD-NEXT: add x10, sp, #840
+; CHECK-SD-NEXT: mov v2.b[4], w4
+; CHECK-SD-NEXT: add x8, sp, #904
+; CHECK-SD-NEXT: add x9, sp, #56
+; CHECK-SD-NEXT: ld1 { v22.b }[4], [x8]
; CHECK-SD-NEXT: ld1 { v23.b }[4], [x13]
-; CHECK-SD-NEXT: ld1 { v7.b }[5], [x10]
-; CHECK-SD-NEXT: add x10, sp, #848
-; CHECK-SD-NEXT: ld1 { v18.b }[4], [x11]
-; CHECK-SD-NEXT: ld1 { v19.b }[4], [x12]
-; CHECK-SD-NEXT: add x11, sp, #584
-; CHECK-SD-NEXT: add x12, sp, #648
-; CHECK-SD-NEXT: mov v3.b[5], w5
-; CHECK-SD-NEXT: ld1 { v22.b }[5], [x9]
-; CHECK-SD-NEXT: ld1 { v23.b }[5], [x12]
-; CHECK-SD-NEXT: add x12, sp, #592
-; CHECK-SD-NEXT: movi v21.2d, #0000000000000000
-; CHECK-SD-NEXT: ld1 { v18.b }[5], [x10]
-; CHECK-SD-NEXT: ld1 { v19.b }[5], [x11]
-; CHECK-SD-NEXT: add x11, sp, #856
-; CHECK-SD-NEXT: add x9, sp, #920
+; CHECK-SD-NEXT: ld1 { v7.b }[5], [x9]
+; CHECK-SD-NEXT: ld1 { v18.b }[4], [x10]
+; CHECK-SD-NEXT: ld1 { v19.b }[4], [x11]
+; CHECK-SD-NEXT: add x9, sp, #848
+; CHECK-SD-NEXT: add x10, sp, #584
+; CHECK-SD-NEXT: add x8, sp, #912
+; CHECK-SD-NEXT: add x11, sp, #648
+; CHECK-SD-NEXT: mov v2.b[5], w5
+; CHECK-SD-NEXT: ld1 { v22.b }[5], [x8]
+; CHECK-SD-NEXT: ld1 { v23.b }[5], [x11]
+; CHECK-SD-NEXT: ld1 { v18.b }[5], [x9]
+; CHECK-SD-NEXT: ld1 { v19.b }[5], [x10]
+; CHECK-SD-NEXT: add x10, sp, #856
+; CHECK-SD-NEXT: add x11, sp, #592
+; CHECK-SD-NEXT: add x8, sp, #920
; CHECK-SD-NEXT: add x13, sp, #656
-; CHECK-SD-NEXT: add x10, sp, #64
-; CHECK-SD-NEXT: ld1 { v22.b }[6], [x9]
+; CHECK-SD-NEXT: add x9, sp, #64
+; CHECK-SD-NEXT: ld1 { v22.b }[6], [x8]
; CHECK-SD-NEXT: ld1 { v23.b }[6], [x13]
-; CHECK-SD-NEXT: mov v3.b[6], w6
-; CHECK-SD-NEXT: ld1 { v18.b }[6], [x11]
-; CHECK-SD-NEXT: ld1 { v19.b }[6], [x12]
-; CHECK-SD-NEXT: ld1 { v7.b }[6], [x10]
-; CHECK-SD-NEXT: add x10, sp, #864
-; CHECK-SD-NEXT: add x11, sp, #600
-; CHECK-SD-NEXT: add x9, sp, #928
-; CHECK-SD-NEXT: add x12, sp, #664
-; CHECK-SD-NEXT: mov v21.s[0], v24.s[0]
-; CHECK-SD-NEXT: ld1 { v22.b }[7], [x9]
-; CHECK-SD-NEXT: ld1 { v18.b }[7], [x10]
-; CHECK-SD-NEXT: ld1 { v19.b }[7], [x11]
-; CHECK-SD-NEXT: ld1 { v23.b }[7], [x12]
-; CHECK-SD-NEXT: add x8, sp, #200
-; CHECK-SD-NEXT: mov v3.b[7], w7
-; CHECK-SD-NEXT: add x10, sp, #336
-; CHECK-SD-NEXT: ld1 { v5.b }[7], [x8]
+; CHECK-SD-NEXT: ld1 { v18.b }[6], [x10]
+; CHECK-SD-NEXT: ld1 { v19.b }[6], [x11]
+; CHECK-SD-NEXT: mov v2.b[6], w6
+; CHECK-SD-NEXT: ld1 { v7.b }[6], [x9]
+; CHECK-SD-NEXT: add x9, sp, #864
+; CHECK-SD-NEXT: add x10, sp, #600
+; CHECK-SD-NEXT: add x8, sp, #928
+; CHECK-SD-NEXT: add x11, sp, #664
+; CHECK-SD-NEXT: mov v20.s[0], v24.s[0]
+; CHECK-SD-NEXT: ld1 { v18.b }[7], [x9]
+; CHECK-SD-NEXT: ld1 { v19.b }[7], [x10]
+; CHECK-SD-NEXT: ld1 { v22.b }[7], [x8]
+; CHECK-SD-NEXT: ld1 { v23.b }[7], [x11]
+; CHECK-SD-NEXT: mov v2.b[7], w7
+; CHECK-SD-NEXT: add x12, sp, #200
+; CHECK-SD-NEXT: add x9, sp, #336
; CHECK-SD-NEXT: add x8, sp, #72
-; CHECK-SD-NEXT: ld1 { v6.b }[7], [x10]
+; CHECK-SD-NEXT: ld1 { v5.b }[7], [x12]
; CHECK-SD-NEXT: smull v18.8h, v19.8b, v18.8b
; CHECK-SD-NEXT: movi v19.2d, #0000000000000000
+; CHECK-SD-NEXT: ld1 { v6.b }[7], [x9]
; CHECK-SD-NEXT: ld1 { v7.b }[7], [x8]
; CHECK-SD-NEXT: smull v22.8h, v23.8b, v22.8b
-; CHECK-SD-NEXT: sshll v20.4s, v20.4h, #0
+; CHECK-SD-NEXT: sshll v21.4s, v21.4h, #0
; CHECK-SD-NEXT: smull v0.8h, v1.8b, v0.8b
-; CHECK-SD-NEXT: saddw v1.4s, v21.4s, v16.4h
-; CHECK-SD-NEXT: smull v2.8h, v3.8b, v2.8b
+; CHECK-SD-NEXT: saddw v1.4s, v20.4s, v16.4h
+; CHECK-SD-NEXT: smull v2.8h, v2.8b, v3.8b
; CHECK-SD-NEXT: smull v3.8h, v5.8b, v4.8b
; CHECK-SD-NEXT: smull v4.8h, v7.8b, v6.8b
-; CHECK-SD-NEXT: mov v19.s[0], v20.s[0]
+; CHECK-SD-NEXT: mov v19.s[0], v21.s[0]
; CHECK-SD-NEXT: saddl2 v5.4s, v18.8h, v17.8h
-; CHECK-SD-NEXT: saddl v7.4s, v18.4h, v17.4h
; CHECK-SD-NEXT: saddl2 v6.4s, v16.8h, v22.8h
+; CHECK-SD-NEXT: saddl v7.4s, v18.4h, v17.4h
; CHECK-SD-NEXT: saddw v1.4s, v1.4s, v22.4h
; CHECK-SD-NEXT: saddl2 v17.4s, v2.8h, v0.8h
; CHECK-SD-NEXT: saddl2 v16.4s, v4.8h, v3.8h
-; CHECK-SD-NEXT: saddl v3.4s, v4.4h, v3.4h
; CHECK-SD-NEXT: saddw v2.4s, v19.4s, v2.4h
; CHECK-SD-NEXT: add v5.4s, v6.4s, v5.4s
; CHECK-SD-NEXT: add v1.4s, v1.4s, v7.4s
+; CHECK-SD-NEXT: saddl v3.4s, v4.4h, v3.4h
; CHECK-SD-NEXT: add v6.4s, v17.4s, v16.4s
; CHECK-SD-NEXT: saddw v0.4s, v2.4s, v0.4h
; CHECK-SD-NEXT: add v1.4s, v1.4s, v5.4s
diff --git a/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll b/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
index 4b917977acd58..6f21896dfa9ed 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
@@ -195,7 +195,7 @@ define amdgpu_ps float @v_test_cvt_v2f64_v2bf16_v(<2 x double> %src) {
; GFX-950-NEXT: v_cvt_f32_f64_e32 v7, v[0:1]
; GFX-950-NEXT: v_cndmask_b32_e64 v2, -1, 1, s[2:3]
; GFX-950-NEXT: v_add_u32_e32 v2, v6, v2
-; GFX-950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX-950-NEXT: s_or_b64 vcc, s[0:1], vcc
; GFX-950-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX-950-NEXT: v_cvt_f64_f32_e32 v[2:3], v7
; GFX-950-NEXT: v_and_b32_e32 v8, 1, v7
@@ -232,7 +232,7 @@ define amdgpu_ps float @v_test_cvt_v2f64_v2bf16_v(<2 x double> %src) {
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-NEXT: v_add_nc_u32_e32 v0, v9, v0
; GFX1250-NEXT: v_cmp_ne_u32_e64 s2, 0, v11
-; GFX1250-NEXT: s_or_b32 vcc_lo, s1, vcc_lo
+; GFX1250-NEXT: s_or_b32 vcc_lo, vcc_lo, s1
; GFX1250-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo
; GFX1250-NEXT: s_or_b32 vcc_lo, s2, s0
; GFX1250-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
index 0193feec27c86..ecaa11dd3cc26 100644
--- a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
+++ b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
@@ -3750,56 +3750,57 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GCN-ISEL-NEXT: [[S_MUL_I32_19:%[0-9]+]]:sreg_32 = S_MUL_I32 [[COPY22]], [[COPY70]]
; GCN-ISEL-NEXT: [[S_USUBO:%[0-9]+]]:sreg_32, [[S_USUBO1:%[0-9]+]]:sreg_64_xexec = S_USUBO_PSEUDO [[COPY57]], killed [[S_MUL_I32_19]], implicit-def dead $scc
; GCN-ISEL-NEXT: [[S_SUB_C:%[0-9]+]]:sreg_32, [[S_SUB_C1:%[0-9]+]]:sreg_64_xexec = S_SUB_CO_PSEUDO killed [[S_SUB_I32_3]], [[COPY23]], [[S_USUBO1]], implicit-def dead $scc
-; GCN-ISEL-NEXT: [[S_USUBO2:%[0-9]+]]:sreg_32, [[S_USUBO3:%[0-9]+]]:sreg_64_xexec = S_USUBO_PSEUDO [[S_USUBO]], [[COPY22]], implicit-def dead $scc
+; GCN-ISEL-NEXT: [[COPY73:%[0-9]+]]:sreg_32 = COPY killed [[S_USUBO]]
+; GCN-ISEL-NEXT: [[S_USUBO2:%[0-9]+]]:sreg_32, [[S_USUBO3:%[0-9]+]]:sreg_64_xexec = S_USUBO_PSEUDO [[COPY73]], [[COPY22]], implicit-def dead $scc
; GCN-ISEL-NEXT: [[S_SUB_C2:%[0-9]+]]:sreg_32, [[S_SUB_C3:%[0-9]+]]:sreg_64_xexec = S_SUB_CO_PSEUDO killed [[S_SUB_C]], [[S_MOV_B32_10]], killed [[S_USUBO3]], implicit-def dead $scc
-; GCN-ISEL-NEXT: S_CMP_GE_U32 [[S_SUB_C2]], [[COPY23]], implicit-def $scc
+; GCN-ISEL-NEXT: [[COPY74:%[0-9]+]]:sreg_32 = COPY killed [[S_SUB_C2]]
+; GCN-ISEL-NEXT: S_CMP_GE_U32 [[COPY74]], [[COPY23]], implicit-def $scc
; GCN-ISEL-NEXT: [[S_MOV_B32_11:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
; GCN-ISEL-NEXT: [[S_CSELECT_B32_3:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[S_MOV_B32_11]], [[S_MOV_B32_10]], implicit $scc
; GCN-ISEL-NEXT: S_CMP_GE_U32 killed [[S_USUBO2]], [[COPY22]], implicit-def $scc
; GCN-ISEL-NEXT: [[S_CSELECT_B32_4:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[S_MOV_B32_11]], [[S_MOV_B32_10]], implicit $scc
-; GCN-ISEL-NEXT: S_CMP_EQ_U32 [[S_SUB_C2]], [[COPY23]], implicit-def $scc
+; GCN-ISEL-NEXT: S_CMP_EQ_U32 [[COPY74]], [[COPY23]], implicit-def $scc
; GCN-ISEL-NEXT: [[S_CSELECT_B32_5:%[0-9]+]]:sreg_32 = S_CSELECT_B32 killed [[S_CSELECT_B32_4]], killed [[S_CSELECT_B32_3]], implicit $scc
-; GCN-ISEL-NEXT: [[COPY73:%[0-9]+]]:sreg_32 = COPY killed [[S_CSELECT_B32_5]]
; GCN-ISEL-NEXT: [[REG_SEQUENCE22:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY70]], %subreg.sub0, [[COPY69]], %subreg.sub1
; GCN-ISEL-NEXT: [[S_MOV_B64_2:%[0-9]+]]:sreg_64 = S_MOV_B64 1
; GCN-ISEL-NEXT: [[S_ADD_U6:%[0-9]+]]:sreg_64 = S_ADD_U64_PSEUDO [[REG_SEQUENCE22]], killed [[S_MOV_B64_2]], implicit-def dead $scc
-; GCN-ISEL-NEXT: [[COPY74:%[0-9]+]]:sreg_32 = COPY [[S_ADD_U6]].sub0
+; GCN-ISEL-NEXT: [[COPY75:%[0-9]+]]:sreg_32 = COPY [[S_ADD_U6]].sub0
; GCN-ISEL-NEXT: [[S_MOV_B64_3:%[0-9]+]]:sreg_64 = S_MOV_B64 2
; GCN-ISEL-NEXT: [[S_ADD_U7:%[0-9]+]]:sreg_64 = S_ADD_U64_PSEUDO [[REG_SEQUENCE22]], killed [[S_MOV_B64_3]], implicit-def dead $scc
-; GCN-ISEL-NEXT: [[COPY75:%[0-9]+]]:sreg_32 = COPY [[S_ADD_U7]].sub0
-; GCN-ISEL-NEXT: S_CMP_LG_U32 killed [[COPY73]], [[S_MOV_B32_10]], implicit-def $scc
-; GCN-ISEL-NEXT: [[S_CSELECT_B32_6:%[0-9]+]]:sreg_32 = S_CSELECT_B32 killed [[COPY75]], killed [[COPY74]], implicit $scc
-; GCN-ISEL-NEXT: [[COPY76:%[0-9]+]]:sreg_32 = COPY [[S_ADD_U6]].sub1
-; GCN-ISEL-NEXT: [[COPY77:%[0-9]+]]:sreg_32 = COPY [[S_ADD_U7]].sub1
-; GCN-ISEL-NEXT: [[S_CSELECT_B32_7:%[0-9]+]]:sreg_32 = S_CSELECT_B32 killed [[COPY77]], killed [[COPY76]], implicit $scc
+; GCN-ISEL-NEXT: [[COPY76:%[0-9]+]]:sreg_32 = COPY [[S_ADD_U7]].sub0
+; GCN-ISEL-NEXT: S_CMP_LG_U32 killed [[S_CSELECT_B32_5]], [[S_MOV_B32_10]], implicit-def $scc
+; GCN-ISEL-NEXT: [[S_CSELECT_B32_6:%[0-9]+]]:sreg_32 = S_CSELECT_B32 killed [[COPY76]], killed [[COPY75]], implicit $scc
+; GCN-ISEL-NEXT: [[COPY77:%[0-9]+]]:sreg_32 = COPY [[S_ADD_U6]].sub1
+; GCN-ISEL-NEXT: [[COPY78:%[0-9]+]]:sreg_32 = COPY [[S_ADD_U7]].sub1
+; GCN-ISEL-NEXT: [[S_CSELECT_B32_7:%[0-9]+]]:sreg_32 = S_CSELECT_B32 killed [[COPY78]], killed [[COPY77]], implicit $scc
; GCN-ISEL-NEXT: [[S_SUB_C4:%[0-9]+]]:sreg_32, [[S_SUB_C5:%[0-9]+]]:sreg_64_xexec = S_SUB_CO_PSEUDO [[COPY62]], [[S_ADD_I32_8]], [[S_USUBO1]], implicit-def dead $scc
-; GCN-ISEL-NEXT: S_CMP_GE_U32 [[S_SUB_C4]], [[COPY23]], implicit-def $scc
+; GCN-ISEL-NEXT: [[COPY79:%[0-9]+]]:sreg_32 = COPY killed [[S_SUB_C4]]
+; GCN-ISEL-NEXT: S_CMP_GE_U32 [[COPY79]], [[COPY23]], implicit-def $scc
; GCN-ISEL-NEXT: [[S_CSELECT_B32_8:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[S_MOV_B32_11]], [[S_MOV_B32_10]], implicit $scc
-; GCN-ISEL-NEXT: S_CMP_GE_U32 [[S_USUBO]], [[COPY22]], implicit-def $scc
+; GCN-ISEL-NEXT: S_CMP_GE_U32 [[COPY73]], [[COPY22]], implicit-def $scc
; GCN-ISEL-NEXT: [[S_CSELECT_B32_9:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[S_MOV_B32_11]], [[S_MOV_B32_10]], implicit $scc
-; GCN-ISEL-NEXT: S_CMP_EQ_U32 [[S_SUB_C4]], [[COPY23]], implicit-def $scc
+; GCN-ISEL-NEXT: S_CMP_EQ_U32 [[COPY79]], [[COPY23]], implicit-def $scc
; GCN-ISEL-NEXT: [[S_CSELECT_B32_10:%[0-9]+]]:sreg_32 = S_CSELECT_B32 killed [[S_CSELECT_B32_9]], killed [[S_CSELECT_B32_8]], implicit $scc
-; GCN-ISEL-NEXT: [[COPY78:%[0-9]+]]:sreg_32 = COPY killed [[S_CSELECT_B32_10]]
-; GCN-ISEL-NEXT: S_CMP_LG_U32 killed [[COPY78]], [[S_MOV_B32_10]], implicit-def $scc
+; GCN-ISEL-NEXT: S_CMP_LG_U32 killed [[S_CSELECT_B32_10]], [[S_MOV_B32_10]], implicit-def $scc
; GCN-ISEL-NEXT: [[S_CSELECT_B32_11:%[0-9]+]]:sreg_32 = S_CSELECT_B32 killed [[S_CSELECT_B32_7]], [[COPY69]], implicit $scc
; GCN-ISEL-NEXT: [[S_CSELECT_B32_12:%[0-9]+]]:sreg_32 = S_CSELECT_B32 killed [[S_CSELECT_B32_6]], [[COPY70]], implicit $scc
; GCN-ISEL-NEXT: [[REG_SEQUENCE23:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[S_CSELECT_B32_12]], %subreg.sub0, killed [[S_CSELECT_B32_11]], %subreg.sub1
; GCN-ISEL-NEXT: [[S_MOV_B64_4:%[0-9]+]]:sreg_64 = S_MOV_B64 0
-; GCN-ISEL-NEXT: [[COPY79:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE23]]
+; GCN-ISEL-NEXT: [[COPY80:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE23]]
; GCN-ISEL-NEXT: S_BRANCH %bb.1
; GCN-ISEL-NEXT: {{ $}}
; GCN-ISEL-NEXT: bb.4..split:
; GCN-ISEL-NEXT: [[PHI2:%[0-9]+]]:sreg_64 = PHI [[PHI]], %bb.1, [[COPY21]], %bb.2
-; GCN-ISEL-NEXT: [[COPY80:%[0-9]+]]:sreg_32 = COPY [[COPY7]].sub1
-; GCN-ISEL-NEXT: [[COPY81:%[0-9]+]]:sreg_32 = COPY [[COPY7]].sub0
-; GCN-ISEL-NEXT: [[REG_SEQUENCE24:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[COPY81]], %subreg.sub0, killed [[COPY80]], %subreg.sub1
-; GCN-ISEL-NEXT: [[COPY82:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE24]].sub1
-; GCN-ISEL-NEXT: [[COPY83:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE24]].sub0
+; GCN-ISEL-NEXT: [[COPY81:%[0-9]+]]:sreg_32 = COPY [[COPY7]].sub1
+; GCN-ISEL-NEXT: [[COPY82:%[0-9]+]]:sreg_32 = COPY [[COPY7]].sub0
+; GCN-ISEL-NEXT: [[REG_SEQUENCE24:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[COPY82]], %subreg.sub0, killed [[COPY81]], %subreg.sub1
+; GCN-ISEL-NEXT: [[COPY83:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE24]].sub1
+; GCN-ISEL-NEXT: [[COPY84:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE24]].sub0
; GCN-ISEL-NEXT: [[S_MOV_B32_12:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
; GCN-ISEL-NEXT: [[S_MOV_B32_13:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
-; GCN-ISEL-NEXT: [[REG_SEQUENCE25:%[0-9]+]]:sgpr_128 = REG_SEQUENCE killed [[COPY83]], %subreg.sub0, killed [[COPY82]], %subreg.sub1, killed [[S_MOV_B32_13]], %subreg.sub2, killed [[S_MOV_B32_12]], %subreg.sub3
-; GCN-ISEL-NEXT: [[COPY84:%[0-9]+]]:vreg_64 = COPY [[PHI2]]
-; GCN-ISEL-NEXT: BUFFER_STORE_DWORDX2_OFFSET [[COPY84]], killed [[REG_SEQUENCE25]], 0, 0, 0, 0, implicit $exec :: (store (s64) into %ir.15, addrspace 1)
+; GCN-ISEL-NEXT: [[REG_SEQUENCE25:%[0-9]+]]:sgpr_128 = REG_SEQUENCE killed [[COPY84]], %subreg.sub0, killed [[COPY83]], %subreg.sub1, killed [[S_MOV_B32_13]], %subreg.sub2, killed [[S_MOV_B32_12]], %subreg.sub3
+; GCN-ISEL-NEXT: [[COPY85:%[0-9]+]]:vreg_64 = COPY [[PHI2]]
+; GCN-ISEL-NEXT: BUFFER_STORE_DWORDX2_OFFSET [[COPY85]], killed [[REG_SEQUENCE25]], 0, 0, 0, 0, implicit $exec :: (store (s64) into %ir.15, addrspace 1)
; GCN-ISEL-NEXT: S_ENDPGM 0
%result = udiv i64 %x, %y
store i64 %result, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/clmul.ll b/llvm/test/CodeGen/AMDGPU/clmul.ll
index 03cf3da9bde19..a649ac3c29338 100644
--- a/llvm/test/CodeGen/AMDGPU/clmul.ll
+++ b/llvm/test/CodeGen/AMDGPU/clmul.ll
@@ -978,15 +978,15 @@ define amdgpu_kernel void @test_clmulr_i32(ptr addrspace(1) %out, ptr addrspace(
; SI-NEXT: s_mov_b32 s9, s7
; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
; SI-NEXT: s_mov_b32 s7, 0
-; SI-NEXT: s_mov_b32 s21, s7
+; SI-NEXT: s_mov_b32 s19, s7
; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5
+; SI-NEXT: s_mov_b32 s13, s7
; SI-NEXT: s_mov_b32 s9, s7
-; SI-NEXT: s_mov_b32 s15, s7
; SI-NEXT: s_mov_b32 s11, s7
-; SI-NEXT: s_mov_b32 s13, s7
+; SI-NEXT: s_mov_b32 s15, s7
; SI-NEXT: s_mov_b32 s17, s7
-; SI-NEXT: s_mov_b32 s19, s7
+; SI-NEXT: s_mov_b32 s21, s7
; SI-NEXT: s_mov_b32 s23, s7
; SI-NEXT: s_mov_b32 s25, s7
; SI-NEXT: s_mov_b32 s27, s7
@@ -996,139 +996,139 @@ define amdgpu_kernel void @test_clmulr_i32(ptr addrspace(1) %out, ptr addrspace(
; SI-NEXT: s_mov_b32 s37, s7
; SI-NEXT: s_mov_b32 s39, s7
; SI-NEXT: s_mov_b32 s41, s7
-; SI-NEXT: s_mov_b32 s43, s7
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_readfirstlane_b32 s33, v1
-; SI-NEXT: s_and_b32 s20, s33, 2
; SI-NEXT: v_readfirstlane_b32 s6, v0
-; SI-NEXT: s_bfe_i32 s8, s33, 0x10000
-; SI-NEXT: v_cmp_eq_u64_e64 s[20:21], s[20:21], 0
+; SI-NEXT: s_and_b32 s18, s33, 1
+; SI-NEXT: s_bfe_i32 s8, s33, 0x10001
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 1
-; SI-NEXT: s_and_b32 s8, s8, s6
-; SI-NEXT: s_and_b64 s[20:21], s[20:21], exec
-; SI-NEXT: s_cselect_b32 s21, 0, s5
-; SI-NEXT: s_cselect_b32 s20, 0, s4
-; SI-NEXT: s_and_b32 s14, s33, 4
-; SI-NEXT: s_xor_b64 s[20:21], s[8:9], s[20:21]
-; SI-NEXT: v_cmp_eq_u64_e64 s[8:9], s[14:15], 0
-; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 2
+; SI-NEXT: v_cmp_eq_u64_e64 s[18:19], s[18:19], 0
+; SI-NEXT: s_and_b32 s43, s8, s5
+; SI-NEXT: s_and_b32 s42, s8, s4
+; SI-NEXT: s_and_b64 s[18:19], s[18:19], exec
+; SI-NEXT: s_cselect_b32 s19, 0, 0
+; SI-NEXT: s_cselect_b32 s18, 0, s6
+; SI-NEXT: s_and_b32 s12, s33, 4
+; SI-NEXT: v_cmp_eq_u64_e64 s[12:13], s[12:13], 0
+; SI-NEXT: s_xor_b64 s[18:19], s[18:19], s[42:43]
+; SI-NEXT: s_lshl_b64 s[42:43], s[6:7], 2
+; SI-NEXT: s_and_b64 s[12:13], s[12:13], exec
+; SI-NEXT: s_cselect_b32 s43, 0, s43
+; SI-NEXT: s_cselect_b32 s42, 0, s42
+; SI-NEXT: s_and_b32 s8, s33, 8
+; SI-NEXT: v_cmp_eq_u64_e64 s[8:9], s[8:9], 0
+; SI-NEXT: s_xor_b64 s[18:19], s[18:19], s[42:43]
+; SI-NEXT: s_lshl_b64 s[42:43], s[6:7], 3
; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
-; SI-NEXT: s_cselect_b32 s15, 0, s15
-; SI-NEXT: s_cselect_b32 s14, 0, s14
-; SI-NEXT: s_and_b32 s10, s33, 8
+; SI-NEXT: s_cselect_b32 s9, 0, s43
+; SI-NEXT: s_cselect_b32 s8, 0, s42
+; SI-NEXT: s_and_b32 s10, s33, 16
; SI-NEXT: v_cmp_eq_u64_e64 s[10:11], s[10:11], 0
-; SI-NEXT: s_xor_b64 s[14:15], s[20:21], s[14:15]
-; SI-NEXT: s_lshl_b64 s[20:21], s[6:7], 3
+; SI-NEXT: s_lshl_b64 s[42:43], s[6:7], 4
+; SI-NEXT: s_xor_b64 s[8:9], s[18:19], s[8:9]
; SI-NEXT: s_and_b64 s[10:11], s[10:11], exec
-; SI-NEXT: s_cselect_b32 s11, 0, s21
-; SI-NEXT: s_cselect_b32 s10, 0, s20
-; SI-NEXT: s_and_b32 s12, s33, 16
-; SI-NEXT: v_cmp_eq_u64_e64 s[12:13], s[12:13], 0
-; SI-NEXT: s_lshl_b64 s[20:21], s[6:7], 4
-; SI-NEXT: s_xor_b64 s[10:11], s[14:15], s[10:11]
-; SI-NEXT: s_and_b64 s[12:13], s[12:13], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s21
-; SI-NEXT: s_cselect_b32 s12, 0, s20
-; SI-NEXT: s_and_b32 s16, s33, 32
+; SI-NEXT: s_cselect_b32 s11, 0, s43
+; SI-NEXT: s_cselect_b32 s10, 0, s42
+; SI-NEXT: s_and_b32 s14, s33, 32
+; SI-NEXT: v_cmp_eq_u64_e64 s[14:15], s[14:15], 0
+; SI-NEXT: s_lshl_b64 s[18:19], s[6:7], 5
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[14:15], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s19
+; SI-NEXT: s_cselect_b32 s10, 0, s18
+; SI-NEXT: s_and_b32 s16, s33, 64
; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[16:17], 0
-; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 5
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s18, s33, 64
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[18:19], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 6
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s22, s33, 0x80
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[22:23], 0
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
+; SI-NEXT: s_and_b32 s20, s33, 0x80
+; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[20:21], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 7
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s24, s33, 0x100
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[24:25], 0
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
+; SI-NEXT: s_and_b32 s22, s33, 0x100
+; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[22:23], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 8
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s26, s33, 0x200
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[26:27], 0
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
+; SI-NEXT: s_and_b32 s24, s33, 0x200
+; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[24:25], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 9
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s28, s33, 0x400
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[28:29], 0
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
+; SI-NEXT: s_and_b32 s26, s33, 0x400
+; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[26:27], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 10
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s30, s33, 0x800
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[30:31], 0
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
+; SI-NEXT: s_and_b32 s28, s33, 0x800
+; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[28:29], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 11
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s34, s33, 0x1000
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[34:35], 0
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
+; SI-NEXT: s_and_b32 s30, s33, 0x1000
+; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[30:31], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 12
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s36, s33, 0x2000
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[36:37], 0
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
+; SI-NEXT: s_and_b32 s34, s33, 0x2000
+; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[34:35], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 13
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s38, s33, 0x4000
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[38:39], 0
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
+; SI-NEXT: s_and_b32 s36, s33, 0x4000
+; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[36:37], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 14
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s40, s33, 0x8000
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[40:41], 0
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
+; SI-NEXT: s_and_b32 s38, s33, 0x8000
+; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[38:39], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 15
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s42, s33, 0x10000
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[42:43], 0
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
+; SI-NEXT: s_and_b32 s40, s33, 0x10000
+; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[40:41], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 16
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
; SI-NEXT: s_mov_b32 s5, s7
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
; SI-NEXT: s_and_b32 s4, s33, 0x20000
; SI-NEXT: v_cmp_eq_u64_e64 s[4:5], s[4:5], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 17
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
-; SI-NEXT: s_mov_b32 s9, s7
+; SI-NEXT: s_mov_b32 s13, s7
; SI-NEXT: s_cselect_b32 s5, 0, s15
; SI-NEXT: s_cselect_b32 s4, 0, s14
-; SI-NEXT: s_and_b32 s8, s33, 0x40000
-; SI-NEXT: v_cmp_eq_u64_e64 s[8:9], s[8:9], 0
-; SI-NEXT: s_lshl_b64 s[12:13], s[6:7], 18
-; SI-NEXT: s_xor_b64 s[4:5], s[10:11], s[4:5]
-; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
-; SI-NEXT: s_cselect_b32 s9, 0, s13
-; SI-NEXT: s_cselect_b32 s8, 0, s12
+; SI-NEXT: s_and_b32 s12, s33, 0x40000
+; SI-NEXT: v_cmp_eq_u64_e64 s[12:13], s[12:13], 0
+; SI-NEXT: s_lshl_b64 s[10:11], s[6:7], 18
+; SI-NEXT: s_xor_b64 s[4:5], s[8:9], s[4:5]
+; SI-NEXT: s_and_b64 s[8:9], s[12:13], exec
+; SI-NEXT: s_cselect_b32 s9, 0, s11
+; SI-NEXT: s_cselect_b32 s8, 0, s10
; SI-NEXT: s_and_b32 s10, s33, 0x80000
; SI-NEXT: s_mov_b32 s11, s7
; SI-NEXT: s_xor_b64 s[4:5], s[4:5], s[8:9]
@@ -1247,11 +1247,11 @@ define amdgpu_kernel void @test_clmulr_i32(ptr addrspace(1) %out, ptr addrspace(
; VI-NEXT: s_mov_b32 s8, s6
; VI-NEXT: s_mov_b32 s9, s7
; VI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
-; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s7, 0
+; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5
-; VI-NEXT: s_mov_b32 s11, s7
; VI-NEXT: s_mov_b32 s9, s7
+; VI-NEXT: s_mov_b32 s11, s7
; VI-NEXT: s_mov_b32 s13, s7
; VI-NEXT: s_mov_b32 s15, s7
; VI-NEXT: s_mov_b32 s17, s7
@@ -1268,117 +1268,117 @@ define amdgpu_kernel void @test_clmulr_i32(ptr addrspace(1) %out, ptr addrspace(
; VI-NEXT: s_mov_b32 s41, s7
; VI-NEXT: s_mov_b32 s43, s7
; VI-NEXT: s_mov_b32 s45, s7
-; VI-NEXT: s_mov_b32 s47, s7
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_readfirstlane_b32 s4, v1
; VI-NEXT: v_readfirstlane_b32 s6, v0
-; VI-NEXT: s_bfe_i32 s5, s4, 0x10000
-; VI-NEXT: s_lshl_b64 s[48:49], s[6:7], 1
-; VI-NEXT: s_and_b32 s10, s4, 2
-; VI-NEXT: s_and_b32 s8, s5, s6
+; VI-NEXT: v_readfirstlane_b32 s4, v1
+; VI-NEXT: s_bfe_i32 s5, s4, 0x10001
+; VI-NEXT: s_lshl_b64 s[46:47], s[6:7], 1
+; VI-NEXT: s_and_b32 s8, s4, 1
+; VI-NEXT: s_and_b32 s47, s5, s47
+; VI-NEXT: s_and_b32 s46, s5, s46
+; VI-NEXT: s_cmp_eq_u64 s[8:9], 0
+; VI-NEXT: s_cselect_b32 s9, 0, 0
+; VI-NEXT: s_cselect_b32 s8, 0, s6
+; VI-NEXT: s_lshl_b64 s[48:49], s[6:7], 2
+; VI-NEXT: s_and_b32 s10, s4, 4
+; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[46:47]
; VI-NEXT: s_cmp_eq_u64 s[10:11], 0
; VI-NEXT: s_cselect_b32 s11, 0, s49
; VI-NEXT: s_cselect_b32 s10, 0, s48
-; VI-NEXT: s_lshl_b64 s[48:49], s[6:7], 2
-; VI-NEXT: s_and_b32 s12, s4, 4
+; VI-NEXT: s_lshl_b64 s[46:47], s[6:7], 3
+; VI-NEXT: s_and_b32 s12, s4, 8
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
; VI-NEXT: s_cmp_eq_u64 s[12:13], 0
-; VI-NEXT: s_cselect_b32 s11, 0, s49
-; VI-NEXT: s_cselect_b32 s10, 0, s48
-; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 3
-; VI-NEXT: s_and_b32 s14, s4, 8
-; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[14:15], 0
-; VI-NEXT: s_cselect_b32 s11, 0, s13
-; VI-NEXT: s_cselect_b32 s10, 0, s12
+; VI-NEXT: s_cselect_b32 s11, 0, s47
+; VI-NEXT: s_cselect_b32 s10, 0, s46
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 4
-; VI-NEXT: s_and_b32 s16, s4, 16
+; VI-NEXT: s_and_b32 s14, s4, 16
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[16:17], 0
+; VI-NEXT: s_cmp_eq_u64 s[14:15], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 5
-; VI-NEXT: s_and_b32 s18, s4, 32
+; VI-NEXT: s_and_b32 s16, s4, 32
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[18:19], 0
+; VI-NEXT: s_cmp_eq_u64 s[16:17], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 6
-; VI-NEXT: s_and_b32 s20, s4, 64
+; VI-NEXT: s_and_b32 s18, s4, 64
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[20:21], 0
+; VI-NEXT: s_cmp_eq_u64 s[18:19], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 7
-; VI-NEXT: s_and_b32 s22, s4, 0x80
+; VI-NEXT: s_and_b32 s20, s4, 0x80
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[22:23], 0
+; VI-NEXT: s_cmp_eq_u64 s[20:21], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 8
-; VI-NEXT: s_and_b32 s24, s4, 0x100
+; VI-NEXT: s_and_b32 s22, s4, 0x100
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[24:25], 0
+; VI-NEXT: s_cmp_eq_u64 s[22:23], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 9
-; VI-NEXT: s_and_b32 s26, s4, 0x200
+; VI-NEXT: s_and_b32 s24, s4, 0x200
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[26:27], 0
+; VI-NEXT: s_cmp_eq_u64 s[24:25], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 10
-; VI-NEXT: s_and_b32 s28, s4, 0x400
+; VI-NEXT: s_and_b32 s26, s4, 0x400
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[28:29], 0
+; VI-NEXT: s_cmp_eq_u64 s[26:27], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 11
-; VI-NEXT: s_and_b32 s30, s4, 0x800
+; VI-NEXT: s_and_b32 s28, s4, 0x800
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[30:31], 0
+; VI-NEXT: s_cmp_eq_u64 s[28:29], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 12
-; VI-NEXT: s_and_b32 s34, s4, 0x1000
+; VI-NEXT: s_and_b32 s30, s4, 0x1000
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[34:35], 0
+; VI-NEXT: s_cmp_eq_u64 s[30:31], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 13
-; VI-NEXT: s_and_b32 s36, s4, 0x2000
+; VI-NEXT: s_and_b32 s34, s4, 0x2000
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[36:37], 0
+; VI-NEXT: s_cmp_eq_u64 s[34:35], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 14
-; VI-NEXT: s_and_b32 s38, s4, 0x4000
+; VI-NEXT: s_and_b32 s36, s4, 0x4000
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[38:39], 0
+; VI-NEXT: s_cmp_eq_u64 s[36:37], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 15
-; VI-NEXT: s_and_b32 s40, s4, 0x8000
+; VI-NEXT: s_and_b32 s38, s4, 0x8000
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[40:41], 0
+; VI-NEXT: s_cmp_eq_u64 s[38:39], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 16
-; VI-NEXT: s_and_b32 s42, s4, 0x10000
+; VI-NEXT: s_and_b32 s40, s4, 0x10000
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[42:43], 0
+; VI-NEXT: s_cmp_eq_u64 s[40:41], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 17
-; VI-NEXT: s_and_b32 s44, s4, 0x20000
+; VI-NEXT: s_and_b32 s42, s4, 0x20000
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[44:45], 0
+; VI-NEXT: s_cmp_eq_u64 s[42:43], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 18
-; VI-NEXT: s_and_b32 s46, s4, 0x40000
+; VI-NEXT: s_and_b32 s44, s4, 0x40000
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[46:47], 0
+; VI-NEXT: s_cmp_eq_u64 s[44:45], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 19
@@ -1477,10 +1477,11 @@ define amdgpu_kernel void @test_clmulr_i32(ptr addrspace(1) %out, ptr addrspace(
; GFX9-NEXT: s_mov_b32 s4, s10
; GFX9-NEXT: s_mov_b32 s5, s11
; GFX9-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0
-; GFX9-NEXT: s_mov_b32 s0, s8
; GFX9-NEXT: s_mov_b32 s5, 0
-; GFX9-NEXT: s_mov_b32 s11, s5
+; GFX9-NEXT: s_mov_b32 s0, s8
+; GFX9-NEXT: s_mov_b32 s1, s9
; GFX9-NEXT: s_mov_b32 s7, s5
+; GFX9-NEXT: s_mov_b32 s11, s5
; GFX9-NEXT: s_mov_b32 s13, s5
; GFX9-NEXT: s_mov_b32 s15, s5
; GFX9-NEXT: s_mov_b32 s17, s5
@@ -1497,118 +1498,117 @@ define amdgpu_kernel void @test_clmulr_i32(ptr addrspace(1) %out, ptr addrspace(
; GFX9-NEXT: s_mov_b32 s41, s5
; GFX9-NEXT: s_mov_b32 s43, s5
; GFX9-NEXT: s_mov_b32 s45, s5
-; GFX9-NEXT: s_mov_b32 s47, s5
-; GFX9-NEXT: s_mov_b32 s1, s9
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_readfirstlane_b32 s8, v1
; GFX9-NEXT: v_readfirstlane_b32 s4, v0
-; GFX9-NEXT: s_bfe_i32 s6, s8, 0x10000
-; GFX9-NEXT: s_lshl_b64 s[48:49], s[4:5], 1
-; GFX9-NEXT: s_and_b32 s10, s8, 2
-; GFX9-NEXT: s_and_b32 s6, s6, s4
+; GFX9-NEXT: v_readfirstlane_b32 s8, v1
+; GFX9-NEXT: s_bfe_i32 s9, s8, 0x10001
+; GFX9-NEXT: s_lshl_b64 s[46:47], s[4:5], 1
+; GFX9-NEXT: s_and_b32 s6, s8, 1
+; GFX9-NEXT: s_and_b32 s47, s9, s47
+; GFX9-NEXT: s_and_b32 s46, s9, s46
+; GFX9-NEXT: s_cmp_eq_u64 s[6:7], 0
+; GFX9-NEXT: s_cselect_b32 s7, 0, 0
+; GFX9-NEXT: s_cselect_b32 s6, 0, s4
+; GFX9-NEXT: s_lshl_b64 s[48:49], s[4:5], 2
+; GFX9-NEXT: s_and_b32 s10, s8, 4
+; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[46:47]
; GFX9-NEXT: s_cmp_eq_u64 s[10:11], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s49
; GFX9-NEXT: s_cselect_b32 s10, 0, s48
-; GFX9-NEXT: s_lshl_b64 s[48:49], s[4:5], 2
-; GFX9-NEXT: s_and_b32 s12, s8, 4
+; GFX9-NEXT: s_lshl_b64 s[46:47], s[4:5], 3
+; GFX9-NEXT: s_and_b32 s12, s8, 8
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
; GFX9-NEXT: s_cmp_eq_u64 s[12:13], 0
-; GFX9-NEXT: s_cselect_b32 s11, 0, s49
-; GFX9-NEXT: s_cselect_b32 s10, 0, s48
-; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 3
-; GFX9-NEXT: s_and_b32 s14, s8, 8
-; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[14:15], 0
-; GFX9-NEXT: s_cselect_b32 s11, 0, s13
-; GFX9-NEXT: s_cselect_b32 s10, 0, s12
+; GFX9-NEXT: s_cselect_b32 s11, 0, s47
+; GFX9-NEXT: s_cselect_b32 s10, 0, s46
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 4
-; GFX9-NEXT: s_and_b32 s16, s8, 16
+; GFX9-NEXT: s_and_b32 s14, s8, 16
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[14:15], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 5
-; GFX9-NEXT: s_and_b32 s18, s8, 32
+; GFX9-NEXT: s_and_b32 s16, s8, 32
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[18:19], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 6
-; GFX9-NEXT: s_and_b32 s20, s8, 64
+; GFX9-NEXT: s_and_b32 s18, s8, 64
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[20:21], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[18:19], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 7
-; GFX9-NEXT: s_and_b32 s22, s8, 0x80
+; GFX9-NEXT: s_and_b32 s20, s8, 0x80
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[22:23], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[20:21], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 8
-; GFX9-NEXT: s_and_b32 s24, s8, 0x100
+; GFX9-NEXT: s_and_b32 s22, s8, 0x100
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[24:25], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[22:23], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 9
-; GFX9-NEXT: s_and_b32 s26, s8, 0x200
+; GFX9-NEXT: s_and_b32 s24, s8, 0x200
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[26:27], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[24:25], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 10
-; GFX9-NEXT: s_and_b32 s28, s8, 0x400
+; GFX9-NEXT: s_and_b32 s26, s8, 0x400
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[28:29], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[26:27], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 11
-; GFX9-NEXT: s_and_b32 s30, s8, 0x800
+; GFX9-NEXT: s_and_b32 s28, s8, 0x800
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[30:31], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[28:29], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 12
-; GFX9-NEXT: s_and_b32 s34, s8, 0x1000
+; GFX9-NEXT: s_and_b32 s30, s8, 0x1000
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[34:35], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[30:31], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 13
-; GFX9-NEXT: s_and_b32 s36, s8, 0x2000
+; GFX9-NEXT: s_and_b32 s34, s8, 0x2000
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[36:37], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[34:35], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 14
-; GFX9-NEXT: s_and_b32 s38, s8, 0x4000
+; GFX9-NEXT: s_and_b32 s36, s8, 0x4000
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[38:39], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[36:37], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 15
-; GFX9-NEXT: s_and_b32 s40, s8, 0x8000
+; GFX9-NEXT: s_and_b32 s38, s8, 0x8000
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[40:41], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[38:39], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 16
-; GFX9-NEXT: s_and_b32 s42, s8, 0x10000
+; GFX9-NEXT: s_and_b32 s40, s8, 0x10000
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[42:43], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[40:41], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 17
-; GFX9-NEXT: s_and_b32 s44, s8, 0x20000
+; GFX9-NEXT: s_and_b32 s42, s8, 0x20000
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[44:45], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[42:43], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 18
-; GFX9-NEXT: s_and_b32 s46, s8, 0x40000
+; GFX9-NEXT: s_and_b32 s44, s8, 0x40000
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[46:47], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[44:45], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 19
@@ -1709,195 +1709,195 @@ define amdgpu_kernel void @test_clmulr_i32(ptr addrspace(1) %out, ptr addrspace(
; GFX10-NEXT: s_mov_b32 s3, 0
; GFX10-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
-; GFX10-NEXT: s_mov_b32 s11, s3
; GFX10-NEXT: s_mov_b32 s9, s3
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_readfirstlane_b32 s4, v1
; GFX10-NEXT: v_readfirstlane_b32 s2, v0
-; GFX10-NEXT: s_bfe_i32 s5, s4, 0x10000
-; GFX10-NEXT: s_and_b32 s10, s4, 2
-; GFX10-NEXT: s_lshl_b64 s[12:13], s[2:3], 1
-; GFX10-NEXT: s_and_b32 s8, s5, s2
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_bfe_i32 s5, s4, 0x10001
+; GFX10-NEXT: s_lshl_b64 s[10:11], s[2:3], 1
+; GFX10-NEXT: s_and_b32 s8, s4, 1
+; GFX10-NEXT: s_and_b32 s11, s5, s11
+; GFX10-NEXT: s_and_b32 s10, s5, s10
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_mov_b32 s5, s1
-; GFX10-NEXT: s_cselect_b32 s13, 0, s13
-; GFX10-NEXT: s_cselect_b32 s12, 0, s12
-; GFX10-NEXT: s_and_b32 s10, s4, 4
+; GFX10-NEXT: s_cselect_b32 s13, 0, 0
+; GFX10-NEXT: s_cselect_b32 s12, 0, s2
+; GFX10-NEXT: s_and_b32 s8, s4, 4
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 2
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[12:13], s[10:11]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 8
+; GFX10-NEXT: s_and_b32 s8, s4, 8
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 3
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 16
+; GFX10-NEXT: s_and_b32 s8, s4, 16
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 4
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 32
+; GFX10-NEXT: s_and_b32 s8, s4, 32
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 5
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 64
+; GFX10-NEXT: s_and_b32 s8, s4, 64
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 6
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x80
+; GFX10-NEXT: s_and_b32 s8, s4, 0x80
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 7
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x100
+; GFX10-NEXT: s_and_b32 s8, s4, 0x100
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 8
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x200
+; GFX10-NEXT: s_and_b32 s8, s4, 0x200
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 9
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x400
+; GFX10-NEXT: s_and_b32 s8, s4, 0x400
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 10
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x800
+; GFX10-NEXT: s_and_b32 s8, s4, 0x800
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 11
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x1000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x1000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 12
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x2000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x2000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 13
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x4000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x4000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 14
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x8000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x8000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 15
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x10000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x10000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 16
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x20000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x20000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 17
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x40000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x40000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 18
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x80000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x80000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 19
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x100000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x100000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 20
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x200000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x200000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 21
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x400000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x400000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 22
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x800000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x800000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 23
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x1000000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x1000000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 24
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x2000000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x2000000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 25
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x4000000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x4000000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 26
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x8000000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x8000000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 27
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x10000000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x10000000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 28
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x20000000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x20000000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 29
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 2.0
+; GFX10-NEXT: s_and_b32 s8, s4, 2.0
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 30
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
-; GFX10-NEXT: s_cselect_b32 s11, 0, s15
-; GFX10-NEXT: s_cselect_b32 s10, 0, s14
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
+; GFX10-NEXT: s_cselect_b32 s9, 0, s15
+; GFX10-NEXT: s_cselect_b32 s8, 0, s14
; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 31
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; GFX10-NEXT: s_xor_b64 s[8:9], s[10:11], s[8:9]
; GFX10-NEXT: s_cmp_gt_i32 s4, -1
; GFX10-NEXT: s_mov_b32 s4, s0
; GFX10-NEXT: s_cselect_b32 s3, 0, s3
@@ -1920,195 +1920,195 @@ define amdgpu_kernel void @test_clmulr_i32(ptr addrspace(1) %out, ptr addrspace(
; GFX11-NEXT: s_mov_b32 s9, s3
; GFX11-NEXT: s_mov_b32 s3, 0
; GFX11-NEXT: buffer_load_b64 v[0:1], off, s[8:11], 0
-; GFX11-NEXT: s_mov_b32 s11, s3
; GFX11-NEXT: s_mov_b32 s9, s3
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s4, v1
; GFX11-NEXT: v_readfirstlane_b32 s2, v0
-; GFX11-NEXT: s_bfe_i32 s5, s4, 0x10000
-; GFX11-NEXT: s_and_b32 s10, s4, 2
-; GFX11-NEXT: s_lshl_b64 s[12:13], s[2:3], 1
-; GFX11-NEXT: s_and_b32 s8, s5, s2
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_bfe_i32 s5, s4, 0x10001
+; GFX11-NEXT: s_lshl_b64 s[10:11], s[2:3], 1
+; GFX11-NEXT: s_and_b32 s8, s4, 1
+; GFX11-NEXT: s_and_b32 s11, s5, s11
+; GFX11-NEXT: s_and_b32 s10, s5, s10
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_mov_b32 s5, s1
-; GFX11-NEXT: s_cselect_b32 s13, 0, s13
-; GFX11-NEXT: s_cselect_b32 s12, 0, s12
-; GFX11-NEXT: s_and_b32 s10, s4, 4
+; GFX11-NEXT: s_cselect_b32 s13, 0, 0
+; GFX11-NEXT: s_cselect_b32 s12, 0, s2
+; GFX11-NEXT: s_and_b32 s8, s4, 4
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 2
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[12:13], s[10:11]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 8
+; GFX11-NEXT: s_and_b32 s8, s4, 8
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 3
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 16
+; GFX11-NEXT: s_and_b32 s8, s4, 16
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 4
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 32
+; GFX11-NEXT: s_and_b32 s8, s4, 32
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 5
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 64
+; GFX11-NEXT: s_and_b32 s8, s4, 64
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 6
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x80
+; GFX11-NEXT: s_and_b32 s8, s4, 0x80
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 7
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x100
+; GFX11-NEXT: s_and_b32 s8, s4, 0x100
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 8
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x200
+; GFX11-NEXT: s_and_b32 s8, s4, 0x200
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 9
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x400
+; GFX11-NEXT: s_and_b32 s8, s4, 0x400
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 10
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x800
+; GFX11-NEXT: s_and_b32 s8, s4, 0x800
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 11
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x1000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x1000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 12
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x2000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x2000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 13
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x4000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x4000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 14
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x8000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x8000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 15
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x10000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x10000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 16
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x20000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x20000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 17
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x40000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x40000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 18
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x80000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x80000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 19
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x100000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x100000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 20
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x200000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x200000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 21
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x400000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x400000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 22
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x800000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x800000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 23
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x1000000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x1000000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 24
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x2000000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x2000000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 25
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x4000000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x4000000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 26
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x8000000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x8000000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 27
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x10000000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x10000000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 28
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x20000000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x20000000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 29
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 2.0
+; GFX11-NEXT: s_and_b32 s8, s4, 2.0
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 30
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
-; GFX11-NEXT: s_cselect_b32 s11, 0, s15
-; GFX11-NEXT: s_cselect_b32 s10, 0, s14
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
+; GFX11-NEXT: s_cselect_b32 s9, 0, s15
+; GFX11-NEXT: s_cselect_b32 s8, 0, s14
; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 31
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; GFX11-NEXT: s_xor_b64 s[8:9], s[10:11], s[8:9]
; GFX11-NEXT: s_cmp_gt_i32 s4, -1
; GFX11-NEXT: s_mov_b32 s4, s0
; GFX11-NEXT: s_cselect_b32 s3, 0, s3
@@ -2706,15 +2706,15 @@ define amdgpu_kernel void @test_clmulh_i32(ptr addrspace(1) %out, ptr addrspace(
; SI-NEXT: s_mov_b32 s9, s7
; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
; SI-NEXT: s_mov_b32 s7, 0
-; SI-NEXT: s_mov_b32 s21, s7
+; SI-NEXT: s_mov_b32 s19, s7
; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5
+; SI-NEXT: s_mov_b32 s13, s7
; SI-NEXT: s_mov_b32 s9, s7
-; SI-NEXT: s_mov_b32 s15, s7
; SI-NEXT: s_mov_b32 s11, s7
-; SI-NEXT: s_mov_b32 s13, s7
+; SI-NEXT: s_mov_b32 s15, s7
; SI-NEXT: s_mov_b32 s17, s7
-; SI-NEXT: s_mov_b32 s19, s7
+; SI-NEXT: s_mov_b32 s21, s7
; SI-NEXT: s_mov_b32 s23, s7
; SI-NEXT: s_mov_b32 s25, s7
; SI-NEXT: s_mov_b32 s27, s7
@@ -2724,139 +2724,139 @@ define amdgpu_kernel void @test_clmulh_i32(ptr addrspace(1) %out, ptr addrspace(
; SI-NEXT: s_mov_b32 s37, s7
; SI-NEXT: s_mov_b32 s39, s7
; SI-NEXT: s_mov_b32 s41, s7
-; SI-NEXT: s_mov_b32 s43, s7
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_readfirstlane_b32 s33, v1
-; SI-NEXT: s_and_b32 s20, s33, 2
; SI-NEXT: v_readfirstlane_b32 s6, v0
-; SI-NEXT: s_bfe_i32 s8, s33, 0x10000
-; SI-NEXT: v_cmp_eq_u64_e64 s[20:21], s[20:21], 0
+; SI-NEXT: s_and_b32 s18, s33, 1
+; SI-NEXT: s_bfe_i32 s8, s33, 0x10001
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 1
-; SI-NEXT: s_and_b32 s8, s8, s6
-; SI-NEXT: s_and_b64 s[20:21], s[20:21], exec
-; SI-NEXT: s_cselect_b32 s21, 0, s5
-; SI-NEXT: s_cselect_b32 s20, 0, s4
-; SI-NEXT: s_and_b32 s14, s33, 4
-; SI-NEXT: s_xor_b64 s[20:21], s[8:9], s[20:21]
-; SI-NEXT: v_cmp_eq_u64_e64 s[8:9], s[14:15], 0
-; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 2
+; SI-NEXT: v_cmp_eq_u64_e64 s[18:19], s[18:19], 0
+; SI-NEXT: s_and_b32 s43, s8, s5
+; SI-NEXT: s_and_b32 s42, s8, s4
+; SI-NEXT: s_and_b64 s[18:19], s[18:19], exec
+; SI-NEXT: s_cselect_b32 s19, 0, 0
+; SI-NEXT: s_cselect_b32 s18, 0, s6
+; SI-NEXT: s_and_b32 s12, s33, 4
+; SI-NEXT: v_cmp_eq_u64_e64 s[12:13], s[12:13], 0
+; SI-NEXT: s_xor_b64 s[18:19], s[18:19], s[42:43]
+; SI-NEXT: s_lshl_b64 s[42:43], s[6:7], 2
+; SI-NEXT: s_and_b64 s[12:13], s[12:13], exec
+; SI-NEXT: s_cselect_b32 s43, 0, s43
+; SI-NEXT: s_cselect_b32 s42, 0, s42
+; SI-NEXT: s_and_b32 s8, s33, 8
+; SI-NEXT: v_cmp_eq_u64_e64 s[8:9], s[8:9], 0
+; SI-NEXT: s_xor_b64 s[18:19], s[18:19], s[42:43]
+; SI-NEXT: s_lshl_b64 s[42:43], s[6:7], 3
; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
-; SI-NEXT: s_cselect_b32 s15, 0, s15
-; SI-NEXT: s_cselect_b32 s14, 0, s14
-; SI-NEXT: s_and_b32 s10, s33, 8
+; SI-NEXT: s_cselect_b32 s9, 0, s43
+; SI-NEXT: s_cselect_b32 s8, 0, s42
+; SI-NEXT: s_and_b32 s10, s33, 16
; SI-NEXT: v_cmp_eq_u64_e64 s[10:11], s[10:11], 0
-; SI-NEXT: s_xor_b64 s[14:15], s[20:21], s[14:15]
-; SI-NEXT: s_lshl_b64 s[20:21], s[6:7], 3
+; SI-NEXT: s_lshl_b64 s[42:43], s[6:7], 4
+; SI-NEXT: s_xor_b64 s[8:9], s[18:19], s[8:9]
; SI-NEXT: s_and_b64 s[10:11], s[10:11], exec
-; SI-NEXT: s_cselect_b32 s11, 0, s21
-; SI-NEXT: s_cselect_b32 s10, 0, s20
-; SI-NEXT: s_and_b32 s12, s33, 16
-; SI-NEXT: v_cmp_eq_u64_e64 s[12:13], s[12:13], 0
-; SI-NEXT: s_lshl_b64 s[20:21], s[6:7], 4
-; SI-NEXT: s_xor_b64 s[10:11], s[14:15], s[10:11]
-; SI-NEXT: s_and_b64 s[12:13], s[12:13], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s21
-; SI-NEXT: s_cselect_b32 s12, 0, s20
-; SI-NEXT: s_and_b32 s16, s33, 32
+; SI-NEXT: s_cselect_b32 s11, 0, s43
+; SI-NEXT: s_cselect_b32 s10, 0, s42
+; SI-NEXT: s_and_b32 s14, s33, 32
+; SI-NEXT: v_cmp_eq_u64_e64 s[14:15], s[14:15], 0
+; SI-NEXT: s_lshl_b64 s[18:19], s[6:7], 5
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[14:15], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s19
+; SI-NEXT: s_cselect_b32 s10, 0, s18
+; SI-NEXT: s_and_b32 s16, s33, 64
; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[16:17], 0
-; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 5
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s18, s33, 64
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[18:19], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 6
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s22, s33, 0x80
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[22:23], 0
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
+; SI-NEXT: s_and_b32 s20, s33, 0x80
+; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[20:21], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 7
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s24, s33, 0x100
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[24:25], 0
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
+; SI-NEXT: s_and_b32 s22, s33, 0x100
+; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[22:23], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 8
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s26, s33, 0x200
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[26:27], 0
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
+; SI-NEXT: s_and_b32 s24, s33, 0x200
+; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[24:25], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 9
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s28, s33, 0x400
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[28:29], 0
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
+; SI-NEXT: s_and_b32 s26, s33, 0x400
+; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[26:27], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 10
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s30, s33, 0x800
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[30:31], 0
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
+; SI-NEXT: s_and_b32 s28, s33, 0x800
+; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[28:29], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 11
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s34, s33, 0x1000
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[34:35], 0
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
+; SI-NEXT: s_and_b32 s30, s33, 0x1000
+; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[30:31], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 12
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s36, s33, 0x2000
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[36:37], 0
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
+; SI-NEXT: s_and_b32 s34, s33, 0x2000
+; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[34:35], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 13
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s38, s33, 0x4000
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[38:39], 0
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
+; SI-NEXT: s_and_b32 s36, s33, 0x4000
+; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[36:37], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 14
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s40, s33, 0x8000
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[40:41], 0
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
+; SI-NEXT: s_and_b32 s38, s33, 0x8000
+; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[38:39], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 15
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
-; SI-NEXT: s_and_b32 s42, s33, 0x10000
-; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[42:43], 0
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
+; SI-NEXT: s_and_b32 s40, s33, 0x10000
+; SI-NEXT: v_cmp_eq_u64_e64 s[16:17], s[40:41], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 16
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; SI-NEXT: s_and_b64 s[12:13], s[16:17], exec
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; SI-NEXT: s_and_b64 s[10:11], s[16:17], exec
; SI-NEXT: s_mov_b32 s5, s7
-; SI-NEXT: s_cselect_b32 s13, 0, s15
-; SI-NEXT: s_cselect_b32 s12, 0, s14
+; SI-NEXT: s_cselect_b32 s11, 0, s15
+; SI-NEXT: s_cselect_b32 s10, 0, s14
; SI-NEXT: s_and_b32 s4, s33, 0x20000
; SI-NEXT: v_cmp_eq_u64_e64 s[4:5], s[4:5], 0
; SI-NEXT: s_lshl_b64 s[14:15], s[6:7], 17
-; SI-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; SI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
-; SI-NEXT: s_mov_b32 s9, s7
+; SI-NEXT: s_mov_b32 s13, s7
; SI-NEXT: s_cselect_b32 s5, 0, s15
; SI-NEXT: s_cselect_b32 s4, 0, s14
-; SI-NEXT: s_and_b32 s8, s33, 0x40000
-; SI-NEXT: v_cmp_eq_u64_e64 s[8:9], s[8:9], 0
-; SI-NEXT: s_lshl_b64 s[12:13], s[6:7], 18
-; SI-NEXT: s_xor_b64 s[4:5], s[10:11], s[4:5]
-; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
-; SI-NEXT: s_cselect_b32 s9, 0, s13
-; SI-NEXT: s_cselect_b32 s8, 0, s12
+; SI-NEXT: s_and_b32 s12, s33, 0x40000
+; SI-NEXT: v_cmp_eq_u64_e64 s[12:13], s[12:13], 0
+; SI-NEXT: s_lshl_b64 s[10:11], s[6:7], 18
+; SI-NEXT: s_xor_b64 s[4:5], s[8:9], s[4:5]
+; SI-NEXT: s_and_b64 s[8:9], s[12:13], exec
+; SI-NEXT: s_cselect_b32 s9, 0, s11
+; SI-NEXT: s_cselect_b32 s8, 0, s10
; SI-NEXT: s_and_b32 s10, s33, 0x80000
; SI-NEXT: s_mov_b32 s11, s7
; SI-NEXT: s_xor_b64 s[4:5], s[4:5], s[8:9]
@@ -2974,11 +2974,11 @@ define amdgpu_kernel void @test_clmulh_i32(ptr addrspace(1) %out, ptr addrspace(
; VI-NEXT: s_mov_b32 s8, s6
; VI-NEXT: s_mov_b32 s9, s7
; VI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
-; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s7, 0
+; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5
-; VI-NEXT: s_mov_b32 s11, s7
; VI-NEXT: s_mov_b32 s9, s7
+; VI-NEXT: s_mov_b32 s11, s7
; VI-NEXT: s_mov_b32 s13, s7
; VI-NEXT: s_mov_b32 s15, s7
; VI-NEXT: s_mov_b32 s17, s7
@@ -2995,117 +2995,117 @@ define amdgpu_kernel void @test_clmulh_i32(ptr addrspace(1) %out, ptr addrspace(
; VI-NEXT: s_mov_b32 s41, s7
; VI-NEXT: s_mov_b32 s43, s7
; VI-NEXT: s_mov_b32 s45, s7
-; VI-NEXT: s_mov_b32 s47, s7
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_readfirstlane_b32 s4, v1
; VI-NEXT: v_readfirstlane_b32 s6, v0
-; VI-NEXT: s_bfe_i32 s5, s4, 0x10000
-; VI-NEXT: s_lshl_b64 s[48:49], s[6:7], 1
-; VI-NEXT: s_and_b32 s10, s4, 2
-; VI-NEXT: s_and_b32 s8, s5, s6
+; VI-NEXT: v_readfirstlane_b32 s4, v1
+; VI-NEXT: s_bfe_i32 s5, s4, 0x10001
+; VI-NEXT: s_lshl_b64 s[46:47], s[6:7], 1
+; VI-NEXT: s_and_b32 s8, s4, 1
+; VI-NEXT: s_and_b32 s47, s5, s47
+; VI-NEXT: s_and_b32 s46, s5, s46
+; VI-NEXT: s_cmp_eq_u64 s[8:9], 0
+; VI-NEXT: s_cselect_b32 s9, 0, 0
+; VI-NEXT: s_cselect_b32 s8, 0, s6
+; VI-NEXT: s_lshl_b64 s[48:49], s[6:7], 2
+; VI-NEXT: s_and_b32 s10, s4, 4
+; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[46:47]
; VI-NEXT: s_cmp_eq_u64 s[10:11], 0
; VI-NEXT: s_cselect_b32 s11, 0, s49
; VI-NEXT: s_cselect_b32 s10, 0, s48
-; VI-NEXT: s_lshl_b64 s[48:49], s[6:7], 2
-; VI-NEXT: s_and_b32 s12, s4, 4
+; VI-NEXT: s_lshl_b64 s[46:47], s[6:7], 3
+; VI-NEXT: s_and_b32 s12, s4, 8
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
; VI-NEXT: s_cmp_eq_u64 s[12:13], 0
-; VI-NEXT: s_cselect_b32 s11, 0, s49
-; VI-NEXT: s_cselect_b32 s10, 0, s48
-; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 3
-; VI-NEXT: s_and_b32 s14, s4, 8
-; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[14:15], 0
-; VI-NEXT: s_cselect_b32 s11, 0, s13
-; VI-NEXT: s_cselect_b32 s10, 0, s12
+; VI-NEXT: s_cselect_b32 s11, 0, s47
+; VI-NEXT: s_cselect_b32 s10, 0, s46
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 4
-; VI-NEXT: s_and_b32 s16, s4, 16
+; VI-NEXT: s_and_b32 s14, s4, 16
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[16:17], 0
+; VI-NEXT: s_cmp_eq_u64 s[14:15], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 5
-; VI-NEXT: s_and_b32 s18, s4, 32
+; VI-NEXT: s_and_b32 s16, s4, 32
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[18:19], 0
+; VI-NEXT: s_cmp_eq_u64 s[16:17], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 6
-; VI-NEXT: s_and_b32 s20, s4, 64
+; VI-NEXT: s_and_b32 s18, s4, 64
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[20:21], 0
+; VI-NEXT: s_cmp_eq_u64 s[18:19], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 7
-; VI-NEXT: s_and_b32 s22, s4, 0x80
+; VI-NEXT: s_and_b32 s20, s4, 0x80
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[22:23], 0
+; VI-NEXT: s_cmp_eq_u64 s[20:21], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 8
-; VI-NEXT: s_and_b32 s24, s4, 0x100
+; VI-NEXT: s_and_b32 s22, s4, 0x100
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[24:25], 0
+; VI-NEXT: s_cmp_eq_u64 s[22:23], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 9
-; VI-NEXT: s_and_b32 s26, s4, 0x200
+; VI-NEXT: s_and_b32 s24, s4, 0x200
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[26:27], 0
+; VI-NEXT: s_cmp_eq_u64 s[24:25], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 10
-; VI-NEXT: s_and_b32 s28, s4, 0x400
+; VI-NEXT: s_and_b32 s26, s4, 0x400
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[28:29], 0
+; VI-NEXT: s_cmp_eq_u64 s[26:27], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 11
-; VI-NEXT: s_and_b32 s30, s4, 0x800
+; VI-NEXT: s_and_b32 s28, s4, 0x800
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[30:31], 0
+; VI-NEXT: s_cmp_eq_u64 s[28:29], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 12
-; VI-NEXT: s_and_b32 s34, s4, 0x1000
+; VI-NEXT: s_and_b32 s30, s4, 0x1000
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[34:35], 0
+; VI-NEXT: s_cmp_eq_u64 s[30:31], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 13
-; VI-NEXT: s_and_b32 s36, s4, 0x2000
+; VI-NEXT: s_and_b32 s34, s4, 0x2000
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[36:37], 0
+; VI-NEXT: s_cmp_eq_u64 s[34:35], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 14
-; VI-NEXT: s_and_b32 s38, s4, 0x4000
+; VI-NEXT: s_and_b32 s36, s4, 0x4000
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[38:39], 0
+; VI-NEXT: s_cmp_eq_u64 s[36:37], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 15
-; VI-NEXT: s_and_b32 s40, s4, 0x8000
+; VI-NEXT: s_and_b32 s38, s4, 0x8000
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[40:41], 0
+; VI-NEXT: s_cmp_eq_u64 s[38:39], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 16
-; VI-NEXT: s_and_b32 s42, s4, 0x10000
+; VI-NEXT: s_and_b32 s40, s4, 0x10000
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[42:43], 0
+; VI-NEXT: s_cmp_eq_u64 s[40:41], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 17
-; VI-NEXT: s_and_b32 s44, s4, 0x20000
+; VI-NEXT: s_and_b32 s42, s4, 0x20000
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[44:45], 0
+; VI-NEXT: s_cmp_eq_u64 s[42:43], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 18
-; VI-NEXT: s_and_b32 s46, s4, 0x40000
+; VI-NEXT: s_and_b32 s44, s4, 0x40000
; VI-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
-; VI-NEXT: s_cmp_eq_u64 s[46:47], 0
+; VI-NEXT: s_cmp_eq_u64 s[44:45], 0
; VI-NEXT: s_cselect_b32 s11, 0, s13
; VI-NEXT: s_cselect_b32 s10, 0, s12
; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 19
@@ -3203,10 +3203,11 @@ define amdgpu_kernel void @test_clmulh_i32(ptr addrspace(1) %out, ptr addrspace(
; GFX9-NEXT: s_mov_b32 s4, s10
; GFX9-NEXT: s_mov_b32 s5, s11
; GFX9-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0
-; GFX9-NEXT: s_mov_b32 s0, s8
; GFX9-NEXT: s_mov_b32 s5, 0
-; GFX9-NEXT: s_mov_b32 s11, s5
+; GFX9-NEXT: s_mov_b32 s0, s8
+; GFX9-NEXT: s_mov_b32 s1, s9
; GFX9-NEXT: s_mov_b32 s7, s5
+; GFX9-NEXT: s_mov_b32 s11, s5
; GFX9-NEXT: s_mov_b32 s13, s5
; GFX9-NEXT: s_mov_b32 s15, s5
; GFX9-NEXT: s_mov_b32 s17, s5
@@ -3223,118 +3224,117 @@ define amdgpu_kernel void @test_clmulh_i32(ptr addrspace(1) %out, ptr addrspace(
; GFX9-NEXT: s_mov_b32 s41, s5
; GFX9-NEXT: s_mov_b32 s43, s5
; GFX9-NEXT: s_mov_b32 s45, s5
-; GFX9-NEXT: s_mov_b32 s47, s5
-; GFX9-NEXT: s_mov_b32 s1, s9
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_readfirstlane_b32 s8, v1
; GFX9-NEXT: v_readfirstlane_b32 s4, v0
-; GFX9-NEXT: s_bfe_i32 s6, s8, 0x10000
-; GFX9-NEXT: s_lshl_b64 s[48:49], s[4:5], 1
-; GFX9-NEXT: s_and_b32 s10, s8, 2
-; GFX9-NEXT: s_and_b32 s6, s6, s4
+; GFX9-NEXT: v_readfirstlane_b32 s8, v1
+; GFX9-NEXT: s_bfe_i32 s9, s8, 0x10001
+; GFX9-NEXT: s_lshl_b64 s[46:47], s[4:5], 1
+; GFX9-NEXT: s_and_b32 s6, s8, 1
+; GFX9-NEXT: s_and_b32 s47, s9, s47
+; GFX9-NEXT: s_and_b32 s46, s9, s46
+; GFX9-NEXT: s_cmp_eq_u64 s[6:7], 0
+; GFX9-NEXT: s_cselect_b32 s7, 0, 0
+; GFX9-NEXT: s_cselect_b32 s6, 0, s4
+; GFX9-NEXT: s_lshl_b64 s[48:49], s[4:5], 2
+; GFX9-NEXT: s_and_b32 s10, s8, 4
+; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[46:47]
; GFX9-NEXT: s_cmp_eq_u64 s[10:11], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s49
; GFX9-NEXT: s_cselect_b32 s10, 0, s48
-; GFX9-NEXT: s_lshl_b64 s[48:49], s[4:5], 2
-; GFX9-NEXT: s_and_b32 s12, s8, 4
+; GFX9-NEXT: s_lshl_b64 s[46:47], s[4:5], 3
+; GFX9-NEXT: s_and_b32 s12, s8, 8
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
; GFX9-NEXT: s_cmp_eq_u64 s[12:13], 0
-; GFX9-NEXT: s_cselect_b32 s11, 0, s49
-; GFX9-NEXT: s_cselect_b32 s10, 0, s48
-; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 3
-; GFX9-NEXT: s_and_b32 s14, s8, 8
-; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[14:15], 0
-; GFX9-NEXT: s_cselect_b32 s11, 0, s13
-; GFX9-NEXT: s_cselect_b32 s10, 0, s12
+; GFX9-NEXT: s_cselect_b32 s11, 0, s47
+; GFX9-NEXT: s_cselect_b32 s10, 0, s46
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 4
-; GFX9-NEXT: s_and_b32 s16, s8, 16
+; GFX9-NEXT: s_and_b32 s14, s8, 16
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[14:15], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 5
-; GFX9-NEXT: s_and_b32 s18, s8, 32
+; GFX9-NEXT: s_and_b32 s16, s8, 32
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[18:19], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 6
-; GFX9-NEXT: s_and_b32 s20, s8, 64
+; GFX9-NEXT: s_and_b32 s18, s8, 64
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[20:21], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[18:19], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 7
-; GFX9-NEXT: s_and_b32 s22, s8, 0x80
+; GFX9-NEXT: s_and_b32 s20, s8, 0x80
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[22:23], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[20:21], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 8
-; GFX9-NEXT: s_and_b32 s24, s8, 0x100
+; GFX9-NEXT: s_and_b32 s22, s8, 0x100
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[24:25], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[22:23], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 9
-; GFX9-NEXT: s_and_b32 s26, s8, 0x200
+; GFX9-NEXT: s_and_b32 s24, s8, 0x200
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[26:27], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[24:25], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 10
-; GFX9-NEXT: s_and_b32 s28, s8, 0x400
+; GFX9-NEXT: s_and_b32 s26, s8, 0x400
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[28:29], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[26:27], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 11
-; GFX9-NEXT: s_and_b32 s30, s8, 0x800
+; GFX9-NEXT: s_and_b32 s28, s8, 0x800
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[30:31], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[28:29], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 12
-; GFX9-NEXT: s_and_b32 s34, s8, 0x1000
+; GFX9-NEXT: s_and_b32 s30, s8, 0x1000
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[34:35], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[30:31], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 13
-; GFX9-NEXT: s_and_b32 s36, s8, 0x2000
+; GFX9-NEXT: s_and_b32 s34, s8, 0x2000
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[36:37], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[34:35], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 14
-; GFX9-NEXT: s_and_b32 s38, s8, 0x4000
+; GFX9-NEXT: s_and_b32 s36, s8, 0x4000
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[38:39], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[36:37], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 15
-; GFX9-NEXT: s_and_b32 s40, s8, 0x8000
+; GFX9-NEXT: s_and_b32 s38, s8, 0x8000
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[40:41], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[38:39], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 16
-; GFX9-NEXT: s_and_b32 s42, s8, 0x10000
+; GFX9-NEXT: s_and_b32 s40, s8, 0x10000
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[42:43], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[40:41], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 17
-; GFX9-NEXT: s_and_b32 s44, s8, 0x20000
+; GFX9-NEXT: s_and_b32 s42, s8, 0x20000
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[44:45], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[42:43], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 18
-; GFX9-NEXT: s_and_b32 s46, s8, 0x40000
+; GFX9-NEXT: s_and_b32 s44, s8, 0x40000
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
-; GFX9-NEXT: s_cmp_eq_u64 s[46:47], 0
+; GFX9-NEXT: s_cmp_eq_u64 s[44:45], 0
; GFX9-NEXT: s_cselect_b32 s11, 0, s13
; GFX9-NEXT: s_cselect_b32 s10, 0, s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], 19
@@ -3434,195 +3434,195 @@ define amdgpu_kernel void @test_clmulh_i32(ptr addrspace(1) %out, ptr addrspace(
; GFX10-NEXT: s_mov_b32 s3, 0
; GFX10-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
-; GFX10-NEXT: s_mov_b32 s11, s3
; GFX10-NEXT: s_mov_b32 s9, s3
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_readfirstlane_b32 s4, v1
; GFX10-NEXT: v_readfirstlane_b32 s2, v0
-; GFX10-NEXT: s_bfe_i32 s5, s4, 0x10000
-; GFX10-NEXT: s_and_b32 s10, s4, 2
-; GFX10-NEXT: s_lshl_b64 s[12:13], s[2:3], 1
-; GFX10-NEXT: s_and_b32 s8, s5, s2
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_bfe_i32 s5, s4, 0x10001
+; GFX10-NEXT: s_lshl_b64 s[10:11], s[2:3], 1
+; GFX10-NEXT: s_and_b32 s8, s4, 1
+; GFX10-NEXT: s_and_b32 s11, s5, s11
+; GFX10-NEXT: s_and_b32 s10, s5, s10
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_mov_b32 s5, s1
-; GFX10-NEXT: s_cselect_b32 s13, 0, s13
-; GFX10-NEXT: s_cselect_b32 s12, 0, s12
-; GFX10-NEXT: s_and_b32 s10, s4, 4
+; GFX10-NEXT: s_cselect_b32 s13, 0, 0
+; GFX10-NEXT: s_cselect_b32 s12, 0, s2
+; GFX10-NEXT: s_and_b32 s8, s4, 4
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 2
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[12:13], s[10:11]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 8
+; GFX10-NEXT: s_and_b32 s8, s4, 8
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 3
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 16
+; GFX10-NEXT: s_and_b32 s8, s4, 16
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 4
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 32
+; GFX10-NEXT: s_and_b32 s8, s4, 32
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 5
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 64
+; GFX10-NEXT: s_and_b32 s8, s4, 64
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 6
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x80
+; GFX10-NEXT: s_and_b32 s8, s4, 0x80
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 7
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x100
+; GFX10-NEXT: s_and_b32 s8, s4, 0x100
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 8
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x200
+; GFX10-NEXT: s_and_b32 s8, s4, 0x200
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 9
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x400
+; GFX10-NEXT: s_and_b32 s8, s4, 0x400
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 10
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x800
+; GFX10-NEXT: s_and_b32 s8, s4, 0x800
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 11
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x1000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x1000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 12
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x2000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x2000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 13
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x4000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x4000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 14
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x8000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x8000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 15
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x10000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x10000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 16
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x20000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x20000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 17
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x40000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x40000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 18
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x80000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x80000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 19
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x100000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x100000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 20
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x200000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x200000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 21
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x400000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x400000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 22
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x800000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x800000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 23
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x1000000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x1000000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 24
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x2000000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x2000000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 25
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x4000000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x4000000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 26
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x8000000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x8000000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 27
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x10000000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x10000000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 28
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 0x20000000
+; GFX10-NEXT: s_and_b32 s8, s4, 0x20000000
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 29
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX10-NEXT: s_cselect_b32 s13, 0, s15
; GFX10-NEXT: s_cselect_b32 s12, 0, s14
-; GFX10-NEXT: s_and_b32 s10, s4, 2.0
+; GFX10-NEXT: s_and_b32 s8, s4, 2.0
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], 30
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
-; GFX10-NEXT: s_cselect_b32 s11, 0, s15
-; GFX10-NEXT: s_cselect_b32 s10, 0, s14
+; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u64 s[8:9], 0
+; GFX10-NEXT: s_cselect_b32 s9, 0, s15
+; GFX10-NEXT: s_cselect_b32 s8, 0, s14
; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 31
-; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; GFX10-NEXT: s_xor_b64 s[8:9], s[10:11], s[8:9]
; GFX10-NEXT: s_cmp_gt_i32 s4, -1
; GFX10-NEXT: s_mov_b32 s4, s0
; GFX10-NEXT: s_cselect_b32 s3, 0, s3
@@ -3644,195 +3644,195 @@ define amdgpu_kernel void @test_clmulh_i32(ptr addrspace(1) %out, ptr addrspace(
; GFX11-NEXT: s_mov_b32 s9, s3
; GFX11-NEXT: s_mov_b32 s3, 0
; GFX11-NEXT: buffer_load_b64 v[0:1], off, s[8:11], 0
-; GFX11-NEXT: s_mov_b32 s11, s3
; GFX11-NEXT: s_mov_b32 s9, s3
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s4, v1
; GFX11-NEXT: v_readfirstlane_b32 s2, v0
-; GFX11-NEXT: s_bfe_i32 s5, s4, 0x10000
-; GFX11-NEXT: s_and_b32 s10, s4, 2
-; GFX11-NEXT: s_lshl_b64 s[12:13], s[2:3], 1
-; GFX11-NEXT: s_and_b32 s8, s5, s2
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_bfe_i32 s5, s4, 0x10001
+; GFX11-NEXT: s_lshl_b64 s[10:11], s[2:3], 1
+; GFX11-NEXT: s_and_b32 s8, s4, 1
+; GFX11-NEXT: s_and_b32 s11, s5, s11
+; GFX11-NEXT: s_and_b32 s10, s5, s10
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_mov_b32 s5, s1
-; GFX11-NEXT: s_cselect_b32 s13, 0, s13
-; GFX11-NEXT: s_cselect_b32 s12, 0, s12
-; GFX11-NEXT: s_and_b32 s10, s4, 4
+; GFX11-NEXT: s_cselect_b32 s13, 0, 0
+; GFX11-NEXT: s_cselect_b32 s12, 0, s2
+; GFX11-NEXT: s_and_b32 s8, s4, 4
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 2
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[12:13], s[10:11]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 8
+; GFX11-NEXT: s_and_b32 s8, s4, 8
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 3
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 16
+; GFX11-NEXT: s_and_b32 s8, s4, 16
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 4
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 32
+; GFX11-NEXT: s_and_b32 s8, s4, 32
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 5
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 64
+; GFX11-NEXT: s_and_b32 s8, s4, 64
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 6
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x80
+; GFX11-NEXT: s_and_b32 s8, s4, 0x80
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 7
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x100
+; GFX11-NEXT: s_and_b32 s8, s4, 0x100
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 8
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x200
+; GFX11-NEXT: s_and_b32 s8, s4, 0x200
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 9
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x400
+; GFX11-NEXT: s_and_b32 s8, s4, 0x400
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 10
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x800
+; GFX11-NEXT: s_and_b32 s8, s4, 0x800
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 11
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x1000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x1000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 12
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x2000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x2000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 13
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x4000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x4000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 14
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x8000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x8000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 15
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x10000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x10000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 16
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x20000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x20000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 17
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x40000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x40000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 18
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x80000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x80000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 19
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x100000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x100000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 20
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x200000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x200000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 21
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x400000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x400000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 22
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x800000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x800000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 23
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x1000000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x1000000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 24
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x2000000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x2000000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 25
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x4000000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x4000000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 26
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x8000000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x8000000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 27
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x10000000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x10000000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 28
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 0x20000000
+; GFX11-NEXT: s_and_b32 s8, s4, 0x20000000
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 29
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
; GFX11-NEXT: s_cselect_b32 s13, 0, s15
; GFX11-NEXT: s_cselect_b32 s12, 0, s14
-; GFX11-NEXT: s_and_b32 s10, s4, 2.0
+; GFX11-NEXT: s_and_b32 s8, s4, 2.0
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], 30
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
-; GFX11-NEXT: s_cselect_b32 s11, 0, s15
-; GFX11-NEXT: s_cselect_b32 s10, 0, s14
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u64 s[8:9], 0
+; GFX11-NEXT: s_cselect_b32 s9, 0, s15
+; GFX11-NEXT: s_cselect_b32 s8, 0, s14
; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 31
-; GFX11-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
+; GFX11-NEXT: s_xor_b64 s[8:9], s[10:11], s[8:9]
; GFX11-NEXT: s_cmp_gt_i32 s4, -1
; GFX11-NEXT: s_mov_b32 s4, s0
; GFX11-NEXT: s_cselect_b32 s3, 0, s3
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
index 1bbe503bfe072..4b51e78e634b2 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
@@ -14,12 +14,11 @@ define amdgpu_kernel void @uniform_trunc_i16_to_i1(ptr addrspace(1) %out, i16 %x
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE killed [[COPY2]], %subreg.sub0, killed [[COPY1]], %subreg.sub1, killed [[S_MOV_B32_1]], %subreg.sub2, killed [[S_MOV_B32_]], %subreg.sub3
+ ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY killed [[S_LOAD_DWORD_IMM]]
; GCN-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 16
- ; GCN-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[S_LOAD_DWORD_IMM]], [[S_MOV_B32_2]], implicit-def dead $scc
- ; GCN-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[S_LOAD_DWORD_IMM]], [[S_MOV_B32_2]], implicit-def dead $scc
- ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY killed [[S_LSHR_B32_]]
- ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY3]], implicit-def dead $scc
- ; GCN-NEXT: S_CMP_EQ_U32 killed [[S_AND_B32_]], 1, implicit-def $scc
+ ; GCN-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY3]], killed [[S_MOV_B32_2]], implicit-def dead $scc
+ ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 65536, [[COPY3]], implicit-def dead $scc
+ ; GCN-NEXT: S_CMP_LG_U32 killed [[S_AND_B32_]], 0, implicit-def $scc
; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_64 = COPY $scc
; GCN-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GCN-NEXT: S_CMP_LT_I32 killed [[S_LSHL_B32_]], killed [[S_MOV_B32_3]], implicit-def $scc
diff --git a/llvm/test/CodeGen/AMDGPU/fract-match.ll b/llvm/test/CodeGen/AMDGPU/fract-match.ll
index 17c93482564f8..9f5efb9d7005d 100644
--- a/llvm/test/CodeGen/AMDGPU/fract-match.ll
+++ b/llvm/test/CodeGen/AMDGPU/fract-match.ll
@@ -138,26 +138,30 @@ define <3 x float> @safe_math_fract_v3f32(<3 x float> %x, ptr addrspace(1) write
; GFX6-LABEL: safe_math_fract_v3f32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s6, 0
+; GFX6-NEXT: v_floor_f32_e32 v6, v1
+; GFX6-NEXT: s_mov_b32 s4, s6
; GFX6-NEXT: v_floor_f32_e32 v7, v2
+; GFX6-NEXT: v_sub_f32_e32 v8, v1, v6
; GFX6-NEXT: v_floor_f32_e32 v5, v0
-; GFX6-NEXT: v_sub_f32_e32 v8, v2, v7
-; GFX6-NEXT: v_sub_f32_e32 v9, v0, v5
-; GFX6-NEXT: v_min_f32_e32 v8, 0x3f7fffff, v8
-; GFX6-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; GFX6-NEXT: v_sub_f32_e32 v9, v2, v7
+; GFX6-NEXT: v_min_f32_e32 v8, s4, v8
+; GFX6-NEXT: v_cmp_u_f32_e32 vcc, s4, v1
+; GFX6-NEXT: v_sub_f32_e32 v10, v0, v5
; GFX6-NEXT: v_min_f32_e32 v9, 0x3f7fffff, v9
-; GFX6-NEXT: v_cndmask_b32_e32 v8, v8, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
+; GFX6-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; GFX6-NEXT: v_min_f32_e32 v10, 0x3f7fffff, v10
+; GFX6-NEXT: v_cndmask_b32_e32 v8, v9, v2, vcc
; GFX6-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v9, v10, v0, vcc
; GFX6-NEXT: v_mov_b32_e32 v10, 0x204
-; GFX6-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc
; GFX6-NEXT: v_cmp_class_f32_e32 vcc, v0, v10
-; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: v_cndmask_b32_e64 v0, v9, 0, vcc
; GFX6-NEXT: v_cmp_class_f32_e32 vcc, v2, v10
; GFX6-NEXT: s_mov_b32 s7, 0xf000
-; GFX6-NEXT: s_mov_b32 s4, s6
; GFX6-NEXT: s_mov_b32 s5, s6
; GFX6-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc
-; GFX6-NEXT: v_floor_f32_e32 v6, v1
; GFX6-NEXT: buffer_store_dword v7, v[3:4], s[4:7], 0 addr64 offset:8
; GFX6-NEXT: buffer_store_dwordx2 v[5:6], v[3:4], s[4:7], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll
index 8880bc9bb2057..f4b183cd8149e 100644
--- a/llvm/test/CodeGen/AMDGPU/srem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/srem64.ll
@@ -944,20 +944,20 @@ define amdgpu_kernel void @s_test_srem32_64(ptr addrspace(1) %out, i64 %x, i64 %
define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_srem33_64:
; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; GCN-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
+; GCN-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0xd
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_ashr_i64 s[6:7], s[2:3], 31
-; GCN-NEXT: s_ashr_i64 s[2:3], s[4:5], 31
-; GCN-NEXT: s_ashr_i32 s4, s3, 31
-; GCN-NEXT: s_add_u32 s2, s2, s4
-; GCN-NEXT: s_mov_b32 s5, s4
-; GCN-NEXT: s_addc_u32 s3, s3, s4
-; GCN-NEXT: s_xor_b64 s[4:5], s[2:3], s[4:5]
+; GCN-NEXT: s_ashr_i64 s[0:1], s[10:11], 31
+; GCN-NEXT: s_ashr_i64 s[4:5], s[2:3], 31
+; GCN-NEXT: s_ashr_i32 s2, s3, 31
+; GCN-NEXT: s_add_u32 s4, s4, s2
+; GCN-NEXT: s_mov_b32 s3, s2
+; GCN-NEXT: s_addc_u32 s5, s5, s2
+; GCN-NEXT: s_xor_b64 s[4:5], s[4:5], s[2:3]
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s5
-; GCN-NEXT: s_sub_u32 s8, 0, s4
-; GCN-NEXT: s_subb_u32 s9, 0, s5
+; GCN-NEXT: s_sub_u32 s6, 0, s4
+; GCN-NEXT: s_subb_u32 s7, 0, s5
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0
; GCN-NEXT: v_rcp_f32_e32 v0, v0
@@ -967,104 +967,105 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_mul_hi_u32 v2, s8, v0
+; GCN-NEXT: v_mul_hi_u32 v2, s6, v0
; GCN-NEXT: v_readfirstlane_b32 s10, v1
; GCN-NEXT: v_readfirstlane_b32 s2, v0
-; GCN-NEXT: s_mul_i32 s11, s8, s10
-; GCN-NEXT: v_readfirstlane_b32 s14, v2
-; GCN-NEXT: s_mul_i32 s12, s9, s2
-; GCN-NEXT: s_mul_i32 s13, s8, s2
-; GCN-NEXT: s_add_i32 s11, s14, s11
-; GCN-NEXT: v_mul_hi_u32 v3, v0, s13
-; GCN-NEXT: s_add_i32 s11, s11, s12
-; GCN-NEXT: v_mul_hi_u32 v0, v0, s11
-; GCN-NEXT: v_mul_hi_u32 v4, v1, s13
-; GCN-NEXT: v_readfirstlane_b32 s12, v3
-; GCN-NEXT: s_mul_i32 s14, s2, s11
-; GCN-NEXT: v_mul_hi_u32 v1, v1, s11
-; GCN-NEXT: s_add_u32 s12, s12, s14
+; GCN-NEXT: s_mul_i32 s12, s6, s10
+; GCN-NEXT: v_readfirstlane_b32 s15, v2
+; GCN-NEXT: s_mul_i32 s13, s7, s2
+; GCN-NEXT: s_mul_i32 s14, s6, s2
+; GCN-NEXT: s_add_i32 s12, s15, s12
+; GCN-NEXT: v_mul_hi_u32 v3, v0, s14
+; GCN-NEXT: s_add_i32 s12, s12, s13
+; GCN-NEXT: v_mul_hi_u32 v0, v0, s12
+; GCN-NEXT: v_mul_hi_u32 v4, v1, s14
+; GCN-NEXT: v_readfirstlane_b32 s13, v3
+; GCN-NEXT: s_mul_i32 s15, s2, s12
+; GCN-NEXT: s_add_u32 s13, s13, s15
+; GCN-NEXT: v_readfirstlane_b32 s15, v0
+; GCN-NEXT: v_mul_hi_u32 v0, v1, s12
+; GCN-NEXT: s_addc_u32 s15, 0, s15
+; GCN-NEXT: s_mul_i32 s14, s10, s14
+; GCN-NEXT: v_readfirstlane_b32 s16, v4
+; GCN-NEXT: s_add_u32 s13, s13, s14
+; GCN-NEXT: s_addc_u32 s13, s15, s16
; GCN-NEXT: v_readfirstlane_b32 s14, v0
-; GCN-NEXT: s_addc_u32 s14, 0, s14
-; GCN-NEXT: s_mul_i32 s13, s10, s13
-; GCN-NEXT: v_readfirstlane_b32 s15, v4
-; GCN-NEXT: s_add_u32 s12, s12, s13
-; GCN-NEXT: s_addc_u32 s12, s14, s15
-; GCN-NEXT: v_readfirstlane_b32 s13, v1
-; GCN-NEXT: s_addc_u32 s13, s13, 0
-; GCN-NEXT: s_mul_i32 s11, s10, s11
-; GCN-NEXT: s_add_u32 s11, s12, s11
-; GCN-NEXT: s_addc_u32 s12, 0, s13
-; GCN-NEXT: s_add_u32 s11, s2, s11
-; GCN-NEXT: v_mov_b32_e32 v0, s11
-; GCN-NEXT: v_mul_hi_u32 v0, s8, v0
-; GCN-NEXT: s_addc_u32 s10, s10, s12
-; GCN-NEXT: s_mul_i32 s12, s8, s10
-; GCN-NEXT: s_mul_i32 s9, s9, s11
-; GCN-NEXT: v_readfirstlane_b32 s13, v0
-; GCN-NEXT: s_add_i32 s12, s13, s12
-; GCN-NEXT: s_mul_i32 s8, s8, s11
-; GCN-NEXT: s_add_i32 s9, s12, s9
-; GCN-NEXT: v_mov_b32_e32 v2, s8
-; GCN-NEXT: v_mov_b32_e32 v0, s9
+; GCN-NEXT: s_addc_u32 s14, s14, 0
+; GCN-NEXT: s_mul_i32 s12, s10, s12
+; GCN-NEXT: s_add_u32 s12, s13, s12
+; GCN-NEXT: s_addc_u32 s13, 0, s14
+; GCN-NEXT: s_add_u32 s12, s2, s12
+; GCN-NEXT: v_mov_b32_e32 v0, s12
+; GCN-NEXT: v_mul_hi_u32 v0, s6, v0
+; GCN-NEXT: s_addc_u32 s10, s10, s13
+; GCN-NEXT: s_mul_i32 s13, s6, s10
+; GCN-NEXT: s_mul_i32 s7, s7, s12
+; GCN-NEXT: v_readfirstlane_b32 s14, v0
+; GCN-NEXT: s_add_i32 s13, s14, s13
+; GCN-NEXT: s_mul_i32 s6, s6, s12
+; GCN-NEXT: s_add_i32 s7, s13, s7
+; GCN-NEXT: v_mov_b32_e32 v2, s6
+; GCN-NEXT: v_mov_b32_e32 v0, s7
; GCN-NEXT: v_mul_hi_u32 v3, s10, v2
-; GCN-NEXT: v_mul_hi_u32 v2, s11, v2
+; GCN-NEXT: v_mul_hi_u32 v2, s12, v2
; GCN-NEXT: v_mul_hi_u32 v1, s10, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s11, v0
-; GCN-NEXT: s_mul_i32 s13, s11, s9
-; GCN-NEXT: v_readfirstlane_b32 s15, v2
-; GCN-NEXT: s_add_u32 s13, s15, s13
-; GCN-NEXT: v_readfirstlane_b32 s14, v0
-; GCN-NEXT: s_mul_i32 s8, s10, s8
-; GCN-NEXT: s_addc_u32 s14, 0, s14
-; GCN-NEXT: v_readfirstlane_b32 s12, v3
-; GCN-NEXT: s_add_u32 s8, s13, s8
-; GCN-NEXT: s_addc_u32 s8, s14, s12
-; GCN-NEXT: v_readfirstlane_b32 s12, v1
-; GCN-NEXT: s_addc_u32 s12, s12, 0
-; GCN-NEXT: s_mul_i32 s9, s10, s9
-; GCN-NEXT: s_add_u32 s8, s8, s9
-; GCN-NEXT: s_addc_u32 s9, 0, s12
-; GCN-NEXT: s_add_u32 s11, s11, s8
-; GCN-NEXT: s_addc_u32 s10, s10, s9
-; GCN-NEXT: s_ashr_i32 s8, s7, 31
-; GCN-NEXT: s_add_u32 s6, s6, s8
-; GCN-NEXT: s_mov_b32 s9, s8
-; GCN-NEXT: s_addc_u32 s7, s7, s8
-; GCN-NEXT: s_xor_b64 s[6:7], s[6:7], s[8:9]
-; GCN-NEXT: v_mov_b32_e32 v0, s10
-; GCN-NEXT: v_mul_hi_u32 v1, s6, v0
-; GCN-NEXT: v_mov_b32_e32 v2, s11
-; GCN-NEXT: v_mul_hi_u32 v3, s6, v2
-; GCN-NEXT: s_mul_i32 s12, s6, s10
+; GCN-NEXT: v_mul_hi_u32 v0, s12, v0
+; GCN-NEXT: s_mul_i32 s14, s12, s7
+; GCN-NEXT: v_readfirstlane_b32 s16, v2
+; GCN-NEXT: s_add_u32 s14, s16, s14
+; GCN-NEXT: v_readfirstlane_b32 s15, v0
+; GCN-NEXT: s_mul_i32 s6, s10, s6
+; GCN-NEXT: s_addc_u32 s15, 0, s15
+; GCN-NEXT: v_readfirstlane_b32 s13, v3
+; GCN-NEXT: s_add_u32 s6, s14, s6
+; GCN-NEXT: s_addc_u32 s6, s15, s13
; GCN-NEXT: v_readfirstlane_b32 s13, v1
-; GCN-NEXT: v_mul_hi_u32 v1, s7, v2
+; GCN-NEXT: s_addc_u32 s13, s13, 0
+; GCN-NEXT: s_mul_i32 s7, s10, s7
+; GCN-NEXT: s_add_u32 s6, s6, s7
+; GCN-NEXT: s_addc_u32 s7, 0, s13
+; GCN-NEXT: s_add_u32 s12, s12, s6
+; GCN-NEXT: s_addc_u32 s13, s10, s7
+; GCN-NEXT: s_ashr_i32 s6, s11, 31
+; GCN-NEXT: s_add_u32 s0, s0, s6
+; GCN-NEXT: s_mov_b32 s7, s6
+; GCN-NEXT: s_addc_u32 s1, s1, s6
+; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[6:7]
+; GCN-NEXT: v_mov_b32_e32 v0, s13
+; GCN-NEXT: v_mul_hi_u32 v1, s10, v0
+; GCN-NEXT: v_mov_b32_e32 v2, s12
+; GCN-NEXT: v_mul_hi_u32 v3, s10, v2
+; GCN-NEXT: s_mov_b32 s0, s8
+; GCN-NEXT: v_readfirstlane_b32 s8, v1
+; GCN-NEXT: v_mul_hi_u32 v1, s11, v2
+; GCN-NEXT: s_mul_i32 s1, s10, s13
; GCN-NEXT: v_readfirstlane_b32 s14, v3
-; GCN-NEXT: v_mul_hi_u32 v0, s7, v0
-; GCN-NEXT: s_add_u32 s12, s14, s12
-; GCN-NEXT: s_addc_u32 s13, 0, s13
-; GCN-NEXT: s_mul_i32 s11, s7, s11
+; GCN-NEXT: v_mul_hi_u32 v0, s11, v0
+; GCN-NEXT: s_add_u32 s1, s14, s1
+; GCN-NEXT: s_addc_u32 s8, 0, s8
+; GCN-NEXT: s_mul_i32 s12, s11, s12
; GCN-NEXT: v_readfirstlane_b32 s14, v1
-; GCN-NEXT: s_add_u32 s11, s12, s11
-; GCN-NEXT: s_addc_u32 s11, s13, s14
-; GCN-NEXT: v_readfirstlane_b32 s12, v0
-; GCN-NEXT: s_addc_u32 s12, s12, 0
-; GCN-NEXT: s_mul_i32 s10, s7, s10
-; GCN-NEXT: s_add_u32 s10, s11, s10
-; GCN-NEXT: v_mov_b32_e32 v0, s10
+; GCN-NEXT: s_add_u32 s1, s1, s12
+; GCN-NEXT: s_addc_u32 s1, s8, s14
+; GCN-NEXT: v_readfirstlane_b32 s8, v0
+; GCN-NEXT: s_addc_u32 s8, s8, 0
+; GCN-NEXT: s_mul_i32 s12, s11, s13
+; GCN-NEXT: s_add_u32 s12, s1, s12
+; GCN-NEXT: v_mov_b32_e32 v0, s12
; GCN-NEXT: v_mul_hi_u32 v0, s4, v0
-; GCN-NEXT: s_addc_u32 s11, 0, s12
-; GCN-NEXT: s_mul_i32 s11, s4, s11
-; GCN-NEXT: s_mov_b32 s2, -1
-; GCN-NEXT: v_readfirstlane_b32 s12, v0
-; GCN-NEXT: s_add_i32 s11, s12, s11
-; GCN-NEXT: s_mul_i32 s12, s5, s10
-; GCN-NEXT: s_add_i32 s14, s11, s12
-; GCN-NEXT: s_sub_i32 s12, s7, s14
-; GCN-NEXT: s_mul_i32 s10, s4, s10
-; GCN-NEXT: s_sub_u32 s6, s6, s10
-; GCN-NEXT: s_cselect_b64 s[10:11], -1, 0
-; GCN-NEXT: s_subb_u32 s15, s12, s5
-; GCN-NEXT: s_sub_u32 s16, s6, s4
+; GCN-NEXT: s_addc_u32 s8, 0, s8
+; GCN-NEXT: s_mov_b32 s1, s9
+; GCN-NEXT: s_mul_i32 s8, s4, s8
+; GCN-NEXT: v_readfirstlane_b32 s9, v0
+; GCN-NEXT: s_add_i32 s8, s9, s8
+; GCN-NEXT: s_mul_i32 s9, s5, s12
+; GCN-NEXT: s_add_i32 s14, s8, s9
+; GCN-NEXT: s_sub_i32 s13, s11, s14
+; GCN-NEXT: s_mul_i32 s8, s4, s12
+; GCN-NEXT: s_sub_u32 s10, s10, s8
+; GCN-NEXT: s_cselect_b64 s[8:9], -1, 0
+; GCN-NEXT: s_subb_u32 s15, s13, s5
+; GCN-NEXT: s_sub_u32 s16, s10, s4
; GCN-NEXT: s_cselect_b64 s[12:13], -1, 0
; GCN-NEXT: s_subb_u32 s17, s15, 0
; GCN-NEXT: s_cmp_ge_u32 s17, s5
@@ -1080,21 +1081,22 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-NEXT: s_cmp_lg_u32 s18, 0
; GCN-NEXT: s_cselect_b32 s13, s13, s16
; GCN-NEXT: s_cselect_b32 s12, s12, s17
-; GCN-NEXT: s_or_b32 s10, s10, s11
-; GCN-NEXT: s_subb_u32 s7, s7, s14
-; GCN-NEXT: s_cmp_ge_u32 s7, s5
-; GCN-NEXT: s_cselect_b32 s10, -1, 0
-; GCN-NEXT: s_cmp_ge_u32 s6, s4
+; GCN-NEXT: s_or_b32 s8, s8, s9
+; GCN-NEXT: s_subb_u32 s8, s11, s14
+; GCN-NEXT: s_cmp_ge_u32 s8, s5
+; GCN-NEXT: s_cselect_b32 s9, -1, 0
+; GCN-NEXT: s_cmp_ge_u32 s10, s4
; GCN-NEXT: s_cselect_b32 s4, -1, 0
-; GCN-NEXT: s_cmp_eq_u32 s7, s5
-; GCN-NEXT: s_cselect_b32 s4, s4, s10
+; GCN-NEXT: s_cmp_eq_u32 s8, s5
+; GCN-NEXT: s_cselect_b32 s4, s4, s9
; GCN-NEXT: s_cmp_lg_u32 s4, 0
-; GCN-NEXT: s_cselect_b32 s5, s12, s7
-; GCN-NEXT: s_cselect_b32 s4, s13, s6
-; GCN-NEXT: s_xor_b64 s[4:5], s[4:5], s[8:9]
-; GCN-NEXT: s_sub_u32 s4, s4, s8
-; GCN-NEXT: s_subb_u32 s5, s5, s8
+; GCN-NEXT: s_cselect_b32 s5, s12, s8
+; GCN-NEXT: s_cselect_b32 s4, s13, s10
+; GCN-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]
+; GCN-NEXT: s_sub_u32 s4, s4, s6
+; GCN-NEXT: s_subb_u32 s5, s5, s6
; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-NEXT: s_endpgm
@@ -1102,25 +1104,25 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-IR-LABEL: s_test_srem33_64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; GCN-IR-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
; GCN-IR-NEXT: s_mov_b32 s13, 0
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 31
-; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[4:5], 31
; GCN-IR-NEXT: s_ashr_i32 s4, s3, 31
+; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[2:3], 31
; GCN-IR-NEXT: s_mov_b32 s5, s4
-; GCN-IR-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
+; GCN-IR-NEXT: s_ashr_i64 s[10:11], s[8:9], 31
+; GCN-IR-NEXT: s_xor_b64 s[2:3], s[6:7], s[4:5]
; GCN-IR-NEXT: s_sub_u32 s6, s2, s4
; GCN-IR-NEXT: s_subb_u32 s7, s3, s4
; GCN-IR-NEXT: s_ashr_i32 s2, s9, 31
; GCN-IR-NEXT: s_mov_b32 s3, s2
-; GCN-IR-NEXT: s_xor_b64 s[8:9], s[8:9], s[2:3]
+; GCN-IR-NEXT: s_xor_b64 s[8:9], s[10:11], s[2:3]
; GCN-IR-NEXT: s_sub_u32 s8, s8, s2
; GCN-IR-NEXT: s_subb_u32 s9, s9, s2
-; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
-; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[2:3], s[8:9], 0
+; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[2:3], s[6:7], 0
+; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[8:9], 0
; GCN-IR-NEXT: s_flbit_i32_b64 s12, s[8:9]
-; GCN-IR-NEXT: s_or_b64 s[10:11], s[2:3], s[10:11]
+; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[2:3]
; GCN-IR-NEXT: s_flbit_i32_b64 s18, s[6:7]
; GCN-IR-NEXT: s_sub_u32 s14, s12, s18
; GCN-IR-NEXT: s_subb_u32 s15, 0, 0
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
index 8ca36d4b9a5fa..11432e9ac8628 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
@@ -3951,8 +3951,8 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[4:5]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[2:3]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
@@ -4055,8 +4055,8 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[4:5]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[2:3]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
@@ -4163,8 +4163,8 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[4:5]
; GFX9-SDAG-NEXT: s_nop 1
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[2:3]
; GFX9-SDAG-NEXT: s_nop 1
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -4271,8 +4271,8 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX10-SDAG-NEXT: v_cmp_gt_i64_e64 s4, v[2:3], v[6:7]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -4375,8 +4375,8 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX11-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[6:7]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -4490,8 +4490,8 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
index 2107f2d6dd587..82cceaac20b8c 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
@@ -3950,8 +3950,8 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[4:5]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
@@ -4054,8 +4054,8 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[4:5]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
@@ -4162,8 +4162,8 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[4:5]
; GFX9-SDAG-NEXT: s_nop 1
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GFX9-SDAG-NEXT: s_nop 1
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -4270,8 +4270,8 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX10-SDAG-NEXT: v_cmp_lt_i64_e64 s4, v[2:3], v[6:7]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -4374,8 +4374,8 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX11-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[6:7]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -4489,8 +4489,8 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
index 78a8ec8d408d0..d1b6ed8fc3c07 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
@@ -3826,8 +3826,8 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[4:5]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[2:3]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
@@ -3930,8 +3930,8 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[4:5]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[2:3]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
@@ -4038,8 +4038,8 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[4:5]
; GFX9-SDAG-NEXT: s_nop 1
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[2:3]
; GFX9-SDAG-NEXT: s_nop 1
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -4146,8 +4146,8 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX10-SDAG-NEXT: v_cmp_gt_u64_e64 s4, v[2:3], v[6:7]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -4250,8 +4250,8 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX11-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[6:7]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -4365,8 +4365,8 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
index 5b2c1c3134acd..861ba34be38ba 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
@@ -3557,8 +3557,8 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[4:5]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
@@ -3661,8 +3661,8 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[4:5]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
@@ -3769,8 +3769,8 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[4:5]
; GFX9-SDAG-NEXT: s_nop 1
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GFX9-SDAG-NEXT: s_nop 1
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -3877,8 +3877,8 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX10-SDAG-NEXT: v_cmp_lt_u64_e64 s4, v[2:3], v[6:7]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -3981,8 +3981,8 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX11-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[6:7]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -4096,8 +4096,8 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
diff --git a/llvm/test/CodeGen/NVPTX/i128.ll b/llvm/test/CodeGen/NVPTX/i128.ll
index df1214c3f5e00..faf22112d56b4 100644
--- a/llvm/test/CodeGen/NVPTX/i128.ll
+++ b/llvm/test/CodeGen/NVPTX/i128.ll
@@ -149,75 +149,75 @@ define i128 @urem_i128(i128 %lhs, i128 %rhs) {
; CHECK-NEXT: .reg .b64 %rd<66>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %_udiv-special-cases
-; CHECK-NEXT: ld.param.v2.b64 {%rd5, %rd6}, [urem_i128_param_0];
+; CHECK-NEXT: ld.param.v2.b64 {%rd7, %rd8}, [urem_i128_param_0];
; CHECK-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [urem_i128_param_1];
-; CHECK-NEXT: or.b64 %rd7, %rd1, %rd2;
-; CHECK-NEXT: setp.eq.b64 %p1, %rd7, 0;
-; CHECK-NEXT: or.b64 %rd8, %rd5, %rd6;
-; CHECK-NEXT: setp.eq.b64 %p2, %rd8, 0;
+; CHECK-NEXT: or.b64 %rd9, %rd1, %rd2;
+; CHECK-NEXT: setp.eq.b64 %p1, %rd9, 0;
+; CHECK-NEXT: or.b64 %rd10, %rd7, %rd8;
+; CHECK-NEXT: setp.eq.b64 %p2, %rd10, 0;
; CHECK-NEXT: or.pred %p3, %p1, %p2;
; CHECK-NEXT: setp.ne.b64 %p4, %rd2, 0;
; CHECK-NEXT: clz.b64 %r1, %rd2;
-; CHECK-NEXT: cvt.u64.u32 %rd9, %r1;
+; CHECK-NEXT: cvt.u64.u32 %rd11, %r1;
; CHECK-NEXT: clz.b64 %r2, %rd1;
-; CHECK-NEXT: cvt.u64.u32 %rd10, %r2;
-; CHECK-NEXT: add.s64 %rd11, %rd10, 64;
-; CHECK-NEXT: selp.b64 %rd12, %rd9, %rd11, %p4;
-; CHECK-NEXT: setp.ne.b64 %p5, %rd6, 0;
-; CHECK-NEXT: clz.b64 %r3, %rd6;
-; CHECK-NEXT: cvt.u64.u32 %rd13, %r3;
-; CHECK-NEXT: clz.b64 %r4, %rd5;
-; CHECK-NEXT: cvt.u64.u32 %rd14, %r4;
-; CHECK-NEXT: add.s64 %rd15, %rd14, 64;
-; CHECK-NEXT: selp.b64 %rd16, %rd13, %rd15, %p5;
-; CHECK-NEXT: mov.b64 %rd17, 0;
-; CHECK-NEXT: sub.cc.s64 %rd18, %rd12, %rd16;
-; CHECK-NEXT: subc.cc.s64 %rd19, %rd17, 0;
-; CHECK-NEXT: setp.gt.u64 %p6, %rd18, 127;
-; CHECK-NEXT: setp.eq.b64 %p7, %rd19, 0;
+; CHECK-NEXT: cvt.u64.u32 %rd12, %r2;
+; CHECK-NEXT: add.s64 %rd13, %rd12, 64;
+; CHECK-NEXT: selp.b64 %rd14, %rd11, %rd13, %p4;
+; CHECK-NEXT: setp.ne.b64 %p5, %rd8, 0;
+; CHECK-NEXT: clz.b64 %r3, %rd8;
+; CHECK-NEXT: cvt.u64.u32 %rd15, %r3;
+; CHECK-NEXT: clz.b64 %r4, %rd7;
+; CHECK-NEXT: cvt.u64.u32 %rd16, %r4;
+; CHECK-NEXT: add.s64 %rd17, %rd16, 64;
+; CHECK-NEXT: selp.b64 %rd18, %rd15, %rd17, %p5;
+; CHECK-NEXT: mov.b64 %rd19, 0;
+; CHECK-NEXT: sub.cc.s64 %rd3, %rd14, %rd18;
+; CHECK-NEXT: subc.cc.s64 %rd4, %rd19, 0;
+; CHECK-NEXT: setp.gt.u64 %p6, %rd3, 127;
+; CHECK-NEXT: setp.eq.b64 %p7, %rd4, 0;
; CHECK-NEXT: and.pred %p8, %p7, %p6;
-; CHECK-NEXT: setp.ne.b64 %p9, %rd19, 0;
+; CHECK-NEXT: setp.ne.b64 %p9, %rd4, 0;
; CHECK-NEXT: or.pred %p10, %p8, %p9;
; CHECK-NEXT: or.pred %p11, %p3, %p10;
-; CHECK-NEXT: xor.b64 %rd20, %rd18, 127;
-; CHECK-NEXT: or.b64 %rd21, %rd20, %rd19;
+; CHECK-NEXT: xor.b64 %rd20, %rd3, 127;
+; CHECK-NEXT: or.b64 %rd21, %rd20, %rd4;
; CHECK-NEXT: setp.eq.b64 %p12, %rd21, 0;
-; CHECK-NEXT: selp.b64 %rd65, 0, %rd6, %p11;
-; CHECK-NEXT: selp.b64 %rd64, 0, %rd5, %p11;
+; CHECK-NEXT: selp.b64 %rd65, 0, %rd8, %p11;
+; CHECK-NEXT: selp.b64 %rd64, 0, %rd7, %p11;
; CHECK-NEXT: or.pred %p13, %p11, %p12;
; CHECK-NEXT: @%p13 bra $L__BB1_5;
; CHECK-NEXT: // %bb.1: // %udiv-bb1
-; CHECK-NEXT: add.cc.s64 %rd58, %rd18, 1;
-; CHECK-NEXT: addc.cc.s64 %rd59, %rd19, 0;
+; CHECK-NEXT: add.cc.s64 %rd58, %rd3, 1;
+; CHECK-NEXT: addc.cc.s64 %rd59, %rd4, 0;
; CHECK-NEXT: or.b64 %rd22, %rd58, %rd59;
; CHECK-NEXT: setp.eq.b64 %p14, %rd22, 0;
-; CHECK-NEXT: cvt.u32.u64 %r5, %rd18;
+; CHECK-NEXT: cvt.u32.u64 %r5, %rd3;
; CHECK-NEXT: sub.s32 %r6, 127, %r5;
-; CHECK-NEXT: shl.b64 %rd23, %rd6, %r6;
+; CHECK-NEXT: shl.b64 %rd23, %rd8, %r6;
; CHECK-NEXT: sub.s32 %r7, 64, %r6;
-; CHECK-NEXT: shr.u64 %rd24, %rd5, %r7;
+; CHECK-NEXT: shr.u64 %rd24, %rd7, %r7;
; CHECK-NEXT: or.b64 %rd25, %rd23, %rd24;
; CHECK-NEXT: sub.s32 %r8, 63, %r5;
-; CHECK-NEXT: shl.b64 %rd26, %rd5, %r8;
+; CHECK-NEXT: shl.b64 %rd26, %rd7, %r8;
; CHECK-NEXT: setp.gt.s32 %p15, %r6, 63;
; CHECK-NEXT: selp.b64 %rd63, %rd26, %rd25, %p15;
-; CHECK-NEXT: shl.b64 %rd62, %rd5, %r6;
+; CHECK-NEXT: shl.b64 %rd62, %rd7, %r6;
; CHECK-NEXT: mov.b64 %rd57, 0;
; CHECK-NEXT: mov.b64 %rd56, %rd57;
; CHECK-NEXT: @%p14 bra $L__BB1_4;
; CHECK-NEXT: // %bb.2: // %udiv-preheader
; CHECK-NEXT: cvt.u32.u64 %r9, %rd58;
-; CHECK-NEXT: shr.u64 %rd27, %rd5, %r9;
+; CHECK-NEXT: shr.u64 %rd27, %rd7, %r9;
; CHECK-NEXT: sub.s32 %r10, 64, %r9;
-; CHECK-NEXT: shl.b64 %rd28, %rd6, %r10;
+; CHECK-NEXT: shl.b64 %rd28, %rd8, %r10;
; CHECK-NEXT: or.b64 %rd29, %rd27, %rd28;
; CHECK-NEXT: add.s32 %r11, %r9, -64;
-; CHECK-NEXT: shr.u64 %rd30, %rd6, %r11;
+; CHECK-NEXT: shr.u64 %rd30, %rd8, %r11;
; CHECK-NEXT: setp.gt.s32 %p16, %r9, 63;
; CHECK-NEXT: selp.b64 %rd60, %rd30, %rd29, %p16;
-; CHECK-NEXT: shr.u64 %rd61, %rd6, %r9;
-; CHECK-NEXT: add.cc.s64 %rd3, %rd1, -1;
-; CHECK-NEXT: addc.cc.s64 %rd4, %rd2, -1;
+; CHECK-NEXT: shr.u64 %rd61, %rd8, %r9;
+; CHECK-NEXT: add.cc.s64 %rd5, %rd1, -1;
+; CHECK-NEXT: addc.cc.s64 %rd6, %rd2, -1;
; CHECK-NEXT: mov.b64 %rd56, %rd57;
; CHECK-NEXT: $L__BB1_3: // %udiv-do-while
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
@@ -233,8 +233,8 @@ define i128 @urem_i128(i128 %lhs, i128 %rhs) {
; CHECK-NEXT: shl.b64 %rd40, %rd62, 1;
; CHECK-NEXT: or.b64 %rd62, %rd56, %rd40;
; CHECK-NEXT: or.b64 %rd63, %rd57, %rd39;
-; CHECK-NEXT: sub.cc.s64 %rd41, %rd3, %rd36;
-; CHECK-NEXT: subc.cc.s64 %rd42, %rd4, %rd33;
+; CHECK-NEXT: sub.cc.s64 %rd41, %rd5, %rd36;
+; CHECK-NEXT: subc.cc.s64 %rd42, %rd6, %rd33;
; CHECK-NEXT: shr.s64 %rd43, %rd42, 63;
; CHECK-NEXT: and.b64 %rd56, %rd43, 1;
; CHECK-NEXT: and.b64 %rd44, %rd43, %rd1;
@@ -257,8 +257,8 @@ define i128 @urem_i128(i128 %lhs, i128 %rhs) {
; CHECK-NEXT: mad.lo.s64 %rd51, %rd1, %rd65, %rd50;
; CHECK-NEXT: mad.lo.s64 %rd52, %rd2, %rd64, %rd51;
; CHECK-NEXT: mul.lo.s64 %rd53, %rd1, %rd64;
-; CHECK-NEXT: sub.cc.s64 %rd54, %rd5, %rd53;
-; CHECK-NEXT: subc.cc.s64 %rd55, %rd6, %rd52;
+; CHECK-NEXT: sub.cc.s64 %rd54, %rd7, %rd53;
+; CHECK-NEXT: subc.cc.s64 %rd55, %rd8, %rd52;
; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd54, %rd55};
; CHECK-NEXT: ret;
%div = urem i128 %lhs, %rhs
@@ -441,75 +441,75 @@ define i128 @udiv_i128(i128 %lhs, i128 %rhs) {
; CHECK-NEXT: .reg .b64 %rd<60>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %_udiv-special-cases
-; CHECK-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [udiv_i128_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd5, %rd6}, [udiv_i128_param_1];
-; CHECK-NEXT: or.b64 %rd7, %rd5, %rd6;
-; CHECK-NEXT: setp.eq.b64 %p1, %rd7, 0;
-; CHECK-NEXT: or.b64 %rd8, %rd3, %rd4;
-; CHECK-NEXT: setp.eq.b64 %p2, %rd8, 0;
+; CHECK-NEXT: ld.param.v2.b64 {%rd5, %rd6}, [udiv_i128_param_0];
+; CHECK-NEXT: ld.param.v2.b64 {%rd7, %rd8}, [udiv_i128_param_1];
+; CHECK-NEXT: or.b64 %rd9, %rd7, %rd8;
+; CHECK-NEXT: setp.eq.b64 %p1, %rd9, 0;
+; CHECK-NEXT: or.b64 %rd10, %rd5, %rd6;
+; CHECK-NEXT: setp.eq.b64 %p2, %rd10, 0;
; CHECK-NEXT: or.pred %p3, %p1, %p2;
-; CHECK-NEXT: setp.ne.b64 %p4, %rd6, 0;
-; CHECK-NEXT: clz.b64 %r1, %rd6;
-; CHECK-NEXT: cvt.u64.u32 %rd9, %r1;
-; CHECK-NEXT: clz.b64 %r2, %rd5;
-; CHECK-NEXT: cvt.u64.u32 %rd10, %r2;
-; CHECK-NEXT: add.s64 %rd11, %rd10, 64;
-; CHECK-NEXT: selp.b64 %rd12, %rd9, %rd11, %p4;
-; CHECK-NEXT: setp.ne.b64 %p5, %rd4, 0;
-; CHECK-NEXT: clz.b64 %r3, %rd4;
-; CHECK-NEXT: cvt.u64.u32 %rd13, %r3;
-; CHECK-NEXT: clz.b64 %r4, %rd3;
-; CHECK-NEXT: cvt.u64.u32 %rd14, %r4;
-; CHECK-NEXT: add.s64 %rd15, %rd14, 64;
-; CHECK-NEXT: selp.b64 %rd16, %rd13, %rd15, %p5;
-; CHECK-NEXT: mov.b64 %rd17, 0;
-; CHECK-NEXT: sub.cc.s64 %rd18, %rd12, %rd16;
-; CHECK-NEXT: subc.cc.s64 %rd19, %rd17, 0;
-; CHECK-NEXT: setp.gt.u64 %p6, %rd18, 127;
-; CHECK-NEXT: setp.eq.b64 %p7, %rd19, 0;
+; CHECK-NEXT: setp.ne.b64 %p4, %rd8, 0;
+; CHECK-NEXT: clz.b64 %r1, %rd8;
+; CHECK-NEXT: cvt.u64.u32 %rd11, %r1;
+; CHECK-NEXT: clz.b64 %r2, %rd7;
+; CHECK-NEXT: cvt.u64.u32 %rd12, %r2;
+; CHECK-NEXT: add.s64 %rd13, %rd12, 64;
+; CHECK-NEXT: selp.b64 %rd14, %rd11, %rd13, %p4;
+; CHECK-NEXT: setp.ne.b64 %p5, %rd6, 0;
+; CHECK-NEXT: clz.b64 %r3, %rd6;
+; CHECK-NEXT: cvt.u64.u32 %rd15, %r3;
+; CHECK-NEXT: clz.b64 %r4, %rd5;
+; CHECK-NEXT: cvt.u64.u32 %rd16, %r4;
+; CHECK-NEXT: add.s64 %rd17, %rd16, 64;
+; CHECK-NEXT: selp.b64 %rd18, %rd15, %rd17, %p5;
+; CHECK-NEXT: mov.b64 %rd19, 0;
+; CHECK-NEXT: sub.cc.s64 %rd1, %rd14, %rd18;
+; CHECK-NEXT: subc.cc.s64 %rd2, %rd19, 0;
+; CHECK-NEXT: setp.gt.u64 %p6, %rd1, 127;
+; CHECK-NEXT: setp.eq.b64 %p7, %rd2, 0;
; CHECK-NEXT: and.pred %p8, %p7, %p6;
-; CHECK-NEXT: setp.ne.b64 %p9, %rd19, 0;
+; CHECK-NEXT: setp.ne.b64 %p9, %rd2, 0;
; CHECK-NEXT: or.pred %p10, %p8, %p9;
; CHECK-NEXT: or.pred %p11, %p3, %p10;
-; CHECK-NEXT: xor.b64 %rd20, %rd18, 127;
-; CHECK-NEXT: or.b64 %rd21, %rd20, %rd19;
+; CHECK-NEXT: xor.b64 %rd20, %rd1, 127;
+; CHECK-NEXT: or.b64 %rd21, %rd20, %rd2;
; CHECK-NEXT: setp.eq.b64 %p12, %rd21, 0;
-; CHECK-NEXT: selp.b64 %rd59, 0, %rd4, %p11;
-; CHECK-NEXT: selp.b64 %rd58, 0, %rd3, %p11;
+; CHECK-NEXT: selp.b64 %rd59, 0, %rd6, %p11;
+; CHECK-NEXT: selp.b64 %rd58, 0, %rd5, %p11;
; CHECK-NEXT: or.pred %p13, %p11, %p12;
; CHECK-NEXT: @%p13 bra $L__BB5_5;
; CHECK-NEXT: // %bb.1: // %udiv-bb1
-; CHECK-NEXT: add.cc.s64 %rd52, %rd18, 1;
-; CHECK-NEXT: addc.cc.s64 %rd53, %rd19, 0;
+; CHECK-NEXT: add.cc.s64 %rd52, %rd1, 1;
+; CHECK-NEXT: addc.cc.s64 %rd53, %rd2, 0;
; CHECK-NEXT: or.b64 %rd22, %rd52, %rd53;
; CHECK-NEXT: setp.eq.b64 %p14, %rd22, 0;
-; CHECK-NEXT: cvt.u32.u64 %r5, %rd18;
+; CHECK-NEXT: cvt.u32.u64 %r5, %rd1;
; CHECK-NEXT: sub.s32 %r6, 127, %r5;
-; CHECK-NEXT: shl.b64 %rd23, %rd4, %r6;
+; CHECK-NEXT: shl.b64 %rd23, %rd6, %r6;
; CHECK-NEXT: sub.s32 %r7, 64, %r6;
-; CHECK-NEXT: shr.u64 %rd24, %rd3, %r7;
+; CHECK-NEXT: shr.u64 %rd24, %rd5, %r7;
; CHECK-NEXT: or.b64 %rd25, %rd23, %rd24;
; CHECK-NEXT: sub.s32 %r8, 63, %r5;
-; CHECK-NEXT: shl.b64 %rd26, %rd3, %r8;
+; CHECK-NEXT: shl.b64 %rd26, %rd5, %r8;
; CHECK-NEXT: setp.gt.s32 %p15, %r6, 63;
; CHECK-NEXT: selp.b64 %rd57, %rd26, %rd25, %p15;
-; CHECK-NEXT: shl.b64 %rd56, %rd3, %r6;
+; CHECK-NEXT: shl.b64 %rd56, %rd5, %r6;
; CHECK-NEXT: mov.b64 %rd51, 0;
; CHECK-NEXT: mov.b64 %rd50, %rd51;
; CHECK-NEXT: @%p14 bra $L__BB5_4;
; CHECK-NEXT: // %bb.2: // %udiv-preheader
; CHECK-NEXT: cvt.u32.u64 %r9, %rd52;
-; CHECK-NEXT: shr.u64 %rd27, %rd3, %r9;
+; CHECK-NEXT: shr.u64 %rd27, %rd5, %r9;
; CHECK-NEXT: sub.s32 %r10, 64, %r9;
-; CHECK-NEXT: shl.b64 %rd28, %rd4, %r10;
+; CHECK-NEXT: shl.b64 %rd28, %rd6, %r10;
; CHECK-NEXT: or.b64 %rd29, %rd27, %rd28;
; CHECK-NEXT: add.s32 %r11, %r9, -64;
-; CHECK-NEXT: shr.u64 %rd30, %rd4, %r11;
+; CHECK-NEXT: shr.u64 %rd30, %rd6, %r11;
; CHECK-NEXT: setp.gt.s32 %p16, %r9, 63;
; CHECK-NEXT: selp.b64 %rd54, %rd30, %rd29, %p16;
-; CHECK-NEXT: shr.u64 %rd55, %rd4, %r9;
-; CHECK-NEXT: add.cc.s64 %rd1, %rd5, -1;
-; CHECK-NEXT: addc.cc.s64 %rd2, %rd6, -1;
+; CHECK-NEXT: shr.u64 %rd55, %rd6, %r9;
+; CHECK-NEXT: add.cc.s64 %rd3, %rd7, -1;
+; CHECK-NEXT: addc.cc.s64 %rd4, %rd8, -1;
; CHECK-NEXT: mov.b64 %rd50, %rd51;
; CHECK-NEXT: $L__BB5_3: // %udiv-do-while
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
@@ -525,12 +525,12 @@ define i128 @udiv_i128(i128 %lhs, i128 %rhs) {
; CHECK-NEXT: shl.b64 %rd40, %rd56, 1;
; CHECK-NEXT: or.b64 %rd56, %rd50, %rd40;
; CHECK-NEXT: or.b64 %rd57, %rd51, %rd39;
-; CHECK-NEXT: sub.cc.s64 %rd41, %rd1, %rd36;
-; CHECK-NEXT: subc.cc.s64 %rd42, %rd2, %rd33;
+; CHECK-NEXT: sub.cc.s64 %rd41, %rd3, %rd36;
+; CHECK-NEXT: subc.cc.s64 %rd42, %rd4, %rd33;
; CHECK-NEXT: shr.s64 %rd43, %rd42, 63;
; CHECK-NEXT: and.b64 %rd50, %rd43, 1;
-; CHECK-NEXT: and.b64 %rd44, %rd43, %rd5;
-; CHECK-NEXT: and.b64 %rd45, %rd43, %rd6;
+; CHECK-NEXT: and.b64 %rd44, %rd43, %rd7;
+; CHECK-NEXT: and.b64 %rd45, %rd43, %rd8;
; CHECK-NEXT: sub.cc.s64 %rd54, %rd36, %rd44;
; CHECK-NEXT: subc.cc.s64 %rd55, %rd33, %rd45;
; CHECK-NEXT: add.cc.s64 %rd52, %rd52, -1;
diff --git a/llvm/test/CodeGen/RISCV/abds.ll b/llvm/test/CodeGen/RISCV/abds.ll
index 0d36b59822032..d14ddc9daaf1d 100644
--- a/llvm/test/CodeGen/RISCV/abds.ll
+++ b/llvm/test/CodeGen/RISCV/abds.ll
@@ -2030,31 +2030,31 @@ define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: .LBB31_2:
; RV32I-NEXT: sub a6, a2, a6
; RV32I-NEXT: sub a1, a1, a4
-; RV32I-NEXT: sltu a2, a6, t1
-; RV32I-NEXT: sub a1, a1, t0
-; RV32I-NEXT: sub a2, a7, a2
+; RV32I-NEXT: sltu a4, a6, t1
+; RV32I-NEXT: sub a2, a1, t0
+; RV32I-NEXT: sub a1, a7, a4
; RV32I-NEXT: sub a4, a6, t1
; RV32I-NEXT: sub a3, a5, a3
-; RV32I-NEXT: bgez a2, .LBB31_4
+; RV32I-NEXT: bgez a1, .LBB31_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: neg a5, a4
-; RV32I-NEXT: or a6, a3, a1
+; RV32I-NEXT: or a6, a3, a2
; RV32I-NEXT: snez a4, a4
; RV32I-NEXT: snez a7, a3
+; RV32I-NEXT: neg a3, a3
; RV32I-NEXT: snez a6, a6
-; RV32I-NEXT: add a2, a2, a4
-; RV32I-NEXT: add a1, a1, a7
+; RV32I-NEXT: add a1, a1, a4
+; RV32I-NEXT: add a2, a2, a7
; RV32I-NEXT: sltu a7, a5, a6
-; RV32I-NEXT: neg a2, a2
-; RV32I-NEXT: sub a4, a5, a6
; RV32I-NEXT: neg a1, a1
-; RV32I-NEXT: sub a2, a2, a7
-; RV32I-NEXT: neg a3, a3
+; RV32I-NEXT: sub a4, a5, a6
+; RV32I-NEXT: sub a1, a1, a7
+; RV32I-NEXT: neg a2, a2
; RV32I-NEXT: .LBB31_4:
; RV32I-NEXT: sw a3, 0(a0)
-; RV32I-NEXT: sw a1, 4(a0)
+; RV32I-NEXT: sw a2, 4(a0)
; RV32I-NEXT: sw a4, 8(a0)
-; RV32I-NEXT: sw a2, 12(a0)
+; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: ret
;
; RV64I-LABEL: abd_subnsw_i128:
@@ -2093,31 +2093,31 @@ define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
; RV32ZBB-NEXT: .LBB31_2:
; RV32ZBB-NEXT: sub a6, a2, a6
; RV32ZBB-NEXT: sub a1, a1, a4
-; RV32ZBB-NEXT: sltu a2, a6, t1
-; RV32ZBB-NEXT: sub a1, a1, t0
-; RV32ZBB-NEXT: sub a2, a7, a2
+; RV32ZBB-NEXT: sltu a4, a6, t1
+; RV32ZBB-NEXT: sub a2, a1, t0
+; RV32ZBB-NEXT: sub a1, a7, a4
; RV32ZBB-NEXT: sub a4, a6, t1
; RV32ZBB-NEXT: sub a3, a5, a3
-; RV32ZBB-NEXT: bgez a2, .LBB31_4
+; RV32ZBB-NEXT: bgez a1, .LBB31_4
; RV32ZBB-NEXT: # %bb.3:
; RV32ZBB-NEXT: neg a5, a4
-; RV32ZBB-NEXT: or a6, a3, a1
+; RV32ZBB-NEXT: or a6, a3, a2
; RV32ZBB-NEXT: snez a4, a4
; RV32ZBB-NEXT: snez a7, a3
+; RV32ZBB-NEXT: neg a3, a3
; RV32ZBB-NEXT: snez a6, a6
-; RV32ZBB-NEXT: add a2, a2, a4
-; RV32ZBB-NEXT: add a1, a1, a7
+; RV32ZBB-NEXT: add a1, a1, a4
+; RV32ZBB-NEXT: add a2, a2, a7
; RV32ZBB-NEXT: sltu a7, a5, a6
-; RV32ZBB-NEXT: neg a2, a2
-; RV32ZBB-NEXT: sub a4, a5, a6
; RV32ZBB-NEXT: neg a1, a1
-; RV32ZBB-NEXT: sub a2, a2, a7
-; RV32ZBB-NEXT: neg a3, a3
+; RV32ZBB-NEXT: sub a4, a5, a6
+; RV32ZBB-NEXT: sub a1, a1, a7
+; RV32ZBB-NEXT: neg a2, a2
; RV32ZBB-NEXT: .LBB31_4:
; RV32ZBB-NEXT: sw a3, 0(a0)
-; RV32ZBB-NEXT: sw a1, 4(a0)
+; RV32ZBB-NEXT: sw a2, 4(a0)
; RV32ZBB-NEXT: sw a4, 8(a0)
-; RV32ZBB-NEXT: sw a2, 12(a0)
+; RV32ZBB-NEXT: sw a1, 12(a0)
; RV32ZBB-NEXT: ret
;
; RV64ZBB-LABEL: abd_subnsw_i128:
@@ -2161,31 +2161,31 @@ define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: .LBB32_2:
; RV32I-NEXT: sub a6, a2, a6
; RV32I-NEXT: sub a1, a1, a4
-; RV32I-NEXT: sltu a2, a6, t1
-; RV32I-NEXT: sub a1, a1, t0
-; RV32I-NEXT: sub a2, a7, a2
+; RV32I-NEXT: sltu a4, a6, t1
+; RV32I-NEXT: sub a2, a1, t0
+; RV32I-NEXT: sub a1, a7, a4
; RV32I-NEXT: sub a4, a6, t1
; RV32I-NEXT: sub a3, a5, a3
-; RV32I-NEXT: bgez a2, .LBB32_4
+; RV32I-NEXT: bgez a1, .LBB32_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: neg a5, a4
-; RV32I-NEXT: or a6, a3, a1
+; RV32I-NEXT: or a6, a3, a2
; RV32I-NEXT: snez a4, a4
; RV32I-NEXT: snez a7, a3
+; RV32I-NEXT: neg a3, a3
; RV32I-NEXT: snez a6, a6
-; RV32I-NEXT: add a2, a2, a4
-; RV32I-NEXT: add a1, a1, a7
+; RV32I-NEXT: add a1, a1, a4
+; RV32I-NEXT: add a2, a2, a7
; RV32I-NEXT: sltu a7, a5, a6
-; RV32I-NEXT: neg a2, a2
-; RV32I-NEXT: sub a4, a5, a6
; RV32I-NEXT: neg a1, a1
-; RV32I-NEXT: sub a2, a2, a7
-; RV32I-NEXT: neg a3, a3
+; RV32I-NEXT: sub a4, a5, a6
+; RV32I-NEXT: sub a1, a1, a7
+; RV32I-NEXT: neg a2, a2
; RV32I-NEXT: .LBB32_4:
; RV32I-NEXT: sw a3, 0(a0)
-; RV32I-NEXT: sw a1, 4(a0)
+; RV32I-NEXT: sw a2, 4(a0)
; RV32I-NEXT: sw a4, 8(a0)
-; RV32I-NEXT: sw a2, 12(a0)
+; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: ret
;
; RV64I-LABEL: abd_subnsw_i128_undef:
@@ -2224,31 +2224,31 @@ define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {
; RV32ZBB-NEXT: .LBB32_2:
; RV32ZBB-NEXT: sub a6, a2, a6
; RV32ZBB-NEXT: sub a1, a1, a4
-; RV32ZBB-NEXT: sltu a2, a6, t1
-; RV32ZBB-NEXT: sub a1, a1, t0
-; RV32ZBB-NEXT: sub a2, a7, a2
+; RV32ZBB-NEXT: sltu a4, a6, t1
+; RV32ZBB-NEXT: sub a2, a1, t0
+; RV32ZBB-NEXT: sub a1, a7, a4
; RV32ZBB-NEXT: sub a4, a6, t1
; RV32ZBB-NEXT: sub a3, a5, a3
-; RV32ZBB-NEXT: bgez a2, .LBB32_4
+; RV32ZBB-NEXT: bgez a1, .LBB32_4
; RV32ZBB-NEXT: # %bb.3:
; RV32ZBB-NEXT: neg a5, a4
-; RV32ZBB-NEXT: or a6, a3, a1
+; RV32ZBB-NEXT: or a6, a3, a2
; RV32ZBB-NEXT: snez a4, a4
; RV32ZBB-NEXT: snez a7, a3
+; RV32ZBB-NEXT: neg a3, a3
; RV32ZBB-NEXT: snez a6, a6
-; RV32ZBB-NEXT: add a2, a2, a4
-; RV32ZBB-NEXT: add a1, a1, a7
+; RV32ZBB-NEXT: add a1, a1, a4
+; RV32ZBB-NEXT: add a2, a2, a7
; RV32ZBB-NEXT: sltu a7, a5, a6
-; RV32ZBB-NEXT: neg a2, a2
-; RV32ZBB-NEXT: sub a4, a5, a6
; RV32ZBB-NEXT: neg a1, a1
-; RV32ZBB-NEXT: sub a2, a2, a7
-; RV32ZBB-NEXT: neg a3, a3
+; RV32ZBB-NEXT: sub a4, a5, a6
+; RV32ZBB-NEXT: sub a1, a1, a7
+; RV32ZBB-NEXT: neg a2, a2
; RV32ZBB-NEXT: .LBB32_4:
; RV32ZBB-NEXT: sw a3, 0(a0)
-; RV32ZBB-NEXT: sw a1, 4(a0)
+; RV32ZBB-NEXT: sw a2, 4(a0)
; RV32ZBB-NEXT: sw a4, 8(a0)
-; RV32ZBB-NEXT: sw a2, 12(a0)
+; RV32ZBB-NEXT: sw a1, 12(a0)
; RV32ZBB-NEXT: ret
;
; RV64ZBB-LABEL: abd_subnsw_i128_undef:
diff --git a/llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll b/llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll
index 749e7d2c97ff6..d58e7d9732a12 100644
--- a/llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll
+++ b/llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll
@@ -38,69 +38,69 @@ define void @test_bitint_200_add(ptr %a, ptr %b, ptr %out) nounwind {
; RV32: # %bb.0:
; RV32-NEXT: lw a4, 0(a0)
; RV32-NEXT: lw a5, 4(a0)
-; RV32-NEXT: lw t1, 8(a0)
-; RV32-NEXT: lw t0, 12(a0)
+; RV32-NEXT: lw t2, 8(a0)
+; RV32-NEXT: lw t1, 12(a0)
; RV32-NEXT: lw a3, 4(a1)
; RV32-NEXT: lw a7, 0(a1)
-; RV32-NEXT: lw t2, 8(a1)
+; RV32-NEXT: lw t3, 8(a1)
; RV32-NEXT: lw a6, 12(a1)
-; RV32-NEXT: add t3, a5, a3
+; RV32-NEXT: add t4, a5, a3
; RV32-NEXT: add a3, a4, a7
-; RV32-NEXT: sltu a7, a3, a4
-; RV32-NEXT: add a4, t3, a7
+; RV32-NEXT: sltu t0, a3, a4
+; RV32-NEXT: add a4, t4, t0
; RV32-NEXT: beq a4, a5, .LBB0_2
; RV32-NEXT: # %bb.1:
-; RV32-NEXT: sltu a7, a4, a5
+; RV32-NEXT: sltu t0, a4, a5
; RV32-NEXT: .LBB0_2:
-; RV32-NEXT: add t2, t1, t2
-; RV32-NEXT: add a6, t0, a6
-; RV32-NEXT: add a5, t2, a7
-; RV32-NEXT: sltu t3, t2, t1
-; RV32-NEXT: sltu t2, a5, t2
+; RV32-NEXT: lw a7, 20(a0)
+; RV32-NEXT: add t3, t2, t3
+; RV32-NEXT: add a6, t1, a6
+; RV32-NEXT: add a5, t3, t0
+; RV32-NEXT: sltu t4, t3, t2
+; RV32-NEXT: sltu t3, a5, t3
+; RV32-NEXT: add a6, a6, t4
; RV32-NEXT: add a6, a6, t3
-; RV32-NEXT: add a6, a6, t2
-; RV32-NEXT: beq a6, t0, .LBB0_4
+; RV32-NEXT: beq a6, t1, .LBB0_4
; RV32-NEXT: # %bb.3:
-; RV32-NEXT: sltu t4, a6, t0
+; RV32-NEXT: sltu t4, a6, t1
; RV32-NEXT: j .LBB0_5
; RV32-NEXT: .LBB0_4:
-; RV32-NEXT: sltu t4, a5, t1
+; RV32-NEXT: sltu t4, a5, t2
; RV32-NEXT: .LBB0_5:
; RV32-NEXT: lw t3, 16(a0)
-; RV32-NEXT: lw t2, 20(a0)
; RV32-NEXT: lw t6, 16(a1)
; RV32-NEXT: lw t5, 20(a1)
-; RV32-NEXT: xor t1, a5, t1
-; RV32-NEXT: xor t0, a6, t0
-; RV32-NEXT: or t0, t1, t0
-; RV32-NEXT: beqz t0, .LBB0_7
+; RV32-NEXT: xor t2, a5, t2
+; RV32-NEXT: xor t1, a6, t1
+; RV32-NEXT: or t1, t2, t1
+; RV32-NEXT: beqz t1, .LBB0_7
; RV32-NEXT: # %bb.6:
-; RV32-NEXT: mv a7, t4
+; RV32-NEXT: mv t0, t4
; RV32-NEXT: .LBB0_7:
; RV32-NEXT: lbu a0, 24(a0)
-; RV32-NEXT: lbu a1, 24(a1)
+; RV32-NEXT: lbu t1, 24(a1)
; RV32-NEXT: add t6, t3, t6
-; RV32-NEXT: add t4, t2, t5
-; RV32-NEXT: add a7, t6, a7
-; RV32-NEXT: sltu t1, t6, t3
-; RV32-NEXT: sltu t3, a7, t6
-; RV32-NEXT: add t4, t4, t1
-; RV32-NEXT: add t0, t4, t3
-; RV32-NEXT: sltu t5, t0, t4
+; RV32-NEXT: add t4, a7, t5
+; RV32-NEXT: add t0, t6, t0
+; RV32-NEXT: sltu t2, t6, t3
+; RV32-NEXT: sltu t3, t0, t6
+; RV32-NEXT: add t4, t4, t2
+; RV32-NEXT: add a1, t4, t3
+; RV32-NEXT: sltu t5, a1, t4
; RV32-NEXT: and t3, t3, t5
-; RV32-NEXT: beq t4, t2, .LBB0_9
+; RV32-NEXT: beq t4, a7, .LBB0_9
; RV32-NEXT: # %bb.8:
-; RV32-NEXT: sltu t1, t4, t2
+; RV32-NEXT: sltu t2, t4, a7
; RV32-NEXT: .LBB0_9:
-; RV32-NEXT: add a0, a0, a1
+; RV32-NEXT: add a0, a0, t1
; RV32-NEXT: sw a3, 0(a2)
; RV32-NEXT: sw a4, 4(a2)
; RV32-NEXT: sw a5, 8(a2)
; RV32-NEXT: sw a6, 12(a2)
-; RV32-NEXT: add a0, a0, t1
+; RV32-NEXT: add a0, a0, t2
; RV32-NEXT: add a0, a0, t3
-; RV32-NEXT: sw a7, 16(a2)
-; RV32-NEXT: sw t0, 20(a2)
+; RV32-NEXT: sw t0, 16(a2)
+; RV32-NEXT: sw a1, 20(a2)
; RV32-NEXT: sb a0, 24(a2)
; RV32-NEXT: ret
%1 = load i200, ptr %a, align 8
diff --git a/llvm/test/CodeGen/RISCV/clmul.ll b/llvm/test/CodeGen/RISCV/clmul.ll
index d9bbe20b8730d..15d1e44c21de3 100644
--- a/llvm/test/CodeGen/RISCV/clmul.ll
+++ b/llvm/test/CodeGen/RISCV/clmul.ll
@@ -2916,19 +2916,19 @@ define i64 @clmul_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: addi s2, s2, 1365
; RV32I-NEXT: srli a2, a3, 1
; RV32I-NEXT: and a3, a3, s2
-; RV32I-NEXT: and a2, a2, s2
; RV32I-NEXT: slli a3, a3, 1
-; RV32I-NEXT: or t5, a2, a3
-; RV32I-NEXT: srli a2, a4, 1
-; RV32I-NEXT: and a3, a4, s2
-; RV32I-NEXT: and a2, a2, s2
-; RV32I-NEXT: slli a3, a3, 1
-; RV32I-NEXT: or t2, a2, a3
-; RV32I-NEXT: srli a3, a3, 31
-; RV32I-NEXT: seqz a2, a3
-; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli a3, t5, 31
-; RV32I-NEXT: and a2, a2, a3
+; RV32I-NEXT: and a7, a2, s2
+; RV32I-NEXT: or t5, a7, a3
+; RV32I-NEXT: srli a3, a4, 1
+; RV32I-NEXT: and a4, a4, s2
+; RV32I-NEXT: and a3, a3, s2
+; RV32I-NEXT: slli a4, a4, 1
+; RV32I-NEXT: slli a2, a2, 31
+; RV32I-NEXT: or t2, a3, a4
+; RV32I-NEXT: srli a4, a4, 31
+; RV32I-NEXT: seqz a3, a4
+; RV32I-NEXT: addi a3, a3, -1
+; RV32I-NEXT: and a2, a3, a2
; RV32I-NEXT: sw a2, 296(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a2, t2, 2
; RV32I-NEXT: seqz a2, a2
@@ -5706,6 +5706,7 @@ define i64 @clmul_i64(i64 %a, i64 %b) nounwind {
; RV32IMZBS-NEXT: xor a4, a4, a1
; RV32IMZBS-NEXT: lui a1, 61681
; RV32IMZBS-NEXT: addi a1, a1, -241
+; RV32IMZBS-NEXT: sw a1, 336(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: srli a3, s8, 4
; RV32IMZBS-NEXT: and s1, s8, a1
; RV32IMZBS-NEXT: and a3, a3, a1
@@ -5718,283 +5719,282 @@ define i64 @clmul_i64(i64 %a, i64 %b) nounwind {
; RV32IMZBS-NEXT: or s2, a3, s2
; RV32IMZBS-NEXT: xor t3, a5, t3
; RV32IMZBS-NEXT: lui a3, 209715
-; RV32IMZBS-NEXT: lw a5, 156(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t5, t5, a5
-; RV32IMZBS-NEXT: lui s3, 349525
-; RV32IMZBS-NEXT: addi a5, a3, 819
-; RV32IMZBS-NEXT: lw a3, 72(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s0, s0, a3
-; RV32IMZBS-NEXT: addi a3, s3, 1365
+; RV32IMZBS-NEXT: lw a1, 156(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor t5, t5, a1
+; RV32IMZBS-NEXT: lui a1, 349525
+; RV32IMZBS-NEXT: addi a3, a3, 819
+; RV32IMZBS-NEXT: sw a3, 328(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a5, 72(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s0, s0, a5
+; RV32IMZBS-NEXT: addi a1, a1, 1365
; RV32IMZBS-NEXT: xor a7, a7, t0
-; RV32IMZBS-NEXT: lw t0, 160(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t0, t1, t0
-; RV32IMZBS-NEXT: lw t1, 76(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t1, t4, t1
+; RV32IMZBS-NEXT: lw a5, 160(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor t0, t1, a5
+; RV32IMZBS-NEXT: lw a5, 76(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor t1, t4, a5
; RV32IMZBS-NEXT: xor a0, a0, a2
; RV32IMZBS-NEXT: lw a2, 164(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a2, t6, a2
-; RV32IMZBS-NEXT: lw t4, 84(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a4, a4, t4
+; RV32IMZBS-NEXT: lw a5, 84(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a4, a4, a5
; RV32IMZBS-NEXT: srli t4, s1, 2
-; RV32IMZBS-NEXT: and s1, s1, a5
+; RV32IMZBS-NEXT: and s1, s1, a3
; RV32IMZBS-NEXT: srli t6, s2, 2
-; RV32IMZBS-NEXT: and s2, s2, a5
+; RV32IMZBS-NEXT: and s2, s2, a3
; RV32IMZBS-NEXT: xor t3, t3, t5
-; RV32IMZBS-NEXT: lw t5, 92(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t5, s0, t5
+; RV32IMZBS-NEXT: lw a5, 92(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor t5, s0, a5
; RV32IMZBS-NEXT: xor a7, a7, t0
-; RV32IMZBS-NEXT: lw t0, 88(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t0, t1, t0
+; RV32IMZBS-NEXT: lw a5, 88(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor t0, t1, a5
; RV32IMZBS-NEXT: xor a0, a0, a2
; RV32IMZBS-NEXT: lw a2, 80(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a2, a4, a2
-; RV32IMZBS-NEXT: and a4, t4, a5
+; RV32IMZBS-NEXT: and a4, t4, a3
; RV32IMZBS-NEXT: slli s1, s1, 2
-; RV32IMZBS-NEXT: and t1, t6, a5
+; RV32IMZBS-NEXT: and t1, t6, a3
; RV32IMZBS-NEXT: slli s2, s2, 2
; RV32IMZBS-NEXT: xor t3, t3, t5
; RV32IMZBS-NEXT: xor a7, a7, t0
; RV32IMZBS-NEXT: xor a0, a0, a2
-; RV32IMZBS-NEXT: sw a0, 336(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 332(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: or a4, a4, s1
; RV32IMZBS-NEXT: or a0, t1, s2
; RV32IMZBS-NEXT: xor a2, t3, t2
; RV32IMZBS-NEXT: xor a6, a7, a6
; RV32IMZBS-NEXT: srli a7, a4, 1
-; RV32IMZBS-NEXT: and a4, a4, a3
+; RV32IMZBS-NEXT: sw a1, 320(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a4, a4, a1
; RV32IMZBS-NEXT: srli t0, a0, 1
-; RV32IMZBS-NEXT: and a0, a0, a3
+; RV32IMZBS-NEXT: and a0, a0, a1
; RV32IMZBS-NEXT: xor a2, a6, a2
-; RV32IMZBS-NEXT: sw a2, 332(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a2, a7, a3
+; RV32IMZBS-NEXT: sw a2, 324(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a7, a1
; RV32IMZBS-NEXT: slli a4, a4, 1
-; RV32IMZBS-NEXT: and a7, t0, a3
+; RV32IMZBS-NEXT: and a6, t0, a1
; RV32IMZBS-NEXT: slli a0, a0, 1
-; RV32IMZBS-NEXT: or t3, a2, a4
-; RV32IMZBS-NEXT: or t1, a7, a0
+; RV32IMZBS-NEXT: slli a7, a7, 31
+; RV32IMZBS-NEXT: or s6, a2, a4
+; RV32IMZBS-NEXT: or t1, a6, a0
; RV32IMZBS-NEXT: srli a0, a0, 31
-; RV32IMZBS-NEXT: slli a2, t3, 1
+; RV32IMZBS-NEXT: slli a2, s6, 1
; RV32IMZBS-NEXT: andi a4, t1, 2
-; RV32IMZBS-NEXT: slli a7, t3, 2
-; RV32IMZBS-NEXT: andi s6, t1, 4
-; RV32IMZBS-NEXT: slli t0, t3, 3
-; RV32IMZBS-NEXT: andi t5, t1, 8
-; RV32IMZBS-NEXT: slli t6, t3, 4
-; RV32IMZBS-NEXT: andi s0, t1, 16
-; RV32IMZBS-NEXT: slli s1, t3, 5
-; RV32IMZBS-NEXT: andi s2, t1, 32
-; RV32IMZBS-NEXT: slli t4, t3, 6
-; RV32IMZBS-NEXT: andi s4, t1, 64
-; RV32IMZBS-NEXT: slli t2, t3, 7
-; RV32IMZBS-NEXT: andi s3, t1, 128
-; RV32IMZBS-NEXT: slli s5, t3, 8
-; RV32IMZBS-NEXT: andi s8, t1, 256
-; RV32IMZBS-NEXT: slli a6, t3, 31
+; RV32IMZBS-NEXT: slli a6, s6, 2
+; RV32IMZBS-NEXT: andi t4, t1, 4
+; RV32IMZBS-NEXT: slli t5, s6, 3
+; RV32IMZBS-NEXT: andi t6, t1, 8
+; RV32IMZBS-NEXT: slli t0, s6, 4
+; RV32IMZBS-NEXT: andi s1, t1, 16
+; RV32IMZBS-NEXT: slli a1, s6, 5
+; RV32IMZBS-NEXT: andi s3, t1, 32
+; RV32IMZBS-NEXT: slli a3, s6, 6
+; RV32IMZBS-NEXT: andi s5, t1, 64
+; RV32IMZBS-NEXT: slli t2, s6, 7
+; RV32IMZBS-NEXT: andi s7, t1, 128
+; RV32IMZBS-NEXT: slli s8, s6, 8
+; RV32IMZBS-NEXT: andi s9, t1, 256
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
-; RV32IMZBS-NEXT: and a0, a0, a6
-; RV32IMZBS-NEXT: sw a0, 328(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a0, t3, 9
+; RV32IMZBS-NEXT: and a0, a0, a7
+; RV32IMZBS-NEXT: sw a0, 316(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a0, s6, 9
; RV32IMZBS-NEXT: seqz a4, a4
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: and a2, a4, a2
-; RV32IMZBS-NEXT: sw a2, 324(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 312(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a2, t1, 512
-; RV32IMZBS-NEXT: seqz a4, s6
+; RV32IMZBS-NEXT: seqz a4, t4
; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: and a4, a4, a7
-; RV32IMZBS-NEXT: sw a4, 320(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, t3, 10
-; RV32IMZBS-NEXT: seqz a7, t5
+; RV32IMZBS-NEXT: and a4, a4, a6
+; RV32IMZBS-NEXT: sw a4, 308(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 10
+; RV32IMZBS-NEXT: seqz a7, t6
; RV32IMZBS-NEXT: addi a7, a7, -1
-; RV32IMZBS-NEXT: and a6, a7, t0
-; RV32IMZBS-NEXT: sw a6, 316(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a5, a7, t5
+; RV32IMZBS-NEXT: sw a5, 304(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a7, t1, 1024
-; RV32IMZBS-NEXT: seqz t5, s0
+; RV32IMZBS-NEXT: seqz t5, s1
; RV32IMZBS-NEXT: addi t5, t5, -1
-; RV32IMZBS-NEXT: and a6, t5, t6
-; RV32IMZBS-NEXT: sw a6, 312(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli t5, t3, 11
-; RV32IMZBS-NEXT: seqz t6, s2
+; RV32IMZBS-NEXT: and a5, t5, t0
+; RV32IMZBS-NEXT: sw a5, 300(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli s10, s6, 11
+; RV32IMZBS-NEXT: seqz t6, s3
; RV32IMZBS-NEXT: addi t6, t6, -1
-; RV32IMZBS-NEXT: and a6, t6, s1
-; RV32IMZBS-NEXT: sw a6, 304(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: not s2, t1
-; RV32IMZBS-NEXT: seqz t6, s4
+; RV32IMZBS-NEXT: and a1, t6, a1
+; RV32IMZBS-NEXT: sw a1, 296(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: not a5, t1
+; RV32IMZBS-NEXT: seqz t6, s5
; RV32IMZBS-NEXT: addi t6, t6, -1
-; RV32IMZBS-NEXT: and a6, t6, t4
-; RV32IMZBS-NEXT: sw a6, 308(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli s10, t3, 12
-; RV32IMZBS-NEXT: seqz s1, s3
+; RV32IMZBS-NEXT: and a1, t6, a3
+; RV32IMZBS-NEXT: sw a1, 292(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli s11, s6, 12
+; RV32IMZBS-NEXT: seqz s1, s7
; RV32IMZBS-NEXT: addi s1, s1, -1
-; RV32IMZBS-NEXT: and a6, s1, t2
-; RV32IMZBS-NEXT: sw a6, 296(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, t3, 13
-; RV32IMZBS-NEXT: seqz s1, s8
+; RV32IMZBS-NEXT: and s3, s1, t2
+; RV32IMZBS-NEXT: slli a1, s6, 13
+; RV32IMZBS-NEXT: seqz s1, s9
; RV32IMZBS-NEXT: addi s1, s1, -1
-; RV32IMZBS-NEXT: and s1, s1, s5
-; RV32IMZBS-NEXT: slli t0, t3, 14
+; RV32IMZBS-NEXT: and s5, s1, s8
+; RV32IMZBS-NEXT: slli s7, s6, 14
; RV32IMZBS-NEXT: seqz a2, a2
; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: and a0, a2, a0
-; RV32IMZBS-NEXT: sw a0, 292(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a0, t3, 15
+; RV32IMZBS-NEXT: and t5, a2, a0
+; RV32IMZBS-NEXT: slli a0, s6, 15
; RV32IMZBS-NEXT: seqz a2, a7
; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: and a2, a2, a4
-; RV32IMZBS-NEXT: sw a2, 300(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a2, s2, 11
+; RV32IMZBS-NEXT: and s1, a2, a4
+; RV32IMZBS-NEXT: bexti a2, a5, 11
; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: and t5, a2, t5
-; RV32IMZBS-NEXT: bexti a2, s2, 12
+; RV32IMZBS-NEXT: and s9, a2, s10
+; RV32IMZBS-NEXT: bexti a2, a5, 12
; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: and s10, a2, s10
-; RV32IMZBS-NEXT: bexti a2, s2, 13
+; RV32IMZBS-NEXT: and s10, a2, s11
+; RV32IMZBS-NEXT: bexti a2, a5, 13
; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: and s8, a2, a6
-; RV32IMZBS-NEXT: bexti a2, s2, 14
+; RV32IMZBS-NEXT: and s8, a2, a1
+; RV32IMZBS-NEXT: bexti a2, a5, 14
; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: and t6, a2, t0
-; RV32IMZBS-NEXT: bexti a2, s2, 15
+; RV32IMZBS-NEXT: and s7, a2, s7
+; RV32IMZBS-NEXT: bexti a2, a5, 15
; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: and s0, a2, a0
-; RV32IMZBS-NEXT: bexti a0, s2, 16
+; RV32IMZBS-NEXT: and t4, a2, a0
+; RV32IMZBS-NEXT: bexti a0, a5, 16
; RV32IMZBS-NEXT: addi a0, a0, -1
-; RV32IMZBS-NEXT: slli a4, t3, 16
+; RV32IMZBS-NEXT: slli a4, s6, 16
; RV32IMZBS-NEXT: and a4, a0, a4
-; RV32IMZBS-NEXT: bexti a0, s2, 17
+; RV32IMZBS-NEXT: bexti a0, a5, 17
; RV32IMZBS-NEXT: addi a0, a0, -1
-; RV32IMZBS-NEXT: slli a2, t3, 17
+; RV32IMZBS-NEXT: slli a2, s6, 17
; RV32IMZBS-NEXT: and a0, a0, a2
-; RV32IMZBS-NEXT: bexti a2, s2, 18
+; RV32IMZBS-NEXT: bexti a2, a5, 18
; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: slli a7, t3, 18
+; RV32IMZBS-NEXT: slli a7, s6, 18
; RV32IMZBS-NEXT: and a2, a2, a7
-; RV32IMZBS-NEXT: bexti a7, s2, 19
+; RV32IMZBS-NEXT: bexti a7, a5, 19
; RV32IMZBS-NEXT: addi a7, a7, -1
-; RV32IMZBS-NEXT: slli s11, t3, 19
+; RV32IMZBS-NEXT: slli s11, s6, 19
; RV32IMZBS-NEXT: and s11, a7, s11
-; RV32IMZBS-NEXT: bexti a7, s2, 20
+; RV32IMZBS-NEXT: bexti a7, a5, 20
; RV32IMZBS-NEXT: addi a7, a7, -1
-; RV32IMZBS-NEXT: slli ra, t3, 20
+; RV32IMZBS-NEXT: slli ra, s6, 20
; RV32IMZBS-NEXT: and ra, a7, ra
-; RV32IMZBS-NEXT: bexti a7, s2, 21
+; RV32IMZBS-NEXT: bexti a7, a5, 21
; RV32IMZBS-NEXT: addi a7, a7, -1
-; RV32IMZBS-NEXT: slli a6, t3, 21
+; RV32IMZBS-NEXT: slli a6, s6, 21
; RV32IMZBS-NEXT: and a7, a7, a6
-; RV32IMZBS-NEXT: bexti a6, s2, 22
+; RV32IMZBS-NEXT: bexti a6, a5, 22
; RV32IMZBS-NEXT: addi a6, a6, -1
-; RV32IMZBS-NEXT: slli t0, t3, 22
-; RV32IMZBS-NEXT: and a6, a6, t0
-; RV32IMZBS-NEXT: bexti t0, s2, 23
-; RV32IMZBS-NEXT: addi t0, t0, -1
-; RV32IMZBS-NEXT: slli t4, t3, 23
-; RV32IMZBS-NEXT: and t0, t0, t4
-; RV32IMZBS-NEXT: bexti t4, s2, 24
-; RV32IMZBS-NEXT: addi t4, t4, -1
-; RV32IMZBS-NEXT: slli s3, t3, 24
-; RV32IMZBS-NEXT: and t4, t4, s3
-; RV32IMZBS-NEXT: bexti s3, s2, 25
-; RV32IMZBS-NEXT: addi s3, s3, -1
-; RV32IMZBS-NEXT: slli t2, t3, 25
-; RV32IMZBS-NEXT: and t2, s3, t2
-; RV32IMZBS-NEXT: bexti s3, s2, 26
-; RV32IMZBS-NEXT: addi s3, s3, -1
-; RV32IMZBS-NEXT: slli s5, t3, 26
-; RV32IMZBS-NEXT: and s3, s3, s5
-; RV32IMZBS-NEXT: bexti s5, s2, 27
-; RV32IMZBS-NEXT: addi s5, s5, -1
-; RV32IMZBS-NEXT: slli s6, t3, 27
-; RV32IMZBS-NEXT: and s5, s5, s6
-; RV32IMZBS-NEXT: bexti s6, s2, 28
-; RV32IMZBS-NEXT: addi s6, s6, -1
-; RV32IMZBS-NEXT: slli s7, t3, 28
-; RV32IMZBS-NEXT: and s6, s6, s7
-; RV32IMZBS-NEXT: bexti s7, s2, 29
-; RV32IMZBS-NEXT: addi s7, s7, -1
-; RV32IMZBS-NEXT: slli s9, t3, 29
-; RV32IMZBS-NEXT: and s7, s7, s9
+; RV32IMZBS-NEXT: slli t3, s6, 22
+; RV32IMZBS-NEXT: and a6, a6, t3
+; RV32IMZBS-NEXT: bexti t3, a5, 23
+; RV32IMZBS-NEXT: addi t3, t3, -1
+; RV32IMZBS-NEXT: slli s0, s6, 23
+; RV32IMZBS-NEXT: and t3, t3, s0
+; RV32IMZBS-NEXT: bexti s0, a5, 24
+; RV32IMZBS-NEXT: addi s0, s0, -1
+; RV32IMZBS-NEXT: slli t0, s6, 24
+; RV32IMZBS-NEXT: and t0, s0, t0
+; RV32IMZBS-NEXT: bexti s0, a5, 25
+; RV32IMZBS-NEXT: addi s0, s0, -1
+; RV32IMZBS-NEXT: slli t2, s6, 25
+; RV32IMZBS-NEXT: and t2, s0, t2
+; RV32IMZBS-NEXT: bexti s0, a5, 26
+; RV32IMZBS-NEXT: addi s0, s0, -1
+; RV32IMZBS-NEXT: slli s2, s6, 26
+; RV32IMZBS-NEXT: and s0, s0, s2
+; RV32IMZBS-NEXT: bexti s2, a5, 27
+; RV32IMZBS-NEXT: addi s2, s2, -1
+; RV32IMZBS-NEXT: slli a1, s6, 27
+; RV32IMZBS-NEXT: and a1, s2, a1
+; RV32IMZBS-NEXT: bexti s2, a5, 28
+; RV32IMZBS-NEXT: addi s2, s2, -1
+; RV32IMZBS-NEXT: slli a3, s6, 28
+; RV32IMZBS-NEXT: and a3, s2, a3
+; RV32IMZBS-NEXT: bexti s2, a5, 29
+; RV32IMZBS-NEXT: addi s2, s2, -1
+; RV32IMZBS-NEXT: slli s4, s6, 29
+; RV32IMZBS-NEXT: and s2, s2, s4
; RV32IMZBS-NEXT: andi t1, t1, 1
; RV32IMZBS-NEXT: seqz t1, t1
; RV32IMZBS-NEXT: addi t1, t1, -1
-; RV32IMZBS-NEXT: and t1, t1, t3
-; RV32IMZBS-NEXT: slli t3, t3, 30
-; RV32IMZBS-NEXT: bexti s2, s2, 30
-; RV32IMZBS-NEXT: addi s2, s2, -1
-; RV32IMZBS-NEXT: and t3, s2, t3
-; RV32IMZBS-NEXT: lw s2, 324(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t1, t1, s2
-; RV32IMZBS-NEXT: lw s2, 320(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 316(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s2, s2, s9
-; RV32IMZBS-NEXT: lw s9, 312(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s4, 304(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s9, s9, s4
-; RV32IMZBS-NEXT: lw s4, 296(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s1, s4, s1
-; RV32IMZBS-NEXT: xor t5, t5, s10
+; RV32IMZBS-NEXT: and t1, t1, s6
+; RV32IMZBS-NEXT: slli s6, s6, 30
+; RV32IMZBS-NEXT: bexti a5, a5, 30
+; RV32IMZBS-NEXT: addi a5, a5, -1
+; RV32IMZBS-NEXT: and a5, a5, s6
+; RV32IMZBS-NEXT: lw s4, 312(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor t1, t1, s4
+; RV32IMZBS-NEXT: lw s4, 308(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s6, 304(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s4, s4, s6
+; RV32IMZBS-NEXT: lw s6, 300(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t6, 296(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s6, s6, t6
+; RV32IMZBS-NEXT: xor s3, s3, s5
+; RV32IMZBS-NEXT: xor s5, s9, s10
; RV32IMZBS-NEXT: xor a0, a4, a0
-; RV32IMZBS-NEXT: xor a4, a6, t0
-; RV32IMZBS-NEXT: xor a6, s7, t3
-; RV32IMZBS-NEXT: xor t0, t1, s2
-; RV32IMZBS-NEXT: lw t1, 308(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t1, s9, t1
-; RV32IMZBS-NEXT: lw t3, 292(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t3, s1, t3
-; RV32IMZBS-NEXT: xor t5, t5, s8
+; RV32IMZBS-NEXT: xor a4, a6, t3
+; RV32IMZBS-NEXT: xor a5, s2, a5
+; RV32IMZBS-NEXT: xor a6, t1, s4
+; RV32IMZBS-NEXT: lw t1, 292(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor t1, s6, t1
+; RV32IMZBS-NEXT: xor t3, s3, t5
+; RV32IMZBS-NEXT: xor t5, s5, s8
; RV32IMZBS-NEXT: xor a0, a0, a2
-; RV32IMZBS-NEXT: xor a2, a4, t4
-; RV32IMZBS-NEXT: lw a4, 328(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a4, a6, a4
-; RV32IMZBS-NEXT: xor a6, t0, t1
-; RV32IMZBS-NEXT: lw t0, 300(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t0, t3, t0
-; RV32IMZBS-NEXT: xor t1, t5, t6
+; RV32IMZBS-NEXT: xor a2, a4, t0
+; RV32IMZBS-NEXT: lw a4, 316(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a4, a5, a4
+; RV32IMZBS-NEXT: xor a5, a6, t1
+; RV32IMZBS-NEXT: xor a6, t3, s1
+; RV32IMZBS-NEXT: xor t0, t5, s7
; RV32IMZBS-NEXT: xor a0, a0, s11
; RV32IMZBS-NEXT: xor a2, a2, t2
-; RV32IMZBS-NEXT: xor a6, a6, t0
-; RV32IMZBS-NEXT: xor t0, t1, s0
+; RV32IMZBS-NEXT: xor a5, a5, a6
+; RV32IMZBS-NEXT: xor a6, t0, t4
; RV32IMZBS-NEXT: xor a0, a0, ra
-; RV32IMZBS-NEXT: xor a2, a2, s3
-; RV32IMZBS-NEXT: xor a6, a6, t0
+; RV32IMZBS-NEXT: xor a2, a2, s0
+; RV32IMZBS-NEXT: xor a5, a5, a6
; RV32IMZBS-NEXT: xor a0, a0, a7
-; RV32IMZBS-NEXT: xor a2, a2, s5
-; RV32IMZBS-NEXT: xor a0, a6, a0
-; RV32IMZBS-NEXT: xor a2, a2, s6
-; RV32IMZBS-NEXT: xor a0, a0, a2
+; RV32IMZBS-NEXT: xor a1, a2, a1
+; RV32IMZBS-NEXT: xor a0, a5, a0
+; RV32IMZBS-NEXT: xor a1, a1, a3
+; RV32IMZBS-NEXT: xor a0, a0, a1
; RV32IMZBS-NEXT: xor a0, a0, a4
-; RV32IMZBS-NEXT: srli a2, a0, 8
-; RV32IMZBS-NEXT: srli a4, a0, 24
-; RV32IMZBS-NEXT: lw a6, 344(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: and a2, a2, a6
-; RV32IMZBS-NEXT: or a2, a2, a4
-; RV32IMZBS-NEXT: and a4, a0, a6
+; RV32IMZBS-NEXT: srli a1, a0, 8
+; RV32IMZBS-NEXT: srli a2, a0, 24
+; RV32IMZBS-NEXT: lw a3, 344(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: and a1, a1, a3
+; RV32IMZBS-NEXT: or a1, a1, a2
+; RV32IMZBS-NEXT: and a2, a0, a3
; RV32IMZBS-NEXT: slli a0, a0, 24
-; RV32IMZBS-NEXT: slli a4, a4, 8
-; RV32IMZBS-NEXT: or a0, a0, a4
+; RV32IMZBS-NEXT: slli a2, a2, 8
; RV32IMZBS-NEXT: or a0, a0, a2
-; RV32IMZBS-NEXT: srli a2, a0, 4
-; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: and a1, a2, a1
+; RV32IMZBS-NEXT: or a0, a0, a1
+; RV32IMZBS-NEXT: srli a1, a0, 4
+; RV32IMZBS-NEXT: lw a2, 336(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: and a0, a0, a2
+; RV32IMZBS-NEXT: and a1, a1, a2
; RV32IMZBS-NEXT: slli a0, a0, 4
; RV32IMZBS-NEXT: or a0, a1, a0
; RV32IMZBS-NEXT: srli a1, a0, 2
-; RV32IMZBS-NEXT: and a0, a0, a5
-; RV32IMZBS-NEXT: and a1, a1, a5
+; RV32IMZBS-NEXT: lw a2, 328(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: and a0, a0, a2
+; RV32IMZBS-NEXT: and a1, a1, a2
; RV32IMZBS-NEXT: slli a0, a0, 2
; RV32IMZBS-NEXT: or a0, a1, a0
; RV32IMZBS-NEXT: lui a1, 349525
; RV32IMZBS-NEXT: addi a1, a1, 1364
-; RV32IMZBS-NEXT: and a3, a0, a3
+; RV32IMZBS-NEXT: lw a2, 320(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: and a2, a0, a2
; RV32IMZBS-NEXT: srli a0, a0, 1
; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: slli a3, a3, 1
-; RV32IMZBS-NEXT: or a0, a0, a3
+; RV32IMZBS-NEXT: slli a2, a2, 1
+; RV32IMZBS-NEXT: or a0, a0, a2
; RV32IMZBS-NEXT: srli a0, a0, 1
-; RV32IMZBS-NEXT: lw a1, 332(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 324(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a0, a1
; RV32IMZBS-NEXT: lw a0, 340(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 336(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 332(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a2, a0
; RV32IMZBS-NEXT: lw ra, 396(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw s0, 392(sp) # 4-byte Folded Reload
@@ -8922,40 +8922,40 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: sw a1, 716(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui s2, 349525
; RV32I-NEXT: addi s2, s2, 1365
-; RV32I-NEXT: srli a1, t2, 1
-; RV32I-NEXT: and a3, t2, s2
-; RV32I-NEXT: and a1, a1, s2
-; RV32I-NEXT: slli a3, a3, 1
-; RV32I-NEXT: or a1, a1, a3
+; RV32I-NEXT: srli a3, t2, 1
+; RV32I-NEXT: and a1, t2, s2
+; RV32I-NEXT: slli a1, a1, 1
+; RV32I-NEXT: and t0, a3, s2
+; RV32I-NEXT: or a1, t0, a1
; RV32I-NEXT: xor a0, a4, a0
; RV32I-NEXT: sw a0, 708(sp) # 4-byte Folded Spill
-; RV32I-NEXT: srli a0, s4, 1
-; RV32I-NEXT: and a3, s4, s2
-; RV32I-NEXT: and a0, a0, s2
-; RV32I-NEXT: slli a3, a3, 1
-; RV32I-NEXT: or a2, a0, a3
+; RV32I-NEXT: srli a4, s4, 1
+; RV32I-NEXT: and a0, s4, s2
+; RV32I-NEXT: slli a0, a0, 1
+; RV32I-NEXT: and t0, a4, s2
+; RV32I-NEXT: or a2, t0, a0
; RV32I-NEXT: xor a0, a7, a5
; RV32I-NEXT: sw a0, 704(sp) # 4-byte Folded Spill
; RV32I-NEXT: srli a0, s0, 1
-; RV32I-NEXT: and a3, s0, s2
+; RV32I-NEXT: and a5, s0, s2
; RV32I-NEXT: and a0, a0, s2
-; RV32I-NEXT: slli a3, a3, 1
-; RV32I-NEXT: or a0, a0, a3
-; RV32I-NEXT: srli a3, a3, 31
-; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: slli a4, a1, 31
-; RV32I-NEXT: and a3, a3, a4
+; RV32I-NEXT: slli a5, a5, 1
+; RV32I-NEXT: slli a3, a3, 31
+; RV32I-NEXT: or a0, a0, a5
+; RV32I-NEXT: srli a5, a5, 31
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: and a3, a5, a3
; RV32I-NEXT: sw a3, 700(sp) # 4-byte Folded Spill
; RV32I-NEXT: srli a3, s5, 1
-; RV32I-NEXT: and a4, s5, s2
+; RV32I-NEXT: and a5, s5, s2
; RV32I-NEXT: and a3, a3, s2
-; RV32I-NEXT: slli a4, a4, 1
-; RV32I-NEXT: or t3, a3, a4
-; RV32I-NEXT: srli a4, a4, 31
-; RV32I-NEXT: seqz a3, a4
+; RV32I-NEXT: slli a5, a5, 1
+; RV32I-NEXT: slli a4, a4, 31
+; RV32I-NEXT: or t3, a3, a5
+; RV32I-NEXT: srli a5, a5, 31
+; RV32I-NEXT: seqz a3, a5
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: slli a4, a2, 31
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: sw a3, 692(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a3, a0, 2
@@ -14929,34 +14929,36 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32IMZBS-NEXT: xor a5, a3, a5
; RV32IMZBS-NEXT: lui a2, 349525
; RV32IMZBS-NEXT: xor a0, a0, a1
-; RV32IMZBS-NEXT: addi s5, a2, 1365
+; RV32IMZBS-NEXT: addi s6, a2, 1365
; RV32IMZBS-NEXT: xor a1, t1, t6
; RV32IMZBS-NEXT: srli t1, a6, 1
-; RV32IMZBS-NEXT: and a6, a6, s5
+; RV32IMZBS-NEXT: and a6, a6, s6
; RV32IMZBS-NEXT: xor t2, s2, s3
; RV32IMZBS-NEXT: srli t6, t3, 1
-; RV32IMZBS-NEXT: and t3, t3, s5
+; RV32IMZBS-NEXT: and t3, t3, s6
; RV32IMZBS-NEXT: xor t4, t4, t5
; RV32IMZBS-NEXT: srli t5, s1, 1
-; RV32IMZBS-NEXT: and s1, s1, s5
+; RV32IMZBS-NEXT: and s1, s1, s6
; RV32IMZBS-NEXT: xor a7, a7, t0
; RV32IMZBS-NEXT: srli t0, s4, 1
-; RV32IMZBS-NEXT: and s0, s4, s5
+; RV32IMZBS-NEXT: and s0, s4, s6
; RV32IMZBS-NEXT: xor a4, a4, a5
-; RV32IMZBS-NEXT: and a5, t1, s5
+; RV32IMZBS-NEXT: and a5, t1, s6
; RV32IMZBS-NEXT: slli a6, a6, 1
-; RV32IMZBS-NEXT: and t1, t6, s5
+; RV32IMZBS-NEXT: and t6, t6, s6
; RV32IMZBS-NEXT: slli t3, t3, 1
+; RV32IMZBS-NEXT: slli t1, t1, 31
; RV32IMZBS-NEXT: lw a2, 676(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t6, a0, a2
+; RV32IMZBS-NEXT: xor s2, a0, a2
; RV32IMZBS-NEXT: lw a0, 680(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s2, a1, a0
-; RV32IMZBS-NEXT: and t5, t5, s5
+; RV32IMZBS-NEXT: xor s3, a1, a0
+; RV32IMZBS-NEXT: and s4, t5, s6
; RV32IMZBS-NEXT: slli s1, s1, 1
-; RV32IMZBS-NEXT: and t0, t0, s5
+; RV32IMZBS-NEXT: and t0, t0, s6
; RV32IMZBS-NEXT: slli s0, s0, 1
+; RV32IMZBS-NEXT: slli t5, t5, 31
; RV32IMZBS-NEXT: lw a0, 672(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s3, t2, a0
+; RV32IMZBS-NEXT: xor s5, t2, a0
; RV32IMZBS-NEXT: lw a0, 660(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t4, t4, a0
; RV32IMZBS-NEXT: lw a0, 652(sp) # 4-byte Folded Reload
@@ -14966,36 +14968,34 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32IMZBS-NEXT: xor a0, a4, a0
; RV32IMZBS-NEXT: sw a0, 716(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: or a0, a5, a6
-; RV32IMZBS-NEXT: or a1, t1, t3
+; RV32IMZBS-NEXT: or a1, t6, t3
; RV32IMZBS-NEXT: srli a4, t3, 31
-; RV32IMZBS-NEXT: xor a2, s2, t6
+; RV32IMZBS-NEXT: xor a2, s3, s2
; RV32IMZBS-NEXT: sw a2, 708(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: or a3, t5, s1
+; RV32IMZBS-NEXT: or a3, s4, s1
; RV32IMZBS-NEXT: or t3, t0, s0
; RV32IMZBS-NEXT: srli s0, s0, 31
-; RV32IMZBS-NEXT: xor a2, t4, s3
+; RV32IMZBS-NEXT: xor a2, t4, s5
; RV32IMZBS-NEXT: sw a2, 704(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: slli a5, a0, 1
; RV32IMZBS-NEXT: andi a6, a1, 2
; RV32IMZBS-NEXT: slli a7, a0, 2
; RV32IMZBS-NEXT: andi t0, a1, 4
-; RV32IMZBS-NEXT: slli t1, a0, 3
-; RV32IMZBS-NEXT: andi t4, a1, 8
-; RV32IMZBS-NEXT: slli t5, a0, 4
-; RV32IMZBS-NEXT: andi t6, a1, 16
-; RV32IMZBS-NEXT: slli s1, a0, 5
-; RV32IMZBS-NEXT: andi s2, a1, 32
-; RV32IMZBS-NEXT: slli s3, a0, 31
+; RV32IMZBS-NEXT: slli t4, a0, 3
+; RV32IMZBS-NEXT: andi t6, a1, 8
+; RV32IMZBS-NEXT: slli s1, a0, 4
+; RV32IMZBS-NEXT: andi s2, a1, 16
+; RV32IMZBS-NEXT: slli s3, a0, 5
; RV32IMZBS-NEXT: seqz a4, a4
; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: and a2, a4, s3
+; RV32IMZBS-NEXT: and a2, a4, t1
; RV32IMZBS-NEXT: sw a2, 692(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a3, 31
-; RV32IMZBS-NEXT: seqz s0, s0
-; RV32IMZBS-NEXT: addi s0, s0, -1
-; RV32IMZBS-NEXT: and a4, s0, a4
-; RV32IMZBS-NEXT: sw a4, 700(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a0, 6
+; RV32IMZBS-NEXT: andi a4, a1, 32
+; RV32IMZBS-NEXT: seqz t1, s0
+; RV32IMZBS-NEXT: addi t1, t1, -1
+; RV32IMZBS-NEXT: and a2, t1, t5
+; RV32IMZBS-NEXT: sw a2, 700(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli t1, a0, 6
; RV32IMZBS-NEXT: seqz a6, a6
; RV32IMZBS-NEXT: addi a6, a6, -1
; RV32IMZBS-NEXT: and a2, a6, a5
@@ -15006,45 +15006,45 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32IMZBS-NEXT: and a2, a6, a7
; RV32IMZBS-NEXT: sw a2, 684(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: slli a6, a0, 7
-; RV32IMZBS-NEXT: seqz a7, t4
+; RV32IMZBS-NEXT: seqz a7, t6
; RV32IMZBS-NEXT: addi a7, a7, -1
-; RV32IMZBS-NEXT: and a2, a7, t1
+; RV32IMZBS-NEXT: and a2, a7, t4
; RV32IMZBS-NEXT: sw a2, 672(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a7, a1, 128
-; RV32IMZBS-NEXT: seqz t0, t6
+; RV32IMZBS-NEXT: seqz t0, s2
; RV32IMZBS-NEXT: addi t0, t0, -1
-; RV32IMZBS-NEXT: and a2, t0, t5
+; RV32IMZBS-NEXT: and a2, t0, s1
; RV32IMZBS-NEXT: sw a2, 668(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: slli t0, a0, 8
-; RV32IMZBS-NEXT: seqz t1, s2
-; RV32IMZBS-NEXT: addi t1, t1, -1
-; RV32IMZBS-NEXT: and a2, t1, s1
+; RV32IMZBS-NEXT: seqz a4, a4
+; RV32IMZBS-NEXT: addi a4, a4, -1
+; RV32IMZBS-NEXT: and a2, a4, s3
; RV32IMZBS-NEXT: sw a2, 664(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi t1, a1, 256
+; RV32IMZBS-NEXT: andi a4, a1, 256
; RV32IMZBS-NEXT: seqz a5, a5
; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: and a4, a5, a4
-; RV32IMZBS-NEXT: sw a4, 680(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a0, 9
-; RV32IMZBS-NEXT: seqz a5, a7
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: and a2, a5, a6
+; RV32IMZBS-NEXT: and a2, a5, t1
+; RV32IMZBS-NEXT: sw a2, 680(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a5, a0, 9
+; RV32IMZBS-NEXT: seqz a7, a7
+; RV32IMZBS-NEXT: addi a7, a7, -1
+; RV32IMZBS-NEXT: and a2, a7, a6
; RV32IMZBS-NEXT: sw a2, 652(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a5, a1, 512
-; RV32IMZBS-NEXT: seqz a6, t1
-; RV32IMZBS-NEXT: addi a6, a6, -1
-; RV32IMZBS-NEXT: and a2, a6, t0
+; RV32IMZBS-NEXT: andi a6, a1, 512
+; RV32IMZBS-NEXT: seqz a4, a4
+; RV32IMZBS-NEXT: addi a4, a4, -1
+; RV32IMZBS-NEXT: and a2, a4, t0
; RV32IMZBS-NEXT: sw a2, 644(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, a0, 10
+; RV32IMZBS-NEXT: slli a4, a0, 10
+; RV32IMZBS-NEXT: seqz a6, a6
+; RV32IMZBS-NEXT: addi a6, a6, -1
+; RV32IMZBS-NEXT: and a2, a6, a5
+; RV32IMZBS-NEXT: sw a2, 660(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a5, a1, 1024
; RV32IMZBS-NEXT: seqz a5, a5
; RV32IMZBS-NEXT: addi a5, a5, -1
; RV32IMZBS-NEXT: and a4, a5, a4
-; RV32IMZBS-NEXT: sw a4, 660(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a4, a1, 1024
-; RV32IMZBS-NEXT: seqz a4, a4
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: and a2, a4, a6
-; RV32IMZBS-NEXT: sw a2, 676(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a4, 676(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: not a5, a1
; RV32IMZBS-NEXT: bexti a4, a5, 11
; RV32IMZBS-NEXT: addi a4, a4, -1
@@ -15243,7 +15243,7 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32IMZBS-NEXT: bexti a1, a0, 17
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: slli a4, a3, 17
-; RV32IMZBS-NEXT: and s6, a1, a4
+; RV32IMZBS-NEXT: and s5, a1, a4
; RV32IMZBS-NEXT: bexti a1, a0, 18
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: slli a4, a3, 18
@@ -15340,7 +15340,7 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32IMZBS-NEXT: lw ra, 516(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw s11, 504(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor ra, ra, s11
-; RV32IMZBS-NEXT: xor s6, s9, s6
+; RV32IMZBS-NEXT: xor s5, s9, s5
; RV32IMZBS-NEXT: xor t6, s0, t6
; RV32IMZBS-NEXT: xor t4, t5, t4
; RV32IMZBS-NEXT: xor t1, t1, t3
@@ -15363,7 +15363,7 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32IMZBS-NEXT: xor a2, a2, t2
; RV32IMZBS-NEXT: lw t2, 520(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t2, ra, t2
-; RV32IMZBS-NEXT: xor t3, s6, s10
+; RV32IMZBS-NEXT: xor t3, s5, s10
; RV32IMZBS-NEXT: xor t5, t6, s1
; RV32IMZBS-NEXT: lw t6, 700(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t4, t4, t6
@@ -15458,8 +15458,8 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32IMZBS-NEXT: slli a0, a0, 2
; RV32IMZBS-NEXT: or a0, a3, a0
; RV32IMZBS-NEXT: srli a3, a1, 1
-; RV32IMZBS-NEXT: and a1, a1, s5
-; RV32IMZBS-NEXT: and a4, a0, s5
+; RV32IMZBS-NEXT: and a1, a1, s6
+; RV32IMZBS-NEXT: and a4, a0, s6
; RV32IMZBS-NEXT: srli a0, a0, 1
; RV32IMZBS-NEXT: and a3, a3, a2
; RV32IMZBS-NEXT: and a0, a0, a2
@@ -17979,42 +17979,42 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: sw a1, 720(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui s2, 349525
; RV32I-NEXT: addi s2, s2, 1365
-; RV32I-NEXT: srli a1, a6, 1
-; RV32I-NEXT: and a3, a6, s2
-; RV32I-NEXT: and a1, a1, s2
-; RV32I-NEXT: slli a3, a3, 1
-; RV32I-NEXT: or a1, a1, a3
+; RV32I-NEXT: srli a3, a6, 1
+; RV32I-NEXT: and a1, a6, s2
+; RV32I-NEXT: slli a1, a1, 1
+; RV32I-NEXT: and a6, a3, s2
+; RV32I-NEXT: or a1, a6, a1
; RV32I-NEXT: xor a0, t0, a0
; RV32I-NEXT: sw a0, 712(sp) # 4-byte Folded Spill
-; RV32I-NEXT: srli a0, s1, 1
+; RV32I-NEXT: srli a6, s1, 1
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: slli s1, s1, 1
+; RV32I-NEXT: and a0, a6, s2
; RV32I-NEXT: or a4, a0, s1
; RV32I-NEXT: xor a0, t1, a5
; RV32I-NEXT: sw a0, 708(sp) # 4-byte Folded Spill
; RV32I-NEXT: srli a0, t3, 1
-; RV32I-NEXT: and a3, t3, s2
+; RV32I-NEXT: and a5, t3, s2
; RV32I-NEXT: and a0, a0, s2
-; RV32I-NEXT: slli a3, a3, 1
-; RV32I-NEXT: or a0, a0, a3
-; RV32I-NEXT: srli a3, a3, 31
-; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: slli a5, a1, 31
-; RV32I-NEXT: and a3, a3, a5
+; RV32I-NEXT: slli a5, a5, 1
+; RV32I-NEXT: slli a3, a3, 31
+; RV32I-NEXT: or a0, a0, a5
+; RV32I-NEXT: srli a5, a5, 31
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: and a3, a5, a3
; RV32I-NEXT: sw a3, 700(sp) # 4-byte Folded Spill
; RV32I-NEXT: srli a3, s4, 1
; RV32I-NEXT: and a5, s4, s2
; RV32I-NEXT: and a3, a3, s2
; RV32I-NEXT: slli a5, a5, 1
+; RV32I-NEXT: slli a6, a6, 31
; RV32I-NEXT: or t1, a3, a5
; RV32I-NEXT: srli a5, a5, 31
; RV32I-NEXT: seqz a3, a5
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: slli a5, a4, 31
-; RV32I-NEXT: and a3, a3, a5
-; RV32I-NEXT: sw a3, 696(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a2, a3, a6
+; RV32I-NEXT: sw a2, 696(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a3, a0, 2
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: addi a3, a3, -1
@@ -23994,32 +23994,34 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32IMZBS-NEXT: xor a5, a3, a5
; RV32IMZBS-NEXT: lui a2, 349525
; RV32IMZBS-NEXT: xor a0, a0, a1
-; RV32IMZBS-NEXT: addi s5, a2, 1365
+; RV32IMZBS-NEXT: addi s6, a2, 1365
; RV32IMZBS-NEXT: xor a1, t1, t6
; RV32IMZBS-NEXT: srli t1, a6, 1
-; RV32IMZBS-NEXT: and a6, a6, s5
+; RV32IMZBS-NEXT: and a6, a6, s6
; RV32IMZBS-NEXT: xor t2, s2, s3
; RV32IMZBS-NEXT: srli t6, t3, 1
-; RV32IMZBS-NEXT: and t3, t3, s5
+; RV32IMZBS-NEXT: and t3, t3, s6
; RV32IMZBS-NEXT: xor t4, t4, t5
; RV32IMZBS-NEXT: srli t5, s1, 1
-; RV32IMZBS-NEXT: and s1, s1, s5
+; RV32IMZBS-NEXT: and s1, s1, s6
; RV32IMZBS-NEXT: xor a7, a7, t0
; RV32IMZBS-NEXT: srli t0, s4, 1
-; RV32IMZBS-NEXT: and s0, s4, s5
+; RV32IMZBS-NEXT: and s0, s4, s6
; RV32IMZBS-NEXT: xor a4, a4, a5
-; RV32IMZBS-NEXT: and a5, t1, s5
+; RV32IMZBS-NEXT: and a5, t1, s6
; RV32IMZBS-NEXT: slli a6, a6, 1
-; RV32IMZBS-NEXT: and t1, t6, s5
+; RV32IMZBS-NEXT: and t6, t6, s6
; RV32IMZBS-NEXT: slli t3, t3, 1
+; RV32IMZBS-NEXT: slli s2, t1, 31
; RV32IMZBS-NEXT: lw a2, 664(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t6, a0, a2
+; RV32IMZBS-NEXT: xor t1, a0, a2
; RV32IMZBS-NEXT: lw a0, 668(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s2, a1, a0
-; RV32IMZBS-NEXT: and t5, t5, s5
+; RV32IMZBS-NEXT: xor s3, a1, a0
+; RV32IMZBS-NEXT: and s4, t5, s6
; RV32IMZBS-NEXT: slli s1, s1, 1
-; RV32IMZBS-NEXT: and s3, t0, s5
+; RV32IMZBS-NEXT: and s5, t0, s6
; RV32IMZBS-NEXT: slli s0, s0, 1
+; RV32IMZBS-NEXT: slli t5, t5, 31
; RV32IMZBS-NEXT: lw a0, 660(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t2, t2, a0
; RV32IMZBS-NEXT: lw a0, 648(sp) # 4-byte Folded Reload
@@ -24031,12 +24033,12 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32IMZBS-NEXT: xor a0, a4, a0
; RV32IMZBS-NEXT: sw a0, 704(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: or a0, a5, a6
-; RV32IMZBS-NEXT: or a1, t1, t3
+; RV32IMZBS-NEXT: or a1, t6, t3
; RV32IMZBS-NEXT: srli a4, t3, 31
-; RV32IMZBS-NEXT: xor a2, s2, t6
+; RV32IMZBS-NEXT: xor a2, s3, t1
; RV32IMZBS-NEXT: sw a2, 696(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: or a3, t5, s1
-; RV32IMZBS-NEXT: or t1, s3, s0
+; RV32IMZBS-NEXT: or a3, s4, s1
+; RV32IMZBS-NEXT: or t1, s5, s0
; RV32IMZBS-NEXT: srli s0, s0, 31
; RV32IMZBS-NEXT: xor a2, t4, t2
; RV32IMZBS-NEXT: sw a2, 692(sp) # 4-byte Folded Spill
@@ -24046,21 +24048,19 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32IMZBS-NEXT: andi t2, a1, 4
; RV32IMZBS-NEXT: slli t3, a0, 3
; RV32IMZBS-NEXT: andi t4, a1, 8
-; RV32IMZBS-NEXT: slli t5, a0, 4
-; RV32IMZBS-NEXT: andi t6, a1, 16
-; RV32IMZBS-NEXT: slli s1, a0, 5
-; RV32IMZBS-NEXT: andi s2, a1, 32
-; RV32IMZBS-NEXT: slli s3, a0, 31
+; RV32IMZBS-NEXT: slli t6, a0, 4
+; RV32IMZBS-NEXT: andi s1, a1, 16
+; RV32IMZBS-NEXT: slli s3, a0, 5
; RV32IMZBS-NEXT: seqz a4, a4
; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: and a2, a4, s3
+; RV32IMZBS-NEXT: and a2, a4, s2
; RV32IMZBS-NEXT: sw a2, 680(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a3, 31
+; RV32IMZBS-NEXT: andi a4, a1, 32
; RV32IMZBS-NEXT: seqz s0, s0
; RV32IMZBS-NEXT: addi s0, s0, -1
-; RV32IMZBS-NEXT: and a4, s0, a4
-; RV32IMZBS-NEXT: sw a4, 688(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a0, 6
+; RV32IMZBS-NEXT: and a2, s0, t5
+; RV32IMZBS-NEXT: sw a2, 688(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli t5, a0, 6
; RV32IMZBS-NEXT: seqz a6, a6
; RV32IMZBS-NEXT: addi a6, a6, -1
; RV32IMZBS-NEXT: and a2, a6, a5
@@ -24076,61 +24076,60 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32IMZBS-NEXT: and a2, a7, t3
; RV32IMZBS-NEXT: sw a2, 660(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a7, a1, 128
-; RV32IMZBS-NEXT: seqz t2, t6
+; RV32IMZBS-NEXT: seqz t2, s1
; RV32IMZBS-NEXT: addi t2, t2, -1
-; RV32IMZBS-NEXT: and a2, t2, t5
+; RV32IMZBS-NEXT: and a2, t2, t6
; RV32IMZBS-NEXT: sw a2, 656(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: slli t2, a0, 8
-; RV32IMZBS-NEXT: seqz t3, s2
-; RV32IMZBS-NEXT: addi t3, t3, -1
-; RV32IMZBS-NEXT: and a2, t3, s1
+; RV32IMZBS-NEXT: seqz a4, a4
+; RV32IMZBS-NEXT: addi a4, a4, -1
+; RV32IMZBS-NEXT: and a2, a4, s3
; RV32IMZBS-NEXT: sw a2, 652(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi t3, a1, 256
+; RV32IMZBS-NEXT: andi a4, a1, 256
; RV32IMZBS-NEXT: seqz a5, a5
; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: and a4, a5, a4
-; RV32IMZBS-NEXT: sw a4, 668(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a0, 9
-; RV32IMZBS-NEXT: seqz a5, a7
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: and a2, a5, a6
-; RV32IMZBS-NEXT: sw a2, 640(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a5, a1, 512
-; RV32IMZBS-NEXT: seqz a6, t3
+; RV32IMZBS-NEXT: and a2, a5, t5
+; RV32IMZBS-NEXT: sw a2, 668(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a5, a0, 9
+; RV32IMZBS-NEXT: seqz a7, a7
+; RV32IMZBS-NEXT: addi a7, a7, -1
+; RV32IMZBS-NEXT: and a7, a7, a6
+; RV32IMZBS-NEXT: andi a6, a1, 512
+; RV32IMZBS-NEXT: seqz a4, a4
+; RV32IMZBS-NEXT: addi a4, a4, -1
+; RV32IMZBS-NEXT: and a2, a4, t2
+; RV32IMZBS-NEXT: sw a2, 636(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, a0, 10
+; RV32IMZBS-NEXT: seqz a6, a6
; RV32IMZBS-NEXT: addi a6, a6, -1
-; RV32IMZBS-NEXT: and a2, a6, t2
-; RV32IMZBS-NEXT: sw a2, 632(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, a0, 10
+; RV32IMZBS-NEXT: and a2, a6, a5
+; RV32IMZBS-NEXT: sw a2, 648(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a5, a1, 1024
; RV32IMZBS-NEXT: seqz a5, a5
; RV32IMZBS-NEXT: addi a5, a5, -1
; RV32IMZBS-NEXT: and a4, a5, a4
-; RV32IMZBS-NEXT: sw a4, 648(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a4, a1, 1024
-; RV32IMZBS-NEXT: seqz a4, a4
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: and a2, a4, a6
-; RV32IMZBS-NEXT: sw a2, 664(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a4, 664(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: not a5, a1
; RV32IMZBS-NEXT: bexti a4, a5, 11
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: slli a6, a0, 11
; RV32IMZBS-NEXT: and a2, a4, a6
-; RV32IMZBS-NEXT: sw a2, 616(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 620(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a4, a5, 12
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: slli a6, a0, 12
; RV32IMZBS-NEXT: and a2, a4, a6
-; RV32IMZBS-NEXT: sw a2, 608(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 612(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a4, a5, 13
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: slli a6, a0, 13
; RV32IMZBS-NEXT: and a2, a4, a6
-; RV32IMZBS-NEXT: sw a2, 628(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 632(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a4, a5, 14
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: slli a6, a0, 14
; RV32IMZBS-NEXT: and a2, a4, a6
-; RV32IMZBS-NEXT: sw a2, 636(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 640(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a4, a5, 15
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: slli a6, a0, 15
@@ -24140,223 +24139,223 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: slli a6, a0, 16
; RV32IMZBS-NEXT: and a2, a4, a6
-; RV32IMZBS-NEXT: sw a2, 592(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 596(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a4, a5, 17
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: slli a6, a0, 17
; RV32IMZBS-NEXT: and a2, a4, a6
-; RV32IMZBS-NEXT: sw a2, 584(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 588(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a4, a5, 18
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: slli a6, a0, 18
; RV32IMZBS-NEXT: and a2, a4, a6
-; RV32IMZBS-NEXT: sw a2, 604(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 608(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a4, a5, 19
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: slli a6, a0, 19
; RV32IMZBS-NEXT: and a2, a4, a6
-; RV32IMZBS-NEXT: sw a2, 612(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 616(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a4, a5, 20
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: slli a6, a0, 20
; RV32IMZBS-NEXT: and a2, a4, a6
-; RV32IMZBS-NEXT: sw a2, 620(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 624(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a4, a5, 21
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: slli a6, a0, 21
; RV32IMZBS-NEXT: and a2, a4, a6
-; RV32IMZBS-NEXT: sw a2, 624(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 628(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a4, a5, 22
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: slli a6, a0, 22
; RV32IMZBS-NEXT: and a2, a4, a6
-; RV32IMZBS-NEXT: sw a2, 572(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 576(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a4, a5, 23
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: slli a6, a0, 23
; RV32IMZBS-NEXT: and a2, a4, a6
-; RV32IMZBS-NEXT: sw a2, 568(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 572(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a4, a5, 24
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: slli a6, a0, 24
; RV32IMZBS-NEXT: and a2, a4, a6
-; RV32IMZBS-NEXT: sw a2, 576(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 580(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a4, a5, 25
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: slli a6, a0, 25
; RV32IMZBS-NEXT: and a2, a4, a6
-; RV32IMZBS-NEXT: sw a2, 580(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 584(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a4, a5, 26
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: slli a6, a0, 26
; RV32IMZBS-NEXT: and a2, a4, a6
-; RV32IMZBS-NEXT: sw a2, 588(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 592(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a4, a5, 27
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: slli a6, a0, 27
; RV32IMZBS-NEXT: and a2, a4, a6
-; RV32IMZBS-NEXT: sw a2, 596(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 600(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a4, a5, 28
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: slli a6, a0, 28
; RV32IMZBS-NEXT: and a2, a4, a6
-; RV32IMZBS-NEXT: sw a2, 600(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 604(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a4, a5, 29
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: slli a6, a0, 29
; RV32IMZBS-NEXT: and a2, a4, a6
-; RV32IMZBS-NEXT: sw a2, 564(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 568(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a1, a1, 1
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: and a1, a1, a0
-; RV32IMZBS-NEXT: sw a1, 556(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 560(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: slli a0, a0, 30
; RV32IMZBS-NEXT: bexti a1, a5, 30
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: and a0, a1, a0
-; RV32IMZBS-NEXT: sw a0, 560(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 564(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, t1, 2
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: slli a1, a3, 1
; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: sw a0, 552(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 556(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, t1, 4
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: slli a1, a3, 2
; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: sw a0, 548(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 552(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, t1, 8
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: slli a1, a3, 3
; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: sw a0, 544(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 548(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, t1, 16
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: slli a1, a3, 4
; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: sw a0, 536(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 540(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, t1, 32
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: slli a1, a3, 5
; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: sw a0, 528(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 532(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, t1, 64
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: slli a1, a3, 6
; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: sw a0, 540(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 544(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, t1, 128
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: slli a1, a3, 7
; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: sw a0, 520(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 524(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, t1, 256
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: slli a1, a3, 8
; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: sw a0, 512(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 516(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, t1, 512
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: slli a1, a3, 9
; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: sw a0, 524(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 528(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, t1, 1024
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
-; RV32IMZBS-NEXT: slli a1, a3, 10
-; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: sw a0, 532(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, a3, 10
+; RV32IMZBS-NEXT: and a0, a0, a4
+; RV32IMZBS-NEXT: sw a0, 536(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: not a0, t1
; RV32IMZBS-NEXT: bexti a1, a0, 11
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a4, a3, 11
-; RV32IMZBS-NEXT: and a1, a1, a4
-; RV32IMZBS-NEXT: sw a1, 500(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a5, a3, 11
+; RV32IMZBS-NEXT: and a1, a1, a5
+; RV32IMZBS-NEXT: sw a1, 504(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 12
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: slli s0, a3, 12
; RV32IMZBS-NEXT: and a1, a1, s0
-; RV32IMZBS-NEXT: sw a1, 488(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 492(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 13
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a4, a3, 13
-; RV32IMZBS-NEXT: and a1, a1, a4
-; RV32IMZBS-NEXT: sw a1, 504(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a5, a3, 13
+; RV32IMZBS-NEXT: and a1, a1, a5
+; RV32IMZBS-NEXT: sw a1, 508(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 14
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a4, a3, 14
-; RV32IMZBS-NEXT: and a1, a1, a4
-; RV32IMZBS-NEXT: sw a1, 508(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a5, a3, 14
+; RV32IMZBS-NEXT: and a1, a1, a5
+; RV32IMZBS-NEXT: sw a1, 512(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 15
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a4, a3, 15
-; RV32IMZBS-NEXT: and a1, a1, a4
-; RV32IMZBS-NEXT: sw a1, 516(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a5, a3, 15
+; RV32IMZBS-NEXT: and a1, a1, a5
+; RV32IMZBS-NEXT: sw a1, 520(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 16
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a4, a3, 16
-; RV32IMZBS-NEXT: and s9, a1, a4
+; RV32IMZBS-NEXT: slli a5, a3, 16
+; RV32IMZBS-NEXT: and s7, a1, a5
; RV32IMZBS-NEXT: bexti a1, a0, 17
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a4, a3, 17
-; RV32IMZBS-NEXT: and s6, a1, a4
+; RV32IMZBS-NEXT: slli a5, a3, 17
+; RV32IMZBS-NEXT: and s5, a1, a5
; RV32IMZBS-NEXT: bexti a1, a0, 18
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a4, a3, 18
-; RV32IMZBS-NEXT: and s10, a1, a4
+; RV32IMZBS-NEXT: slli a5, a3, 18
+; RV32IMZBS-NEXT: and s9, a1, a5
; RV32IMZBS-NEXT: bexti a1, a0, 19
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a4, a3, 19
-; RV32IMZBS-NEXT: and a1, a1, a4
-; RV32IMZBS-NEXT: sw a1, 484(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a5, a3, 19
+; RV32IMZBS-NEXT: and a1, a1, a5
+; RV32IMZBS-NEXT: sw a1, 488(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 20
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: slli s1, a3, 20
; RV32IMZBS-NEXT: and a1, a1, s1
-; RV32IMZBS-NEXT: sw a1, 492(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 496(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 21
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a4, a3, 21
-; RV32IMZBS-NEXT: and a1, a1, a4
-; RV32IMZBS-NEXT: sw a1, 496(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a5, a3, 21
+; RV32IMZBS-NEXT: and a1, a1, a5
+; RV32IMZBS-NEXT: sw a1, 500(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 22
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a4, a3, 22
-; RV32IMZBS-NEXT: and s0, a1, a4
+; RV32IMZBS-NEXT: slli a5, a3, 22
+; RV32IMZBS-NEXT: and s11, a1, a5
; RV32IMZBS-NEXT: bexti a1, a0, 23
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: slli a5, a3, 23
; RV32IMZBS-NEXT: and t6, a1, a5
-; RV32IMZBS-NEXT: bexti a5, a0, 24
+; RV32IMZBS-NEXT: bexti a4, a0, 24
+; RV32IMZBS-NEXT: addi a4, a4, -1
+; RV32IMZBS-NEXT: slli a5, a3, 24
+; RV32IMZBS-NEXT: and s0, a4, a5
+; RV32IMZBS-NEXT: bexti a5, a0, 25
; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, a3, 24
+; RV32IMZBS-NEXT: slli a6, a3, 25
; RV32IMZBS-NEXT: and s1, a5, a6
-; RV32IMZBS-NEXT: bexti a6, a0, 25
+; RV32IMZBS-NEXT: bexti a6, a0, 26
; RV32IMZBS-NEXT: addi a6, a6, -1
-; RV32IMZBS-NEXT: slli a7, a3, 25
-; RV32IMZBS-NEXT: and s2, a6, a7
-; RV32IMZBS-NEXT: bexti a7, a0, 26
-; RV32IMZBS-NEXT: addi a7, a7, -1
; RV32IMZBS-NEXT: slli t2, a3, 26
-; RV32IMZBS-NEXT: and s3, a7, t2
+; RV32IMZBS-NEXT: and s2, a6, t2
; RV32IMZBS-NEXT: bexti t2, a0, 27
; RV32IMZBS-NEXT: addi t2, t2, -1
; RV32IMZBS-NEXT: slli t3, a3, 27
-; RV32IMZBS-NEXT: and s7, t2, t3
+; RV32IMZBS-NEXT: and s4, t2, t3
; RV32IMZBS-NEXT: bexti t3, a0, 28
; RV32IMZBS-NEXT: addi t3, t3, -1
; RV32IMZBS-NEXT: slli t0, a3, 28
-; RV32IMZBS-NEXT: and s4, t3, t0
+; RV32IMZBS-NEXT: and s3, t3, t0
; RV32IMZBS-NEXT: bexti t0, a0, 29
; RV32IMZBS-NEXT: addi t0, t0, -1
; RV32IMZBS-NEXT: slli a2, a3, 29
@@ -24370,7 +24369,7 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: and t4, a0, a3
; RV32IMZBS-NEXT: lw a0, 676(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 556(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 560(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t3, a1, a0
; RV32IMZBS-NEXT: lw a0, 672(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a1, 660(sp) # 4-byte Folded Reload
@@ -24378,106 +24377,105 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32IMZBS-NEXT: lw a0, 656(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a1, 652(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a6, a0, a1
-; RV32IMZBS-NEXT: lw a0, 640(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 632(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a7, a0, a1
-; RV32IMZBS-NEXT: lw a0, 616(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 608(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 636(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a7, a7, a0
+; RV32IMZBS-NEXT: lw a0, 620(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 612(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t2, a0, a1
-; RV32IMZBS-NEXT: lw a0, 592(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a3, 584(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 596(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a3, 588(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a3, a0, a3
-; RV32IMZBS-NEXT: lw a0, 572(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a4, 568(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 576(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a4, 572(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a4, a0, a4
-; RV32IMZBS-NEXT: lw a0, 564(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a5, 560(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 568(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a5, 564(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a5, a0, a5
-; RV32IMZBS-NEXT: lw a0, 552(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 556(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, t0, a0
-; RV32IMZBS-NEXT: lw a0, 548(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 544(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 552(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 548(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a0, a1
-; RV32IMZBS-NEXT: lw a1, 536(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 528(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 540(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 532(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: lw a2, 520(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw ra, 512(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 524(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw ra, 516(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a2, a2, ra
-; RV32IMZBS-NEXT: lw ra, 500(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s11, 488(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor ra, ra, s11
-; RV32IMZBS-NEXT: xor s6, s9, s6
-; RV32IMZBS-NEXT: xor t6, s0, t6
+; RV32IMZBS-NEXT: lw ra, 504(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s10, 492(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor ra, ra, s10
+; RV32IMZBS-NEXT: xor s5, s7, s5
+; RV32IMZBS-NEXT: xor t6, s11, t6
; RV32IMZBS-NEXT: xor t4, t5, t4
; RV32IMZBS-NEXT: xor t1, t3, t1
; RV32IMZBS-NEXT: lw t3, 668(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a6, a6, t3
; RV32IMZBS-NEXT: lw t3, 648(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a7, a7, t3
-; RV32IMZBS-NEXT: lw t3, 628(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t3, 632(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t2, t2, t3
-; RV32IMZBS-NEXT: lw t3, 604(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t3, 608(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a3, a3, t3
-; RV32IMZBS-NEXT: lw t3, 576(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t3, 580(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a4, a4, t3
; RV32IMZBS-NEXT: lw t3, 680(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a5, a5, t3
; RV32IMZBS-NEXT: xor a0, t0, a0
-; RV32IMZBS-NEXT: lw t0, 540(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t0, 544(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, t0
-; RV32IMZBS-NEXT: lw t0, 524(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t0, 528(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a2, a2, t0
-; RV32IMZBS-NEXT: lw t0, 504(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t0, 508(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, ra, t0
-; RV32IMZBS-NEXT: xor t3, s6, s10
-; RV32IMZBS-NEXT: xor t5, t6, s1
+; RV32IMZBS-NEXT: xor t3, s5, s9
+; RV32IMZBS-NEXT: xor t5, t6, s0
; RV32IMZBS-NEXT: lw t6, 688(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t4, t4, t6
; RV32IMZBS-NEXT: xor a6, t1, a6
; RV32IMZBS-NEXT: lw t1, 664(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a7, a7, t1
-; RV32IMZBS-NEXT: lw t1, 636(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t1, 640(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t1, t2, t1
-; RV32IMZBS-NEXT: lw t2, 612(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t2, 616(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a3, a3, t2
-; RV32IMZBS-NEXT: lw t2, 580(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t2, 584(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a4, a4, t2
; RV32IMZBS-NEXT: xor a0, a0, a1
-; RV32IMZBS-NEXT: lw a1, 532(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 536(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a2, a1
-; RV32IMZBS-NEXT: lw a2, 508(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 512(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a2, t0, a2
-; RV32IMZBS-NEXT: lw t0, 484(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t0, 488(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, t3, t0
-; RV32IMZBS-NEXT: xor t2, t5, s2
+; RV32IMZBS-NEXT: xor t2, t5, s1
; RV32IMZBS-NEXT: xor a6, a6, a7
; RV32IMZBS-NEXT: lw a7, 644(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a7, t1, a7
-; RV32IMZBS-NEXT: lw t1, 620(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t1, 624(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a3, a3, t1
-; RV32IMZBS-NEXT: lw t1, 588(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t1, 592(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a4, a4, t1
; RV32IMZBS-NEXT: xor a0, a0, a1
-; RV32IMZBS-NEXT: lw a1, 516(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 520(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a2, a1
-; RV32IMZBS-NEXT: lw a2, 492(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 496(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a2, t0, a2
-; RV32IMZBS-NEXT: xor t0, t2, s3
+; RV32IMZBS-NEXT: xor t0, t2, s2
; RV32IMZBS-NEXT: xor a6, a6, a7
-; RV32IMZBS-NEXT: lw a7, 624(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a7, 628(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a3, a3, a7
-; RV32IMZBS-NEXT: lw a7, 596(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a7, 600(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a4, a4, a7
; RV32IMZBS-NEXT: xor a0, a0, a1
-; RV32IMZBS-NEXT: lw a1, 496(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 500(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a2, a1
-; RV32IMZBS-NEXT: xor a2, t0, s7
+; RV32IMZBS-NEXT: xor a2, t0, s4
; RV32IMZBS-NEXT: xor a3, a6, a3
-; RV32IMZBS-NEXT: lw a6, 600(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a6, 604(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a4, a4, a6
; RV32IMZBS-NEXT: xor a0, a0, a1
-; RV32IMZBS-NEXT: xor a1, a2, s4
+; RV32IMZBS-NEXT: xor a1, a2, s3
; RV32IMZBS-NEXT: xor a3, a3, a4
; RV32IMZBS-NEXT: xor a0, a0, a1
; RV32IMZBS-NEXT: xor a3, a3, a5
@@ -24525,8 +24523,8 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32IMZBS-NEXT: slli a0, a0, 2
; RV32IMZBS-NEXT: or a0, a3, a0
; RV32IMZBS-NEXT: srli a3, a1, 1
-; RV32IMZBS-NEXT: and a1, a1, s5
-; RV32IMZBS-NEXT: and a4, a0, s5
+; RV32IMZBS-NEXT: and a1, a1, s6
+; RV32IMZBS-NEXT: and a4, a0, s6
; RV32IMZBS-NEXT: srli a0, a0, 1
; RV32IMZBS-NEXT: and a3, a3, a2
; RV32IMZBS-NEXT: and a0, a0, a2
diff --git a/llvm/test/CodeGen/RISCV/clmulh.ll b/llvm/test/CodeGen/RISCV/clmulh.ll
index 154db64ec555b..d78c748fa36b1 100644
--- a/llvm/test/CodeGen/RISCV/clmulh.ll
+++ b/llvm/test/CodeGen/RISCV/clmulh.ll
@@ -787,32 +787,32 @@ define i32 @clmulh_i32(i32 %a, i32 %b) nounwind {
; RV32I-NEXT: sw s10, 64(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s11, 60(sp) # 4-byte Folded Spill
; RV32I-NEXT: srli s0, a0, 8
-; RV32I-NEXT: lui t5, 16
+; RV32I-NEXT: lui a3, 16
; RV32I-NEXT: srli s1, a0, 24
; RV32I-NEXT: slli s2, a0, 24
; RV32I-NEXT: lui a4, 61681
; RV32I-NEXT: lui a5, 209715
-; RV32I-NEXT: lui a2, 349525
+; RV32I-NEXT: lui s3, 349525
; RV32I-NEXT: srli s6, a1, 8
; RV32I-NEXT: srli s4, a1, 24
; RV32I-NEXT: slli s5, a1, 24
; RV32I-NEXT: li a7, 1
; RV32I-NEXT: lui ra, 1
-; RV32I-NEXT: lui a3, 2
-; RV32I-NEXT: lui t2, 4
+; RV32I-NEXT: lui a2, 2
+; RV32I-NEXT: lui a6, 4
; RV32I-NEXT: lui t0, 8
-; RV32I-NEXT: lui t1, 32
-; RV32I-NEXT: lui a6, 64
+; RV32I-NEXT: lui t3, 32
+; RV32I-NEXT: lui t5, 64
; RV32I-NEXT: lui t6, 128
-; RV32I-NEXT: addi t3, t5, -256
-; RV32I-NEXT: addi t4, a4, -241
-; RV32I-NEXT: addi s3, a5, 819
-; RV32I-NEXT: addi s11, a2, 1365
-; RV32I-NEXT: slli a2, a7, 11
-; RV32I-NEXT: and a4, s0, t3
-; RV32I-NEXT: and a0, a0, t3
-; RV32I-NEXT: and a5, s6, t3
-; RV32I-NEXT: and a1, a1, t3
+; RV32I-NEXT: addi t1, a3, -256
+; RV32I-NEXT: addi t2, a4, -241
+; RV32I-NEXT: addi t4, a5, 819
+; RV32I-NEXT: addi s11, s3, 1365
+; RV32I-NEXT: slli a7, a7, 11
+; RV32I-NEXT: and a4, s0, t1
+; RV32I-NEXT: and a0, a0, t1
+; RV32I-NEXT: and a5, s6, t1
+; RV32I-NEXT: and a1, a1, t1
; RV32I-NEXT: or a4, a4, s1
; RV32I-NEXT: slli a0, a0, 8
; RV32I-NEXT: or a5, a5, s4
@@ -822,222 +822,222 @@ define i32 @clmulh_i32(i32 %a, i32 %b) nounwind {
; RV32I-NEXT: or a0, a0, a4
; RV32I-NEXT: or a1, a1, a5
; RV32I-NEXT: srli a4, a0, 4
-; RV32I-NEXT: and a0, a0, t4
+; RV32I-NEXT: and a0, a0, t2
; RV32I-NEXT: srli a5, a1, 4
-; RV32I-NEXT: and a1, a1, t4
-; RV32I-NEXT: and a4, a4, t4
+; RV32I-NEXT: and a1, a1, t2
+; RV32I-NEXT: and a4, a4, t2
; RV32I-NEXT: slli a0, a0, 4
-; RV32I-NEXT: and a5, a5, t4
+; RV32I-NEXT: and a5, a5, t2
; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: srli a4, a0, 2
-; RV32I-NEXT: and a0, a0, s3
+; RV32I-NEXT: and a0, a0, t4
; RV32I-NEXT: srli a5, a1, 2
-; RV32I-NEXT: and a1, a1, s3
-; RV32I-NEXT: and a4, a4, s3
+; RV32I-NEXT: and a1, a1, t4
+; RV32I-NEXT: and a4, a4, t4
; RV32I-NEXT: slli a0, a0, 2
-; RV32I-NEXT: and a5, a5, s3
+; RV32I-NEXT: and a5, a5, t4
; RV32I-NEXT: slli a1, a1, 2
-; RV32I-NEXT: or a0, a4, a0
+; RV32I-NEXT: or a4, a4, a0
; RV32I-NEXT: or a1, a5, a1
-; RV32I-NEXT: srli a4, a0, 1
-; RV32I-NEXT: and a0, a0, s11
-; RV32I-NEXT: srli a5, a1, 1
-; RV32I-NEXT: and s0, a1, s11
-; RV32I-NEXT: and a1, a4, s11
-; RV32I-NEXT: slli a0, a0, 1
-; RV32I-NEXT: and a4, a5, s11
+; RV32I-NEXT: srli a0, a4, 1
+; RV32I-NEXT: and s0, a4, s11
+; RV32I-NEXT: srli a4, a1, 1
+; RV32I-NEXT: and s2, a1, s11
+; RV32I-NEXT: and a1, a0, s11
; RV32I-NEXT: slli s0, s0, 1
-; RV32I-NEXT: or s4, a1, a0
-; RV32I-NEXT: or a7, a4, s0
-; RV32I-NEXT: srli s0, s0, 31
-; RV32I-NEXT: slli a4, s4, 1
-; RV32I-NEXT: andi a5, a7, 2
-; RV32I-NEXT: slli s1, s4, 2
-; RV32I-NEXT: andi s2, a7, 4
-; RV32I-NEXT: slli a0, s4, 3
-; RV32I-NEXT: andi s5, a7, 8
-; RV32I-NEXT: slli s6, s4, 4
-; RV32I-NEXT: andi s7, a7, 16
-; RV32I-NEXT: slli s8, s4, 5
-; RV32I-NEXT: andi s9, a7, 32
-; RV32I-NEXT: slli s10, s4, 31
-; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: and a1, s0, s10
-; RV32I-NEXT: sw a1, 56(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s0, s4, 6
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: and a4, a5, a4
+; RV32I-NEXT: and s1, a4, s11
+; RV32I-NEXT: slli s2, s2, 1
+; RV32I-NEXT: slli a0, a0, 31
+; RV32I-NEXT: or s7, a1, s0
+; RV32I-NEXT: or s0, s1, s2
+; RV32I-NEXT: srli a4, s2, 31
+; RV32I-NEXT: slli a5, s7, 1
+; RV32I-NEXT: andi s1, s0, 2
+; RV32I-NEXT: slli s2, s7, 2
+; RV32I-NEXT: andi s4, s0, 4
+; RV32I-NEXT: slli a1, s7, 3
+; RV32I-NEXT: andi s6, s0, 8
+; RV32I-NEXT: slli s5, s7, 4
+; RV32I-NEXT: andi s8, s0, 16
+; RV32I-NEXT: slli s9, s7, 5
+; RV32I-NEXT: andi s10, s0, 32
+; RV32I-NEXT: seqz a4, a4
+; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a0, a4, a0
+; RV32I-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a0, s7, 6
+; RV32I-NEXT: seqz a4, s1
+; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: sw a4, 52(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a7, 64
-; RV32I-NEXT: seqz a5, s2
+; RV32I-NEXT: andi a4, s0, 64
+; RV32I-NEXT: seqz a5, s4
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: and a5, a5, s1
+; RV32I-NEXT: and a5, a5, s2
; RV32I-NEXT: sw a5, 48(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, s4, 7
-; RV32I-NEXT: seqz s1, s5
+; RV32I-NEXT: slli a5, s7, 7
+; RV32I-NEXT: seqz s1, s6
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: and a0, s1, a0
-; RV32I-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi s1, a7, 128
-; RV32I-NEXT: seqz s2, s7
+; RV32I-NEXT: and a1, s1, a1
+; RV32I-NEXT: sw a1, 44(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi s1, s0, 128
+; RV32I-NEXT: seqz s2, s8
; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: and a0, s2, s6
-; RV32I-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s2, s4, 8
-; RV32I-NEXT: seqz s6, s9
-; RV32I-NEXT: addi s6, s6, -1
-; RV32I-NEXT: and a0, s6, s8
-; RV32I-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi s8, a7, 256
+; RV32I-NEXT: and a1, s2, s5
+; RV32I-NEXT: sw a1, 40(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s2, s7, 8
+; RV32I-NEXT: seqz s4, s10
+; RV32I-NEXT: addi s4, s4, -1
+; RV32I-NEXT: and a1, s4, s9
+; RV32I-NEXT: sw a1, 32(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi s4, s0, 256
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: and a4, a4, s0
-; RV32I-NEXT: sw a4, 36(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, s4, 9
-; RV32I-NEXT: seqz s0, s1
-; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: and a5, s0, a5
-; RV32I-NEXT: sw a5, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a5, a7, 512
-; RV32I-NEXT: seqz s0, s8
-; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: and a0, s0, s2
-; RV32I-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s0, s4, 10
-; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: and a0, a4, a0
+; RV32I-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a0, s7, 9
+; RV32I-NEXT: seqz a4, s1
+; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a4, a4, a5
+; RV32I-NEXT: sw a4, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a4, s0, 512
+; RV32I-NEXT: seqz a5, s4
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: sw a4, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a7, 1024
+; RV32I-NEXT: and a1, a5, s2
+; RV32I-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, s7, 10
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: and a4, a4, s0
-; RV32I-NEXT: sw a4, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, s4, 11
-; RV32I-NEXT: and a5, a7, a2
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: sw a4, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, s4, 12
-; RV32I-NEXT: and a5, a7, ra
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: and ra, a5, a4
-; RV32I-NEXT: slli a4, s4, 13
-; RV32I-NEXT: and a2, a7, a3
-; RV32I-NEXT: seqz a2, a2
-; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and s7, a2, a4
-; RV32I-NEXT: slli a2, s4, 14
-; RV32I-NEXT: and a4, a7, t2
+; RV32I-NEXT: and a0, a4, a0
+; RV32I-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a0, s0, 1024
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: addi a0, a0, -1
+; RV32I-NEXT: and a0, a0, a5
+; RV32I-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a0, s7, 11
+; RV32I-NEXT: and a4, s0, a7
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: and s8, a4, a2
-; RV32I-NEXT: slli a2, s4, 15
-; RV32I-NEXT: and a4, a7, t0
+; RV32I-NEXT: and a0, a4, a0
+; RV32I-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a0, s7, 12
+; RV32I-NEXT: and a4, s0, ra
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: and s6, a4, a2
-; RV32I-NEXT: slli a2, s4, 16
-; RV32I-NEXT: and a3, a7, t5
-; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: and s2, a3, a2
-; RV32I-NEXT: slli a2, s4, 17
-; RV32I-NEXT: and a3, a7, t1
-; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: and t5, a3, a2
-; RV32I-NEXT: slli a2, s4, 18
-; RV32I-NEXT: and a3, a7, a6
-; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: and s0, a3, a2
-; RV32I-NEXT: slli a2, s4, 19
-; RV32I-NEXT: and a3, a7, t6
-; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: and s1, a3, a2
-; RV32I-NEXT: lui a2, 256
-; RV32I-NEXT: and a2, a7, a2
+; RV32I-NEXT: and ra, a4, a0
+; RV32I-NEXT: slli a0, s7, 13
+; RV32I-NEXT: and a2, s0, a2
+; RV32I-NEXT: seqz a2, a2
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and s4, a2, a0
+; RV32I-NEXT: slli a0, s7, 14
+; RV32I-NEXT: and a2, s0, a6
+; RV32I-NEXT: seqz a2, a2
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and s8, a2, a0
+; RV32I-NEXT: slli a0, s7, 15
+; RV32I-NEXT: and a2, s0, t0
+; RV32I-NEXT: seqz a2, a2
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and s6, a2, a0
+; RV32I-NEXT: slli a0, s7, 16
+; RV32I-NEXT: and a3, s0, a3
+; RV32I-NEXT: seqz a2, a3
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and s2, a2, a0
+; RV32I-NEXT: slli a0, s7, 17
+; RV32I-NEXT: and a2, s0, t3
+; RV32I-NEXT: seqz a2, a2
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and t3, a2, a0
+; RV32I-NEXT: slli a0, s7, 18
+; RV32I-NEXT: and a2, s0, t5
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli a3, s4, 20
-; RV32I-NEXT: and t6, a2, a3
-; RV32I-NEXT: lui a2, 512
-; RV32I-NEXT: and a2, a7, a2
+; RV32I-NEXT: and t5, a2, a0
+; RV32I-NEXT: slli a0, s7, 19
+; RV32I-NEXT: and a2, s0, t6
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli a3, s4, 21
-; RV32I-NEXT: and s5, a2, a3
-; RV32I-NEXT: lui a2, 1024
-; RV32I-NEXT: and a2, a7, a2
+; RV32I-NEXT: and s1, a2, a0
+; RV32I-NEXT: lui a0, 256
+; RV32I-NEXT: and a0, s0, a0
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: addi a0, a0, -1
+; RV32I-NEXT: slli a2, s7, 20
+; RV32I-NEXT: and t6, a0, a2
+; RV32I-NEXT: lui a0, 512
+; RV32I-NEXT: and a0, s0, a0
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: addi a0, a0, -1
+; RV32I-NEXT: slli a2, s7, 21
+; RV32I-NEXT: and s3, a0, a2
+; RV32I-NEXT: lui a0, 1024
+; RV32I-NEXT: and a0, s0, a0
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: addi a0, a0, -1
+; RV32I-NEXT: slli a2, s7, 22
+; RV32I-NEXT: and a7, a0, a2
+; RV32I-NEXT: lui a2, 2048
+; RV32I-NEXT: and a2, s0, a2
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli a3, s4, 22
-; RV32I-NEXT: and t2, a2, a3
-; RV32I-NEXT: lui a3, 2048
-; RV32I-NEXT: and a3, a7, a3
+; RV32I-NEXT: slli a3, s7, 23
+; RV32I-NEXT: and a2, a2, a3
+; RV32I-NEXT: lui a3, 4096
+; RV32I-NEXT: and a3, s0, a3
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: slli a4, s4, 23
-; RV32I-NEXT: and t0, a3, a4
-; RV32I-NEXT: lui a4, 4096
-; RV32I-NEXT: and a4, a7, a4
+; RV32I-NEXT: slli a4, s7, 24
+; RV32I-NEXT: and a3, a3, a4
+; RV32I-NEXT: lui a4, 8192
+; RV32I-NEXT: and a4, s0, a4
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: slli a5, s4, 24
+; RV32I-NEXT: slli a5, s7, 25
; RV32I-NEXT: and a4, a4, a5
-; RV32I-NEXT: lui a5, 8192
-; RV32I-NEXT: and a5, a7, a5
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, s4, 25
-; RV32I-NEXT: and t1, a5, a6
; RV32I-NEXT: lui a5, 16384
-; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: and a5, s0, a5
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, s4, 26
-; RV32I-NEXT: and a3, a5, a6
+; RV32I-NEXT: slli a6, s7, 26
+; RV32I-NEXT: and t0, a5, a6
; RV32I-NEXT: lui a5, 32768
-; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: and a5, s0, a5
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, s4, 27
+; RV32I-NEXT: slli a6, s7, 27
; RV32I-NEXT: and a6, a5, a6
; RV32I-NEXT: lui a5, 65536
-; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: and a5, s0, a5
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a0, s4, 28
-; RV32I-NEXT: and a5, a5, a0
-; RV32I-NEXT: lui a0, 131072
-; RV32I-NEXT: and a0, a7, a0
-; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: addi a0, a0, -1
-; RV32I-NEXT: slli a1, s4, 29
-; RV32I-NEXT: and a2, a0, a1
-; RV32I-NEXT: lui a1, 262144
-; RV32I-NEXT: and a1, a7, a1
-; RV32I-NEXT: andi a7, a7, 1
-; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: and a7, a7, s4
-; RV32I-NEXT: slli s4, s4, 30
+; RV32I-NEXT: slli a1, s7, 28
+; RV32I-NEXT: and a5, a5, a1
+; RV32I-NEXT: lui a1, 131072
+; RV32I-NEXT: and a1, s0, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: and a1, a1, s4
+; RV32I-NEXT: slli s5, s7, 29
+; RV32I-NEXT: and a1, a1, s5
+; RV32I-NEXT: lui s5, 262144
+; RV32I-NEXT: and s5, s0, s5
+; RV32I-NEXT: andi s0, s0, 1
+; RV32I-NEXT: seqz s0, s0
+; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: and s0, s0, s7
+; RV32I-NEXT: slli s7, s7, 30
+; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: and s5, s5, s7
; RV32I-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a7, a7, a0
+; RV32I-NEXT: xor s0, s0, a0
; RV32I-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s4, 44(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s4, a0, s4
+; RV32I-NEXT: lw s7, 44(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s7, a0, s7
; RV32I-NEXT: lw a0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s10, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a0, s10
@@ -1046,60 +1046,60 @@ define i32 @clmulh_i32(i32 %a, i32 %b) nounwind {
; RV32I-NEXT: xor s10, s10, s9
; RV32I-NEXT: lw s9, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s9, s9, ra
-; RV32I-NEXT: xor t5, s2, t5
-; RV32I-NEXT: xor t0, t2, t0
-; RV32I-NEXT: xor a1, a2, a1
-; RV32I-NEXT: xor a2, a7, s4
-; RV32I-NEXT: lw a7, 36(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a7
-; RV32I-NEXT: lw a7, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a7, s10, a7
-; RV32I-NEXT: xor t2, s9, s7
-; RV32I-NEXT: xor t5, t5, s0
-; RV32I-NEXT: xor a4, t0, a4
-; RV32I-NEXT: lw t0, 56(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a1, a1, t0
-; RV32I-NEXT: xor a0, a2, a0
-; RV32I-NEXT: lw a2, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t3, s2, t3
; RV32I-NEXT: xor a2, a7, a2
-; RV32I-NEXT: xor a7, t2, s8
-; RV32I-NEXT: xor t0, t5, s1
-; RV32I-NEXT: xor a4, a4, t1
-; RV32I-NEXT: xor a0, a0, a2
-; RV32I-NEXT: xor a2, a7, s6
-; RV32I-NEXT: xor a7, t0, t6
-; RV32I-NEXT: xor a3, a4, a3
-; RV32I-NEXT: lui a4, 349525
-; RV32I-NEXT: addi a4, a4, 1364
-; RV32I-NEXT: xor a0, a0, a2
-; RV32I-NEXT: xor a2, a7, s5
-; RV32I-NEXT: xor a3, a3, a6
-; RV32I-NEXT: xor a0, a0, a2
-; RV32I-NEXT: xor a3, a3, a5
+; RV32I-NEXT: xor a1, a1, s5
+; RV32I-NEXT: xor a7, s0, s7
+; RV32I-NEXT: lw s0, 36(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a0, a0, s0
+; RV32I-NEXT: lw s0, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s0, s10, s0
+; RV32I-NEXT: xor s2, s9, s4
+; RV32I-NEXT: xor t3, t3, t5
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: lw a3, 56(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a3
+; RV32I-NEXT: xor a0, a7, a0
+; RV32I-NEXT: lw a3, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a3, s0, a3
+; RV32I-NEXT: xor a7, s2, s8
+; RV32I-NEXT: xor t3, t3, s1
+; RV32I-NEXT: xor a2, a2, a4
+; RV32I-NEXT: xor a0, a0, a3
+; RV32I-NEXT: xor a3, a7, s6
+; RV32I-NEXT: xor a4, t3, t6
+; RV32I-NEXT: lui a7, 349525
+; RV32I-NEXT: addi a7, a7, 1364
+; RV32I-NEXT: xor a2, a2, t0
+; RV32I-NEXT: xor a0, a0, a3
+; RV32I-NEXT: xor a3, a4, s3
+; RV32I-NEXT: xor a2, a2, a6
; RV32I-NEXT: xor a0, a0, a3
+; RV32I-NEXT: xor a2, a2, a5
+; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: srli a2, a0, 24
; RV32I-NEXT: slli a3, a0, 24
-; RV32I-NEXT: and a0, a0, t3
-; RV32I-NEXT: and a1, a1, t3
+; RV32I-NEXT: and a0, a0, t1
+; RV32I-NEXT: and a1, a1, t1
; RV32I-NEXT: slli a0, a0, 8
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 4
-; RV32I-NEXT: and a0, a0, t4
-; RV32I-NEXT: and a1, a1, t4
+; RV32I-NEXT: and a0, a0, t2
+; RV32I-NEXT: and a1, a1, t2
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 2
-; RV32I-NEXT: and a0, a0, s3
-; RV32I-NEXT: and a1, a1, s3
+; RV32I-NEXT: and a0, a0, t4
+; RV32I-NEXT: and a1, a1, t4
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a0, a0, s11
-; RV32I-NEXT: and a1, a1, a4
+; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a0, a0, 1
@@ -1880,89 +1880,89 @@ define i32 @clmulh_i32(i32 %a, i32 %b) nounwind {
; RV32IMZBS-NEXT: slli a0, a0, 2
; RV32IMZBS-NEXT: and a3, a3, a7
; RV32IMZBS-NEXT: slli a1, a1, 2
-; RV32IMZBS-NEXT: or a0, a2, a0
+; RV32IMZBS-NEXT: or a2, a2, a0
; RV32IMZBS-NEXT: or a1, a3, a1
-; RV32IMZBS-NEXT: srli a2, a0, 1
+; RV32IMZBS-NEXT: srli a0, a2, 1
; RV32IMZBS-NEXT: sw a6, 28(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a0, a0, a6
+; RV32IMZBS-NEXT: and a2, a2, a6
; RV32IMZBS-NEXT: srli a3, a1, 1
-; RV32IMZBS-NEXT: and a1, a1, a6
-; RV32IMZBS-NEXT: and a4, a2, a6
-; RV32IMZBS-NEXT: slli a0, a0, 1
+; RV32IMZBS-NEXT: and t1, a1, a6
+; RV32IMZBS-NEXT: and a1, a0, a6
+; RV32IMZBS-NEXT: slli a2, a2, 1
; RV32IMZBS-NEXT: and a3, a3, a6
-; RV32IMZBS-NEXT: slli a2, a1, 1
-; RV32IMZBS-NEXT: or s2, a4, a0
-; RV32IMZBS-NEXT: or a1, a3, a2
-; RV32IMZBS-NEXT: srli a2, a2, 31
-; RV32IMZBS-NEXT: slli a3, s2, 1
-; RV32IMZBS-NEXT: andi a4, a1, 2
-; RV32IMZBS-NEXT: slli a5, s2, 2
-; RV32IMZBS-NEXT: andi t1, a1, 4
-; RV32IMZBS-NEXT: slli a0, s2, 3
-; RV32IMZBS-NEXT: andi t4, a1, 8
-; RV32IMZBS-NEXT: slli t5, s2, 4
-; RV32IMZBS-NEXT: andi t6, a1, 16
-; RV32IMZBS-NEXT: slli s0, s2, 5
-; RV32IMZBS-NEXT: andi s1, a1, 32
-; RV32IMZBS-NEXT: slli a7, s2, 6
-; RV32IMZBS-NEXT: andi s3, a1, 64
-; RV32IMZBS-NEXT: slli s4, s2, 7
-; RV32IMZBS-NEXT: andi s5, a1, 128
-; RV32IMZBS-NEXT: slli s6, s2, 8
-; RV32IMZBS-NEXT: andi s7, a1, 256
-; RV32IMZBS-NEXT: slli s8, s2, 9
-; RV32IMZBS-NEXT: andi s9, a1, 512
-; RV32IMZBS-NEXT: slli s10, s2, 10
-; RV32IMZBS-NEXT: slli t3, s2, 31
+; RV32IMZBS-NEXT: slli t1, t1, 1
+; RV32IMZBS-NEXT: slli a4, a0, 31
+; RV32IMZBS-NEXT: or t4, a1, a2
+; RV32IMZBS-NEXT: or t0, a3, t1
+; RV32IMZBS-NEXT: srli a2, t1, 31
+; RV32IMZBS-NEXT: slli a3, t4, 1
+; RV32IMZBS-NEXT: andi a5, t0, 2
+; RV32IMZBS-NEXT: slli t1, t4, 2
+; RV32IMZBS-NEXT: andi t2, t0, 4
+; RV32IMZBS-NEXT: slli a0, t4, 3
+; RV32IMZBS-NEXT: andi t5, t0, 8
+; RV32IMZBS-NEXT: slli t6, t4, 4
+; RV32IMZBS-NEXT: andi s0, t0, 16
+; RV32IMZBS-NEXT: slli s1, t4, 5
+; RV32IMZBS-NEXT: andi s2, t0, 32
+; RV32IMZBS-NEXT: slli s3, t4, 6
+; RV32IMZBS-NEXT: andi s4, t0, 64
+; RV32IMZBS-NEXT: slli s5, t4, 7
+; RV32IMZBS-NEXT: andi s6, t0, 128
+; RV32IMZBS-NEXT: slli s7, t4, 8
+; RV32IMZBS-NEXT: andi s8, t0, 256
+; RV32IMZBS-NEXT: slli s9, t4, 9
+; RV32IMZBS-NEXT: andi s10, t0, 512
+; RV32IMZBS-NEXT: slli s11, t4, 10
; RV32IMZBS-NEXT: seqz a2, a2
; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: and a2, a2, t3
+; RV32IMZBS-NEXT: and a2, a2, a4
; RV32IMZBS-NEXT: sw a2, 24(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a6, a1, 1024
-; RV32IMZBS-NEXT: seqz a4, a4
+; RV32IMZBS-NEXT: andi a6, t0, 1024
+; RV32IMZBS-NEXT: seqz a4, a5
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: and a3, a4, a3
; RV32IMZBS-NEXT: sw a3, 20(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a3, s2, 11
-; RV32IMZBS-NEXT: seqz a4, t1
+; RV32IMZBS-NEXT: slli a3, t4, 11
+; RV32IMZBS-NEXT: seqz a4, t2
; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: and a4, a4, a5
-; RV32IMZBS-NEXT: sw a4, 16(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: not t3, a1
-; RV32IMZBS-NEXT: seqz a4, t4
+; RV32IMZBS-NEXT: and a1, a4, t1
+; RV32IMZBS-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: not t3, t0
+; RV32IMZBS-NEXT: seqz a4, t5
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: and a0, a4, a0
; RV32IMZBS-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, s2, 12
-; RV32IMZBS-NEXT: seqz a5, t6
+; RV32IMZBS-NEXT: slli a4, t4, 12
+; RV32IMZBS-NEXT: seqz a5, s0
; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: and a0, a5, t5
+; RV32IMZBS-NEXT: and a0, a5, t6
; RV32IMZBS-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a5, s2, 13
-; RV32IMZBS-NEXT: seqz t5, s1
+; RV32IMZBS-NEXT: slli a5, t4, 13
+; RV32IMZBS-NEXT: seqz t5, s2
; RV32IMZBS-NEXT: addi t5, t5, -1
-; RV32IMZBS-NEXT: and t6, t5, s0
-; RV32IMZBS-NEXT: slli s11, s2, 14
-; RV32IMZBS-NEXT: seqz t5, s3
+; RV32IMZBS-NEXT: and t6, t5, s1
+; RV32IMZBS-NEXT: slli ra, t4, 14
+; RV32IMZBS-NEXT: seqz t5, s4
; RV32IMZBS-NEXT: addi t5, t5, -1
-; RV32IMZBS-NEXT: and a0, t5, a7
+; RV32IMZBS-NEXT: and a0, t5, s3
; RV32IMZBS-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli ra, s2, 15
-; RV32IMZBS-NEXT: seqz s0, s5
+; RV32IMZBS-NEXT: slli s4, t4, 15
+; RV32IMZBS-NEXT: seqz s0, s6
; RV32IMZBS-NEXT: addi s0, s0, -1
-; RV32IMZBS-NEXT: and s1, s0, s4
-; RV32IMZBS-NEXT: slli s4, s2, 16
-; RV32IMZBS-NEXT: seqz s0, s7
+; RV32IMZBS-NEXT: and s1, s0, s5
+; RV32IMZBS-NEXT: slli a2, t4, 16
+; RV32IMZBS-NEXT: seqz s0, s8
; RV32IMZBS-NEXT: addi s0, s0, -1
-; RV32IMZBS-NEXT: and s3, s0, s6
-; RV32IMZBS-NEXT: slli a2, s2, 17
-; RV32IMZBS-NEXT: seqz s0, s9
-; RV32IMZBS-NEXT: addi s0, s0, -1
-; RV32IMZBS-NEXT: and t4, s0, s8
-; RV32IMZBS-NEXT: slli s0, s2, 18
+; RV32IMZBS-NEXT: and s3, s0, s7
+; RV32IMZBS-NEXT: slli s0, t4, 17
+; RV32IMZBS-NEXT: seqz s2, s10
+; RV32IMZBS-NEXT: addi s2, s2, -1
+; RV32IMZBS-NEXT: and s2, s2, s9
+; RV32IMZBS-NEXT: slli s10, t4, 18
; RV32IMZBS-NEXT: seqz a6, a6
; RV32IMZBS-NEXT: addi a6, a6, -1
-; RV32IMZBS-NEXT: and t5, a6, s10
+; RV32IMZBS-NEXT: and t5, a6, s11
; RV32IMZBS-NEXT: bexti s5, t3, 11
; RV32IMZBS-NEXT: addi s5, s5, -1
; RV32IMZBS-NEXT: and s8, s5, a3
@@ -1974,88 +1974,88 @@ define i32 @clmulh_i32(i32 %a, i32 %b) nounwind {
; RV32IMZBS-NEXT: and s7, a3, a5
; RV32IMZBS-NEXT: bexti a3, t3, 14
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: and s6, a3, s11
+; RV32IMZBS-NEXT: and s6, a3, ra
; RV32IMZBS-NEXT: bexti a3, t3, 15
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: and s5, a3, ra
+; RV32IMZBS-NEXT: and s5, a3, s4
; RV32IMZBS-NEXT: bexti a3, t3, 16
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: and t0, a3, s4
-; RV32IMZBS-NEXT: bexti a3, t3, 17
-; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: and a6, a3, a2
+; RV32IMZBS-NEXT: and t2, a3, a2
+; RV32IMZBS-NEXT: bexti a2, t3, 17
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: and a6, a2, s0
; RV32IMZBS-NEXT: bexti a3, t3, 18
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: and ra, a3, s0
+; RV32IMZBS-NEXT: and ra, a3, s10
; RV32IMZBS-NEXT: bexti a3, t3, 19
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a5, s2, 19
+; RV32IMZBS-NEXT: slli a5, t4, 19
; RV32IMZBS-NEXT: and s10, a3, a5
; RV32IMZBS-NEXT: bexti a3, t3, 20
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a5, s2, 20
+; RV32IMZBS-NEXT: slli a5, t4, 20
; RV32IMZBS-NEXT: and s11, a3, a5
; RV32IMZBS-NEXT: bexti a3, t3, 21
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a5, s2, 21
+; RV32IMZBS-NEXT: slli a5, t4, 21
; RV32IMZBS-NEXT: and s4, a3, a5
; RV32IMZBS-NEXT: bexti a3, t3, 22
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a5, s2, 22
+; RV32IMZBS-NEXT: slli a5, t4, 22
; RV32IMZBS-NEXT: and s0, a3, a5
; RV32IMZBS-NEXT: bexti a3, t3, 23
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a5, s2, 23
+; RV32IMZBS-NEXT: slli a5, t4, 23
; RV32IMZBS-NEXT: and a3, a3, a5
; RV32IMZBS-NEXT: bexti a4, t3, 24
; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: slli a5, s2, 24
+; RV32IMZBS-NEXT: slli a5, t4, 24
; RV32IMZBS-NEXT: and a4, a4, a5
; RV32IMZBS-NEXT: bexti a5, t3, 25
; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a7, s2, 25
+; RV32IMZBS-NEXT: slli a7, t4, 25
; RV32IMZBS-NEXT: and a2, a5, a7
; RV32IMZBS-NEXT: bexti a5, t3, 26
; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a7, s2, 26
+; RV32IMZBS-NEXT: slli a7, t4, 26
; RV32IMZBS-NEXT: and a5, a5, a7
; RV32IMZBS-NEXT: bexti a7, t3, 27
; RV32IMZBS-NEXT: addi a7, a7, -1
-; RV32IMZBS-NEXT: slli t1, s2, 27
+; RV32IMZBS-NEXT: slli t1, t4, 27
; RV32IMZBS-NEXT: and t1, a7, t1
; RV32IMZBS-NEXT: bexti a7, t3, 28
; RV32IMZBS-NEXT: addi a7, a7, -1
-; RV32IMZBS-NEXT: slli a0, s2, 28
+; RV32IMZBS-NEXT: slli a0, t4, 28
; RV32IMZBS-NEXT: and a7, a7, a0
; RV32IMZBS-NEXT: bexti a0, t3, 29
; RV32IMZBS-NEXT: addi a0, a0, -1
-; RV32IMZBS-NEXT: slli t2, s2, 29
-; RV32IMZBS-NEXT: and a0, a0, t2
-; RV32IMZBS-NEXT: andi a1, a1, 1
+; RV32IMZBS-NEXT: slli a1, t4, 29
+; RV32IMZBS-NEXT: and a0, a0, a1
+; RV32IMZBS-NEXT: andi a1, t0, 1
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: and a1, a1, s2
-; RV32IMZBS-NEXT: slli s2, s2, 30
-; RV32IMZBS-NEXT: bexti t2, t3, 30
-; RV32IMZBS-NEXT: addi t2, t2, -1
-; RV32IMZBS-NEXT: and t2, t2, s2
+; RV32IMZBS-NEXT: and a1, a1, t4
+; RV32IMZBS-NEXT: slli t4, t4, 30
+; RV32IMZBS-NEXT: bexti t0, t3, 30
+; RV32IMZBS-NEXT: addi t0, t0, -1
+; RV32IMZBS-NEXT: and t0, t0, t4
; RV32IMZBS-NEXT: lw t3, 20(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, t3
; RV32IMZBS-NEXT: lw t3, 16(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s2, 12(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t3, t3, s2
-; RV32IMZBS-NEXT: lw s2, 8(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t6, s2, t6
-; RV32IMZBS-NEXT: xor s1, s1, s3
-; RV32IMZBS-NEXT: xor s2, s8, s9
-; RV32IMZBS-NEXT: xor a6, t0, a6
+; RV32IMZBS-NEXT: lw t4, 12(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor t3, t3, t4
+; RV32IMZBS-NEXT: lw t4, 8(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor t4, t4, t6
+; RV32IMZBS-NEXT: xor t6, s1, s3
+; RV32IMZBS-NEXT: xor s1, s8, s9
+; RV32IMZBS-NEXT: xor a6, t2, a6
; RV32IMZBS-NEXT: xor a3, s0, a3
-; RV32IMZBS-NEXT: xor a0, a0, t2
+; RV32IMZBS-NEXT: xor a0, a0, t0
; RV32IMZBS-NEXT: xor a1, a1, t3
; RV32IMZBS-NEXT: lw t0, 4(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t0, t6, t0
-; RV32IMZBS-NEXT: xor t2, s1, t4
-; RV32IMZBS-NEXT: xor t3, s2, s7
+; RV32IMZBS-NEXT: xor t0, t4, t0
+; RV32IMZBS-NEXT: xor t2, t6, s2
+; RV32IMZBS-NEXT: xor t3, s1, s7
; RV32IMZBS-NEXT: xor a6, a6, ra
; RV32IMZBS-NEXT: xor a3, a3, a4
; RV32IMZBS-NEXT: lw a4, 24(sp) # 4-byte Folded Reload
@@ -2069,24 +2069,24 @@ define i32 @clmulh_i32(i32 %a, i32 %b) nounwind {
; RV32IMZBS-NEXT: xor a3, t0, s5
; RV32IMZBS-NEXT: xor a4, a6, s11
; RV32IMZBS-NEXT: xor a2, a2, a5
+; RV32IMZBS-NEXT: lui a5, 349525
+; RV32IMZBS-NEXT: addi a5, a5, 1364
; RV32IMZBS-NEXT: xor a1, a1, a3
-; RV32IMZBS-NEXT: lui a3, 349525
-; RV32IMZBS-NEXT: addi a3, a3, 1364
-; RV32IMZBS-NEXT: xor a4, a4, s4
+; RV32IMZBS-NEXT: xor a3, a4, s4
; RV32IMZBS-NEXT: xor a2, a2, t1
-; RV32IMZBS-NEXT: xor a1, a1, a4
+; RV32IMZBS-NEXT: xor a1, a1, a3
; RV32IMZBS-NEXT: xor a2, a2, a7
; RV32IMZBS-NEXT: xor a1, a1, a2
; RV32IMZBS-NEXT: xor a0, a1, a0
; RV32IMZBS-NEXT: srli a1, a0, 8
; RV32IMZBS-NEXT: srli a2, a0, 24
-; RV32IMZBS-NEXT: slli a4, a0, 24
-; RV32IMZBS-NEXT: lw a5, 40(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: and a0, a0, a5
-; RV32IMZBS-NEXT: and a1, a1, a5
+; RV32IMZBS-NEXT: slli a3, a0, 24
+; RV32IMZBS-NEXT: lw a4, 40(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: and a0, a0, a4
+; RV32IMZBS-NEXT: and a1, a1, a4
; RV32IMZBS-NEXT: slli a0, a0, 8
; RV32IMZBS-NEXT: or a1, a1, a2
-; RV32IMZBS-NEXT: or a0, a4, a0
+; RV32IMZBS-NEXT: or a0, a3, a0
; RV32IMZBS-NEXT: or a0, a0, a1
; RV32IMZBS-NEXT: srli a1, a0, 4
; RV32IMZBS-NEXT: lw a2, 36(sp) # 4-byte Folded Reload
@@ -2103,7 +2103,7 @@ define i32 @clmulh_i32(i32 %a, i32 %b) nounwind {
; RV32IMZBS-NEXT: srli a1, a0, 1
; RV32IMZBS-NEXT: lw a2, 28(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: and a0, a0, a2
-; RV32IMZBS-NEXT: and a1, a1, a3
+; RV32IMZBS-NEXT: and a1, a1, a5
; RV32IMZBS-NEXT: slli a0, a0, 1
; RV32IMZBS-NEXT: or a0, a1, a0
; RV32IMZBS-NEXT: srli a0, a0, 1
@@ -2441,1288 +2441,1288 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: sw s11, 764(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a3, 752(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a2, 748(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw t0, 0(a0)
+; RV32I-NEXT: lw t3, 0(a0)
; RV32I-NEXT: lw t4, 4(a0)
-; RV32I-NEXT: lw a7, 8(a0)
-; RV32I-NEXT: lw t2, 12(a0)
+; RV32I-NEXT: lw a4, 8(a0)
+; RV32I-NEXT: lw a0, 12(a0)
; RV32I-NEXT: lw s5, 0(a1)
-; RV32I-NEXT: lw a3, 4(a1)
-; RV32I-NEXT: lw t1, 8(a1)
-; RV32I-NEXT: lw a0, 12(a1)
-; RV32I-NEXT: lui a5, 16
-; RV32I-NEXT: lui a1, 61681
-; RV32I-NEXT: lui a2, 209715
-; RV32I-NEXT: lui a4, 349525
-; RV32I-NEXT: addi s11, a5, -256
-; RV32I-NEXT: addi s10, a1, -241
-; RV32I-NEXT: addi s9, a2, 819
-; RV32I-NEXT: addi s8, a4, 1365
-; RV32I-NEXT: srli a1, a3, 8
-; RV32I-NEXT: srli t5, a3, 24
-; RV32I-NEXT: and a2, a3, s11
-; RV32I-NEXT: slli a3, a3, 24
-; RV32I-NEXT: srli a5, t4, 8
-; RV32I-NEXT: srli a6, t4, 24
-; RV32I-NEXT: and a4, t4, s11
+; RV32I-NEXT: lw a6, 4(a1)
+; RV32I-NEXT: lw a5, 8(a1)
+; RV32I-NEXT: lw a1, 12(a1)
+; RV32I-NEXT: lui t0, 16
+; RV32I-NEXT: lui a2, 61681
+; RV32I-NEXT: lui a3, 209715
+; RV32I-NEXT: lui a7, 349525
+; RV32I-NEXT: addi s11, t0, -256
+; RV32I-NEXT: addi s10, a2, -241
+; RV32I-NEXT: addi s9, a3, 819
+; RV32I-NEXT: addi s8, a7, 1365
+; RV32I-NEXT: srli a2, a6, 8
+; RV32I-NEXT: srli s6, a6, 24
+; RV32I-NEXT: and a3, a6, s11
+; RV32I-NEXT: slli a6, a6, 24
+; RV32I-NEXT: srli t0, t4, 8
+; RV32I-NEXT: srli t2, t4, 24
+; RV32I-NEXT: and a7, t4, s11
; RV32I-NEXT: slli t4, t4, 24
-; RV32I-NEXT: srli s2, s5, 8
-; RV32I-NEXT: srli t3, s5, 24
+; RV32I-NEXT: srli t1, s5, 8
+; RV32I-NEXT: srli t5, s5, 24
; RV32I-NEXT: and s3, s5, s11
; RV32I-NEXT: slli s5, s5, 24
-; RV32I-NEXT: srli t6, t0, 8
-; RV32I-NEXT: srli s1, t0, 24
-; RV32I-NEXT: and s0, t0, s11
-; RV32I-NEXT: slli t0, t0, 24
-; RV32I-NEXT: and a1, a1, s11
-; RV32I-NEXT: or a1, a1, t5
-; RV32I-NEXT: srli t5, a0, 8
-; RV32I-NEXT: slli a2, a2, 8
-; RV32I-NEXT: or a2, a3, a2
-; RV32I-NEXT: srli s6, a0, 24
-; RV32I-NEXT: and a3, a5, s11
-; RV32I-NEXT: or a3, a3, a6
-; RV32I-NEXT: and s4, a0, s11
-; RV32I-NEXT: slli s7, a0, 24
-; RV32I-NEXT: slli a4, a4, 8
-; RV32I-NEXT: or a0, t4, a4
-; RV32I-NEXT: srli a5, t2, 8
-; RV32I-NEXT: and a4, s2, s11
-; RV32I-NEXT: or a4, a4, t3
-; RV32I-NEXT: srli a6, t2, 24
+; RV32I-NEXT: srli t6, t3, 8
+; RV32I-NEXT: srli s1, t3, 24
+; RV32I-NEXT: and s0, t3, s11
+; RV32I-NEXT: slli t3, t3, 24
+; RV32I-NEXT: and a2, a2, s11
+; RV32I-NEXT: or a2, a2, s6
+; RV32I-NEXT: srli s6, a1, 8
+; RV32I-NEXT: slli a3, a3, 8
+; RV32I-NEXT: or a3, a6, a3
+; RV32I-NEXT: srli s4, a1, 24
+; RV32I-NEXT: and a6, t0, s11
+; RV32I-NEXT: or a6, a6, t2
+; RV32I-NEXT: and s2, a1, s11
+; RV32I-NEXT: slli s7, a1, 24
+; RV32I-NEXT: slli a7, a7, 8
+; RV32I-NEXT: or a1, t4, a7
+; RV32I-NEXT: srli t0, a0, 8
+; RV32I-NEXT: and a7, t1, s11
+; RV32I-NEXT: or a7, a7, t5
+; RV32I-NEXT: srli t2, a0, 24
; RV32I-NEXT: slli s3, s3, 8
; RV32I-NEXT: or t4, s5, s3
-; RV32I-NEXT: and s2, t2, s11
-; RV32I-NEXT: slli s3, t2, 24
-; RV32I-NEXT: and t2, t6, s11
-; RV32I-NEXT: or t2, t2, s1
-; RV32I-NEXT: srli t3, t1, 8
+; RV32I-NEXT: and t1, a0, s11
+; RV32I-NEXT: slli s3, a0, 24
+; RV32I-NEXT: and a0, t6, s11
+; RV32I-NEXT: or a0, a0, s1
+; RV32I-NEXT: srli t5, a5, 8
; RV32I-NEXT: slli s0, s0, 8
-; RV32I-NEXT: or s0, t0, s0
-; RV32I-NEXT: srli s5, t1, 24
-; RV32I-NEXT: and t0, t5, s11
-; RV32I-NEXT: or t0, t0, s6
-; RV32I-NEXT: and t6, t1, s11
-; RV32I-NEXT: slli t5, t1, 24
-; RV32I-NEXT: slli s4, s4, 8
-; RV32I-NEXT: or t1, s7, s4
-; RV32I-NEXT: srli s1, a7, 8
-; RV32I-NEXT: and a5, a5, s11
-; RV32I-NEXT: or a5, a5, a6
-; RV32I-NEXT: srli a6, a7, 24
+; RV32I-NEXT: or s0, t3, s0
+; RV32I-NEXT: srli s5, a5, 24
+; RV32I-NEXT: and t3, s6, s11
+; RV32I-NEXT: or t3, t3, s4
+; RV32I-NEXT: and t6, a5, s11
+; RV32I-NEXT: slli s6, a5, 24
; RV32I-NEXT: slli s2, s2, 8
-; RV32I-NEXT: or s2, s3, s2
-; RV32I-NEXT: and s3, a7, s11
-; RV32I-NEXT: slli a7, a7, 24
-; RV32I-NEXT: and t3, t3, s11
+; RV32I-NEXT: or a5, s7, s2
+; RV32I-NEXT: srli s1, a4, 8
+; RV32I-NEXT: and t0, t0, s11
+; RV32I-NEXT: or t0, t0, t2
+; RV32I-NEXT: srli t2, a4, 24
+; RV32I-NEXT: slli t1, t1, 8
+; RV32I-NEXT: or t1, s3, t1
+; RV32I-NEXT: and s2, a4, s11
+; RV32I-NEXT: slli a4, a4, 24
+; RV32I-NEXT: and t5, t5, s11
; RV32I-NEXT: slli t6, t6, 8
; RV32I-NEXT: and s1, s1, s11
-; RV32I-NEXT: slli s3, s3, 8
-; RV32I-NEXT: or t3, t3, s5
-; RV32I-NEXT: or t5, t5, t6
-; RV32I-NEXT: or a6, s1, a6
-; RV32I-NEXT: or a7, a7, s3
-; RV32I-NEXT: or a1, a2, a1
-; RV32I-NEXT: or a0, a0, a3
-; RV32I-NEXT: or a2, t4, a4
-; RV32I-NEXT: or a3, s0, t2
-; RV32I-NEXT: or a4, t1, t0
-; RV32I-NEXT: or a5, s2, a5
-; RV32I-NEXT: or t0, t5, t3
-; RV32I-NEXT: or a6, a7, a6
-; RV32I-NEXT: srli a7, a1, 4
+; RV32I-NEXT: slli s2, s2, 8
+; RV32I-NEXT: or t5, t5, s5
+; RV32I-NEXT: or t6, s6, t6
+; RV32I-NEXT: or t2, s1, t2
+; RV32I-NEXT: or a4, a4, s2
+; RV32I-NEXT: or a2, a3, a2
+; RV32I-NEXT: or a1, a1, a6
+; RV32I-NEXT: or a3, t4, a7
+; RV32I-NEXT: or a0, s0, a0
+; RV32I-NEXT: or a5, a5, t3
+; RV32I-NEXT: or a6, t1, t0
+; RV32I-NEXT: or a7, t6, t5
+; RV32I-NEXT: or a4, a4, t2
+; RV32I-NEXT: srli t0, a2, 4
; RV32I-NEXT: sw s10, 760(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a1, a1, s10
-; RV32I-NEXT: srli t1, a0, 4
-; RV32I-NEXT: and a0, a0, s10
-; RV32I-NEXT: srli t2, a2, 4
; RV32I-NEXT: and a2, a2, s10
-; RV32I-NEXT: srli t3, a3, 4
+; RV32I-NEXT: srli t1, a1, 4
+; RV32I-NEXT: and a1, a1, s10
+; RV32I-NEXT: srli t2, a3, 4
; RV32I-NEXT: and a3, a3, s10
-; RV32I-NEXT: srli t4, a4, 4
-; RV32I-NEXT: and a4, a4, s10
-; RV32I-NEXT: srli t5, a5, 4
+; RV32I-NEXT: srli t3, a0, 4
+; RV32I-NEXT: and a0, a0, s10
+; RV32I-NEXT: srli t4, a5, 4
; RV32I-NEXT: and a5, a5, s10
-; RV32I-NEXT: srli t6, t0, 4
-; RV32I-NEXT: and t0, t0, s10
-; RV32I-NEXT: srli s0, a6, 4
+; RV32I-NEXT: srli t5, a6, 4
; RV32I-NEXT: and a6, a6, s10
+; RV32I-NEXT: srli t6, a7, 4
; RV32I-NEXT: and a7, a7, s10
-; RV32I-NEXT: slli a1, a1, 4
+; RV32I-NEXT: srli s0, a4, 4
+; RV32I-NEXT: and a4, a4, s10
+; RV32I-NEXT: and t0, t0, s10
+; RV32I-NEXT: slli a2, a2, 4
; RV32I-NEXT: and t1, t1, s10
-; RV32I-NEXT: slli a0, a0, 4
+; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: and t2, t2, s10
-; RV32I-NEXT: slli a2, a2, 4
-; RV32I-NEXT: and t3, t3, s10
; RV32I-NEXT: slli a3, a3, 4
+; RV32I-NEXT: and t3, t3, s10
+; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: and t4, t4, s10
-; RV32I-NEXT: slli a4, a4, 4
-; RV32I-NEXT: and t5, t5, s10
; RV32I-NEXT: slli a5, a5, 4
+; RV32I-NEXT: and t5, t5, s10
+; RV32I-NEXT: slli a6, a6, 4
; RV32I-NEXT: and t6, t6, s10
-; RV32I-NEXT: slli t0, t0, 4
+; RV32I-NEXT: slli a7, a7, 4
; RV32I-NEXT: and s0, s0, s10
-; RV32I-NEXT: slli a6, a6, 4
-; RV32I-NEXT: or a1, a7, a1
-; RV32I-NEXT: or a0, t1, a0
-; RV32I-NEXT: or a2, t2, a2
-; RV32I-NEXT: or a3, t3, a3
-; RV32I-NEXT: or a4, t4, a4
-; RV32I-NEXT: or a5, t5, a5
-; RV32I-NEXT: or a7, t6, t0
-; RV32I-NEXT: or a6, s0, a6
-; RV32I-NEXT: srli t0, a1, 2
-; RV32I-NEXT: sw s9, 740(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a1, a1, s9
-; RV32I-NEXT: srli t1, a0, 2
-; RV32I-NEXT: and a0, a0, s9
-; RV32I-NEXT: srli t2, a2, 2
+; RV32I-NEXT: slli a4, a4, 4
+; RV32I-NEXT: or a2, t0, a2
+; RV32I-NEXT: or a1, t1, a1
+; RV32I-NEXT: or a3, t2, a3
+; RV32I-NEXT: or a0, t3, a0
+; RV32I-NEXT: or a5, t4, a5
+; RV32I-NEXT: or a6, t5, a6
+; RV32I-NEXT: or a7, t6, a7
+; RV32I-NEXT: or a4, s0, a4
+; RV32I-NEXT: srli t0, a2, 2
+; RV32I-NEXT: sw s9, 744(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, s9
-; RV32I-NEXT: srli t3, a3, 2
+; RV32I-NEXT: srli t1, a1, 2
+; RV32I-NEXT: and a1, a1, s9
+; RV32I-NEXT: srli t2, a3, 2
; RV32I-NEXT: and a3, a3, s9
-; RV32I-NEXT: srli t4, a4, 2
-; RV32I-NEXT: and a4, a4, s9
-; RV32I-NEXT: srli t5, a5, 2
+; RV32I-NEXT: srli t3, a0, 2
+; RV32I-NEXT: and a0, a0, s9
+; RV32I-NEXT: srli t4, a5, 2
; RV32I-NEXT: and a5, a5, s9
+; RV32I-NEXT: srli t5, a6, 2
+; RV32I-NEXT: and a6, a6, s9
; RV32I-NEXT: srli t6, a7, 2
; RV32I-NEXT: and a7, a7, s9
-; RV32I-NEXT: srli s0, a6, 2
-; RV32I-NEXT: and a6, a6, s9
+; RV32I-NEXT: srli s0, a4, 2
+; RV32I-NEXT: and a4, a4, s9
; RV32I-NEXT: and t0, t0, s9
-; RV32I-NEXT: slli a1, a1, 2
+; RV32I-NEXT: slli a2, a2, 2
; RV32I-NEXT: and t1, t1, s9
-; RV32I-NEXT: slli a0, a0, 2
+; RV32I-NEXT: slli a1, a1, 2
; RV32I-NEXT: and t2, t2, s9
-; RV32I-NEXT: slli a2, a2, 2
-; RV32I-NEXT: and t3, t3, s9
; RV32I-NEXT: slli a3, a3, 2
+; RV32I-NEXT: and t3, t3, s9
+; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: and t4, t4, s9
-; RV32I-NEXT: slli a4, a4, 2
-; RV32I-NEXT: and t5, t5, s9
; RV32I-NEXT: slli a5, a5, 2
+; RV32I-NEXT: and t5, t5, s9
+; RV32I-NEXT: slli a6, a6, 2
; RV32I-NEXT: and t6, t6, s9
; RV32I-NEXT: slli a7, a7, 2
; RV32I-NEXT: and s0, s0, s9
-; RV32I-NEXT: slli a6, a6, 2
-; RV32I-NEXT: or a1, t0, a1
-; RV32I-NEXT: or a0, t1, a0
-; RV32I-NEXT: or a2, t2, a2
-; RV32I-NEXT: or a3, t3, a3
-; RV32I-NEXT: or a4, t4, a4
-; RV32I-NEXT: or a5, t5, a5
+; RV32I-NEXT: slli a4, a4, 2
+; RV32I-NEXT: or a2, t0, a2
+; RV32I-NEXT: or a1, t1, a1
+; RV32I-NEXT: or a3, t2, a3
+; RV32I-NEXT: or a0, t3, a0
+; RV32I-NEXT: or a5, t4, a5
+; RV32I-NEXT: or a6, t5, a6
; RV32I-NEXT: or a7, t6, a7
-; RV32I-NEXT: or a6, s0, a6
-; RV32I-NEXT: srli t0, a1, 1
-; RV32I-NEXT: sw s8, 744(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a1, a1, s8
-; RV32I-NEXT: srli t1, a0, 1
-; RV32I-NEXT: and a0, a0, s8
+; RV32I-NEXT: or t0, s0, a4
; RV32I-NEXT: srli t2, a2, 1
; RV32I-NEXT: and a2, a2, s8
-; RV32I-NEXT: srli t3, a3, 1
+; RV32I-NEXT: srli t3, a1, 1
+; RV32I-NEXT: and a1, a1, s8
+; RV32I-NEXT: srli t4, a3, 1
; RV32I-NEXT: and a3, a3, s8
-; RV32I-NEXT: srli t4, a4, 1
-; RV32I-NEXT: and a4, a4, s8
-; RV32I-NEXT: srli t5, a5, 1
+; RV32I-NEXT: srli t5, a0, 1
+; RV32I-NEXT: and a0, a0, s8
+; RV32I-NEXT: srli a4, a5, 1
; RV32I-NEXT: and a5, a5, s8
-; RV32I-NEXT: srli t6, a7, 1
-; RV32I-NEXT: and a7, a7, s8
-; RV32I-NEXT: srli s0, a6, 1
+; RV32I-NEXT: srli t6, a6, 1
; RV32I-NEXT: and a6, a6, s8
-; RV32I-NEXT: and t0, t0, s8
-; RV32I-NEXT: slli a1, a1, 1
-; RV32I-NEXT: and t1, t1, s8
-; RV32I-NEXT: slli s1, a0, 1
-; RV32I-NEXT: and s2, t2, s8
+; RV32I-NEXT: srli t1, a7, 1
+; RV32I-NEXT: and a7, a7, s8
+; RV32I-NEXT: and s0, t2, s8
; RV32I-NEXT: slli a2, a2, 1
; RV32I-NEXT: and t3, t3, s8
-; RV32I-NEXT: slli s3, a3, 1
-; RV32I-NEXT: and t4, t4, s8
-; RV32I-NEXT: slli a4, a4, 1
+; RV32I-NEXT: slli s1, a1, 1
+; RV32I-NEXT: and s2, t4, s8
+; RV32I-NEXT: slli a3, a3, 1
+; RV32I-NEXT: slli s4, t4, 31
; RV32I-NEXT: and t5, t5, s8
+; RV32I-NEXT: slli s3, a0, 1
+; RV32I-NEXT: slli t2, t2, 31
+; RV32I-NEXT: and s5, a4, s8
; RV32I-NEXT: slli a5, a5, 1
; RV32I-NEXT: and t6, t6, s8
-; RV32I-NEXT: slli s4, a7, 1
-; RV32I-NEXT: and s6, s0, s8
-; RV32I-NEXT: slli t2, a6, 1
-; RV32I-NEXT: or a0, t0, a1
-; RV32I-NEXT: or a1, t1, s1
-; RV32I-NEXT: or a2, s2, a2
-; RV32I-NEXT: srli a7, s1, 31
-; RV32I-NEXT: or a3, t3, s3
-; RV32I-NEXT: srli t1, s3, 31
-; RV32I-NEXT: or s0, t4, a4
-; RV32I-NEXT: or s5, t5, a5
-; RV32I-NEXT: or s2, t6, s4
-; RV32I-NEXT: srli a4, a5, 31
-; RV32I-NEXT: or s6, s6, t2
-; RV32I-NEXT: srli t3, t2, 31
-; RV32I-NEXT: srli a5, a0, 8
-; RV32I-NEXT: srli a6, a0, 24
-; RV32I-NEXT: srli t0, a1, 8
-; RV32I-NEXT: srli t2, a1, 24
-; RV32I-NEXT: slli t4, a1, 24
-; RV32I-NEXT: and t5, a1, s11
-; RV32I-NEXT: slli t6, a2, 31
-; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: slli s1, a0, 31
-; RV32I-NEXT: seqz t1, t1
+; RV32I-NEXT: slli t4, a6, 1
+; RV32I-NEXT: and a6, t1, s8
+; RV32I-NEXT: slli a7, a7, 1
+; RV32I-NEXT: or a1, s0, a2
+; RV32I-NEXT: or a0, t3, s1
+; RV32I-NEXT: or a2, s2, a3
+; RV32I-NEXT: srli s1, s1, 31
+; RV32I-NEXT: or a3, t5, s3
+; RV32I-NEXT: srli t3, s3, 31
+; RV32I-NEXT: or s3, s5, a5
+; RV32I-NEXT: or s6, t6, t4
+; RV32I-NEXT: or s5, a6, a7
+; RV32I-NEXT: srli a5, a1, 8
+; RV32I-NEXT: srli a6, a1, 24
+; RV32I-NEXT: srli a7, a0, 8
+; RV32I-NEXT: srli t5, a0, 24
+; RV32I-NEXT: slli t6, a0, 24
; RV32I-NEXT: and a5, a5, s11
; RV32I-NEXT: or a5, a5, a6
-; RV32I-NEXT: srli s4, s0, 8
-; RV32I-NEXT: and a6, t0, s11
-; RV32I-NEXT: or a6, a6, t2
-; RV32I-NEXT: srli t2, s0, 24
-; RV32I-NEXT: slli t5, t5, 8
-; RV32I-NEXT: or t0, t4, t5
-; RV32I-NEXT: srli t4, s5, 8
-; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: and t5, a7, t6
-; RV32I-NEXT: sw t5, 720(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t1, t1, s1
-; RV32I-NEXT: sw t1, 728(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a7, a7, s1
-; RV32I-NEXT: sw a7, 736(sp) # 4-byte Folded Spill
-; RV32I-NEXT: srli a7, s5, 24
-; RV32I-NEXT: and t1, s4, s11
-; RV32I-NEXT: or t2, t1, t2
-; RV32I-NEXT: slli t5, s5, 24
-; RV32I-NEXT: and t1, t4, s11
-; RV32I-NEXT: or t1, t1, a7
-; RV32I-NEXT: and a7, s5, s11
-; RV32I-NEXT: slli a7, a7, 8
-; RV32I-NEXT: or a7, t5, a7
-; RV32I-NEXT: slli t4, s2, 31
-; RV32I-NEXT: seqz a4, a4
+; RV32I-NEXT: and s0, a0, s11
+; RV32I-NEXT: seqz s1, s1
; RV32I-NEXT: seqz t3, t3
-; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: addi t5, t3, -1
-; RV32I-NEXT: and t3, a4, t4
-; RV32I-NEXT: sw t3, 724(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, s0, 31
-; RV32I-NEXT: and t4, t5, t3
-; RV32I-NEXT: sw t4, 732(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, t3
+; RV32I-NEXT: and a6, a7, s11
+; RV32I-NEXT: or a6, a6, t5
+; RV32I-NEXT: srli t5, s3, 8
+; RV32I-NEXT: slli s0, s0, 8
+; RV32I-NEXT: or a7, t6, s0
+; RV32I-NEXT: srli t6, s3, 24
+; RV32I-NEXT: addi s1, s1, -1
+; RV32I-NEXT: addi t3, t3, -1
+; RV32I-NEXT: and s0, s1, s4
+; RV32I-NEXT: sw s0, 728(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t3, t3, t2
+; RV32I-NEXT: sw t3, 732(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t2, s1, t2
+; RV32I-NEXT: sw t2, 736(sp) # 4-byte Folded Spill
+; RV32I-NEXT: srli t2, s6, 8
+; RV32I-NEXT: and t3, t5, s11
+; RV32I-NEXT: or t6, t3, t6
+; RV32I-NEXT: srli t3, s6, 24
+; RV32I-NEXT: and t2, t2, s11
+; RV32I-NEXT: or s2, t2, t3
+; RV32I-NEXT: and t2, s6, s11
+; RV32I-NEXT: slli t2, t2, 8
+; RV32I-NEXT: slli t3, s6, 24
+; RV32I-NEXT: or s7, t3, t2
+; RV32I-NEXT: srli t2, t0, 1
+; RV32I-NEXT: sw s8, 740(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and s0, t0, s8
+; RV32I-NEXT: slli t0, t1, 31
+; RV32I-NEXT: and t1, t2, s8
+; RV32I-NEXT: slli s0, s0, 1
+; RV32I-NEXT: slli a4, a4, 31
+; RV32I-NEXT: srli t3, t4, 31
+; RV32I-NEXT: or t2, t1, s0
+; RV32I-NEXT: srli s0, s0, 31
+; RV32I-NEXT: seqz t1, t3
+; RV32I-NEXT: seqz t3, s0
+; RV32I-NEXT: addi t1, t1, -1
+; RV32I-NEXT: addi t3, t3, -1
+; RV32I-NEXT: and t0, t1, t0
+; RV32I-NEXT: sw t0, 720(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t0, t3, a4
+; RV32I-NEXT: sw t0, 724(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, t1, a4
; RV32I-NEXT: sw a4, 716(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a0, s11
; RV32I-NEXT: sw s11, 756(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a4, 8
-; RV32I-NEXT: slli t4, a0, 24
-; RV32I-NEXT: or a4, t4, a4
-; RV32I-NEXT: or a4, a4, a5
+; RV32I-NEXT: and t0, a1, s11
+; RV32I-NEXT: slli t0, t0, 8
+; RV32I-NEXT: slli t4, a1, 24
+; RV32I-NEXT: or t0, t4, t0
+; RV32I-NEXT: or a4, t0, a5
; RV32I-NEXT: sw a4, 708(sp) # 4-byte Folded Spill
-; RV32I-NEXT: or a4, t0, a6
+; RV32I-NEXT: or a4, a7, a6
; RV32I-NEXT: sw a4, 712(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a1, 2
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 2
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 1
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 684(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 1
-; RV32I-NEXT: and s1, a5, a6
-; RV32I-NEXT: and t5, a4, a6
-; RV32I-NEXT: andi a4, a1, 4
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 4
+; RV32I-NEXT: andi a5, a0, 2
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a6, a3, 2
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 2
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 664(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 2
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 676(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 692(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a1, 8
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 8
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 1
+; RV32I-NEXT: and s4, a5, a7
+; RV32I-NEXT: slli a7, a1, 1
+; RV32I-NEXT: and t5, a6, a7
+; RV32I-NEXT: and t3, a5, a7
+; RV32I-NEXT: andi a5, a0, 4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a6, a3, 4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 3
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 640(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 3
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 656(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 668(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a1, 16
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 16
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 2
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 672(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 2
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 684(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and s1, a5, a7
+; RV32I-NEXT: andi a5, a0, 8
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a6, a3, 8
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 4
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 624(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 4
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 636(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 3
+; RV32I-NEXT: and a4, a5, a7
; RV32I-NEXT: sw a4, 648(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a1, 32
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 32
+; RV32I-NEXT: slli a7, a1, 3
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 664(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 676(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a5, a0, 16
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a6, a3, 16
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 5
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 604(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 5
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 616(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 628(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a1, 64
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 64
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 4
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 632(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 4
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 644(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 656(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a5, a0, 32
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a6, a3, 32
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 5
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 612(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 5
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 624(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 636(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a5, a0, 64
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: andi a6, a3, 64
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 6
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 672(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 6
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 680(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 6
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 680(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 6
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 688(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
; RV32I-NEXT: sw a4, 696(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a1, 128
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 128
+; RV32I-NEXT: andi a5, a0, 128
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a6, a3, 128
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 7
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 580(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 7
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 588(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 592(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a1, 256
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 256
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 7
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 588(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 7
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 596(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 600(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a5, a0, 256
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a6, a3, 256
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 8
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 556(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 8
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 564(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 584(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a1, 512
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 512
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 8
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 564(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 8
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 572(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 592(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a5, a0, 512
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a6, a3, 512
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 9
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 612(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 9
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 620(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 632(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a1, 1024
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 1024
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 9
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 620(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 9
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 628(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 640(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a5, a0, 1024
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a6, a3, 1024
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 10
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 688(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 10
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 700(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 10
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 692(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 10
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 700(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
; RV32I-NEXT: sw a4, 704(sp) # 4-byte Folded Spill
-; RV32I-NEXT: li a4, 1
-; RV32I-NEXT: slli t0, a4, 11
-; RV32I-NEXT: and a4, a1, t0
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, t0
+; RV32I-NEXT: li a5, 1
+; RV32I-NEXT: slli t0, a5, 11
+; RV32I-NEXT: and a5, a0, t0
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a3, t0
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 11
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 508(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 11
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 520(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 532(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 1
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 11
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 516(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 11
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 528(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 540(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 1
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a3, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 12
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 500(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 12
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 504(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 12
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 508(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 12
+; RV32I-NEXT: and a4, a6, a7
; RV32I-NEXT: sw a4, 512(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 2
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 520(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a3, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 13
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 536(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 13
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 540(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 552(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 4
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 13
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 544(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 13
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 548(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 560(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 4
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a3, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 14
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 596(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 14
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 600(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 14
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 604(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 14
+; RV32I-NEXT: and a4, a6, a7
; RV32I-NEXT: sw a4, 608(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 8
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 616(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 8
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a3, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 15
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 644(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 15
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 652(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 15
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 652(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 15
+; RV32I-NEXT: and a4, a6, a7
; RV32I-NEXT: sw a4, 660(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 16
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 668(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 16
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a3, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 16
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 432(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 16
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 440(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 444(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 32
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 16
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 440(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 16
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 448(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 452(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 32
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a3, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 17
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 412(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 17
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 420(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 436(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 64
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 17
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 420(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 17
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 428(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 444(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 64
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a3, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 18
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 460(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 18
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 468(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 484(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 128
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 18
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 468(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 18
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 476(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 492(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 128
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a3, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 19
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 516(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 19
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 524(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 528(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 256
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 19
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 524(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 19
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 532(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 536(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 256
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a3, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 20
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 544(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 20
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 548(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 560(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 512
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 20
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 552(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 20
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 556(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 568(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 512
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a3, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 21
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 568(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 21
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 572(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 21
+; RV32I-NEXT: and a4, a5, a7
; RV32I-NEXT: sw a4, 576(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 1024
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: slli a7, a1, 21
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 580(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 584(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 1024
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a3, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 22
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 380(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 22
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 392(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 396(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 2048
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 22
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 388(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 22
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 400(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 404(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 2048
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a3, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 23
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 368(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 23
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 372(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 388(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 4096
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 23
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 376(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 23
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 380(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 396(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 4096
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a3, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 24
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 400(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a5, t4
-; RV32I-NEXT: sw a5, 404(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, t4
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 24
+; RV32I-NEXT: and a4, a5, a7
; RV32I-NEXT: sw a4, 408(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 8192
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: and a4, a6, t4
+; RV32I-NEXT: sw a4, 412(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, t4
+; RV32I-NEXT: sw a4, 416(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 8192
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a3, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 25
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 416(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 25
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 424(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 428(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 16384
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 25
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 424(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 25
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 432(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 436(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 16384
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a3, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 26
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 448(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 26
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 452(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 464(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 32768
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 26
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 456(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 26
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 460(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 472(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 32768
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a3, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 27
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 472(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 27
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 476(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 27
+; RV32I-NEXT: and a4, a5, a7
; RV32I-NEXT: sw a4, 480(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 65536
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: slli a7, a1, 27
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 484(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 488(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 65536
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a3, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 28
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 492(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 28
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 488(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 28
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 500(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 28
+; RV32I-NEXT: and a4, a6, a7
; RV32I-NEXT: sw a4, 496(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 131072
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 504(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 131072
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a3, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 29
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 356(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 29
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 360(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 29
+; RV32I-NEXT: and a4, a5, a7
; RV32I-NEXT: sw a4, 364(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 262144
-; RV32I-NEXT: andi a4, a1, 1
-; RV32I-NEXT: and a1, a1, a5
-; RV32I-NEXT: lui t3, 262144
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 1
+; RV32I-NEXT: slli a7, a1, 29
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 368(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 372(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 262144
+; RV32I-NEXT: andi a5, a0, 1
+; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a6, a3, 1
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 30
-; RV32I-NEXT: and a2, a4, a2
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a2, 30
+; RV32I-NEXT: and a2, a5, a2
; RV32I-NEXT: sw a2, 324(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a5, a0
-; RV32I-NEXT: sw a5, 348(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a0
-; RV32I-NEXT: slli a0, a0, 30
-; RV32I-NEXT: and a2, a3, t3
-; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: and a2, a6, a1
+; RV32I-NEXT: sw a2, 352(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a5, a5, a1
+; RV32I-NEXT: slli a1, a1, 30
+; RV32I-NEXT: and a2, a3, a4
+; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: seqz a2, a2
-; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and a3, a1, a6
+; RV32I-NEXT: and a3, a0, a7
; RV32I-NEXT: sw a3, 316(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a2, a2, a0
-; RV32I-NEXT: sw a2, 344(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t3, a1, a0
-; RV32I-NEXT: and a0, s0, s11
+; RV32I-NEXT: and a2, a2, a1
+; RV32I-NEXT: sw a2, 348(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, a0, a1
+; RV32I-NEXT: and a0, s3, s11
; RV32I-NEXT: slli a0, a0, 8
-; RV32I-NEXT: slli t4, s0, 24
+; RV32I-NEXT: slli t4, s3, 24
; RV32I-NEXT: or a0, t4, a0
-; RV32I-NEXT: or a0, a0, t2
-; RV32I-NEXT: sw a0, 376(sp) # 4-byte Folded Spill
-; RV32I-NEXT: or a0, a7, t1
+; RV32I-NEXT: or a0, a0, t6
; RV32I-NEXT: sw a0, 384(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a0, s5, 2
+; RV32I-NEXT: or a0, s7, s2
+; RV32I-NEXT: sw a0, 392(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a0, s6, 2
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 2
+; RV32I-NEXT: andi a1, t2, 2
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 1
+; RV32I-NEXT: slli a2, s5, 1
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 320(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 1
-; RV32I-NEXT: and t2, a1, a2
-; RV32I-NEXT: and a7, a0, a2
-; RV32I-NEXT: andi a0, s5, 4
+; RV32I-NEXT: slli a2, s3, 1
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: sw a1, 344(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: sw a0, 360(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a0, s6, 4
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 4
+; RV32I-NEXT: andi a1, t2, 4
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 2
+; RV32I-NEXT: slli a2, s5, 2
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 296(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 2
+; RV32I-NEXT: slli a2, s3, 2
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sw a1, 312(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: sw a0, 332(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a0, s5, 8
+; RV32I-NEXT: andi a0, s6, 8
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 8
+; RV32I-NEXT: andi a1, t2, 8
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 3
+; RV32I-NEXT: slli a2, s5, 3
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 280(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 3
+; RV32I-NEXT: slli a2, s3, 3
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sw a1, 292(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: sw a0, 304(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a0, s5, 16
+; RV32I-NEXT: andi a0, s6, 16
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 16
+; RV32I-NEXT: andi a1, t2, 16
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 4
+; RV32I-NEXT: slli a2, s5, 4
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 256(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 4
+; RV32I-NEXT: slli a2, s3, 4
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sw a1, 268(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: sw a0, 288(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a0, s5, 32
+; RV32I-NEXT: andi a0, s6, 32
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 32
+; RV32I-NEXT: andi a1, t2, 32
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 5
+; RV32I-NEXT: slli a2, s5, 5
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 228(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 5
+; RV32I-NEXT: slli a2, s3, 5
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sw a1, 248(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: sw a0, 264(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a0, s5, 64
+; RV32I-NEXT: andi a0, s6, 64
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 64
+; RV32I-NEXT: andi a1, t2, 64
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 6
+; RV32I-NEXT: slli a2, s5, 6
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 300(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 6
+; RV32I-NEXT: slli a2, s3, 6
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sw a1, 308(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: sw a0, 328(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a0, s5, 128
+; RV32I-NEXT: andi a0, s6, 128
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 128
+; RV32I-NEXT: andi a1, t2, 128
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 7
+; RV32I-NEXT: slli a2, s5, 7
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 212(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 7
+; RV32I-NEXT: slli a2, s3, 7
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sw a1, 220(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: sw a0, 224(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a0, s5, 256
+; RV32I-NEXT: andi a0, s6, 256
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 256
+; RV32I-NEXT: andi a1, t2, 256
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 8
+; RV32I-NEXT: slli a2, s5, 8
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 188(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 8
+; RV32I-NEXT: slli a2, s3, 8
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sw a1, 204(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: sw a0, 216(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a0, s5, 512
+; RV32I-NEXT: andi a0, s6, 512
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 512
+; RV32I-NEXT: andi a1, t2, 512
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 9
+; RV32I-NEXT: slli a2, s5, 9
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 232(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 9
+; RV32I-NEXT: slli a2, s3, 9
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sw a1, 244(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: sw a0, 260(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a0, s5, 1024
+; RV32I-NEXT: andi a0, s6, 1024
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 1024
+; RV32I-NEXT: andi a1, t2, 1024
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 10
+; RV32I-NEXT: slli a2, s5, 10
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 336(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 10
+; RV32I-NEXT: slli a2, s3, 10
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sw a1, 340(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 352(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw t0, 456(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a0, s5, t0
+; RV32I-NEXT: sw a0, 356(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw t0, 464(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a0, s6, t0
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, t0
+; RV32I-NEXT: and a1, t2, t0
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 11
+; RV32I-NEXT: slli a2, s5, 11
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 140(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 11
+; RV32I-NEXT: slli a2, s3, 11
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sw a1, 148(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: sw a0, 156(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 1
-; RV32I-NEXT: and a0, s5, a1
+; RV32I-NEXT: and a0, s6, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 12
+; RV32I-NEXT: slli a2, s5, 12
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 120(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 12
+; RV32I-NEXT: slli a2, s3, 12
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sw a1, 128(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: sw a0, 144(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 2
-; RV32I-NEXT: and a0, s5, a1
+; RV32I-NEXT: and a0, s6, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 13
+; RV32I-NEXT: slli a2, s5, 13
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 168(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 13
+; RV32I-NEXT: slli a2, s3, 13
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sw a1, 172(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: sw a0, 192(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 4
-; RV32I-NEXT: and a0, s5, a1
+; RV32I-NEXT: and a0, s6, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 14
+; RV32I-NEXT: slli a2, s5, 14
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 236(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 14
+; RV32I-NEXT: slli a2, s3, 14
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sw a1, 240(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: sw a0, 252(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 8
-; RV32I-NEXT: and a0, s5, a1
+; RV32I-NEXT: and a0, s6, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 15
+; RV32I-NEXT: slli a2, s5, 15
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 272(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 15
+; RV32I-NEXT: slli a2, s3, 15
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sw a1, 276(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: sw a0, 284(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 16
-; RV32I-NEXT: and a0, s5, a1
+; RV32I-NEXT: and a0, s6, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 16
+; RV32I-NEXT: slli a2, s5, 16
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 56(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 16
+; RV32I-NEXT: slli a2, s3, 16
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sw a1, 72(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 32
-; RV32I-NEXT: and a0, s5, a1
+; RV32I-NEXT: and a0, s6, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 17
+; RV32I-NEXT: slli a2, s5, 17
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 48(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 17
-; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: slli s0, s3, 17
+; RV32I-NEXT: and a1, a1, s0
; RV32I-NEXT: sw a1, 52(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: sw a0, 60(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 64
-; RV32I-NEXT: and a0, s5, a1
+; RV32I-NEXT: and a0, s6, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 18
+; RV32I-NEXT: slli a2, s5, 18
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 96(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 18
+; RV32I-NEXT: slli a2, s3, 18
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sw a1, 108(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: sw a0, 116(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 128
-; RV32I-NEXT: and a0, s5, a1
+; RV32I-NEXT: and a0, s6, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 19
+; RV32I-NEXT: slli a2, s5, 19
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 152(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 19
+; RV32I-NEXT: slli a2, s3, 19
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sw a1, 160(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: sw a0, 164(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 256
-; RV32I-NEXT: and a0, s5, a1
+; RV32I-NEXT: and a0, s6, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 20
+; RV32I-NEXT: slli a2, s5, 20
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 176(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 20
+; RV32I-NEXT: slli a2, s3, 20
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sw a1, 180(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: sw a0, 184(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 512
-; RV32I-NEXT: and a0, s5, a1
+; RV32I-NEXT: and a0, s6, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 21
+; RV32I-NEXT: slli a2, s5, 21
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: sw a2, 196(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, s0, 21
+; RV32I-NEXT: slli a2, s3, 21
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sw a1, 200(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: sw a0, 208(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 1024
-; RV32I-NEXT: and a0, s5, a1
+; RV32I-NEXT: and a0, s6, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, s2, 22
+; RV32I-NEXT: slli a2, s5, 22
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, s0, 22
-; RV32I-NEXT: and a2, a1, a5
-; RV32I-NEXT: and a0, a0, a5
+; RV32I-NEXT: sw a2, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, s3, 22
+; RV32I-NEXT: and a1, a1, a3
+; RV32I-NEXT: sw a1, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 2048
-; RV32I-NEXT: and a0, s5, a1
+; RV32I-NEXT: and a0, s6, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a3, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a0, s2, 23
+; RV32I-NEXT: slli a0, s5, 23
; RV32I-NEXT: and a0, a3, a0
-; RV32I-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, s0, 23
-; RV32I-NEXT: and a5, a1, a6
-; RV32I-NEXT: and a0, a3, a6
-; RV32I-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, s3, 23
+; RV32I-NEXT: and a0, a1, a7
+; RV32I-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a0, a3, a7
+; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, 4096
-; RV32I-NEXT: and a6, s5, a0
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: and t0, s6, a0
+; RV32I-NEXT: and a7, s6, a0
+; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: and t0, t2, a0
; RV32I-NEXT: seqz t0, t0
-; RV32I-NEXT: addi t1, a6, -1
+; RV32I-NEXT: addi t1, a7, -1
; RV32I-NEXT: addi t0, t0, -1
-; RV32I-NEXT: slli a6, s2, 24
-; RV32I-NEXT: and a0, t1, a6
+; RV32I-NEXT: slli a7, s5, 24
+; RV32I-NEXT: and a0, t1, a7
; RV32I-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, t0, t4
; RV32I-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, t1, t4
; RV32I-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, 8192
-; RV32I-NEXT: and t4, s5, a0
+; RV32I-NEXT: and t4, s6, a0
; RV32I-NEXT: seqz t4, t4
-; RV32I-NEXT: and t6, s6, a0
+; RV32I-NEXT: and t6, t2, a0
; RV32I-NEXT: seqz t6, t6
-; RV32I-NEXT: addi s4, t4, -1
+; RV32I-NEXT: addi s2, t4, -1
; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: slli t4, s2, 25
-; RV32I-NEXT: and a0, s4, t4
+; RV32I-NEXT: slli t4, s5, 25
+; RV32I-NEXT: and a0, s2, t4
; RV32I-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s7, s0, 25
+; RV32I-NEXT: slli s7, s3, 25
; RV32I-NEXT: and a0, t6, s7
; RV32I-NEXT: sw a0, 68(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a0, s4, s7
+; RV32I-NEXT: and a0, s2, s7
; RV32I-NEXT: sw a0, 76(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, 16384
-; RV32I-NEXT: and s7, s5, a0
+; RV32I-NEXT: and s7, s6, a0
; RV32I-NEXT: seqz s7, s7
-; RV32I-NEXT: and s8, s6, a0
+; RV32I-NEXT: and s8, t2, a0
; RV32I-NEXT: seqz s8, s8
; RV32I-NEXT: addi s9, s7, -1
; RV32I-NEXT: addi s8, s8, -1
-; RV32I-NEXT: slli s7, s2, 26
+; RV32I-NEXT: slli s7, s5, 26
; RV32I-NEXT: and a0, s9, s7
; RV32I-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s10, s0, 26
+; RV32I-NEXT: slli s10, s3, 26
; RV32I-NEXT: and a0, s8, s10
; RV32I-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, s9, s10
; RV32I-NEXT: sw a0, 92(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, 32768
-; RV32I-NEXT: and s9, s5, a0
+; RV32I-NEXT: and s9, s6, a0
; RV32I-NEXT: seqz s9, s9
-; RV32I-NEXT: and s10, s6, a0
+; RV32I-NEXT: and s10, t2, a0
; RV32I-NEXT: seqz s10, s10
; RV32I-NEXT: addi s9, s9, -1
; RV32I-NEXT: addi s10, s10, -1
-; RV32I-NEXT: slli s11, s2, 27
+; RV32I-NEXT: slli s11, s5, 27
; RV32I-NEXT: and a0, s9, s11
; RV32I-NEXT: sw a0, 100(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s11, s0, 27
+; RV32I-NEXT: slli s11, s3, 27
; RV32I-NEXT: and a0, s10, s11
; RV32I-NEXT: sw a0, 104(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, s9, s11
; RV32I-NEXT: sw a0, 112(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, 65536
-; RV32I-NEXT: and s9, s5, a0
+; RV32I-NEXT: and s9, s6, a0
; RV32I-NEXT: seqz s9, s9
-; RV32I-NEXT: and s10, s6, a0
+; RV32I-NEXT: and s10, t2, a0
; RV32I-NEXT: seqz s10, s10
; RV32I-NEXT: addi s9, s9, -1
; RV32I-NEXT: addi s10, s10, -1
-; RV32I-NEXT: slli s11, s2, 28
+; RV32I-NEXT: slli s11, s5, 28
; RV32I-NEXT: and a0, s9, s11
; RV32I-NEXT: sw a0, 132(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s11, s0, 28
+; RV32I-NEXT: slli s11, s3, 28
; RV32I-NEXT: and a0, s10, s11
; RV32I-NEXT: sw a0, 124(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, s9, s11
; RV32I-NEXT: sw a0, 136(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, 131072
-; RV32I-NEXT: and s9, s5, a0
+; RV32I-NEXT: and s9, s6, a0
; RV32I-NEXT: seqz s9, s9
-; RV32I-NEXT: and s10, s6, a0
+; RV32I-NEXT: and s10, t2, a0
; RV32I-NEXT: seqz s10, s10
; RV32I-NEXT: addi s9, s9, -1
; RV32I-NEXT: addi s10, s10, -1
-; RV32I-NEXT: slli s11, s2, 29
-; RV32I-NEXT: and a6, s9, s11
-; RV32I-NEXT: slli ra, s0, 29
+; RV32I-NEXT: slli s11, s5, 29
+; RV32I-NEXT: and a7, s9, s11
+; RV32I-NEXT: slli ra, s3, 29
; RV32I-NEXT: and a3, s10, ra
-; RV32I-NEXT: and a0, s9, ra
-; RV32I-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi ra, s5, 1
-; RV32I-NEXT: lui a0, 262144
-; RV32I-NEXT: and s5, s5, a0
+; RV32I-NEXT: and s8, s9, ra
+; RV32I-NEXT: andi ra, s6, 1
+; RV32I-NEXT: lui a1, 262144
+; RV32I-NEXT: and s6, s6, a1
; RV32I-NEXT: seqz ra, ra
-; RV32I-NEXT: andi s8, s6, 1
-; RV32I-NEXT: seqz s8, s8
+; RV32I-NEXT: andi a4, t2, 1
+; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: addi ra, ra, -1
-; RV32I-NEXT: addi s8, s8, -1
-; RV32I-NEXT: slli s3, s2, 30
-; RV32I-NEXT: and s2, ra, s2
-; RV32I-NEXT: and s8, s8, s0
-; RV32I-NEXT: and a1, ra, s0
-; RV32I-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s0, s0, 30
-; RV32I-NEXT: and s6, s6, a0
-; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: mv a0, s5
+; RV32I-NEXT: slli s5, s5, 30
+; RV32I-NEXT: and a0, ra, a0
+; RV32I-NEXT: and a4, a4, s3
+; RV32I-NEXT: and a2, ra, s3
+; RV32I-NEXT: sw a2, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s3, s3, 30
+; RV32I-NEXT: and t2, t2, a1
; RV32I-NEXT: seqz s6, s6
-; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: seqz t2, t2
; RV32I-NEXT: addi s6, s6, -1
-; RV32I-NEXT: and s3, s5, s3
-; RV32I-NEXT: and s6, s6, s0
-; RV32I-NEXT: and a0, s5, s0
-; RV32I-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 684(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi t2, t2, -1
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: and t2, t2, s3
+; RV32I-NEXT: and a1, s6, s3
+; RV32I-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a1, 324(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a1, a0
-; RV32I-NEXT: sw a0, 684(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 664(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 640(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 664(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 624(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 604(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 624(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 580(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 556(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 604(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 508(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 500(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 580(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 432(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 412(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 556(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 380(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, s4
+; RV32I-NEXT: sw a1, 324(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 672(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 648(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 648(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 632(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 612(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 632(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 588(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 564(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 612(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 516(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 508(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 588(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 440(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 420(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 564(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 388(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 376(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 516(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 364(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 316(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 508(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 352(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, t5
+; RV32I-NEXT: sw a1, 672(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 684(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 664(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 664(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 644(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 624(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 644(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 596(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 572(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 572(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 528(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 512(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 528(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 448(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 428(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 512(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 400(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 380(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 448(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a1, 368(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 508(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 356(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 316(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 500(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 348(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, s1
-; RV32I-NEXT: sw a0, 640(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 676(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 348(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 440(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a1, a5, t3
+; RV32I-NEXT: sw a1, 684(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 676(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, s1, a1
+; RV32I-NEXT: sw a1, 676(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a1, 656(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 432(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 636(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 616(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 616(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 588(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 564(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 588(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 520(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 504(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 564(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 440(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 420(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 520(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 392(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 636(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 656(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 600(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 592(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 428(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 540(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 520(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 520(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 452(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 444(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 452(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 404(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 396(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s10, a1, a2
; RV32I-NEXT: lw a1, 372(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 504(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 360(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 344(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 440(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor a0, a4, t5
-; RV32I-NEXT: sw a0, 636(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 692(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 668(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s10, a0, a1
-; RV32I-NEXT: lw a0, 648(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 628(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s11, a0, a1
-; RV32I-NEXT: lw a0, 592(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 584(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s11, a1, a6
+; RV32I-NEXT: lw a1, 320(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor ra, a0, a1
-; RV32I-NEXT: lw a0, 532(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 512(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 584(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 444(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 436(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 532(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 396(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 388(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 512(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 364(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, t3
-; RV32I-NEXT: sw a0, 444(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 320(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, s2, a0
-; RV32I-NEXT: sw a0, 692(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 296(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 280(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s4, a0, a1
+; RV32I-NEXT: lw s0, 280(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s0, a0, s0
; RV32I-NEXT: lw a0, 256(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 228(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s5, a0, a1
+; RV32I-NEXT: lw s1, 228(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s1, a0, s1
; RV32I-NEXT: lw a0, 212(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a1, 188(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s7, a0, a1
+; RV32I-NEXT: xor s2, a0, a1
; RV32I-NEXT: lw a0, 140(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 120(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s0, a0, s0
+; RV32I-NEXT: lw a1, 120(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s3, a0, a1
; RV32I-NEXT: lw a0, 56(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 48(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s1, a0, s1
-; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s2, a0, a1
-; RV32I-NEXT: xor s3, a6, s3
-; RV32I-NEXT: xor s8, s8, t2
+; RV32I-NEXT: lw a1, 48(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s6, a0, a1
+; RV32I-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s7, a0, a1
+; RV32I-NEXT: xor s5, a7, s5
+; RV32I-NEXT: lw a0, 344(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s4, a4, a0
; RV32I-NEXT: lw a0, 312(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a1, 292(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t0, a0, a1
@@ -3731,17 +3731,20 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: xor t1, a0, a1
; RV32I-NEXT: lw a0, 220(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a1, 204(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t2, a0, a1
+; RV32I-NEXT: xor t3, a0, a1
; RV32I-NEXT: lw a0, 148(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a1, 128(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t3, a0, a1
+; RV32I-NEXT: xor t4, a0, a1
; RV32I-NEXT: lw a0, 72(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a1, 52(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t4, a0, a1
-; RV32I-NEXT: xor t5, a2, a5
-; RV32I-NEXT: xor t6, a3, s6
-; RV32I-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a7, a0, a7
+; RV32I-NEXT: xor t5, a0, a1
+; RV32I-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t6, a0, a1
+; RV32I-NEXT: xor t2, a3, t2
+; RV32I-NEXT: lw a0, 360(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a7, a1, a0
; RV32I-NEXT: lw a0, 332(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a1, 304(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a0, a1
@@ -3758,125 +3761,130 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: lw a5, 60(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a4, a4, a5
; RV32I-NEXT: lw a5, 32(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a6, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lw a6, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s6, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a6, a6, s6
-; RV32I-NEXT: lw s6, 684(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 664(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, s6, s9
-; RV32I-NEXT: sw s6, 676(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s6, 672(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 624(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, s9, s6
-; RV32I-NEXT: sw s6, 672(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s6, 612(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 604(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, s9, s6
-; RV32I-NEXT: sw s6, 668(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s6, 536(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 580(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, s9, s6
-; RV32I-NEXT: sw s6, 664(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s6, 460(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 556(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, s9, s6
-; RV32I-NEXT: sw s6, 656(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s6, 400(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 508(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, s9, s6
-; RV32I-NEXT: sw s6, 648(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s6, 720(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 500(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, s9, s6
-; RV32I-NEXT: sw s6, 720(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s6, 640(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 432(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, s6, s9
-; RV32I-NEXT: sw s6, 628(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s6, 680(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 616(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, s9, s6
-; RV32I-NEXT: sw s6, 624(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s6, 620(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a6, s8, a6
+; RV32I-NEXT: lw s8, 324(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 648(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s8, s9
+; RV32I-NEXT: sw s8, 648(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 680(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 632(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s9, s8
+; RV32I-NEXT: sw s8, 636(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 620(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 612(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s9, s8
+; RV32I-NEXT: sw s8, 632(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 544(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s9, 588(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, s9, s6
-; RV32I-NEXT: sw s6, 620(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s6, 540(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s9, s8
+; RV32I-NEXT: sw s8, 624(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 468(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s9, 564(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, s9, s6
-; RV32I-NEXT: sw s6, 616(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s6, 468(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 520(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, s9, s6
-; RV32I-NEXT: sw s6, 612(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s6, 404(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 504(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, s9, s6
-; RV32I-NEXT: sw s6, 604(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s6, 728(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 440(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, s9, s6
-; RV32I-NEXT: sw s6, 728(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s6, 636(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, s6, s10
-; RV32I-NEXT: sw s6, 592(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s6, 696(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s11, s11, s6
-; RV32I-NEXT: lw s6, 632(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor ra, ra, s6
-; RV32I-NEXT: lw s6, 552(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 584(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, s9, s6
-; RV32I-NEXT: sw s6, 632(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s6, 484(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 532(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s10, s9, s6
-; RV32I-NEXT: lw s6, 408(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s9, s8
+; RV32I-NEXT: sw s8, 620(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 408(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 516(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s9, s8
+; RV32I-NEXT: sw s8, 612(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 728(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 508(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s9, s8
+; RV32I-NEXT: sw s8, 728(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 672(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 664(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s8, s9
+; RV32I-NEXT: sw s8, 600(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 688(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 644(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s9, s8
+; RV32I-NEXT: sw s8, 596(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 628(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 572(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s9, s8
+; RV32I-NEXT: sw s8, 592(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 548(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 528(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s9, s8
+; RV32I-NEXT: sw s8, 588(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 476(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s9, 512(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, s9, s6
-; RV32I-NEXT: sw s6, 588(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s6, 736(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 444(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, s9, s6
-; RV32I-NEXT: sw s6, 736(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s6, 692(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s4, s6, s4
-; RV32I-NEXT: sw s4, 696(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s4, 300(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s5, s5, s4
-; RV32I-NEXT: lw s4, 232(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s4, s7, s4
-; RV32I-NEXT: sw s4, 692(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s4, 168(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s4, s0, s4
+; RV32I-NEXT: xor s8, s9, s8
+; RV32I-NEXT: sw s8, 572(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 412(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 448(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s9, s8
+; RV32I-NEXT: sw s8, 564(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 732(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 440(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s9, s8
+; RV32I-NEXT: sw s8, 732(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 684(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 676(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s8, s9
+; RV32I-NEXT: sw s8, 548(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 696(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 656(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s9, s8
+; RV32I-NEXT: sw s8, 544(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 640(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 428(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s9, s8
+; RV32I-NEXT: sw s8, 540(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 560(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 520(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s9, s8
+; RV32I-NEXT: sw s8, 560(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 492(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 452(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s9, s9, s8
+; RV32I-NEXT: lw s8, 416(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s10, s10, s8
+; RV32I-NEXT: lw s8, 736(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s11, s8
+; RV32I-NEXT: sw s8, 736(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor s0, ra, s0
+; RV32I-NEXT: sw s0, 696(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s0, 300(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s1, s1, s0
+; RV32I-NEXT: lw s0, 232(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s2, s2, s0
+; RV32I-NEXT: lw s0, 168(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s0, s3, s0
+; RV32I-NEXT: sw s0, 688(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw s0, 96(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s0, s1, s0
+; RV32I-NEXT: xor s0, s6, s0
; RV32I-NEXT: sw s0, 684(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw s0, 36(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s0, s2, s0
+; RV32I-NEXT: xor s0, s7, s0
; RV32I-NEXT: sw s0, 680(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s0, 724(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s0, s3, s0
-; RV32I-NEXT: sw s0, 724(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor s0, s8, t0
+; RV32I-NEXT: lw s0, 720(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s0, s5, s0
+; RV32I-NEXT: sw s0, 720(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor t0, s4, t0
+; RV32I-NEXT: sw t0, 676(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw t0, 308(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t1, t1, t0
; RV32I-NEXT: lw t0, 244(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t2, t2, t0
-; RV32I-NEXT: lw t0, 172(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t3, t3, t0
+; RV32I-NEXT: lw t0, 172(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t0, t4, t0
+; RV32I-NEXT: sw t0, 672(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw t0, 108(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t4, t4, t0
+; RV32I-NEXT: xor t0, t5, t0
+; RV32I-NEXT: sw t0, 664(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw t0, 40(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t5, t5, t0
-; RV32I-NEXT: lw t0, 732(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t0, t6, t0
-; RV32I-NEXT: sw t0, 732(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor a7, a7, a0
+; RV32I-NEXT: sw t0, 656(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw t0, 724(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t0, t2, t0
+; RV32I-NEXT: sw t0, 724(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a0, a7, a0
+; RV32I-NEXT: sw a0, 644(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 328(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t6, a1, a0
+; RV32I-NEXT: xor ra, a1, a0
; RV32I-NEXT: lw a0, 260(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a2, a0
; RV32I-NEXT: sw a0, 640(sp) # 4-byte Folded Spill
@@ -3886,321 +3894,329 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: xor a4, a4, a0
; RV32I-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a5, a0
-; RV32I-NEXT: sw a0, 636(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 628(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 716(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a6, a0
; RV32I-NEXT: sw a0, 716(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a1, 708(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a5, a1, 4
+; RV32I-NEXT: srli a6, a1, 4
; RV32I-NEXT: lw a0, 760(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a1, a0
-; RV32I-NEXT: and a5, a5, a0
-; RV32I-NEXT: slli a6, a6, 4
-; RV32I-NEXT: or a1, a5, a6
+; RV32I-NEXT: and a7, a1, a0
+; RV32I-NEXT: and a6, a6, a0
+; RV32I-NEXT: slli a7, a7, 4
+; RV32I-NEXT: or a1, a6, a7
; RV32I-NEXT: sw a1, 708(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a1, 712(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a6, a1, 4
+; RV32I-NEXT: srli a7, a1, 4
; RV32I-NEXT: and t0, a1, a0
-; RV32I-NEXT: and a6, a6, a0
+; RV32I-NEXT: and a7, a7, a0
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: slli t0, t0, 4
-; RV32I-NEXT: or a0, a6, t0
+; RV32I-NEXT: or a0, a7, t0
; RV32I-NEXT: sw a0, 712(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 676(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 672(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a5, a0, a2
-; RV32I-NEXT: lw a0, 688(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 668(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s9, a2, a0
-; RV32I-NEXT: lw a0, 596(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 664(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a6, a2, a0
-; RV32I-NEXT: lw a0, 516(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 656(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a2, a0
-; RV32I-NEXT: sw a0, 676(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 416(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 648(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a2, a0
-; RV32I-NEXT: sw a0, 672(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 628(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 624(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 648(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 636(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a0, a2
-; RV32I-NEXT: sw a0, 688(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 700(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 620(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a2, a0
-; RV32I-NEXT: sw a0, 664(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 600(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 616(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a0, 648(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 692(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 632(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s11, a2, a0
+; RV32I-NEXT: lw a0, 604(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 624(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a2, a0
-; RV32I-NEXT: sw a0, 656(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 636(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 524(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 612(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 620(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a2, a0
-; RV32I-NEXT: sw a0, 648(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 632(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 424(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 604(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 612(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a2, a0
-; RV32I-NEXT: sw a0, 628(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 592(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, s11
-; RV32I-NEXT: sw a0, 668(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 704(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor ra, ra, a0
+; RV32I-NEXT: sw a0, 624(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 600(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 596(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a0, a0, a2
+; RV32I-NEXT: sw a0, 692(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 700(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 592(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s5, a2, a0
; RV32I-NEXT: lw a0, 608(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 632(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s7, a2, a0
-; RV32I-NEXT: lw a0, 528(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s8, s10, a0
-; RV32I-NEXT: lw a0, 428(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a2, 588(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s11, a2, a0
-; RV32I-NEXT: lw a0, 376(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli s6, a0, 4
+; RV32I-NEXT: xor s6, a2, a0
+; RV32I-NEXT: lw a0, 532(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 572(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s7, a2, a0
+; RV32I-NEXT: lw a0, 432(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 564(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a0, a2, a0
+; RV32I-NEXT: sw a0, 620(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 548(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 544(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a0, a0, a2
+; RV32I-NEXT: sw a0, 700(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 704(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 540(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s3, a2, a0
+; RV32I-NEXT: lw a0, 616(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 560(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, a2, a0
+; RV32I-NEXT: lw a0, 536(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s4, s9, a0
+; RV32I-NEXT: lw a0, 436(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a0, s10, a0
+; RV32I-NEXT: sw a0, 616(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 384(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli s9, a0, 4
; RV32I-NEXT: and s10, a0, a1
-; RV32I-NEXT: and s6, s6, a1
+; RV32I-NEXT: and s9, s9, a1
; RV32I-NEXT: slli s10, s10, 4
-; RV32I-NEXT: or a0, s6, s10
-; RV32I-NEXT: sw a0, 704(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 384(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli s10, a0, 4
+; RV32I-NEXT: or a0, s9, s10
+; RV32I-NEXT: sw a0, 612(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 392(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli s9, a0, 4
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: and s10, s10, a1
+; RV32I-NEXT: and s9, s9, a1
; RV32I-NEXT: slli a0, a0, 4
-; RV32I-NEXT: or a0, s10, a0
-; RV32I-NEXT: sw a0, 700(sp) # 4-byte Folded Spill
+; RV32I-NEXT: or a0, s9, a0
+; RV32I-NEXT: sw a0, 704(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 696(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, a0, s5
+; RV32I-NEXT: xor s9, a0, s1
; RV32I-NEXT: lw a0, 336(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 692(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s5, a1, a0
+; RV32I-NEXT: xor s0, s2, a0
; RV32I-NEXT: lw a0, 236(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s1, s4, a0
+; RV32I-NEXT: lw s1, 688(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s1, s1, a0
; RV32I-NEXT: lw a0, 152(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a1, 684(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s2, a1, a0
; RV32I-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a1, 680(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s3, a1, a0
-; RV32I-NEXT: xor s4, s0, t1
+; RV32I-NEXT: xor t5, a1, a0
+; RV32I-NEXT: lw a0, 676(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t6, a0, t1
; RV32I-NEXT: lw a0, 340(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s0, t2, a0
+; RV32I-NEXT: xor t4, t3, a0
; RV32I-NEXT: lw a0, 240(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t3, t3, a0
+; RV32I-NEXT: lw a1, 672(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t1, a1, a0
; RV32I-NEXT: lw a0, 160(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t4, t4, a0
+; RV32I-NEXT: lw a1, 664(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t2, a1, a0
; RV32I-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t5, t5, a0
-; RV32I-NEXT: xor t6, a7, t6
-; RV32I-NEXT: lw a0, 352(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 656(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t3, a1, a0
+; RV32I-NEXT: lw a0, 644(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor ra, a0, ra
+; RV32I-NEXT: lw a0, 356(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a1, 640(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t0, a1, a0
; RV32I-NEXT: lw a0, 252(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t1, a3, a0
+; RV32I-NEXT: xor a5, a3, a0
; RV32I-NEXT: lw a0, 164(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t2, a4, a0
+; RV32I-NEXT: xor a6, a4, a0
; RV32I-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 636(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 628(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a7, a1, a0
-; RV32I-NEXT: xor s9, a5, s9
-; RV32I-NEXT: lw a0, 644(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a4, a6, a0
-; RV32I-NEXT: lw a0, 544(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a5, 676(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a5, a5, a0
-; RV32I-NEXT: lw a0, 448(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 672(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a6, a1, a0
-; RV32I-NEXT: lw a0, 688(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a3, 664(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a3, a0, a3
+; RV32I-NEXT: lw a0, 648(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s11, a0, s11
; RV32I-NEXT: lw a0, 652(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 656(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a1, a0
-; RV32I-NEXT: lw a1, 548(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 648(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a1, a2, a1
-; RV32I-NEXT: lw a2, 452(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s10, 628(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a2, s10, a2
-; RV32I-NEXT: lw s10, 668(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor ra, s10, ra
-; RV32I-NEXT: lw s10, 660(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s7, s7, s10
-; RV32I-NEXT: lw s10, 560(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s8, s8, s10
-; RV32I-NEXT: lw s10, 464(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s11, s11, s10
-; RV32I-NEXT: xor s5, s6, s5
-; RV32I-NEXT: lw s6, 272(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s1, s1, s6
-; RV32I-NEXT: lw s6, 176(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s2, s2, s6
-; RV32I-NEXT: lw s6, 84(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s3, s3, s6
-; RV32I-NEXT: xor s0, s4, s0
-; RV32I-NEXT: lw s4, 276(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t3, t3, s4
-; RV32I-NEXT: lw s4, 180(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t4, t4, s4
-; RV32I-NEXT: lw s4, 88(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t5, t5, s4
-; RV32I-NEXT: xor t0, t6, t0
-; RV32I-NEXT: lw t6, 284(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 636(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a3, a3, a0
+; RV32I-NEXT: lw a0, 552(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 632(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a4, a4, a0
+; RV32I-NEXT: lw a0, 456(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 624(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, a0
+; RV32I-NEXT: lw a0, 692(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s5, a0, s5
+; RV32I-NEXT: lw a0, 660(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s6, s6, a0
+; RV32I-NEXT: lw a0, 556(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s7, s7, a0
+; RV32I-NEXT: lw a0, 460(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 620(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a0
+; RV32I-NEXT: lw a0, 700(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s3, a0, s3
+; RV32I-NEXT: lw a0, 668(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s8, a0
+; RV32I-NEXT: lw a0, 568(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s4, s4, a0
+; RV32I-NEXT: lw a0, 472(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s10, 616(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a0, s10, a0
+; RV32I-NEXT: xor s0, s9, s0
+; RV32I-NEXT: lw s9, 272(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s1, s1, s9
+; RV32I-NEXT: lw s9, 176(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s2, s2, s9
+; RV32I-NEXT: lw s9, 84(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t5, t5, s9
+; RV32I-NEXT: xor t4, t6, t4
+; RV32I-NEXT: lw t6, 276(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t1, t1, t6
-; RV32I-NEXT: lw t6, 184(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t6, 180(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t2, t2, t6
+; RV32I-NEXT: lw t6, 88(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t3, t3, t6
+; RV32I-NEXT: xor t0, ra, t0
+; RV32I-NEXT: lw t6, 284(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a5, a5, t6
+; RV32I-NEXT: lw t6, 184(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a6, a6, t6
; RV32I-NEXT: lw t6, 92(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a7, a7, t6
-; RV32I-NEXT: xor a4, s9, a4
-; RV32I-NEXT: lw t6, 568(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t6, a5, t6
-; RV32I-NEXT: lw a5, 472(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a6, a6, a5
-; RV32I-NEXT: xor a0, a3, a0
-; RV32I-NEXT: lw a3, 572(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: lw a3, 476(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: xor a3, ra, s7
-; RV32I-NEXT: lw a5, 576(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s4, s8, a5
-; RV32I-NEXT: lw a5, 480(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, s11, a5
-; RV32I-NEXT: xor s1, s5, s1
-; RV32I-NEXT: lw a5, 196(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s2, s2, a5
-; RV32I-NEXT: lw a5, 100(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s3, s3, a5
-; RV32I-NEXT: xor t3, s0, t3
-; RV32I-NEXT: lw a5, 200(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t4, t4, a5
-; RV32I-NEXT: lw a5, 104(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t5, t5, a5
-; RV32I-NEXT: xor t0, t0, t1
-; RV32I-NEXT: lw a5, 208(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t1, t2, a5
-; RV32I-NEXT: lw a5, 112(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a7, a7, a5
-; RV32I-NEXT: lw t2, 708(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a5, t2, 2
-; RV32I-NEXT: lw s5, 740(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t2, t2, s5
-; RV32I-NEXT: and a5, a5, s5
-; RV32I-NEXT: slli t2, t2, 2
-; RV32I-NEXT: or t2, a5, t2
-; RV32I-NEXT: lw s0, 712(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a5, s0, 2
-; RV32I-NEXT: and s0, s0, s5
-; RV32I-NEXT: and a5, a5, s5
-; RV32I-NEXT: slli s0, s0, 2
-; RV32I-NEXT: or a5, a5, s0
+; RV32I-NEXT: xor a3, s11, a3
+; RV32I-NEXT: lw t6, 576(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a4, a4, t6
-; RV32I-NEXT: lw t6, 492(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t6, a6, t6
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: lw a1, 488(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a1, a2, a1
-; RV32I-NEXT: xor a2, a3, s4
-; RV32I-NEXT: lw a3, 496(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a3, s6, a3
-; RV32I-NEXT: lw s0, 704(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a6, s0, 2
-; RV32I-NEXT: and s0, s0, s5
-; RV32I-NEXT: and a6, a6, s5
-; RV32I-NEXT: slli s0, s0, 2
-; RV32I-NEXT: or s0, a6, s0
-; RV32I-NEXT: lw s4, 700(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a6, s4, 2
-; RV32I-NEXT: and s4, s4, s5
-; RV32I-NEXT: and a6, a6, s5
-; RV32I-NEXT: slli s4, s4, 2
-; RV32I-NEXT: or s4, a6, s4
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: lw a6, 132(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s2, s3, a6
+; RV32I-NEXT: lw t6, 480(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, t6
+; RV32I-NEXT: xor t6, s5, s6
+; RV32I-NEXT: lw s5, 580(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s5, s7, s5
+; RV32I-NEXT: lw s6, 484(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, s6
+; RV32I-NEXT: xor s3, s3, s8
+; RV32I-NEXT: lw s6, 584(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s4, s4, s6
+; RV32I-NEXT: lw s6, 488(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a0, a0, s6
+; RV32I-NEXT: xor s0, s0, s1
+; RV32I-NEXT: lw s1, 196(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s1, s2, s1
+; RV32I-NEXT: lw s2, 100(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t5, t5, s2
+; RV32I-NEXT: xor t1, t4, t1
+; RV32I-NEXT: lw t4, 200(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t2, t2, t4
+; RV32I-NEXT: lw t4, 104(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t3, t3, t4
-; RV32I-NEXT: lw a6, 124(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t4, t5, a6
-; RV32I-NEXT: xor t0, t0, t1
-; RV32I-NEXT: lw a6, 136(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a7, a7, a6
-; RV32I-NEXT: xor a4, a4, t6
+; RV32I-NEXT: xor a5, t0, a5
+; RV32I-NEXT: lw t0, 208(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t0, a6, t0
+; RV32I-NEXT: lw a6, 112(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t4, a7, a6
+; RV32I-NEXT: lw a7, 708(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a6, a7, 2
+; RV32I-NEXT: lw s6, 744(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, a7, s6
+; RV32I-NEXT: and a6, a6, s6
+; RV32I-NEXT: slli a7, a7, 2
+; RV32I-NEXT: or s2, a6, a7
+; RV32I-NEXT: lw a7, 712(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a6, a7, 2
+; RV32I-NEXT: and a7, a7, s6
+; RV32I-NEXT: and a6, a6, s6
+; RV32I-NEXT: slli a7, a7, 2
+; RV32I-NEXT: or a6, a6, a7
+; RV32I-NEXT: xor a3, a3, a4
+; RV32I-NEXT: lw a4, 500(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, a4
+; RV32I-NEXT: xor a4, t6, s5
+; RV32I-NEXT: lw a7, 496(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a7
+; RV32I-NEXT: xor t6, s3, s4
+; RV32I-NEXT: lw a7, 504(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a0, a0, a7
+; RV32I-NEXT: lw s3, 612(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a7, s3, 2
+; RV32I-NEXT: and s3, s3, s6
+; RV32I-NEXT: and a7, a7, s6
+; RV32I-NEXT: slli s3, s3, 2
+; RV32I-NEXT: or s3, a7, s3
+; RV32I-NEXT: lw s4, 704(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a7, s4, 2
+; RV32I-NEXT: and s4, s4, s6
+; RV32I-NEXT: and a7, a7, s6
+; RV32I-NEXT: mv s5, s6
+; RV32I-NEXT: slli s4, s4, 2
+; RV32I-NEXT: or s4, a7, s4
+; RV32I-NEXT: xor s0, s0, s1
+; RV32I-NEXT: lw a7, 132(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t5, t5, a7
+; RV32I-NEXT: xor t1, t1, t2
+; RV32I-NEXT: lw a7, 124(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t2, t3, a7
+; RV32I-NEXT: xor a5, a5, t0
+; RV32I-NEXT: lw a7, 136(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t0, t4, a7
+; RV32I-NEXT: xor a2, a3, a2
+; RV32I-NEXT: xor a1, a4, a1
+; RV32I-NEXT: xor a0, t6, a0
+; RV32I-NEXT: xor a3, s0, t5
+; RV32I-NEXT: xor a4, t1, t2
+; RV32I-NEXT: xor a5, a5, t0
+; RV32I-NEXT: lw a7, 728(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, a7
+; RV32I-NEXT: lw a7, 732(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t0, a1, a7
+; RV32I-NEXT: lw a1, 736(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: xor a1, s1, s2
-; RV32I-NEXT: xor a3, t3, t4
-; RV32I-NEXT: xor a7, t0, a7
-; RV32I-NEXT: lw a6, 720(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a4, a4, a6
-; RV32I-NEXT: lw a6, 728(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a6
-; RV32I-NEXT: lw a6, 736(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a2, a2, a6
-; RV32I-NEXT: lw a6, 724(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t0, a1, a6
-; RV32I-NEXT: lw a1, 732(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 720(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a3, a3, a1
+; RV32I-NEXT: lw a1, 724(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t1, a4, a1
; RV32I-NEXT: lw a1, 716(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a7, a7, a1
-; RV32I-NEXT: srli a1, t2, 1
-; RV32I-NEXT: lw s2, 744(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, t2, s2
-; RV32I-NEXT: and a1, a1, s2
-; RV32I-NEXT: slli t1, t1, 1
-; RV32I-NEXT: or a1, a1, t1
-; RV32I-NEXT: xor a0, a0, a4
-; RV32I-NEXT: sw a0, 736(sp) # 4-byte Folded Spill
-; RV32I-NEXT: srli a0, s0, 1
-; RV32I-NEXT: and a4, s0, s2
-; RV32I-NEXT: and a0, a0, s2
+; RV32I-NEXT: xor a5, a5, a1
+; RV32I-NEXT: srli a7, s2, 1
+; RV32I-NEXT: lw t2, 740(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a1, s2, t2
+; RV32I-NEXT: slli a1, a1, 1
+; RV32I-NEXT: and a4, a7, t2
+; RV32I-NEXT: or a1, a4, a1
+; RV32I-NEXT: xor a2, t0, a2
+; RV32I-NEXT: sw a2, 736(sp) # 4-byte Folded Spill
+; RV32I-NEXT: srli a2, s3, 1
+; RV32I-NEXT: and a4, s3, t2
; RV32I-NEXT: slli a4, a4, 1
-; RV32I-NEXT: or t2, a0, a4
-; RV32I-NEXT: xor a0, a3, t0
-; RV32I-NEXT: sw a0, 732(sp) # 4-byte Folded Spill
-; RV32I-NEXT: srli a0, a2, 8
-; RV32I-NEXT: lw a6, 756(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a0, a0, a6
-; RV32I-NEXT: srli a3, a2, 24
-; RV32I-NEXT: or a3, a0, a3
-; RV32I-NEXT: slli a0, a2, 24
-; RV32I-NEXT: and a2, a2, a6
-; RV32I-NEXT: slli a2, a2, 8
-; RV32I-NEXT: or a2, a0, a2
-; RV32I-NEXT: srli a0, a7, 8
-; RV32I-NEXT: and a0, a0, a6
-; RV32I-NEXT: srli a4, a7, 24
-; RV32I-NEXT: or a4, a0, a4
-; RV32I-NEXT: slli a0, a7, 24
-; RV32I-NEXT: and a7, a7, a6
-; RV32I-NEXT: slli a7, a7, 8
-; RV32I-NEXT: or a7, a0, a7
-; RV32I-NEXT: srli a0, a5, 1
-; RV32I-NEXT: and a5, a5, s2
+; RV32I-NEXT: and t0, a2, t2
+; RV32I-NEXT: mv s2, t2
+; RV32I-NEXT: or t2, t0, a4
+; RV32I-NEXT: xor a3, t1, a3
+; RV32I-NEXT: sw a3, 732(sp) # 4-byte Folded Spill
+; RV32I-NEXT: srli a3, a0, 8
+; RV32I-NEXT: lw a4, 756(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a3, a3, a4
+; RV32I-NEXT: srli t0, a0, 24
+; RV32I-NEXT: or a3, a3, t0
+; RV32I-NEXT: slli t0, a0, 24
+; RV32I-NEXT: and a0, a0, a4
+; RV32I-NEXT: slli a0, a0, 8
+; RV32I-NEXT: or t0, t0, a0
+; RV32I-NEXT: srli a0, a5, 8
+; RV32I-NEXT: and a0, a0, a4
+; RV32I-NEXT: srli t1, a5, 24
+; RV32I-NEXT: or t1, a0, t1
+; RV32I-NEXT: slli a0, a5, 24
+; RV32I-NEXT: and a5, a5, a4
+; RV32I-NEXT: slli a5, a5, 8
+; RV32I-NEXT: or a5, a0, a5
+; RV32I-NEXT: srli a0, a6, 1
+; RV32I-NEXT: and a6, a6, s2
; RV32I-NEXT: and a0, a0, s2
-; RV32I-NEXT: slli a5, a5, 1
-; RV32I-NEXT: or a0, a0, a5
-; RV32I-NEXT: srli a5, a5, 31
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli t0, a1, 31
-; RV32I-NEXT: and a5, a5, t0
-; RV32I-NEXT: sw a5, 720(sp) # 4-byte Folded Spill
-; RV32I-NEXT: or a2, a2, a3
-; RV32I-NEXT: sw a2, 716(sp) # 4-byte Folded Spill
-; RV32I-NEXT: srli a2, s4, 1
-; RV32I-NEXT: and a3, s4, s2
-; RV32I-NEXT: and a2, a2, s2
-; RV32I-NEXT: slli a3, a3, 1
-; RV32I-NEXT: or t4, a2, a3
-; RV32I-NEXT: srli a3, a3, 31
-; RV32I-NEXT: seqz a2, a3
-; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli a3, t2, 31
-; RV32I-NEXT: and a2, a2, a3
+; RV32I-NEXT: slli a6, a6, 1
+; RV32I-NEXT: slli a7, a7, 31
+; RV32I-NEXT: or a0, a0, a6
+; RV32I-NEXT: srli a6, a6, 31
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 720(sp) # 4-byte Folded Spill
+; RV32I-NEXT: or a3, t0, a3
+; RV32I-NEXT: sw a3, 716(sp) # 4-byte Folded Spill
+; RV32I-NEXT: srli a3, s4, 1
+; RV32I-NEXT: and a6, s4, s2
+; RV32I-NEXT: and a3, a3, s2
+; RV32I-NEXT: slli a6, a6, 1
+; RV32I-NEXT: slli a2, a2, 31
+; RV32I-NEXT: or t4, a3, a6
+; RV32I-NEXT: srli a3, a6, 31
+; RV32I-NEXT: seqz a3, a3
+; RV32I-NEXT: addi a3, a3, -1
+; RV32I-NEXT: and a2, a3, a2
; RV32I-NEXT: sw a2, 728(sp) # 4-byte Folded Spill
-; RV32I-NEXT: or a2, a7, a4
+; RV32I-NEXT: or a2, a5, t1
; RV32I-NEXT: sw a2, 724(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a2, a0, 2
; RV32I-NEXT: seqz a2, a2
@@ -4262,7 +4278,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: slli a3, a1, 10
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: sw a2, 708(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a4, 456(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 464(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a2, a0, a4
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
@@ -4276,8 +4292,8 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: slli a3, a1, 12
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: sw a2, 644(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a6, 2
-; RV32I-NEXT: and a2, a0, a6
+; RV32I-NEXT: lui s1, 2
+; RV32I-NEXT: and a2, a0, s1
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a3, a1, 13
@@ -4304,8 +4320,8 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: slli a3, a1, 16
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: sw a2, 628(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui s3, 32
-; RV32I-NEXT: and a2, a0, s3
+; RV32I-NEXT: lui t3, 32
+; RV32I-NEXT: and a2, a0, t3
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a3, a1, 17
@@ -4401,8 +4417,8 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: and a2, a2, a1
; RV32I-NEXT: sw a2, 592(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a1, a1, 30
-; RV32I-NEXT: lui t3, 262144
-; RV32I-NEXT: and a0, a0, t3
+; RV32I-NEXT: lui a6, 262144
+; RV32I-NEXT: and a0, a0, a6
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and a0, a0, a1
@@ -4478,7 +4494,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli a1, t2, 12
; RV32I-NEXT: and s9, a0, a1
-; RV32I-NEXT: and a0, t4, a6
+; RV32I-NEXT: and a0, t4, s1
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli s1, t2, 13
@@ -4499,9 +4515,9 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: and a0, t4, t1
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
-; RV32I-NEXT: slli a4, t2, 16
-; RV32I-NEXT: and s7, a0, a4
-; RV32I-NEXT: and a0, t4, s3
+; RV32I-NEXT: slli a1, t2, 16
+; RV32I-NEXT: and s7, a0, a1
+; RV32I-NEXT: and a0, t4, t3
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli a2, t2, 17
@@ -4554,35 +4570,35 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: and a5, t4, a0
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a7, t2, 26
-; RV32I-NEXT: and s6, a5, a7
+; RV32I-NEXT: slli t0, t2, 26
+; RV32I-NEXT: and s6, a5, t0
; RV32I-NEXT: lui a0, 32768
-; RV32I-NEXT: and a7, t4, a0
-; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: slli t0, t2, 27
-; RV32I-NEXT: and s8, a7, t0
-; RV32I-NEXT: lui a0, 65536
; RV32I-NEXT: and t0, t4, a0
; RV32I-NEXT: seqz t0, t0
; RV32I-NEXT: addi t0, t0, -1
-; RV32I-NEXT: slli t1, t2, 28
-; RV32I-NEXT: and s10, t0, t1
-; RV32I-NEXT: lui a0, 131072
+; RV32I-NEXT: slli t1, t2, 27
+; RV32I-NEXT: and s8, t0, t1
+; RV32I-NEXT: lui a0, 65536
; RV32I-NEXT: and t1, t4, a0
; RV32I-NEXT: seqz t1, t1
; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: slli a6, t2, 29
-; RV32I-NEXT: and t5, t1, a6
-; RV32I-NEXT: and t1, t4, t3
+; RV32I-NEXT: slli a4, t2, 28
+; RV32I-NEXT: and s10, t1, a4
+; RV32I-NEXT: lui a0, 131072
+; RV32I-NEXT: and a4, t4, a0
+; RV32I-NEXT: seqz a4, a4
+; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: slli a7, t2, 29
+; RV32I-NEXT: and t5, a4, a7
+; RV32I-NEXT: and a7, t4, a6
; RV32I-NEXT: andi t4, t4, 1
; RV32I-NEXT: seqz t4, t4
; RV32I-NEXT: addi t4, t4, -1
; RV32I-NEXT: and t4, t4, t2
; RV32I-NEXT: slli t2, t2, 30
-; RV32I-NEXT: seqz t1, t1
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: and t1, t1, t2
+; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: and a7, a7, t2
; RV32I-NEXT: lw a0, 712(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a1, 592(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t2, a1, a0
@@ -4605,16 +4621,16 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: lw a6, 604(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: lw a6, 600(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a7, 596(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a6, a6, a7
-; RV32I-NEXT: lw a7, 588(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t4, t4, a7
-; RV32I-NEXT: lw a7, 584(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t0, 572(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: lw t0, 568(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t0, 596(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a6, a6, t0
+; RV32I-NEXT: lw t0, 588(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t4, t4, t0
+; RV32I-NEXT: lw t0, 584(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 572(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t0, t0, t1
+; RV32I-NEXT: lw t1, 568(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw t3, 564(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t0, t0, t3
+; RV32I-NEXT: xor t1, t1, t3
; RV32I-NEXT: lw t3, 548(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 544(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t3, t3, ra
@@ -4622,7 +4638,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: xor s9, ra, s9
; RV32I-NEXT: xor s3, s7, s3
; RV32I-NEXT: xor t6, s0, t6
-; RV32I-NEXT: xor t1, t5, t1
+; RV32I-NEXT: xor a7, t5, a7
; RV32I-NEXT: xor a0, t2, a0
; RV32I-NEXT: lw t2, 700(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a1, a1, t2
@@ -4643,9 +4659,9 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: and a4, a4, s7
; RV32I-NEXT: slli t5, t5, 4
; RV32I-NEXT: or t5, a4, t5
-; RV32I-NEXT: xor a7, t4, a7
+; RV32I-NEXT: xor t0, t4, t0
; RV32I-NEXT: lw a4, 580(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t0, t0, a4
+; RV32I-NEXT: xor t1, t1, a4
; RV32I-NEXT: lw a4, 560(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t3, t3, a4
; RV32I-NEXT: lw a4, 540(sp) # 4-byte Folded Reload
@@ -4653,13 +4669,13 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: xor s0, s3, s11
; RV32I-NEXT: xor t6, t6, s1
; RV32I-NEXT: lw a4, 728(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a4, t1, a4
+; RV32I-NEXT: xor a4, a7, a4
; RV32I-NEXT: lw s1, 724(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli t1, s1, 4
+; RV32I-NEXT: srli a7, s1, 4
; RV32I-NEXT: and s1, s1, s7
-; RV32I-NEXT: and t1, t1, s7
+; RV32I-NEXT: and a7, a7, s7
; RV32I-NEXT: slli s1, s1, 4
-; RV32I-NEXT: or t1, t1, s1
+; RV32I-NEXT: or a7, a7, s1
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: lw a1, 708(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a1, a2, a1
@@ -4669,9 +4685,9 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: xor a3, t2, a3
; RV32I-NEXT: lw t2, 616(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a5, a5, t2
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: lw t0, 576(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t0, t3, t0
+; RV32I-NEXT: xor t0, t0, t1
+; RV32I-NEXT: lw t1, 576(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t1, t3, t1
; RV32I-NEXT: lw t2, 552(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t2, t4, t2
; RV32I-NEXT: lw t3, 524(sp) # 4-byte Folded Reload
@@ -4684,11 +4700,11 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: xor a2, a3, a2
; RV32I-NEXT: lw a3, 624(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a3, a5, a3
-; RV32I-NEXT: xor a5, a7, t0
-; RV32I-NEXT: lw a7, 556(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a7, t2, a7
-; RV32I-NEXT: lw t0, 528(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t0, t3, t0
+; RV32I-NEXT: xor a5, t0, t1
+; RV32I-NEXT: lw t0, 556(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t0, t2, t0
+; RV32I-NEXT: lw t1, 528(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t1, t3, t1
; RV32I-NEXT: xor t2, t4, s6
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: lw a1, 664(sp) # 4-byte Folded Reload
@@ -4700,34 +4716,34 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: and a3, a3, s5
; RV32I-NEXT: slli t3, t3, 2
; RV32I-NEXT: or a3, a3, t3
-; RV32I-NEXT: xor a5, a5, a7
-; RV32I-NEXT: lw a7, 536(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a7, t0, a7
-; RV32I-NEXT: xor t0, t2, s8
-; RV32I-NEXT: srli t2, t1, 2
-; RV32I-NEXT: and t1, t1, s5
+; RV32I-NEXT: xor a5, a5, t0
+; RV32I-NEXT: lw t0, 536(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t0, t1, t0
+; RV32I-NEXT: xor t1, t2, s8
+; RV32I-NEXT: srli t2, a7, 2
+; RV32I-NEXT: and a7, a7, s5
; RV32I-NEXT: and t2, t2, s5
-; RV32I-NEXT: slli t1, t1, 2
-; RV32I-NEXT: or t1, t2, t1
+; RV32I-NEXT: slli a7, a7, 2
+; RV32I-NEXT: or a7, t2, a7
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: lw a1, 640(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a2, a2, a1
-; RV32I-NEXT: xor a5, a5, a7
-; RV32I-NEXT: xor a7, t0, s10
+; RV32I-NEXT: xor a5, a5, t0
+; RV32I-NEXT: xor t0, t1, s10
; RV32I-NEXT: srli a1, a3, 1
; RV32I-NEXT: xor a2, a0, a2
-; RV32I-NEXT: srli a0, t1, 1
+; RV32I-NEXT: srli a0, a7, 1
; RV32I-NEXT: and a3, a3, s2
-; RV32I-NEXT: and t0, t1, s2
-; RV32I-NEXT: xor a5, a5, a7
-; RV32I-NEXT: and a7, a1, s2
+; RV32I-NEXT: and a7, a7, s2
+; RV32I-NEXT: xor a5, a5, t0
+; RV32I-NEXT: and t0, a1, s2
; RV32I-NEXT: slli a3, a3, 1
; RV32I-NEXT: xor a6, a2, a6
; RV32I-NEXT: and t1, a0, s2
-; RV32I-NEXT: slli t0, t0, 1
+; RV32I-NEXT: slli a7, a7, 1
; RV32I-NEXT: xor a4, a5, a4
-; RV32I-NEXT: or a2, a7, a3
-; RV32I-NEXT: or a3, t1, t0
+; RV32I-NEXT: or a2, t0, a3
+; RV32I-NEXT: or a3, t1, a7
; RV32I-NEXT: srli a5, a6, 8
; RV32I-NEXT: srli a7, a6, 24
; RV32I-NEXT: slli t0, a6, 24
@@ -4885,131 +4901,132 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64I-NEXT: sd s11, 1016(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a5, 1008(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a4, 1000(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv a4, a0
-; RV64I-NEXT: srli a5, a2, 24
-; RV64I-NEXT: lui s3, 4080
-; RV64I-NEXT: srli a6, a2, 8
+; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: srli a4, a2, 24
+; RV64I-NEXT: lui t6, 4080
+; RV64I-NEXT: srli a7, a2, 8
; RV64I-NEXT: li t4, 255
; RV64I-NEXT: srli t0, a2, 40
-; RV64I-NEXT: lui a0, 16
-; RV64I-NEXT: srli t1, a2, 56
-; RV64I-NEXT: srliw t2, a2, 24
-; RV64I-NEXT: slli a7, a2, 56
-; RV64I-NEXT: lui s6, 61681
-; RV64I-NEXT: lui t6, 209715
-; RV64I-NEXT: lui s4, 349525
-; RV64I-NEXT: srli s5, a4, 24
-; RV64I-NEXT: srli t3, a4, 8
-; RV64I-NEXT: srli t5, a4, 40
-; RV64I-NEXT: srli s2, a4, 56
-; RV64I-NEXT: srliw s0, a4, 24
-; RV64I-NEXT: slli ra, a4, 56
+; RV64I-NEXT: lui s2, 16
+; RV64I-NEXT: srli a5, a2, 56
+; RV64I-NEXT: srliw t1, a2, 24
+; RV64I-NEXT: slli a0, a2, 56
+; RV64I-NEXT: sd a0, 952(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui t2, 61681
+; RV64I-NEXT: lui s11, 209715
+; RV64I-NEXT: lui s1, 349525
+; RV64I-NEXT: srli t3, s4, 24
+; RV64I-NEXT: srli s3, s4, 8
+; RV64I-NEXT: srli a6, s4, 40
+; RV64I-NEXT: srli t5, s4, 56
+; RV64I-NEXT: srliw s5, s4, 24
+; RV64I-NEXT: slli ra, s4, 56
; RV64I-NEXT: srli s8, a3, 24
; RV64I-NEXT: srli s10, a3, 8
; RV64I-NEXT: srli s7, a3, 40
; RV64I-NEXT: srli s9, a3, 56
-; RV64I-NEXT: and a5, a5, s3
-; RV64I-NEXT: slli s1, t4, 24
-; RV64I-NEXT: and a6, a6, s1
-; RV64I-NEXT: or a6, a6, a5
-; RV64I-NEXT: addi a0, a0, -256
-; RV64I-NEXT: and a5, t0, a0
-; RV64I-NEXT: or t0, a5, t1
-; RV64I-NEXT: and a5, a2, s3
-; RV64I-NEXT: slli t2, t2, 32
-; RV64I-NEXT: addi t1, s6, -241
-; RV64I-NEXT: addi s11, t6, 819
-; RV64I-NEXT: addi t4, s4, 1365
-; RV64I-NEXT: slli a5, a5, 24
-; RV64I-NEXT: or a5, a5, t2
-; RV64I-NEXT: slli s4, t1, 32
-; RV64I-NEXT: add s4, t1, s4
+; RV64I-NEXT: and a4, a4, t6
+; RV64I-NEXT: slli s0, t4, 24
+; RV64I-NEXT: and a7, a7, s0
+; RV64I-NEXT: or a7, a7, a4
+; RV64I-NEXT: addi a0, s2, -256
+; RV64I-NEXT: and a4, t0, a0
+; RV64I-NEXT: or a5, a4, a5
+; RV64I-NEXT: and a4, a2, t6
+; RV64I-NEXT: slli t1, t1, 32
+; RV64I-NEXT: addi s6, t2, -241
+; RV64I-NEXT: addi s11, s11, 819
+; RV64I-NEXT: addi t0, s1, 1365
+; RV64I-NEXT: slli a4, a4, 24
+; RV64I-NEXT: or a4, a4, t1
+; RV64I-NEXT: slli t1, s6, 32
+; RV64I-NEXT: add s6, s6, t1
; RV64I-NEXT: slli t1, s11, 32
; RV64I-NEXT: add s11, s11, t1
-; RV64I-NEXT: slli t1, t4, 32
-; RV64I-NEXT: add s6, t4, t1
-; RV64I-NEXT: srliw t2, a3, 24
-; RV64I-NEXT: and t1, s5, s3
-; RV64I-NEXT: and t3, t3, s1
-; RV64I-NEXT: or t1, t3, t1
-; RV64I-NEXT: srli t3, a1, 24
-; RV64I-NEXT: and t4, t5, a0
-; RV64I-NEXT: or t4, t4, s2
-; RV64I-NEXT: and t5, a4, s3
-; RV64I-NEXT: slli s0, s0, 32
+; RV64I-NEXT: slli t1, t0, 32
+; RV64I-NEXT: add s2, t0, t1
+; RV64I-NEXT: srliw t1, a3, 24
+; RV64I-NEXT: and t0, t3, t6
+; RV64I-NEXT: and t2, s3, s0
+; RV64I-NEXT: or t0, t2, t0
+; RV64I-NEXT: srli t2, a1, 24
+; RV64I-NEXT: and a6, a6, a0
+; RV64I-NEXT: or a6, a6, t5
+; RV64I-NEXT: and t3, s4, t6
+; RV64I-NEXT: slli s5, s5, 32
+; RV64I-NEXT: slli t3, t3, 24
+; RV64I-NEXT: or t3, t3, s5
+; RV64I-NEXT: srli t4, a1, 8
+; RV64I-NEXT: and t5, s8, t6
+; RV64I-NEXT: mv s5, s0
+; RV64I-NEXT: sd s0, 992(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and s0, s10, s0
+; RV64I-NEXT: or s0, s0, t5
+; RV64I-NEXT: srli t5, a1, 40
+; RV64I-NEXT: and s1, s7, a0
+; RV64I-NEXT: or s1, s1, s9
+; RV64I-NEXT: and s3, a3, t6
+; RV64I-NEXT: slli t1, t1, 32
+; RV64I-NEXT: slli s3, s3, 24
+; RV64I-NEXT: or t1, s3, t1
+; RV64I-NEXT: srli s3, a1, 56
+; RV64I-NEXT: and t2, t2, t6
+; RV64I-NEXT: and t4, t4, s5
+; RV64I-NEXT: or t2, t4, t2
+; RV64I-NEXT: srliw t4, a1, 24
+; RV64I-NEXT: and t5, t5, a0
+; RV64I-NEXT: or s3, t5, s3
+; RV64I-NEXT: and t5, a1, t6
+; RV64I-NEXT: slli t4, t4, 32
; RV64I-NEXT: slli t5, t5, 24
-; RV64I-NEXT: or t6, t5, s0
-; RV64I-NEXT: srli t5, a1, 8
-; RV64I-NEXT: and s0, s8, s3
-; RV64I-NEXT: mv s8, s1
-; RV64I-NEXT: sd s1, 992(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and s1, s10, s1
-; RV64I-NEXT: or s0, s1, s0
-; RV64I-NEXT: srli s1, a1, 40
-; RV64I-NEXT: and s2, s7, a0
-; RV64I-NEXT: or s2, s2, s9
-; RV64I-NEXT: and s5, a3, s3
-; RV64I-NEXT: slli t2, t2, 32
-; RV64I-NEXT: slli s5, s5, 24
-; RV64I-NEXT: or t2, s5, t2
-; RV64I-NEXT: srli s5, a1, 56
-; RV64I-NEXT: and t3, t3, s3
-; RV64I-NEXT: and t5, t5, s8
-; RV64I-NEXT: or t3, t5, t3
-; RV64I-NEXT: srliw t5, a1, 24
-; RV64I-NEXT: and s1, s1, a0
-; RV64I-NEXT: or s1, s1, s5
-; RV64I-NEXT: and s5, a1, s3
-; RV64I-NEXT: slli t5, t5, 32
-; RV64I-NEXT: slli s5, s5, 24
-; RV64I-NEXT: or s5, s5, t5
+; RV64I-NEXT: or t4, t5, t4
; RV64I-NEXT: li t5, 1
-; RV64I-NEXT: or a6, a6, t0
-; RV64I-NEXT: slli t0, a3, 56
-; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: or a5, a7, a5
+; RV64I-NEXT: slli a7, a3, 56
+; RV64I-NEXT: mv s5, a0
; RV64I-NEXT: sd a0, 976(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a2, a2, a0
; RV64I-NEXT: slli a2, a2, 40
-; RV64I-NEXT: or a2, a7, a2
-; RV64I-NEXT: slli a7, a1, 56
-; RV64I-NEXT: or t1, t1, t4
+; RV64I-NEXT: ld a0, 952(sp) # 8-byte Folded Reload
+; RV64I-NEXT: or a2, a0, a2
+; RV64I-NEXT: slli t6, a1, 56
+; RV64I-NEXT: or a6, t0, a6
; RV64I-NEXT: slli s7, t5, 11
-; RV64I-NEXT: sd s7, 440(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a0, a4, a0
-; RV64I-NEXT: and a3, a3, s3
-; RV64I-NEXT: and a1, a1, s3
+; RV64I-NEXT: and a0, s4, s5
+; RV64I-NEXT: and a3, a3, s5
+; RV64I-NEXT: and a1, a1, s5
; RV64I-NEXT: slli a0, a0, 40
; RV64I-NEXT: slli a3, a3, 40
; RV64I-NEXT: slli a1, a1, 40
; RV64I-NEXT: or a0, ra, a0
-; RV64I-NEXT: or a4, s0, s2
-; RV64I-NEXT: or a3, t0, a3
-; RV64I-NEXT: or t0, t3, s1
-; RV64I-NEXT: or a1, a7, a1
+; RV64I-NEXT: or s0, s0, s1
+; RV64I-NEXT: or a3, a7, a3
+; RV64I-NEXT: or a7, t2, s3
+; RV64I-NEXT: or a1, t6, a1
+; RV64I-NEXT: or a2, a2, a4
+; RV64I-NEXT: or a0, a0, t3
+; RV64I-NEXT: or a3, a3, t1
+; RV64I-NEXT: or a1, a1, t4
; RV64I-NEXT: or a2, a2, a5
-; RV64I-NEXT: or a0, a0, t6
-; RV64I-NEXT: or a3, a3, t2
-; RV64I-NEXT: or a1, a1, s5
-; RV64I-NEXT: or a2, a2, a6
-; RV64I-NEXT: or a0, a0, t1
-; RV64I-NEXT: or a3, a3, a4
-; RV64I-NEXT: or a1, a1, t0
+; RV64I-NEXT: or a0, a0, a6
+; RV64I-NEXT: or a3, a3, s0
+; RV64I-NEXT: or a1, a1, a7
; RV64I-NEXT: srli a4, a2, 4
-; RV64I-NEXT: sd s4, 984(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, a2, s4
+; RV64I-NEXT: sd s6, 984(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a2, a2, s6
; RV64I-NEXT: srli a5, a0, 4
-; RV64I-NEXT: and a0, a0, s4
+; RV64I-NEXT: and a0, a0, s6
; RV64I-NEXT: srli a6, a3, 4
-; RV64I-NEXT: and a3, a3, s4
+; RV64I-NEXT: and a3, a3, s6
; RV64I-NEXT: srli a7, a1, 4
-; RV64I-NEXT: and a1, a1, s4
-; RV64I-NEXT: and a4, a4, s4
+; RV64I-NEXT: and a1, a1, s6
+; RV64I-NEXT: and a4, a4, s6
; RV64I-NEXT: slli a2, a2, 4
-; RV64I-NEXT: and a5, a5, s4
+; RV64I-NEXT: and a5, a5, s6
; RV64I-NEXT: slli a0, a0, 4
-; RV64I-NEXT: and a6, a6, s4
+; RV64I-NEXT: and a6, a6, s6
; RV64I-NEXT: slli a3, a3, 4
-; RV64I-NEXT: and a7, a7, s4
+; RV64I-NEXT: and a7, a7, s6
; RV64I-NEXT: slli a1, a1, 4
; RV64I-NEXT: or a2, a4, a2
; RV64I-NEXT: or a0, a5, a0
@@ -5035,911 +5052,911 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64I-NEXT: or a2, a4, a2
; RV64I-NEXT: or a0, a5, a0
; RV64I-NEXT: or a3, a6, a3
-; RV64I-NEXT: or a1, a7, a1
-; RV64I-NEXT: srli a4, a2, 1
-; RV64I-NEXT: sd s6, 960(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, a2, s6
-; RV64I-NEXT: srli a5, a0, 1
-; RV64I-NEXT: and a0, a0, s6
-; RV64I-NEXT: srli a6, a3, 1
-; RV64I-NEXT: and a3, a3, s6
-; RV64I-NEXT: srli a7, a1, 1
-; RV64I-NEXT: and a1, a1, s6
-; RV64I-NEXT: and a4, a4, s6
-; RV64I-NEXT: slli a2, a2, 1
-; RV64I-NEXT: and a5, a5, s6
-; RV64I-NEXT: slli a0, a0, 1
-; RV64I-NEXT: and a6, a6, s6
-; RV64I-NEXT: slli t0, a3, 1
-; RV64I-NEXT: and a7, a7, s6
-; RV64I-NEXT: slli a3, a1, 1
-; RV64I-NEXT: or s0, a4, a2
-; RV64I-NEXT: or s1, a5, a0
-; RV64I-NEXT: srli a2, a0, 63
-; RV64I-NEXT: or a1, a6, t0
-; RV64I-NEXT: or t0, a7, a3
-; RV64I-NEXT: srli a3, a3, 63
-; RV64I-NEXT: slli a4, s0, 1
-; RV64I-NEXT: andi a5, s1, 2
-; RV64I-NEXT: slli a6, s0, 2
-; RV64I-NEXT: andi a7, s1, 4
-; RV64I-NEXT: slli a0, s0, 3
-; RV64I-NEXT: andi t1, s1, 8
-; RV64I-NEXT: slli t2, s0, 4
-; RV64I-NEXT: andi t3, s1, 16
-; RV64I-NEXT: slli t4, s0, 5
-; RV64I-NEXT: andi t6, s1, 32
-; RV64I-NEXT: slli s2, s0, 63
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: and a2, a2, s2
-; RV64I-NEXT: sd a2, 944(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, a1, 63
-; RV64I-NEXT: seqz a3, a3
-; RV64I-NEXT: addi a3, a3, -1
-; RV64I-NEXT: and a2, a3, a2
-; RV64I-NEXT: sd a2, 952(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, s0, 6
-; RV64I-NEXT: seqz a3, a5
-; RV64I-NEXT: addi a3, a3, -1
-; RV64I-NEXT: and a3, a3, a4
-; RV64I-NEXT: sd a3, 456(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a3, s1, 64
-; RV64I-NEXT: seqz a4, a7
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: and a4, a4, a6
-; RV64I-NEXT: sd a4, 448(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a4, s0, 7
-; RV64I-NEXT: seqz a5, t1
+; RV64I-NEXT: or a4, a7, a1
+; RV64I-NEXT: srli a6, a2, 1
+; RV64I-NEXT: sd s2, 960(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a5, a2, s2
+; RV64I-NEXT: srli a7, a0, 1
+; RV64I-NEXT: and a0, a0, s2
+; RV64I-NEXT: srli a1, a3, 1
+; RV64I-NEXT: and t0, a3, s2
+; RV64I-NEXT: srli t1, a4, 1
+; RV64I-NEXT: and t2, a4, s2
+; RV64I-NEXT: and a2, a6, s2
+; RV64I-NEXT: slli a3, a5, 1
+; RV64I-NEXT: and a4, a7, s2
+; RV64I-NEXT: slli a5, a0, 1
+; RV64I-NEXT: slli a0, a6, 63
+; RV64I-NEXT: and a6, a1, s2
+; RV64I-NEXT: slli a7, t0, 1
+; RV64I-NEXT: and t6, t1, s2
+; RV64I-NEXT: slli t0, t2, 1
+; RV64I-NEXT: slli a1, a1, 63
+; RV64I-NEXT: or a2, a2, a3
+; RV64I-NEXT: or a4, a4, a5
+; RV64I-NEXT: srli a5, a5, 63
+; RV64I-NEXT: or t1, a6, a7
+; RV64I-NEXT: or t6, t6, t0
+; RV64I-NEXT: srli a6, t0, 63
+; RV64I-NEXT: slli a7, a2, 1
+; RV64I-NEXT: andi t0, a4, 2
+; RV64I-NEXT: slli a3, a2, 2
+; RV64I-NEXT: andi t2, a4, 4
+; RV64I-NEXT: slli t3, a2, 3
+; RV64I-NEXT: andi t4, a4, 8
+; RV64I-NEXT: slli s0, a2, 4
+; RV64I-NEXT: andi s1, a4, 16
+; RV64I-NEXT: slli s3, a2, 5
+; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: addi a5, a5, -1
; RV64I-NEXT: and a0, a5, a0
-; RV64I-NEXT: sd a0, 912(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a5, s1, 128
-; RV64I-NEXT: seqz a6, t3
+; RV64I-NEXT: sd a0, 944(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a0, a4, 32
+; RV64I-NEXT: seqz a5, a6
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: and a1, a5, a1
+; RV64I-NEXT: sd a1, 952(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a1, a2, 6
+; RV64I-NEXT: seqz a5, t0
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: and a5, a5, a7
+; RV64I-NEXT: sd a5, 456(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a5, a4, 64
+; RV64I-NEXT: seqz a6, t2
; RV64I-NEXT: addi a6, a6, -1
-; RV64I-NEXT: and a0, a6, t2
-; RV64I-NEXT: sd a0, 896(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a6, s0, 8
-; RV64I-NEXT: seqz a7, t6
+; RV64I-NEXT: and a3, a6, a3
+; RV64I-NEXT: sd a3, 920(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a6, a2, 7
+; RV64I-NEXT: seqz a7, t4
; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: and a0, a7, t4
-; RV64I-NEXT: sd a0, 472(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a7, s1, 256
-; RV64I-NEXT: seqz a3, a3
-; RV64I-NEXT: addi a3, a3, -1
-; RV64I-NEXT: and a2, a3, a2
-; RV64I-NEXT: sd a2, 928(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, s0, 9
-; RV64I-NEXT: seqz a3, a5
-; RV64I-NEXT: addi a3, a3, -1
-; RV64I-NEXT: and a3, a3, a4
-; RV64I-NEXT: sd a3, 464(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a3, s1, 512
-; RV64I-NEXT: seqz a4, a7
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: and a0, a4, a6
-; RV64I-NEXT: sd a0, 872(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a4, s0, 10
-; RV64I-NEXT: seqz a3, a3
-; RV64I-NEXT: addi a3, a3, -1
-; RV64I-NEXT: and a2, a3, a2
-; RV64I-NEXT: sd a2, 904(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a2, s1, 1024
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: and a2, a2, a4
-; RV64I-NEXT: sd a2, 936(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, s7
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 11
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 848(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 1
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 12
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 840(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 2
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 13
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 864(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 4
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 14
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 888(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 8
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 15
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 920(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 16
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 16
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 800(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 32
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 17
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 784(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 64
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 18
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 816(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 128
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 19
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 832(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 256
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 20
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 856(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 512
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 21
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 880(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 1024
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 22
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 736(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 2048
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: and a3, a7, t3
+; RV64I-NEXT: sd a3, 904(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a7, a4, 128
+; RV64I-NEXT: seqz t0, s1
+; RV64I-NEXT: addi t0, t0, -1
+; RV64I-NEXT: and a3, t0, s0
+; RV64I-NEXT: sd a3, 888(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli t0, a2, 8
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: and a0, a0, s3
+; RV64I-NEXT: sd a0, 448(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a0, a4, 256
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: and a1, a5, a1
+; RV64I-NEXT: sd a1, 928(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a1, a2, 9
+; RV64I-NEXT: seqz a5, a7
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 872(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a5, a4, 512
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: and a0, a0, t0
+; RV64I-NEXT: sd a0, 856(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, a2, 10
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: and a1, a5, a1
+; RV64I-NEXT: sd a1, 896(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a1, a4, 1024
+; RV64I-NEXT: seqz a1, a1
+; RV64I-NEXT: addi a1, a1, -1
+; RV64I-NEXT: and a0, a1, a0
+; RV64I-NEXT: sd a0, 936(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, s7
+; RV64I-NEXT: mv s0, s7
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 11
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 832(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 1
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 12
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 824(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 2
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 13
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 848(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 4
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 14
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 880(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 8
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 15
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 912(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 16
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 16
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 784(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 32
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 17
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 768(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 64
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 18
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 800(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 128
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 19
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 816(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 256
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 20
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 840(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 512
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 21
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 864(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 1024
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 22
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 720(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 2048
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 23
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 712(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 4096
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 24
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 744(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 8192
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 25
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 760(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 16384
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 26
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 776(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 32768
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 27
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 792(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 65536
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 28
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 808(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 131072
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 29
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 656(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 262144
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 30
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 640(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sraiw a0, a4, 31
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 31
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 680(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 32
+; RV64I-NEXT: sd a0, 440(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 32
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 696(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 33
+; RV64I-NEXT: sd a0, 432(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 33
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 704(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 34
+; RV64I-NEXT: sd a0, 424(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 34
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 728(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 35
+; RV64I-NEXT: sd a0, 416(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 35
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 736(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 36
+; RV64I-NEXT: sd a0, 408(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 36
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 752(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 37
+; RV64I-NEXT: sd a0, 400(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 37
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 584(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 38
+; RV64I-NEXT: sd a0, 392(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 38
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 568(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 39
+; RV64I-NEXT: sd a0, 384(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 39
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 616(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 40
+; RV64I-NEXT: sd a0, 376(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 40
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 624(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 41
+; RV64I-NEXT: sd a0, 368(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 41
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 632(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s1, t5, 42
+; RV64I-NEXT: and a0, a4, s1
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 42
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 648(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a1, t5, 43
+; RV64I-NEXT: and a0, a4, a1
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a5, a2, 43
+; RV64I-NEXT: and a0, a0, a5
+; RV64I-NEXT: sd a0, 664(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 44
+; RV64I-NEXT: and a5, a4, a0
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 44
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 672(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli ra, t5, 45
+; RV64I-NEXT: and a5, a4, ra
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 45
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 688(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s11, t5, 46
+; RV64I-NEXT: and a5, a4, s11
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 46
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 528(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s8, t5, 47
+; RV64I-NEXT: and a5, a4, s8
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 47
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 520(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s7, t5, 48
+; RV64I-NEXT: and a5, a4, s7
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 48
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 536(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s6, t5, 49
+; RV64I-NEXT: and a5, a4, s6
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 49
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 544(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s5, t5, 50
+; RV64I-NEXT: and a5, a4, s5
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 50
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 552(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli t3, t5, 51
+; RV64I-NEXT: and a5, a4, t3
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 51
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 560(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli t2, t5, 52
+; RV64I-NEXT: and a5, a4, t2
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 52
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 576(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli t0, t5, 53
+; RV64I-NEXT: and a5, a4, t0
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 53
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 592(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a7, t5, 54
+; RV64I-NEXT: and a5, a4, a7
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 54
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 608(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a3, t5, 55
+; RV64I-NEXT: and a5, a4, a3
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 55
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: sd a5, 600(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s4, t5, 56
+; RV64I-NEXT: and a5, a4, s4
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 56
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: sd a5, 472(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s3, t5, 57
+; RV64I-NEXT: and a5, a4, s3
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 57
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: sd a5, 464(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s2, t5, 58
+; RV64I-NEXT: and a5, a4, s2
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 58
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: sd a5, 480(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli t4, t5, 59
+; RV64I-NEXT: and a5, a4, t4
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 59
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: sd a5, 488(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s10, t5, 60
+; RV64I-NEXT: and a5, a4, s10
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 60
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: sd a5, 496(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s9, t5, 61
+; RV64I-NEXT: and a5, a4, s9
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 61
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: sd a5, 504(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a6, t5, 62
+; RV64I-NEXT: andi a5, a4, 1
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: and t5, a5, a2
+; RV64I-NEXT: slli a2, a2, 62
+; RV64I-NEXT: and a4, a4, a6
+; RV64I-NEXT: seqz a4, a4
+; RV64I-NEXT: addi a4, a4, -1
+; RV64I-NEXT: and a2, a4, a2
+; RV64I-NEXT: sd a2, 512(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a2, t6, 2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 23
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 728(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 4096
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 1
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 336(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a2, t6, 4
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 24
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 760(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 8192
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 2
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 352(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a2, t6, 8
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 25
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 776(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 16384
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 3
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 328(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a2, t6, 16
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 26
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 792(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 32768
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 4
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 312(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a2, t6, 32
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 27
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 808(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 65536
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 5
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 296(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a2, t6, 64
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 28
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 824(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 131072
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 6
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 360(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a2, t6, 128
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 29
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 672(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 262144
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 7
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 280(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a2, t6, 256
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 30
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 656(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sraiw a2, s1, 31
+; RV64I-NEXT: slli a4, t1, 8
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 264(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a2, t6, 512
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 31
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 696(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 32
-; RV64I-NEXT: sd a2, 432(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 9
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 304(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a2, t6, 1024
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 32
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 712(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 33
-; RV64I-NEXT: sd a2, 424(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 10
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 344(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a2, t6, s0
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 33
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 720(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 34
-; RV64I-NEXT: sd a2, 416(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 11
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 240(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 1
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 34
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 744(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 35
-; RV64I-NEXT: sd a2, 408(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 12
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 216(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 2
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 35
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 752(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 36
-; RV64I-NEXT: sd a2, 400(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 13
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 256(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 4
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 36
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 768(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 37
-; RV64I-NEXT: sd a2, 392(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 14
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 288(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 8
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 37
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 600(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 38
-; RV64I-NEXT: sd a2, 376(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 15
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 320(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 16
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 38
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 584(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 39
-; RV64I-NEXT: sd a2, 368(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 16
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 184(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 32
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 39
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 632(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 40
-; RV64I-NEXT: sd a2, 360(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 17
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 176(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 64
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 40
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 640(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 41
-; RV64I-NEXT: sd a2, 328(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 18
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 200(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 128
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 41
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 648(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli ra, t5, 42
-; RV64I-NEXT: and a2, s1, ra
+; RV64I-NEXT: slli a4, t1, 19
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 232(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 256
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 42
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 664(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a3, t5, 43
-; RV64I-NEXT: and a2, s1, a3
+; RV64I-NEXT: slli a4, t1, 20
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 248(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 512
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a4, s0, 43
+; RV64I-NEXT: slli a4, t1, 21
; RV64I-NEXT: and a2, a2, a4
-; RV64I-NEXT: sd a2, 680(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 44
-; RV64I-NEXT: and a4, s1, a2
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 44
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 688(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s11, t5, 45
-; RV64I-NEXT: and a4, s1, s11
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 45
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 704(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s8, t5, 46
-; RV64I-NEXT: and a4, s1, s8
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 46
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 544(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s7, t5, 47
-; RV64I-NEXT: and a4, s1, s7
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 47
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 536(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s6, t5, 48
-; RV64I-NEXT: and a4, s1, s6
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 48
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 552(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s5, t5, 49
-; RV64I-NEXT: and a4, s1, s5
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 49
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 560(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s4, t5, 50
-; RV64I-NEXT: and a4, s1, s4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 50
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 568(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s3, t5, 51
-; RV64I-NEXT: and a4, s1, s3
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 51
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 576(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli t1, t5, 52
-; RV64I-NEXT: and a4, s1, t1
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 52
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 592(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a7, t5, 53
-; RV64I-NEXT: and a4, s1, a7
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 53
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 608(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a6, t5, 54
-; RV64I-NEXT: and a4, s1, a6
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 54
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 624(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a0, t5, 55
-; RV64I-NEXT: and a4, s1, a0
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 55
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 616(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s2, t5, 56
-; RV64I-NEXT: and a4, s1, s2
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 56
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 488(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli t6, t5, 57
-; RV64I-NEXT: and a4, s1, t6
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 57
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 480(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli t4, t5, 58
-; RV64I-NEXT: and a4, s1, t4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 58
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 496(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli t3, t5, 59
-; RV64I-NEXT: and a4, s1, t3
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 59
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 504(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s10, t5, 60
-; RV64I-NEXT: and a4, s1, s10
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 60
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 512(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s9, t5, 61
-; RV64I-NEXT: and a4, s1, s9
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 61
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 520(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli t2, t5, 62
-; RV64I-NEXT: andi a4, s1, 1
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: and t5, a4, s0
-; RV64I-NEXT: slli s0, s0, 62
-; RV64I-NEXT: and a4, s1, t2
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: and a4, a4, s0
-; RV64I-NEXT: sd a4, 528(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, t0, 2
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 1
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 384(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, t0, 4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 2
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 344(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, t0, 8
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 3
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 320(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, t0, 16
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 312(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, t0, 32
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 5
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 296(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, t0, 64
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 6
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 352(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, t0, 128
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 7
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 280(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, t0, 256
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 8
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 264(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, t0, 512
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 9
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 304(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, t0, 1024
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 10
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 336(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 440(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 11
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 240(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 1
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 12
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 216(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 2
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 13
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 256(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 4
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 14
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 288(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 8
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 15
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 440(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 16
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 16
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 184(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 32
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 17
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 176(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 64
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 18
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 200(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 128
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 19
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 232(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 256
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 20
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 248(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 512
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 21
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 272(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 1024
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 22
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 152(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 2048
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 23
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 136(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 4096
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 24
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 160(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 8192
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 25
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 168(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 16384
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 26
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 192(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 32768
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 27
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 208(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 65536
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 28
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 224(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 131072
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli s1, a1, 29
-; RV64I-NEXT: and a4, a4, s1
-; RV64I-NEXT: sd a4, 112(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 262144
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 30
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 104(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sraiw a4, t0, 31
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 31
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 120(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 432(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 32
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 128(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 424(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 33
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 144(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 416(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 34
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 416(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 408(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 35
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 424(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 400(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 36
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 432(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 392(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 37
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 64(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 376(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 38
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 48(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 368(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 39
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 80(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 360(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 40
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 360(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 328(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli s0, a1, 41
-; RV64I-NEXT: and a4, a4, s0
-; RV64I-NEXT: sd a4, 368(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a4, t0, ra
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 42
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 376(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a3, t0, a3
-; RV64I-NEXT: seqz a3, a3
-; RV64I-NEXT: addi a3, a3, -1
-; RV64I-NEXT: slli a4, a1, 43
-; RV64I-NEXT: and a3, a3, a4
-; RV64I-NEXT: sd a3, 392(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, a2
+; RV64I-NEXT: sd a2, 272(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 1024
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 22
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 152(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 2048
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 44
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 400(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, s11
+; RV64I-NEXT: slli a4, t1, 23
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 136(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 4096
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 45
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 408(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, s8
+; RV64I-NEXT: slli a4, t1, 24
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 160(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 8192
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a5, a1, 46
-; RV64I-NEXT: and a2, a2, a5
-; RV64I-NEXT: sd a2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, s7
+; RV64I-NEXT: slli a4, t1, 25
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 168(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 16384
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a4, a1, 47
-; RV64I-NEXT: and s11, a2, a4
-; RV64I-NEXT: and a2, t0, s6
+; RV64I-NEXT: slli a4, t1, 26
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 192(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 32768
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 48
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, s5
+; RV64I-NEXT: slli a4, t1, 27
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 208(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 65536
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 49
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, s4
+; RV64I-NEXT: slli a4, t1, 28
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 224(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 131072
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 50
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, s3
+; RV64I-NEXT: slli s0, t1, 29
+; RV64I-NEXT: and a2, a2, s0
+; RV64I-NEXT: sd a2, 112(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 262144
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 51
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 56(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, t1
+; RV64I-NEXT: slli a4, t1, 30
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 104(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sraiw a2, t6, 31
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 52
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 72(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, a7
+; RV64I-NEXT: slli a4, t1, 31
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 120(sp) # 8-byte Folded Spill
+; RV64I-NEXT: ld a2, 440(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 53
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 88(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, a6
+; RV64I-NEXT: slli a4, t1, 32
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 128(sp) # 8-byte Folded Spill
+; RV64I-NEXT: ld a2, 432(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 54
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 328(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, a0
+; RV64I-NEXT: slli a4, t1, 33
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 144(sp) # 8-byte Folded Spill
+; RV64I-NEXT: ld a2, 424(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 55
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 96(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, s2
+; RV64I-NEXT: slli a4, t1, 34
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 424(sp) # 8-byte Folded Spill
+; RV64I-NEXT: ld a2, 416(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 56
-; RV64I-NEXT: and s6, a2, a3
-; RV64I-NEXT: and a3, t0, t6
-; RV64I-NEXT: seqz a3, a3
-; RV64I-NEXT: addi a3, a3, -1
-; RV64I-NEXT: slli a4, a1, 57
-; RV64I-NEXT: and s5, a3, a4
-; RV64I-NEXT: and a4, t0, t4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 58
-; RV64I-NEXT: and s7, a4, a5
-; RV64I-NEXT: and a5, t0, t3
-; RV64I-NEXT: seqz a5, a5
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a0, a1, 59
-; RV64I-NEXT: and s8, a5, a0
-; RV64I-NEXT: and a0, t0, s10
+; RV64I-NEXT: slli a4, t1, 35
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 432(sp) # 8-byte Folded Spill
+; RV64I-NEXT: ld a2, 408(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 36
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 440(sp) # 8-byte Folded Spill
+; RV64I-NEXT: ld a2, 400(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 37
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 64(sp) # 8-byte Folded Spill
+; RV64I-NEXT: ld a2, 392(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 38
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 48(sp) # 8-byte Folded Spill
+; RV64I-NEXT: ld a2, 384(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 39
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 80(sp) # 8-byte Folded Spill
+; RV64I-NEXT: ld a2, 376(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 40
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 376(sp) # 8-byte Folded Spill
+; RV64I-NEXT: ld a2, 368(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 41
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 384(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a2, t6, s1
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli s1, t1, 42
+; RV64I-NEXT: and a2, a2, s1
+; RV64I-NEXT: sd a2, 392(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a1, t6, a1
+; RV64I-NEXT: seqz a1, a1
+; RV64I-NEXT: addi a1, a1, -1
+; RV64I-NEXT: slli a2, t1, 43
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: sd a1, 400(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, a0
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: slli s10, a1, 60
-; RV64I-NEXT: and s10, a0, s10
-; RV64I-NEXT: and a0, t0, s9
+; RV64I-NEXT: slli a1, t1, 44
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 408(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, ra
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: slli s9, a1, 61
-; RV64I-NEXT: and s9, a0, s9
-; RV64I-NEXT: and a0, t0, t2
-; RV64I-NEXT: andi t0, t0, 1
-; RV64I-NEXT: seqz t0, t0
-; RV64I-NEXT: addi t0, t0, -1
-; RV64I-NEXT: and t0, t0, a1
-; RV64I-NEXT: slli a1, a1, 62
+; RV64I-NEXT: slli a1, t1, 45
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 416(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, s11
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a4, t1, 46
+; RV64I-NEXT: and a0, a0, a4
+; RV64I-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, s8
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a2, t1, 47
+; RV64I-NEXT: and s11, a0, a2
+; RV64I-NEXT: and a0, t6, s7
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a5, t1, 48
+; RV64I-NEXT: and a0, a0, a5
+; RV64I-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, s6
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, t1, 49
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, s5
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, t1, 50
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, t3
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, t1, 51
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 56(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, t2
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, t1, 52
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 72(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, t0
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, t1, 53
; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 88(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, a7
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, t1, 54
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 368(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, a3
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, t1, 55
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 96(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, s4
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, t1, 56
+; RV64I-NEXT: and s6, a0, a1
+; RV64I-NEXT: and a1, t6, s3
+; RV64I-NEXT: seqz a1, a1
+; RV64I-NEXT: addi a1, a1, -1
+; RV64I-NEXT: slli a2, t1, 57
+; RV64I-NEXT: and s5, a1, a2
+; RV64I-NEXT: and a2, t6, s2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 58
+; RV64I-NEXT: and s7, a2, a4
+; RV64I-NEXT: and a4, t6, t4
+; RV64I-NEXT: seqz a4, a4
+; RV64I-NEXT: addi a4, a4, -1
+; RV64I-NEXT: slli a3, t1, 59
+; RV64I-NEXT: and s8, a4, a3
+; RV64I-NEXT: and a3, t6, s10
+; RV64I-NEXT: seqz a3, a3
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: slli s10, t1, 60
+; RV64I-NEXT: and s10, a3, s10
+; RV64I-NEXT: and a3, t6, s9
+; RV64I-NEXT: seqz a3, a3
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: slli s9, t1, 61
+; RV64I-NEXT: and s9, a3, s9
+; RV64I-NEXT: and a3, t6, a6
+; RV64I-NEXT: andi t6, t6, 1
+; RV64I-NEXT: seqz t6, t6
+; RV64I-NEXT: addi t6, t6, -1
+; RV64I-NEXT: and t6, t6, t1
+; RV64I-NEXT: slli t1, t1, 62
+; RV64I-NEXT: seqz a3, a3
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: and a0, a3, t1
; RV64I-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: ld a0, 456(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s4, t5, a0
-; RV64I-NEXT: ld a0, 912(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a0, 920(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 904(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t2, a0, a1
+; RV64I-NEXT: ld a0, 888(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld a1, 448(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t3, a1, a0
-; RV64I-NEXT: ld a0, 896(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld a1, 472(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t4, a0, a1
+; RV64I-NEXT: xor t3, a0, a1
; RV64I-NEXT: ld a0, 872(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld a1, 464(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t5, a1, a0
-; RV64I-NEXT: ld a0, 848(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld a1, 840(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t6, a0, a1
-; RV64I-NEXT: ld a0, 800(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 784(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 856(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t4, a0, a1
+; RV64I-NEXT: ld a0, 832(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 824(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t5, a0, a1
+; RV64I-NEXT: ld a0, 784(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 768(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s0, a0, s0
-; RV64I-NEXT: ld a0, 736(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 728(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a0, 720(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 712(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s1, a0, s1
-; RV64I-NEXT: ld a0, 672(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld a1, 656(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a0, 656(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 640(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s2, a0, a1
-; RV64I-NEXT: ld a0, 600(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld a1, 584(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a0, 584(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 568(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s3, a0, a1
-; RV64I-NEXT: ld a0, 544(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld a1, 536(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a0, 528(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 520(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t0, a0, a1
+; RV64I-NEXT: ld a0, 472(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 464(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t1, a0, a1
-; RV64I-NEXT: ld a0, 488(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld a1, 480(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t2, a0, a1
-; RV64I-NEXT: ld a0, 384(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t0, t0, a0
-; RV64I-NEXT: ld a0, 344(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld a1, 320(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a0, 336(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t6, t6, a0
+; RV64I-NEXT: ld a0, 352(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 328(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ld a1, 312(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld a2, 296(sp) # 8-byte Folded Reload
@@ -5965,62 +5982,62 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64I-NEXT: ld ra, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s11, ra, s11
; RV64I-NEXT: xor s5, s6, s5
-; RV64I-NEXT: xor t3, s4, t3
+; RV64I-NEXT: xor t2, s4, t2
; RV64I-NEXT: ld s4, 928(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t3, t3, s4
+; RV64I-NEXT: ld s4, 896(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t4, t4, s4
-; RV64I-NEXT: ld s4, 904(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 848(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t5, t5, s4
-; RV64I-NEXT: ld s4, 864(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t6, t6, s4
-; RV64I-NEXT: ld s4, 816(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 800(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s0, s0, s4
-; RV64I-NEXT: ld s4, 760(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 744(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s1, s1, s4
-; RV64I-NEXT: ld s4, 696(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 680(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s2, s2, s4
-; RV64I-NEXT: ld s4, 632(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 616(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s3, s3, s4
-; RV64I-NEXT: ld s4, 552(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 536(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t0, t0, s4
+; RV64I-NEXT: ld s4, 480(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t1, t1, s4
-; RV64I-NEXT: ld s4, 496(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t2, t2, s4
-; RV64I-NEXT: xor a0, t0, a0
-; RV64I-NEXT: ld t0, 352(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor a1, a1, t0
-; RV64I-NEXT: ld t0, 304(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor a2, a2, t0
-; RV64I-NEXT: ld t0, 256(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor a3, a3, t0
-; RV64I-NEXT: ld t0, 200(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor a4, a4, t0
-; RV64I-NEXT: ld t0, 160(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor a5, a5, t0
-; RV64I-NEXT: ld t0, 120(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor a6, a6, t0
-; RV64I-NEXT: ld t0, 80(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor a7, a7, t0
-; RV64I-NEXT: ld t0, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t0, s11, t0
+; RV64I-NEXT: xor a0, t6, a0
+; RV64I-NEXT: ld t6, 360(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a1, a1, t6
+; RV64I-NEXT: ld t6, 304(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a2, a2, t6
+; RV64I-NEXT: ld t6, 256(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a3, a3, t6
+; RV64I-NEXT: ld t6, 200(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a4, a4, t6
+; RV64I-NEXT: ld t6, 160(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a5, a5, t6
+; RV64I-NEXT: ld t6, 120(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a6, a6, t6
+; RV64I-NEXT: ld t6, 80(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a7, a7, t6
+; RV64I-NEXT: ld t6, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t6, s11, t6
; RV64I-NEXT: xor s4, s5, s7
-; RV64I-NEXT: xor t3, t3, t4
-; RV64I-NEXT: ld t4, 936(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t2, t2, t3
+; RV64I-NEXT: ld t3, 936(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t3, t4, t3
+; RV64I-NEXT: ld t4, 880(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t4, t5, t4
-; RV64I-NEXT: ld t5, 888(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t5, t6, t5
-; RV64I-NEXT: ld t6, 832(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t6, s0, t6
-; RV64I-NEXT: ld s0, 776(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld t5, 816(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t5, s0, t5
+; RV64I-NEXT: ld s0, 760(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s0, s1, s0
-; RV64I-NEXT: ld s1, 712(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 696(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s1, s2, s1
-; RV64I-NEXT: ld s2, 640(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 624(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s2, s3, s2
-; RV64I-NEXT: ld s3, 560(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 544(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t0, t0, s3
+; RV64I-NEXT: ld s3, 488(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t1, t1, s3
-; RV64I-NEXT: ld s3, 504(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t2, t2, s3
; RV64I-NEXT: xor a0, a0, a1
-; RV64I-NEXT: ld a1, 336(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 344(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a1, a2, a1
; RV64I-NEXT: ld a2, 288(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a2, a3, a2
@@ -6030,28 +6047,28 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64I-NEXT: xor a4, a5, a4
; RV64I-NEXT: ld a5, 128(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a5, a6, a5
-; RV64I-NEXT: ld a6, 360(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a6, 376(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a6, a7, a6
; RV64I-NEXT: ld a7, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor a7, t0, a7
-; RV64I-NEXT: xor t0, s4, s8
-; RV64I-NEXT: xor t3, t3, t4
-; RV64I-NEXT: ld t4, 920(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a7, t6, a7
+; RV64I-NEXT: xor t6, s4, s8
+; RV64I-NEXT: xor t2, t2, t3
+; RV64I-NEXT: ld t3, 912(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t3, t4, t3
+; RV64I-NEXT: ld t4, 840(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t4, t5, t4
-; RV64I-NEXT: ld t5, 856(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t5, t6, t5
-; RV64I-NEXT: ld t6, 792(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t6, s0, t6
-; RV64I-NEXT: ld s0, 720(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld t5, 776(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t5, s0, t5
+; RV64I-NEXT: ld s0, 704(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s0, s1, s0
-; RV64I-NEXT: ld s1, 648(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 632(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s1, s2, s1
-; RV64I-NEXT: ld s2, 568(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 552(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t0, t0, s2
+; RV64I-NEXT: ld s2, 496(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t1, t1, s2
-; RV64I-NEXT: ld s2, 512(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t2, t2, s2
; RV64I-NEXT: xor a0, a0, a1
-; RV64I-NEXT: ld a1, 440(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 320(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a1, a2, a1
; RV64I-NEXT: ld a2, 248(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a2, a3, a2
@@ -6059,95 +6076,95 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64I-NEXT: xor a3, a4, a3
; RV64I-NEXT: ld a4, 144(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a4, a5, a4
-; RV64I-NEXT: ld a5, 368(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a5, 384(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a5, a6, a5
; RV64I-NEXT: ld a6, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a6, a7, a6
-; RV64I-NEXT: xor a7, t0, s10
-; RV64I-NEXT: xor t0, t3, t4
-; RV64I-NEXT: ld t3, 880(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t3, t5, t3
-; RV64I-NEXT: ld t4, 808(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t4, t6, t4
-; RV64I-NEXT: ld t5, 744(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a7, t6, s10
+; RV64I-NEXT: xor t2, t2, t3
+; RV64I-NEXT: ld t3, 864(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t3, t4, t3
+; RV64I-NEXT: ld t4, 792(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t4, t5, t4
+; RV64I-NEXT: ld t5, 728(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t5, s0, t5
-; RV64I-NEXT: ld t6, 664(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld t6, 648(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t6, s1, t6
-; RV64I-NEXT: ld s0, 576(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 560(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t0, t0, s0
+; RV64I-NEXT: ld s0, 504(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t1, t1, s0
-; RV64I-NEXT: ld s0, 520(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t2, t2, s0
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ld a1, 272(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a1, a2, a1
; RV64I-NEXT: ld a2, 208(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a2, a3, a2
-; RV64I-NEXT: ld a3, 416(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a3, 424(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a3, a4, a3
-; RV64I-NEXT: ld a4, 376(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a4, 392(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a4, a5, a4
; RV64I-NEXT: ld a5, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a5, a6, a5
; RV64I-NEXT: xor a6, a7, s9
-; RV64I-NEXT: xor a7, t0, t3
-; RV64I-NEXT: ld t0, 824(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t0, t4, t0
-; RV64I-NEXT: ld t3, 752(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a7, t2, t3
+; RV64I-NEXT: ld t2, 808(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t2, t4, t2
+; RV64I-NEXT: ld t3, 736(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t3, t5, t3
-; RV64I-NEXT: ld t4, 680(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld t4, 664(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t4, t6, t4
-; RV64I-NEXT: ld t5, 592(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld t5, 576(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t0, t0, t5
+; RV64I-NEXT: ld t5, 512(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t1, t1, t5
-; RV64I-NEXT: ld t5, 528(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t2, t2, t5
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ld a1, 224(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a1, a2, a1
-; RV64I-NEXT: ld a2, 424(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a2, 432(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a2, a3, a2
-; RV64I-NEXT: ld a3, 392(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a3, 400(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a3, a4, a3
; RV64I-NEXT: ld a4, 72(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a4, a5, a4
; RV64I-NEXT: ld a5, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a5, a6, a5
-; RV64I-NEXT: xor a6, a7, t0
-; RV64I-NEXT: ld a7, 768(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a6, a7, t2
+; RV64I-NEXT: ld a7, 752(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a7, t3, a7
-; RV64I-NEXT: ld t0, 688(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t0, t4, t0
-; RV64I-NEXT: ld t3, 608(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t1, t1, t3
+; RV64I-NEXT: ld t2, 672(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t2, t4, t2
+; RV64I-NEXT: ld t3, 592(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t0, t0, t3
; RV64I-NEXT: ld t3, 944(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t2, t2, t3
+; RV64I-NEXT: xor t1, t1, t3
; RV64I-NEXT: xor a0, a0, a1
-; RV64I-NEXT: ld a1, 432(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 440(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a1, a2, a1
-; RV64I-NEXT: ld a2, 400(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a2, 408(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a2, a3, a2
; RV64I-NEXT: ld a3, 88(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a3, a4, a3
; RV64I-NEXT: ld a4, 952(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a4, a5, a4
; RV64I-NEXT: xor a5, a6, a7
-; RV64I-NEXT: ld a6, 704(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor a6, t0, a6
-; RV64I-NEXT: ld a7, 624(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor a7, t1, a7
+; RV64I-NEXT: ld a6, 688(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a6, t2, a6
+; RV64I-NEXT: ld a7, 608(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a7, t0, a7
; RV64I-NEXT: xor a0, a0, a1
-; RV64I-NEXT: ld a1, 408(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 416(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a1, a2, a1
-; RV64I-NEXT: ld a2, 328(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a2, 368(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a2, a3, a2
; RV64I-NEXT: xor a3, a5, a6
-; RV64I-NEXT: ld a5, 616(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a5, 600(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a5, a7, a5
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ld a1, 96(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a1, a2, a1
; RV64I-NEXT: xor a3, a3, a5
; RV64I-NEXT: xor a0, a0, a1
-; RV64I-NEXT: xor a1, a3, t2
+; RV64I-NEXT: xor a1, a3, t1
; RV64I-NEXT: xor a0, a0, a4
; RV64I-NEXT: srli a2, a1, 40
; RV64I-NEXT: srli a3, a1, 56
@@ -9406,1570 +9423,1561 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
;
; RV32IMZBS-LABEL: commutative_clmulh_v2i64:
; RV32IMZBS: # %bb.0:
-; RV32IMZBS-NEXT: addi sp, sp, -800
-; RV32IMZBS-NEXT: sw ra, 796(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: sw s0, 792(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: sw s1, 788(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: sw s2, 784(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: sw s3, 780(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: sw s4, 776(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: sw s5, 772(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: sw s6, 768(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: sw s7, 764(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: sw s8, 760(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: sw s9, 756(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: sw s10, 752(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: sw s11, 748(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: sw a3, 736(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: sw a2, 732(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s7, 0(a0)
-; RV32IMZBS-NEXT: lw a4, 4(a0)
+; RV32IMZBS-NEXT: addi sp, sp, -784
+; RV32IMZBS-NEXT: sw ra, 780(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw s0, 776(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw s1, 772(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw s2, 768(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw s3, 764(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw s4, 760(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw s5, 756(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw s6, 752(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw s7, 748(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw s8, 744(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw s9, 740(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw s10, 736(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw s11, 732(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 720(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 716(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw t6, 0(a0)
+; RV32IMZBS-NEXT: lw t4, 4(a0)
; RV32IMZBS-NEXT: lw a7, 8(a0)
; RV32IMZBS-NEXT: lw t1, 12(a0)
; RV32IMZBS-NEXT: lw s4, 0(a1)
-; RV32IMZBS-NEXT: lw t6, 4(a1)
+; RV32IMZBS-NEXT: lw a2, 4(a1)
; RV32IMZBS-NEXT: lw t0, 8(a1)
; RV32IMZBS-NEXT: lw t2, 12(a1)
; RV32IMZBS-NEXT: lui a0, 16
; RV32IMZBS-NEXT: lui a1, 61681
-; RV32IMZBS-NEXT: lui a2, 209715
-; RV32IMZBS-NEXT: lui a3, 349525
-; RV32IMZBS-NEXT: addi s10, a0, -256
-; RV32IMZBS-NEXT: addi s9, a1, -241
-; RV32IMZBS-NEXT: addi s8, a2, 819
-; RV32IMZBS-NEXT: addi s6, a3, 1365
-; RV32IMZBS-NEXT: srli s0, t6, 8
-; RV32IMZBS-NEXT: srli s1, t6, 24
-; RV32IMZBS-NEXT: and t5, t6, s10
-; RV32IMZBS-NEXT: slli t6, t6, 24
-; RV32IMZBS-NEXT: srli a3, a4, 8
-; RV32IMZBS-NEXT: srli a5, a4, 24
-; RV32IMZBS-NEXT: and t3, a4, s10
-; RV32IMZBS-NEXT: slli a4, a4, 24
-; RV32IMZBS-NEXT: srli a2, s4, 8
-; RV32IMZBS-NEXT: srli s2, s4, 24
-; RV32IMZBS-NEXT: and a0, s4, s10
+; RV32IMZBS-NEXT: lui a3, 209715
+; RV32IMZBS-NEXT: lui a4, 349525
+; RV32IMZBS-NEXT: addi s9, a0, -256
+; RV32IMZBS-NEXT: addi s8, a1, -241
+; RV32IMZBS-NEXT: addi s7, a3, 819
+; RV32IMZBS-NEXT: addi s5, a4, 1365
+; RV32IMZBS-NEXT: srli a3, a2, 8
+; RV32IMZBS-NEXT: srli s1, a2, 24
+; RV32IMZBS-NEXT: and t5, a2, s9
+; RV32IMZBS-NEXT: slli a2, a2, 24
+; RV32IMZBS-NEXT: srli a4, t4, 8
+; RV32IMZBS-NEXT: srli s3, t4, 24
+; RV32IMZBS-NEXT: and t3, t4, s9
+; RV32IMZBS-NEXT: slli t4, t4, 24
+; RV32IMZBS-NEXT: srli a6, s4, 8
+; RV32IMZBS-NEXT: srli s0, s4, 24
+; RV32IMZBS-NEXT: and a0, s4, s9
; RV32IMZBS-NEXT: slli a1, s4, 24
-; RV32IMZBS-NEXT: srli s4, s7, 8
-; RV32IMZBS-NEXT: srli t4, s7, 24
-; RV32IMZBS-NEXT: and a6, s7, s10
-; RV32IMZBS-NEXT: slli s7, s7, 24
-; RV32IMZBS-NEXT: srli s3, t2, 8
-; RV32IMZBS-NEXT: and s0, s0, s10
-; RV32IMZBS-NEXT: or s0, s0, s1
-; RV32IMZBS-NEXT: srli s5, t2, 24
+; RV32IMZBS-NEXT: srli s4, t6, 8
+; RV32IMZBS-NEXT: srli s6, t6, 24
+; RV32IMZBS-NEXT: and a5, t6, s9
+; RV32IMZBS-NEXT: slli t6, t6, 24
+; RV32IMZBS-NEXT: srli s2, t2, 8
+; RV32IMZBS-NEXT: and a3, a3, s9
+; RV32IMZBS-NEXT: or a3, a3, s1
+; RV32IMZBS-NEXT: srli s10, t2, 24
; RV32IMZBS-NEXT: slli t5, t5, 8
-; RV32IMZBS-NEXT: or t5, t6, t5
-; RV32IMZBS-NEXT: and t6, t2, s10
+; RV32IMZBS-NEXT: or t5, a2, t5
+; RV32IMZBS-NEXT: and a2, t2, s9
; RV32IMZBS-NEXT: slli s1, t2, 24
-; RV32IMZBS-NEXT: and a3, a3, s10
-; RV32IMZBS-NEXT: or t2, a3, a5
-; RV32IMZBS-NEXT: srli a3, t1, 8
+; RV32IMZBS-NEXT: and a4, a4, s9
+; RV32IMZBS-NEXT: or t2, a4, s3
+; RV32IMZBS-NEXT: srli a4, t1, 8
; RV32IMZBS-NEXT: slli t3, t3, 8
-; RV32IMZBS-NEXT: or t3, a4, t3
-; RV32IMZBS-NEXT: srli a5, t1, 24
-; RV32IMZBS-NEXT: and a2, a2, s10
-; RV32IMZBS-NEXT: or a2, a2, s2
-; RV32IMZBS-NEXT: and a4, t1, s10
+; RV32IMZBS-NEXT: or t3, t4, t3
+; RV32IMZBS-NEXT: srli s3, t1, 24
+; RV32IMZBS-NEXT: and a6, a6, s9
+; RV32IMZBS-NEXT: or a6, a6, s0
+; RV32IMZBS-NEXT: and t4, t1, s9
; RV32IMZBS-NEXT: slli t1, t1, 24
; RV32IMZBS-NEXT: slli a0, a0, 8
; RV32IMZBS-NEXT: or a0, a1, a0
-; RV32IMZBS-NEXT: srli s2, t0, 8
-; RV32IMZBS-NEXT: and a1, s4, s10
-; RV32IMZBS-NEXT: or a1, a1, t4
-; RV32IMZBS-NEXT: srli t4, t0, 24
-; RV32IMZBS-NEXT: slli a6, a6, 8
-; RV32IMZBS-NEXT: or s4, s7, a6
-; RV32IMZBS-NEXT: and s7, t0, s10
-; RV32IMZBS-NEXT: slli a6, t0, 24
-; RV32IMZBS-NEXT: and t0, s3, s10
-; RV32IMZBS-NEXT: or t0, t0, s5
-; RV32IMZBS-NEXT: srli s3, a7, 8
-; RV32IMZBS-NEXT: slli t6, t6, 8
-; RV32IMZBS-NEXT: or t6, s1, t6
+; RV32IMZBS-NEXT: srli s0, t0, 8
+; RV32IMZBS-NEXT: and a1, s4, s9
+; RV32IMZBS-NEXT: or a1, a1, s6
+; RV32IMZBS-NEXT: srli s6, t0, 24
+; RV32IMZBS-NEXT: slli a5, a5, 8
+; RV32IMZBS-NEXT: or s4, t6, a5
+; RV32IMZBS-NEXT: and t6, t0, s9
+; RV32IMZBS-NEXT: slli a5, t0, 24
+; RV32IMZBS-NEXT: and t0, s2, s9
+; RV32IMZBS-NEXT: or t0, t0, s10
+; RV32IMZBS-NEXT: srli s2, a7, 8
+; RV32IMZBS-NEXT: slli a2, a2, 8
+; RV32IMZBS-NEXT: or a2, s1, a2
; RV32IMZBS-NEXT: srli s1, a7, 24
-; RV32IMZBS-NEXT: and a3, a3, s10
-; RV32IMZBS-NEXT: or a3, a3, a5
-; RV32IMZBS-NEXT: and a5, a7, s10
+; RV32IMZBS-NEXT: and a4, a4, s9
+; RV32IMZBS-NEXT: or a4, a4, s3
+; RV32IMZBS-NEXT: and s3, a7, s9
; RV32IMZBS-NEXT: slli a7, a7, 24
-; RV32IMZBS-NEXT: slli a4, a4, 8
-; RV32IMZBS-NEXT: and s2, s2, s10
-; RV32IMZBS-NEXT: slli s7, s7, 8
-; RV32IMZBS-NEXT: and s3, s3, s10
-; RV32IMZBS-NEXT: slli a5, a5, 8
-; RV32IMZBS-NEXT: or a4, t1, a4
-; RV32IMZBS-NEXT: or t1, s2, t4
-; RV32IMZBS-NEXT: or a6, a6, s7
-; RV32IMZBS-NEXT: or t4, s3, s1
-; RV32IMZBS-NEXT: or a5, a7, a5
-; RV32IMZBS-NEXT: or a7, t5, s0
+; RV32IMZBS-NEXT: slli t4, t4, 8
+; RV32IMZBS-NEXT: and s0, s0, s9
+; RV32IMZBS-NEXT: slli t6, t6, 8
+; RV32IMZBS-NEXT: and s2, s2, s9
+; RV32IMZBS-NEXT: slli s3, s3, 8
+; RV32IMZBS-NEXT: or t1, t1, t4
+; RV32IMZBS-NEXT: or t4, s0, s6
+; RV32IMZBS-NEXT: or a5, a5, t6
+; RV32IMZBS-NEXT: or t6, s2, s1
+; RV32IMZBS-NEXT: or a7, a7, s3
+; RV32IMZBS-NEXT: or a3, t5, a3
; RV32IMZBS-NEXT: or t2, t3, t2
-; RV32IMZBS-NEXT: or a0, a0, a2
+; RV32IMZBS-NEXT: or a0, a0, a6
; RV32IMZBS-NEXT: or a1, s4, a1
-; RV32IMZBS-NEXT: or a2, t6, t0
-; RV32IMZBS-NEXT: or a3, a4, a3
-; RV32IMZBS-NEXT: or a4, a6, t1
+; RV32IMZBS-NEXT: or a2, a2, t0
+; RV32IMZBS-NEXT: or a4, t1, a4
; RV32IMZBS-NEXT: or a5, a5, t4
-; RV32IMZBS-NEXT: srli a6, a7, 4
-; RV32IMZBS-NEXT: sw s9, 744(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a7, a7, s9
+; RV32IMZBS-NEXT: or a6, a7, t6
+; RV32IMZBS-NEXT: srli a7, a3, 4
+; RV32IMZBS-NEXT: sw s8, 728(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a3, a3, s8
; RV32IMZBS-NEXT: srli t0, t2, 4
-; RV32IMZBS-NEXT: and t1, t2, s9
+; RV32IMZBS-NEXT: and t1, t2, s8
; RV32IMZBS-NEXT: srli t2, a0, 4
-; RV32IMZBS-NEXT: and a0, a0, s9
+; RV32IMZBS-NEXT: and a0, a0, s8
; RV32IMZBS-NEXT: srli t3, a1, 4
-; RV32IMZBS-NEXT: and a1, a1, s9
+; RV32IMZBS-NEXT: and a1, a1, s8
; RV32IMZBS-NEXT: srli t4, a2, 4
-; RV32IMZBS-NEXT: and a2, a2, s9
-; RV32IMZBS-NEXT: srli t5, a3, 4
-; RV32IMZBS-NEXT: and a3, a3, s9
-; RV32IMZBS-NEXT: srli t6, a4, 4
-; RV32IMZBS-NEXT: and a4, a4, s9
-; RV32IMZBS-NEXT: srli s0, a5, 4
-; RV32IMZBS-NEXT: and a5, a5, s9
-; RV32IMZBS-NEXT: and a6, a6, s9
-; RV32IMZBS-NEXT: slli a7, a7, 4
-; RV32IMZBS-NEXT: and t0, t0, s9
+; RV32IMZBS-NEXT: and a2, a2, s8
+; RV32IMZBS-NEXT: srli t5, a4, 4
+; RV32IMZBS-NEXT: and a4, a4, s8
+; RV32IMZBS-NEXT: srli t6, a5, 4
+; RV32IMZBS-NEXT: and a5, a5, s8
+; RV32IMZBS-NEXT: srli s0, a6, 4
+; RV32IMZBS-NEXT: and a6, a6, s8
+; RV32IMZBS-NEXT: and a7, a7, s8
+; RV32IMZBS-NEXT: slli a3, a3, 4
+; RV32IMZBS-NEXT: and t0, t0, s8
; RV32IMZBS-NEXT: slli t1, t1, 4
-; RV32IMZBS-NEXT: and t2, t2, s9
+; RV32IMZBS-NEXT: and t2, t2, s8
; RV32IMZBS-NEXT: slli a0, a0, 4
-; RV32IMZBS-NEXT: and t3, t3, s9
+; RV32IMZBS-NEXT: and t3, t3, s8
; RV32IMZBS-NEXT: slli a1, a1, 4
-; RV32IMZBS-NEXT: and t4, t4, s9
+; RV32IMZBS-NEXT: and t4, t4, s8
; RV32IMZBS-NEXT: slli a2, a2, 4
-; RV32IMZBS-NEXT: and t5, t5, s9
-; RV32IMZBS-NEXT: slli a3, a3, 4
-; RV32IMZBS-NEXT: and t6, t6, s9
+; RV32IMZBS-NEXT: and t5, t5, s8
; RV32IMZBS-NEXT: slli a4, a4, 4
-; RV32IMZBS-NEXT: and s0, s0, s9
+; RV32IMZBS-NEXT: and t6, t6, s8
; RV32IMZBS-NEXT: slli a5, a5, 4
-; RV32IMZBS-NEXT: or a6, a6, a7
+; RV32IMZBS-NEXT: and s0, s0, s8
+; RV32IMZBS-NEXT: slli a6, a6, 4
+; RV32IMZBS-NEXT: or a3, a7, a3
; RV32IMZBS-NEXT: or a7, t0, t1
; RV32IMZBS-NEXT: or a0, t2, a0
; RV32IMZBS-NEXT: or a1, t3, a1
; RV32IMZBS-NEXT: or a2, t4, a2
-; RV32IMZBS-NEXT: or a3, t5, a3
-; RV32IMZBS-NEXT: or a4, t6, a4
-; RV32IMZBS-NEXT: or a5, s0, a5
-; RV32IMZBS-NEXT: srli t0, a6, 2
-; RV32IMZBS-NEXT: sw s8, 728(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a6, a6, s8
+; RV32IMZBS-NEXT: or a4, t5, a4
+; RV32IMZBS-NEXT: or a5, t6, a5
+; RV32IMZBS-NEXT: or a6, s0, a6
+; RV32IMZBS-NEXT: srli t0, a3, 2
+; RV32IMZBS-NEXT: sw s7, 712(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a3, a3, s7
; RV32IMZBS-NEXT: srli t1, a7, 2
-; RV32IMZBS-NEXT: and a7, a7, s8
+; RV32IMZBS-NEXT: and a7, a7, s7
; RV32IMZBS-NEXT: srli t2, a0, 2
-; RV32IMZBS-NEXT: and a0, a0, s8
+; RV32IMZBS-NEXT: and a0, a0, s7
; RV32IMZBS-NEXT: srli t3, a1, 2
-; RV32IMZBS-NEXT: and a1, a1, s8
+; RV32IMZBS-NEXT: and a1, a1, s7
; RV32IMZBS-NEXT: srli t4, a2, 2
-; RV32IMZBS-NEXT: and a2, a2, s8
-; RV32IMZBS-NEXT: srli t5, a3, 2
-; RV32IMZBS-NEXT: and a3, a3, s8
-; RV32IMZBS-NEXT: srli t6, a4, 2
-; RV32IMZBS-NEXT: and a4, a4, s8
-; RV32IMZBS-NEXT: srli s0, a5, 2
-; RV32IMZBS-NEXT: and a5, a5, s8
-; RV32IMZBS-NEXT: and t0, t0, s8
-; RV32IMZBS-NEXT: slli a6, a6, 2
-; RV32IMZBS-NEXT: and t1, t1, s8
+; RV32IMZBS-NEXT: and a2, a2, s7
+; RV32IMZBS-NEXT: srli t5, a4, 2
+; RV32IMZBS-NEXT: and a4, a4, s7
+; RV32IMZBS-NEXT: srli t6, a5, 2
+; RV32IMZBS-NEXT: and a5, a5, s7
+; RV32IMZBS-NEXT: srli s0, a6, 2
+; RV32IMZBS-NEXT: and a6, a6, s7
+; RV32IMZBS-NEXT: and t0, t0, s7
+; RV32IMZBS-NEXT: slli a3, a3, 2
+; RV32IMZBS-NEXT: and t1, t1, s7
; RV32IMZBS-NEXT: slli a7, a7, 2
-; RV32IMZBS-NEXT: and t2, t2, s8
+; RV32IMZBS-NEXT: and t2, t2, s7
; RV32IMZBS-NEXT: slli a0, a0, 2
-; RV32IMZBS-NEXT: and t3, t3, s8
+; RV32IMZBS-NEXT: and t3, t3, s7
; RV32IMZBS-NEXT: slli a1, a1, 2
-; RV32IMZBS-NEXT: and t4, t4, s8
+; RV32IMZBS-NEXT: and t4, t4, s7
; RV32IMZBS-NEXT: slli a2, a2, 2
-; RV32IMZBS-NEXT: and t5, t5, s8
-; RV32IMZBS-NEXT: slli a3, a3, 2
-; RV32IMZBS-NEXT: and t6, t6, s8
+; RV32IMZBS-NEXT: and t5, t5, s7
; RV32IMZBS-NEXT: slli a4, a4, 2
-; RV32IMZBS-NEXT: and s0, s0, s8
+; RV32IMZBS-NEXT: and t6, t6, s7
; RV32IMZBS-NEXT: slli a5, a5, 2
-; RV32IMZBS-NEXT: or a6, t0, a6
+; RV32IMZBS-NEXT: and s0, s0, s7
+; RV32IMZBS-NEXT: slli a6, a6, 2
+; RV32IMZBS-NEXT: or a3, t0, a3
; RV32IMZBS-NEXT: or a7, t1, a7
; RV32IMZBS-NEXT: or a0, t2, a0
; RV32IMZBS-NEXT: or a1, t3, a1
-; RV32IMZBS-NEXT: or a2, t4, a2
-; RV32IMZBS-NEXT: or a3, t5, a3
-; RV32IMZBS-NEXT: or a4, t6, a4
-; RV32IMZBS-NEXT: or a5, s0, a5
-; RV32IMZBS-NEXT: srli t0, a6, 1
-; RV32IMZBS-NEXT: sw s6, 724(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a6, a6, s6
-; RV32IMZBS-NEXT: srli t1, a7, 1
-; RV32IMZBS-NEXT: and a7, a7, s6
-; RV32IMZBS-NEXT: srli t2, a0, 1
-; RV32IMZBS-NEXT: and a0, a0, s6
-; RV32IMZBS-NEXT: srli t3, a1, 1
-; RV32IMZBS-NEXT: and a1, a1, s6
-; RV32IMZBS-NEXT: srli t4, a2, 1
-; RV32IMZBS-NEXT: and a2, a2, s6
-; RV32IMZBS-NEXT: srli t5, a3, 1
-; RV32IMZBS-NEXT: and a3, a3, s6
+; RV32IMZBS-NEXT: or t0, t4, a2
+; RV32IMZBS-NEXT: or a4, t5, a4
+; RV32IMZBS-NEXT: or a5, t6, a5
+; RV32IMZBS-NEXT: or a2, s0, a6
+; RV32IMZBS-NEXT: srli a6, a3, 1
+; RV32IMZBS-NEXT: mv s6, s5
+; RV32IMZBS-NEXT: and t2, a3, s5
+; RV32IMZBS-NEXT: srli t3, a7, 1
+; RV32IMZBS-NEXT: and a7, a7, s5
+; RV32IMZBS-NEXT: srli t4, a0, 1
+; RV32IMZBS-NEXT: and a0, a0, s5
+; RV32IMZBS-NEXT: srli t5, a1, 1
+; RV32IMZBS-NEXT: and a1, a1, s5
+; RV32IMZBS-NEXT: srli t1, t0, 1
+; RV32IMZBS-NEXT: and t0, t0, s5
; RV32IMZBS-NEXT: srli t6, a4, 1
-; RV32IMZBS-NEXT: and a4, a4, s6
-; RV32IMZBS-NEXT: srli s0, a5, 1
-; RV32IMZBS-NEXT: and a5, a5, s6
-; RV32IMZBS-NEXT: and t0, t0, s6
-; RV32IMZBS-NEXT: slli a6, a6, 1
-; RV32IMZBS-NEXT: and t1, t1, s6
+; RV32IMZBS-NEXT: and a4, a4, s5
+; RV32IMZBS-NEXT: srli a3, a5, 1
+; RV32IMZBS-NEXT: and a5, a5, s5
+; RV32IMZBS-NEXT: and s0, a6, s5
+; RV32IMZBS-NEXT: slli t2, t2, 1
+; RV32IMZBS-NEXT: and t3, t3, s5
; RV32IMZBS-NEXT: slli a7, a7, 1
-; RV32IMZBS-NEXT: and t2, t2, s6
-; RV32IMZBS-NEXT: slli s1, a0, 1
-; RV32IMZBS-NEXT: and t3, t3, s6
-; RV32IMZBS-NEXT: slli s2, a1, 1
-; RV32IMZBS-NEXT: and t4, t4, s6
-; RV32IMZBS-NEXT: slli s3, a2, 1
-; RV32IMZBS-NEXT: and s4, t5, s6
-; RV32IMZBS-NEXT: slli s5, a3, 1
-; RV32IMZBS-NEXT: and t6, t6, s6
-; RV32IMZBS-NEXT: slli a4, a4, 1
-; RV32IMZBS-NEXT: and s0, s0, s6
-; RV32IMZBS-NEXT: slli t5, a5, 1
-; RV32IMZBS-NEXT: or s7, t0, a6
-; RV32IMZBS-NEXT: or a0, t1, a7
-; RV32IMZBS-NEXT: or ra, t2, s1
-; RV32IMZBS-NEXT: srli a2, a7, 31
-; RV32IMZBS-NEXT: or a1, t3, s2
-; RV32IMZBS-NEXT: srli a3, s2, 31
-; RV32IMZBS-NEXT: or a7, t4, s3
-; RV32IMZBS-NEXT: or t1, s4, s5
-; RV32IMZBS-NEXT: or t0, t6, a4
-; RV32IMZBS-NEXT: srli t3, s5, 31
-; RV32IMZBS-NEXT: or t2, s0, t5
-; RV32IMZBS-NEXT: srli t5, t5, 31
-; RV32IMZBS-NEXT: srli a4, s7, 8
-; RV32IMZBS-NEXT: srli a5, s7, 24
-; RV32IMZBS-NEXT: srli a6, a0, 8
-; RV32IMZBS-NEXT: srli t4, a0, 24
-; RV32IMZBS-NEXT: slli t6, a0, 24
-; RV32IMZBS-NEXT: and s0, a0, s10
-; RV32IMZBS-NEXT: slli s1, ra, 31
-; RV32IMZBS-NEXT: seqz a2, a2
-; RV32IMZBS-NEXT: slli s2, s7, 31
-; RV32IMZBS-NEXT: seqz a3, a3
-; RV32IMZBS-NEXT: srli s3, a7, 8
-; RV32IMZBS-NEXT: and a4, a4, s10
-; RV32IMZBS-NEXT: or a4, a4, a5
-; RV32IMZBS-NEXT: srli s4, a7, 24
-; RV32IMZBS-NEXT: and a5, a6, s10
-; RV32IMZBS-NEXT: or a5, a5, t4
-; RV32IMZBS-NEXT: srli t4, t1, 8
-; RV32IMZBS-NEXT: slli s0, s0, 8
-; RV32IMZBS-NEXT: or a6, t6, s0
-; RV32IMZBS-NEXT: srli t6, t1, 24
-; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: and s1, a2, s1
-; RV32IMZBS-NEXT: sw s1, 704(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a3, a3, s2
-; RV32IMZBS-NEXT: sw a3, 712(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a2, a2, s2
-; RV32IMZBS-NEXT: sw a2, 720(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli s0, t1, 24
-; RV32IMZBS-NEXT: and a2, s3, s10
-; RV32IMZBS-NEXT: or a3, a2, s4
-; RV32IMZBS-NEXT: and s1, t1, s10
-; RV32IMZBS-NEXT: and a2, t4, s10
-; RV32IMZBS-NEXT: or a2, a2, t6
-; RV32IMZBS-NEXT: slli t6, t0, 31
-; RV32IMZBS-NEXT: seqz s2, t3
-; RV32IMZBS-NEXT: slli s1, s1, 8
-; RV32IMZBS-NEXT: or t3, s0, s1
-; RV32IMZBS-NEXT: slli t4, a7, 31
-; RV32IMZBS-NEXT: seqz s0, t5
-; RV32IMZBS-NEXT: addi t5, s2, -1
-; RV32IMZBS-NEXT: addi s0, s0, -1
-; RV32IMZBS-NEXT: and t6, t5, t6
-; RV32IMZBS-NEXT: sw t6, 708(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and t6, s0, t4
-; RV32IMZBS-NEXT: sw t6, 716(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and t4, t5, t4
-; RV32IMZBS-NEXT: sw t4, 700(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and t4, s7, s10
-; RV32IMZBS-NEXT: sw s10, 740(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli t4, t4, 8
-; RV32IMZBS-NEXT: slli t5, s7, 24
-; RV32IMZBS-NEXT: or t4, t5, t4
-; RV32IMZBS-NEXT: or a4, t4, a4
-; RV32IMZBS-NEXT: sw a4, 692(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: or a4, a6, a5
-; RV32IMZBS-NEXT: sw a4, 696(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a4, a0, 2
-; RV32IMZBS-NEXT: seqz a4, a4
-; RV32IMZBS-NEXT: andi a5, a1, 2
-; RV32IMZBS-NEXT: seqz a5, a5
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 1
-; RV32IMZBS-NEXT: and s5, a4, a6
-; RV32IMZBS-NEXT: slli a6, s7, 1
-; RV32IMZBS-NEXT: and s3, a5, a6
-; RV32IMZBS-NEXT: and s2, a4, a6
-; RV32IMZBS-NEXT: andi a4, a0, 4
-; RV32IMZBS-NEXT: seqz a4, a4
-; RV32IMZBS-NEXT: andi a5, a1, 4
-; RV32IMZBS-NEXT: seqz a5, a5
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 2
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 644(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 2
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 660(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and s4, a4, a6
-; RV32IMZBS-NEXT: andi a4, a0, 8
-; RV32IMZBS-NEXT: seqz a4, a4
-; RV32IMZBS-NEXT: andi a5, a1, 8
-; RV32IMZBS-NEXT: seqz a5, a5
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 3
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 632(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 3
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 640(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 648(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a4, a0, 16
-; RV32IMZBS-NEXT: seqz a4, a4
-; RV32IMZBS-NEXT: andi a5, a1, 16
-; RV32IMZBS-NEXT: seqz a5, a5
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 4
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 612(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 4
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 628(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 636(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a4, a0, 32
-; RV32IMZBS-NEXT: seqz a4, a4
-; RV32IMZBS-NEXT: andi a5, a1, 32
-; RV32IMZBS-NEXT: seqz a5, a5
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 5
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 576(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 5
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 584(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 616(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a4, a0, 64
-; RV32IMZBS-NEXT: seqz a4, a4
-; RV32IMZBS-NEXT: andi a5, a1, 64
-; RV32IMZBS-NEXT: seqz a5, a5
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 6
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 652(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 6
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 668(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 680(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a4, a0, 128
-; RV32IMZBS-NEXT: seqz a4, a4
-; RV32IMZBS-NEXT: andi a5, a1, 128
-; RV32IMZBS-NEXT: seqz a5, a5
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 7
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 548(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 7
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 556(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 560(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a4, a0, 256
-; RV32IMZBS-NEXT: seqz a4, a4
-; RV32IMZBS-NEXT: andi a5, a1, 256
-; RV32IMZBS-NEXT: seqz a5, a5
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 8
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 516(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 8
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 540(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 552(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a4, a0, 512
-; RV32IMZBS-NEXT: seqz a4, a4
-; RV32IMZBS-NEXT: andi a5, a1, 512
-; RV32IMZBS-NEXT: seqz a5, a5
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 9
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 580(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 9
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 600(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 624(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a4, a0, 1024
-; RV32IMZBS-NEXT: seqz a4, a4
-; RV32IMZBS-NEXT: andi a5, a1, 1024
-; RV32IMZBS-NEXT: seqz a5, a5
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 10
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 676(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 10
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 684(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 688(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: not t6, a0
-; RV32IMZBS-NEXT: bexti a4, t6, 11
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: not s0, a1
-; RV32IMZBS-NEXT: bexti a5, s0, 11
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 11
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 464(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 11
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 476(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 488(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a4, t6, 12
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: bexti a5, s0, 12
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 12
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 452(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 12
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 460(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 468(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a4, t6, 13
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: bexti a5, s0, 13
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 13
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 508(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 13
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 524(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 544(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a4, t6, 14
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: bexti a5, s0, 14
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 14
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 592(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 14
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 608(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 620(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a4, t6, 15
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: bexti a5, s0, 15
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 15
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 656(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 15
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 664(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 672(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a4, t6, 16
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: bexti a5, s0, 16
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 16
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 416(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 16
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 424(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 428(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a4, t6, 17
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: bexti a5, s0, 17
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 17
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 408(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 17
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 412(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 420(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a4, t6, 18
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: bexti a5, s0, 18
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 18
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 444(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 18
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 448(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 456(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a4, t6, 19
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: bexti a5, s0, 19
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 19
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 504(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 19
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 512(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 520(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a4, t6, 20
+; RV32IMZBS-NEXT: and s1, t4, s5
+; RV32IMZBS-NEXT: slli s2, a0, 1
+; RV32IMZBS-NEXT: slli s3, t4, 31
+; RV32IMZBS-NEXT: and t4, t5, s5
+; RV32IMZBS-NEXT: slli s4, a1, 1
+; RV32IMZBS-NEXT: slli s5, a6, 31
+; RV32IMZBS-NEXT: and a6, t1, s6
+; RV32IMZBS-NEXT: slli t0, t0, 1
+; RV32IMZBS-NEXT: and t6, t6, s6
+; RV32IMZBS-NEXT: slli t5, a4, 1
+; RV32IMZBS-NEXT: and a4, a3, s6
+; RV32IMZBS-NEXT: mv s7, s6
+; RV32IMZBS-NEXT: slli a5, a5, 1
+; RV32IMZBS-NEXT: or s6, s0, t2
+; RV32IMZBS-NEXT: or a0, t3, a7
+; RV32IMZBS-NEXT: or s10, s1, s2
+; RV32IMZBS-NEXT: srli a7, a7, 31
+; RV32IMZBS-NEXT: or a1, t4, s4
+; RV32IMZBS-NEXT: srli s0, s4, 31
+; RV32IMZBS-NEXT: or t2, a6, t0
+; RV32IMZBS-NEXT: or t4, t6, t5
+; RV32IMZBS-NEXT: or t3, a4, a5
+; RV32IMZBS-NEXT: srli a4, s6, 8
+; RV32IMZBS-NEXT: srli a5, s6, 24
+; RV32IMZBS-NEXT: srli t0, a0, 8
+; RV32IMZBS-NEXT: srli t6, a0, 24
+; RV32IMZBS-NEXT: slli s1, a0, 24
+; RV32IMZBS-NEXT: and s2, a0, s9
+; RV32IMZBS-NEXT: seqz s4, a7
+; RV32IMZBS-NEXT: seqz s0, s0
+; RV32IMZBS-NEXT: and a4, a4, s9
+; RV32IMZBS-NEXT: or a6, a4, a5
+; RV32IMZBS-NEXT: srli a4, t2, 8
+; RV32IMZBS-NEXT: and a5, t0, s9
+; RV32IMZBS-NEXT: or a7, a5, t6
+; RV32IMZBS-NEXT: srli a5, t2, 24
+; RV32IMZBS-NEXT: slli s2, s2, 8
+; RV32IMZBS-NEXT: or t0, s1, s2
+; RV32IMZBS-NEXT: srli t6, t4, 8
+; RV32IMZBS-NEXT: addi s4, s4, -1
+; RV32IMZBS-NEXT: addi s0, s0, -1
+; RV32IMZBS-NEXT: and s1, s4, s3
+; RV32IMZBS-NEXT: sw s1, 696(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and s0, s0, s5
+; RV32IMZBS-NEXT: sw s0, 700(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and s0, s4, s5
+; RV32IMZBS-NEXT: sw s0, 704(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: srli s0, t4, 24
+; RV32IMZBS-NEXT: and a4, a4, s9
+; RV32IMZBS-NEXT: or s5, a4, a5
+; RV32IMZBS-NEXT: slli a4, t4, 24
+; RV32IMZBS-NEXT: and a5, t6, s9
+; RV32IMZBS-NEXT: or s11, a5, s0
+; RV32IMZBS-NEXT: and a5, t4, s9
+; RV32IMZBS-NEXT: slli a5, a5, 8
+; RV32IMZBS-NEXT: or a5, a4, a5
+; RV32IMZBS-NEXT: srli a4, a2, 1
+; RV32IMZBS-NEXT: sw s7, 708(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and s1, a2, s7
+; RV32IMZBS-NEXT: slli a2, a3, 31
+; RV32IMZBS-NEXT: and a3, a4, s7
+; RV32IMZBS-NEXT: slli s1, s1, 1
+; RV32IMZBS-NEXT: slli t1, t1, 31
+; RV32IMZBS-NEXT: srli a4, t5, 31
+; RV32IMZBS-NEXT: or s3, a3, s1
+; RV32IMZBS-NEXT: srli s1, s1, 31
+; RV32IMZBS-NEXT: seqz a3, a4
+; RV32IMZBS-NEXT: seqz a4, s1
+; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: bexti a5, s0, 20
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 20
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 564(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 20
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 568(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
+; RV32IMZBS-NEXT: and a2, a3, a2
+; RV32IMZBS-NEXT: sw a2, 688(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a4, t1
+; RV32IMZBS-NEXT: sw a2, 692(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a3, t1
+; RV32IMZBS-NEXT: sw a2, 684(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw s9, 724(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, s6, s9
+; RV32IMZBS-NEXT: slli a2, a2, 8
+; RV32IMZBS-NEXT: slli t1, s6, 24
+; RV32IMZBS-NEXT: or a2, t1, a2
+; RV32IMZBS-NEXT: or a2, a2, a6
+; RV32IMZBS-NEXT: sw a2, 676(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: or a2, t0, a7
+; RV32IMZBS-NEXT: sw a2, 680(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a2, a0, 2
+; RV32IMZBS-NEXT: seqz a2, a2
+; RV32IMZBS-NEXT: andi a3, a1, 2
+; RV32IMZBS-NEXT: seqz a3, a3
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 1
+; RV32IMZBS-NEXT: and s1, a2, a4
+; RV32IMZBS-NEXT: slli a4, s6, 1
+; RV32IMZBS-NEXT: and t6, a3, a4
+; RV32IMZBS-NEXT: and t0, a2, a4
+; RV32IMZBS-NEXT: andi a2, a0, 4
+; RV32IMZBS-NEXT: seqz a2, a2
+; RV32IMZBS-NEXT: andi a3, a1, 4
+; RV32IMZBS-NEXT: seqz a3, a3
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 2
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 640(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 2
+; RV32IMZBS-NEXT: and s2, a3, a4
+; RV32IMZBS-NEXT: and s0, a2, a4
+; RV32IMZBS-NEXT: andi a2, a0, 8
+; RV32IMZBS-NEXT: seqz a2, a2
+; RV32IMZBS-NEXT: andi a3, a1, 8
+; RV32IMZBS-NEXT: seqz a3, a3
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 3
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 628(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 3
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 636(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and s4, a2, a4
+; RV32IMZBS-NEXT: andi a2, a0, 16
+; RV32IMZBS-NEXT: seqz a2, a2
+; RV32IMZBS-NEXT: andi a3, a1, 16
+; RV32IMZBS-NEXT: seqz a3, a3
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 4
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 608(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 4
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 624(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 632(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a2, a0, 32
+; RV32IMZBS-NEXT: seqz a2, a2
+; RV32IMZBS-NEXT: andi a3, a1, 32
+; RV32IMZBS-NEXT: seqz a3, a3
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 5
+; RV32IMZBS-NEXT: and a4, a2, a4
; RV32IMZBS-NEXT: sw a4, 572(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a4, t6, 21
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: bexti a5, s0, 21
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 21
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 588(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 21
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 596(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 604(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a4, t6, 22
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: bexti a5, s0, 22
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 22
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 372(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 22
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 380(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 384(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a4, t6, 23
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: bexti a5, s0, 23
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 23
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 364(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 23
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 368(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 376(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a4, t6, 24
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: bexti a5, s0, 24
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 24
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 396(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a5, a5, t5
-; RV32IMZBS-NEXT: sw a5, 400(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, t5
+; RV32IMZBS-NEXT: slli a4, s6, 5
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 580(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 612(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a2, a0, 64
+; RV32IMZBS-NEXT: seqz a2, a2
+; RV32IMZBS-NEXT: andi a3, a1, 64
+; RV32IMZBS-NEXT: seqz a3, a3
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 6
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 4(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 6
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 652(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 664(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a2, a0, 128
+; RV32IMZBS-NEXT: seqz a2, a2
+; RV32IMZBS-NEXT: andi a3, a1, 128
+; RV32IMZBS-NEXT: seqz a3, a3
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 7
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 544(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 7
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 552(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 556(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a2, a0, 256
+; RV32IMZBS-NEXT: seqz a2, a2
+; RV32IMZBS-NEXT: andi a3, a1, 256
+; RV32IMZBS-NEXT: seqz a3, a3
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 8
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 512(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 8
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 536(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 548(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a2, a0, 512
+; RV32IMZBS-NEXT: seqz a2, a2
+; RV32IMZBS-NEXT: andi a3, a1, 512
+; RV32IMZBS-NEXT: seqz a3, a3
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 9
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 576(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 9
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 596(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 620(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a2, a0, 1024
+; RV32IMZBS-NEXT: seqz a2, a2
+; RV32IMZBS-NEXT: andi a3, a1, 1024
+; RV32IMZBS-NEXT: seqz a3, a3
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 10
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 660(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 10
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 668(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 672(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: not a6, a0
+; RV32IMZBS-NEXT: bexti a2, a6, 11
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: not a7, a1
+; RV32IMZBS-NEXT: bexti a3, a7, 11
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 11
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 460(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 11
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 472(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 484(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a2, a6, 12
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: bexti a3, a7, 12
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 12
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 448(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 12
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 456(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 464(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a2, a6, 13
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: bexti a3, a7, 13
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 13
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 504(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 13
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 520(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 540(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a2, a6, 14
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: bexti a3, a7, 14
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 14
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 588(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 14
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 604(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 616(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a2, a6, 15
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: bexti a3, a7, 15
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 15
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 644(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 15
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 648(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 656(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a2, a6, 16
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: bexti a3, a7, 16
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 16
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 412(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 16
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 420(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 424(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a2, a6, 17
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: bexti a3, a7, 17
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 17
+; RV32IMZBS-NEXT: and a4, a2, a4
; RV32IMZBS-NEXT: sw a4, 404(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a4, t6, 25
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: bexti a5, s0, 25
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 25
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 432(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 25
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 436(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
+; RV32IMZBS-NEXT: slli a4, s6, 17
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 408(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 416(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a2, a6, 18
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: bexti a3, a7, 18
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 18
+; RV32IMZBS-NEXT: and a4, a2, a4
; RV32IMZBS-NEXT: sw a4, 440(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a4, t6, 26
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: bexti a5, s0, 26
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 26
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 472(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 26
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 480(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 484(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a4, t6, 27
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: bexti a5, s0, 27
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 27
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 492(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 27
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 496(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
+; RV32IMZBS-NEXT: slli a4, s6, 18
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 444(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 452(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a2, a6, 19
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: bexti a3, a7, 19
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 19
+; RV32IMZBS-NEXT: and a4, a2, a4
; RV32IMZBS-NEXT: sw a4, 500(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a4, t6, 28
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: bexti a5, s0, 28
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 28
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 532(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 28
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 528(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a6
-; RV32IMZBS-NEXT: sw a4, 536(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a4, t6, 29
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: bexti a5, s0, 29
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, ra, 29
-; RV32IMZBS-NEXT: and a6, a4, a6
-; RV32IMZBS-NEXT: sw a6, 356(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s7, 29
-; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: sw a5, 360(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a6, a4, a6
+; RV32IMZBS-NEXT: slli a4, s6, 19
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 508(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 516(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a2, a6, 20
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: bexti a3, a7, 20
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 20
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 560(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 20
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 564(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 568(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a2, a6, 21
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: bexti a3, a7, 21
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 21
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 584(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 21
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 592(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 600(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a2, a6, 22
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: bexti a3, a7, 22
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 22
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 368(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 22
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 376(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 380(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a2, a6, 23
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: bexti a3, a7, 23
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 23
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 360(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 23
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 364(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 372(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a2, a6, 24
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: bexti a3, a7, 24
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 24
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 392(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a3, a3, t1
+; RV32IMZBS-NEXT: sw a3, 396(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, t1
+; RV32IMZBS-NEXT: sw a2, 400(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a2, a6, 25
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: bexti a3, a7, 25
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 25
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 428(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 25
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 432(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 436(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a2, a6, 26
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: bexti a3, a7, 26
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 26
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 468(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 26
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 476(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 480(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a2, a6, 27
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: bexti a3, a7, 27
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 27
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 488(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 27
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 492(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 496(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a2, a6, 28
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: bexti a3, a7, 28
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 28
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 528(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 28
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 524(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 532(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a2, a6, 29
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: bexti a3, a7, 29
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s10, 29
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 348(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s6, 29
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 352(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 356(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, a0, 1
; RV32IMZBS-NEXT: andi a1, a1, 1
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a4, ra, 30
-; RV32IMZBS-NEXT: and a5, a0, ra
-; RV32IMZBS-NEXT: sw a5, 320(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a1, a1, s7
-; RV32IMZBS-NEXT: sw a1, 344(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and ra, a0, s7
-; RV32IMZBS-NEXT: slli s7, s7, 30
-; RV32IMZBS-NEXT: bexti a0, t6, 30
-; RV32IMZBS-NEXT: bexti a1, s0, 30
+; RV32IMZBS-NEXT: slli a2, s10, 30
+; RV32IMZBS-NEXT: and a3, a0, s10
+; RV32IMZBS-NEXT: sw a3, 312(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a1, a1, s6
+; RV32IMZBS-NEXT: sw a1, 340(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and s10, a0, s6
+; RV32IMZBS-NEXT: slli s6, s6, 30
+; RV32IMZBS-NEXT: bexti a0, a6, 30
+; RV32IMZBS-NEXT: bexti a1, a7, 30
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: and a4, a0, a4
-; RV32IMZBS-NEXT: sw a4, 312(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a1, a1, s7
-; RV32IMZBS-NEXT: sw a1, 340(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and s7, a0, s7
-; RV32IMZBS-NEXT: and a0, a7, s10
+; RV32IMZBS-NEXT: and a2, a0, a2
+; RV32IMZBS-NEXT: sw a2, 308(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a1, a1, s6
+; RV32IMZBS-NEXT: sw a1, 336(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a6, a0, s6
+; RV32IMZBS-NEXT: and a0, t2, s9
; RV32IMZBS-NEXT: slli a0, a0, 8
-; RV32IMZBS-NEXT: slli s1, a7, 24
-; RV32IMZBS-NEXT: or a0, s1, a0
-; RV32IMZBS-NEXT: or a0, a0, a3
+; RV32IMZBS-NEXT: slli s8, t2, 24
+; RV32IMZBS-NEXT: or a0, s8, a0
+; RV32IMZBS-NEXT: or a0, a0, s5
+; RV32IMZBS-NEXT: sw a0, 384(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: or a0, a5, s11
; RV32IMZBS-NEXT: sw a0, 388(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: or a0, t3, a2
-; RV32IMZBS-NEXT: sw a0, 392(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, t1, 2
+; RV32IMZBS-NEXT: andi a0, t4, 2
; RV32IMZBS-NEXT: seqz a0, a0
-; RV32IMZBS-NEXT: andi a1, t2, 2
+; RV32IMZBS-NEXT: andi a1, s3, 2
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t0, 1
-; RV32IMZBS-NEXT: and a2, a0, a2
-; RV32IMZBS-NEXT: sw a2, 316(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a7, 1
-; RV32IMZBS-NEXT: and t3, a1, a2
-; RV32IMZBS-NEXT: and a0, a0, a2
-; RV32IMZBS-NEXT: sw a0, 352(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, t1, 4
+; RV32IMZBS-NEXT: slli a2, t3, 1
+; RV32IMZBS-NEXT: and s6, a0, a2
+; RV32IMZBS-NEXT: slli a2, t2, 1
+; RV32IMZBS-NEXT: and a1, a1, a2
+; RV32IMZBS-NEXT: sw a1, 332(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a7, a0, a2
+; RV32IMZBS-NEXT: andi a0, t4, 4
; RV32IMZBS-NEXT: seqz a0, a0
-; RV32IMZBS-NEXT: andi a1, t2, 4
+; RV32IMZBS-NEXT: andi a1, s3, 4
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t0, 2
+; RV32IMZBS-NEXT: slli a2, t3, 2
; RV32IMZBS-NEXT: and a2, a0, a2
-; RV32IMZBS-NEXT: sw a2, 292(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a7, 2
+; RV32IMZBS-NEXT: sw a2, 288(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a2, t2, 2
; RV32IMZBS-NEXT: and a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 308(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 304(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a0, a0, a2
-; RV32IMZBS-NEXT: sw a0, 328(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, t1, 8
+; RV32IMZBS-NEXT: sw a0, 320(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a0, t4, 8
; RV32IMZBS-NEXT: seqz a0, a0
-; RV32IMZBS-NEXT: andi a1, t2, 8
+; RV32IMZBS-NEXT: andi a1, s3, 8
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t0, 3
+; RV32IMZBS-NEXT: slli a2, t3, 3
; RV32IMZBS-NEXT: and a2, a0, a2
-; RV32IMZBS-NEXT: sw a2, 268(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a7, 3
+; RV32IMZBS-NEXT: sw a2, 264(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a2, t2, 3
; RV32IMZBS-NEXT: and a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 284(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 280(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a0, a0, a2
-; RV32IMZBS-NEXT: sw a0, 300(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, t1, 16
+; RV32IMZBS-NEXT: sw a0, 296(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a0, t4, 16
; RV32IMZBS-NEXT: seqz a0, a0
-; RV32IMZBS-NEXT: andi a1, t2, 16
+; RV32IMZBS-NEXT: andi a1, s3, 16
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t0, 4
+; RV32IMZBS-NEXT: slli a2, t3, 4
; RV32IMZBS-NEXT: and a2, a0, a2
-; RV32IMZBS-NEXT: sw a2, 248(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a7, 4
+; RV32IMZBS-NEXT: sw a2, 244(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a2, t2, 4
; RV32IMZBS-NEXT: and a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 264(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 260(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a0, a0, a2
-; RV32IMZBS-NEXT: sw a0, 272(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, t1, 32
+; RV32IMZBS-NEXT: sw a0, 268(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a0, t4, 32
; RV32IMZBS-NEXT: seqz a0, a0
-; RV32IMZBS-NEXT: andi a1, t2, 32
+; RV32IMZBS-NEXT: andi a1, s3, 32
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t0, 5
+; RV32IMZBS-NEXT: slli a2, t3, 5
; RV32IMZBS-NEXT: and a2, a0, a2
-; RV32IMZBS-NEXT: sw a2, 224(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a7, 5
+; RV32IMZBS-NEXT: sw a2, 220(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a2, t2, 5
; RV32IMZBS-NEXT: and a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 236(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 232(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a0, a0, a2
-; RV32IMZBS-NEXT: sw a0, 256(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, t1, 64
+; RV32IMZBS-NEXT: sw a0, 252(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a0, t4, 64
; RV32IMZBS-NEXT: seqz a0, a0
-; RV32IMZBS-NEXT: andi a1, t2, 64
+; RV32IMZBS-NEXT: andi a1, s3, 64
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t0, 6
+; RV32IMZBS-NEXT: slli a2, t3, 6
; RV32IMZBS-NEXT: and a2, a0, a2
-; RV32IMZBS-NEXT: sw a2, 296(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a7, 6
+; RV32IMZBS-NEXT: sw a2, 292(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a2, t2, 6
; RV32IMZBS-NEXT: and a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 304(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 300(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a0, a0, a2
-; RV32IMZBS-NEXT: sw a0, 324(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, t1, 128
+; RV32IMZBS-NEXT: sw a0, 316(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a0, t4, 128
; RV32IMZBS-NEXT: seqz a0, a0
-; RV32IMZBS-NEXT: andi a1, t2, 128
+; RV32IMZBS-NEXT: andi a1, s3, 128
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t0, 7
+; RV32IMZBS-NEXT: slli a2, t3, 7
; RV32IMZBS-NEXT: and a2, a0, a2
-; RV32IMZBS-NEXT: sw a2, 184(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a7, 7
+; RV32IMZBS-NEXT: sw a2, 180(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a2, t2, 7
; RV32IMZBS-NEXT: and a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 200(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 196(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a0, a0, a2
-; RV32IMZBS-NEXT: sw a0, 208(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, t1, 256
+; RV32IMZBS-NEXT: sw a0, 204(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a0, t4, 256
; RV32IMZBS-NEXT: seqz a0, a0
-; RV32IMZBS-NEXT: andi a1, t2, 256
+; RV32IMZBS-NEXT: andi a1, s3, 256
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t0, 8
+; RV32IMZBS-NEXT: slli a2, t3, 8
; RV32IMZBS-NEXT: and a2, a0, a2
-; RV32IMZBS-NEXT: sw a2, 168(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a7, 8
+; RV32IMZBS-NEXT: sw a2, 164(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a2, t2, 8
; RV32IMZBS-NEXT: and a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 180(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 176(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a0, a0, a2
-; RV32IMZBS-NEXT: sw a0, 188(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, t1, 512
+; RV32IMZBS-NEXT: sw a0, 184(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a0, t4, 512
; RV32IMZBS-NEXT: seqz a0, a0
-; RV32IMZBS-NEXT: andi a1, t2, 512
+; RV32IMZBS-NEXT: andi a1, s3, 512
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t0, 9
+; RV32IMZBS-NEXT: slli a2, t3, 9
; RV32IMZBS-NEXT: and a2, a0, a2
-; RV32IMZBS-NEXT: sw a2, 228(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a7, 9
+; RV32IMZBS-NEXT: sw a2, 224(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a2, t2, 9
; RV32IMZBS-NEXT: and a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 232(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 228(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a0, a0, a2
-; RV32IMZBS-NEXT: sw a0, 252(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, t1, 1024
+; RV32IMZBS-NEXT: sw a0, 248(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a0, t4, 1024
; RV32IMZBS-NEXT: seqz a0, a0
-; RV32IMZBS-NEXT: andi a1, t2, 1024
+; RV32IMZBS-NEXT: andi a1, s3, 1024
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t0, 10
+; RV32IMZBS-NEXT: slli a2, t3, 10
; RV32IMZBS-NEXT: and a2, a0, a2
-; RV32IMZBS-NEXT: sw a2, 332(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a7, 10
+; RV32IMZBS-NEXT: sw a2, 324(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a2, t2, 10
; RV32IMZBS-NEXT: and a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 336(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 328(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a0, a0, a2
-; RV32IMZBS-NEXT: sw a0, 348(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: not a1, t1
+; RV32IMZBS-NEXT: sw a0, 344(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: not a1, t4
; RV32IMZBS-NEXT: bexti a0, a1, 11
; RV32IMZBS-NEXT: addi a2, a0, -1
-; RV32IMZBS-NEXT: not a0, t2
+; RV32IMZBS-NEXT: not a0, s3
; RV32IMZBS-NEXT: bexti a3, a0, 11
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 11
+; RV32IMZBS-NEXT: slli a4, t3, 11
; RV32IMZBS-NEXT: and a4, a2, a4
-; RV32IMZBS-NEXT: sw a4, 112(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 11
+; RV32IMZBS-NEXT: sw a4, 108(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, t2, 11
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 128(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 124(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
-; RV32IMZBS-NEXT: sw a2, 136(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 132(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a2, a1, 12
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 12
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 12
+; RV32IMZBS-NEXT: slli a4, t3, 12
; RV32IMZBS-NEXT: and a4, a2, a4
-; RV32IMZBS-NEXT: sw a4, 88(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 12
+; RV32IMZBS-NEXT: sw a4, 84(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, t2, 12
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 104(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 100(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
-; RV32IMZBS-NEXT: sw a2, 116(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 112(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a2, a1, 13
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 13
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 13
+; RV32IMZBS-NEXT: slli a4, t3, 13
; RV32IMZBS-NEXT: and a4, a2, a4
-; RV32IMZBS-NEXT: sw a4, 140(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 13
+; RV32IMZBS-NEXT: sw a4, 136(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, t2, 13
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 164(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 160(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
-; RV32IMZBS-NEXT: sw a2, 176(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 172(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a2, a1, 14
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 14
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 14
+; RV32IMZBS-NEXT: slli a4, t3, 14
; RV32IMZBS-NEXT: and a4, a2, a4
-; RV32IMZBS-NEXT: sw a4, 240(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 14
+; RV32IMZBS-NEXT: sw a4, 236(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, t2, 14
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 244(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 240(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
-; RV32IMZBS-NEXT: sw a2, 260(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 256(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a2, a1, 15
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 15
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 15
+; RV32IMZBS-NEXT: slli a4, t3, 15
; RV32IMZBS-NEXT: and a4, a2, a4
-; RV32IMZBS-NEXT: sw a4, 276(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 15
+; RV32IMZBS-NEXT: sw a4, 272(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, t2, 15
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 280(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 276(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
-; RV32IMZBS-NEXT: sw a2, 288(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 284(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a2, a1, 16
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 16
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 16
+; RV32IMZBS-NEXT: slli a4, t3, 16
; RV32IMZBS-NEXT: and a4, a2, a4
-; RV32IMZBS-NEXT: sw a4, 52(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 16
+; RV32IMZBS-NEXT: sw a4, 48(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, t2, 16
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 60(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 56(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
-; RV32IMZBS-NEXT: sw a2, 64(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 60(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a2, a1, 17
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 17
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli s0, t0, 17
-; RV32IMZBS-NEXT: and s0, a2, s0
-; RV32IMZBS-NEXT: sw s0, 44(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 17
+; RV32IMZBS-NEXT: slli a4, t3, 17
+; RV32IMZBS-NEXT: and a4, a2, a4
+; RV32IMZBS-NEXT: sw a4, 40(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, t2, 17
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 48(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 44(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
-; RV32IMZBS-NEXT: sw a2, 56(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 52(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a2, a1, 18
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 18
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 18
+; RV32IMZBS-NEXT: slli a4, t3, 18
; RV32IMZBS-NEXT: and a4, a2, a4
-; RV32IMZBS-NEXT: sw a4, 76(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 18
+; RV32IMZBS-NEXT: sw a4, 72(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, t2, 18
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 84(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 80(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
-; RV32IMZBS-NEXT: sw a2, 92(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 88(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a2, a1, 19
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 19
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 19
+; RV32IMZBS-NEXT: slli a4, t3, 19
; RV32IMZBS-NEXT: and a4, a2, a4
-; RV32IMZBS-NEXT: sw a4, 144(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 19
+; RV32IMZBS-NEXT: sw a4, 140(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, t2, 19
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 160(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 156(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
-; RV32IMZBS-NEXT: sw a2, 172(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 168(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a2, a1, 20
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 20
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 20
+; RV32IMZBS-NEXT: slli a4, t3, 20
; RV32IMZBS-NEXT: and a4, a2, a4
-; RV32IMZBS-NEXT: sw a4, 192(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 20
+; RV32IMZBS-NEXT: sw a4, 188(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, t2, 20
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 196(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 192(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
-; RV32IMZBS-NEXT: sw a2, 204(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 200(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a2, a1, 21
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 21
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 21
+; RV32IMZBS-NEXT: slli a4, t3, 21
; RV32IMZBS-NEXT: and a4, a2, a4
-; RV32IMZBS-NEXT: sw a4, 212(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 21
+; RV32IMZBS-NEXT: sw a4, 208(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, t2, 21
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 216(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 212(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
-; RV32IMZBS-NEXT: sw a2, 220(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 216(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a2, a1, 22
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 22
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 22
+; RV32IMZBS-NEXT: slli a4, t3, 22
; RV32IMZBS-NEXT: and a4, a2, a4
-; RV32IMZBS-NEXT: sw a4, 20(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a5, a7, 22
+; RV32IMZBS-NEXT: sw a4, 16(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a5, t2, 22
; RV32IMZBS-NEXT: and a4, a3, a5
; RV32IMZBS-NEXT: and a2, a2, a5
-; RV32IMZBS-NEXT: sw a2, 28(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 24(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a2, a1, 23
; RV32IMZBS-NEXT: addi a5, a2, -1
; RV32IMZBS-NEXT: bexti a2, a0, 23
; RV32IMZBS-NEXT: addi a3, a2, -1
-; RV32IMZBS-NEXT: slli a2, t0, 23
+; RV32IMZBS-NEXT: slli a2, t3, 23
; RV32IMZBS-NEXT: and a2, a5, a2
-; RV32IMZBS-NEXT: sw a2, 16(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli t4, a7, 23
-; RV32IMZBS-NEXT: and a3, a3, t4
-; RV32IMZBS-NEXT: and a2, a5, t4
-; RV32IMZBS-NEXT: sw a2, 24(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti t4, a1, 24
-; RV32IMZBS-NEXT: addi t6, t4, -1
-; RV32IMZBS-NEXT: bexti t4, a0, 24
-; RV32IMZBS-NEXT: addi t5, t4, -1
-; RV32IMZBS-NEXT: slli t4, t0, 24
-; RV32IMZBS-NEXT: and a2, t6, t4
+; RV32IMZBS-NEXT: sw a2, 12(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli t1, t2, 23
+; RV32IMZBS-NEXT: and a3, a3, t1
+; RV32IMZBS-NEXT: and a2, a5, t1
+; RV32IMZBS-NEXT: sw a2, 20(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti t1, a1, 24
+; RV32IMZBS-NEXT: addi s5, t1, -1
+; RV32IMZBS-NEXT: bexti t1, a0, 24
+; RV32IMZBS-NEXT: addi t5, t1, -1
+; RV32IMZBS-NEXT: slli t1, t3, 24
+; RV32IMZBS-NEXT: and a2, s5, t1
+; RV32IMZBS-NEXT: sw a2, 28(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, t5, s8
; RV32IMZBS-NEXT: sw a2, 32(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a2, t5, s1
+; RV32IMZBS-NEXT: and a2, s5, s8
; RV32IMZBS-NEXT: sw a2, 36(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a2, t6, s1
-; RV32IMZBS-NEXT: sw a2, 40(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti s1, a1, 25
-; RV32IMZBS-NEXT: addi s8, s1, -1
-; RV32IMZBS-NEXT: bexti s1, a0, 25
-; RV32IMZBS-NEXT: addi s6, s1, -1
-; RV32IMZBS-NEXT: slli s1, t0, 25
-; RV32IMZBS-NEXT: and a2, s8, s1
+; RV32IMZBS-NEXT: bexti s5, a1, 25
+; RV32IMZBS-NEXT: addi s8, s5, -1
+; RV32IMZBS-NEXT: bexti s5, a0, 25
+; RV32IMZBS-NEXT: addi s5, s5, -1
+; RV32IMZBS-NEXT: slli s9, t3, 25
+; RV32IMZBS-NEXT: and a2, s8, s9
+; RV32IMZBS-NEXT: sw a2, 64(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli s9, t2, 25
+; RV32IMZBS-NEXT: and a2, s5, s9
; RV32IMZBS-NEXT: sw a2, 68(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli s9, a7, 25
-; RV32IMZBS-NEXT: and a2, s6, s9
-; RV32IMZBS-NEXT: sw a2, 72(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, s8, s9
-; RV32IMZBS-NEXT: sw a2, 80(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 76(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti s8, a1, 26
; RV32IMZBS-NEXT: addi s8, s8, -1
; RV32IMZBS-NEXT: bexti s9, a0, 26
; RV32IMZBS-NEXT: addi s9, s9, -1
-; RV32IMZBS-NEXT: slli s10, t0, 26
-; RV32IMZBS-NEXT: and a2, s8, s10
+; RV32IMZBS-NEXT: slli s11, t3, 26
+; RV32IMZBS-NEXT: and a2, s8, s11
+; RV32IMZBS-NEXT: sw a2, 92(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli s11, t2, 26
+; RV32IMZBS-NEXT: and a2, s9, s11
; RV32IMZBS-NEXT: sw a2, 96(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli s10, a7, 26
-; RV32IMZBS-NEXT: and a2, s9, s10
-; RV32IMZBS-NEXT: sw a2, 100(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a2, s8, s10
-; RV32IMZBS-NEXT: sw a2, 108(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, s8, s11
+; RV32IMZBS-NEXT: sw a2, 104(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti s8, a1, 27
; RV32IMZBS-NEXT: addi s8, s8, -1
; RV32IMZBS-NEXT: bexti s9, a0, 27
; RV32IMZBS-NEXT: addi s9, s9, -1
-; RV32IMZBS-NEXT: slli s10, t0, 27
-; RV32IMZBS-NEXT: and a2, s8, s10
+; RV32IMZBS-NEXT: slli s11, t3, 27
+; RV32IMZBS-NEXT: and a2, s8, s11
+; RV32IMZBS-NEXT: sw a2, 116(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli s11, t2, 27
+; RV32IMZBS-NEXT: and a2, s9, s11
; RV32IMZBS-NEXT: sw a2, 120(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli s10, a7, 27
-; RV32IMZBS-NEXT: and a2, s9, s10
-; RV32IMZBS-NEXT: sw a2, 124(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a2, s8, s10
-; RV32IMZBS-NEXT: sw a2, 132(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, s8, s11
+; RV32IMZBS-NEXT: sw a2, 128(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti s8, a1, 28
; RV32IMZBS-NEXT: addi s8, s8, -1
; RV32IMZBS-NEXT: bexti s9, a0, 28
; RV32IMZBS-NEXT: addi s9, s9, -1
-; RV32IMZBS-NEXT: slli s10, t0, 28
-; RV32IMZBS-NEXT: and a2, s8, s10
-; RV32IMZBS-NEXT: sw a2, 152(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli s10, a7, 28
-; RV32IMZBS-NEXT: and a2, s9, s10
+; RV32IMZBS-NEXT: slli s11, t3, 28
+; RV32IMZBS-NEXT: and a2, s8, s11
; RV32IMZBS-NEXT: sw a2, 148(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a2, s8, s10
-; RV32IMZBS-NEXT: sw a2, 156(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli s11, t2, 28
+; RV32IMZBS-NEXT: and a2, s9, s11
+; RV32IMZBS-NEXT: sw a2, 144(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a2, s8, s11
+; RV32IMZBS-NEXT: sw a2, 152(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti s8, a1, 29
; RV32IMZBS-NEXT: addi s8, s8, -1
; RV32IMZBS-NEXT: bexti s9, a0, 29
; RV32IMZBS-NEXT: addi s9, s9, -1
-; RV32IMZBS-NEXT: slli s10, t0, 29
-; RV32IMZBS-NEXT: and t4, s8, s10
-; RV32IMZBS-NEXT: slli s11, a7, 29
-; RV32IMZBS-NEXT: and a5, s9, s11
-; RV32IMZBS-NEXT: and a2, s8, s11
-; RV32IMZBS-NEXT: sw a2, 12(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi t1, t1, 1
-; RV32IMZBS-NEXT: andi t2, t2, 1
-; RV32IMZBS-NEXT: seqz t1, t1
-; RV32IMZBS-NEXT: seqz t2, t2
-; RV32IMZBS-NEXT: addi t1, t1, -1
-; RV32IMZBS-NEXT: addi t2, t2, -1
-; RV32IMZBS-NEXT: slli s11, t0, 30
-; RV32IMZBS-NEXT: and t0, t1, t0
-; RV32IMZBS-NEXT: and t2, t2, a7
-; RV32IMZBS-NEXT: and a2, t1, a7
+; RV32IMZBS-NEXT: slli s11, t3, 29
+; RV32IMZBS-NEXT: and t1, s8, s11
+; RV32IMZBS-NEXT: slli ra, t2, 29
+; RV32IMZBS-NEXT: and a5, s9, ra
+; RV32IMZBS-NEXT: and a2, s8, ra
; RV32IMZBS-NEXT: sw a2, 8(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a7, a7, 30
+; RV32IMZBS-NEXT: andi t4, t4, 1
+; RV32IMZBS-NEXT: andi s3, s3, 1
+; RV32IMZBS-NEXT: seqz t4, t4
+; RV32IMZBS-NEXT: seqz s3, s3
+; RV32IMZBS-NEXT: addi t4, t4, -1
+; RV32IMZBS-NEXT: addi s3, s3, -1
+; RV32IMZBS-NEXT: slli ra, t3, 30
+; RV32IMZBS-NEXT: and t3, t4, t3
+; RV32IMZBS-NEXT: and s3, s3, t2
+; RV32IMZBS-NEXT: and s7, t4, t2
+; RV32IMZBS-NEXT: slli t2, t2, 30
; RV32IMZBS-NEXT: bexti a1, a1, 30
; RV32IMZBS-NEXT: bexti a0, a0, 30
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: addi a0, a0, -1
-; RV32IMZBS-NEXT: and s11, a1, s11
-; RV32IMZBS-NEXT: and a0, a0, a7
-; RV32IMZBS-NEXT: and a1, a1, a7
-; RV32IMZBS-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 320(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a1, a1, s5
-; RV32IMZBS-NEXT: sw a1, 320(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 644(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 632(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 644(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 612(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 576(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 612(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 548(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 516(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 576(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 464(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 452(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: and ra, a1, ra
+; RV32IMZBS-NEXT: and a0, a0, t2
+; RV32IMZBS-NEXT: and a1, a1, t2
+; RV32IMZBS-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 312(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a1, a1, s1
+; RV32IMZBS-NEXT: sw a1, 312(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 640(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 628(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 548(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 416(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 408(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 640(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 608(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 572(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 516(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 372(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 364(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 628(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 544(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 512(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 464(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 356(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 312(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 572(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 460(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 448(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 452(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 344(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a1, a1, s3
-; RV32IMZBS-NEXT: sw a1, 632(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 660(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 640(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 544(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 412(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 404(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 416(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 628(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 584(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 512(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 368(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 360(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 584(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 556(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 540(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 460(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 348(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 308(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 556(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 476(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 460(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 448(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 340(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a1, a1, t6
+; RV32IMZBS-NEXT: sw a1, 608(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 636(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a1, s2, a1
+; RV32IMZBS-NEXT: sw a1, 412(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 624(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 580(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 540(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 424(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 412(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 580(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 552(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 536(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 476(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 380(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 368(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 536(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 472(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 456(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 460(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 360(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 340(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 472(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 420(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 408(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 424(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: xor a1, ra, s2
-; RV32IMZBS-NEXT: sw a1, 628(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 648(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor ra, s4, a1
-; RV32IMZBS-NEXT: lw a1, 636(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 616(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 456(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 376(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 364(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 412(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 560(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 552(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 420(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 352(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 336(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
+; RV32IMZBS-NEXT: sw a1, 408(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: xor a1, s10, t0
; RV32IMZBS-NEXT: sw a1, 552(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 488(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 468(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s10, s0, s4
+; RV32IMZBS-NEXT: lw a1, 632(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 612(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s11, a1, a2
+; RV32IMZBS-NEXT: lw a1, 556(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 548(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 488(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 428(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 420(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 548(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 484(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 464(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a1, a1, a2
+; RV32IMZBS-NEXT: sw a1, 464(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 424(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 416(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 468(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 384(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 376(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 424(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 380(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 372(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 428(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: xor s9, a6, s7
-; RV32IMZBS-NEXT: lw a1, 316(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s10, t0, a1
-; RV32IMZBS-NEXT: lw a1, 292(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 268(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 416(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 356(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s9, a1, a6
+; RV32IMZBS-NEXT: xor a1, t3, s6
+; RV32IMZBS-NEXT: sw a1, 484(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 288(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 264(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s5, a1, a2
+; RV32IMZBS-NEXT: lw a1, 244(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 220(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s6, a1, a2
-; RV32IMZBS-NEXT: lw a1, 248(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s0, 224(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 180(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s0, 164(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s0, a1, s0
-; RV32IMZBS-NEXT: lw a1, 184(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s1, 168(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 108(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s1, 84(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s1, a1, s1
-; RV32IMZBS-NEXT: lw a1, 112(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 88(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s3, a1, a2
-; RV32IMZBS-NEXT: lw a1, 52(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 44(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 48(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 40(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s2, a1, a2
+; RV32IMZBS-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 12(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s4, a1, a2
-; RV32IMZBS-NEXT: lw a1, 20(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 16(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s5, a1, a2
-; RV32IMZBS-NEXT: xor s11, t4, s11
-; RV32IMZBS-NEXT: xor s2, t2, t3
-; RV32IMZBS-NEXT: lw a1, 308(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 284(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor ra, t1, ra
+; RV32IMZBS-NEXT: lw a1, 332(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s3, s3, a1
+; RV32IMZBS-NEXT: lw a1, 304(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 280(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t1, a1, a2
-; RV32IMZBS-NEXT: lw a1, 264(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 236(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 260(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 232(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t2, a1, a2
-; RV32IMZBS-NEXT: lw a1, 200(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 180(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 196(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 176(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t3, a1, a2
-; RV32IMZBS-NEXT: lw a1, 128(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 104(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 124(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 100(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t4, a1, a2
-; RV32IMZBS-NEXT: lw a1, 60(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 48(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 56(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 44(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t5, a1, a2
; RV32IMZBS-NEXT: xor t6, a4, a3
; RV32IMZBS-NEXT: xor t0, a5, a0
-; RV32IMZBS-NEXT: lw a0, 352(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 8(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a7, a1, a0
-; RV32IMZBS-NEXT: lw a0, 328(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 300(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a7, s7, a7
+; RV32IMZBS-NEXT: lw a0, 320(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 296(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a0, a1
-; RV32IMZBS-NEXT: lw a1, 272(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 256(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 268(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 252(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: lw a2, 208(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a3, 188(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 204(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a3, 184(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a2, a2, a3
-; RV32IMZBS-NEXT: lw a3, 136(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a4, 116(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a3, 132(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a4, 112(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a3, a3, a4
-; RV32IMZBS-NEXT: lw a4, 64(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a5, 56(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a4, 60(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a5, 52(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a4, a4, a5
-; RV32IMZBS-NEXT: lw a5, 28(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a6, 24(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a5, 24(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a6, 20(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a5, a5, a6
-; RV32IMZBS-NEXT: lw a6, 12(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s7, 4(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a6, 8(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s7, 0(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a6, a6, s7
-; RV32IMZBS-NEXT: lw s7, 320(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 644(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s7, 312(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 640(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s7, s7, s8
-; RV32IMZBS-NEXT: sw s7, 660(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s7, 652(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 612(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s7, s8, s7
-; RV32IMZBS-NEXT: sw s7, 652(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s7, 580(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 576(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s7, s8, s7
-; RV32IMZBS-NEXT: sw s7, 648(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s7, 508(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 548(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s7, s8, s7
-; RV32IMZBS-NEXT: sw s7, 644(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s7, 444(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 516(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s7, s8, s7
; RV32IMZBS-NEXT: sw s7, 640(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s7, 396(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 464(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s7, 4(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 628(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s7, s8, s7
; RV32IMZBS-NEXT: sw s7, 636(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s7, 704(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 452(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s7, 576(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 572(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s7, s8, s7
-; RV32IMZBS-NEXT: sw s7, 704(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s7, 632(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 416(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s7, s7, s8
-; RV32IMZBS-NEXT: sw s7, 616(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s7, 668(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 584(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw s7, 632(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 504(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 544(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s7, s8, s7
-; RV32IMZBS-NEXT: sw s7, 612(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s7, 600(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 556(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw s7, 628(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 440(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 512(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s7, s8, s7
-; RV32IMZBS-NEXT: sw s7, 600(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s7, 524(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 540(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw s7, 624(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 392(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 460(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s8, s7
+; RV32IMZBS-NEXT: sw s7, 612(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 696(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 448(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s7, s8, s7
-; RV32IMZBS-NEXT: sw s7, 584(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s7, 448(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 476(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw s7, 696(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 608(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 412(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s7, s8
+; RV32IMZBS-NEXT: sw s7, 608(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 652(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 580(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s7, s8, s7
; RV32IMZBS-NEXT: sw s7, 580(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s7, 400(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 460(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s7, 596(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 536(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s8, s7
+; RV32IMZBS-NEXT: sw s7, 596(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 520(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 472(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s7, s8, s7
; RV32IMZBS-NEXT: sw s7, 576(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s7, 712(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 424(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s7, 444(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 456(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s7, s8, s7
-; RV32IMZBS-NEXT: sw s7, 712(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s7, 628(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s7, s7, ra
-; RV32IMZBS-NEXT: sw s7, 560(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s7, 680(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 412(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor ra, s8, s7
-; RV32IMZBS-NEXT: lw s7, 624(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 552(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw s7, 572(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 396(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 420(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s7, s8, s7
; RV32IMZBS-NEXT: sw s7, 556(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s7, 544(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 488(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s7, 700(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 408(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s7, s8, s7
+; RV32IMZBS-NEXT: sw s7, 700(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 552(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s7, s10
; RV32IMZBS-NEXT: sw s7, 552(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s7, 456(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 468(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s7, 664(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s11, s11, s7
+; RV32IMZBS-NEXT: lw s7, 620(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 548(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s10, s8, s7
+; RV32IMZBS-NEXT: lw s7, 540(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 464(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s7, s8, s7
; RV32IMZBS-NEXT: sw s7, 548(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s7, 404(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 428(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s7, 452(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 424(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s8, s7
+; RV32IMZBS-NEXT: sw s7, 544(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 400(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 416(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s8, s8, s7
-; RV32IMZBS-NEXT: lw s7, 720(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s7, 704(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s7, s9, s7
-; RV32IMZBS-NEXT: sw s7, 720(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: xor s6, s10, s6
-; RV32IMZBS-NEXT: sw s6, 680(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s6, 296(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s6, s0, s6
-; RV32IMZBS-NEXT: lw s0, 228(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw s7, 704(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 484(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s5, s7, s5
+; RV32IMZBS-NEXT: sw s5, 664(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s5, 292(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s6, s6, s5
+; RV32IMZBS-NEXT: lw s5, 224(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s5, s0, s5
+; RV32IMZBS-NEXT: lw s0, 136(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s1, s1, s0
-; RV32IMZBS-NEXT: lw s0, 140(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s3, s3, s0
-; RV32IMZBS-NEXT: lw s0, 76(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s2, s2, s0
+; RV32IMZBS-NEXT: lw s0, 28(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s4, s4, s0
-; RV32IMZBS-NEXT: lw s0, 32(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s0, s5, s0
-; RV32IMZBS-NEXT: sw s0, 668(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s0, 708(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s0, s11, s0
-; RV32IMZBS-NEXT: sw s0, 708(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: xor s0, s2, t1
-; RV32IMZBS-NEXT: lw t1, 304(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s0, 688(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s0, ra, s0
+; RV32IMZBS-NEXT: sw s0, 688(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: xor s0, s3, t1
+; RV32IMZBS-NEXT: lw t1, 300(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t2, t2, t1
-; RV32IMZBS-NEXT: lw t1, 232(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t1, 228(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t3, t3, t1
-; RV32IMZBS-NEXT: lw t1, 164(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t1, 160(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t4, t4, t1
-; RV32IMZBS-NEXT: lw t1, 84(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t1, 80(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t5, t5, t1
-; RV32IMZBS-NEXT: lw t1, 36(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t1, 32(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t6, t6, t1
-; RV32IMZBS-NEXT: lw t1, 716(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t1, 692(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, t0, t1
-; RV32IMZBS-NEXT: sw t0, 716(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw t0, 692(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: xor a7, a7, a0
-; RV32IMZBS-NEXT: lw a0, 324(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 316(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, a1, a0
-; RV32IMZBS-NEXT: lw a0, 252(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 248(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t1, a2, a0
-; RV32IMZBS-NEXT: lw a0, 176(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a0, a3, a0
-; RV32IMZBS-NEXT: sw a0, 632(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 92(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 172(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a3, a3, a0
+; RV32IMZBS-NEXT: lw a0, 88(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a4, a0
-; RV32IMZBS-NEXT: sw a0, 628(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 40(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a0, 652(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a5, a0
-; RV32IMZBS-NEXT: sw a0, 624(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 700(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a0, 620(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a0, 684(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a6, a0
-; RV32IMZBS-NEXT: sw a0, 700(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a4, 692(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: srli a3, a4, 4
-; RV32IMZBS-NEXT: lw a1, 744(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: and a4, a4, a1
-; RV32IMZBS-NEXT: and a3, a3, a1
-; RV32IMZBS-NEXT: slli a4, a4, 4
-; RV32IMZBS-NEXT: or a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 692(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a5, 696(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a0, 684(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a5, 676(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: srli a4, a5, 4
-; RV32IMZBS-NEXT: and a5, a5, a1
-; RV32IMZBS-NEXT: and a4, a4, a1
+; RV32IMZBS-NEXT: lw a0, 728(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: and a5, a5, a0
+; RV32IMZBS-NEXT: and a4, a4, a0
; RV32IMZBS-NEXT: slli a5, a5, 4
; RV32IMZBS-NEXT: or a4, a4, a5
-; RV32IMZBS-NEXT: sw a4, 696(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a4, 676(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 680(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: srli a5, a1, 4
+; RV32IMZBS-NEXT: and a6, a1, a0
+; RV32IMZBS-NEXT: and a5, a5, a0
+; RV32IMZBS-NEXT: mv a1, a0
+; RV32IMZBS-NEXT: slli a6, a6, 4
+; RV32IMZBS-NEXT: or a0, a5, a6
+; RV32IMZBS-NEXT: sw a0, 680(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a0, 640(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 636(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a4, a0, a2
; RV32IMZBS-NEXT: lw a0, 660(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 652(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a3, a0, a2
-; RV32IMZBS-NEXT: lw a0, 676(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 648(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a4, a2, a0
-; RV32IMZBS-NEXT: lw a0, 592(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 644(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 632(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a5, a2, a0
-; RV32IMZBS-NEXT: lw a0, 504(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 640(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a0, a2, a0
-; RV32IMZBS-NEXT: sw a0, 660(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 432(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 636(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 588(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 628(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a6, a2, a0
+; RV32IMZBS-NEXT: lw a0, 500(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 624(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a2, a0
-; RV32IMZBS-NEXT: sw a0, 652(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 616(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a0, 640(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a0, 428(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a2, 612(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a0, a0, a2
-; RV32IMZBS-NEXT: sw a0, 676(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 684(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 600(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s11, a2, a0
-; RV32IMZBS-NEXT: lw a0, 608(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 584(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a2, a0
-; RV32IMZBS-NEXT: sw a0, 644(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 512(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a0, 636(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a0, 608(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a2, 580(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a0, a0, a2
+; RV32IMZBS-NEXT: sw a0, 660(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a0, 668(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 596(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a2, a0
-; RV32IMZBS-NEXT: sw a0, 640(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 436(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a0, 628(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a0, 604(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a2, 576(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a2, a0
-; RV32IMZBS-NEXT: sw a0, 636(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 560(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a0, a0, ra
-; RV32IMZBS-NEXT: sw a0, 648(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 688(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a0, 624(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a0, 508(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 572(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a0, a2, a0
+; RV32IMZBS-NEXT: sw a0, 612(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a0, 432(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a2, 556(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor ra, a2, a0
-; RV32IMZBS-NEXT: lw a0, 620(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 552(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a2, a0
-; RV32IMZBS-NEXT: sw a0, 620(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 520(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a0, 608(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a0, 552(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a0, a0, s11
+; RV32IMZBS-NEXT: sw a0, 632(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a0, 672(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s10, s10, a0
+; RV32IMZBS-NEXT: lw a0, 616(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a2, 548(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor ra, a2, a0
+; RV32IMZBS-NEXT: lw a0, 516(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 544(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s9, a2, a0
-; RV32IMZBS-NEXT: lw a0, 440(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s10, s8, a0
-; RV32IMZBS-NEXT: lw a0, 388(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 436(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s11, s8, a0
+; RV32IMZBS-NEXT: lw a0, 384(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: srli s7, a0, 4
; RV32IMZBS-NEXT: and s8, a0, a1
; RV32IMZBS-NEXT: and s7, s7, a1
; RV32IMZBS-NEXT: slli s8, s8, 4
; RV32IMZBS-NEXT: or a0, s7, s8
-; RV32IMZBS-NEXT: sw a0, 688(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 392(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a0, 672(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a0, 388(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: srli s8, a0, 4
; RV32IMZBS-NEXT: and a0, a0, a1
; RV32IMZBS-NEXT: and s8, s8, a1
; RV32IMZBS-NEXT: slli a0, a0, 4
; RV32IMZBS-NEXT: or a0, s8, a0
-; RV32IMZBS-NEXT: sw a0, 684(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 680(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a0, 668(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a0, 664(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s7, a0, s6
-; RV32IMZBS-NEXT: lw a0, 332(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s5, s1, a0
-; RV32IMZBS-NEXT: lw a0, 240(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s6, s3, a0
-; RV32IMZBS-NEXT: lw a0, 144(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s2, s4, a0
-; RV32IMZBS-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 668(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s3, a1, a0
+; RV32IMZBS-NEXT: lw a0, 324(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s5, s5, a0
+; RV32IMZBS-NEXT: lw a0, 236(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s6, s1, a0
+; RV32IMZBS-NEXT: lw a0, 140(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s2, s2, a0
+; RV32IMZBS-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s3, s4, a0
; RV32IMZBS-NEXT: xor s4, s0, t2
-; RV32IMZBS-NEXT: lw a0, 336(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 328(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s0, t3, a0
-; RV32IMZBS-NEXT: lw a0, 244(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 240(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s1, t4, a0
-; RV32IMZBS-NEXT: lw a0, 160(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 156(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t4, t5, a0
-; RV32IMZBS-NEXT: lw a0, 72(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t5, t6, a0
; RV32IMZBS-NEXT: xor t6, a7, t0
-; RV32IMZBS-NEXT: lw a0, 348(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 344(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t2, t1, a0
-; RV32IMZBS-NEXT: lw a0, 260(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 632(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t3, a1, a0
-; RV32IMZBS-NEXT: lw a0, 172(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 628(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 256(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor t3, a3, a0
+; RV32IMZBS-NEXT: lw a0, 168(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 652(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a7, a1, a0
-; RV32IMZBS-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 624(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 620(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, a1, a0
-; RV32IMZBS-NEXT: xor t1, a3, a4
-; RV32IMZBS-NEXT: lw a0, 656(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a6, a5, a0
-; RV32IMZBS-NEXT: lw a0, 564(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a4, 660(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a4, a4, a0
-; RV32IMZBS-NEXT: lw a0, 472(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a5, 652(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor t1, a4, a5
+; RV32IMZBS-NEXT: lw a0, 644(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a4, a6, a0
+; RV32IMZBS-NEXT: lw a0, 560(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a5, 640(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a5, a5, a0
-; RV32IMZBS-NEXT: lw a0, 676(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s11, a0, s11
-; RV32IMZBS-NEXT: lw a0, 664(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a3, 644(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a3, a3, a0
-; RV32IMZBS-NEXT: lw a0, 568(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 640(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a1, a1, a0
-; RV32IMZBS-NEXT: lw a0, 480(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 636(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a2, a2, a0
+; RV32IMZBS-NEXT: lw a0, 468(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 636(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a6, a1, a0
+; RV32IMZBS-NEXT: lw a0, 660(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a3, 628(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a3, a0, a3
; RV32IMZBS-NEXT: lw a0, 648(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor ra, a0, ra
-; RV32IMZBS-NEXT: lw a0, 672(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 620(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a0, s8, a0
-; RV32IMZBS-NEXT: lw s8, 572(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 624(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a0, a1, a0
+; RV32IMZBS-NEXT: lw a1, 564(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 612(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a1, a2, a1
+; RV32IMZBS-NEXT: lw a2, 476(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 608(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a2, s8, a2
+; RV32IMZBS-NEXT: lw s8, 632(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s10, s8, s10
+; RV32IMZBS-NEXT: lw s8, 656(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor ra, ra, s8
+; RV32IMZBS-NEXT: lw s8, 568(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s9, s9, s8
-; RV32IMZBS-NEXT: lw s8, 484(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s10, s10, s8
+; RV32IMZBS-NEXT: lw s8, 480(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s11, s11, s8
; RV32IMZBS-NEXT: xor s5, s7, s5
-; RV32IMZBS-NEXT: lw s7, 276(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s7, 272(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s6, s6, s7
-; RV32IMZBS-NEXT: lw s7, 192(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s7, 188(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s2, s2, s7
-; RV32IMZBS-NEXT: lw s7, 96(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s7, 92(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s3, s3, s7
; RV32IMZBS-NEXT: xor s0, s4, s0
-; RV32IMZBS-NEXT: lw s4, 280(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s4, 276(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s1, s1, s4
-; RV32IMZBS-NEXT: lw s4, 196(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s4, 192(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t4, t4, s4
-; RV32IMZBS-NEXT: lw s4, 100(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s4, 96(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t5, t5, s4
; RV32IMZBS-NEXT: xor t2, t6, t2
-; RV32IMZBS-NEXT: lw t6, 288(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t6, 284(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t3, t3, t6
-; RV32IMZBS-NEXT: lw t6, 204(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t6, 200(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a7, a7, t6
-; RV32IMZBS-NEXT: lw t6, 108(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t6, 104(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, t0, t6
-; RV32IMZBS-NEXT: xor a6, t1, a6
-; RV32IMZBS-NEXT: lw t1, 588(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a4, a4, t1
-; RV32IMZBS-NEXT: lw t1, 492(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a4, t1, a4
+; RV32IMZBS-NEXT: lw t1, 584(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a5, a5, t1
-; RV32IMZBS-NEXT: xor a3, s11, a3
-; RV32IMZBS-NEXT: lw t1, 596(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a1, a1, t1
-; RV32IMZBS-NEXT: lw t1, 496(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a2, a2, t1
-; RV32IMZBS-NEXT: xor a0, ra, a0
-; RV32IMZBS-NEXT: lw t1, 604(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t1, 488(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a6, a6, t1
+; RV32IMZBS-NEXT: xor a0, a3, a0
+; RV32IMZBS-NEXT: lw a3, 592(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a1, a1, a3
+; RV32IMZBS-NEXT: lw a3, 492(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a2, a2, a3
+; RV32IMZBS-NEXT: xor a3, s10, ra
+; RV32IMZBS-NEXT: lw t1, 600(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t1, s9, t1
-; RV32IMZBS-NEXT: lw t6, 500(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t6, s10, t6
+; RV32IMZBS-NEXT: lw t6, 496(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor t6, s11, t6
; RV32IMZBS-NEXT: xor s4, s5, s6
-; RV32IMZBS-NEXT: lw s5, 212(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s5, 208(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s2, s2, s5
-; RV32IMZBS-NEXT: lw s5, 120(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s5, 116(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s3, s3, s5
; RV32IMZBS-NEXT: xor s0, s0, s1
-; RV32IMZBS-NEXT: lw s1, 216(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s1, 212(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t4, t4, s1
-; RV32IMZBS-NEXT: lw s1, 124(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s1, 120(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t5, t5, s1
; RV32IMZBS-NEXT: xor t2, t2, t3
-; RV32IMZBS-NEXT: lw t3, 220(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t3, 216(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a7, a7, t3
-; RV32IMZBS-NEXT: lw t3, 132(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t3, 128(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, t0, t3
-; RV32IMZBS-NEXT: lw s1, 692(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s1, 676(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: srli t3, s1, 2
-; RV32IMZBS-NEXT: lw s6, 728(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s6, 712(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: and s1, s1, s6
; RV32IMZBS-NEXT: and t3, t3, s6
; RV32IMZBS-NEXT: slli s1, s1, 2
; RV32IMZBS-NEXT: or t3, t3, s1
-; RV32IMZBS-NEXT: lw s5, 696(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s5, 680(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: srli s1, s5, 2
; RV32IMZBS-NEXT: and s5, s5, s6
; RV32IMZBS-NEXT: and s1, s1, s6
; RV32IMZBS-NEXT: slli s5, s5, 2
; RV32IMZBS-NEXT: or s1, s1, s5
-; RV32IMZBS-NEXT: xor a4, a6, a4
-; RV32IMZBS-NEXT: lw a6, 532(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a5, a5, a6
-; RV32IMZBS-NEXT: xor a1, a3, a1
-; RV32IMZBS-NEXT: lw a3, 528(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a2, a2, a3
-; RV32IMZBS-NEXT: xor a0, a0, t1
-; RV32IMZBS-NEXT: lw a3, 536(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a4, a4, a5
+; RV32IMZBS-NEXT: lw a5, 528(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a5, a6, a5
+; RV32IMZBS-NEXT: xor a0, a0, a1
+; RV32IMZBS-NEXT: lw a1, 524(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a1, a2, a1
+; RV32IMZBS-NEXT: xor a2, a3, t1
+; RV32IMZBS-NEXT: lw a3, 532(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a3, t6, a3
-; RV32IMZBS-NEXT: lw t1, 688(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t1, 672(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: srli a6, t1, 2
; RV32IMZBS-NEXT: and t1, t1, s6
; RV32IMZBS-NEXT: and a6, a6, s6
; RV32IMZBS-NEXT: slli t1, t1, 2
; RV32IMZBS-NEXT: or a6, a6, t1
-; RV32IMZBS-NEXT: lw t6, 684(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t6, 668(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: srli t1, t6, 2
; RV32IMZBS-NEXT: and t6, t6, s6
; RV32IMZBS-NEXT: and t1, t1, s6
@@ -10977,20 +10985,20 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: slli t6, t6, 2
; RV32IMZBS-NEXT: or t1, t1, t6
; RV32IMZBS-NEXT: xor t6, s4, s2
-; RV32IMZBS-NEXT: lw s2, 152(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s2, 148(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s2, s3, s2
; RV32IMZBS-NEXT: xor t4, s0, t4
-; RV32IMZBS-NEXT: lw s0, 148(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s0, 144(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t5, t5, s0
; RV32IMZBS-NEXT: xor a7, t2, a7
-; RV32IMZBS-NEXT: lw t2, 156(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t2, 152(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, t0, t2
; RV32IMZBS-NEXT: xor a4, a4, a5
-; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: srli a2, t3, 1
-; RV32IMZBS-NEXT: lw s11, 724(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a0, a0, a1
+; RV32IMZBS-NEXT: srli a1, t3, 1
+; RV32IMZBS-NEXT: lw s11, 708(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: and a5, t3, s11
-; RV32IMZBS-NEXT: xor a0, a0, a3
+; RV32IMZBS-NEXT: xor a2, a2, a3
; RV32IMZBS-NEXT: srli a3, s1, 1
; RV32IMZBS-NEXT: and t2, s1, s11
; RV32IMZBS-NEXT: xor t3, t6, s2
@@ -11000,297 +11008,297 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: srli t5, t1, 1
; RV32IMZBS-NEXT: and t1, t1, s11
; RV32IMZBS-NEXT: xor a7, a7, t0
-; RV32IMZBS-NEXT: and a2, a2, s11
+; RV32IMZBS-NEXT: and t0, a1, s11
; RV32IMZBS-NEXT: slli a5, a5, 1
; RV32IMZBS-NEXT: and a3, a3, s11
; RV32IMZBS-NEXT: slli t2, t2, 1
-; RV32IMZBS-NEXT: lw t0, 704(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a4, a4, t0
-; RV32IMZBS-NEXT: lw t0, 712(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t0, a1, t0
-; RV32IMZBS-NEXT: lw s0, 720(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s0, a0, s0
-; RV32IMZBS-NEXT: and t6, t6, s11
+; RV32IMZBS-NEXT: slli s0, a1, 31
+; RV32IMZBS-NEXT: lw a1, 696(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a4, a4, a1
+; RV32IMZBS-NEXT: lw s1, 700(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s1, a0, s1
+; RV32IMZBS-NEXT: lw a0, 704(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a2, a2, a0
+; RV32IMZBS-NEXT: and s2, t6, s11
; RV32IMZBS-NEXT: slli a6, a6, 1
; RV32IMZBS-NEXT: and t5, t5, s11
; RV32IMZBS-NEXT: slli t1, t1, 1
-; RV32IMZBS-NEXT: lw a0, 708(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s1, t3, a0
-; RV32IMZBS-NEXT: lw a0, 716(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: slli s4, t6, 31
+; RV32IMZBS-NEXT: lw a0, 688(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s3, t3, a0
+; RV32IMZBS-NEXT: lw a0, 692(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t3, t4, a0
-; RV32IMZBS-NEXT: lw a0, 700(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 684(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a7, a7, a0
-; RV32IMZBS-NEXT: or a0, a2, a5
+; RV32IMZBS-NEXT: or a0, t0, a5
; RV32IMZBS-NEXT: or a1, a3, t2
-; RV32IMZBS-NEXT: srli a2, t2, 31
-; RV32IMZBS-NEXT: xor a3, t0, a4
-; RV32IMZBS-NEXT: sw a3, 720(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: srli a3, s0, 8
-; RV32IMZBS-NEXT: srli a4, s0, 24
-; RV32IMZBS-NEXT: slli a5, s0, 24
-; RV32IMZBS-NEXT: lw s4, 740(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: and t2, s0, s4
-; RV32IMZBS-NEXT: or t4, t6, a6
+; RV32IMZBS-NEXT: srli a3, t2, 31
+; RV32IMZBS-NEXT: xor a4, s1, a4
+; RV32IMZBS-NEXT: sw a4, 704(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: srli a4, a2, 8
+; RV32IMZBS-NEXT: srli a5, a2, 24
+; RV32IMZBS-NEXT: slli t2, a2, 24
+; RV32IMZBS-NEXT: lw s6, 724(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: and a2, a2, s6
+; RV32IMZBS-NEXT: or t4, s2, a6
; RV32IMZBS-NEXT: or t6, t5, t1
; RV32IMZBS-NEXT: srli a6, t1, 31
-; RV32IMZBS-NEXT: xor t0, t3, s1
-; RV32IMZBS-NEXT: sw t0, 716(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: xor t0, t3, s3
+; RV32IMZBS-NEXT: sw t0, 700(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: srli t1, a7, 8
-; RV32IMZBS-NEXT: srli t3, a7, 24
+; RV32IMZBS-NEXT: srli t0, a7, 24
; RV32IMZBS-NEXT: slli t5, a7, 24
-; RV32IMZBS-NEXT: and a7, a7, s4
-; RV32IMZBS-NEXT: slli t0, a0, 1
-; RV32IMZBS-NEXT: andi s0, a1, 2
-; RV32IMZBS-NEXT: slli s1, a0, 2
-; RV32IMZBS-NEXT: andi s2, a1, 4
-; RV32IMZBS-NEXT: slli s3, a0, 3
-; RV32IMZBS-NEXT: and a3, a3, s4
-; RV32IMZBS-NEXT: or a3, a3, a4
-; RV32IMZBS-NEXT: andi a4, a1, 8
-; RV32IMZBS-NEXT: slli t2, t2, 8
-; RV32IMZBS-NEXT: or a5, a5, t2
-; RV32IMZBS-NEXT: slli t2, a0, 4
-; RV32IMZBS-NEXT: and t1, t1, s4
-; RV32IMZBS-NEXT: or t1, t1, t3
-; RV32IMZBS-NEXT: andi t3, a1, 16
+; RV32IMZBS-NEXT: and a7, a7, s6
+; RV32IMZBS-NEXT: slli s1, a0, 1
+; RV32IMZBS-NEXT: andi s2, a1, 2
+; RV32IMZBS-NEXT: slli s3, a0, 2
+; RV32IMZBS-NEXT: and a4, a4, s6
+; RV32IMZBS-NEXT: or a4, a4, a5
+; RV32IMZBS-NEXT: andi a5, a1, 4
+; RV32IMZBS-NEXT: slli a2, a2, 8
+; RV32IMZBS-NEXT: or a2, t2, a2
+; RV32IMZBS-NEXT: slli t2, a0, 3
+; RV32IMZBS-NEXT: and t1, t1, s6
+; RV32IMZBS-NEXT: or t1, t1, t0
+; RV32IMZBS-NEXT: andi t0, a1, 8
; RV32IMZBS-NEXT: slli a7, a7, 8
; RV32IMZBS-NEXT: or a7, t5, a7
-; RV32IMZBS-NEXT: slli t5, a0, 31
-; RV32IMZBS-NEXT: seqz a2, a2
-; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: and a2, a2, t5
-; RV32IMZBS-NEXT: sw a2, 704(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli t5, a0, 4
+; RV32IMZBS-NEXT: seqz a3, a3
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: and a3, a3, s0
+; RV32IMZBS-NEXT: sw a3, 688(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a3, a1, 16
+; RV32IMZBS-NEXT: or a2, a2, a4
+; RV32IMZBS-NEXT: sw a2, 684(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: slli a2, a0, 5
-; RV32IMZBS-NEXT: or a3, a5, a3
-; RV32IMZBS-NEXT: sw a3, 700(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a3, t4, 31
-; RV32IMZBS-NEXT: seqz a5, a6
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: and a3, a5, a3
-; RV32IMZBS-NEXT: sw a3, 712(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a3, a1, 32
-; RV32IMZBS-NEXT: or a5, a7, t1
-; RV32IMZBS-NEXT: sw a5, 708(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a5, a0, 6
-; RV32IMZBS-NEXT: seqz a6, s0
-; RV32IMZBS-NEXT: addi a6, a6, -1
-; RV32IMZBS-NEXT: and a6, a6, t0
+; RV32IMZBS-NEXT: seqz a4, a6
+; RV32IMZBS-NEXT: addi a4, a4, -1
+; RV32IMZBS-NEXT: and a4, a4, s4
+; RV32IMZBS-NEXT: sw a4, 696(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a4, a1, 32
+; RV32IMZBS-NEXT: or a6, a7, t1
; RV32IMZBS-NEXT: sw a6, 692(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a6, a1, 64
+; RV32IMZBS-NEXT: slli a6, a0, 6
; RV32IMZBS-NEXT: seqz a7, s2
; RV32IMZBS-NEXT: addi a7, a7, -1
; RV32IMZBS-NEXT: and a7, a7, s1
-; RV32IMZBS-NEXT: sw a7, 688(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a7, a0, 7
-; RV32IMZBS-NEXT: seqz a4, a4
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: and a4, a4, s3
-; RV32IMZBS-NEXT: sw a4, 676(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a4, a1, 128
-; RV32IMZBS-NEXT: seqz t1, t3
+; RV32IMZBS-NEXT: sw a7, 676(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a7, a1, 64
+; RV32IMZBS-NEXT: seqz a5, a5
+; RV32IMZBS-NEXT: addi a5, a5, -1
+; RV32IMZBS-NEXT: and a5, a5, s3
+; RV32IMZBS-NEXT: sw a5, 672(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a5, a0, 7
+; RV32IMZBS-NEXT: seqz t1, t0
; RV32IMZBS-NEXT: addi t1, t1, -1
; RV32IMZBS-NEXT: and t0, t1, t2
-; RV32IMZBS-NEXT: sw t0, 672(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli t1, a0, 8
+; RV32IMZBS-NEXT: sw t0, 660(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi t1, a1, 128
; RV32IMZBS-NEXT: seqz a3, a3
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: and a2, a3, a2
-; RV32IMZBS-NEXT: sw a2, 664(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a2, a1, 256
-; RV32IMZBS-NEXT: seqz a3, a6
-; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: and a3, a3, a5
-; RV32IMZBS-NEXT: sw a3, 684(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a3, a0, 9
+; RV32IMZBS-NEXT: and a3, a3, t5
+; RV32IMZBS-NEXT: sw a3, 656(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a3, a0, 8
; RV32IMZBS-NEXT: seqz a4, a4
; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: and a5, a4, a7
-; RV32IMZBS-NEXT: andi a4, a1, 512
+; RV32IMZBS-NEXT: and a2, a4, a2
+; RV32IMZBS-NEXT: sw a2, 648(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a2, a1, 256
+; RV32IMZBS-NEXT: seqz a4, a7
+; RV32IMZBS-NEXT: addi a4, a4, -1
+; RV32IMZBS-NEXT: and a4, a4, a6
+; RV32IMZBS-NEXT: sw a4, 668(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, a0, 9
+; RV32IMZBS-NEXT: seqz a6, t1
+; RV32IMZBS-NEXT: addi a6, a6, -1
+; RV32IMZBS-NEXT: and t1, a6, a5
+; RV32IMZBS-NEXT: andi a5, a1, 512
; RV32IMZBS-NEXT: seqz a2, a2
; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: and t1, a2, t1
+; RV32IMZBS-NEXT: and a2, a2, a3
+; RV32IMZBS-NEXT: sw a2, 632(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: slli a2, a0, 10
-; RV32IMZBS-NEXT: seqz a4, a4
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: and a3, a4, a3
-; RV32IMZBS-NEXT: sw a3, 660(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: seqz a3, a5
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 644(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a3, a1, 1024
; RV32IMZBS-NEXT: seqz a3, a3
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: and a2, a3, a2
-; RV32IMZBS-NEXT: sw a2, 696(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a2, 680(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: not a2, a1
; RV32IMZBS-NEXT: bexti a3, a2, 11
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 11
-; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 636(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a5, a3, a4
; RV32IMZBS-NEXT: bexti a3, a2, 12
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 12
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 632(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 616(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 13
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 13
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 644(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 624(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 14
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 14
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 668(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 652(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 15
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 15
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 680(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 664(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 16
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 16
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 612(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 596(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 17
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 17
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 608(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 592(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 18
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 18
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 620(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 604(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 19
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 19
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 648(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 628(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 20
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 20
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 652(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 636(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 21
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 21
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 656(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 640(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 22
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 22
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 600(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 584(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 23
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 23
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 596(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 580(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 24
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 24
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 604(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 588(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 25
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 25
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 616(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 600(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 26
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 26
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 624(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 608(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 27
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 27
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 628(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 612(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 28
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 28
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 640(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 620(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 29
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 29
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 592(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 576(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a1, a1, 1
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: and a1, a1, a0
-; RV32IMZBS-NEXT: sw a1, 584(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 568(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: slli a0, a0, 30
; RV32IMZBS-NEXT: bexti a1, a2, 30
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: and a0, a1, a0
-; RV32IMZBS-NEXT: sw a0, 588(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 572(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, t6, 2
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: slli a1, t4, 1
; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: sw a0, 580(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 564(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, t6, 4
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: slli a1, t4, 2
; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: sw a0, 576(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 560(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, t6, 8
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: slli a1, t4, 3
; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: sw a0, 564(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 548(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, t6, 16
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: slli a1, t4, 4
; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: sw a0, 560(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 544(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, t6, 32
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: slli a1, t4, 5
; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: sw a0, 556(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 540(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, t6, 64
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: slli a1, t4, 6
; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: sw a0, 572(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 556(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, t6, 128
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: slli a1, t4, 7
; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: sw a0, 540(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 524(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, t6, 256
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: slli s1, t4, 8
; RV32IMZBS-NEXT: and a0, a0, s1
-; RV32IMZBS-NEXT: sw a0, 532(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 516(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, t6, 512
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: slli a1, t4, 9
; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: sw a0, 552(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 536(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, t6, 1024
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: slli a1, t4, 10
; RV32IMZBS-NEXT: and a0, a0, a1
-; RV32IMZBS-NEXT: sw a0, 568(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 552(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: not a0, t6
; RV32IMZBS-NEXT: bexti a1, a0, 11
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: slli a2, t4, 11
; RV32IMZBS-NEXT: and a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 516(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 500(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 12
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: slli a2, t4, 12
@@ -11299,17 +11307,17 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: slli s0, t4, 13
; RV32IMZBS-NEXT: and a1, a1, s0
-; RV32IMZBS-NEXT: sw a1, 528(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 512(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 14
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: slli a2, t4, 14
; RV32IMZBS-NEXT: and a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 544(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 528(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 15
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: slli a2, t4, 15
; RV32IMZBS-NEXT: and a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 548(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 532(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 16
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: slli a3, t4, 16
@@ -11326,17 +11334,17 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: slli a4, t4, 19
; RV32IMZBS-NEXT: and a1, a1, a4
-; RV32IMZBS-NEXT: sw a1, 520(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 504(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 20
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: slli a4, t4, 20
; RV32IMZBS-NEXT: and a1, a1, a4
-; RV32IMZBS-NEXT: sw a1, 524(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 508(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 21
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: slli a4, t4, 21
; RV32IMZBS-NEXT: and a1, a1, a4
-; RV32IMZBS-NEXT: sw a1, 536(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 520(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 22
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: slli a4, t4, 22
@@ -11377,115 +11385,115 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: bexti a0, a0, 30
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: and a6, a0, t4
-; RV32IMZBS-NEXT: lw a0, 692(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 584(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 676(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 568(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t4, a1, a0
-; RV32IMZBS-NEXT: lw a0, 688(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 676(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t6, a0, a1
; RV32IMZBS-NEXT: lw a0, 672(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 664(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 660(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor t6, a0, a1
+; RV32IMZBS-NEXT: lw a0, 656(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 648(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a0, a1
-; RV32IMZBS-NEXT: xor a1, a5, t1
-; RV32IMZBS-NEXT: lw a2, 636(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a3, 632(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a2, a2, a3
-; RV32IMZBS-NEXT: lw a3, 612(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a4, 608(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 632(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a1, t1, a1
+; RV32IMZBS-NEXT: lw a2, 616(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a2, a5, a2
+; RV32IMZBS-NEXT: lw a3, 596(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a4, 592(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a3, a3, a4
-; RV32IMZBS-NEXT: lw a4, 600(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a5, 596(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a4, 584(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a5, 580(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a4, a4, a5
-; RV32IMZBS-NEXT: lw a5, 592(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a7, 588(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a5, 576(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a7, 572(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a5, a5, a7
-; RV32IMZBS-NEXT: lw a7, 580(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a7, 564(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t3, t3, a7
-; RV32IMZBS-NEXT: lw a7, 576(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw t0, 564(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a7, 560(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t0, 548(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a7, a7, t0
-; RV32IMZBS-NEXT: lw t0, 560(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw t1, 556(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t0, t0, t1
+; RV32IMZBS-NEXT: lw t0, 544(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw t1, 540(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw ra, 532(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t1, t1, ra
+; RV32IMZBS-NEXT: xor t0, t0, t1
+; RV32IMZBS-NEXT: lw t1, 524(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw ra, 516(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor t1, t1, ra
+; RV32IMZBS-NEXT: lw ra, 500(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s9, ra, s9
; RV32IMZBS-NEXT: xor s3, s4, s3
; RV32IMZBS-NEXT: xor s0, s1, s0
; RV32IMZBS-NEXT: xor t2, t2, a6
; RV32IMZBS-NEXT: xor t4, t4, t6
-; RV32IMZBS-NEXT: lw a6, 684(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a6, 668(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a0, a6
-; RV32IMZBS-NEXT: lw a6, 660(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a1, a1, a6
; RV32IMZBS-NEXT: lw a6, 644(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a1, a1, a6
+; RV32IMZBS-NEXT: lw a6, 624(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t6, a2, a6
-; RV32IMZBS-NEXT: lw a2, 620(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a3, a3, a2
; RV32IMZBS-NEXT: lw a2, 604(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a3, a3, a2
+; RV32IMZBS-NEXT: lw a2, 588(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a4, a4, a2
-; RV32IMZBS-NEXT: lw a2, 704(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 688(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a6, a5, a2
-; RV32IMZBS-NEXT: lw a5, 700(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a5, 684(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: srli a2, a5, 4
-; RV32IMZBS-NEXT: lw s4, 744(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s4, 728(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: and a5, a5, s4
; RV32IMZBS-NEXT: and a2, a2, s4
; RV32IMZBS-NEXT: slli a5, a5, 4
; RV32IMZBS-NEXT: or a5, a2, a5
; RV32IMZBS-NEXT: xor a7, t3, a7
-; RV32IMZBS-NEXT: lw a2, 572(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 556(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, t0, a2
-; RV32IMZBS-NEXT: lw a2, 552(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 536(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t1, t1, a2
-; RV32IMZBS-NEXT: lw a2, 528(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 512(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t3, s9, a2
; RV32IMZBS-NEXT: xor s1, s3, s8
; RV32IMZBS-NEXT: xor s0, s0, s2
-; RV32IMZBS-NEXT: lw a2, 712(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 696(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a2, t2, a2
-; RV32IMZBS-NEXT: lw s2, 708(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s2, 692(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: srli t2, s2, 4
; RV32IMZBS-NEXT: and s2, s2, s4
; RV32IMZBS-NEXT: and t2, t2, s4
; RV32IMZBS-NEXT: slli s2, s2, 4
; RV32IMZBS-NEXT: or t2, t2, s2
; RV32IMZBS-NEXT: xor a0, t4, a0
-; RV32IMZBS-NEXT: lw t4, 696(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t4, 680(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, t4
-; RV32IMZBS-NEXT: lw t4, 668(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t4, 652(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t4, t6, t4
-; RV32IMZBS-NEXT: lw t6, 648(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t6, 628(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a3, a3, t6
-; RV32IMZBS-NEXT: lw t6, 616(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t6, 600(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a4, a4, t6
; RV32IMZBS-NEXT: xor a7, a7, t0
-; RV32IMZBS-NEXT: lw t0, 568(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t0, 552(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, t1, t0
-; RV32IMZBS-NEXT: lw t1, 544(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t1, 528(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t1, t3, t1
-; RV32IMZBS-NEXT: lw t3, 520(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t3, 504(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t3, s1, t3
; RV32IMZBS-NEXT: xor t6, s0, s6
; RV32IMZBS-NEXT: xor a0, a0, a1
-; RV32IMZBS-NEXT: lw a1, 680(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 664(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, t4, a1
-; RV32IMZBS-NEXT: lw t4, 652(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t4, 636(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a3, a3, t4
-; RV32IMZBS-NEXT: lw t4, 624(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t4, 608(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a4, a4, t4
; RV32IMZBS-NEXT: xor a7, a7, t0
-; RV32IMZBS-NEXT: lw t0, 548(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t0, 532(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, t1, t0
-; RV32IMZBS-NEXT: lw t1, 524(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t1, 508(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t1, t3, t1
; RV32IMZBS-NEXT: xor t3, t6, s7
; RV32IMZBS-NEXT: xor a0, a0, a1
-; RV32IMZBS-NEXT: lw a1, 656(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 640(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a3, a1
-; RV32IMZBS-NEXT: lw a3, 628(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a3, 612(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a3, a4, a3
; RV32IMZBS-NEXT: srli a4, a5, 2
; RV32IMZBS-NEXT: and a5, a5, s5
@@ -11493,7 +11501,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: slli a5, a5, 2
; RV32IMZBS-NEXT: or a4, a4, a5
; RV32IMZBS-NEXT: xor a5, a7, t0
-; RV32IMZBS-NEXT: lw a7, 536(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a7, 520(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a7, t1, a7
; RV32IMZBS-NEXT: xor t0, t3, s10
; RV32IMZBS-NEXT: srli t1, t2, 2
@@ -11502,7 +11510,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: slli t2, t2, 2
; RV32IMZBS-NEXT: or t1, t1, t2
; RV32IMZBS-NEXT: xor a0, a0, a1
-; RV32IMZBS-NEXT: lw a1, 640(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 620(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a3, a3, a1
; RV32IMZBS-NEXT: xor a5, a5, a7
; RV32IMZBS-NEXT: xor a7, t0, t5
@@ -11523,7 +11531,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: srli a4, a6, 8
; RV32IMZBS-NEXT: srli a7, a6, 24
; RV32IMZBS-NEXT: slli t0, a6, 24
-; RV32IMZBS-NEXT: lw t2, 740(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t2, 724(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: and a6, a6, t2
; RV32IMZBS-NEXT: and a4, a4, t2
; RV32IMZBS-NEXT: or a4, a4, a7
@@ -11573,9 +11581,9 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: or a5, a7, a5
; RV32IMZBS-NEXT: srli a6, a6, 1
; RV32IMZBS-NEXT: srli a5, a5, 1
-; RV32IMZBS-NEXT: lw a7, 720(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a7, 704(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a6, a6, a7
-; RV32IMZBS-NEXT: lw a7, 716(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a7, 700(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a5, a5, a7
; RV32IMZBS-NEXT: srli a7, a6, 8
; RV32IMZBS-NEXT: srli t0, a6, 24
@@ -11633,162 +11641,163 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: or a0, a4, a0
; RV32IMZBS-NEXT: srli a2, a2, 1
; RV32IMZBS-NEXT: srli a3, a3, 1
-; RV32IMZBS-NEXT: lw a4, 732(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a4, 716(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: sw a1, 0(a4)
; RV32IMZBS-NEXT: sw a2, 4(a4)
; RV32IMZBS-NEXT: sw a0, 8(a4)
; RV32IMZBS-NEXT: sw a3, 12(a4)
-; RV32IMZBS-NEXT: lw a4, 736(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a4, 720(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: sw a1, 0(a4)
; RV32IMZBS-NEXT: sw a2, 4(a4)
; RV32IMZBS-NEXT: sw a0, 8(a4)
; RV32IMZBS-NEXT: sw a3, 12(a4)
-; RV32IMZBS-NEXT: lw ra, 796(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s0, 792(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s1, 788(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s2, 784(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s3, 780(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s4, 776(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s5, 772(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s6, 768(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s7, 764(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 760(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 756(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s10, 752(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s11, 748(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: addi sp, sp, 800
+; RV32IMZBS-NEXT: lw ra, 780(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s0, 776(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s1, 772(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s2, 768(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s3, 764(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s4, 760(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s5, 756(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s6, 752(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s7, 748(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 744(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s9, 740(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s10, 736(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s11, 732(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: addi sp, sp, 784
; RV32IMZBS-NEXT: ret
;
; RV64IMZBS-LABEL: commutative_clmulh_v2i64:
; RV64IMZBS: # %bb.0:
-; RV64IMZBS-NEXT: addi sp, sp, -1088
-; RV64IMZBS-NEXT: sd ra, 1080(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s0, 1072(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s1, 1064(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s2, 1056(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s3, 1048(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s4, 1040(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s5, 1032(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s6, 1024(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s7, 1016(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s8, 1008(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s9, 1000(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s10, 992(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s11, 984(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd a5, 976(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd a4, 968(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: mv t5, a0
-; RV64IMZBS-NEXT: srli a5, a2, 24
-; RV64IMZBS-NEXT: lui s8, 4080
-; RV64IMZBS-NEXT: srli a7, a2, 8
+; RV64IMZBS-NEXT: addi sp, sp, -1072
+; RV64IMZBS-NEXT: sd ra, 1064(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s0, 1056(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s1, 1048(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s2, 1040(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s3, 1032(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s4, 1024(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s5, 1016(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s6, 1008(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s7, 1000(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s8, 992(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s9, 984(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s10, 976(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s11, 968(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd a5, 960(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd a4, 952(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: mv a4, a1
+; RV64IMZBS-NEXT: mv a5, a0
+; RV64IMZBS-NEXT: srli a7, a2, 24
+; RV64IMZBS-NEXT: lui s2, 4080
+; RV64IMZBS-NEXT: srli t1, a2, 8
; RV64IMZBS-NEXT: li t3, 255
-; RV64IMZBS-NEXT: srli a4, a2, 40
-; RV64IMZBS-NEXT: lui a6, 16
-; RV64IMZBS-NEXT: srli t0, a2, 56
-; RV64IMZBS-NEXT: srliw t1, a2, 24
+; RV64IMZBS-NEXT: srli a6, a2, 40
+; RV64IMZBS-NEXT: lui t0, 16
+; RV64IMZBS-NEXT: srli s5, a2, 56
+; RV64IMZBS-NEXT: srliw t4, a2, 24
; RV64IMZBS-NEXT: slli a0, a2, 56
-; RV64IMZBS-NEXT: sd a0, 920(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: lui t6, 61681
-; RV64IMZBS-NEXT: lui s2, 209715
-; RV64IMZBS-NEXT: lui t4, 349525
-; RV64IMZBS-NEXT: srli t2, t5, 24
-; RV64IMZBS-NEXT: srli s0, t5, 8
-; RV64IMZBS-NEXT: srli s1, t5, 40
-; RV64IMZBS-NEXT: srli s3, t5, 56
-; RV64IMZBS-NEXT: srliw s4, t5, 24
-; RV64IMZBS-NEXT: slli a0, t5, 56
-; RV64IMZBS-NEXT: sd a0, 912(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd a0, 904(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: lui s8, 61681
+; RV64IMZBS-NEXT: lui s9, 209715
+; RV64IMZBS-NEXT: lui s4, 349525
+; RV64IMZBS-NEXT: srli s3, a5, 24
+; RV64IMZBS-NEXT: srli t6, a5, 8
+; RV64IMZBS-NEXT: srli t2, a5, 40
+; RV64IMZBS-NEXT: srli s0, a5, 56
+; RV64IMZBS-NEXT: srliw s1, a5, 24
+; RV64IMZBS-NEXT: slli a0, a5, 56
+; RV64IMZBS-NEXT: sd a0, 896(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: srli s7, a3, 24
; RV64IMZBS-NEXT: srli ra, a3, 8
; RV64IMZBS-NEXT: srli s6, a3, 40
; RV64IMZBS-NEXT: srli s11, a3, 56
-; RV64IMZBS-NEXT: and a5, a5, s8
-; RV64IMZBS-NEXT: slli t3, t3, 24
-; RV64IMZBS-NEXT: and a7, a7, t3
-; RV64IMZBS-NEXT: or a5, a7, a5
-; RV64IMZBS-NEXT: srliw a0, a3, 24
-; RV64IMZBS-NEXT: addi s5, a6, -256
-; RV64IMZBS-NEXT: and a4, a4, s5
-; RV64IMZBS-NEXT: or a6, a4, t0
-; RV64IMZBS-NEXT: and a4, a2, s8
-; RV64IMZBS-NEXT: slli t1, t1, 32
-; RV64IMZBS-NEXT: addi s10, t6, -241
-; RV64IMZBS-NEXT: addi a7, s2, 819
-; RV64IMZBS-NEXT: addi t0, t4, 1365
-; RV64IMZBS-NEXT: slli a4, a4, 24
-; RV64IMZBS-NEXT: or a4, a4, t1
-; RV64IMZBS-NEXT: slli t1, s10, 32
-; RV64IMZBS-NEXT: add s10, s10, t1
-; RV64IMZBS-NEXT: slli t1, a7, 32
-; RV64IMZBS-NEXT: add t4, a7, t1
-; RV64IMZBS-NEXT: slli a7, t0, 32
-; RV64IMZBS-NEXT: add s9, t0, a7
-; RV64IMZBS-NEXT: slli a7, a3, 56
-; RV64IMZBS-NEXT: and t0, t2, s8
-; RV64IMZBS-NEXT: and t1, s0, t3
-; RV64IMZBS-NEXT: or t0, t1, t0
-; RV64IMZBS-NEXT: srli t1, a1, 24
-; RV64IMZBS-NEXT: and t2, s1, s5
-; RV64IMZBS-NEXT: or t2, t2, s3
-; RV64IMZBS-NEXT: and t6, t5, s8
-; RV64IMZBS-NEXT: slli s4, s4, 32
+; RV64IMZBS-NEXT: and a7, a7, s2
+; RV64IMZBS-NEXT: slli a1, t3, 24
+; RV64IMZBS-NEXT: and t1, t1, a1
+; RV64IMZBS-NEXT: or a7, t1, a7
+; RV64IMZBS-NEXT: srliw t5, a3, 24
+; RV64IMZBS-NEXT: addi a0, t0, -256
+; RV64IMZBS-NEXT: and a6, a6, a0
+; RV64IMZBS-NEXT: or t0, a6, s5
+; RV64IMZBS-NEXT: and a6, a2, s2
+; RV64IMZBS-NEXT: slli t4, t4, 32
+; RV64IMZBS-NEXT: addi s10, s8, -241
+; RV64IMZBS-NEXT: addi t1, s9, 819
+; RV64IMZBS-NEXT: addi t3, s4, 1365
+; RV64IMZBS-NEXT: slli a6, a6, 24
+; RV64IMZBS-NEXT: or a6, a6, t4
+; RV64IMZBS-NEXT: slli t4, s10, 32
+; RV64IMZBS-NEXT: add s10, s10, t4
+; RV64IMZBS-NEXT: slli t4, t1, 32
+; RV64IMZBS-NEXT: add s8, t1, t4
+; RV64IMZBS-NEXT: slli t1, t3, 32
+; RV64IMZBS-NEXT: add s9, t3, t1
+; RV64IMZBS-NEXT: slli t1, a3, 56
+; RV64IMZBS-NEXT: and t3, s3, s2
+; RV64IMZBS-NEXT: and t4, t6, a1
+; RV64IMZBS-NEXT: or t3, t4, t3
+; RV64IMZBS-NEXT: srli t4, a4, 24
+; RV64IMZBS-NEXT: and t2, t2, a0
+; RV64IMZBS-NEXT: or t2, t2, s0
+; RV64IMZBS-NEXT: lui s5, 4080
+; RV64IMZBS-NEXT: and t6, a5, s5
+; RV64IMZBS-NEXT: slli s1, s1, 32
; RV64IMZBS-NEXT: slli t6, t6, 24
-; RV64IMZBS-NEXT: or t6, t6, s4
-; RV64IMZBS-NEXT: srli s0, a1, 8
-; RV64IMZBS-NEXT: and s1, s7, s8
-; RV64IMZBS-NEXT: mv s7, t3
-; RV64IMZBS-NEXT: sd t3, 960(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: and s2, ra, t3
+; RV64IMZBS-NEXT: or t6, t6, s1
+; RV64IMZBS-NEXT: srli s0, a4, 8
+; RV64IMZBS-NEXT: and s1, s7, s5
+; RV64IMZBS-NEXT: sd a1, 944(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: and s2, ra, a1
; RV64IMZBS-NEXT: or s1, s2, s1
-; RV64IMZBS-NEXT: srli s2, a1, 40
-; RV64IMZBS-NEXT: and s3, s6, s5
+; RV64IMZBS-NEXT: srli s2, a4, 40
+; RV64IMZBS-NEXT: and s3, s6, a0
; RV64IMZBS-NEXT: or s3, s3, s11
-; RV64IMZBS-NEXT: and s4, a3, s8
-; RV64IMZBS-NEXT: slli t3, a0, 32
+; RV64IMZBS-NEXT: and s4, a3, s5
+; RV64IMZBS-NEXT: slli t5, t5, 32
; RV64IMZBS-NEXT: slli s4, s4, 24
-; RV64IMZBS-NEXT: or t3, s4, t3
-; RV64IMZBS-NEXT: srli s4, a1, 56
-; RV64IMZBS-NEXT: and t1, t1, s8
-; RV64IMZBS-NEXT: lui a0, 4080
-; RV64IMZBS-NEXT: and s0, s0, s7
-; RV64IMZBS-NEXT: or t1, s0, t1
-; RV64IMZBS-NEXT: srliw s0, a1, 24
-; RV64IMZBS-NEXT: and s2, s2, s5
+; RV64IMZBS-NEXT: or t5, s4, t5
+; RV64IMZBS-NEXT: srli s4, a4, 56
+; RV64IMZBS-NEXT: and t4, t4, s5
+; RV64IMZBS-NEXT: and s0, s0, a1
+; RV64IMZBS-NEXT: or t4, s0, t4
+; RV64IMZBS-NEXT: srliw s0, a4, 24
+; RV64IMZBS-NEXT: and s2, s2, a0
; RV64IMZBS-NEXT: or s2, s2, s4
-; RV64IMZBS-NEXT: and s4, a1, a0
+; RV64IMZBS-NEXT: and s4, a4, s5
; RV64IMZBS-NEXT: slli s0, s0, 32
; RV64IMZBS-NEXT: slli s4, s4, 24
; RV64IMZBS-NEXT: or s0, s4, s0
-; RV64IMZBS-NEXT: slli s4, a1, 56
-; RV64IMZBS-NEXT: sd s5, 944(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: and a2, a2, s5
-; RV64IMZBS-NEXT: and a0, t5, s5
-; RV64IMZBS-NEXT: and a3, a3, s5
-; RV64IMZBS-NEXT: and a1, a1, s5
+; RV64IMZBS-NEXT: slli s4, a4, 56
+; RV64IMZBS-NEXT: mv a1, a0
+; RV64IMZBS-NEXT: sd a0, 920(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: and a2, a2, a0
+; RV64IMZBS-NEXT: and a0, a5, a0
+; RV64IMZBS-NEXT: and a3, a3, a1
+; RV64IMZBS-NEXT: and a1, a4, a1
; RV64IMZBS-NEXT: slli a2, a2, 40
; RV64IMZBS-NEXT: slli a0, a0, 40
; RV64IMZBS-NEXT: slli a3, a3, 40
; RV64IMZBS-NEXT: slli a1, a1, 40
-; RV64IMZBS-NEXT: or a5, a5, a6
-; RV64IMZBS-NEXT: ld a6, 920(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: or a2, a6, a2
-; RV64IMZBS-NEXT: or a6, t0, t2
-; RV64IMZBS-NEXT: ld t0, 912(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: or a0, t0, a0
-; RV64IMZBS-NEXT: or t0, s1, s3
-; RV64IMZBS-NEXT: or a3, a7, a3
-; RV64IMZBS-NEXT: or a7, t1, s2
+; RV64IMZBS-NEXT: or a7, a7, t0
+; RV64IMZBS-NEXT: ld a4, 904(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: or a2, a4, a2
+; RV64IMZBS-NEXT: or a4, t3, t2
+; RV64IMZBS-NEXT: ld a5, 896(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: or a0, a5, a0
+; RV64IMZBS-NEXT: or a5, s1, s3
+; RV64IMZBS-NEXT: or a3, t1, a3
+; RV64IMZBS-NEXT: or t0, t4, s2
; RV64IMZBS-NEXT: or a1, s4, a1
-; RV64IMZBS-NEXT: or a2, a2, a4
+; RV64IMZBS-NEXT: or a2, a2, a6
; RV64IMZBS-NEXT: or a0, a0, t6
-; RV64IMZBS-NEXT: or a3, a3, t3
+; RV64IMZBS-NEXT: or a3, a3, t5
; RV64IMZBS-NEXT: or a1, a1, s0
-; RV64IMZBS-NEXT: or a2, a2, a5
-; RV64IMZBS-NEXT: or a0, a0, a6
-; RV64IMZBS-NEXT: or a3, a3, t0
-; RV64IMZBS-NEXT: or a1, a1, a7
+; RV64IMZBS-NEXT: or a2, a2, a7
+; RV64IMZBS-NEXT: or a0, a0, a4
+; RV64IMZBS-NEXT: or a3, a3, a5
+; RV64IMZBS-NEXT: or a1, a1, t0
; RV64IMZBS-NEXT: srli a4, a2, 4
-; RV64IMZBS-NEXT: sd s10, 952(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s10, 936(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: and a2, a2, s10
; RV64IMZBS-NEXT: srli a5, a0, 4
; RV64IMZBS-NEXT: and a0, a0, s10
@@ -11809,711 +11818,707 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: or a3, a6, a3
; RV64IMZBS-NEXT: or a1, a7, a1
; RV64IMZBS-NEXT: srli a4, a2, 2
-; RV64IMZBS-NEXT: sd t4, 936(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: and a2, a2, t4
+; RV64IMZBS-NEXT: sd s8, 928(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: and a2, a2, s8
; RV64IMZBS-NEXT: srli a5, a0, 2
-; RV64IMZBS-NEXT: and a0, a0, t4
+; RV64IMZBS-NEXT: and a0, a0, s8
; RV64IMZBS-NEXT: srli a6, a3, 2
-; RV64IMZBS-NEXT: and a3, a3, t4
+; RV64IMZBS-NEXT: and a3, a3, s8
; RV64IMZBS-NEXT: srli a7, a1, 2
-; RV64IMZBS-NEXT: and a1, a1, t4
-; RV64IMZBS-NEXT: and a4, a4, t4
+; RV64IMZBS-NEXT: and a1, a1, s8
+; RV64IMZBS-NEXT: and a4, a4, s8
; RV64IMZBS-NEXT: slli a2, a2, 2
-; RV64IMZBS-NEXT: and a5, a5, t4
+; RV64IMZBS-NEXT: and a5, a5, s8
; RV64IMZBS-NEXT: slli a0, a0, 2
-; RV64IMZBS-NEXT: and a6, a6, t4
+; RV64IMZBS-NEXT: and a6, a6, s8
; RV64IMZBS-NEXT: slli a3, a3, 2
-; RV64IMZBS-NEXT: and a7, a7, t4
+; RV64IMZBS-NEXT: and a7, a7, s8
; RV64IMZBS-NEXT: slli a1, a1, 2
; RV64IMZBS-NEXT: or a2, a4, a2
; RV64IMZBS-NEXT: or a0, a5, a0
; RV64IMZBS-NEXT: or a3, a6, a3
-; RV64IMZBS-NEXT: or a1, a7, a1
-; RV64IMZBS-NEXT: srli a4, a2, 1
-; RV64IMZBS-NEXT: sd s9, 928(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: and a2, a2, s9
-; RV64IMZBS-NEXT: srli a5, a0, 1
+; RV64IMZBS-NEXT: or a4, a7, a1
+; RV64IMZBS-NEXT: srli a6, a2, 1
+; RV64IMZBS-NEXT: sd s9, 912(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: and a5, a2, s9
+; RV64IMZBS-NEXT: srli a7, a0, 1
; RV64IMZBS-NEXT: and a0, a0, s9
-; RV64IMZBS-NEXT: srli a6, a3, 1
-; RV64IMZBS-NEXT: and a3, a3, s9
-; RV64IMZBS-NEXT: srli a7, a1, 1
-; RV64IMZBS-NEXT: and a1, a1, s9
-; RV64IMZBS-NEXT: and a4, a4, s9
-; RV64IMZBS-NEXT: slli a2, a2, 1
-; RV64IMZBS-NEXT: and a5, a5, s9
-; RV64IMZBS-NEXT: slli t0, a0, 1
-; RV64IMZBS-NEXT: and a6, a6, s9
-; RV64IMZBS-NEXT: slli a3, a3, 1
-; RV64IMZBS-NEXT: and a7, a7, s9
-; RV64IMZBS-NEXT: slli a0, a1, 1
-; RV64IMZBS-NEXT: or t4, a4, a2
-; RV64IMZBS-NEXT: or t5, a5, t0
-; RV64IMZBS-NEXT: srli a2, t0, 63
-; RV64IMZBS-NEXT: or t0, a6, a3
-; RV64IMZBS-NEXT: or s5, a7, a0
-; RV64IMZBS-NEXT: srli a0, a0, 63
-; RV64IMZBS-NEXT: slli a3, t4, 1
-; RV64IMZBS-NEXT: andi a4, t5, 2
-; RV64IMZBS-NEXT: slli a5, t4, 2
-; RV64IMZBS-NEXT: andi a6, t5, 4
-; RV64IMZBS-NEXT: slli a7, t4, 3
-; RV64IMZBS-NEXT: andi t1, t5, 8
-; RV64IMZBS-NEXT: slli t2, t4, 4
-; RV64IMZBS-NEXT: andi t3, t5, 16
-; RV64IMZBS-NEXT: slli t6, t4, 5
-; RV64IMZBS-NEXT: andi s0, t5, 32
-; RV64IMZBS-NEXT: slli s1, t4, 6
-; RV64IMZBS-NEXT: andi s2, t5, 64
-; RV64IMZBS-NEXT: slli s3, t4, 7
-; RV64IMZBS-NEXT: slli s4, t4, 63
-; RV64IMZBS-NEXT: seqz a2, a2
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: and a1, a2, s4
-; RV64IMZBS-NEXT: sd a1, 912(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: slli a2, t0, 63
-; RV64IMZBS-NEXT: seqz a0, a0
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: and a0, a0, a2
-; RV64IMZBS-NEXT: sd a0, 920(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: andi a0, t5, 128
-; RV64IMZBS-NEXT: seqz a2, a4
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 880(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: slli a2, t4, 8
-; RV64IMZBS-NEXT: seqz a3, a6
-; RV64IMZBS-NEXT: addi a3, a3, -1
-; RV64IMZBS-NEXT: and a3, a3, a5
-; RV64IMZBS-NEXT: sd a3, 864(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: andi a3, t5, 256
-; RV64IMZBS-NEXT: seqz a4, t1
-; RV64IMZBS-NEXT: addi a4, a4, -1
-; RV64IMZBS-NEXT: and a1, a4, a7
-; RV64IMZBS-NEXT: sd a1, 848(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: slli a4, t4, 9
-; RV64IMZBS-NEXT: seqz a5, t3
+; RV64IMZBS-NEXT: srli a1, a3, 1
+; RV64IMZBS-NEXT: and t0, a3, s9
+; RV64IMZBS-NEXT: srli t1, a4, 1
+; RV64IMZBS-NEXT: and t2, a4, s9
+; RV64IMZBS-NEXT: and a2, a6, s9
+; RV64IMZBS-NEXT: slli a3, a5, 1
+; RV64IMZBS-NEXT: and a4, a7, s9
+; RV64IMZBS-NEXT: slli a5, a0, 1
+; RV64IMZBS-NEXT: slli a0, a6, 63
+; RV64IMZBS-NEXT: and a6, a1, s9
+; RV64IMZBS-NEXT: slli a7, t0, 1
+; RV64IMZBS-NEXT: and t0, t1, s9
+; RV64IMZBS-NEXT: slli t1, t2, 1
+; RV64IMZBS-NEXT: slli a1, a1, 63
+; RV64IMZBS-NEXT: or s1, a2, a3
+; RV64IMZBS-NEXT: or a4, a4, a5
+; RV64IMZBS-NEXT: srli a5, a5, 63
+; RV64IMZBS-NEXT: or a3, a6, a7
+; RV64IMZBS-NEXT: or s5, t0, t1
+; RV64IMZBS-NEXT: srli a6, t1, 63
+; RV64IMZBS-NEXT: slli a7, s1, 1
+; RV64IMZBS-NEXT: andi t0, a4, 2
+; RV64IMZBS-NEXT: slli t1, s1, 2
+; RV64IMZBS-NEXT: andi t2, a4, 4
+; RV64IMZBS-NEXT: slli t3, s1, 3
+; RV64IMZBS-NEXT: andi t4, a4, 8
+; RV64IMZBS-NEXT: slli t5, s1, 4
+; RV64IMZBS-NEXT: andi t6, a4, 16
+; RV64IMZBS-NEXT: slli s0, s1, 5
+; RV64IMZBS-NEXT: andi s2, a4, 32
+; RV64IMZBS-NEXT: slli s3, s1, 6
+; RV64IMZBS-NEXT: andi s4, a4, 64
+; RV64IMZBS-NEXT: seqz a5, a5
+; RV64IMZBS-NEXT: addi a5, a5, -1
+; RV64IMZBS-NEXT: and a0, a5, a0
+; RV64IMZBS-NEXT: sd a0, 896(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: slli a0, s1, 7
+; RV64IMZBS-NEXT: seqz a5, a6
+; RV64IMZBS-NEXT: addi a5, a5, -1
+; RV64IMZBS-NEXT: and a1, a5, a1
+; RV64IMZBS-NEXT: sd a1, 904(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: andi a1, a4, 128
+; RV64IMZBS-NEXT: seqz a5, t0
; RV64IMZBS-NEXT: addi a5, a5, -1
-; RV64IMZBS-NEXT: and t2, a5, t2
-; RV64IMZBS-NEXT: andi a5, t5, 512
-; RV64IMZBS-NEXT: seqz a6, s0
+; RV64IMZBS-NEXT: and a2, a5, a7
+; RV64IMZBS-NEXT: sd a2, 864(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: slli a5, s1, 8
+; RV64IMZBS-NEXT: seqz a6, t2
; RV64IMZBS-NEXT: addi a6, a6, -1
-; RV64IMZBS-NEXT: and t3, a6, t6
-; RV64IMZBS-NEXT: slli a6, t4, 10
-; RV64IMZBS-NEXT: seqz a7, s2
+; RV64IMZBS-NEXT: and a2, a6, t1
+; RV64IMZBS-NEXT: sd a2, 848(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: andi a6, a4, 256
+; RV64IMZBS-NEXT: seqz a7, t4
; RV64IMZBS-NEXT: addi a7, a7, -1
-; RV64IMZBS-NEXT: and a1, a7, s1
-; RV64IMZBS-NEXT: sd a1, 888(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: andi a7, t5, 1024
-; RV64IMZBS-NEXT: seqz a0, a0
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: and t6, a0, s3
-; RV64IMZBS-NEXT: slli a0, t4, 11
-; RV64IMZBS-NEXT: seqz a3, a3
-; RV64IMZBS-NEXT: addi a3, a3, -1
-; RV64IMZBS-NEXT: and s2, a3, a2
-; RV64IMZBS-NEXT: not a2, t5
-; RV64IMZBS-NEXT: seqz a3, a5
-; RV64IMZBS-NEXT: addi a3, a3, -1
-; RV64IMZBS-NEXT: and a3, a3, a4
-; RV64IMZBS-NEXT: sd a3, 840(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: slli a3, t4, 12
-; RV64IMZBS-NEXT: seqz a4, a7
-; RV64IMZBS-NEXT: addi a4, a4, -1
-; RV64IMZBS-NEXT: and a1, a4, a6
-; RV64IMZBS-NEXT: sd a1, 904(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a4, a2, 11
-; RV64IMZBS-NEXT: addi a4, a4, -1
-; RV64IMZBS-NEXT: and a6, a4, a0
-; RV64IMZBS-NEXT: bexti a0, a2, 12
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 776(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 13
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 13
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 816(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 14
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 14
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 856(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 15
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 15
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 896(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 16
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 16
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 736(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 17
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 17
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 728(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 18
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 18
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 768(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 19
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 19
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 800(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 20
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 20
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 832(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 21
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 21
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 872(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 22
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 22
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 680(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 23
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 23
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 664(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 24
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 24
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 712(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 25
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 25
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 752(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 26
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 26
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 792(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 27
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 27
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 808(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 28
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 28
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 824(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 29
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 29
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 608(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 30
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 30
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 600(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sraiw a0, t5, 31
-; RV64IMZBS-NEXT: seqz a0, a0
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 31
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 648(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 32
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 32
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 672(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 33
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 33
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 704(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 34
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 34
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 744(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 35
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 35
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 760(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 36
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 36
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 784(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 37
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 37
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 552(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 38
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 38
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 544(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 39
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 39
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 568(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 40
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 40
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 592(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 41
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 41
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 640(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 42
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 42
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 656(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 43
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 43
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 688(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 44
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 44
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 696(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 45
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 45
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 720(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 46
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 46
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 496(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 47
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 47
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 488(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 48
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 48
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 520(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 49
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 49
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 536(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 50
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 50
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 560(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 51
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 51
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 576(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 52
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 52
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 584(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 53
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 53
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 616(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 54
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 54
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 624(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 55
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 55
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 632(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 56
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 56
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 464(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 57
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 57
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 456(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 58
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 58
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 472(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 59
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 59
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 480(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 60
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 60
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 504(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 61
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 61
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 512(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: andi a0, t5, 1
-; RV64IMZBS-NEXT: seqz a0, a0
+; RV64IMZBS-NEXT: and t3, a7, t3
+; RV64IMZBS-NEXT: slli a7, s1, 9
+; RV64IMZBS-NEXT: seqz t0, t6
+; RV64IMZBS-NEXT: addi t0, t0, -1
+; RV64IMZBS-NEXT: and t4, t0, t5
+; RV64IMZBS-NEXT: andi t0, a4, 512
+; RV64IMZBS-NEXT: seqz t1, s2
+; RV64IMZBS-NEXT: addi t1, t1, -1
+; RV64IMZBS-NEXT: and t5, t1, s0
+; RV64IMZBS-NEXT: slli t1, s1, 10
+; RV64IMZBS-NEXT: seqz t2, s4
+; RV64IMZBS-NEXT: addi t2, t2, -1
+; RV64IMZBS-NEXT: and a2, t2, s3
+; RV64IMZBS-NEXT: sd a2, 872(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: andi t2, a4, 1024
+; RV64IMZBS-NEXT: seqz a1, a1
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: and t6, a1, a0
+; RV64IMZBS-NEXT: slli a1, s1, 11
+; RV64IMZBS-NEXT: seqz a0, a6
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: and t5, a0, t4
-; RV64IMZBS-NEXT: slli t4, t4, 62
-; RV64IMZBS-NEXT: bexti a0, a2, 62
+; RV64IMZBS-NEXT: and s2, a0, a5
+; RV64IMZBS-NEXT: not a0, a4
+; RV64IMZBS-NEXT: seqz a5, t0
+; RV64IMZBS-NEXT: addi a5, a5, -1
+; RV64IMZBS-NEXT: and a2, a5, a7
+; RV64IMZBS-NEXT: sd a2, 832(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: slli a5, s1, 12
+; RV64IMZBS-NEXT: seqz a6, t2
+; RV64IMZBS-NEXT: addi a6, a6, -1
+; RV64IMZBS-NEXT: and a2, a6, t1
+; RV64IMZBS-NEXT: sd a2, 888(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a6, a0, 11
+; RV64IMZBS-NEXT: addi a6, a6, -1
+; RV64IMZBS-NEXT: and a7, a6, a1
+; RV64IMZBS-NEXT: bexti a1, a0, 12
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: and t1, a1, a5
+; RV64IMZBS-NEXT: bexti a1, a0, 13
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 13
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 808(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 14
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 14
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 840(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 15
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 15
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 880(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 16
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 16
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 736(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 17
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 17
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 728(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 18
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 18
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 768(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 19
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 19
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 792(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 20
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 20
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 824(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 21
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 21
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 856(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 22
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 22
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 680(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 23
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 23
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 664(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 24
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 24
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 712(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 25
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 25
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 752(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 26
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 26
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 784(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 27
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 27
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 800(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 28
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 28
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 816(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 29
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 29
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 608(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 30
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 30
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 600(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sraiw a1, a4, 31
+; RV64IMZBS-NEXT: seqz a1, a1
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 31
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 648(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 32
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 32
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 672(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 33
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 33
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 704(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 34
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 34
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 744(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 35
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 35
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 760(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 36
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 36
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 776(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 37
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 37
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 552(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 38
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 38
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 544(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 39
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 39
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 568(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 40
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 40
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 592(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 41
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 41
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 640(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 42
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 42
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 656(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 43
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 43
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 688(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 44
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 44
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 696(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 45
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 45
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 720(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 46
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 46
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 496(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 47
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 47
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 488(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 48
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 48
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 520(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 49
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 49
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 536(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 50
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 50
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 560(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 51
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 51
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 576(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 52
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 52
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 584(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 53
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 53
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 616(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 54
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 54
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 624(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 55
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 55
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 632(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 56
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 56
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 464(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 57
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 57
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 456(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 58
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 58
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 472(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 59
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 59
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 480(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 60
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 60
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 504(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 61
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 61
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 512(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: andi a4, a4, 1
+; RV64IMZBS-NEXT: seqz a1, a4
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: and s3, a1, s1
+; RV64IMZBS-NEXT: slli s1, s1, 62
+; RV64IMZBS-NEXT: bexti a0, a0, 62
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: and a0, a0, t4
+; RV64IMZBS-NEXT: and a0, a0, s1
; RV64IMZBS-NEXT: sd a0, 528(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: andi a0, s5, 2
; RV64IMZBS-NEXT: seqz a0, a0
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a2, t0, 1
-; RV64IMZBS-NEXT: and a0, a0, a2
+; RV64IMZBS-NEXT: slli a1, a3, 1
+; RV64IMZBS-NEXT: and a0, a0, a1
; RV64IMZBS-NEXT: sd a0, 448(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: andi a0, s5, 4
; RV64IMZBS-NEXT: seqz a0, a0
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a2, t0, 2
-; RV64IMZBS-NEXT: and a0, a0, a2
+; RV64IMZBS-NEXT: slli a1, a3, 2
+; RV64IMZBS-NEXT: and a0, a0, a1
; RV64IMZBS-NEXT: sd a0, 432(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: andi a0, s5, 8
; RV64IMZBS-NEXT: seqz a0, a0
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a2, t0, 3
-; RV64IMZBS-NEXT: and a0, a0, a2
+; RV64IMZBS-NEXT: slli a1, a3, 3
+; RV64IMZBS-NEXT: and a0, a0, a1
; RV64IMZBS-NEXT: sd a0, 408(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: andi a0, s5, 16
; RV64IMZBS-NEXT: seqz a0, a0
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a2, t0, 4
-; RV64IMZBS-NEXT: and a0, a0, a2
+; RV64IMZBS-NEXT: slli a1, a3, 4
+; RV64IMZBS-NEXT: and a0, a0, a1
; RV64IMZBS-NEXT: sd a0, 400(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: andi a0, s5, 32
; RV64IMZBS-NEXT: seqz a0, a0
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a2, t0, 5
-; RV64IMZBS-NEXT: and a0, a0, a2
+; RV64IMZBS-NEXT: slli a1, a3, 5
+; RV64IMZBS-NEXT: and a0, a0, a1
; RV64IMZBS-NEXT: sd a0, 376(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: andi a0, s5, 64
; RV64IMZBS-NEXT: seqz a0, a0
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a2, t0, 6
-; RV64IMZBS-NEXT: and a0, a0, a2
+; RV64IMZBS-NEXT: slli a1, a3, 6
+; RV64IMZBS-NEXT: and a0, a0, a1
; RV64IMZBS-NEXT: sd a0, 440(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: andi a0, s5, 128
; RV64IMZBS-NEXT: seqz a0, a0
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a2, t0, 7
-; RV64IMZBS-NEXT: and a0, a0, a2
+; RV64IMZBS-NEXT: slli a1, a3, 7
+; RV64IMZBS-NEXT: and a0, a0, a1
; RV64IMZBS-NEXT: sd a0, 360(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: andi a0, s5, 256
; RV64IMZBS-NEXT: seqz a0, a0
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a2, t0, 8
-; RV64IMZBS-NEXT: and a0, a0, a2
+; RV64IMZBS-NEXT: slli a1, a3, 8
+; RV64IMZBS-NEXT: and a0, a0, a1
; RV64IMZBS-NEXT: sd a0, 344(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: andi a0, s5, 512
; RV64IMZBS-NEXT: seqz a0, a0
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a2, t0, 9
-; RV64IMZBS-NEXT: and a0, a0, a2
+; RV64IMZBS-NEXT: slli a1, a3, 9
+; RV64IMZBS-NEXT: and a0, a0, a1
; RV64IMZBS-NEXT: sd a0, 392(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: andi a0, s5, 1024
; RV64IMZBS-NEXT: seqz a0, a0
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a2, t0, 10
-; RV64IMZBS-NEXT: and a0, a0, a2
+; RV64IMZBS-NEXT: slli a1, a3, 10
+; RV64IMZBS-NEXT: and a0, a0, a1
; RV64IMZBS-NEXT: sd a0, 424(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: not a0, s5
-; RV64IMZBS-NEXT: bexti a2, a0, 11
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 11
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 304(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 12
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 12
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 296(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 13
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 13
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 328(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 14
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 14
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 368(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 15
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 15
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 416(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 16
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 16
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 248(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 17
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 17
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 232(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 18
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 18
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 280(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 19
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 19
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 320(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 20
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 20
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 352(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 21
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 21
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 384(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 22
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 22
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 192(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 23
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 23
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 168(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 24
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 24
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 224(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 25
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 25
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 256(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 26
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 26
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 288(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 27
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 27
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 312(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 28
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 28
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 336(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 29
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 29
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 136(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 30
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 30
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 112(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sraiw a2, s5, 31
-; RV64IMZBS-NEXT: seqz a2, a2
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 31
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 152(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 32
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 32
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 184(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 33
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 33
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 216(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 34
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 34
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 240(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 35
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 35
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 264(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 36
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 36
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 272(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 37
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 37
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 56(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 38
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 38
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 48(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 39
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 39
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 72(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 40
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 40
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 96(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 41
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 41
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 144(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 42
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 42
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 160(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 43
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 43
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 176(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 44
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 44
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 200(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 45
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 45
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 208(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 46
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 46
-; RV64IMZBS-NEXT: and s11, a2, a3
-; RV64IMZBS-NEXT: bexti a2, a0, 47
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a4, t0, 47
-; RV64IMZBS-NEXT: and s9, a2, a4
-; RV64IMZBS-NEXT: bexti a2, a0, 48
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 48
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 24(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 49
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 49
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 40(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 50
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 50
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 64(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 51
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli s0, t0, 51
-; RV64IMZBS-NEXT: and a2, a2, s0
-; RV64IMZBS-NEXT: sd a2, 80(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 52
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli s1, t0, 52
-; RV64IMZBS-NEXT: and a2, a2, s1
-; RV64IMZBS-NEXT: sd a2, 88(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 53
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 53
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 104(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 54
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 54
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 120(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 55
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 55
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 128(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 56
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 56
-; RV64IMZBS-NEXT: and s6, a2, a3
-; RV64IMZBS-NEXT: bexti a3, a0, 57
-; RV64IMZBS-NEXT: addi a3, a3, -1
-; RV64IMZBS-NEXT: slli a4, t0, 57
-; RV64IMZBS-NEXT: and s4, a3, a4
-; RV64IMZBS-NEXT: bexti a4, a0, 58
+; RV64IMZBS-NEXT: bexti a1, a0, 11
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 11
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 304(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 12
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 12
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 296(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 13
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 13
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 328(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 14
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 14
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 368(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 15
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 15
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 416(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 16
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 16
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 248(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 17
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 17
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 232(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 18
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 18
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 280(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 19
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 19
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 320(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 20
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 20
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 352(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 21
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 21
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 384(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 22
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 22
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 192(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 23
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 23
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 168(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 24
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 24
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 224(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 25
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 25
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 256(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 26
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 26
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 288(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 27
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 27
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 312(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 28
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 28
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 336(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 29
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 29
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 136(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 30
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 30
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 112(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sraiw a1, s5, 31
+; RV64IMZBS-NEXT: seqz a1, a1
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 31
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 152(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 32
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 32
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 184(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 33
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 33
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 216(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 34
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 34
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 240(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 35
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 35
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 264(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 36
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 36
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 272(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 37
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 37
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 56(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 38
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 38
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 48(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 39
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 39
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 72(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 40
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 40
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 96(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 41
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 41
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 144(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 42
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 42
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 160(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 43
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 43
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 176(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 44
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 44
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 200(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 45
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 45
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 208(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 46
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 46
+; RV64IMZBS-NEXT: and s11, a1, a4
+; RV64IMZBS-NEXT: bexti a1, a0, 47
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, a3, 47
+; RV64IMZBS-NEXT: and s9, a1, a5
+; RV64IMZBS-NEXT: bexti a1, a0, 48
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 48
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 24(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 49
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 49
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 40(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 50
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 50
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 64(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 51
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli s0, a3, 51
+; RV64IMZBS-NEXT: and a1, a1, s0
+; RV64IMZBS-NEXT: sd a1, 80(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 52
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli s1, a3, 52
+; RV64IMZBS-NEXT: and a1, a1, s1
+; RV64IMZBS-NEXT: sd a1, 88(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 53
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 53
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 104(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 54
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 54
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 120(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 55
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 55
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 128(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 56
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 56
+; RV64IMZBS-NEXT: and s6, a1, a4
+; RV64IMZBS-NEXT: bexti a4, a0, 57
; RV64IMZBS-NEXT: addi a4, a4, -1
-; RV64IMZBS-NEXT: slli a5, t0, 58
-; RV64IMZBS-NEXT: and s7, a4, a5
-; RV64IMZBS-NEXT: bexti a5, a0, 59
+; RV64IMZBS-NEXT: slli a5, a3, 57
+; RV64IMZBS-NEXT: and s4, a4, a5
+; RV64IMZBS-NEXT: bexti a5, a0, 58
; RV64IMZBS-NEXT: addi a5, a5, -1
-; RV64IMZBS-NEXT: slli a7, t0, 59
-; RV64IMZBS-NEXT: and s8, a5, a7
-; RV64IMZBS-NEXT: bexti a7, a0, 60
-; RV64IMZBS-NEXT: addi a7, a7, -1
-; RV64IMZBS-NEXT: slli t1, t0, 60
-; RV64IMZBS-NEXT: and s10, a7, t1
-; RV64IMZBS-NEXT: bexti t1, a0, 61
-; RV64IMZBS-NEXT: addi t1, t1, -1
-; RV64IMZBS-NEXT: slli a1, t0, 61
-; RV64IMZBS-NEXT: and a1, t1, a1
+; RV64IMZBS-NEXT: slli a6, a3, 58
+; RV64IMZBS-NEXT: and s7, a5, a6
+; RV64IMZBS-NEXT: bexti a6, a0, 59
+; RV64IMZBS-NEXT: addi a6, a6, -1
+; RV64IMZBS-NEXT: slli t0, a3, 59
+; RV64IMZBS-NEXT: and s8, a6, t0
+; RV64IMZBS-NEXT: bexti t0, a0, 60
+; RV64IMZBS-NEXT: addi t0, t0, -1
+; RV64IMZBS-NEXT: slli t2, a3, 60
+; RV64IMZBS-NEXT: and s10, t0, t2
+; RV64IMZBS-NEXT: bexti t2, a0, 61
+; RV64IMZBS-NEXT: addi t2, t2, -1
+; RV64IMZBS-NEXT: slli a2, a3, 61
+; RV64IMZBS-NEXT: and a1, t2, a2
; RV64IMZBS-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: andi a1, s5, 1
-; RV64IMZBS-NEXT: seqz a1, a1
-; RV64IMZBS-NEXT: addi a1, a1, -1
-; RV64IMZBS-NEXT: and a1, a1, t0
-; RV64IMZBS-NEXT: slli t0, t0, 62
+; RV64IMZBS-NEXT: andi a2, s5, 1
+; RV64IMZBS-NEXT: seqz a2, a2
+; RV64IMZBS-NEXT: addi a2, a2, -1
+; RV64IMZBS-NEXT: and a2, a2, a3
+; RV64IMZBS-NEXT: slli a3, a3, 62
; RV64IMZBS-NEXT: bexti a0, a0, 62
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: and a0, a0, t0
+; RV64IMZBS-NEXT: and a0, a0, a3
; RV64IMZBS-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: ld a0, 880(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor s3, t5, a0
; RV64IMZBS-NEXT: ld a0, 864(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld a2, 848(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor s5, a0, a2
-; RV64IMZBS-NEXT: xor t2, t2, t3
-; RV64IMZBS-NEXT: xor t4, t6, s2
-; RV64IMZBS-NEXT: ld a0, 776(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor t5, a6, a0
+; RV64IMZBS-NEXT: xor s3, s3, a0
+; RV64IMZBS-NEXT: ld a0, 848(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor s5, a0, t3
+; RV64IMZBS-NEXT: xor t2, t4, t5
+; RV64IMZBS-NEXT: xor t3, t6, s2
+; RV64IMZBS-NEXT: xor t5, a7, t1
; RV64IMZBS-NEXT: ld a0, 736(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld a2, 728(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor t6, a0, a2
+; RV64IMZBS-NEXT: ld a1, 728(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor t6, a0, a1
; RV64IMZBS-NEXT: ld a0, 680(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: ld s0, 664(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor s0, a0, s0
@@ -12521,16 +12526,16 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: ld s1, 600(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor s1, a0, s1
; RV64IMZBS-NEXT: ld a0, 552(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld a2, 544(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor s2, a0, a2
+; RV64IMZBS-NEXT: ld a1, 544(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor s2, a0, a1
; RV64IMZBS-NEXT: ld a0, 496(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld a2, 488(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor t0, a0, a2
+; RV64IMZBS-NEXT: ld a1, 488(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor t0, a0, a1
; RV64IMZBS-NEXT: ld a0, 464(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld a2, 456(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor t1, a0, a2
+; RV64IMZBS-NEXT: ld a1, 456(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor t1, a0, a1
; RV64IMZBS-NEXT: ld a0, 448(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor t3, a1, a0
+; RV64IMZBS-NEXT: xor t4, a2, a0
; RV64IMZBS-NEXT: ld a0, 432(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: ld a1, 408(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor a0, a0, a1
@@ -12558,11 +12563,11 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: xor s9, s11, s9
; RV64IMZBS-NEXT: xor s4, s6, s4
; RV64IMZBS-NEXT: xor s3, s3, s5
-; RV64IMZBS-NEXT: ld s5, 888(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s5, 872(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t2, t2, s5
-; RV64IMZBS-NEXT: ld s5, 840(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor t4, t4, s5
-; RV64IMZBS-NEXT: ld s5, 816(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s5, 832(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor t3, t3, s5
+; RV64IMZBS-NEXT: ld s5, 808(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t5, t5, s5
; RV64IMZBS-NEXT: ld s5, 768(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t6, t6, s5
@@ -12576,30 +12581,30 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: xor t0, t0, s5
; RV64IMZBS-NEXT: ld s5, 472(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t1, t1, s5
-; RV64IMZBS-NEXT: xor a0, t3, a0
-; RV64IMZBS-NEXT: ld t3, 440(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor a1, a1, t3
-; RV64IMZBS-NEXT: ld t3, 392(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor a2, a2, t3
-; RV64IMZBS-NEXT: ld t3, 328(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor a3, a3, t3
-; RV64IMZBS-NEXT: ld t3, 280(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor a4, a4, t3
-; RV64IMZBS-NEXT: ld t3, 224(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor a5, a5, t3
-; RV64IMZBS-NEXT: ld t3, 152(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor a6, a6, t3
-; RV64IMZBS-NEXT: ld t3, 72(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor a7, a7, t3
-; RV64IMZBS-NEXT: ld t3, 24(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor t3, s9, t3
+; RV64IMZBS-NEXT: xor a0, t4, a0
+; RV64IMZBS-NEXT: ld t4, 440(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor a1, a1, t4
+; RV64IMZBS-NEXT: ld t4, 392(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor a2, a2, t4
+; RV64IMZBS-NEXT: ld t4, 328(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor a3, a3, t4
+; RV64IMZBS-NEXT: ld t4, 280(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor a4, a4, t4
+; RV64IMZBS-NEXT: ld t4, 224(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor a5, a5, t4
+; RV64IMZBS-NEXT: ld t4, 152(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor a6, a6, t4
+; RV64IMZBS-NEXT: ld t4, 72(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor a7, a7, t4
+; RV64IMZBS-NEXT: ld t4, 24(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor t4, s9, t4
; RV64IMZBS-NEXT: xor s4, s4, s7
; RV64IMZBS-NEXT: xor t2, s3, t2
-; RV64IMZBS-NEXT: ld s3, 904(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor t4, t4, s3
-; RV64IMZBS-NEXT: ld s3, 856(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s3, 888(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor t3, t3, s3
+; RV64IMZBS-NEXT: ld s3, 840(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t5, t5, s3
-; RV64IMZBS-NEXT: ld s3, 800(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s3, 792(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t6, t6, s3
; RV64IMZBS-NEXT: ld s3, 752(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor s0, s0, s3
@@ -12625,14 +12630,14 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: ld a6, 96(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor a6, a7, a6
; RV64IMZBS-NEXT: ld a7, 40(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor a7, t3, a7
-; RV64IMZBS-NEXT: xor t3, s4, s8
-; RV64IMZBS-NEXT: xor t2, t2, t4
-; RV64IMZBS-NEXT: ld t4, 896(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor t4, t5, t4
-; RV64IMZBS-NEXT: ld t5, 832(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor a7, t4, a7
+; RV64IMZBS-NEXT: xor t4, s4, s8
+; RV64IMZBS-NEXT: xor t2, t2, t3
+; RV64IMZBS-NEXT: ld t3, 880(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor t3, t5, t3
+; RV64IMZBS-NEXT: ld t5, 824(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t5, t6, t5
-; RV64IMZBS-NEXT: ld t6, 792(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld t6, 784(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t6, s0, t6
; RV64IMZBS-NEXT: ld s0, 704(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor s0, s1, s0
@@ -12655,11 +12660,11 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: xor a5, a6, a5
; RV64IMZBS-NEXT: ld a6, 64(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor a6, a7, a6
-; RV64IMZBS-NEXT: xor a7, t3, s10
-; RV64IMZBS-NEXT: xor t2, t2, t4
-; RV64IMZBS-NEXT: ld t3, 872(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor a7, t4, s10
+; RV64IMZBS-NEXT: xor t2, t2, t3
+; RV64IMZBS-NEXT: ld t3, 856(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t3, t5, t3
-; RV64IMZBS-NEXT: ld t4, 808(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld t4, 800(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t4, t6, t4
; RV64IMZBS-NEXT: ld t5, 744(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t5, s0, t5
@@ -12683,7 +12688,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: ld a6, 16(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor a6, a7, a6
; RV64IMZBS-NEXT: xor a7, t2, t3
-; RV64IMZBS-NEXT: ld t2, 824(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld t2, 816(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t2, t4, t2
; RV64IMZBS-NEXT: ld t3, 760(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t3, t5, t3
@@ -12705,13 +12710,13 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: ld a5, 32(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor a5, a6, a5
; RV64IMZBS-NEXT: xor a6, a7, t2
-; RV64IMZBS-NEXT: ld a7, 784(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld a7, 776(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor a7, t3, a7
; RV64IMZBS-NEXT: ld t2, 696(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t2, t4, t2
; RV64IMZBS-NEXT: ld t3, 616(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t0, t0, t3
-; RV64IMZBS-NEXT: ld t3, 912(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld t3, 896(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t1, t1, t3
; RV64IMZBS-NEXT: xor a0, a0, a1
; RV64IMZBS-NEXT: ld a1, 272(sp) # 8-byte Folded Reload
@@ -12720,7 +12725,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: xor a2, a3, a2
; RV64IMZBS-NEXT: ld a3, 104(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor a3, a4, a3
-; RV64IMZBS-NEXT: ld a4, 920(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld a4, 904(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor a4, a5, a4
; RV64IMZBS-NEXT: xor a5, a6, a7
; RV64IMZBS-NEXT: ld a6, 720(sp) # 8-byte Folded Reload
@@ -12732,9 +12737,9 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: xor a2, a2, a0
; RV64IMZBS-NEXT: ld a0, 120(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor a3, a3, a0
-; RV64IMZBS-NEXT: xor a5, a5, a6
; RV64IMZBS-NEXT: lui a0, %hi(.LCPI6_0)
; RV64IMZBS-NEXT: ld a0, %lo(.LCPI6_0)(a0)
+; RV64IMZBS-NEXT: xor a5, a5, a6
; RV64IMZBS-NEXT: ld a6, 632(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor a6, a7, a6
; RV64IMZBS-NEXT: xor a1, a1, a2
@@ -12749,40 +12754,40 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: srli a5, a2, 24
; RV64IMZBS-NEXT: srli a6, a2, 8
; RV64IMZBS-NEXT: srliw a7, a2, 24
-; RV64IMZBS-NEXT: lui t3, 4080
-; RV64IMZBS-NEXT: and t0, a2, t3
-; RV64IMZBS-NEXT: srli t1, a1, 8
-; RV64IMZBS-NEXT: ld t2, 960(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: and a6, a6, t2
-; RV64IMZBS-NEXT: and t1, t1, t2
-; RV64IMZBS-NEXT: slli t2, a2, 56
-; RV64IMZBS-NEXT: ld t4, 944(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: and a2, a2, t4
-; RV64IMZBS-NEXT: and a3, a3, t4
+; RV64IMZBS-NEXT: lui t4, 4080
+; RV64IMZBS-NEXT: and t0, a2, t4
+; RV64IMZBS-NEXT: slli t1, a2, 56
+; RV64IMZBS-NEXT: ld t5, 920(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: and a2, a2, t5
+; RV64IMZBS-NEXT: srli t2, a1, 8
+; RV64IMZBS-NEXT: ld t3, 944(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: and a6, a6, t3
+; RV64IMZBS-NEXT: and t2, t2, t3
+; RV64IMZBS-NEXT: srli t3, a1, 40
+; RV64IMZBS-NEXT: and a3, a3, t5
; RV64IMZBS-NEXT: or a3, a3, a4
-; RV64IMZBS-NEXT: srli a4, a1, 40
-; RV64IMZBS-NEXT: and a5, a5, t3
+; RV64IMZBS-NEXT: srli a4, a1, 56
+; RV64IMZBS-NEXT: and a5, a5, t4
; RV64IMZBS-NEXT: or a5, a6, a5
-; RV64IMZBS-NEXT: srli a6, a1, 56
+; RV64IMZBS-NEXT: srli a6, a1, 24
; RV64IMZBS-NEXT: slli a7, a7, 32
; RV64IMZBS-NEXT: slli t0, t0, 24
; RV64IMZBS-NEXT: or a7, t0, a7
-; RV64IMZBS-NEXT: srli t0, a1, 24
-; RV64IMZBS-NEXT: slli a2, a2, 40
-; RV64IMZBS-NEXT: or a2, t2, a2
-; RV64IMZBS-NEXT: srliw t2, a1, 24
-; RV64IMZBS-NEXT: and t0, t0, t3
-; RV64IMZBS-NEXT: and t3, a1, t3
-; RV64IMZBS-NEXT: and a4, a4, t4
+; RV64IMZBS-NEXT: srliw t0, a1, 24
+; RV64IMZBS-NEXT: and a6, a6, t4
; RV64IMZBS-NEXT: and t4, a1, t4
+; RV64IMZBS-NEXT: and t3, t3, t5
+; RV64IMZBS-NEXT: and t5, a1, t5
; RV64IMZBS-NEXT: slli a1, a1, 56
-; RV64IMZBS-NEXT: slli t2, t2, 32
-; RV64IMZBS-NEXT: slli t3, t3, 24
-; RV64IMZBS-NEXT: slli t4, t4, 40
-; RV64IMZBS-NEXT: or a4, a4, a6
-; RV64IMZBS-NEXT: or a6, t1, t0
-; RV64IMZBS-NEXT: or t0, t3, t2
-; RV64IMZBS-NEXT: or a1, a1, t4
+; RV64IMZBS-NEXT: slli a2, a2, 40
+; RV64IMZBS-NEXT: slli t0, t0, 32
+; RV64IMZBS-NEXT: slli t4, t4, 24
+; RV64IMZBS-NEXT: slli t5, t5, 40
+; RV64IMZBS-NEXT: or a2, t1, a2
+; RV64IMZBS-NEXT: or a4, t3, a4
+; RV64IMZBS-NEXT: or a6, t2, a6
+; RV64IMZBS-NEXT: or t0, t4, t0
+; RV64IMZBS-NEXT: or a1, a1, t5
; RV64IMZBS-NEXT: or a3, a5, a3
; RV64IMZBS-NEXT: or a2, a2, a7
; RV64IMZBS-NEXT: or a4, a6, a4
@@ -12790,7 +12795,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: or a2, a2, a3
; RV64IMZBS-NEXT: or a1, a1, a4
; RV64IMZBS-NEXT: srli a3, a2, 4
-; RV64IMZBS-NEXT: ld a5, 952(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld a5, 936(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: and a2, a2, a5
; RV64IMZBS-NEXT: srli a4, a1, 4
; RV64IMZBS-NEXT: and a1, a1, a5
@@ -12801,7 +12806,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: or a2, a3, a2
; RV64IMZBS-NEXT: or a1, a4, a1
; RV64IMZBS-NEXT: srli a3, a2, 2
-; RV64IMZBS-NEXT: ld a5, 936(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld a5, 928(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: and a2, a2, a5
; RV64IMZBS-NEXT: srli a4, a1, 2
; RV64IMZBS-NEXT: and a1, a1, a5
@@ -12812,7 +12817,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: or a2, a3, a2
; RV64IMZBS-NEXT: or a1, a4, a1
; RV64IMZBS-NEXT: srli a3, a2, 1
-; RV64IMZBS-NEXT: ld a5, 928(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld a5, 912(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: and a2, a2, a5
; RV64IMZBS-NEXT: srli a4, a1, 1
; RV64IMZBS-NEXT: and a1, a1, a5
@@ -12824,26 +12829,26 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: or a0, a0, a1
; RV64IMZBS-NEXT: srli a2, a2, 1
; RV64IMZBS-NEXT: srli a0, a0, 1
-; RV64IMZBS-NEXT: ld a1, 968(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld a1, 952(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: sd a2, 0(a1)
; RV64IMZBS-NEXT: sd a0, 8(a1)
-; RV64IMZBS-NEXT: ld a1, 976(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld a1, 960(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: sd a2, 0(a1)
; RV64IMZBS-NEXT: sd a0, 8(a1)
-; RV64IMZBS-NEXT: ld ra, 1080(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s0, 1072(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s1, 1064(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s2, 1056(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s3, 1048(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s4, 1040(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s5, 1032(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s6, 1024(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s7, 1016(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s8, 1008(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s9, 1000(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s10, 992(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s11, 984(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: addi sp, sp, 1088
+; RV64IMZBS-NEXT: ld ra, 1064(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s0, 1056(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s1, 1048(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s2, 1040(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s3, 1032(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s4, 1024(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s5, 1016(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s6, 1008(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s7, 1000(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s8, 992(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s9, 984(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s10, 976(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s11, 968(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: addi sp, sp, 1072
; RV64IMZBS-NEXT: ret
%x.ext = zext <2 x i64> %x to <2 x i128>
%y.ext = zext <2 x i64> %y to <2 x i128>
diff --git a/llvm/test/CodeGen/RISCV/clmulr.ll b/llvm/test/CodeGen/RISCV/clmulr.ll
index dca39abe43081..a4529896c74ed 100644
--- a/llvm/test/CodeGen/RISCV/clmulr.ll
+++ b/llvm/test/CodeGen/RISCV/clmulr.ll
@@ -805,22 +805,22 @@ define i32 @clmulr_i32(i32 %a, i32 %b) nounwind {
; RV32I-NEXT: srli s4, a1, 24
; RV32I-NEXT: slli s5, a1, 24
; RV32I-NEXT: li t5, 1
-; RV32I-NEXT: lui a7, 1
-; RV32I-NEXT: lui t0, 2
-; RV32I-NEXT: lui s11, 8
+; RV32I-NEXT: lui ra, 2
+; RV32I-NEXT: lui s10, 4
+; RV32I-NEXT: lui t1, 8
; RV32I-NEXT: lui t3, 32
; RV32I-NEXT: lui t4, 64
; RV32I-NEXT: lui t2, 128
; RV32I-NEXT: lui t6, 256
-; RV32I-NEXT: addi t1, a6, -256
-; RV32I-NEXT: addi s3, a3, -241
-; RV32I-NEXT: addi a4, a4, 819
-; RV32I-NEXT: addi a3, a2, 1365
-; RV32I-NEXT: slli a2, t5, 11
-; RV32I-NEXT: and t5, s0, t1
-; RV32I-NEXT: and a0, a0, t1
-; RV32I-NEXT: and s0, s6, t1
-; RV32I-NEXT: and a1, a1, t1
+; RV32I-NEXT: addi a7, a6, -256
+; RV32I-NEXT: addi t0, a3, -241
+; RV32I-NEXT: addi s3, a4, 819
+; RV32I-NEXT: addi a2, a2, 1365
+; RV32I-NEXT: slli a3, t5, 11
+; RV32I-NEXT: and t5, s0, a7
+; RV32I-NEXT: and a0, a0, a7
+; RV32I-NEXT: and s0, s6, a7
+; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: or t5, t5, s1
; RV32I-NEXT: slli a0, a0, 8
; RV32I-NEXT: or s0, s0, s4
@@ -830,278 +830,278 @@ define i32 @clmulr_i32(i32 %a, i32 %b) nounwind {
; RV32I-NEXT: or a0, a0, t5
; RV32I-NEXT: or a1, a1, s0
; RV32I-NEXT: srli t5, a0, 4
-; RV32I-NEXT: and a0, a0, s3
+; RV32I-NEXT: and a0, a0, t0
; RV32I-NEXT: srli s0, a1, 4
-; RV32I-NEXT: and a1, a1, s3
-; RV32I-NEXT: and t5, t5, s3
+; RV32I-NEXT: and a1, a1, t0
+; RV32I-NEXT: and t5, t5, t0
; RV32I-NEXT: slli a0, a0, 4
-; RV32I-NEXT: and s0, s0, s3
+; RV32I-NEXT: and s0, s0, t0
; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: or a0, t5, a0
; RV32I-NEXT: or a1, s0, a1
; RV32I-NEXT: srli t5, a0, 2
-; RV32I-NEXT: sw a4, 40(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a0, a0, a4
+; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: srli s0, a1, 2
-; RV32I-NEXT: and a1, a1, a4
-; RV32I-NEXT: and t5, t5, a4
+; RV32I-NEXT: and a1, a1, s3
+; RV32I-NEXT: and t5, t5, s3
; RV32I-NEXT: slli a0, a0, 2
-; RV32I-NEXT: and s0, s0, a4
+; RV32I-NEXT: and s0, s0, s3
; RV32I-NEXT: slli a1, a1, 2
-; RV32I-NEXT: or a0, t5, a0
+; RV32I-NEXT: or t5, t5, a0
; RV32I-NEXT: or a1, s0, a1
-; RV32I-NEXT: srli t5, a0, 1
-; RV32I-NEXT: sw a3, 36(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a0, a0, a3
+; RV32I-NEXT: srli a0, t5, 1
+; RV32I-NEXT: sw a2, 40(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t5, t5, a2
; RV32I-NEXT: srli s0, a1, 1
-; RV32I-NEXT: and a1, a1, a3
-; RV32I-NEXT: and s1, t5, a3
-; RV32I-NEXT: slli a0, a0, 1
-; RV32I-NEXT: and s0, s0, a3
-; RV32I-NEXT: slli t5, a1, 1
-; RV32I-NEXT: or a4, s1, a0
-; RV32I-NEXT: or a5, s0, t5
-; RV32I-NEXT: srli t5, t5, 31
-; RV32I-NEXT: slli s0, a4, 1
-; RV32I-NEXT: andi s1, a5, 2
-; RV32I-NEXT: slli a0, a4, 2
-; RV32I-NEXT: andi s4, a5, 4
-; RV32I-NEXT: slli s5, a4, 3
-; RV32I-NEXT: andi s6, a5, 8
-; RV32I-NEXT: slli s2, a4, 4
-; RV32I-NEXT: andi s7, a5, 16
-; RV32I-NEXT: slli s8, a4, 5
-; RV32I-NEXT: andi s10, a5, 32
-; RV32I-NEXT: slli s9, a4, 31
-; RV32I-NEXT: seqz t5, t5
-; RV32I-NEXT: addi t5, t5, -1
-; RV32I-NEXT: and a1, t5, s9
-; RV32I-NEXT: sw a1, 32(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t5, a4, 6
+; RV32I-NEXT: and s1, a1, a2
+; RV32I-NEXT: and a1, a0, a2
+; RV32I-NEXT: slli t5, t5, 1
+; RV32I-NEXT: and s0, s0, a2
+; RV32I-NEXT: slli s1, s1, 1
+; RV32I-NEXT: slli a0, a0, 31
+; RV32I-NEXT: or a5, a1, t5
+; RV32I-NEXT: or s0, s0, s1
+; RV32I-NEXT: srli s1, s1, 31
+; RV32I-NEXT: slli t5, a5, 1
+; RV32I-NEXT: andi s2, s0, 2
+; RV32I-NEXT: slli s4, a5, 2
+; RV32I-NEXT: andi s5, s0, 4
+; RV32I-NEXT: slli s6, a5, 3
+; RV32I-NEXT: andi s7, s0, 8
+; RV32I-NEXT: slli a1, a5, 4
+; RV32I-NEXT: andi s9, s0, 16
+; RV32I-NEXT: slli s8, a5, 5
+; RV32I-NEXT: andi s11, s0, 32
; RV32I-NEXT: seqz s1, s1
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: and s0, s1, s0
-; RV32I-NEXT: sw s0, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi s0, a5, 64
-; RV32I-NEXT: seqz s4, s4
+; RV32I-NEXT: and a0, s1, a0
+; RV32I-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, a5, 6
+; RV32I-NEXT: seqz s1, s2
+; RV32I-NEXT: addi s1, s1, -1
+; RV32I-NEXT: and a0, s1, t5
+; RV32I-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi t5, s0, 64
+; RV32I-NEXT: seqz s2, s5
+; RV32I-NEXT: addi s2, s2, -1
+; RV32I-NEXT: and a0, s2, s4
+; RV32I-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s2, a5, 7
+; RV32I-NEXT: seqz s4, s7
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: and a0, s4, a0
+; RV32I-NEXT: and a0, s4, s6
; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s1, a4, 7
-; RV32I-NEXT: seqz s4, s6
-; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: and a0, s4, s5
-; RV32I-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi ra, a5, 128
-; RV32I-NEXT: seqz s5, s7
+; RV32I-NEXT: andi a0, s0, 128
+; RV32I-NEXT: seqz s5, s9
; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: and a0, s5, s2
-; RV32I-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a0, a4, 8
-; RV32I-NEXT: seqz s6, s10
+; RV32I-NEXT: and a1, s5, a1
+; RV32I-NEXT: sw a1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a1, a5, 8
+; RV32I-NEXT: seqz s6, s11
; RV32I-NEXT: addi s6, s6, -1
-; RV32I-NEXT: and a1, s6, s8
-; RV32I-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi s10, a5, 256
-; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: and a1, s0, t5
-; RV32I-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t5, a4, 9
-; RV32I-NEXT: seqz s0, ra
-; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: and s0, s0, s1
-; RV32I-NEXT: sw s0, 0(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi s0, a5, 512
-; RV32I-NEXT: seqz s10, s10
-; RV32I-NEXT: addi s10, s10, -1
-; RV32I-NEXT: and s5, s10, a0
-; RV32I-NEXT: slli a0, a4, 10
-; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: and s10, s0, t5
-; RV32I-NEXT: andi t5, a5, 1024
+; RV32I-NEXT: and a4, s6, s8
+; RV32I-NEXT: sw a4, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi s1, s0, 256
; RV32I-NEXT: seqz t5, t5
; RV32I-NEXT: addi t5, t5, -1
-; RV32I-NEXT: and a0, t5, a0
+; RV32I-NEXT: and a2, t5, a2
+; RV32I-NEXT: sw a2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, a5, 9
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: addi a0, a0, -1
+; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t5, a4, 11
-; RV32I-NEXT: and s0, a5, a2
-; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: and s4, s0, t5
-; RV32I-NEXT: slli t5, a4, 12
-; RV32I-NEXT: and a7, a5, a7
-; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: and ra, a7, t5
-; RV32I-NEXT: slli a7, a4, 13
-; RV32I-NEXT: and t0, a5, t0
-; RV32I-NEXT: seqz t0, t0
-; RV32I-NEXT: addi t0, t0, -1
-; RV32I-NEXT: and t5, t0, a7
-; RV32I-NEXT: slli a7, a4, 14
-; RV32I-NEXT: lui a0, 4
-; RV32I-NEXT: and t0, a5, a0
-; RV32I-NEXT: seqz t0, t0
-; RV32I-NEXT: addi t0, t0, -1
-; RV32I-NEXT: and s1, t0, a7
-; RV32I-NEXT: slli a7, a4, 15
-; RV32I-NEXT: and a2, a5, s11
+; RV32I-NEXT: andi a0, s0, 512
+; RV32I-NEXT: seqz t5, s1
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: and s11, t5, a1
+; RV32I-NEXT: slli t5, a5, 10
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: addi a0, a0, -1
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: sw a0, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a0, s0, 1024
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: addi a0, a0, -1
+; RV32I-NEXT: and a0, a0, t5
+; RV32I-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a0, a5, 11
+; RV32I-NEXT: and a2, s0, a3
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and s0, a2, a7
-; RV32I-NEXT: slli a2, a4, 16
-; RV32I-NEXT: and a7, a5, a6
-; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: and t0, a7, a2
-; RV32I-NEXT: slli a2, a4, 17
-; RV32I-NEXT: and a7, a5, t3
-; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: and a7, a7, a2
-; RV32I-NEXT: slli a2, a4, 18
-; RV32I-NEXT: and t3, a5, t4
+; RV32I-NEXT: and s7, a2, a0
+; RV32I-NEXT: slli a0, a5, 12
+; RV32I-NEXT: lui a2, 1
+; RV32I-NEXT: and a2, s0, a2
+; RV32I-NEXT: seqz a2, a2
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and s2, a2, a0
+; RV32I-NEXT: slli a0, a5, 13
+; RV32I-NEXT: and a2, s0, ra
+; RV32I-NEXT: seqz a2, a2
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and s4, a2, a0
+; RV32I-NEXT: slli a0, a5, 14
+; RV32I-NEXT: and a2, s0, s10
+; RV32I-NEXT: seqz a2, a2
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and s6, a2, a0
+; RV32I-NEXT: slli a0, a5, 15
+; RV32I-NEXT: and a2, s0, t1
+; RV32I-NEXT: seqz a2, a2
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and s5, a2, a0
+; RV32I-NEXT: slli a0, a5, 16
+; RV32I-NEXT: and a2, s0, a6
+; RV32I-NEXT: seqz a2, a2
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and s1, a2, a0
+; RV32I-NEXT: slli a0, a5, 17
+; RV32I-NEXT: and a2, s0, t3
+; RV32I-NEXT: seqz a2, a2
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and t5, a2, a0
+; RV32I-NEXT: slli a0, a5, 18
+; RV32I-NEXT: and t3, s0, t4
; RV32I-NEXT: seqz t3, t3
; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: and t3, t3, a2
-; RV32I-NEXT: slli a2, a4, 19
-; RV32I-NEXT: and t2, a5, t2
+; RV32I-NEXT: and t3, t3, a0
+; RV32I-NEXT: slli a0, a5, 19
+; RV32I-NEXT: and t2, s0, t2
; RV32I-NEXT: seqz t2, t2
; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: and t2, t2, a2
-; RV32I-NEXT: slli a2, a4, 20
-; RV32I-NEXT: and t4, a5, t6
+; RV32I-NEXT: and t2, t2, a0
+; RV32I-NEXT: slli a0, a5, 20
+; RV32I-NEXT: and t4, s0, t6
; RV32I-NEXT: seqz t4, t4
; RV32I-NEXT: addi t4, t4, -1
-; RV32I-NEXT: and t4, t4, a2
-; RV32I-NEXT: lui a2, 512
-; RV32I-NEXT: and a2, a5, a2
+; RV32I-NEXT: and t4, t4, a0
+; RV32I-NEXT: lui a0, 512
+; RV32I-NEXT: and a0, s0, a0
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: addi a0, a0, -1
+; RV32I-NEXT: slli t6, a5, 21
+; RV32I-NEXT: and t6, a0, t6
+; RV32I-NEXT: lui a0, 1024
+; RV32I-NEXT: and a0, s0, a0
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: addi a2, a0, -1
+; RV32I-NEXT: slli a0, a5, 22
+; RV32I-NEXT: and a6, a2, a0
+; RV32I-NEXT: lui a2, 2048
+; RV32I-NEXT: and a2, s0, a2
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli t6, a4, 21
-; RV32I-NEXT: and t6, a2, t6
-; RV32I-NEXT: lui a2, 1024
-; RV32I-NEXT: and a2, a5, a2
+; RV32I-NEXT: slli a1, a5, 23
+; RV32I-NEXT: and a1, a2, a1
+; RV32I-NEXT: lui a2, 4096
+; RV32I-NEXT: and a2, s0, a2
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli a0, a4, 22
-; RV32I-NEXT: and a6, a2, a0
-; RV32I-NEXT: lui a0, 2048
-; RV32I-NEXT: and a0, a5, a0
-; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: addi a0, a0, -1
-; RV32I-NEXT: slli s2, a4, 23
-; RV32I-NEXT: and a2, a0, s2
-; RV32I-NEXT: lui s2, 4096
-; RV32I-NEXT: and s2, a5, s2
-; RV32I-NEXT: seqz s2, s2
-; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: slli s7, a4, 24
-; RV32I-NEXT: and s2, s2, s7
-; RV32I-NEXT: lui s7, 8192
-; RV32I-NEXT: and s7, a5, s7
-; RV32I-NEXT: seqz s7, s7
-; RV32I-NEXT: addi s7, s7, -1
-; RV32I-NEXT: slli s8, a4, 25
-; RV32I-NEXT: and s7, s7, s8
-; RV32I-NEXT: lui s8, 16384
-; RV32I-NEXT: and s8, a5, s8
+; RV32I-NEXT: slli s8, a5, 24
+; RV32I-NEXT: and a2, a2, s8
+; RV32I-NEXT: lui s8, 8192
+; RV32I-NEXT: and s8, s0, s8
; RV32I-NEXT: seqz s8, s8
; RV32I-NEXT: addi s8, s8, -1
-; RV32I-NEXT: slli s9, a4, 26
-; RV32I-NEXT: and s8, s8, s9
-; RV32I-NEXT: lui s9, 32768
-; RV32I-NEXT: and s9, a5, s9
-; RV32I-NEXT: seqz s9, s9
-; RV32I-NEXT: addi s9, s9, -1
-; RV32I-NEXT: slli s11, a4, 27
-; RV32I-NEXT: and s9, s9, s11
-; RV32I-NEXT: lui s11, 65536
-; RV32I-NEXT: and s11, a5, s11
-; RV32I-NEXT: seqz s11, s11
-; RV32I-NEXT: addi s11, s11, -1
-; RV32I-NEXT: slli a1, a4, 28
-; RV32I-NEXT: and a1, s11, a1
-; RV32I-NEXT: lui s11, 131072
-; RV32I-NEXT: and s11, a5, s11
-; RV32I-NEXT: seqz s11, s11
-; RV32I-NEXT: addi s11, s11, -1
-; RV32I-NEXT: slli a3, a4, 29
-; RV32I-NEXT: and a3, s11, a3
-; RV32I-NEXT: lui s11, 262144
-; RV32I-NEXT: and s11, a5, s11
-; RV32I-NEXT: andi a5, a5, 1
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: and a5, a5, a4
-; RV32I-NEXT: slli a4, a4, 30
-; RV32I-NEXT: seqz s11, s11
-; RV32I-NEXT: addi s11, s11, -1
-; RV32I-NEXT: and a4, s11, a4
+; RV32I-NEXT: slli s10, a5, 25
+; RV32I-NEXT: and s8, s8, s10
+; RV32I-NEXT: lui s10, 16384
+; RV32I-NEXT: and s10, s0, s10
+; RV32I-NEXT: seqz s10, s10
+; RV32I-NEXT: addi s10, s10, -1
+; RV32I-NEXT: slli ra, a5, 26
+; RV32I-NEXT: and s10, s10, ra
+; RV32I-NEXT: lui ra, 32768
+; RV32I-NEXT: and ra, s0, ra
+; RV32I-NEXT: seqz ra, ra
+; RV32I-NEXT: addi ra, ra, -1
+; RV32I-NEXT: slli t1, a5, 27
+; RV32I-NEXT: and t1, ra, t1
+; RV32I-NEXT: lui ra, 65536
+; RV32I-NEXT: and ra, s0, ra
+; RV32I-NEXT: seqz ra, ra
+; RV32I-NEXT: addi ra, ra, -1
+; RV32I-NEXT: slli a3, a5, 28
+; RV32I-NEXT: and a3, ra, a3
+; RV32I-NEXT: lui ra, 131072
+; RV32I-NEXT: and ra, s0, ra
+; RV32I-NEXT: seqz ra, ra
+; RV32I-NEXT: addi ra, ra, -1
+; RV32I-NEXT: slli a4, a5, 29
+; RV32I-NEXT: and a4, ra, a4
+; RV32I-NEXT: lui ra, 262144
+; RV32I-NEXT: and ra, s0, ra
+; RV32I-NEXT: andi s0, s0, 1
+; RV32I-NEXT: seqz s0, s0
+; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: and s0, s0, a5
+; RV32I-NEXT: slli a5, a5, 30
+; RV32I-NEXT: seqz ra, ra
+; RV32I-NEXT: addi ra, ra, -1
+; RV32I-NEXT: and a5, ra, a5
+; RV32I-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s0, s0, a0
; RV32I-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a5, a5, a0
-; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s11, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s11, a0, s11
-; RV32I-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s6, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, s6
-; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s5, s6, s5
-; RV32I-NEXT: xor s4, s4, ra
-; RV32I-NEXT: xor a7, t0, a7
-; RV32I-NEXT: xor a2, a6, a2
-; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: xor a4, a5, s11
-; RV32I-NEXT: lw a5, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a5
-; RV32I-NEXT: xor a5, s5, s10
-; RV32I-NEXT: xor a6, s4, t5
-; RV32I-NEXT: xor a7, a7, t3
-; RV32I-NEXT: xor a2, a2, s2
-; RV32I-NEXT: lw t0, 32(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a3, a3, t0
-; RV32I-NEXT: xor a0, a4, a0
-; RV32I-NEXT: lw a4, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a4, a5, a4
-; RV32I-NEXT: xor a5, a6, s1
-; RV32I-NEXT: xor a6, a7, t2
-; RV32I-NEXT: xor a2, a2, s7
+; RV32I-NEXT: lw ra, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor ra, a0, ra
+; RV32I-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a0, a0, s9
+; RV32I-NEXT: lw s9, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s11, s9, s11
+; RV32I-NEXT: xor s2, s7, s2
+; RV32I-NEXT: xor t5, s1, t5
+; RV32I-NEXT: xor a1, a6, a1
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: xor a5, s0, ra
+; RV32I-NEXT: lw a6, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a0, a0, a6
+; RV32I-NEXT: lw a6, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a6, s11, a6
+; RV32I-NEXT: xor s0, s2, s4
+; RV32I-NEXT: xor t3, t5, t3
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: lw a2, 36(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a4, a2
+; RV32I-NEXT: xor a0, a5, a0
+; RV32I-NEXT: lw a4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a4, a6, a4
+; RV32I-NEXT: xor a5, s0, s6
+; RV32I-NEXT: xor a6, t3, t2
+; RV32I-NEXT: xor a1, a1, s8
; RV32I-NEXT: xor a0, a0, a4
-; RV32I-NEXT: xor a5, a5, s0
-; RV32I-NEXT: xor a4, a6, t4
-; RV32I-NEXT: xor a2, a2, s8
-; RV32I-NEXT: xor a0, a0, a5
-; RV32I-NEXT: xor a4, a4, t6
-; RV32I-NEXT: xor a2, a2, s9
+; RV32I-NEXT: xor a4, a5, s5
+; RV32I-NEXT: xor a5, a6, t4
+; RV32I-NEXT: xor a1, a1, s10
; RV32I-NEXT: xor a0, a0, a4
-; RV32I-NEXT: xor a1, a2, a1
+; RV32I-NEXT: xor a4, a5, t6
+; RV32I-NEXT: xor a1, a1, t1
+; RV32I-NEXT: xor a0, a0, a4
+; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a0, a0, a3
+; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: srli a2, a0, 24
; RV32I-NEXT: slli a3, a0, 24
-; RV32I-NEXT: and a0, a0, t1
-; RV32I-NEXT: and a1, a1, t1
+; RV32I-NEXT: and a0, a0, a7
+; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: slli a0, a0, 8
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 4
-; RV32I-NEXT: and a0, a0, s3
-; RV32I-NEXT: and a1, a1, s3
+; RV32I-NEXT: and a0, a0, t0
+; RV32I-NEXT: and a1, a1, t0
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 2
-; RV32I-NEXT: lw a2, 40(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: and a0, a0, s3
+; RV32I-NEXT: and a1, a1, s3
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1
-; RV32I-NEXT: lw a2, 36(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: slli a0, a0, 1
@@ -1880,87 +1880,87 @@ define i32 @clmulr_i32(i32 %a, i32 %b) nounwind {
; RV32IMZBS-NEXT: slli a0, a0, 2
; RV32IMZBS-NEXT: and a7, a7, a4
; RV32IMZBS-NEXT: slli a1, a1, 2
-; RV32IMZBS-NEXT: or a0, a2, a0
+; RV32IMZBS-NEXT: or a2, a2, a0
; RV32IMZBS-NEXT: or a1, a7, a1
-; RV32IMZBS-NEXT: srli a2, a0, 1
+; RV32IMZBS-NEXT: srli a0, a2, 1
; RV32IMZBS-NEXT: sw a3, 28(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a0, a0, a3
+; RV32IMZBS-NEXT: and a2, a2, a3
; RV32IMZBS-NEXT: srli a7, a1, 1
-; RV32IMZBS-NEXT: and a1, a1, a3
-; RV32IMZBS-NEXT: and t0, a2, a3
-; RV32IMZBS-NEXT: slli a0, a0, 1
+; RV32IMZBS-NEXT: and t0, a1, a3
+; RV32IMZBS-NEXT: and a1, a0, a3
+; RV32IMZBS-NEXT: slli a2, a2, 1
; RV32IMZBS-NEXT: and a3, a7, a3
-; RV32IMZBS-NEXT: slli a2, a1, 1
-; RV32IMZBS-NEXT: or s9, t0, a0
-; RV32IMZBS-NEXT: or a1, a3, a2
-; RV32IMZBS-NEXT: srli a2, a2, 31
-; RV32IMZBS-NEXT: slli a0, s9, 1
-; RV32IMZBS-NEXT: andi t0, a1, 2
-; RV32IMZBS-NEXT: slli t2, s9, 2
-; RV32IMZBS-NEXT: andi t3, a1, 4
-; RV32IMZBS-NEXT: slli t4, s9, 3
-; RV32IMZBS-NEXT: andi t5, a1, 8
-; RV32IMZBS-NEXT: slli t6, s9, 4
-; RV32IMZBS-NEXT: andi s0, a1, 16
-; RV32IMZBS-NEXT: slli a7, s9, 5
-; RV32IMZBS-NEXT: andi s2, a1, 32
-; RV32IMZBS-NEXT: slli s3, s9, 6
-; RV32IMZBS-NEXT: andi s4, a1, 64
-; RV32IMZBS-NEXT: slli s5, s9, 7
-; RV32IMZBS-NEXT: andi s6, a1, 128
-; RV32IMZBS-NEXT: slli s1, s9, 8
-; RV32IMZBS-NEXT: andi s7, a1, 256
-; RV32IMZBS-NEXT: slli s8, s9, 9
-; RV32IMZBS-NEXT: andi s10, a1, 512
-; RV32IMZBS-NEXT: slli s11, s9, 10
-; RV32IMZBS-NEXT: andi ra, a1, 1024
-; RV32IMZBS-NEXT: slli t1, s9, 31
+; RV32IMZBS-NEXT: slli t0, t0, 1
+; RV32IMZBS-NEXT: slli t1, a0, 31
+; RV32IMZBS-NEXT: or s8, a1, a2
+; RV32IMZBS-NEXT: or s0, a3, t0
+; RV32IMZBS-NEXT: srli a2, t0, 31
+; RV32IMZBS-NEXT: slli a1, s8, 1
+; RV32IMZBS-NEXT: andi t0, s0, 2
+; RV32IMZBS-NEXT: slli t2, s8, 2
+; RV32IMZBS-NEXT: andi t3, s0, 4
+; RV32IMZBS-NEXT: slli t4, s8, 3
+; RV32IMZBS-NEXT: andi t5, s0, 8
+; RV32IMZBS-NEXT: slli t6, s8, 4
+; RV32IMZBS-NEXT: andi a0, s0, 16
+; RV32IMZBS-NEXT: slli a7, s8, 5
+; RV32IMZBS-NEXT: andi s2, s0, 32
+; RV32IMZBS-NEXT: slli s3, s8, 6
+; RV32IMZBS-NEXT: andi s4, s0, 64
+; RV32IMZBS-NEXT: slli s5, s8, 7
+; RV32IMZBS-NEXT: andi s6, s0, 128
+; RV32IMZBS-NEXT: slli s1, s8, 8
+; RV32IMZBS-NEXT: andi s7, s0, 256
+; RV32IMZBS-NEXT: slli s9, s8, 9
+; RV32IMZBS-NEXT: andi s10, s0, 512
+; RV32IMZBS-NEXT: slli s11, s8, 10
+; RV32IMZBS-NEXT: andi ra, s0, 1024
; RV32IMZBS-NEXT: seqz a2, a2
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: and a2, a2, t1
; RV32IMZBS-NEXT: sw a2, 24(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, s9, 11
+; RV32IMZBS-NEXT: slli a6, s8, 11
; RV32IMZBS-NEXT: seqz t0, t0
; RV32IMZBS-NEXT: addi t0, t0, -1
-; RV32IMZBS-NEXT: and a0, t0, a0
-; RV32IMZBS-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: not t1, a1
+; RV32IMZBS-NEXT: and a1, t0, a1
+; RV32IMZBS-NEXT: sw a1, 20(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: not t1, s0
; RV32IMZBS-NEXT: seqz t0, t3
; RV32IMZBS-NEXT: addi t0, t0, -1
-; RV32IMZBS-NEXT: and a0, t0, t2
-; RV32IMZBS-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a5, s9, 12
+; RV32IMZBS-NEXT: and a1, t0, t2
+; RV32IMZBS-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a5, s8, 12
; RV32IMZBS-NEXT: seqz t2, t5
; RV32IMZBS-NEXT: addi t2, t2, -1
-; RV32IMZBS-NEXT: and a0, t2, t4
-; RV32IMZBS-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, s9, 13
-; RV32IMZBS-NEXT: seqz t3, s0
+; RV32IMZBS-NEXT: and a1, t2, t4
+; RV32IMZBS-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s8, 13
+; RV32IMZBS-NEXT: seqz t3, a0
; RV32IMZBS-NEXT: addi t3, t3, -1
; RV32IMZBS-NEXT: and a0, t3, t6
; RV32IMZBS-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a3, s9, 14
+; RV32IMZBS-NEXT: slli a3, s8, 14
; RV32IMZBS-NEXT: seqz t4, s2
; RV32IMZBS-NEXT: addi t4, t4, -1
; RV32IMZBS-NEXT: and t5, t4, a7
-; RV32IMZBS-NEXT: slli a2, s9, 15
+; RV32IMZBS-NEXT: slli a2, s8, 15
; RV32IMZBS-NEXT: seqz t4, s4
; RV32IMZBS-NEXT: addi t4, t4, -1
; RV32IMZBS-NEXT: and a0, t4, s3
; RV32IMZBS-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli s3, s9, 16
+; RV32IMZBS-NEXT: slli s3, s8, 16
; RV32IMZBS-NEXT: seqz t6, s6
; RV32IMZBS-NEXT: addi t6, t6, -1
-; RV32IMZBS-NEXT: and s0, t6, s5
-; RV32IMZBS-NEXT: slli s4, s9, 17
+; RV32IMZBS-NEXT: and t4, t6, s5
+; RV32IMZBS-NEXT: slli s4, s8, 17
; RV32IMZBS-NEXT: seqz t6, s7
; RV32IMZBS-NEXT: addi t6, t6, -1
; RV32IMZBS-NEXT: and s2, t6, s1
-; RV32IMZBS-NEXT: slli a0, s9, 18
+; RV32IMZBS-NEXT: slli a0, s8, 18
; RV32IMZBS-NEXT: seqz t6, s10
; RV32IMZBS-NEXT: addi t6, t6, -1
-; RV32IMZBS-NEXT: and t4, t6, s8
-; RV32IMZBS-NEXT: slli a7, s9, 19
+; RV32IMZBS-NEXT: and t3, t6, s9
+; RV32IMZBS-NEXT: slli s9, s8, 19
; RV32IMZBS-NEXT: seqz t6, ra
; RV32IMZBS-NEXT: addi t6, t6, -1
; RV32IMZBS-NEXT: and t6, t6, s11
@@ -1975,10 +1975,10 @@ define i32 @clmulr_i32(i32 %a, i32 %b) nounwind {
; RV32IMZBS-NEXT: and s5, a5, a4
; RV32IMZBS-NEXT: bexti a4, t1, 14
; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: and t2, a4, a3
+; RV32IMZBS-NEXT: and a4, a4, a3
; RV32IMZBS-NEXT: bexti a3, t1, 15
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: and t3, a3, a2
+; RV32IMZBS-NEXT: and t2, a3, a2
; RV32IMZBS-NEXT: bexti a2, t1, 16
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: and ra, a2, s3
@@ -1990,90 +1990,90 @@ define i32 @clmulr_i32(i32 %a, i32 %b) nounwind {
; RV32IMZBS-NEXT: and s11, a5, a0
; RV32IMZBS-NEXT: bexti a5, t1, 19
; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: and a3, a5, a7
+; RV32IMZBS-NEXT: and a3, a5, s9
; RV32IMZBS-NEXT: bexti a5, t1, 20
; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, s9, 20
-; RV32IMZBS-NEXT: and a4, a5, a6
+; RV32IMZBS-NEXT: slli a6, s8, 20
+; RV32IMZBS-NEXT: and s9, a5, a6
; RV32IMZBS-NEXT: bexti a5, t1, 21
; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, s9, 21
+; RV32IMZBS-NEXT: slli a6, s8, 21
; RV32IMZBS-NEXT: and s10, a5, a6
; RV32IMZBS-NEXT: bexti a5, t1, 22
; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: slli a6, s9, 22
+; RV32IMZBS-NEXT: slli a6, s8, 22
; RV32IMZBS-NEXT: and a5, a5, a6
; RV32IMZBS-NEXT: bexti a6, t1, 23
; RV32IMZBS-NEXT: addi a6, a6, -1
-; RV32IMZBS-NEXT: slli s3, s9, 23
+; RV32IMZBS-NEXT: slli s3, s8, 23
; RV32IMZBS-NEXT: and a6, a6, s3
; RV32IMZBS-NEXT: bexti s3, t1, 24
; RV32IMZBS-NEXT: addi s3, s3, -1
-; RV32IMZBS-NEXT: slli s4, s9, 24
+; RV32IMZBS-NEXT: slli s4, s8, 24
; RV32IMZBS-NEXT: and s3, s3, s4
; RV32IMZBS-NEXT: bexti s4, t1, 25
; RV32IMZBS-NEXT: addi s4, s4, -1
-; RV32IMZBS-NEXT: slli a0, s9, 25
+; RV32IMZBS-NEXT: slli a0, s8, 25
; RV32IMZBS-NEXT: and a0, s4, a0
; RV32IMZBS-NEXT: bexti s4, t1, 26
; RV32IMZBS-NEXT: addi s4, s4, -1
-; RV32IMZBS-NEXT: slli a7, s9, 26
-; RV32IMZBS-NEXT: and a7, s4, a7
+; RV32IMZBS-NEXT: slli a1, s8, 26
+; RV32IMZBS-NEXT: and a1, s4, a1
; RV32IMZBS-NEXT: bexti s4, t1, 27
; RV32IMZBS-NEXT: addi s4, s4, -1
-; RV32IMZBS-NEXT: slli s1, s9, 27
-; RV32IMZBS-NEXT: and s1, s4, s1
+; RV32IMZBS-NEXT: slli a7, s8, 27
+; RV32IMZBS-NEXT: and a7, s4, a7
; RV32IMZBS-NEXT: bexti s4, t1, 28
; RV32IMZBS-NEXT: addi s4, s4, -1
-; RV32IMZBS-NEXT: slli s7, s9, 28
+; RV32IMZBS-NEXT: slli s1, s8, 28
+; RV32IMZBS-NEXT: and s1, s4, s1
+; RV32IMZBS-NEXT: bexti s4, t1, 29
+; RV32IMZBS-NEXT: addi s4, s4, -1
+; RV32IMZBS-NEXT: slli s7, s8, 29
; RV32IMZBS-NEXT: and s4, s4, s7
-; RV32IMZBS-NEXT: bexti s7, t1, 29
-; RV32IMZBS-NEXT: addi s7, s7, -1
-; RV32IMZBS-NEXT: slli s8, s9, 29
-; RV32IMZBS-NEXT: and s7, s7, s8
-; RV32IMZBS-NEXT: andi a1, a1, 1
-; RV32IMZBS-NEXT: seqz a1, a1
-; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: and a1, a1, s9
-; RV32IMZBS-NEXT: slli s9, s9, 30
+; RV32IMZBS-NEXT: andi s0, s0, 1
+; RV32IMZBS-NEXT: seqz s0, s0
+; RV32IMZBS-NEXT: addi s0, s0, -1
+; RV32IMZBS-NEXT: and s0, s0, s8
+; RV32IMZBS-NEXT: slli s8, s8, 30
; RV32IMZBS-NEXT: bexti t1, t1, 30
; RV32IMZBS-NEXT: addi t1, t1, -1
-; RV32IMZBS-NEXT: and t1, t1, s9
-; RV32IMZBS-NEXT: lw s8, 20(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a1, a1, s8
-; RV32IMZBS-NEXT: lw s8, 16(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 12(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s8, s8, s9
-; RV32IMZBS-NEXT: lw s9, 8(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t5, s9, t5
-; RV32IMZBS-NEXT: xor s0, s0, s2
+; RV32IMZBS-NEXT: and t1, t1, s8
+; RV32IMZBS-NEXT: lw s7, 20(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s0, s0, s7
+; RV32IMZBS-NEXT: lw s7, 16(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 12(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s7, s8
+; RV32IMZBS-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor t5, s8, t5
+; RV32IMZBS-NEXT: xor t4, t4, s2
; RV32IMZBS-NEXT: xor t0, s6, t0
; RV32IMZBS-NEXT: xor a2, ra, a2
; RV32IMZBS-NEXT: xor a5, a5, a6
-; RV32IMZBS-NEXT: xor a6, s7, t1
-; RV32IMZBS-NEXT: xor a1, a1, s8
-; RV32IMZBS-NEXT: lw t1, 4(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t1, t5, t1
-; RV32IMZBS-NEXT: xor t4, s0, t4
+; RV32IMZBS-NEXT: xor a6, s4, t1
+; RV32IMZBS-NEXT: xor t1, s0, s7
+; RV32IMZBS-NEXT: lw s0, 4(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor t5, t5, s0
+; RV32IMZBS-NEXT: xor t3, t4, t3
; RV32IMZBS-NEXT: xor t0, t0, s5
; RV32IMZBS-NEXT: xor a2, a2, s11
; RV32IMZBS-NEXT: xor a5, a5, s3
-; RV32IMZBS-NEXT: lw t5, 24(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a6, a6, t5
-; RV32IMZBS-NEXT: xor a1, a1, t1
-; RV32IMZBS-NEXT: xor t1, t4, t6
-; RV32IMZBS-NEXT: xor t0, t0, t2
+; RV32IMZBS-NEXT: lw t4, 24(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a6, a6, t4
+; RV32IMZBS-NEXT: xor t1, t1, t5
+; RV32IMZBS-NEXT: xor t3, t3, t6
+; RV32IMZBS-NEXT: xor a4, t0, a4
; RV32IMZBS-NEXT: xor a2, a2, a3
; RV32IMZBS-NEXT: xor a0, a5, a0
-; RV32IMZBS-NEXT: xor a1, a1, t1
-; RV32IMZBS-NEXT: xor a3, t0, t3
-; RV32IMZBS-NEXT: xor a2, a2, a4
+; RV32IMZBS-NEXT: xor a3, t1, t3
+; RV32IMZBS-NEXT: xor a4, a4, t2
+; RV32IMZBS-NEXT: xor a2, a2, s9
+; RV32IMZBS-NEXT: xor a0, a0, a1
+; RV32IMZBS-NEXT: xor a3, a3, a4
+; RV32IMZBS-NEXT: xor a1, a2, s10
; RV32IMZBS-NEXT: xor a0, a0, a7
-; RV32IMZBS-NEXT: xor a1, a1, a3
-; RV32IMZBS-NEXT: xor a2, a2, s10
+; RV32IMZBS-NEXT: xor a1, a3, a1
; RV32IMZBS-NEXT: xor a0, a0, s1
-; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: xor a0, a0, s4
; RV32IMZBS-NEXT: xor a0, a1, a0
; RV32IMZBS-NEXT: xor a0, a0, a6
; RV32IMZBS-NEXT: srli a1, a0, 8
@@ -2766,112 +2766,112 @@ define void @mul_use_commutative_clmul_i8(i8 %x, i8 %y, ptr %p0, ptr %p1) nounwi
define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p1) nounwind {
; RV32I-LABEL: commutative_clmulr_v2i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -800
-; RV32I-NEXT: sw ra, 796(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 792(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 788(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 784(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s3, 780(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s4, 776(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s5, 772(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s6, 768(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s7, 764(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s8, 760(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s9, 756(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s10, 752(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s11, 748(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw a3, 736(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw a2, 732(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi sp, sp, -816
+; RV32I-NEXT: sw ra, 812(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 808(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 804(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 800(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 796(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 792(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s5, 788(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s6, 784(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s7, 780(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s8, 776(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s9, 772(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s10, 768(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s11, 764(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a3, 748(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 744(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a2, 0(a0)
-; RV32I-NEXT: lw a4, 4(a0)
-; RV32I-NEXT: lw t0, 8(a0)
+; RV32I-NEXT: lw t4, 4(a0)
+; RV32I-NEXT: lw a4, 8(a0)
; RV32I-NEXT: lw a0, 12(a0)
; RV32I-NEXT: lw s7, 0(a1)
; RV32I-NEXT: lw t2, 4(a1)
-; RV32I-NEXT: lw t1, 8(a1)
+; RV32I-NEXT: lw a6, 8(a1)
; RV32I-NEXT: lw a1, 12(a1)
-; RV32I-NEXT: lui a7, 16
+; RV32I-NEXT: lui t0, 16
; RV32I-NEXT: lui a3, 61681
; RV32I-NEXT: lui a5, 209715
-; RV32I-NEXT: lui a6, 349525
-; RV32I-NEXT: addi ra, a7, -256
+; RV32I-NEXT: lui a7, 349525
+; RV32I-NEXT: addi ra, t0, -256
; RV32I-NEXT: addi s11, a3, -241
; RV32I-NEXT: addi s10, a5, 819
-; RV32I-NEXT: addi s9, a6, 1365
-; RV32I-NEXT: srli a7, t2, 8
-; RV32I-NEXT: srli t4, t2, 24
+; RV32I-NEXT: addi s9, a7, 1365
+; RV32I-NEXT: srli t5, t2, 8
+; RV32I-NEXT: srli s3, t2, 24
; RV32I-NEXT: and a3, t2, ra
; RV32I-NEXT: slli t2, t2, 24
-; RV32I-NEXT: srli a5, a4, 8
-; RV32I-NEXT: srli s3, a4, 24
-; RV32I-NEXT: and t3, a4, ra
-; RV32I-NEXT: slli a4, a4, 24
-; RV32I-NEXT: srli t5, s7, 8
-; RV32I-NEXT: srli s6, s7, 24
-; RV32I-NEXT: and s1, s7, ra
+; RV32I-NEXT: srli a7, t4, 8
+; RV32I-NEXT: srli s4, t4, 24
+; RV32I-NEXT: and t3, t4, ra
+; RV32I-NEXT: slli t4, t4, 24
+; RV32I-NEXT: srli t6, s7, 8
+; RV32I-NEXT: srli s1, s7, 24
+; RV32I-NEXT: and s0, s7, ra
; RV32I-NEXT: slli s7, s7, 24
; RV32I-NEXT: srli s8, a2, 8
-; RV32I-NEXT: srli t6, a2, 24
-; RV32I-NEXT: and s0, a2, ra
-; RV32I-NEXT: slli a6, a2, 24
-; RV32I-NEXT: and a2, a7, ra
-; RV32I-NEXT: or a2, a2, t4
+; RV32I-NEXT: srli t0, a2, 24
+; RV32I-NEXT: and a5, a2, ra
+; RV32I-NEXT: slli t1, a2, 24
+; RV32I-NEXT: and a2, t5, ra
+; RV32I-NEXT: or a2, a2, s3
; RV32I-NEXT: srli s2, a1, 8
; RV32I-NEXT: slli a3, a3, 8
; RV32I-NEXT: or a3, t2, a3
-; RV32I-NEXT: srli s4, a1, 24
-; RV32I-NEXT: and a5, a5, ra
-; RV32I-NEXT: or t2, a5, s3
-; RV32I-NEXT: and s3, a1, ra
-; RV32I-NEXT: slli s5, a1, 24
-; RV32I-NEXT: slli a1, t3, 8
-; RV32I-NEXT: or a1, a4, a1
-; RV32I-NEXT: srli a5, a0, 8
-; RV32I-NEXT: and a4, t5, ra
-; RV32I-NEXT: or t3, a4, s6
-; RV32I-NEXT: srli t5, a0, 24
-; RV32I-NEXT: slli s1, s1, 8
-; RV32I-NEXT: or a4, s7, s1
-; RV32I-NEXT: and a7, a0, ra
-; RV32I-NEXT: slli t4, a0, 24
-; RV32I-NEXT: and a0, s8, ra
-; RV32I-NEXT: or a0, a0, t6
-; RV32I-NEXT: srli s1, t1, 8
+; RV32I-NEXT: srli s5, a1, 24
+; RV32I-NEXT: and a7, a7, ra
+; RV32I-NEXT: or t2, a7, s4
+; RV32I-NEXT: and s4, a1, ra
+; RV32I-NEXT: slli s6, a1, 24
+; RV32I-NEXT: slli t3, t3, 8
+; RV32I-NEXT: or a1, t4, t3
+; RV32I-NEXT: srli a7, a0, 8
+; RV32I-NEXT: and t3, t6, ra
+; RV32I-NEXT: or t3, t3, s1
+; RV32I-NEXT: srli t6, a0, 24
; RV32I-NEXT: slli s0, s0, 8
-; RV32I-NEXT: or t6, a6, s0
-; RV32I-NEXT: srli a6, t1, 24
-; RV32I-NEXT: and s0, s2, ra
-; RV32I-NEXT: or s0, s0, s4
-; RV32I-NEXT: and s7, t1, ra
-; RV32I-NEXT: slli s6, t1, 24
-; RV32I-NEXT: slli s3, s3, 8
-; RV32I-NEXT: or t1, s5, s3
-; RV32I-NEXT: srli s2, t0, 8
-; RV32I-NEXT: and a5, a5, ra
-; RV32I-NEXT: or a5, a5, t5
-; RV32I-NEXT: srli t5, t0, 24
-; RV32I-NEXT: slli a7, a7, 8
-; RV32I-NEXT: or a7, t4, a7
-; RV32I-NEXT: and t4, t0, ra
-; RV32I-NEXT: slli t0, t0, 24
-; RV32I-NEXT: and s1, s1, ra
+; RV32I-NEXT: or t4, s7, s0
+; RV32I-NEXT: and t5, a0, ra
+; RV32I-NEXT: slli s3, a0, 24
+; RV32I-NEXT: and a0, s8, ra
+; RV32I-NEXT: or a0, a0, t0
+; RV32I-NEXT: srli s0, a6, 8
+; RV32I-NEXT: slli a5, a5, 8
+; RV32I-NEXT: or t0, t1, a5
+; RV32I-NEXT: srli t1, a6, 24
+; RV32I-NEXT: and a5, s2, ra
+; RV32I-NEXT: or a5, a5, s5
+; RV32I-NEXT: and s7, a6, ra
+; RV32I-NEXT: slli s1, a6, 24
+; RV32I-NEXT: slli s4, s4, 8
+; RV32I-NEXT: or a6, s6, s4
+; RV32I-NEXT: srli s2, a4, 8
+; RV32I-NEXT: and a7, a7, ra
+; RV32I-NEXT: or a7, a7, t6
+; RV32I-NEXT: srli t6, a4, 24
+; RV32I-NEXT: slli t5, t5, 8
+; RV32I-NEXT: or t5, s3, t5
+; RV32I-NEXT: and s3, a4, ra
+; RV32I-NEXT: slli a4, a4, 24
+; RV32I-NEXT: and s0, s0, ra
; RV32I-NEXT: slli s7, s7, 8
; RV32I-NEXT: and s2, s2, ra
-; RV32I-NEXT: slli t4, t4, 8
-; RV32I-NEXT: or a6, s1, a6
-; RV32I-NEXT: or s1, s6, s7
-; RV32I-NEXT: or t5, s2, t5
-; RV32I-NEXT: or t0, t0, t4
+; RV32I-NEXT: slli s3, s3, 8
+; RV32I-NEXT: or t1, s0, t1
+; RV32I-NEXT: or s0, s1, s7
+; RV32I-NEXT: or t6, s2, t6
+; RV32I-NEXT: or a4, a4, s3
; RV32I-NEXT: or a2, a3, a2
; RV32I-NEXT: or a1, a1, t2
-; RV32I-NEXT: or a3, a4, t3
-; RV32I-NEXT: or a0, t6, a0
-; RV32I-NEXT: or a4, t1, s0
-; RV32I-NEXT: or a5, a7, a5
-; RV32I-NEXT: or a6, s1, a6
-; RV32I-NEXT: or a7, t0, t5
+; RV32I-NEXT: or a3, t4, t3
+; RV32I-NEXT: or a0, t0, a0
+; RV32I-NEXT: or a5, a6, a5
+; RV32I-NEXT: or a6, t5, a7
+; RV32I-NEXT: or a7, s0, t1
+; RV32I-NEXT: or a4, a4, t6
; RV32I-NEXT: srli t0, a2, 4
-; RV32I-NEXT: sw s11, 744(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s11, 760(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, s11
; RV32I-NEXT: srli t1, a1, 4
; RV32I-NEXT: and a1, a1, s11
@@ -2879,14 +2879,14 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: and a3, a3, s11
; RV32I-NEXT: srli t3, a0, 4
; RV32I-NEXT: and a0, a0, s11
-; RV32I-NEXT: srli t4, a4, 4
-; RV32I-NEXT: and a4, a4, s11
-; RV32I-NEXT: srli t5, a5, 4
+; RV32I-NEXT: srli t4, a5, 4
; RV32I-NEXT: and a5, a5, s11
-; RV32I-NEXT: srli t6, a6, 4
+; RV32I-NEXT: srli t5, a6, 4
; RV32I-NEXT: and a6, a6, s11
-; RV32I-NEXT: srli s0, a7, 4
+; RV32I-NEXT: srli t6, a7, 4
; RV32I-NEXT: and a7, a7, s11
+; RV32I-NEXT: srli s0, a4, 4
+; RV32I-NEXT: and a4, a4, s11
; RV32I-NEXT: and t0, t0, s11
; RV32I-NEXT: slli a2, a2, 4
; RV32I-NEXT: and t1, t1, s11
@@ -2896,23 +2896,23 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: and t3, t3, s11
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: and t4, t4, s11
-; RV32I-NEXT: slli a4, a4, 4
-; RV32I-NEXT: and t5, t5, s11
; RV32I-NEXT: slli a5, a5, 4
-; RV32I-NEXT: and t6, t6, s11
+; RV32I-NEXT: and t5, t5, s11
; RV32I-NEXT: slli a6, a6, 4
-; RV32I-NEXT: and s0, s0, s11
+; RV32I-NEXT: and t6, t6, s11
; RV32I-NEXT: slli a7, a7, 4
+; RV32I-NEXT: and s0, s0, s11
+; RV32I-NEXT: slli a4, a4, 4
; RV32I-NEXT: or a2, t0, a2
; RV32I-NEXT: or a1, t1, a1
; RV32I-NEXT: or a3, t2, a3
; RV32I-NEXT: or a0, t3, a0
-; RV32I-NEXT: or a4, t4, a4
-; RV32I-NEXT: or a5, t5, a5
-; RV32I-NEXT: or a6, t6, a6
-; RV32I-NEXT: or a7, s0, a7
+; RV32I-NEXT: or a5, t4, a5
+; RV32I-NEXT: or a6, t5, a6
+; RV32I-NEXT: or a7, t6, a7
+; RV32I-NEXT: or a4, s0, a4
; RV32I-NEXT: srli t0, a2, 2
-; RV32I-NEXT: sw s10, 724(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s10, 740(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, s10
; RV32I-NEXT: srli t1, a1, 2
; RV32I-NEXT: and a1, a1, s10
@@ -2920,14 +2920,14 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: and a3, a3, s10
; RV32I-NEXT: srli t3, a0, 2
; RV32I-NEXT: and a0, a0, s10
-; RV32I-NEXT: srli t4, a4, 2
-; RV32I-NEXT: and a4, a4, s10
-; RV32I-NEXT: srli t5, a5, 2
+; RV32I-NEXT: srli t4, a5, 2
; RV32I-NEXT: and a5, a5, s10
-; RV32I-NEXT: srli t6, a6, 2
+; RV32I-NEXT: srli t5, a6, 2
; RV32I-NEXT: and a6, a6, s10
-; RV32I-NEXT: srli s0, a7, 2
+; RV32I-NEXT: srli t6, a7, 2
; RV32I-NEXT: and a7, a7, s10
+; RV32I-NEXT: srli s0, a4, 2
+; RV32I-NEXT: and a4, a4, s10
; RV32I-NEXT: and t0, t0, s10
; RV32I-NEXT: slli a2, a2, 2
; RV32I-NEXT: and t1, t1, s10
@@ -2937,1900 +2937,1900 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: and t3, t3, s10
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: and t4, t4, s10
-; RV32I-NEXT: slli a4, a4, 2
-; RV32I-NEXT: and t5, t5, s10
; RV32I-NEXT: slli a5, a5, 2
-; RV32I-NEXT: and t6, t6, s10
+; RV32I-NEXT: and t5, t5, s10
; RV32I-NEXT: slli a6, a6, 2
-; RV32I-NEXT: and s0, s0, s10
+; RV32I-NEXT: and t6, t6, s10
; RV32I-NEXT: slli a7, a7, 2
-; RV32I-NEXT: or a2, t0, a2
+; RV32I-NEXT: and s0, s0, s10
+; RV32I-NEXT: slli a4, a4, 2
+; RV32I-NEXT: or t0, t0, a2
; RV32I-NEXT: or a1, t1, a1
; RV32I-NEXT: or a3, t2, a3
-; RV32I-NEXT: or a0, t3, a0
-; RV32I-NEXT: or a4, t4, a4
-; RV32I-NEXT: or a5, t5, a5
-; RV32I-NEXT: or a6, t6, a6
-; RV32I-NEXT: or a7, s0, a7
-; RV32I-NEXT: srli t0, a2, 1
-; RV32I-NEXT: sw s9, 728(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a2, a2, s9
-; RV32I-NEXT: srli t1, a1, 1
+; RV32I-NEXT: or a2, t3, a0
+; RV32I-NEXT: or a0, t4, a5
+; RV32I-NEXT: or a5, t5, a6
+; RV32I-NEXT: or a6, t6, a7
+; RV32I-NEXT: or a4, s0, a4
+; RV32I-NEXT: srli s1, t0, 1
+; RV32I-NEXT: and a7, t0, s9
+; RV32I-NEXT: srli t0, a1, 1
; RV32I-NEXT: and a1, a1, s9
-; RV32I-NEXT: srli t2, a3, 1
+; RV32I-NEXT: srli s2, a3, 1
; RV32I-NEXT: and a3, a3, s9
-; RV32I-NEXT: srli t3, a0, 1
+; RV32I-NEXT: srli s3, a0, 1
; RV32I-NEXT: and a0, a0, s9
-; RV32I-NEXT: srli t4, a4, 1
-; RV32I-NEXT: and a4, a4, s9
-; RV32I-NEXT: srli t5, a5, 1
-; RV32I-NEXT: and a5, a5, s9
+; RV32I-NEXT: srli t1, a5, 1
+; RV32I-NEXT: and s0, a5, s9
; RV32I-NEXT: srli t6, a6, 1
-; RV32I-NEXT: and a6, a6, s9
-; RV32I-NEXT: srli s0, a7, 1
-; RV32I-NEXT: and a7, a7, s9
+; RV32I-NEXT: and a5, a6, s9
+; RV32I-NEXT: and a6, s1, s9
+; RV32I-NEXT: slli a7, a7, 1
; RV32I-NEXT: and t0, t0, s9
-; RV32I-NEXT: slli a2, a2, 1
-; RV32I-NEXT: and t1, t1, s9
-; RV32I-NEXT: slli s1, a1, 1
-; RV32I-NEXT: and t2, t2, s9
+; RV32I-NEXT: slli s4, a1, 1
+; RV32I-NEXT: and t2, s2, s9
; RV32I-NEXT: slli a3, a3, 1
-; RV32I-NEXT: and t3, t3, s9
-; RV32I-NEXT: slli s2, a0, 1
-; RV32I-NEXT: and t4, t4, s9
-; RV32I-NEXT: slli a4, a4, 1
-; RV32I-NEXT: and t5, t5, s9
-; RV32I-NEXT: slli s3, a5, 1
-; RV32I-NEXT: and s4, t6, s9
-; RV32I-NEXT: slli a6, a6, 1
-; RV32I-NEXT: and s5, s0, s9
-; RV32I-NEXT: slli s0, a7, 1
-; RV32I-NEXT: or a0, t0, a2
-; RV32I-NEXT: or a1, t1, s1
-; RV32I-NEXT: or a2, t2, a3
-; RV32I-NEXT: srli t6, s1, 31
-; RV32I-NEXT: or a3, t3, s2
-; RV32I-NEXT: srli a5, s2, 31
-; RV32I-NEXT: or t0, t4, a4
-; RV32I-NEXT: or t3, t5, s3
-; RV32I-NEXT: or t1, s4, a6
-; RV32I-NEXT: srli a4, s3, 31
-; RV32I-NEXT: or s6, s5, s0
-; RV32I-NEXT: srli t2, s0, 31
-; RV32I-NEXT: srli a6, a0, 8
-; RV32I-NEXT: srli a7, a0, 24
-; RV32I-NEXT: srli t4, a1, 8
-; RV32I-NEXT: srli t5, a1, 24
-; RV32I-NEXT: slli s1, a1, 24
-; RV32I-NEXT: and s2, a1, ra
-; RV32I-NEXT: slli s3, a2, 31
-; RV32I-NEXT: seqz s4, t6
-; RV32I-NEXT: srli t6, t0, 8
-; RV32I-NEXT: and a6, a6, ra
-; RV32I-NEXT: or s0, a6, a7
-; RV32I-NEXT: srli a7, t0, 24
-; RV32I-NEXT: and a6, t4, ra
-; RV32I-NEXT: or a6, a6, t5
-; RV32I-NEXT: srli t5, t3, 8
-; RV32I-NEXT: slli s2, s2, 8
-; RV32I-NEXT: or t4, s1, s2
-; RV32I-NEXT: srli s1, t3, 24
-; RV32I-NEXT: and t6, t6, ra
-; RV32I-NEXT: or a7, t6, a7
-; RV32I-NEXT: slli t6, t3, 24
-; RV32I-NEXT: and t5, t5, ra
-; RV32I-NEXT: or t5, t5, s1
-; RV32I-NEXT: and s1, t3, ra
-; RV32I-NEXT: slli s1, s1, 8
-; RV32I-NEXT: or s1, t6, s1
-; RV32I-NEXT: slli t6, a0, 31
-; RV32I-NEXT: seqz s2, a5
-; RV32I-NEXT: addi a5, s4, -1
-; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: and s3, a5, s3
-; RV32I-NEXT: sw s3, 716(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and s2, s2, t6
-; RV32I-NEXT: sw s2, 720(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a5, t6
-; RV32I-NEXT: sw a5, 712(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, t1, 31
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: seqz t6, t2
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and t3, s3, s9
+; RV32I-NEXT: slli t4, a0, 1
+; RV32I-NEXT: and t1, t1, s9
+; RV32I-NEXT: slli s0, s0, 1
+; RV32I-NEXT: and t5, t6, s9
+; RV32I-NEXT: slli a5, a5, 1
+; RV32I-NEXT: or a1, a6, a7
+; RV32I-NEXT: or a0, t0, s4
+; RV32I-NEXT: or a3, t2, a3
+; RV32I-NEXT: or t3, t3, t4
+; RV32I-NEXT: or t4, t1, s0
+; RV32I-NEXT: or s8, t5, a5
+; RV32I-NEXT: srli a5, a1, 8
+; RV32I-NEXT: srli a6, a1, 24
+; RV32I-NEXT: srli a7, a0, 8
+; RV32I-NEXT: srli t0, a0, 24
+; RV32I-NEXT: slli t1, a0, 24
+; RV32I-NEXT: and t5, a0, ra
+; RV32I-NEXT: and a5, a5, ra
+; RV32I-NEXT: or a6, a5, a6
+; RV32I-NEXT: srli s5, t3, 8
+; RV32I-NEXT: and a5, a7, ra
+; RV32I-NEXT: or a7, a5, t0
+; RV32I-NEXT: srli t0, t3, 24
+; RV32I-NEXT: slli t5, t5, 8
+; RV32I-NEXT: or a5, t1, t5
+; RV32I-NEXT: srli t1, t4, 8
+; RV32I-NEXT: and t5, s5, ra
+; RV32I-NEXT: or t5, t5, t0
+; RV32I-NEXT: srli t0, t4, 24
+; RV32I-NEXT: and t1, t1, ra
+; RV32I-NEXT: or t0, t1, t0
+; RV32I-NEXT: and t1, t4, ra
+; RV32I-NEXT: slli t1, t1, 8
+; RV32I-NEXT: slli s5, t4, 24
+; RV32I-NEXT: or t1, s5, t1
+; RV32I-NEXT: srli s5, a2, 1
+; RV32I-NEXT: and a2, a2, s9
+; RV32I-NEXT: slli s2, s2, 31
+; RV32I-NEXT: and s5, s5, s9
+; RV32I-NEXT: slli s6, a2, 1
+; RV32I-NEXT: slli s1, s1, 31
+; RV32I-NEXT: srli s4, s4, 31
+; RV32I-NEXT: or a2, s5, s6
+; RV32I-NEXT: srli s5, s6, 31
+; RV32I-NEXT: seqz s7, s4
+; RV32I-NEXT: seqz s4, s5
+; RV32I-NEXT: addi s7, s7, -1
+; RV32I-NEXT: addi s4, s4, -1
+; RV32I-NEXT: and t2, s7, s2
+; RV32I-NEXT: sw t2, 732(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t2, s4, s1
+; RV32I-NEXT: sw t2, 736(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t2, s7, s1
+; RV32I-NEXT: sw t2, 728(sp) # 4-byte Folded Spill
+; RV32I-NEXT: srli s1, a4, 1
+; RV32I-NEXT: sw s9, 756(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a4, s9
+; RV32I-NEXT: slli s2, t6, 31
+; RV32I-NEXT: and t6, s1, s9
+; RV32I-NEXT: slli s1, a4, 1
+; RV32I-NEXT: slli s3, s3, 31
+; RV32I-NEXT: srli s0, s0, 31
+; RV32I-NEXT: or t2, t6, s1
+; RV32I-NEXT: srli s1, s1, 31
+; RV32I-NEXT: seqz t6, s0
+; RV32I-NEXT: seqz s0, s1
; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: and a5, a4, a5
-; RV32I-NEXT: sw a5, 704(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, t0, 31
-; RV32I-NEXT: and t2, t6, a5
-; RV32I-NEXT: sw t2, 708(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a5
-; RV32I-NEXT: sw a4, 692(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw ra, 740(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a0, ra
-; RV32I-NEXT: slli a4, a4, 8
-; RV32I-NEXT: slli t6, a0, 24
-; RV32I-NEXT: or a4, t6, a4
-; RV32I-NEXT: or a4, a4, s0
-; RV32I-NEXT: sw a4, 684(sp) # 4-byte Folded Spill
-; RV32I-NEXT: or a4, t4, a6
-; RV32I-NEXT: sw a4, 688(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, t0, ra
-; RV32I-NEXT: slli a4, a4, 8
-; RV32I-NEXT: slli s3, t0, 24
-; RV32I-NEXT: or a4, s3, a4
-; RV32I-NEXT: or a4, a4, a7
-; RV32I-NEXT: sw a4, 696(sp) # 4-byte Folded Spill
-; RV32I-NEXT: or a4, s1, t5
+; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: and a4, t6, s2
+; RV32I-NEXT: sw a4, 720(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, s0, s3
+; RV32I-NEXT: sw a4, 724(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, t6, s3
+; RV32I-NEXT: sw a4, 708(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw ra, 752(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t6, a1, ra
+; RV32I-NEXT: slli t6, t6, 8
+; RV32I-NEXT: slli s3, a1, 24
+; RV32I-NEXT: or t6, s3, t6
+; RV32I-NEXT: or a4, t6, a6
; RV32I-NEXT: sw a4, 700(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a1, 2
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 2
+; RV32I-NEXT: or a4, a5, a7
+; RV32I-NEXT: sw a4, 704(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a5, t3, ra
+; RV32I-NEXT: slli a5, a5, 8
+; RV32I-NEXT: slli s2, t3, 24
+; RV32I-NEXT: or a5, s2, a5
+; RV32I-NEXT: or a4, a5, t5
+; RV32I-NEXT: sw a4, 712(sp) # 4-byte Folded Spill
+; RV32I-NEXT: or a4, t1, t0
+; RV32I-NEXT: sw a4, 716(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a5, a0, 2
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a6, a2, 2
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 1
-; RV32I-NEXT: and s4, a4, a6
-; RV32I-NEXT: slli a6, a0, 1
-; RV32I-NEXT: and s2, a5, a6
-; RV32I-NEXT: and t5, a4, a6
-; RV32I-NEXT: andi a4, a1, 4
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 4
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 1
+; RV32I-NEXT: and s5, a5, a7
+; RV32I-NEXT: slli a7, a1, 1
+; RV32I-NEXT: and s1, a6, a7
+; RV32I-NEXT: and t5, a5, a7
+; RV32I-NEXT: andi a5, a0, 4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a6, a2, 4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 2
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 640(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 2
-; RV32I-NEXT: and s7, a5, a6
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 676(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a1, 8
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 8
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 2
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 660(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 2
+; RV32I-NEXT: and s7, a6, a7
+; RV32I-NEXT: and t6, a5, a7
+; RV32I-NEXT: andi a5, a0, 8
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a6, a2, 8
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 3
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 612(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 3
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 628(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 668(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a1, 16
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 16
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 3
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 632(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 3
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 648(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 688(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a5, a0, 16
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a6, a2, 16
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 4
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 604(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 4
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 608(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 652(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a1, 32
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 32
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 4
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 624(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 4
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 628(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 672(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a5, a0, 32
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a6, a2, 32
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 5
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 584(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 5
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 592(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 636(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a1, 64
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 64
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 5
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 604(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 5
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 612(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 656(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a5, a0, 64
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a6, a2, 64
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 6
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 648(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 6
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 656(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 672(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a1, 128
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 128
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 7
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 556(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 7
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 568(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 596(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a1, 256
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 256
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 6
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 668(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 6
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 676(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 692(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a5, a0, 128
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a6, a2, 128
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 8
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 536(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 8
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 540(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 7
+; RV32I-NEXT: and a4, a5, a7
; RV32I-NEXT: sw a4, 576(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a1, 512
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 512
+; RV32I-NEXT: slli a7, a1, 7
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 588(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 616(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a5, a0, 256
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a6, a2, 256
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 9
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 588(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 9
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 600(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 632(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a1, 1024
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 1024
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 8
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 556(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 8
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 560(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 596(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a5, a0, 512
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a6, a2, 512
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 10
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 660(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 10
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 664(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 9
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 608(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 9
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 620(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 652(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a5, a0, 1024
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: andi a6, a2, 1024
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 10
+; RV32I-NEXT: and a4, a5, a7
; RV32I-NEXT: sw a4, 680(sp) # 4-byte Folded Spill
-; RV32I-NEXT: li a4, 1
-; RV32I-NEXT: slli a7, a4, 11
-; RV32I-NEXT: and a4, a1, a7
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a7
+; RV32I-NEXT: slli a7, a1, 10
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 684(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 696(sp) # 4-byte Folded Spill
+; RV32I-NEXT: li a5, 1
+; RV32I-NEXT: slli t0, a5, 11
+; RV32I-NEXT: and a5, a0, t0
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a2, t0
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 11
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 488(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 11
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 500(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 11
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 508(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 11
+; RV32I-NEXT: and a4, a6, a7
; RV32I-NEXT: sw a4, 520(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 1
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 540(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 1
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a2, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 12
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 476(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 12
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 484(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 508(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 2
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 12
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 496(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 12
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 504(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 528(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a2, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 13
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 512(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 13
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 516(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 560(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 4
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 13
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 532(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 13
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 536(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 580(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 4
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a2, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 14
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 572(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 14
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 580(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 616(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 8
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 14
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 592(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 14
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 600(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 636(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 8
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a2, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 15
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 620(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 15
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 624(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 15
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 640(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 15
+; RV32I-NEXT: and a4, a6, a7
; RV32I-NEXT: sw a4, 644(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 16
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 664(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 16
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a2, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 16
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 412(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 16
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 416(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 448(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 32
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 16
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 432(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 16
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 436(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 468(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 32
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a2, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 17
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 396(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 17
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 404(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 420(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 64
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 17
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 416(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 17
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 424(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 440(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 64
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a2, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 18
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 436(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 18
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 444(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 480(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 128
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 18
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 456(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 18
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 464(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 500(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 128
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a2, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 19
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 496(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 19
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 504(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 19
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 516(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 19
+; RV32I-NEXT: and a4, a6, a7
; RV32I-NEXT: sw a4, 524(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 256
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 544(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 256
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a2, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 20
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 528(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 20
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 532(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 20
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 548(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 20
+; RV32I-NEXT: and a4, a6, a7
; RV32I-NEXT: sw a4, 552(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 512
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 572(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 512
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a2, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 21
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 544(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 21
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 548(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 21
+; RV32I-NEXT: and a4, a5, a7
; RV32I-NEXT: sw a4, 564(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 1024
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: slli a7, a1, 21
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 568(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 584(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 1024
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a2, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 22
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 368(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 22
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 372(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 384(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 2048
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 22
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 388(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 22
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 392(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 404(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 2048
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a2, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 23
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 360(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 23
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 364(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 376(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 4096
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 23
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 380(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 23
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 384(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 396(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 4096
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a2, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 24
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 380(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a5, t6
-; RV32I-NEXT: sw a5, 388(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, t6
-; RV32I-NEXT: sw a4, 392(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 8192
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 24
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 400(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a6, s3
+; RV32I-NEXT: sw a4, 408(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, s3
+; RV32I-NEXT: sw a4, 412(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 8192
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a2, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 25
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 400(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 25
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 408(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 424(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 16384
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 25
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 420(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 25
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 428(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 444(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 16384
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a2, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 26
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 428(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 26
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 432(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 460(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 32768
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 26
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 448(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 26
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 452(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 480(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 32768
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a2, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 27
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 452(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 27
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 456(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sw a4, 464(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 65536
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 27
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 472(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 27
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 476(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 484(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 65536
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a2, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 28
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 472(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 28
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 468(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 28
+; RV32I-NEXT: and a4, a5, a7
; RV32I-NEXT: sw a4, 492(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a5, 131072
-; RV32I-NEXT: and a4, a1, a5
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: slli a7, a1, 28
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 488(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 512(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 131072
+; RV32I-NEXT: and a5, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: and a6, a2, a4
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 29
-; RV32I-NEXT: and a6, a4, a6
-; RV32I-NEXT: sw a6, 348(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 29
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sw a5, 352(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t6, a4, a6
-; RV32I-NEXT: lui a5, 262144
-; RV32I-NEXT: andi a4, a1, 1
-; RV32I-NEXT: and a1, a1, a5
-; RV32I-NEXT: lui t2, 262144
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a3, 1
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 29
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 364(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 29
+; RV32I-NEXT: and a4, a6, a7
+; RV32I-NEXT: sw a4, 368(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, a7
+; RV32I-NEXT: sw a4, 376(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 262144
+; RV32I-NEXT: andi a5, a0, 1
+; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a6, a2, 1
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, a2, 30
-; RV32I-NEXT: and a2, a4, a2
-; RV32I-NEXT: sw a2, 308(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a5, a0
-; RV32I-NEXT: sw a5, 332(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a0
-; RV32I-NEXT: sw a4, 356(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a0, a0, 30
-; RV32I-NEXT: and a2, a3, t2
-; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a7, a3, 30
+; RV32I-NEXT: and a3, a5, a3
+; RV32I-NEXT: sw a3, 324(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a3, a6, a1
+; RV32I-NEXT: sw a3, 348(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, a5, a1
+; RV32I-NEXT: slli a1, a1, 30
+; RV32I-NEXT: and a2, a2, a4
+; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: seqz a2, a2
-; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and a3, a1, a6
-; RV32I-NEXT: sw a3, 304(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a2, a2, a0
-; RV32I-NEXT: sw a2, 320(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, a1, a0
-; RV32I-NEXT: andi a0, t3, 2
+; RV32I-NEXT: and a3, a0, a7
+; RV32I-NEXT: sw a3, 320(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a2, a2, a1
+; RV32I-NEXT: sw a2, 336(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: sw a0, 372(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a0, t4, 2
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 2
+; RV32I-NEXT: andi a1, t2, 2
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 1
+; RV32I-NEXT: slli a2, s8, 1
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 300(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t0, 1
+; RV32I-NEXT: sw a2, 316(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, t3, 1
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 312(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 328(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 344(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a0, t3, 4
+; RV32I-NEXT: sw a0, 360(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a0, t4, 4
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 4
+; RV32I-NEXT: andi a1, t2, 4
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 2
+; RV32I-NEXT: slli a2, s8, 2
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 280(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t0, 2
+; RV32I-NEXT: sw a2, 296(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, t3, 2
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 288(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 304(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 336(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a0, t3, 8
+; RV32I-NEXT: sw a0, 352(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a0, t4, 8
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 8
+; RV32I-NEXT: andi a1, t2, 8
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 3
+; RV32I-NEXT: slli a2, s8, 3
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 260(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t0, 3
+; RV32I-NEXT: sw a2, 276(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, t3, 3
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 268(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 284(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 296(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a0, t3, 16
+; RV32I-NEXT: sw a0, 312(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a0, t4, 16
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 16
+; RV32I-NEXT: andi a1, t2, 16
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 4
+; RV32I-NEXT: slli a2, s8, 4
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 236(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t0, 4
+; RV32I-NEXT: sw a2, 252(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, t3, 4
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 244(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 260(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 276(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a0, t3, 32
+; RV32I-NEXT: sw a0, 292(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a0, t4, 32
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 32
+; RV32I-NEXT: andi a1, t2, 32
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 5
+; RV32I-NEXT: slli a2, s8, 5
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 212(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t0, 5
+; RV32I-NEXT: sw a2, 228(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, t3, 5
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 224(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 240(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 252(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a0, t3, 64
+; RV32I-NEXT: sw a0, 268(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a0, t4, 64
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 64
+; RV32I-NEXT: andi a1, t2, 64
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 6
+; RV32I-NEXT: slli a2, s8, 6
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 284(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t0, 6
+; RV32I-NEXT: sw a2, 300(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, t3, 6
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 292(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 308(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 328(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a0, t3, 128
+; RV32I-NEXT: sw a0, 344(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a0, t4, 128
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 128
+; RV32I-NEXT: andi a1, t2, 128
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 7
+; RV32I-NEXT: slli a2, s8, 7
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 192(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t0, 7
+; RV32I-NEXT: sw a2, 208(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, t3, 7
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 200(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 216(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 208(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a0, t3, 256
+; RV32I-NEXT: sw a0, 224(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a0, t4, 256
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 256
+; RV32I-NEXT: andi a1, t2, 256
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 8
+; RV32I-NEXT: slli a2, s8, 8
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 164(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t0, 8
+; RV32I-NEXT: sw a2, 180(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, t3, 8
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 172(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 188(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 204(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a0, t3, 512
+; RV32I-NEXT: sw a0, 220(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a0, t4, 512
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 512
+; RV32I-NEXT: andi a1, t2, 512
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 9
+; RV32I-NEXT: slli a2, s8, 9
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 216(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t0, 9
+; RV32I-NEXT: sw a2, 232(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, t3, 9
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 228(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 244(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 248(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a0, t3, 1024
+; RV32I-NEXT: sw a0, 264(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a0, t4, 1024
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 1024
+; RV32I-NEXT: andi a1, t2, 1024
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 10
+; RV32I-NEXT: slli a2, s8, 10
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 316(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t0, 10
+; RV32I-NEXT: sw a2, 332(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, t3, 10
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 324(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 340(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 340(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw a7, 440(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a0, t3, a7
+; RV32I-NEXT: sw a0, 356(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw t0, 460(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a0, t4, t0
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a7
+; RV32I-NEXT: and a1, t2, t0
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 11
+; RV32I-NEXT: slli a2, s8, 11
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 112(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t0, 11
+; RV32I-NEXT: sw a2, 128(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, t3, 11
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 128(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 144(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 144(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 160(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 1
-; RV32I-NEXT: and a0, t3, a1
+; RV32I-NEXT: and a0, t4, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 12
+; RV32I-NEXT: slli a2, s8, 12
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 104(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t0, 12
+; RV32I-NEXT: sw a2, 120(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, t3, 12
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 108(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 124(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 132(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 148(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 2
-; RV32I-NEXT: and a0, t3, a1
+; RV32I-NEXT: and a0, t4, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 13
+; RV32I-NEXT: slli a2, s8, 13
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 148(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t0, 13
+; RV32I-NEXT: sw a2, 164(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, t3, 13
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 156(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 172(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 180(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 196(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 4
-; RV32I-NEXT: and a0, t3, a1
+; RV32I-NEXT: and a0, t4, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 14
+; RV32I-NEXT: slli a2, s8, 14
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 220(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t0, 14
+; RV32I-NEXT: sw a2, 236(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, t3, 14
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 232(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 248(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 240(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 256(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 8
-; RV32I-NEXT: and a0, t3, a1
+; RV32I-NEXT: and a0, t4, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 15
+; RV32I-NEXT: slli a2, s8, 15
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 256(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t0, 15
+; RV32I-NEXT: sw a2, 272(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, t3, 15
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 264(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 280(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 272(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 288(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 16
-; RV32I-NEXT: and a0, t3, a1
+; RV32I-NEXT: and a0, t4, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli s0, t1, 16
+; RV32I-NEXT: slli s0, s8, 16
; RV32I-NEXT: and s0, a0, s0
-; RV32I-NEXT: slli a2, t0, 16
+; RV32I-NEXT: slli a2, t3, 16
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 48(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 64(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 32
-; RV32I-NEXT: and a0, t3, a1
+; RV32I-NEXT: and a0, t4, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 17
+; RV32I-NEXT: slli a2, s8, 17
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 36(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t0, 17
+; RV32I-NEXT: sw a2, 52(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, t3, 17
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 40(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 56(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 72(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 64
-; RV32I-NEXT: and a0, t3, a1
+; RV32I-NEXT: and a0, t4, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 18
+; RV32I-NEXT: slli a2, s8, 18
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 76(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t0, 18
+; RV32I-NEXT: sw a2, 92(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, t3, 18
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 80(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 96(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 100(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 116(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 128
-; RV32I-NEXT: and a0, t3, a1
+; RV32I-NEXT: and a0, t4, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 19
+; RV32I-NEXT: slli a2, s8, 19
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 136(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t0, 19
+; RV32I-NEXT: sw a2, 152(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, t3, 19
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 140(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 156(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 152(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 168(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 256
-; RV32I-NEXT: and a0, t3, a1
+; RV32I-NEXT: and a0, t4, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 20
+; RV32I-NEXT: slli a2, s8, 20
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 160(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t0, 20
+; RV32I-NEXT: sw a2, 176(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, t3, 20
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 168(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 184(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 176(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 192(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 512
-; RV32I-NEXT: and a0, t3, a1
+; RV32I-NEXT: and a0, t4, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 21
+; RV32I-NEXT: slli a2, s8, 21
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 184(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t0, 21
+; RV32I-NEXT: sw a2, 200(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, t3, 21
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: sw a1, 188(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 204(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: sw a0, 196(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 212(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 1024
-; RV32I-NEXT: and a0, t3, a1
+; RV32I-NEXT: and a0, t4, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a2, t1, 22
+; RV32I-NEXT: slli a2, s8, 22
; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: sw a2, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, t0, 22
-; RV32I-NEXT: and a2, a1, a5
+; RV32I-NEXT: sw a2, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, t3, 22
+; RV32I-NEXT: and a1, a1, a5
+; RV32I-NEXT: sw a1, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a5
-; RV32I-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 2048
-; RV32I-NEXT: and a0, t3, a1
+; RV32I-NEXT: and a0, t4, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: addi a4, a0, -1
+; RV32I-NEXT: addi a5, a0, -1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a0, t1, 23
-; RV32I-NEXT: and a0, a4, a0
-; RV32I-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, t0, 23
-; RV32I-NEXT: and a5, a1, a6
-; RV32I-NEXT: and a0, a4, a6
+; RV32I-NEXT: slli a0, s8, 23
+; RV32I-NEXT: and a0, a5, a0
; RV32I-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, t3, 23
+; RV32I-NEXT: and a0, a1, a7
+; RV32I-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a0, a5, a7
+; RV32I-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, 4096
-; RV32I-NEXT: and a6, t3, a0
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: and a7, s6, a0
+; RV32I-NEXT: and a7, t4, a0
; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: addi t4, a6, -1
-; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: slli a6, t1, 24
-; RV32I-NEXT: and a0, t4, a6
-; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a0, a7, s3
-; RV32I-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a0, t4, s3
-; RV32I-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t0, t2, a0
+; RV32I-NEXT: seqz t0, t0
+; RV32I-NEXT: addi t1, a7, -1
+; RV32I-NEXT: addi t0, t0, -1
+; RV32I-NEXT: slli a7, s8, 24
+; RV32I-NEXT: and a0, t1, a7
+; RV32I-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a0, t0, s2
+; RV32I-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a0, t1, s2
+; RV32I-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, 8192
-; RV32I-NEXT: and s1, t3, a0
-; RV32I-NEXT: seqz s1, s1
-; RV32I-NEXT: and s3, s6, a0
+; RV32I-NEXT: and s2, t4, a0
+; RV32I-NEXT: seqz s2, s2
+; RV32I-NEXT: and s3, t2, a0
; RV32I-NEXT: seqz s3, s3
-; RV32I-NEXT: addi s5, s1, -1
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: slli s1, t1, 25
-; RV32I-NEXT: and a0, s5, s1
-; RV32I-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s8, t0, 25
-; RV32I-NEXT: and a0, s3, s8
-; RV32I-NEXT: sw a0, 52(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a0, s5, s8
+; RV32I-NEXT: addi s4, s2, -1
+; RV32I-NEXT: addi s2, s3, -1
+; RV32I-NEXT: slli s3, s8, 25
+; RV32I-NEXT: mv a1, s8
+; RV32I-NEXT: and a0, s4, s3
; RV32I-NEXT: sw a0, 60(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s6, t3, 25
+; RV32I-NEXT: and a0, s2, s6
+; RV32I-NEXT: sw a0, 68(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a0, s4, s6
+; RV32I-NEXT: sw a0, 76(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, 16384
-; RV32I-NEXT: and s5, t3, a0
-; RV32I-NEXT: seqz s5, s5
-; RV32I-NEXT: and s8, s6, a0
+; RV32I-NEXT: and s6, t4, a0
+; RV32I-NEXT: seqz s6, s6
+; RV32I-NEXT: and s8, t2, a0
; RV32I-NEXT: seqz s8, s8
-; RV32I-NEXT: addi s9, s5, -1
+; RV32I-NEXT: addi s9, s6, -1
; RV32I-NEXT: addi s8, s8, -1
-; RV32I-NEXT: slli s5, t1, 26
-; RV32I-NEXT: and a0, s9, s5
-; RV32I-NEXT: sw a0, 68(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s10, t0, 26
+; RV32I-NEXT: slli s6, a1, 26
+; RV32I-NEXT: and a0, s9, s6
+; RV32I-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s10, t3, 26
; RV32I-NEXT: and a0, s8, s10
-; RV32I-NEXT: sw a0, 72(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, s9, s10
-; RV32I-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 100(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, 32768
-; RV32I-NEXT: and s9, t3, a0
+; RV32I-NEXT: and s9, t4, a0
; RV32I-NEXT: seqz s9, s9
-; RV32I-NEXT: and s10, s6, a0
+; RV32I-NEXT: and s10, t2, a0
; RV32I-NEXT: seqz s10, s10
; RV32I-NEXT: addi s9, s9, -1
; RV32I-NEXT: addi s10, s10, -1
-; RV32I-NEXT: slli s11, t1, 27
+; RV32I-NEXT: slli s11, a1, 27
; RV32I-NEXT: and a0, s9, s11
-; RV32I-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s11, t0, 27
+; RV32I-NEXT: sw a0, 104(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s11, t3, 27
; RV32I-NEXT: and a0, s10, s11
-; RV32I-NEXT: sw a0, 92(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 108(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, s9, s11
-; RV32I-NEXT: sw a0, 96(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 112(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, 65536
-; RV32I-NEXT: and s9, t3, a0
+; RV32I-NEXT: and s9, t4, a0
; RV32I-NEXT: seqz s9, s9
-; RV32I-NEXT: and s10, s6, a0
+; RV32I-NEXT: and s10, t2, a0
; RV32I-NEXT: seqz s10, s10
; RV32I-NEXT: addi s9, s9, -1
; RV32I-NEXT: addi s10, s10, -1
-; RV32I-NEXT: slli s11, t1, 28
+; RV32I-NEXT: slli s11, a1, 28
; RV32I-NEXT: and a0, s9, s11
-; RV32I-NEXT: sw a0, 120(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s11, t0, 28
+; RV32I-NEXT: sw a0, 136(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s11, t3, 28
; RV32I-NEXT: and a0, s10, s11
-; RV32I-NEXT: sw a0, 116(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 132(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, s9, s11
-; RV32I-NEXT: sw a0, 124(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 140(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, 131072
-; RV32I-NEXT: and s9, t3, a0
+; RV32I-NEXT: and s9, t4, a0
; RV32I-NEXT: seqz s9, s9
-; RV32I-NEXT: and s10, s6, a0
+; RV32I-NEXT: and s10, t2, a0
; RV32I-NEXT: seqz s10, s10
; RV32I-NEXT: addi s9, s9, -1
; RV32I-NEXT: addi s10, s10, -1
-; RV32I-NEXT: slli s11, t1, 29
+; RV32I-NEXT: slli s11, a1, 29
; RV32I-NEXT: and s11, s9, s11
-; RV32I-NEXT: slli ra, t0, 29
-; RV32I-NEXT: and a4, s10, ra
-; RV32I-NEXT: and a0, s9, ra
-; RV32I-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi ra, t3, 1
-; RV32I-NEXT: lui a0, 262144
-; RV32I-NEXT: and t3, t3, a0
+; RV32I-NEXT: slli ra, t3, 29
+; RV32I-NEXT: and a5, s10, ra
+; RV32I-NEXT: and s8, s9, ra
+; RV32I-NEXT: andi ra, t4, 1
+; RV32I-NEXT: lui a2, 262144
+; RV32I-NEXT: and t4, t4, a2
; RV32I-NEXT: seqz ra, ra
-; RV32I-NEXT: andi s8, s6, 1
-; RV32I-NEXT: seqz s8, s8
+; RV32I-NEXT: andi a4, t2, 1
+; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: addi ra, ra, -1
-; RV32I-NEXT: addi s8, s8, -1
-; RV32I-NEXT: slli t2, t1, 30
-; RV32I-NEXT: and t1, ra, t1
-; RV32I-NEXT: and s8, s8, t0
-; RV32I-NEXT: and a6, ra, t0
-; RV32I-NEXT: slli t0, t0, 30
-; RV32I-NEXT: and s6, s6, a0
-; RV32I-NEXT: seqz t3, t3
-; RV32I-NEXT: seqz s6, s6
-; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: addi s6, s6, -1
-; RV32I-NEXT: and t2, t3, t2
-; RV32I-NEXT: and s6, s6, t0
-; RV32I-NEXT: and a0, t3, t0
-; RV32I-NEXT: sw a0, 0(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 308(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, s4
-; RV32I-NEXT: sw a0, 308(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 640(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 612(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 612(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 604(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 584(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 604(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 556(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 536(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 556(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 488(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 476(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 536(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 412(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 396(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 488(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 368(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 360(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 476(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 348(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 304(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 412(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 332(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, s2
-; RV32I-NEXT: sw a0, 640(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 628(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, s7, a0
-; RV32I-NEXT: sw a0, 396(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 608(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 592(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 608(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 568(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 540(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 592(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 500(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 484(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 540(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 416(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 404(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 484(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 372(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 364(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 416(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 352(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 320(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 404(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 300(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, t1, a0
-; RV32I-NEXT: sw a0, 628(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 280(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 260(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: slli a0, a1, 30
+; RV32I-NEXT: and a1, ra, a1
+; RV32I-NEXT: and a4, a4, t3
+; RV32I-NEXT: and a7, ra, t3
+; RV32I-NEXT: slli t3, t3, 30
+; RV32I-NEXT: and t2, t2, a2
+; RV32I-NEXT: seqz t4, t4
+; RV32I-NEXT: seqz t2, t2
+; RV32I-NEXT: addi t4, t4, -1
+; RV32I-NEXT: addi t2, t2, -1
+; RV32I-NEXT: and a0, t4, a0
+; RV32I-NEXT: and t2, t2, t3
+; RV32I-NEXT: and a2, t4, t3
+; RV32I-NEXT: sw a2, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a2, 324(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, s5
+; RV32I-NEXT: sw a2, 324(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a2, 660(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 632(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sw a2, 632(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a2, 624(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 604(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sw a2, 624(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a2, 576(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 556(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sw a2, 576(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a2, 508(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 496(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sw a2, 556(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a2, 432(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 416(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sw a2, 508(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a2, 388(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 380(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sw a2, 496(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a2, 364(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 320(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sw a2, 432(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a2, 348(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, s1
+; RV32I-NEXT: sw a2, 660(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a2, 648(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, s7, a2
+; RV32I-NEXT: sw a2, 416(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a2, 628(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 612(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sw a2, 628(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a2, 588(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 560(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sw a2, 612(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a2, 520(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 504(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sw a2, 560(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a2, 436(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 424(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sw a2, 504(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a2, 392(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 384(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sw a2, 436(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a2, 368(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 336(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sw a2, 424(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a2, 316(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 648(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 296(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 276(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 392(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 252(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 228(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s10, a1, a2
+; RV32I-NEXT: lw a1, 208(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 180(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor ra, a1, a2
+; RV32I-NEXT: lw a1, 128(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 120(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 388(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 52(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, s0, a1
+; RV32I-NEXT: sw a1, 384(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: sw a1, 380(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a0, s11, a0
; RV32I-NEXT: sw a0, 368(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 236(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 212(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 364(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 192(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 164(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 360(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 112(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 104(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 352(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s10, s0, a0
-; RV32I-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor ra, a0, a1
-; RV32I-NEXT: xor s11, s11, t2
-; RV32I-NEXT: lw a0, 312(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, s8, a0
-; RV32I-NEXT: sw a0, 372(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 288(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 268(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s2, a0, a1
-; RV32I-NEXT: lw a0, 244(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 224(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 328(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s11, a4, a0
+; RV32I-NEXT: lw a0, 304(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 284(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s5, a0, a1
-; RV32I-NEXT: lw a0, 200(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 172(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s7, a0, a1
-; RV32I-NEXT: lw a0, 128(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 108(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 260(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 240(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s0, a0, s0
-; RV32I-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 40(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 216(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 188(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s1, a0, s1
-; RV32I-NEXT: xor s3, a2, a5
-; RV32I-NEXT: xor s6, a4, s6
-; RV32I-NEXT: lw a0, 356(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s4, a0, t5
-; RV32I-NEXT: lw a0, 676(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 668(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t0, a0, a1
-; RV32I-NEXT: lw a0, 652(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 636(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 144(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 124(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s2, a0, a1
+; RV32I-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 56(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s4, a0, a1
+; RV32I-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s6, a0, a1
+; RV32I-NEXT: xor s3, a5, t2
+; RV32I-NEXT: xor s7, a6, t5
+; RV32I-NEXT: lw a0, 688(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t0, t6, a0
+; RV32I-NEXT: lw a0, 672(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 656(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t1, a0, a1
-; RV32I-NEXT: lw a0, 596(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 576(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 616(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 596(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t2, a0, a1
-; RV32I-NEXT: lw a0, 520(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 508(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 540(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 528(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t3, a0, a1
-; RV32I-NEXT: lw a0, 448(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 420(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 468(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 440(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t4, a0, a1
-; RV32I-NEXT: lw a0, 384(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 376(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 404(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 396(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t5, a0, a1
-; RV32I-NEXT: xor t6, t6, a3
-; RV32I-NEXT: lw a0, 344(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a7, a6, a0
-; RV32I-NEXT: lw a0, 336(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 296(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 376(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 372(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t6, a0, a1
+; RV32I-NEXT: lw a0, 360(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a7, a7, a0
+; RV32I-NEXT: lw a0, 352(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 312(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: lw a1, 276(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 252(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 292(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 268(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: lw a2, 208(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a3, 204(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 224(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 220(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: lw a3, 144(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a4, 132(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 160(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 148(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: lw a4, 64(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a5, 56(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 80(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 72(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: lw a5, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a6, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 36(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lw a6, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 0(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a6, a6, s8
-; RV32I-NEXT: lw s8, 308(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 612(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a6, s8, a6
+; RV32I-NEXT: lw s8, 324(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 632(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s8, s8, s9
-; RV32I-NEXT: sw s8, 596(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s8, 648(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 604(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw s8, 616(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 668(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 624(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s8, s9, s8
-; RV32I-NEXT: sw s8, 584(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s8, 588(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw s8, 604(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 608(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 576(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s9, s8
+; RV32I-NEXT: sw s8, 608(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 532(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s9, 556(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s8, s9, s8
+; RV32I-NEXT: sw s8, 596(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 456(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 508(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, s9, s8
; RV32I-NEXT: sw s8, 588(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s8, 512(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 536(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s8, 400(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 496(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s8, s9, s8
; RV32I-NEXT: sw s8, 576(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s8, 436(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 488(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s8, s9, s8
-; RV32I-NEXT: sw s8, 568(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s8, 380(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 476(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s8, 732(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 432(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s8, s9, s8
-; RV32I-NEXT: sw s8, 556(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s8, 716(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 412(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s8, s9, s8
-; RV32I-NEXT: sw s8, 716(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s8, 640(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 396(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw s8, 732(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 660(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 416(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s8, s8, s9
-; RV32I-NEXT: sw s8, 512(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s8, 656(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 608(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw s8, 532(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 676(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 628(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s8, s9, s8
-; RV32I-NEXT: sw s8, 508(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s8, 600(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 592(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw s8, 528(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 620(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 612(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s8, s9, s8
-; RV32I-NEXT: sw s8, 500(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s8, 516(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 540(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw s8, 520(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 536(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 560(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s8, s9, s8
-; RV32I-NEXT: sw s8, 516(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s8, 444(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 484(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw s8, 536(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 464(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 504(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s8, s9, s8
-; RV32I-NEXT: sw s8, 488(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s8, 388(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 416(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw s8, 508(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 408(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 436(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s8, s9, s8
-; RV32I-NEXT: sw s8, 484(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s8, 720(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 404(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw s8, 504(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 736(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 424(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s8, s9, s8
-; RV32I-NEXT: sw s8, 720(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s8, 628(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 368(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s8, s8, s9
+; RV32I-NEXT: sw s8, 736(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 648(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 392(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s9, s8, s9
+; RV32I-NEXT: lw s8, 300(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s10, s10, s8
+; RV32I-NEXT: lw s8, 232(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, ra, s8
+; RV32I-NEXT: sw s8, 688(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 164(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 388(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, ra, s8
; RV32I-NEXT: sw s8, 676(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s8, 284(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 364(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s8, s9, s8
+; RV32I-NEXT: lw s8, 92(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 384(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, ra, s8
+; RV32I-NEXT: sw s8, 672(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s8, 40(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s8, ra, s8
; RV32I-NEXT: sw s8, 668(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s8, 216(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 360(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s8, s9, s8
-; RV32I-NEXT: sw s8, 656(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s8, 148(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 352(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s9, s9, s8
-; RV32I-NEXT: lw s8, 76(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s10, s10, s8
-; RV32I-NEXT: lw s8, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s8, 720(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 368(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s8, ra, s8
-; RV32I-NEXT: sw s8, 652(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s8, 704(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s8, s11, s8
-; RV32I-NEXT: sw s8, 704(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s8, 372(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s8, s8, s2
-; RV32I-NEXT: lw s2, 292(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s2, s5, s2
-; RV32I-NEXT: sw s2, 648(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s2, 228(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s2, s7, s2
-; RV32I-NEXT: sw s2, 640(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s2, 156(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s0, s0, s2
-; RV32I-NEXT: sw s0, 636(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s0, 80(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s0, s1, s0
-; RV32I-NEXT: sw s0, 628(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s0, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s0, s3, s0
-; RV32I-NEXT: sw s0, 612(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s0, 708(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw s8, 720(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor s8, s11, s5
+; RV32I-NEXT: lw s5, 308(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s0, s0, s5
+; RV32I-NEXT: sw s0, 660(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s0, 244(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s1, s1, s0
+; RV32I-NEXT: lw s0, 172(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s0, s2, s0
+; RV32I-NEXT: sw s0, 656(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s0, 96(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s0, s4, s0
+; RV32I-NEXT: sw s0, 648(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s0, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s0, s6, s0
-; RV32I-NEXT: sw s0, 708(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor t0, s4, t0
-; RV32I-NEXT: sw t0, 608(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw t0, 672(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw s0, 632(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s0, 724(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s0, s3, s0
+; RV32I-NEXT: sw s0, 724(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor t0, s7, t0
+; RV32I-NEXT: sw t0, 628(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw t0, 692(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t1, t1, t0
-; RV32I-NEXT: lw t0, 632(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t0, 652(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t0, t2, t0
-; RV32I-NEXT: sw t0, 672(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw t0, 560(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw t0, 692(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw t0, 580(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t0, t3, t0
-; RV32I-NEXT: sw t0, 632(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw t0, 480(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw t0, 652(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw t0, 500(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t0, t4, t0
-; RV32I-NEXT: sw t0, 604(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw t0, 392(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw t0, 624(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw t0, 412(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t0, t5, t0
-; RV32I-NEXT: sw t0, 600(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw t0, 712(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw t0, 620(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw t0, 728(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t0, t6, t0
-; RV32I-NEXT: sw t0, 712(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw t0, 728(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a0, a7, a0
-; RV32I-NEXT: sw a0, 592(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 328(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a0, 612(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 344(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a1, a0
-; RV32I-NEXT: sw a0, 560(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 248(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a0, 580(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 264(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a2, a0
-; RV32I-NEXT: sw a0, 540(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 180(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a0, 560(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 196(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a3, a3, a0
-; RV32I-NEXT: lw a0, 100(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 116(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a4, a0
-; RV32I-NEXT: sw a0, 536(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a0, 556(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a5, a0
-; RV32I-NEXT: sw a0, 520(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 692(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a0, 540(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 708(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a6, a0
-; RV32I-NEXT: sw a0, 692(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 684(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a5, a0, 4
-; RV32I-NEXT: lw a1, 744(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a0, a1
-; RV32I-NEXT: and a5, a5, a1
-; RV32I-NEXT: slli a6, a6, 4
-; RV32I-NEXT: or a0, a5, a6
-; RV32I-NEXT: sw a0, 684(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 688(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a0, 708(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 700(sp) # 4-byte Folded Reload
; RV32I-NEXT: srli a6, a0, 4
+; RV32I-NEXT: lw a1, 760(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a7, a0, a1
; RV32I-NEXT: and a6, a6, a1
; RV32I-NEXT: slli a7, a7, 4
; RV32I-NEXT: or a0, a6, a7
-; RV32I-NEXT: sw a0, 688(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 596(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 584(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a0, 700(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 704(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a7, a0, 4
+; RV32I-NEXT: and t0, a0, a1
+; RV32I-NEXT: and a7, a7, a1
+; RV32I-NEXT: slli t0, t0, 4
+; RV32I-NEXT: or a0, a7, t0
+; RV32I-NEXT: sw a0, 704(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 616(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 604(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a0, a2
-; RV32I-NEXT: sw a0, 596(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 660(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 588(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a0, 616(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 680(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 608(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor ra, a2, a0
-; RV32I-NEXT: lw a0, 572(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 576(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 592(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 596(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a2, a0
-; RV32I-NEXT: sw a0, 588(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 496(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 568(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a0, 608(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 516(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 588(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a2, a0
-; RV32I-NEXT: sw a0, 584(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 400(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 556(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a0, 604(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 420(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 576(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a2, a0
-; RV32I-NEXT: sw a0, 576(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 512(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 508(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a0, 596(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 532(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 528(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a0, a2
-; RV32I-NEXT: sw a0, 660(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 664(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 500(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a0, 680(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 684(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 520(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s11, a2, a0
-; RV32I-NEXT: lw a0, 580(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 516(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 600(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 536(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a2, a0
-; RV32I-NEXT: sw a0, 664(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 504(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 488(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a0, 684(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 524(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 508(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a2, a0
-; RV32I-NEXT: sw a0, 580(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 408(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 484(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a0, 600(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 428(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 504(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a2, a0
-; RV32I-NEXT: sw a0, 572(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 696(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a0, 592(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 712(sp) # 4-byte Folded Reload
; RV32I-NEXT: srli t2, a0, 4
; RV32I-NEXT: and t3, a0, a1
; RV32I-NEXT: and t2, t2, a1
; RV32I-NEXT: slli t3, t3, 4
; RV32I-NEXT: or a0, t2, t3
-; RV32I-NEXT: sw a0, 696(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 700(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a0, 712(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 716(sp) # 4-byte Folded Reload
; RV32I-NEXT: srli t3, a0, 4
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: and t3, t3, a1
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, t3, a0
-; RV32I-NEXT: sw a0, 700(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 676(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 668(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 676(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 316(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 656(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a0, 716(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a0, s9, s10
+; RV32I-NEXT: sw a0, 588(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 332(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 688(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s5, a1, a0
-; RV32I-NEXT: lw a0, 220(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s6, s9, a0
-; RV32I-NEXT: lw a0, 136(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s2, s10, a0
-; RV32I-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 652(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 236(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 676(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s6, a1, a0
+; RV32I-NEXT: lw a0, 152(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 672(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s2, a1, a0
+; RV32I-NEXT: lw a0, 60(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 668(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s3, a1, a0
-; RV32I-NEXT: lw a0, 648(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 660(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s4, s8, a0
-; RV32I-NEXT: lw a0, 324(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 640(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor s0, s0, a0
-; RV32I-NEXT: lw a0, 232(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 636(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 340(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor s0, s1, a0
+; RV32I-NEXT: lw a0, 248(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 656(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s1, s1, a0
-; RV32I-NEXT: lw a0, 140(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 628(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 156(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 648(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t4, a1, a0
-; RV32I-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 612(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 632(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t5, a1, a0
-; RV32I-NEXT: lw a0, 608(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 628(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t6, a0, t1
-; RV32I-NEXT: lw a0, 680(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 672(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 696(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 692(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t2, a1, a0
-; RV32I-NEXT: lw a0, 616(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 632(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 636(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 652(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t3, a1, a0
-; RV32I-NEXT: lw a0, 524(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 604(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 544(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 624(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a7, a1, a0
-; RV32I-NEXT: lw a0, 424(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 600(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 444(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 620(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t0, a1, a0
-; RV32I-NEXT: lw a0, 592(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 560(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 612(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 580(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t1, a0, a1
-; RV32I-NEXT: lw a0, 340(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a4, 540(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 356(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 560(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a4, a4, a0
-; RV32I-NEXT: lw a0, 240(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 256(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a5, a3, a0
-; RV32I-NEXT: lw a0, 152(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 536(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 168(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 556(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a6, a1, a0
-; RV32I-NEXT: lw a0, 60(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a3, 520(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 540(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a3, a3, a0
-; RV32I-NEXT: lw a0, 596(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 616(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor ra, a0, ra
-; RV32I-NEXT: lw a0, 620(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 588(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 640(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 608(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a1, a0
-; RV32I-NEXT: lw a1, 528(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 584(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 548(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 604(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a1, a2, a1
-; RV32I-NEXT: lw a2, 428(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 576(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 448(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s8, 596(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a2, s8, a2
-; RV32I-NEXT: lw s8, 660(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s8, 680(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s11, s8, s11
-; RV32I-NEXT: lw s8, 624(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 664(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s8, 644(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 684(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s8, s9, s8
-; RV32I-NEXT: lw s9, 532(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s10, 580(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 552(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s10, 600(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s9, s10, s9
-; RV32I-NEXT: lw s10, 432(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 572(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s10, 452(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s7, 592(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s10, s7, s10
-; RV32I-NEXT: lw s7, 676(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s7, 588(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s5, s7, s5
-; RV32I-NEXT: lw s7, 256(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s7, 272(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s6, s6, s7
-; RV32I-NEXT: lw s7, 160(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s7, 176(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s2, s2, s7
-; RV32I-NEXT: lw s7, 68(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s7, 84(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s3, s3, s7
; RV32I-NEXT: xor s0, s4, s0
-; RV32I-NEXT: lw s4, 264(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 280(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s1, s1, s4
-; RV32I-NEXT: lw s4, 168(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 184(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t4, t4, s4
-; RV32I-NEXT: lw s4, 72(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 88(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t5, t5, s4
; RV32I-NEXT: xor t2, t6, t2
-; RV32I-NEXT: lw t6, 644(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t6, 664(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t3, t3, t6
-; RV32I-NEXT: lw t6, 552(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t6, 572(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a7, a7, t6
-; RV32I-NEXT: lw t6, 460(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t6, 480(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t0, t0, t6
; RV32I-NEXT: xor a4, t1, a4
-; RV32I-NEXT: lw t1, 272(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 288(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a5, a5, t1
-; RV32I-NEXT: lw t1, 176(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 192(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a6, a6, t1
-; RV32I-NEXT: lw t1, 84(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 100(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a3, a3, t1
; RV32I-NEXT: xor a0, ra, a0
-; RV32I-NEXT: lw t1, 544(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 564(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a1, a1, t1
-; RV32I-NEXT: lw t1, 452(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 472(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a2, a2, t1
; RV32I-NEXT: xor t1, s11, s8
-; RV32I-NEXT: lw t6, 548(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t6, 568(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t6, s9, t6
-; RV32I-NEXT: lw s4, 456(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 476(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s4, s10, s4
; RV32I-NEXT: xor s5, s5, s6
-; RV32I-NEXT: lw s6, 184(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s6, 200(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s2, s2, s6
-; RV32I-NEXT: lw s6, 88(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s6, 104(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s3, s3, s6
; RV32I-NEXT: xor s0, s0, s1
-; RV32I-NEXT: lw s1, 188(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 204(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t4, t4, s1
-; RV32I-NEXT: lw s1, 92(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 108(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t5, t5, s1
; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: lw t3, 564(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a7, a7, t3
-; RV32I-NEXT: lw t3, 464(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t0, t0, t3
+; RV32I-NEXT: lw t3, 584(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t3, a7, t3
+; RV32I-NEXT: lw a7, 484(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t0, t0, a7
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: lw a5, 196(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t3, a6, a5
-; RV32I-NEXT: lw a5, 96(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a3, a3, a5
-; RV32I-NEXT: lw a6, 684(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a5, a6, 2
-; RV32I-NEXT: lw s6, 724(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 212(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a5, a6, a5
+; RV32I-NEXT: lw a6, 112(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a3, a3, a6
+; RV32I-NEXT: lw a7, 700(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a6, a7, 2
+; RV32I-NEXT: lw s6, 740(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, a7, s6
; RV32I-NEXT: and a6, a6, s6
-; RV32I-NEXT: and a5, a5, s6
-; RV32I-NEXT: slli a6, a6, 2
-; RV32I-NEXT: or s1, a5, a6
-; RV32I-NEXT: lw a6, 688(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a5, a6, 2
+; RV32I-NEXT: slli a7, a7, 2
+; RV32I-NEXT: or s1, a6, a7
+; RV32I-NEXT: lw a7, 704(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a6, a7, 2
+; RV32I-NEXT: and a7, a7, s6
; RV32I-NEXT: and a6, a6, s6
-; RV32I-NEXT: and a5, a5, s6
-; RV32I-NEXT: slli a6, a6, 2
-; RV32I-NEXT: or a5, a5, a6
+; RV32I-NEXT: slli a7, a7, 2
+; RV32I-NEXT: or a6, a6, a7
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: lw a1, 472(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 492(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a1, a2, a1
; RV32I-NEXT: xor a2, t1, t6
-; RV32I-NEXT: lw a6, 468(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t1, s4, a6
-; RV32I-NEXT: lw t6, 696(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a6, t6, 2
+; RV32I-NEXT: lw a7, 488(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t1, s4, a7
+; RV32I-NEXT: lw t6, 712(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a7, t6, 2
; RV32I-NEXT: and t6, t6, s6
-; RV32I-NEXT: and a6, a6, s6
+; RV32I-NEXT: and a7, a7, s6
; RV32I-NEXT: slli t6, t6, 2
-; RV32I-NEXT: or t6, a6, t6
-; RV32I-NEXT: lw s4, 700(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a6, s4, 2
+; RV32I-NEXT: or t6, a7, t6
+; RV32I-NEXT: lw s4, 716(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a7, s4, 2
; RV32I-NEXT: and s4, s4, s6
-; RV32I-NEXT: and a6, a6, s6
+; RV32I-NEXT: and a7, a7, s6
; RV32I-NEXT: slli s4, s4, 2
-; RV32I-NEXT: or a6, a6, s4
+; RV32I-NEXT: or a7, a7, s4
; RV32I-NEXT: xor s2, s5, s2
-; RV32I-NEXT: lw s4, 120(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 136(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s3, s3, s4
; RV32I-NEXT: xor t4, s0, t4
-; RV32I-NEXT: lw s0, 116(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 132(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t5, t5, s0
-; RV32I-NEXT: xor a7, t2, a7
-; RV32I-NEXT: lw t2, 492(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t0, t0, t2
-; RV32I-NEXT: xor a4, a4, t3
-; RV32I-NEXT: lw t2, 124(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a3, a3, t2
+; RV32I-NEXT: xor t2, t2, t3
+; RV32I-NEXT: lw t3, 512(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t0, t0, t3
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: lw a5, 140(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a3, a3, a5
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: xor a1, a2, t1
; RV32I-NEXT: xor a2, s2, s3
-; RV32I-NEXT: xor t1, t4, t5
-; RV32I-NEXT: xor a7, a7, t0
+; RV32I-NEXT: xor a5, t4, t5
+; RV32I-NEXT: xor t0, t2, t0
; RV32I-NEXT: xor a3, a4, a3
-; RV32I-NEXT: lw a4, 716(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 732(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a0, a4
-; RV32I-NEXT: lw a4, 720(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 736(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a4, a1, a4
-; RV32I-NEXT: lw a1, 704(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 720(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a2, a2, a1
+; RV32I-NEXT: lw a1, 724(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a5, a5, a1
+; RV32I-NEXT: lw a1, 728(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t0, t0, a1
; RV32I-NEXT: lw a1, 708(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t0, t1, a1
-; RV32I-NEXT: lw a1, 712(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a7, a7, a1
-; RV32I-NEXT: lw a1, 692(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t1, a3, a1
-; RV32I-NEXT: srli a1, s1, 1
-; RV32I-NEXT: lw s2, 728(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, s1, s2
-; RV32I-NEXT: and a1, a1, s2
-; RV32I-NEXT: slli a3, a3, 1
-; RV32I-NEXT: or a1, a1, a3
+; RV32I-NEXT: srli t2, s1, 1
+; RV32I-NEXT: lw t3, 756(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a1, s1, t3
+; RV32I-NEXT: slli a1, a1, 1
+; RV32I-NEXT: and a3, t2, t3
+; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: xor a0, a4, a0
-; RV32I-NEXT: sw a0, 720(sp) # 4-byte Folded Spill
-; RV32I-NEXT: srli a0, t6, 1
-; RV32I-NEXT: and a3, t6, s2
-; RV32I-NEXT: and a0, a0, s2
-; RV32I-NEXT: slli a3, a3, 1
-; RV32I-NEXT: or t5, a0, a3
-; RV32I-NEXT: xor a0, t0, a2
-; RV32I-NEXT: sw a0, 716(sp) # 4-byte Folded Spill
-; RV32I-NEXT: srli a0, a7, 8
-; RV32I-NEXT: lw a3, 740(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a0, 736(sp) # 4-byte Folded Spill
+; RV32I-NEXT: srli a4, t6, 1
+; RV32I-NEXT: and a0, t6, t3
+; RV32I-NEXT: slli a0, a0, 1
+; RV32I-NEXT: and a3, a4, t3
+; RV32I-NEXT: or t5, a3, a0
+; RV32I-NEXT: xor a2, a5, a2
+; RV32I-NEXT: sw a2, 732(sp) # 4-byte Folded Spill
+; RV32I-NEXT: srli a0, t0, 8
+; RV32I-NEXT: lw a3, 752(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a0, a0, a3
-; RV32I-NEXT: srli a2, a7, 24
+; RV32I-NEXT: srli a2, t0, 24
; RV32I-NEXT: or a2, a0, a2
-; RV32I-NEXT: slli a0, a7, 24
-; RV32I-NEXT: and a4, a7, a3
-; RV32I-NEXT: slli a4, a4, 8
-; RV32I-NEXT: or a4, a0, a4
+; RV32I-NEXT: slli a0, t0, 24
+; RV32I-NEXT: and a5, t0, a3
+; RV32I-NEXT: slli a5, a5, 8
+; RV32I-NEXT: or a5, a0, a5
; RV32I-NEXT: srli a0, t1, 8
; RV32I-NEXT: and a0, a0, a3
-; RV32I-NEXT: srli a7, t1, 24
-; RV32I-NEXT: or a7, a0, a7
-; RV32I-NEXT: slli a0, t1, 24
-; RV32I-NEXT: and t0, t1, a3
-; RV32I-NEXT: slli t0, t0, 8
+; RV32I-NEXT: srli t0, t1, 24
; RV32I-NEXT: or t0, a0, t0
-; RV32I-NEXT: srli a0, a5, 1
-; RV32I-NEXT: and a5, a5, s2
-; RV32I-NEXT: and a0, a0, s2
-; RV32I-NEXT: slli a5, a5, 1
-; RV32I-NEXT: or a0, a0, a5
-; RV32I-NEXT: srli a5, a5, 31
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli t1, a1, 31
-; RV32I-NEXT: and a3, a5, t1
-; RV32I-NEXT: sw a3, 708(sp) # 4-byte Folded Spill
-; RV32I-NEXT: srli a5, a6, 1
-; RV32I-NEXT: and a6, a6, s2
-; RV32I-NEXT: and a5, a5, s2
+; RV32I-NEXT: slli a0, t1, 24
+; RV32I-NEXT: and t1, t1, a3
+; RV32I-NEXT: slli t1, t1, 8
+; RV32I-NEXT: or t1, a0, t1
+; RV32I-NEXT: srli a0, a6, 1
+; RV32I-NEXT: and a6, a6, t3
+; RV32I-NEXT: and a0, a0, t3
; RV32I-NEXT: slli a6, a6, 1
-; RV32I-NEXT: or t3, a5, a6
-; RV32I-NEXT: srli a5, a6, 31
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, t5, 31
-; RV32I-NEXT: and a3, a5, a6
-; RV32I-NEXT: sw a3, 704(sp) # 4-byte Folded Spill
-; RV32I-NEXT: or a2, a4, a2
-; RV32I-NEXT: sw a2, 700(sp) # 4-byte Folded Spill
-; RV32I-NEXT: or a2, t0, a7
-; RV32I-NEXT: sw a2, 712(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t2, t2, 31
+; RV32I-NEXT: or a0, a0, a6
+; RV32I-NEXT: srli a6, a6, 31
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: and a3, a6, t2
+; RV32I-NEXT: sw a3, 724(sp) # 4-byte Folded Spill
+; RV32I-NEXT: srli a6, a7, 1
+; RV32I-NEXT: and a7, a7, t3
+; RV32I-NEXT: and a6, a6, t3
+; RV32I-NEXT: slli a7, a7, 1
+; RV32I-NEXT: slli a4, a4, 31
+; RV32I-NEXT: or t3, a6, a7
+; RV32I-NEXT: srli a6, a7, 31
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: and a3, a6, a4
+; RV32I-NEXT: sw a3, 720(sp) # 4-byte Folded Spill
+; RV32I-NEXT: or a2, a5, a2
+; RV32I-NEXT: sw a2, 716(sp) # 4-byte Folded Spill
+; RV32I-NEXT: or a2, t1, t0
+; RV32I-NEXT: sw a2, 728(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a2, a0, 2
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 696(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 712(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a2, a0, 4
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 2
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 688(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 704(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a2, a0, 8
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 3
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 680(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 696(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a2, a0, 16
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 4
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 676(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 692(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a2, a0, 32
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 5
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 672(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 688(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a2, a0, 64
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 6
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 684(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 700(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a2, a0, 128
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 7
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 656(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 672(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a2, a0, 256
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 8
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 652(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 668(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a2, a0, 512
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 9
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 664(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 680(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a2, a0, 1024
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 10
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 692(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a3, 440(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a2, 708(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a3, 460(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a2, a0, a3
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 11
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 636(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 652(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a5, 1
; RV32I-NEXT: and a2, a0, a5
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 12
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 628(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 644(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a6, 2
; RV32I-NEXT: and a2, a0, a6
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 13
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 644(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 660(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a7, 4
; RV32I-NEXT: and a2, a0, a7
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 14
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 660(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 676(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui s3, 8
; RV32I-NEXT: and a2, a0, s3
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 15
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 668(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 684(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui t1, 16
; RV32I-NEXT: and a2, a0, t1
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 16
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 612(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 628(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui t2, 32
; RV32I-NEXT: and a2, a0, t2
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 17
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 604(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 620(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui t4, 64
; RV32I-NEXT: and a2, a0, t4
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 18
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 620(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 636(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui t6, 128
; RV32I-NEXT: and a2, a0, t6
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 19
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 632(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 648(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui s0, 256
; RV32I-NEXT: and a2, a0, s0
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 20
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 640(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui s4, 512
-; RV32I-NEXT: and a2, a0, s4
+; RV32I-NEXT: sw a2, 656(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui s2, 512
+; RV32I-NEXT: and a2, a0, s2
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 21
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 648(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui s5, 1024
-; RV32I-NEXT: and a2, a0, s5
+; RV32I-NEXT: sw a2, 664(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui s4, 1024
+; RV32I-NEXT: and a2, a0, s4
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 22
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 592(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui s7, 2048
-; RV32I-NEXT: and a2, a0, s7
+; RV32I-NEXT: sw a2, 608(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui s5, 2048
+; RV32I-NEXT: and a2, a0, s5
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 23
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 588(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui s11, 4096
-; RV32I-NEXT: and a2, a0, s11
+; RV32I-NEXT: sw a2, 604(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui s10, 4096
+; RV32I-NEXT: and a2, a0, s10
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 24
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 596(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 612(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a2, 8192
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 25
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 600(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 616(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a2, 16384
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 26
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 608(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 624(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a2, 32768
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 27
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 616(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 632(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a2, 65536
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 28
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 624(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 640(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a2, 131072
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, a1, 29
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: sw a2, 584(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 600(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a2, a0, 1
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: and a2, a2, a1
-; RV32I-NEXT: sw a2, 576(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 592(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a1, a1, 30
; RV32I-NEXT: lui t0, 262144
; RV32I-NEXT: and a0, a0, t0
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: sw a0, 580(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 596(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a0, t3, 2
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli a1, t5, 1
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: sw a0, 572(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 588(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a0, t3, 4
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli a1, t5, 2
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: sw a0, 568(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 584(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a0, t3, 8
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli a1, t5, 3
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: sw a0, 560(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 576(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a0, t3, 16
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli a1, t5, 4
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: sw a0, 552(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 568(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a0, t3, 32
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli a1, t5, 5
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: sw a0, 548(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 564(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a0, t3, 64
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli a1, t5, 6
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: sw a0, 556(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 572(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a0, t3, 128
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli a1, t5, 7
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: sw a0, 532(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 548(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a0, t3, 256
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli a1, t5, 8
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: sw a0, 528(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 544(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a0, t3, 512
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli a1, t5, 9
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: sw a0, 540(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 556(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a0, t3, 1024
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli a1, t5, 10
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: sw a0, 564(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 580(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, t3, a3
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli a1, t5, 11
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: sw a0, 516(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 532(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, t3, a5
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
@@ -4841,24 +4841,24 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli s1, t5, 13
; RV32I-NEXT: and a0, a0, s1
-; RV32I-NEXT: sw a0, 524(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 540(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, t3, a7
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli a1, t5, 14
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: sw a0, 536(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 552(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, t3, s3
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli a1, t5, 15
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: sw a0, 544(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 560(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, t3, t1
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli a1, t5, 16
-; RV32I-NEXT: and s8, a0, a1
+; RV32I-NEXT: and s7, a0, a1
; RV32I-NEXT: and a0, t3, t2
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
@@ -4868,36 +4868,35 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli a1, t5, 18
-; RV32I-NEXT: and s10, a0, a1
+; RV32I-NEXT: and s8, a0, a1
; RV32I-NEXT: and a0, t3, t6
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli a1, t5, 19
-; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: sw a0, 508(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and s11, a0, a1
; RV32I-NEXT: and a0, t3, s0
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli a1, t5, 20
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: sw a0, 512(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a0, t3, s4
+; RV32I-NEXT: sw a0, 528(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a0, t3, s2
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli s0, t5, 21
; RV32I-NEXT: and a0, a0, s0
-; RV32I-NEXT: sw a0, 520(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a0, t3, s5
+; RV32I-NEXT: sw a0, 536(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a0, t3, s4
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli a1, t5, 22
; RV32I-NEXT: and s0, a0, a1
-; RV32I-NEXT: and a1, t3, s7
+; RV32I-NEXT: and a1, t3, s5
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: slli a4, t5, 23
; RV32I-NEXT: and t6, a1, a4
-; RV32I-NEXT: and a4, t3, s11
+; RV32I-NEXT: and a4, t3, s10
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: slli a5, t5, 24
@@ -4907,25 +4906,25 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: addi a5, a5, -1
; RV32I-NEXT: slli a6, t5, 25
-; RV32I-NEXT: and s4, a5, a6
+; RV32I-NEXT: and s2, a5, a6
; RV32I-NEXT: lui a0, 16384
; RV32I-NEXT: and a6, t3, a0
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a6, a6, -1
; RV32I-NEXT: slli a7, t5, 26
-; RV32I-NEXT: and s5, a6, a7
+; RV32I-NEXT: and s4, a6, a7
; RV32I-NEXT: lui a0, 32768
; RV32I-NEXT: and a7, t3, a0
; RV32I-NEXT: seqz a7, a7
; RV32I-NEXT: addi a7, a7, -1
; RV32I-NEXT: slli t2, t5, 27
-; RV32I-NEXT: and s7, a7, t2
+; RV32I-NEXT: and s5, a7, t2
; RV32I-NEXT: lui a0, 65536
; RV32I-NEXT: and t2, t3, a0
; RV32I-NEXT: seqz t2, t2
; RV32I-NEXT: addi t2, t2, -1
; RV32I-NEXT: slli a3, t5, 28
-; RV32I-NEXT: and s11, t2, a3
+; RV32I-NEXT: and s10, t2, a3
; RV32I-NEXT: lui a0, 131072
; RV32I-NEXT: and a3, t3, a0
; RV32I-NEXT: seqz a3, a3
@@ -4941,122 +4940,121 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: seqz t4, t4
; RV32I-NEXT: addi t4, t4, -1
; RV32I-NEXT: and t4, t4, t5
-; RV32I-NEXT: lw a0, 696(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 576(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 712(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 592(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t5, a1, a0
-; RV32I-NEXT: lw a0, 688(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 680(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 704(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 696(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a7, a0, a1
-; RV32I-NEXT: lw a0, 676(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 672(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 692(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 688(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t0, a0, a1
-; RV32I-NEXT: lw a0, 656(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 652(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 672(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 668(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t1, a0, a1
-; RV32I-NEXT: lw a0, 636(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a3, 628(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 652(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 644(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a3, a0, a3
-; RV32I-NEXT: lw a0, 612(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a4, 604(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 628(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 620(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a4, a0, a4
-; RV32I-NEXT: lw a0, 592(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a5, 588(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 608(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 604(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a5, a0, a5
-; RV32I-NEXT: lw a0, 584(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 580(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 600(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 596(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a6, a0, a1
-; RV32I-NEXT: lw a0, 572(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 588(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t3, t3, a0
-; RV32I-NEXT: lw a0, 568(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 560(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 584(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 576(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: lw a1, 552(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 548(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 568(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 564(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: lw a2, 532(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw ra, 528(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 548(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 544(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a2, a2, ra
-; RV32I-NEXT: lw ra, 516(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 532(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor s9, ra, s9
-; RV32I-NEXT: xor s3, s8, s3
+; RV32I-NEXT: xor s3, s7, s3
; RV32I-NEXT: xor t6, s0, t6
; RV32I-NEXT: xor t2, t2, t4
; RV32I-NEXT: xor a7, t5, a7
-; RV32I-NEXT: lw t4, 684(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t4, 700(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t0, t0, t4
-; RV32I-NEXT: lw t4, 664(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t4, 680(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t1, t1, t4
-; RV32I-NEXT: lw t4, 644(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t4, 660(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t4, a3, t4
-; RV32I-NEXT: lw a3, 620(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 636(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a4, a4, a3
-; RV32I-NEXT: lw a3, 596(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 612(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a5, a5, a3
-; RV32I-NEXT: lw a3, 708(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 724(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a3, a6, a3
; RV32I-NEXT: xor a6, t3, a0
-; RV32I-NEXT: lw a0, 556(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 572(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a1, a1, a0
-; RV32I-NEXT: lw a0, 540(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 556(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a2, a2, a0
-; RV32I-NEXT: lw a0, 524(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 540(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t3, s9, a0
-; RV32I-NEXT: xor t5, s3, s10
+; RV32I-NEXT: xor t5, s3, s8
; RV32I-NEXT: xor t6, t6, s1
-; RV32I-NEXT: lw a0, 704(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 720(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, t2, a0
-; RV32I-NEXT: lw s0, 700(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 716(sp) # 4-byte Folded Reload
; RV32I-NEXT: srli t2, s0, 4
-; RV32I-NEXT: lw s3, 744(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 760(sp) # 4-byte Folded Reload
; RV32I-NEXT: and s0, s0, s3
; RV32I-NEXT: and t2, t2, s3
; RV32I-NEXT: slli s0, s0, 4
; RV32I-NEXT: or t2, t2, s0
-; RV32I-NEXT: lw s1, 712(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 728(sp) # 4-byte Folded Reload
; RV32I-NEXT: srli s0, s1, 4
; RV32I-NEXT: and s1, s1, s3
; RV32I-NEXT: and s0, s0, s3
; RV32I-NEXT: slli s1, s1, 4
; RV32I-NEXT: or s0, s0, s1
; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: lw t0, 692(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t0, 708(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t0, t1, t0
-; RV32I-NEXT: lw t1, 660(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 676(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t1, t4, t1
-; RV32I-NEXT: lw t4, 632(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t4, 648(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a4, a4, t4
-; RV32I-NEXT: lw t4, 600(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t4, 616(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a5, a5, t4
; RV32I-NEXT: xor a1, a6, a1
-; RV32I-NEXT: lw a6, 564(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 580(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a2, a2, a6
-; RV32I-NEXT: lw a6, 536(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 552(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a6, t3, a6
-; RV32I-NEXT: lw t3, 508(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t3, t5, t3
-; RV32I-NEXT: xor t4, t6, s4
+; RV32I-NEXT: xor t3, t5, s11
+; RV32I-NEXT: xor t4, t6, s2
; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: lw t0, 668(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t0, 684(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor t0, t1, t0
-; RV32I-NEXT: lw t1, 640(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 656(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a4, a4, t1
-; RV32I-NEXT: lw t1, 608(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 624(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a5, a5, t1
; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: lw a2, 544(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 560(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a2, a6, a2
-; RV32I-NEXT: lw a6, 512(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 528(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a6, t3, a6
-; RV32I-NEXT: xor t1, t4, s5
+; RV32I-NEXT: xor t1, t4, s4
; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: lw t0, 648(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t0, 664(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a4, a4, t0
-; RV32I-NEXT: lw t0, 616(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t0, 632(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a5, a5, t0
; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: lw a2, 520(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 536(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a2, a6, a2
-; RV32I-NEXT: xor a6, t1, s7
+; RV32I-NEXT: xor a6, t1, s5
; RV32I-NEXT: srli t0, t2, 2
; RV32I-NEXT: and t1, t2, s6
; RV32I-NEXT: and t0, t0, s6
@@ -5068,20 +5066,22 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: slli t2, t2, 2
; RV32I-NEXT: or t1, t1, t2
; RV32I-NEXT: xor a4, a7, a4
-; RV32I-NEXT: lw a7, 624(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a7, 640(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a5, a5, a7
; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: xor a2, a6, s11
+; RV32I-NEXT: xor a2, a6, s10
; RV32I-NEXT: xor a4, a4, a5
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: srli a2, t0, 1
-; RV32I-NEXT: and a5, t0, s2
+; RV32I-NEXT: lw a7, 756(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, t0, a7
; RV32I-NEXT: xor a3, a4, a3
; RV32I-NEXT: srli a4, t1, 1
-; RV32I-NEXT: and a6, t1, s2
-; RV32I-NEXT: and a2, a2, s2
+; RV32I-NEXT: and a6, t1, a7
+; RV32I-NEXT: and a2, a2, a7
; RV32I-NEXT: slli a5, a5, 1
-; RV32I-NEXT: and a4, a4, s2
+; RV32I-NEXT: and a4, a4, a7
+; RV32I-NEXT: mv t0, a7
; RV32I-NEXT: slli a6, a6, 1
; RV32I-NEXT: xor a7, a1, a0
; RV32I-NEXT: or a1, a2, a5
@@ -5089,18 +5089,18 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: srli a2, a3, 8
; RV32I-NEXT: srli a4, a3, 24
; RV32I-NEXT: slli a5, a3, 24
-; RV32I-NEXT: lw t0, 740(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, a3, t0
-; RV32I-NEXT: and a2, a2, t0
+; RV32I-NEXT: lw t1, 752(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a3, a3, t1
+; RV32I-NEXT: and a2, a2, t1
; RV32I-NEXT: or a2, a2, a4
; RV32I-NEXT: srli a4, a7, 8
; RV32I-NEXT: slli a3, a3, 8
; RV32I-NEXT: or a3, a5, a3
; RV32I-NEXT: srli a5, a7, 24
-; RV32I-NEXT: and a4, a4, t0
+; RV32I-NEXT: and a4, a4, t1
; RV32I-NEXT: or a4, a4, a5
; RV32I-NEXT: slli a5, a7, 24
-; RV32I-NEXT: and a6, a7, t0
+; RV32I-NEXT: and a6, a7, t1
; RV32I-NEXT: slli a6, a6, 8
; RV32I-NEXT: or a5, a5, a6
; RV32I-NEXT: lui a6, 349525
@@ -5131,31 +5131,31 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: srli a5, a4, 1
; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: and a2, a2, s2
+; RV32I-NEXT: and a2, a2, t0
; RV32I-NEXT: slli a2, a2, 1
; RV32I-NEXT: or a2, a3, a2
-; RV32I-NEXT: and a3, a4, s2
+; RV32I-NEXT: and a3, a4, t0
; RV32I-NEXT: slli a3, a3, 1
; RV32I-NEXT: or a3, a5, a3
; RV32I-NEXT: srli a2, a2, 1
; RV32I-NEXT: srli a3, a3, 1
-; RV32I-NEXT: lw a4, 720(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 736(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: lw a4, 716(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 732(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: srli a4, a2, 8
; RV32I-NEXT: srli a5, a2, 24
; RV32I-NEXT: slli a6, a2, 24
-; RV32I-NEXT: and a2, a2, t0
-; RV32I-NEXT: and a4, a4, t0
+; RV32I-NEXT: and a2, a2, t1
+; RV32I-NEXT: and a4, a4, t1
; RV32I-NEXT: or a4, a4, a5
; RV32I-NEXT: srli a5, a3, 8
; RV32I-NEXT: slli a2, a2, 8
; RV32I-NEXT: or a2, a6, a2
; RV32I-NEXT: srli a6, a3, 24
-; RV32I-NEXT: and a5, a5, t0
+; RV32I-NEXT: and a5, a5, t1
; RV32I-NEXT: or a5, a5, a6
-; RV32I-NEXT: and a6, a3, t0
+; RV32I-NEXT: and a6, a3, t1
; RV32I-NEXT: slli a3, a3, 24
; RV32I-NEXT: slli a6, a6, 8
; RV32I-NEXT: or a3, a3, a6
@@ -5182,39 +5182,39 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: or a2, a4, a2
; RV32I-NEXT: or a3, a5, a3
; RV32I-NEXT: srli a4, a2, 1
-; RV32I-NEXT: and a2, a2, s2
+; RV32I-NEXT: and a2, a2, t0
; RV32I-NEXT: srli a5, a3, 1
-; RV32I-NEXT: and a3, a3, s2
-; RV32I-NEXT: and a4, a4, s2
-; RV32I-NEXT: and a5, a5, s2
+; RV32I-NEXT: and a3, a3, t0
+; RV32I-NEXT: and a4, a4, t0
+; RV32I-NEXT: and a5, a5, t0
; RV32I-NEXT: slli a2, a2, 1
; RV32I-NEXT: or a2, a4, a2
; RV32I-NEXT: slli a3, a3, 1
; RV32I-NEXT: or a3, a5, a3
-; RV32I-NEXT: lw a4, 732(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 744(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a2, 0(a4)
; RV32I-NEXT: sw a1, 4(a4)
; RV32I-NEXT: sw a3, 8(a4)
; RV32I-NEXT: sw a0, 12(a4)
-; RV32I-NEXT: lw a4, 736(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 748(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a2, 0(a4)
; RV32I-NEXT: sw a1, 4(a4)
; RV32I-NEXT: sw a3, 8(a4)
; RV32I-NEXT: sw a0, 12(a4)
-; RV32I-NEXT: lw ra, 796(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 792(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 788(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 784(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 780(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s4, 776(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s5, 772(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s6, 768(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 764(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 760(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 756(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s10, 752(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s11, 748(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 800
+; RV32I-NEXT: lw ra, 812(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 808(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 804(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 800(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 796(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 792(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s5, 788(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s6, 784(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s7, 780(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s8, 776(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 772(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s10, 768(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s11, 764(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 816
; RV32I-NEXT: ret
;
; RV64I-LABEL: commutative_clmulr_v2i64:
@@ -5235,117 +5235,117 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64I-NEXT: sd s11, 1016(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a5, 1008(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a4, 1000(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s5, a0
-; RV64I-NEXT: srli a5, a2, 24
-; RV64I-NEXT: lui s4, 4080
-; RV64I-NEXT: srli a6, a2, 8
-; RV64I-NEXT: li t4, 255
-; RV64I-NEXT: srli a7, a2, 40
-; RV64I-NEXT: lui s0, 16
+; RV64I-NEXT: mv t3, a1
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: srli a4, a2, 24
+; RV64I-NEXT: lui s7, 4080
+; RV64I-NEXT: srli a5, a2, 8
+; RV64I-NEXT: li a0, 255
+; RV64I-NEXT: srli a6, a2, 40
+; RV64I-NEXT: lui s4, 16
; RV64I-NEXT: srli t0, a2, 56
-; RV64I-NEXT: srliw t1, a2, 24
-; RV64I-NEXT: slli a4, a2, 56
-; RV64I-NEXT: lui t2, 61681
-; RV64I-NEXT: lui ra, 209715
-; RV64I-NEXT: lui s3, 349525
-; RV64I-NEXT: srli s6, a0, 24
-; RV64I-NEXT: srli t3, a0, 8
-; RV64I-NEXT: srli t5, a0, 40
-; RV64I-NEXT: srli t6, a0, 56
-; RV64I-NEXT: srliw s1, a0, 24
-; RV64I-NEXT: slli a0, a0, 56
-; RV64I-NEXT: sd a0, 952(sp) # 8-byte Folded Spill
+; RV64I-NEXT: srliw a7, a2, 24
+; RV64I-NEXT: slli t6, a2, 56
+; RV64I-NEXT: lui t1, 61681
+; RV64I-NEXT: lui t2, 209715
+; RV64I-NEXT: lui s1, 349525
+; RV64I-NEXT: srli s0, a1, 24
+; RV64I-NEXT: srli t4, a1, 8
+; RV64I-NEXT: srli t5, a1, 40
+; RV64I-NEXT: srli s5, a1, 56
+; RV64I-NEXT: srliw s6, a1, 24
+; RV64I-NEXT: slli s2, a1, 56
+; RV64I-NEXT: sd s2, 952(sp) # 8-byte Folded Spill
; RV64I-NEXT: srli s8, a3, 24
; RV64I-NEXT: srli s11, a3, 8
-; RV64I-NEXT: srli s7, a3, 40
+; RV64I-NEXT: srli s2, a3, 40
; RV64I-NEXT: srli s10, a3, 56
-; RV64I-NEXT: and a5, a5, s4
-; RV64I-NEXT: slli s2, t4, 24
-; RV64I-NEXT: and a6, a6, s2
-; RV64I-NEXT: or a6, a6, a5
-; RV64I-NEXT: addi a0, s0, -256
-; RV64I-NEXT: and a5, a7, a0
-; RV64I-NEXT: or a7, a5, t0
-; RV64I-NEXT: and a5, a2, s4
-; RV64I-NEXT: slli t1, t1, 32
-; RV64I-NEXT: addi s9, t2, -241
-; RV64I-NEXT: addi ra, ra, 819
-; RV64I-NEXT: addi t0, s3, 1365
-; RV64I-NEXT: slli a5, a5, 24
-; RV64I-NEXT: or a5, a5, t1
-; RV64I-NEXT: slli t1, s9, 32
-; RV64I-NEXT: add s9, s9, t1
-; RV64I-NEXT: slli t1, ra, 32
-; RV64I-NEXT: add ra, ra, t1
-; RV64I-NEXT: slli t1, t0, 32
-; RV64I-NEXT: add s0, t0, t1
-; RV64I-NEXT: srliw t1, a3, 24
-; RV64I-NEXT: and t0, s6, s4
-; RV64I-NEXT: and t2, t3, s2
-; RV64I-NEXT: or t0, t2, t0
-; RV64I-NEXT: srli t2, a1, 24
-; RV64I-NEXT: and t3, t5, a0
-; RV64I-NEXT: or t3, t3, t6
-; RV64I-NEXT: and t4, s5, s4
-; RV64I-NEXT: slli s1, s1, 32
+; RV64I-NEXT: and a4, a4, s7
+; RV64I-NEXT: slli s3, a0, 24
+; RV64I-NEXT: and a5, a5, s3
+; RV64I-NEXT: or a5, a5, a4
+; RV64I-NEXT: addi a0, s4, -256
+; RV64I-NEXT: and a4, a6, a0
+; RV64I-NEXT: or a6, a4, t0
+; RV64I-NEXT: and a4, a2, s7
+; RV64I-NEXT: slli a7, a7, 32
+; RV64I-NEXT: addi s9, t1, -241
+; RV64I-NEXT: addi ra, t2, 819
+; RV64I-NEXT: addi t0, s1, 1365
+; RV64I-NEXT: slli a4, a4, 24
+; RV64I-NEXT: or a4, a4, a7
+; RV64I-NEXT: slli a7, s9, 32
+; RV64I-NEXT: add s9, s9, a7
+; RV64I-NEXT: slli a7, ra, 32
+; RV64I-NEXT: add ra, ra, a7
+; RV64I-NEXT: slli a7, t0, 32
+; RV64I-NEXT: add s4, t0, a7
+; RV64I-NEXT: srliw t0, a3, 24
+; RV64I-NEXT: and a7, s0, s7
+; RV64I-NEXT: and t1, t4, s3
+; RV64I-NEXT: or a7, t1, a7
+; RV64I-NEXT: srli t1, t3, 24
+; RV64I-NEXT: and t2, t5, a0
+; RV64I-NEXT: or t2, t2, s5
+; RV64I-NEXT: and t4, a1, s7
+; RV64I-NEXT: slli s6, s6, 32
; RV64I-NEXT: slli t4, t4, 24
-; RV64I-NEXT: or t4, t4, s1
-; RV64I-NEXT: srli t5, a1, 8
-; RV64I-NEXT: and t6, s8, s4
-; RV64I-NEXT: mv s6, s2
-; RV64I-NEXT: sd s2, 992(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and s1, s11, s2
-; RV64I-NEXT: or t6, s1, t6
-; RV64I-NEXT: srli s1, a1, 40
-; RV64I-NEXT: and s2, s7, a0
+; RV64I-NEXT: or t4, t4, s6
+; RV64I-NEXT: srli t5, t3, 8
+; RV64I-NEXT: and s0, s8, s7
+; RV64I-NEXT: mv s5, s3
+; RV64I-NEXT: sd s3, 992(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and s1, s11, s3
+; RV64I-NEXT: or s0, s1, s0
+; RV64I-NEXT: srli s1, t3, 40
+; RV64I-NEXT: and s2, s2, a0
; RV64I-NEXT: or s2, s2, s10
-; RV64I-NEXT: and s3, a3, s4
-; RV64I-NEXT: slli t1, t1, 32
+; RV64I-NEXT: and s3, a3, s7
+; RV64I-NEXT: slli t0, t0, 32
; RV64I-NEXT: slli s3, s3, 24
-; RV64I-NEXT: or t1, s3, t1
-; RV64I-NEXT: srli s3, a1, 56
-; RV64I-NEXT: and t2, t2, s4
-; RV64I-NEXT: and t5, t5, s6
-; RV64I-NEXT: or t2, t5, t2
-; RV64I-NEXT: srliw t5, a1, 24
+; RV64I-NEXT: or t0, s3, t0
+; RV64I-NEXT: srli s3, t3, 56
+; RV64I-NEXT: and t1, t1, s7
+; RV64I-NEXT: and t5, t5, s5
+; RV64I-NEXT: or t1, t5, t1
+; RV64I-NEXT: srliw t5, t3, 24
; RV64I-NEXT: and s1, s1, a0
; RV64I-NEXT: or s1, s1, s3
-; RV64I-NEXT: and s3, a1, s4
+; RV64I-NEXT: and s3, t3, s7
; RV64I-NEXT: slli t5, t5, 32
; RV64I-NEXT: slli s3, s3, 24
; RV64I-NEXT: or s3, s3, t5
; RV64I-NEXT: li t5, 1
-; RV64I-NEXT: or a6, a6, a7
-; RV64I-NEXT: slli a7, a3, 56
-; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: or a5, a5, a6
+; RV64I-NEXT: slli a6, a3, 56
+; RV64I-NEXT: mv s5, a0
; RV64I-NEXT: sd a0, 976(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a2, a2, a0
; RV64I-NEXT: slli a2, a2, 40
-; RV64I-NEXT: or a2, a4, a2
-; RV64I-NEXT: slli a4, a1, 56
-; RV64I-NEXT: or t0, t0, t3
+; RV64I-NEXT: or a2, t6, a2
+; RV64I-NEXT: slli t6, t3, 56
+; RV64I-NEXT: or a7, a7, t2
; RV64I-NEXT: slli s6, t5, 11
-; RV64I-NEXT: sd s6, 440(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a0, s5, a0
-; RV64I-NEXT: and a3, a3, s4
-; RV64I-NEXT: and a1, a1, s4
+; RV64I-NEXT: and a0, a1, a0
+; RV64I-NEXT: and a3, a3, s5
+; RV64I-NEXT: and a1, t3, s5
; RV64I-NEXT: slli a0, a0, 40
; RV64I-NEXT: slli a3, a3, 40
; RV64I-NEXT: slli a1, a1, 40
-; RV64I-NEXT: ld t3, 952(sp) # 8-byte Folded Reload
-; RV64I-NEXT: or a0, t3, a0
-; RV64I-NEXT: or t3, t6, s2
-; RV64I-NEXT: or a3, a7, a3
-; RV64I-NEXT: or a7, t2, s1
-; RV64I-NEXT: or a1, a4, a1
-; RV64I-NEXT: or a2, a2, a5
+; RV64I-NEXT: ld t2, 952(sp) # 8-byte Folded Reload
+; RV64I-NEXT: or a0, t2, a0
+; RV64I-NEXT: or t2, s0, s2
+; RV64I-NEXT: or a3, a6, a3
+; RV64I-NEXT: or a6, t1, s1
+; RV64I-NEXT: or a1, t6, a1
+; RV64I-NEXT: or a2, a2, a4
; RV64I-NEXT: or a0, a0, t4
-; RV64I-NEXT: or a3, a3, t1
+; RV64I-NEXT: or a3, a3, t0
; RV64I-NEXT: or a1, a1, s3
-; RV64I-NEXT: or a2, a2, a6
-; RV64I-NEXT: or a0, a0, t0
-; RV64I-NEXT: or a3, a3, t3
-; RV64I-NEXT: or a1, a1, a7
+; RV64I-NEXT: or a2, a2, a5
+; RV64I-NEXT: or a0, a0, a7
+; RV64I-NEXT: or a3, a3, t2
+; RV64I-NEXT: or a1, a1, a6
; RV64I-NEXT: srli a4, a2, 4
; RV64I-NEXT: sd s9, 984(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a2, a2, s9
@@ -5387,911 +5387,911 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64I-NEXT: or a2, a4, a2
; RV64I-NEXT: or a0, a5, a0
; RV64I-NEXT: or a3, a6, a3
-; RV64I-NEXT: or a1, a7, a1
-; RV64I-NEXT: srli a4, a2, 1
-; RV64I-NEXT: sd s0, 960(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, a2, s0
-; RV64I-NEXT: srli a5, a0, 1
-; RV64I-NEXT: and a0, a0, s0
-; RV64I-NEXT: srli a6, a3, 1
-; RV64I-NEXT: and a3, a3, s0
-; RV64I-NEXT: srli a7, a1, 1
-; RV64I-NEXT: and a1, a1, s0
-; RV64I-NEXT: and a4, a4, s0
-; RV64I-NEXT: slli a2, a2, 1
-; RV64I-NEXT: and a5, a5, s0
-; RV64I-NEXT: slli a0, a0, 1
-; RV64I-NEXT: and a6, a6, s0
-; RV64I-NEXT: slli t0, a3, 1
-; RV64I-NEXT: and a7, a7, s0
-; RV64I-NEXT: slli a3, a1, 1
-; RV64I-NEXT: or s0, a4, a2
-; RV64I-NEXT: or s1, a5, a0
-; RV64I-NEXT: srli a2, a0, 63
-; RV64I-NEXT: or a1, a6, t0
-; RV64I-NEXT: or t0, a7, a3
-; RV64I-NEXT: srli a3, a3, 63
-; RV64I-NEXT: slli a4, s0, 1
-; RV64I-NEXT: andi a5, s1, 2
-; RV64I-NEXT: slli a6, s0, 2
-; RV64I-NEXT: andi a7, s1, 4
-; RV64I-NEXT: slli a0, s0, 3
-; RV64I-NEXT: andi t1, s1, 8
-; RV64I-NEXT: slli t2, s0, 4
-; RV64I-NEXT: andi t3, s1, 16
-; RV64I-NEXT: slli t4, s0, 5
-; RV64I-NEXT: andi t6, s1, 32
-; RV64I-NEXT: slli s2, s0, 63
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: and a2, a2, s2
-; RV64I-NEXT: sd a2, 944(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, a1, 63
-; RV64I-NEXT: seqz a3, a3
-; RV64I-NEXT: addi a3, a3, -1
-; RV64I-NEXT: and a2, a3, a2
-; RV64I-NEXT: sd a2, 952(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, s0, 6
-; RV64I-NEXT: seqz a3, a5
-; RV64I-NEXT: addi a3, a3, -1
-; RV64I-NEXT: and a3, a3, a4
-; RV64I-NEXT: sd a3, 456(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a3, s1, 64
-; RV64I-NEXT: seqz a4, a7
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: and a4, a4, a6
-; RV64I-NEXT: sd a4, 448(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a4, s0, 7
-; RV64I-NEXT: seqz a5, t1
+; RV64I-NEXT: or a4, a7, a1
+; RV64I-NEXT: srli a6, a2, 1
+; RV64I-NEXT: sd s4, 960(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a5, a2, s4
+; RV64I-NEXT: srli a7, a0, 1
+; RV64I-NEXT: and a0, a0, s4
+; RV64I-NEXT: srli a1, a3, 1
+; RV64I-NEXT: and t0, a3, s4
+; RV64I-NEXT: srli t1, a4, 1
+; RV64I-NEXT: and t2, a4, s4
+; RV64I-NEXT: and a2, a6, s4
+; RV64I-NEXT: slli a3, a5, 1
+; RV64I-NEXT: and a4, a7, s4
+; RV64I-NEXT: slli a5, a0, 1
+; RV64I-NEXT: slli a0, a6, 63
+; RV64I-NEXT: and a6, a1, s4
+; RV64I-NEXT: slli a7, t0, 1
+; RV64I-NEXT: and t6, t1, s4
+; RV64I-NEXT: slli t0, t2, 1
+; RV64I-NEXT: slli a1, a1, 63
+; RV64I-NEXT: or a2, a2, a3
+; RV64I-NEXT: or a4, a4, a5
+; RV64I-NEXT: srli a5, a5, 63
+; RV64I-NEXT: or t1, a6, a7
+; RV64I-NEXT: or t6, t6, t0
+; RV64I-NEXT: srli a6, t0, 63
+; RV64I-NEXT: slli a7, a2, 1
+; RV64I-NEXT: andi t0, a4, 2
+; RV64I-NEXT: slli a3, a2, 2
+; RV64I-NEXT: andi t2, a4, 4
+; RV64I-NEXT: slli t3, a2, 3
+; RV64I-NEXT: andi t4, a4, 8
+; RV64I-NEXT: slli s0, a2, 4
+; RV64I-NEXT: andi s1, a4, 16
+; RV64I-NEXT: slli s2, a2, 5
+; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: addi a5, a5, -1
; RV64I-NEXT: and a0, a5, a0
-; RV64I-NEXT: sd a0, 912(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a5, s1, 128
-; RV64I-NEXT: seqz a6, t3
+; RV64I-NEXT: sd a0, 944(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a0, a4, 32
+; RV64I-NEXT: seqz a5, a6
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: and a1, a5, a1
+; RV64I-NEXT: sd a1, 952(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a1, a2, 6
+; RV64I-NEXT: seqz a5, t0
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: and a5, a5, a7
+; RV64I-NEXT: sd a5, 448(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a5, a4, 64
+; RV64I-NEXT: seqz a6, t2
; RV64I-NEXT: addi a6, a6, -1
-; RV64I-NEXT: and a0, a6, t2
-; RV64I-NEXT: sd a0, 480(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a6, s0, 8
-; RV64I-NEXT: seqz a7, t6
+; RV64I-NEXT: and a3, a6, a3
+; RV64I-NEXT: sd a3, 920(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a6, a2, 7
+; RV64I-NEXT: seqz a7, t4
; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: and a0, a7, t4
-; RV64I-NEXT: sd a0, 472(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a7, s1, 256
-; RV64I-NEXT: seqz a3, a3
-; RV64I-NEXT: addi a3, a3, -1
-; RV64I-NEXT: and a2, a3, a2
-; RV64I-NEXT: sd a2, 928(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, s0, 9
-; RV64I-NEXT: seqz a3, a5
-; RV64I-NEXT: addi a3, a3, -1
-; RV64I-NEXT: and a3, a3, a4
+; RV64I-NEXT: and a3, a7, t3
; RV64I-NEXT: sd a3, 464(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a3, s1, 512
-; RV64I-NEXT: seqz a4, a7
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: and a0, a4, a6
-; RV64I-NEXT: sd a0, 880(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a4, s0, 10
-; RV64I-NEXT: seqz a3, a3
-; RV64I-NEXT: addi a3, a3, -1
-; RV64I-NEXT: and a2, a3, a2
-; RV64I-NEXT: sd a2, 904(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a2, s1, 1024
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: and a2, a2, a4
-; RV64I-NEXT: sd a2, 936(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, s6
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 11
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 856(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 1
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 12
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 848(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 2
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 13
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 872(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 4
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 14
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 896(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 8
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 15
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 920(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 16
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 16
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 808(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 32
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 17
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 792(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 64
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 18
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 824(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 128
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 19
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 840(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 256
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 20
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 864(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 512
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 21
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 888(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 1024
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 22
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 744(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 2048
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 23
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 736(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 4096
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 24
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 768(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 8192
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 25
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 784(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 16384
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 26
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 800(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 32768
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 27
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 816(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 65536
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 28
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 832(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 131072
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 29
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 680(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a2, 262144
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 30
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 664(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sraiw a2, s1, 31
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 31
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 704(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 32
-; RV64I-NEXT: sd a2, 432(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 32
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 720(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 33
-; RV64I-NEXT: sd a2, 424(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, a2
-; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: andi a7, a4, 128
+; RV64I-NEXT: seqz t0, s1
+; RV64I-NEXT: addi t0, t0, -1
+; RV64I-NEXT: and a3, t0, s0
+; RV64I-NEXT: sd a3, 896(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli t0, a2, 8
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: and a0, a0, s2
+; RV64I-NEXT: sd a0, 456(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a0, a4, 256
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: and a1, a5, a1
+; RV64I-NEXT: sd a1, 928(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a1, a2, 9
+; RV64I-NEXT: seqz a5, a7
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 880(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a5, a4, 512
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: and a0, a0, t0
+; RV64I-NEXT: sd a0, 864(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, a2, 10
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: and a1, a5, a1
+; RV64I-NEXT: sd a1, 904(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a1, a4, 1024
+; RV64I-NEXT: seqz a1, a1
+; RV64I-NEXT: addi a1, a1, -1
+; RV64I-NEXT: and a0, a1, a0
+; RV64I-NEXT: sd a0, 936(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, s6
+; RV64I-NEXT: mv s1, s6
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 11
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 840(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 1
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 12
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 832(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 2
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 13
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 856(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 4
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 14
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 888(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 8
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 15
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 912(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 16
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 16
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 792(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 32
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 17
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 776(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 64
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 18
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 808(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 128
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 19
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 824(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 256
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 20
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 848(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 512
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 21
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 872(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 1024
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 22
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 728(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 2048
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 23
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 720(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 4096
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 24
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 752(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 8192
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 25
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 768(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 16384
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 26
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 784(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 32768
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 27
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 800(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 65536
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 28
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 816(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 131072
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 29
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 664(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, 262144
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 30
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 648(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sraiw a0, a4, 31
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 31
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 688(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 32
+; RV64I-NEXT: sd a0, 440(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 32
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 704(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 33
+; RV64I-NEXT: sd a0, 432(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 33
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 712(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 34
+; RV64I-NEXT: sd a0, 424(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 34
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 736(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 35
+; RV64I-NEXT: sd a0, 416(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 35
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 744(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 36
+; RV64I-NEXT: sd a0, 408(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 36
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 760(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 37
+; RV64I-NEXT: sd a0, 400(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 37
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 592(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 38
+; RV64I-NEXT: sd a0, 392(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 38
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 576(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 39
+; RV64I-NEXT: sd a0, 384(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 39
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 624(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 40
+; RV64I-NEXT: sd a0, 376(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 40
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 632(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s0, t5, 41
+; RV64I-NEXT: and a0, a4, s0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 41
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 640(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 42
+; RV64I-NEXT: sd a0, 360(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, a2, 42
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 656(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a1, t5, 43
+; RV64I-NEXT: and a0, a4, a1
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a5, a2, 43
+; RV64I-NEXT: and a0, a0, a5
+; RV64I-NEXT: sd a0, 672(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, t5, 44
+; RV64I-NEXT: and a5, a4, a0
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 44
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 680(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli ra, t5, 45
+; RV64I-NEXT: and a5, a4, ra
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 45
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 696(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s10, t5, 46
+; RV64I-NEXT: and a5, a4, s10
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 46
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 536(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s9, t5, 47
+; RV64I-NEXT: and a5, a4, s9
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 47
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 528(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s8, t5, 48
+; RV64I-NEXT: and a5, a4, s8
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 48
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 544(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s7, t5, 49
+; RV64I-NEXT: and a5, a4, s7
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 49
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 552(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s6, t5, 50
+; RV64I-NEXT: and a5, a4, s6
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 50
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 560(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s5, t5, 51
+; RV64I-NEXT: and a5, a4, s5
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 51
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 568(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli t2, t5, 52
+; RV64I-NEXT: and a5, a4, t2
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 52
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 584(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli t0, t5, 53
+; RV64I-NEXT: and a5, a4, t0
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 53
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 600(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a7, t5, 54
+; RV64I-NEXT: and a5, a4, a7
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 54
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: sd a3, 616(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a3, t5, 55
+; RV64I-NEXT: and a5, a4, a3
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 55
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: sd a5, 608(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s4, t5, 56
+; RV64I-NEXT: and a5, a4, s4
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 56
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: sd a5, 480(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s3, t5, 57
+; RV64I-NEXT: and a5, a4, s3
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 57
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: sd a5, 472(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s2, t5, 58
+; RV64I-NEXT: and a5, a4, s2
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 58
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: sd a5, 488(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli t4, t5, 59
+; RV64I-NEXT: and a5, a4, t4
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 59
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: sd a5, 496(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli t3, t5, 60
+; RV64I-NEXT: and a5, a4, t3
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 60
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: sd a5, 504(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s11, t5, 61
+; RV64I-NEXT: and a5, a4, s11
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, a2, 61
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: sd a5, 512(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a6, t5, 62
+; RV64I-NEXT: andi a5, a4, 1
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: and t5, a5, a2
+; RV64I-NEXT: slli a2, a2, 62
+; RV64I-NEXT: and a4, a4, a6
+; RV64I-NEXT: seqz a4, a4
+; RV64I-NEXT: addi a4, a4, -1
+; RV64I-NEXT: and a2, a4, a2
+; RV64I-NEXT: sd a2, 520(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a2, t6, 2
+; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 33
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 728(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 34
-; RV64I-NEXT: sd a2, 416(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 1
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 336(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a2, t6, 4
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 34
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 752(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 35
-; RV64I-NEXT: sd a2, 408(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 2
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 352(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a2, t6, 8
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 35
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 760(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 36
-; RV64I-NEXT: sd a2, 400(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 3
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 328(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a2, t6, 16
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 36
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 776(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 37
-; RV64I-NEXT: sd a2, 384(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 4
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 312(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a2, t6, 32
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 37
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 608(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 38
-; RV64I-NEXT: sd a2, 376(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 5
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 296(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a2, t6, 64
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 38
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 592(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 39
+; RV64I-NEXT: slli a4, t1, 6
+; RV64I-NEXT: and a2, a2, a4
; RV64I-NEXT: sd a2, 368(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: andi a2, t6, 128
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 39
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 640(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 40
-; RV64I-NEXT: sd a2, 352(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 7
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 280(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a2, t6, 256
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 40
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 648(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 41
-; RV64I-NEXT: sd a2, 328(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, s1, a2
+; RV64I-NEXT: slli a4, t1, 8
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 264(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a2, t6, 512
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 41
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 656(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli ra, t5, 42
-; RV64I-NEXT: and a2, s1, ra
+; RV64I-NEXT: slli a4, t1, 9
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 304(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a2, t6, 1024
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, s0, 42
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 672(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a3, t5, 43
-; RV64I-NEXT: and a2, s1, a3
+; RV64I-NEXT: slli a4, t1, 10
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 344(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a2, t6, s1
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a4, s0, 43
+; RV64I-NEXT: slli a4, t1, 11
; RV64I-NEXT: and a2, a2, a4
-; RV64I-NEXT: sd a2, 688(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a2, t5, 44
-; RV64I-NEXT: and a4, s1, a2
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 44
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 696(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s10, t5, 45
-; RV64I-NEXT: and a4, s1, s10
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 45
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 712(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s9, t5, 46
-; RV64I-NEXT: and a4, s1, s9
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 46
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 552(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s8, t5, 47
-; RV64I-NEXT: and a4, s1, s8
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 47
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 544(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s7, t5, 48
-; RV64I-NEXT: and a4, s1, s7
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 48
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 560(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s6, t5, 49
-; RV64I-NEXT: and a4, s1, s6
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 49
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 568(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s5, t5, 50
-; RV64I-NEXT: and a4, s1, s5
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 50
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 576(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s4, t5, 51
-; RV64I-NEXT: and a4, s1, s4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 51
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 584(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s3, t5, 52
-; RV64I-NEXT: and a4, s1, s3
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 52
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 600(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a7, t5, 53
-; RV64I-NEXT: and a4, s1, a7
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 53
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 616(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a6, t5, 54
-; RV64I-NEXT: and a4, s1, a6
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 54
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 632(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a0, t5, 55
-; RV64I-NEXT: and a4, s1, a0
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 55
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 624(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s2, t5, 56
-; RV64I-NEXT: and a4, s1, s2
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 56
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 496(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli t6, t5, 57
-; RV64I-NEXT: and a4, s1, t6
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 57
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 488(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli t4, t5, 58
-; RV64I-NEXT: and a4, s1, t4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 58
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 504(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli t3, t5, 59
-; RV64I-NEXT: and a4, s1, t3
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 59
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 512(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli t2, t5, 60
-; RV64I-NEXT: and a4, s1, t2
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 60
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 520(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s11, t5, 61
-; RV64I-NEXT: and a4, s1, s11
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s0, 61
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 528(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli t1, t5, 62
-; RV64I-NEXT: andi a4, s1, 1
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: and t5, a4, s0
-; RV64I-NEXT: slli s0, s0, 62
-; RV64I-NEXT: and a4, s1, t1
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: and a4, a4, s0
-; RV64I-NEXT: sd a4, 536(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, t0, 2
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 1
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 392(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, t0, 4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 2
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 344(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, t0, 8
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 3
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 320(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, t0, 16
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 312(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, t0, 32
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 5
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 296(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, t0, 64
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 6
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 360(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, t0, 128
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 7
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 280(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, t0, 256
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 8
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 264(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, t0, 512
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 9
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 304(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, t0, 1024
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 10
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 336(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 440(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 11
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 240(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 1
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 12
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 216(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 2
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 13
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 256(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 4
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 14
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 288(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 8
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 15
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 440(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 16
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 16
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 184(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 32
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 17
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 176(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 64
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 18
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 200(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 128
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 19
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 232(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 256
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 20
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 248(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 512
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 21
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 272(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 1024
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 22
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 152(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 2048
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 23
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 136(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 4096
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 24
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 160(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 8192
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 25
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 168(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 16384
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 26
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 192(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 32768
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 27
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 208(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 65536
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 28
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 224(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 131072
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 29
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 112(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lui a4, 262144
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli s1, a1, 30
-; RV64I-NEXT: and a4, a4, s1
-; RV64I-NEXT: sd a4, 104(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sraiw a4, t0, 31
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 31
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 120(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 432(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 32
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 128(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 424(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 33
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 144(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 416(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 34
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 416(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 408(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 35
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 424(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 400(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 36
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 432(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 384(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 37
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 64(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 376(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 38
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 48(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 368(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 39
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 80(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 352(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli s0, a1, 40
-; RV64I-NEXT: and a4, a4, s0
-; RV64I-NEXT: sd a4, 352(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a4, 328(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, t0, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 41
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 368(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a4, t0, ra
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 42
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: sd a4, 376(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a3, t0, a3
-; RV64I-NEXT: seqz a3, a3
-; RV64I-NEXT: addi a3, a3, -1
-; RV64I-NEXT: slli a4, a1, 43
-; RV64I-NEXT: and a3, a3, a4
-; RV64I-NEXT: sd a3, 384(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, a2
+; RV64I-NEXT: sd a2, 240(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 1
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 44
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 400(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, s10
+; RV64I-NEXT: slli a4, t1, 12
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 216(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 2
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 45
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 408(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, s9
+; RV64I-NEXT: slli a4, t1, 13
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 256(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 4
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 46
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, s8
+; RV64I-NEXT: slli a4, t1, 14
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 288(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 8
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a5, a1, 47
-; RV64I-NEXT: and s10, a2, a5
-; RV64I-NEXT: and a2, t0, s7
+; RV64I-NEXT: slli a4, t1, 15
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 320(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 16
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 48
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, s6
+; RV64I-NEXT: slli a4, t1, 16
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 184(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 32
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 49
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, s5
+; RV64I-NEXT: slli a4, t1, 17
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 176(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 64
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 50
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, s4
+; RV64I-NEXT: slli a4, t1, 18
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 200(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 128
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 19
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 232(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 256
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 51
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 56(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, s3
+; RV64I-NEXT: slli a4, t1, 20
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 248(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 512
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 52
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 72(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, a7
+; RV64I-NEXT: slli a4, t1, 21
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 272(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 1024
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 53
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 88(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, a6
+; RV64I-NEXT: slli a4, t1, 22
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 152(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 2048
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 54
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 328(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, a0
+; RV64I-NEXT: slli a4, t1, 23
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 136(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 4096
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 24
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 160(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 8192
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 25
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 168(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 16384
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 26
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 192(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 32768
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 27
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 208(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 65536
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 28
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 224(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 131072
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 29
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 112(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a2, 262144
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli s1, t1, 30
+; RV64I-NEXT: and a2, a2, s1
+; RV64I-NEXT: sd a2, 104(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sraiw a2, t6, 31
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 31
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 120(sp) # 8-byte Folded Spill
+; RV64I-NEXT: ld a2, 440(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 32
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 128(sp) # 8-byte Folded Spill
+; RV64I-NEXT: ld a2, 432(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 33
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 144(sp) # 8-byte Folded Spill
+; RV64I-NEXT: ld a2, 424(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 34
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 424(sp) # 8-byte Folded Spill
+; RV64I-NEXT: ld a2, 416(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 35
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 432(sp) # 8-byte Folded Spill
+; RV64I-NEXT: ld a2, 408(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, t6, a2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 55
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sd a2, 96(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a2, t0, s2
+; RV64I-NEXT: slli a4, t1, 36
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 440(sp) # 8-byte Folded Spill
+; RV64I-NEXT: ld a2, 400(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 37
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 64(sp) # 8-byte Folded Spill
+; RV64I-NEXT: ld a2, 392(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 38
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 48(sp) # 8-byte Folded Spill
+; RV64I-NEXT: ld a2, 384(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 39
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 80(sp) # 8-byte Folded Spill
+; RV64I-NEXT: ld a2, 376(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 40
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 376(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a2, t6, s0
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli s0, t1, 41
+; RV64I-NEXT: and a2, a2, s0
+; RV64I-NEXT: sd a2, 384(sp) # 8-byte Folded Spill
+; RV64I-NEXT: ld a2, 360(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, t6, a2
+; RV64I-NEXT: seqz a2, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: slli a4, t1, 42
+; RV64I-NEXT: and a2, a2, a4
+; RV64I-NEXT: sd a2, 392(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a1, t6, a1
+; RV64I-NEXT: seqz a1, a1
+; RV64I-NEXT: addi a1, a1, -1
+; RV64I-NEXT: slli a2, t1, 43
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: sd a1, 400(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, a0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, t1, 44
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 408(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, ra
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, t1, 45
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 416(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, s10
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a5, t1, 46
+; RV64I-NEXT: and a0, a0, a5
+; RV64I-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, s9
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a4, t1, 47
+; RV64I-NEXT: and s10, a0, a4
+; RV64I-NEXT: and a0, t6, s8
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, t1, 48
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, s7
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, t1, 49
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, s6
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, t1, 50
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, s5
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, t1, 51
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 56(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, t2
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, t1, 52
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 72(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, t0
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, t1, 53
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 88(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, a7
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, t1, 54
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 360(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, a3
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, t1, 55
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: sd a0, 96(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a0, t6, s4
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: slli a1, t1, 56
+; RV64I-NEXT: and s6, a0, a1
+; RV64I-NEXT: and a1, t6, s3
+; RV64I-NEXT: seqz a1, a1
+; RV64I-NEXT: addi a1, a1, -1
+; RV64I-NEXT: slli a2, t1, 57
+; RV64I-NEXT: and s5, a1, a2
+; RV64I-NEXT: and a2, t6, s2
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli a3, a1, 56
-; RV64I-NEXT: and s6, a2, a3
-; RV64I-NEXT: and a3, t0, t6
-; RV64I-NEXT: seqz a3, a3
-; RV64I-NEXT: addi a3, a3, -1
-; RV64I-NEXT: slli a4, a1, 57
-; RV64I-NEXT: and s5, a3, a4
-; RV64I-NEXT: and a4, t0, t4
+; RV64I-NEXT: slli a4, t1, 58
+; RV64I-NEXT: and s7, a2, a4
+; RV64I-NEXT: and a4, t6, t4
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, a1, 58
-; RV64I-NEXT: and s7, a4, a5
-; RV64I-NEXT: and a5, t0, t3
+; RV64I-NEXT: slli a5, t1, 59
+; RV64I-NEXT: and s8, a4, a5
+; RV64I-NEXT: and a5, t6, t3
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a6, a1, 59
-; RV64I-NEXT: and s8, a5, a6
-; RV64I-NEXT: and a6, t0, t2
-; RV64I-NEXT: seqz a6, a6
-; RV64I-NEXT: addi a6, a6, -1
-; RV64I-NEXT: slli a0, a1, 60
-; RV64I-NEXT: and s9, a6, a0
-; RV64I-NEXT: and a0, t0, s11
-; RV64I-NEXT: seqz a0, a0
-; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: slli s11, a1, 61
-; RV64I-NEXT: and s11, a0, s11
-; RV64I-NEXT: and a0, t0, t1
-; RV64I-NEXT: andi t0, t0, 1
-; RV64I-NEXT: seqz t0, t0
-; RV64I-NEXT: addi t0, t0, -1
-; RV64I-NEXT: and t0, t0, a1
-; RV64I-NEXT: slli a1, a1, 62
-; RV64I-NEXT: seqz a0, a0
-; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: slli a3, t1, 60
+; RV64I-NEXT: and s9, a5, a3
+; RV64I-NEXT: and a3, t6, s11
+; RV64I-NEXT: seqz a3, a3
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: slli s11, t1, 61
+; RV64I-NEXT: and s11, a3, s11
+; RV64I-NEXT: and a3, t6, a6
+; RV64I-NEXT: andi t6, t6, 1
+; RV64I-NEXT: seqz t6, t6
+; RV64I-NEXT: addi t6, t6, -1
+; RV64I-NEXT: and t6, t6, t1
+; RV64I-NEXT: slli t1, t1, 62
+; RV64I-NEXT: seqz a3, a3
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: and a0, a3, t1
; RV64I-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: ld a0, 456(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a0, 448(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s4, t5, a0
-; RV64I-NEXT: ld a0, 912(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld a1, 448(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t3, a1, a0
-; RV64I-NEXT: ld a0, 480(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld a1, 472(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t4, a0, a1
-; RV64I-NEXT: ld a0, 880(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a0, 920(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld a1, 464(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t5, a1, a0
-; RV64I-NEXT: ld a0, 856(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld a1, 848(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t6, a0, a1
-; RV64I-NEXT: ld a0, 808(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 792(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t2, a0, a1
+; RV64I-NEXT: ld a0, 896(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 456(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t3, a0, a1
+; RV64I-NEXT: ld a0, 880(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 864(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t4, a0, a1
+; RV64I-NEXT: ld a0, 840(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 832(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t5, a0, a1
+; RV64I-NEXT: ld a0, 792(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 776(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s0, a0, s0
-; RV64I-NEXT: ld a0, 744(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 736(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a0, 728(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 720(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s1, a0, s1
-; RV64I-NEXT: ld a0, 680(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld a1, 664(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a0, 664(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 648(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s2, a0, a1
-; RV64I-NEXT: ld a0, 608(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld a1, 592(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a0, 592(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 576(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s3, a0, a1
-; RV64I-NEXT: ld a0, 552(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld a1, 544(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a0, 536(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 528(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t0, a0, a1
+; RV64I-NEXT: ld a0, 480(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 472(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t1, a0, a1
-; RV64I-NEXT: ld a0, 496(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld a1, 488(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t2, a0, a1
-; RV64I-NEXT: ld a0, 392(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t0, t0, a0
-; RV64I-NEXT: ld a0, 344(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld a1, 320(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a0, 336(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t6, t6, a0
+; RV64I-NEXT: ld a0, 352(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 328(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ld a1, 312(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld a2, 296(sp) # 8-byte Folded Reload
@@ -6317,62 +6317,62 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64I-NEXT: ld ra, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s10, ra, s10
; RV64I-NEXT: xor s5, s6, s5
-; RV64I-NEXT: xor t3, s4, t3
+; RV64I-NEXT: xor t2, s4, t2
; RV64I-NEXT: ld s4, 928(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t4, t4, s4
+; RV64I-NEXT: xor t3, t3, s4
; RV64I-NEXT: ld s4, 904(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t4, t4, s4
+; RV64I-NEXT: ld s4, 856(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t5, t5, s4
-; RV64I-NEXT: ld s4, 872(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t6, t6, s4
-; RV64I-NEXT: ld s4, 824(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 808(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s0, s0, s4
-; RV64I-NEXT: ld s4, 768(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 752(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s1, s1, s4
-; RV64I-NEXT: ld s4, 704(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 688(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s2, s2, s4
-; RV64I-NEXT: ld s4, 640(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 624(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s3, s3, s4
-; RV64I-NEXT: ld s4, 560(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 544(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t0, t0, s4
+; RV64I-NEXT: ld s4, 488(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t1, t1, s4
-; RV64I-NEXT: ld s4, 504(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t2, t2, s4
-; RV64I-NEXT: xor a0, t0, a0
-; RV64I-NEXT: ld t0, 360(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor a1, a1, t0
-; RV64I-NEXT: ld t0, 304(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor a2, a2, t0
-; RV64I-NEXT: ld t0, 256(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor a3, a3, t0
-; RV64I-NEXT: ld t0, 200(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor a4, a4, t0
-; RV64I-NEXT: ld t0, 160(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor a5, a5, t0
-; RV64I-NEXT: ld t0, 120(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor a6, a6, t0
-; RV64I-NEXT: ld t0, 80(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor a7, a7, t0
-; RV64I-NEXT: ld t0, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t0, s10, t0
+; RV64I-NEXT: xor a0, t6, a0
+; RV64I-NEXT: ld t6, 368(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a1, a1, t6
+; RV64I-NEXT: ld t6, 304(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a2, a2, t6
+; RV64I-NEXT: ld t6, 256(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a3, a3, t6
+; RV64I-NEXT: ld t6, 200(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a4, a4, t6
+; RV64I-NEXT: ld t6, 160(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a5, a5, t6
+; RV64I-NEXT: ld t6, 120(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a6, a6, t6
+; RV64I-NEXT: ld t6, 80(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a7, a7, t6
+; RV64I-NEXT: ld t6, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t6, s10, t6
; RV64I-NEXT: xor s4, s5, s7
-; RV64I-NEXT: xor t3, t3, t4
-; RV64I-NEXT: ld t4, 936(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t2, t2, t3
+; RV64I-NEXT: ld t3, 936(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t3, t4, t3
+; RV64I-NEXT: ld t4, 888(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t4, t5, t4
-; RV64I-NEXT: ld t5, 896(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t5, t6, t5
-; RV64I-NEXT: ld t6, 840(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t6, s0, t6
-; RV64I-NEXT: ld s0, 784(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld t5, 824(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t5, s0, t5
+; RV64I-NEXT: ld s0, 768(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s0, s1, s0
-; RV64I-NEXT: ld s1, 720(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 704(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s1, s2, s1
-; RV64I-NEXT: ld s2, 648(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 632(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s2, s3, s2
-; RV64I-NEXT: ld s3, 568(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 552(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t0, t0, s3
+; RV64I-NEXT: ld s3, 496(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t1, t1, s3
-; RV64I-NEXT: ld s3, 512(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t2, t2, s3
; RV64I-NEXT: xor a0, a0, a1
-; RV64I-NEXT: ld a1, 336(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 344(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a1, a2, a1
; RV64I-NEXT: ld a2, 288(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a2, a3, a2
@@ -6382,28 +6382,28 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64I-NEXT: xor a4, a5, a4
; RV64I-NEXT: ld a5, 128(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a5, a6, a5
-; RV64I-NEXT: ld a6, 352(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a6, 376(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a6, a7, a6
; RV64I-NEXT: ld a7, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor a7, t0, a7
-; RV64I-NEXT: xor t0, s4, s8
-; RV64I-NEXT: xor t3, t3, t4
-; RV64I-NEXT: ld t4, 920(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a7, t6, a7
+; RV64I-NEXT: xor t6, s4, s8
+; RV64I-NEXT: xor t2, t2, t3
+; RV64I-NEXT: ld t3, 912(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t3, t4, t3
+; RV64I-NEXT: ld t4, 848(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t4, t5, t4
-; RV64I-NEXT: ld t5, 864(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t5, t6, t5
-; RV64I-NEXT: ld t6, 800(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t6, s0, t6
-; RV64I-NEXT: ld s0, 728(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld t5, 784(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t5, s0, t5
+; RV64I-NEXT: ld s0, 712(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s0, s1, s0
-; RV64I-NEXT: ld s1, 656(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 640(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor s1, s2, s1
-; RV64I-NEXT: ld s2, 576(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 560(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t0, t0, s2
+; RV64I-NEXT: ld s2, 504(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t1, t1, s2
-; RV64I-NEXT: ld s2, 520(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t2, t2, s2
; RV64I-NEXT: xor a0, a0, a1
-; RV64I-NEXT: ld a1, 440(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 320(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a1, a2, a1
; RV64I-NEXT: ld a2, 248(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a2, a3, a2
@@ -6411,95 +6411,95 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64I-NEXT: xor a3, a4, a3
; RV64I-NEXT: ld a4, 144(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a4, a5, a4
-; RV64I-NEXT: ld a5, 368(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a5, 384(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a5, a6, a5
; RV64I-NEXT: ld a6, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a6, a7, a6
-; RV64I-NEXT: xor a7, t0, s9
-; RV64I-NEXT: xor t0, t3, t4
-; RV64I-NEXT: ld t3, 888(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t3, t5, t3
-; RV64I-NEXT: ld t4, 816(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t4, t6, t4
-; RV64I-NEXT: ld t5, 752(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a7, t6, s9
+; RV64I-NEXT: xor t2, t2, t3
+; RV64I-NEXT: ld t3, 872(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t3, t4, t3
+; RV64I-NEXT: ld t4, 800(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t4, t5, t4
+; RV64I-NEXT: ld t5, 736(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t5, s0, t5
-; RV64I-NEXT: ld t6, 672(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld t6, 656(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t6, s1, t6
-; RV64I-NEXT: ld s0, 584(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 568(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t0, t0, s0
+; RV64I-NEXT: ld s0, 512(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t1, t1, s0
-; RV64I-NEXT: ld s0, 528(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t2, t2, s0
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ld a1, 272(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a1, a2, a1
; RV64I-NEXT: ld a2, 208(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a2, a3, a2
-; RV64I-NEXT: ld a3, 416(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a3, 424(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a3, a4, a3
-; RV64I-NEXT: ld a4, 376(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a4, 392(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a4, a5, a4
; RV64I-NEXT: ld a5, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a5, a6, a5
; RV64I-NEXT: xor a6, a7, s11
-; RV64I-NEXT: xor a7, t0, t3
-; RV64I-NEXT: ld t0, 832(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t0, t4, t0
-; RV64I-NEXT: ld t3, 760(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a7, t2, t3
+; RV64I-NEXT: ld t2, 816(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t2, t4, t2
+; RV64I-NEXT: ld t3, 744(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t3, t5, t3
-; RV64I-NEXT: ld t4, 688(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld t4, 672(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t4, t6, t4
-; RV64I-NEXT: ld t5, 600(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld t5, 584(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t0, t0, t5
+; RV64I-NEXT: ld t5, 520(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor t1, t1, t5
-; RV64I-NEXT: ld t5, 536(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t2, t2, t5
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ld a1, 224(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a1, a2, a1
-; RV64I-NEXT: ld a2, 424(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a2, 432(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a2, a3, a2
-; RV64I-NEXT: ld a3, 384(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a3, 400(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a3, a4, a3
; RV64I-NEXT: ld a4, 72(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a4, a5, a4
; RV64I-NEXT: ld a5, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a5, a6, a5
-; RV64I-NEXT: xor a6, a7, t0
-; RV64I-NEXT: ld a7, 776(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a6, a7, t2
+; RV64I-NEXT: ld a7, 760(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a7, t3, a7
-; RV64I-NEXT: ld t0, 696(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t0, t4, t0
-; RV64I-NEXT: ld t3, 616(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t1, t1, t3
+; RV64I-NEXT: ld t2, 680(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t2, t4, t2
+; RV64I-NEXT: ld t3, 600(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor t0, t0, t3
; RV64I-NEXT: ld t3, 944(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor t2, t2, t3
+; RV64I-NEXT: xor t1, t1, t3
; RV64I-NEXT: xor a0, a0, a1
-; RV64I-NEXT: ld a1, 432(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 440(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a1, a2, a1
-; RV64I-NEXT: ld a2, 400(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a2, 408(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a2, a3, a2
; RV64I-NEXT: ld a3, 88(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a3, a4, a3
; RV64I-NEXT: ld a4, 952(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a4, a5, a4
; RV64I-NEXT: xor a5, a6, a7
-; RV64I-NEXT: ld a6, 712(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor a6, t0, a6
-; RV64I-NEXT: ld a7, 632(sp) # 8-byte Folded Reload
-; RV64I-NEXT: xor a7, t1, a7
+; RV64I-NEXT: ld a6, 696(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a6, t2, a6
+; RV64I-NEXT: ld a7, 616(sp) # 8-byte Folded Reload
+; RV64I-NEXT: xor a7, t0, a7
; RV64I-NEXT: xor a0, a0, a1
-; RV64I-NEXT: ld a1, 408(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a1, 416(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a1, a2, a1
-; RV64I-NEXT: ld a2, 328(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a2, 360(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a2, a3, a2
; RV64I-NEXT: xor a3, a5, a6
-; RV64I-NEXT: ld a5, 624(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a5, 608(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a5, a7, a5
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ld a1, 96(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a1, a2, a1
; RV64I-NEXT: xor a3, a3, a5
; RV64I-NEXT: xor a0, a0, a1
-; RV64I-NEXT: xor a1, a3, t2
+; RV64I-NEXT: xor a1, a3, t1
; RV64I-NEXT: xor a0, a0, a4
; RV64I-NEXT: srli a2, a1, 40
; RV64I-NEXT: srli a3, a1, 56
@@ -9753,820 +9753,821 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: sw s11, 748(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: sw a3, 736(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: sw a2, 732(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s1, 0(a0)
-; RV32IMZBS-NEXT: lw a3, 4(a0)
+; RV32IMZBS-NEXT: lw t6, 0(a0)
+; RV32IMZBS-NEXT: lw a4, 4(a0)
; RV32IMZBS-NEXT: lw a7, 8(a0)
; RV32IMZBS-NEXT: lw t1, 12(a0)
; RV32IMZBS-NEXT: lw s7, 0(a1)
; RV32IMZBS-NEXT: lw a5, 4(a1)
-; RV32IMZBS-NEXT: lw t0, 8(a1)
+; RV32IMZBS-NEXT: lw a3, 8(a1)
; RV32IMZBS-NEXT: lw t2, 12(a1)
; RV32IMZBS-NEXT: lui a0, 16
; RV32IMZBS-NEXT: lui a1, 61681
; RV32IMZBS-NEXT: lui a2, 209715
-; RV32IMZBS-NEXT: lui a4, 349525
+; RV32IMZBS-NEXT: lui a6, 349525
; RV32IMZBS-NEXT: addi ra, a0, -256
; RV32IMZBS-NEXT: addi s11, a1, -241
; RV32IMZBS-NEXT: addi s10, a2, 819
-; RV32IMZBS-NEXT: addi s5, a4, 1365
-; RV32IMZBS-NEXT: srli s0, a5, 8
-; RV32IMZBS-NEXT: srli a2, a5, 24
-; RV32IMZBS-NEXT: and a4, a5, ra
+; RV32IMZBS-NEXT: addi s5, a6, 1365
+; RV32IMZBS-NEXT: srli a2, a5, 8
+; RV32IMZBS-NEXT: srli a6, a5, 24
+; RV32IMZBS-NEXT: and t5, a5, ra
; RV32IMZBS-NEXT: slli a5, a5, 24
-; RV32IMZBS-NEXT: srli t3, a3, 8
-; RV32IMZBS-NEXT: srli t4, a3, 24
-; RV32IMZBS-NEXT: and a0, a3, ra
-; RV32IMZBS-NEXT: slli a1, a3, 24
+; RV32IMZBS-NEXT: srli s2, a4, 8
+; RV32IMZBS-NEXT: srli s3, a4, 24
+; RV32IMZBS-NEXT: and t3, a4, ra
+; RV32IMZBS-NEXT: slli a4, a4, 24
; RV32IMZBS-NEXT: srli s8, s7, 8
; RV32IMZBS-NEXT: srli s9, s7, 24
; RV32IMZBS-NEXT: and s6, s7, ra
; RV32IMZBS-NEXT: slli s7, s7, 24
-; RV32IMZBS-NEXT: srli a3, s1, 8
-; RV32IMZBS-NEXT: srli t5, s1, 24
-; RV32IMZBS-NEXT: and a6, s1, ra
-; RV32IMZBS-NEXT: slli s1, s1, 24
-; RV32IMZBS-NEXT: srli s3, t2, 8
-; RV32IMZBS-NEXT: and t6, s0, ra
-; RV32IMZBS-NEXT: or a2, t6, a2
+; RV32IMZBS-NEXT: srli a0, t6, 8
+; RV32IMZBS-NEXT: srli t4, t6, 24
+; RV32IMZBS-NEXT: and a1, t6, ra
+; RV32IMZBS-NEXT: slli t6, t6, 24
+; RV32IMZBS-NEXT: srli s1, t2, 8
+; RV32IMZBS-NEXT: and a2, a2, ra
+; RV32IMZBS-NEXT: or a2, a2, a6
; RV32IMZBS-NEXT: srli s4, t2, 24
-; RV32IMZBS-NEXT: slli a4, a4, 8
-; RV32IMZBS-NEXT: or a4, a5, a4
+; RV32IMZBS-NEXT: slli t5, t5, 8
+; RV32IMZBS-NEXT: or t5, a5, t5
; RV32IMZBS-NEXT: and a5, t2, ra
-; RV32IMZBS-NEXT: slli s0, t2, 24
-; RV32IMZBS-NEXT: and t2, t3, ra
-; RV32IMZBS-NEXT: or t2, t2, t4
-; RV32IMZBS-NEXT: srli t3, t1, 8
-; RV32IMZBS-NEXT: slli a0, a0, 8
-; RV32IMZBS-NEXT: or a0, a1, a0
-; RV32IMZBS-NEXT: srli s2, t1, 24
-; RV32IMZBS-NEXT: and a1, s8, ra
-; RV32IMZBS-NEXT: or a1, a1, s9
-; RV32IMZBS-NEXT: and t4, t1, ra
-; RV32IMZBS-NEXT: slli t6, t1, 24
+; RV32IMZBS-NEXT: slli a6, t2, 24
+; RV32IMZBS-NEXT: and t0, s2, ra
+; RV32IMZBS-NEXT: or t2, t0, s3
+; RV32IMZBS-NEXT: srli s2, t1, 8
+; RV32IMZBS-NEXT: slli t3, t3, 8
+; RV32IMZBS-NEXT: or t3, a4, t3
+; RV32IMZBS-NEXT: srli s0, t1, 24
+; RV32IMZBS-NEXT: and a4, s8, ra
+; RV32IMZBS-NEXT: or a4, a4, s9
+; RV32IMZBS-NEXT: and s3, t1, ra
+; RV32IMZBS-NEXT: slli t0, t1, 24
; RV32IMZBS-NEXT: slli s6, s6, 8
; RV32IMZBS-NEXT: or t1, s7, s6
-; RV32IMZBS-NEXT: srli s6, t0, 8
-; RV32IMZBS-NEXT: and a3, a3, ra
-; RV32IMZBS-NEXT: or a3, a3, t5
-; RV32IMZBS-NEXT: srli t5, t0, 24
-; RV32IMZBS-NEXT: slli a6, a6, 8
-; RV32IMZBS-NEXT: or a6, s1, a6
-; RV32IMZBS-NEXT: and s7, t0, ra
-; RV32IMZBS-NEXT: slli s1, t0, 24
-; RV32IMZBS-NEXT: and t0, s3, ra
-; RV32IMZBS-NEXT: or t0, t0, s4
-; RV32IMZBS-NEXT: srli s3, a7, 8
+; RV32IMZBS-NEXT: srli s6, a3, 8
+; RV32IMZBS-NEXT: and a0, a0, ra
+; RV32IMZBS-NEXT: or a0, a0, t4
+; RV32IMZBS-NEXT: srli t4, a3, 24
+; RV32IMZBS-NEXT: slli a1, a1, 8
+; RV32IMZBS-NEXT: or a1, t6, a1
+; RV32IMZBS-NEXT: and s7, a3, ra
+; RV32IMZBS-NEXT: slli t6, a3, 24
+; RV32IMZBS-NEXT: and a3, s1, ra
+; RV32IMZBS-NEXT: or a3, a3, s4
+; RV32IMZBS-NEXT: srli s1, a7, 8
; RV32IMZBS-NEXT: slli a5, a5, 8
-; RV32IMZBS-NEXT: or a5, s0, a5
-; RV32IMZBS-NEXT: srli s0, a7, 24
-; RV32IMZBS-NEXT: and t3, t3, ra
-; RV32IMZBS-NEXT: or t3, t3, s2
+; RV32IMZBS-NEXT: or a5, a6, a5
+; RV32IMZBS-NEXT: srli a6, a7, 24
+; RV32IMZBS-NEXT: and s2, s2, ra
+; RV32IMZBS-NEXT: or s0, s2, s0
; RV32IMZBS-NEXT: and s2, a7, ra
; RV32IMZBS-NEXT: slli a7, a7, 24
-; RV32IMZBS-NEXT: slli t4, t4, 8
+; RV32IMZBS-NEXT: slli s3, s3, 8
; RV32IMZBS-NEXT: and s4, s6, ra
; RV32IMZBS-NEXT: slli s7, s7, 8
-; RV32IMZBS-NEXT: and s3, s3, ra
+; RV32IMZBS-NEXT: and s1, s1, ra
; RV32IMZBS-NEXT: slli s2, s2, 8
-; RV32IMZBS-NEXT: or t4, t6, t4
-; RV32IMZBS-NEXT: or t5, s4, t5
-; RV32IMZBS-NEXT: or t6, s1, s7
-; RV32IMZBS-NEXT: or s0, s3, s0
+; RV32IMZBS-NEXT: or t0, t0, s3
+; RV32IMZBS-NEXT: or t4, s4, t4
+; RV32IMZBS-NEXT: or t6, t6, s7
+; RV32IMZBS-NEXT: or a6, s1, a6
; RV32IMZBS-NEXT: or a7, a7, s2
-; RV32IMZBS-NEXT: or a2, a4, a2
-; RV32IMZBS-NEXT: or a0, a0, t2
-; RV32IMZBS-NEXT: or a1, t1, a1
-; RV32IMZBS-NEXT: or a3, a6, a3
-; RV32IMZBS-NEXT: or a4, a5, t0
-; RV32IMZBS-NEXT: or a5, t4, t3
-; RV32IMZBS-NEXT: or a6, t6, t5
-; RV32IMZBS-NEXT: or a7, a7, s0
-; RV32IMZBS-NEXT: srli t0, a2, 4
+; RV32IMZBS-NEXT: or a2, t5, a2
+; RV32IMZBS-NEXT: or t2, t3, t2
+; RV32IMZBS-NEXT: or a4, t1, a4
+; RV32IMZBS-NEXT: or a0, a1, a0
+; RV32IMZBS-NEXT: or a3, a5, a3
+; RV32IMZBS-NEXT: or a1, t0, s0
+; RV32IMZBS-NEXT: or a5, t6, t4
+; RV32IMZBS-NEXT: or a6, a7, a6
+; RV32IMZBS-NEXT: srli a7, a2, 4
; RV32IMZBS-NEXT: sw s11, 744(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, s11
-; RV32IMZBS-NEXT: srli t1, a0, 4
+; RV32IMZBS-NEXT: srli t0, t2, 4
+; RV32IMZBS-NEXT: and t1, t2, s11
+; RV32IMZBS-NEXT: srli t2, a4, 4
+; RV32IMZBS-NEXT: and a4, a4, s11
+; RV32IMZBS-NEXT: srli t3, a0, 4
; RV32IMZBS-NEXT: and a0, a0, s11
-; RV32IMZBS-NEXT: srli t2, a1, 4
-; RV32IMZBS-NEXT: and a1, a1, s11
-; RV32IMZBS-NEXT: srli t3, a3, 4
+; RV32IMZBS-NEXT: srli t4, a3, 4
; RV32IMZBS-NEXT: and a3, a3, s11
-; RV32IMZBS-NEXT: srli t4, a4, 4
-; RV32IMZBS-NEXT: and a4, a4, s11
-; RV32IMZBS-NEXT: srli t5, a5, 4
+; RV32IMZBS-NEXT: srli t5, a1, 4
+; RV32IMZBS-NEXT: and a1, a1, s11
+; RV32IMZBS-NEXT: srli t6, a5, 4
; RV32IMZBS-NEXT: and a5, a5, s11
-; RV32IMZBS-NEXT: srli t6, a6, 4
+; RV32IMZBS-NEXT: srli s0, a6, 4
; RV32IMZBS-NEXT: and a6, a6, s11
-; RV32IMZBS-NEXT: srli s0, a7, 4
; RV32IMZBS-NEXT: and a7, a7, s11
-; RV32IMZBS-NEXT: and t0, t0, s11
; RV32IMZBS-NEXT: slli a2, a2, 4
-; RV32IMZBS-NEXT: and t1, t1, s11
-; RV32IMZBS-NEXT: slli a0, a0, 4
+; RV32IMZBS-NEXT: and t0, t0, s11
+; RV32IMZBS-NEXT: slli t1, t1, 4
; RV32IMZBS-NEXT: and t2, t2, s11
-; RV32IMZBS-NEXT: slli a1, a1, 4
+; RV32IMZBS-NEXT: slli a4, a4, 4
; RV32IMZBS-NEXT: and t3, t3, s11
-; RV32IMZBS-NEXT: slli a3, a3, 4
+; RV32IMZBS-NEXT: slli a0, a0, 4
; RV32IMZBS-NEXT: and t4, t4, s11
-; RV32IMZBS-NEXT: slli a4, a4, 4
+; RV32IMZBS-NEXT: slli a3, a3, 4
; RV32IMZBS-NEXT: and t5, t5, s11
-; RV32IMZBS-NEXT: slli a5, a5, 4
+; RV32IMZBS-NEXT: slli a1, a1, 4
; RV32IMZBS-NEXT: and t6, t6, s11
-; RV32IMZBS-NEXT: slli a6, a6, 4
+; RV32IMZBS-NEXT: slli a5, a5, 4
; RV32IMZBS-NEXT: and s0, s0, s11
-; RV32IMZBS-NEXT: slli a7, a7, 4
-; RV32IMZBS-NEXT: or a2, t0, a2
-; RV32IMZBS-NEXT: or a0, t1, a0
-; RV32IMZBS-NEXT: or a1, t2, a1
-; RV32IMZBS-NEXT: or a3, t3, a3
-; RV32IMZBS-NEXT: or a4, t4, a4
-; RV32IMZBS-NEXT: or a5, t5, a5
-; RV32IMZBS-NEXT: or a6, t6, a6
-; RV32IMZBS-NEXT: or a7, s0, a7
+; RV32IMZBS-NEXT: slli a6, a6, 4
+; RV32IMZBS-NEXT: or a2, a7, a2
+; RV32IMZBS-NEXT: or a7, t0, t1
+; RV32IMZBS-NEXT: or a4, t2, a4
+; RV32IMZBS-NEXT: or a0, t3, a0
+; RV32IMZBS-NEXT: or a3, t4, a3
+; RV32IMZBS-NEXT: or a1, t5, a1
+; RV32IMZBS-NEXT: or a5, t6, a5
+; RV32IMZBS-NEXT: or a6, s0, a6
; RV32IMZBS-NEXT: srli t0, a2, 2
; RV32IMZBS-NEXT: sw s10, 728(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, s10
-; RV32IMZBS-NEXT: srli t1, a0, 2
+; RV32IMZBS-NEXT: srli t1, a7, 2
+; RV32IMZBS-NEXT: and a7, a7, s10
+; RV32IMZBS-NEXT: srli t2, a4, 2
+; RV32IMZBS-NEXT: and a4, a4, s10
+; RV32IMZBS-NEXT: srli t3, a0, 2
; RV32IMZBS-NEXT: and a0, a0, s10
-; RV32IMZBS-NEXT: srli t2, a1, 2
-; RV32IMZBS-NEXT: and a1, a1, s10
-; RV32IMZBS-NEXT: srli t3, a3, 2
+; RV32IMZBS-NEXT: srli t4, a3, 2
; RV32IMZBS-NEXT: and a3, a3, s10
-; RV32IMZBS-NEXT: srli t4, a4, 2
-; RV32IMZBS-NEXT: and a4, a4, s10
-; RV32IMZBS-NEXT: srli t5, a5, 2
+; RV32IMZBS-NEXT: srli t5, a1, 2
+; RV32IMZBS-NEXT: and a1, a1, s10
+; RV32IMZBS-NEXT: srli t6, a5, 2
; RV32IMZBS-NEXT: and a5, a5, s10
-; RV32IMZBS-NEXT: srli t6, a6, 2
+; RV32IMZBS-NEXT: srli s0, a6, 2
; RV32IMZBS-NEXT: and a6, a6, s10
-; RV32IMZBS-NEXT: srli s0, a7, 2
-; RV32IMZBS-NEXT: and a7, a7, s10
; RV32IMZBS-NEXT: and t0, t0, s10
; RV32IMZBS-NEXT: slli a2, a2, 2
; RV32IMZBS-NEXT: and t1, t1, s10
-; RV32IMZBS-NEXT: slli a0, a0, 2
+; RV32IMZBS-NEXT: slli a7, a7, 2
; RV32IMZBS-NEXT: and t2, t2, s10
-; RV32IMZBS-NEXT: slli a1, a1, 2
+; RV32IMZBS-NEXT: slli a4, a4, 2
; RV32IMZBS-NEXT: and t3, t3, s10
-; RV32IMZBS-NEXT: slli a3, a3, 2
+; RV32IMZBS-NEXT: slli a0, a0, 2
; RV32IMZBS-NEXT: and t4, t4, s10
-; RV32IMZBS-NEXT: slli a4, a4, 2
+; RV32IMZBS-NEXT: slli a3, a3, 2
; RV32IMZBS-NEXT: and t5, t5, s10
-; RV32IMZBS-NEXT: slli a5, a5, 2
+; RV32IMZBS-NEXT: slli a1, a1, 2
; RV32IMZBS-NEXT: and t6, t6, s10
-; RV32IMZBS-NEXT: slli a6, a6, 2
+; RV32IMZBS-NEXT: slli a5, a5, 2
; RV32IMZBS-NEXT: and s0, s0, s10
-; RV32IMZBS-NEXT: slli a7, a7, 2
+; RV32IMZBS-NEXT: slli a6, a6, 2
; RV32IMZBS-NEXT: or a2, t0, a2
-; RV32IMZBS-NEXT: or a0, t1, a0
-; RV32IMZBS-NEXT: or a1, t2, a1
-; RV32IMZBS-NEXT: or a3, t3, a3
-; RV32IMZBS-NEXT: or a4, t4, a4
-; RV32IMZBS-NEXT: or a5, t5, a5
-; RV32IMZBS-NEXT: or a6, t6, a6
-; RV32IMZBS-NEXT: or a7, s0, a7
-; RV32IMZBS-NEXT: srli t0, a2, 1
-; RV32IMZBS-NEXT: sw s5, 724(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: or a7, t1, a7
+; RV32IMZBS-NEXT: or a4, t2, a4
+; RV32IMZBS-NEXT: or t0, t3, a0
+; RV32IMZBS-NEXT: or a0, t4, a3
+; RV32IMZBS-NEXT: or a1, t5, a1
+; RV32IMZBS-NEXT: or a3, t6, a5
+; RV32IMZBS-NEXT: or t5, s0, a6
+; RV32IMZBS-NEXT: srli t4, a2, 1
; RV32IMZBS-NEXT: and a2, a2, s5
-; RV32IMZBS-NEXT: srli t1, a0, 1
+; RV32IMZBS-NEXT: srli a6, a7, 1
+; RV32IMZBS-NEXT: and a7, a7, s5
+; RV32IMZBS-NEXT: srli t6, a4, 1
+; RV32IMZBS-NEXT: and t1, a4, s5
+; RV32IMZBS-NEXT: srli a4, a0, 1
; RV32IMZBS-NEXT: and a0, a0, s5
; RV32IMZBS-NEXT: srli t2, a1, 1
; RV32IMZBS-NEXT: and a1, a1, s5
-; RV32IMZBS-NEXT: srli t3, a3, 1
+; RV32IMZBS-NEXT: srli a5, a3, 1
; RV32IMZBS-NEXT: and a3, a3, s5
-; RV32IMZBS-NEXT: srli t4, a4, 1
-; RV32IMZBS-NEXT: and a4, a4, s5
-; RV32IMZBS-NEXT: srli t5, a5, 1
-; RV32IMZBS-NEXT: and a5, a5, s5
-; RV32IMZBS-NEXT: srli t6, a6, 1
-; RV32IMZBS-NEXT: and a6, a6, s5
-; RV32IMZBS-NEXT: srli s0, a7, 1
-; RV32IMZBS-NEXT: and a7, a7, s5
-; RV32IMZBS-NEXT: and t0, t0, s5
+; RV32IMZBS-NEXT: and t3, t4, s5
; RV32IMZBS-NEXT: slli a2, a2, 1
-; RV32IMZBS-NEXT: and t1, t1, s5
+; RV32IMZBS-NEXT: and s0, a6, s5
+; RV32IMZBS-NEXT: slli s1, a7, 1
+; RV32IMZBS-NEXT: and a7, t6, s5
+; RV32IMZBS-NEXT: slli t1, t1, 1
+; RV32IMZBS-NEXT: and s4, a4, s5
; RV32IMZBS-NEXT: slli a0, a0, 1
; RV32IMZBS-NEXT: and t2, t2, s5
-; RV32IMZBS-NEXT: slli a1, a1, 1
-; RV32IMZBS-NEXT: and t3, t3, s5
-; RV32IMZBS-NEXT: slli s1, a3, 1
-; RV32IMZBS-NEXT: and t4, t4, s5
-; RV32IMZBS-NEXT: slli a4, a4, 1
-; RV32IMZBS-NEXT: and t5, t5, s5
-; RV32IMZBS-NEXT: slli a5, a5, 1
-; RV32IMZBS-NEXT: and t6, t6, s5
-; RV32IMZBS-NEXT: slli a6, a6, 1
-; RV32IMZBS-NEXT: and s0, s0, s5
-; RV32IMZBS-NEXT: slli a3, a7, 1
-; RV32IMZBS-NEXT: or s6, t0, a2
-; RV32IMZBS-NEXT: or s8, t1, a0
-; RV32IMZBS-NEXT: or s7, t2, a1
-; RV32IMZBS-NEXT: srli a0, a0, 31
-; RV32IMZBS-NEXT: or s9, t3, s1
-; RV32IMZBS-NEXT: srli a1, s1, 31
-; RV32IMZBS-NEXT: or a7, t4, a4
-; RV32IMZBS-NEXT: or t1, t5, a5
-; RV32IMZBS-NEXT: or t0, t6, a6
-; RV32IMZBS-NEXT: srli a2, a5, 31
-; RV32IMZBS-NEXT: or t4, s0, a3
-; RV32IMZBS-NEXT: srli s0, a3, 31
+; RV32IMZBS-NEXT: slli a6, a1, 1
+; RV32IMZBS-NEXT: and a1, a5, s5
+; RV32IMZBS-NEXT: mv s8, s5
+; RV32IMZBS-NEXT: slli a3, a3, 1
+; RV32IMZBS-NEXT: or s2, t3, a2
+; RV32IMZBS-NEXT: or s6, s0, s1
+; RV32IMZBS-NEXT: or s3, a7, t1
+; RV32IMZBS-NEXT: or t1, s4, a0
+; RV32IMZBS-NEXT: or t3, t2, a6
+; RV32IMZBS-NEXT: or t2, a1, a3
+; RV32IMZBS-NEXT: srli a0, s2, 8
+; RV32IMZBS-NEXT: srli a1, s2, 24
; RV32IMZBS-NEXT: srli a3, s6, 8
-; RV32IMZBS-NEXT: srli a4, s6, 24
-; RV32IMZBS-NEXT: srli a5, s8, 8
-; RV32IMZBS-NEXT: srli a6, s8, 24
-; RV32IMZBS-NEXT: slli t2, s8, 24
-; RV32IMZBS-NEXT: and t3, s8, ra
-; RV32IMZBS-NEXT: slli t5, s7, 31
-; RV32IMZBS-NEXT: seqz s1, a0
-; RV32IMZBS-NEXT: slli t6, s6, 31
-; RV32IMZBS-NEXT: seqz s2, a1
-; RV32IMZBS-NEXT: srli a0, a7, 8
-; RV32IMZBS-NEXT: and a3, a3, ra
-; RV32IMZBS-NEXT: or a3, a3, a4
-; RV32IMZBS-NEXT: srli a4, a7, 24
-; RV32IMZBS-NEXT: and a1, a5, ra
-; RV32IMZBS-NEXT: or a6, a1, a6
-; RV32IMZBS-NEXT: srli a5, t1, 8
-; RV32IMZBS-NEXT: slli t3, t3, 8
-; RV32IMZBS-NEXT: or a1, t2, t3
-; RV32IMZBS-NEXT: srli t2, t1, 24
-; RV32IMZBS-NEXT: and a0, a0, ra
-; RV32IMZBS-NEXT: or a0, a0, a4
-; RV32IMZBS-NEXT: slli t3, t1, 24
-; RV32IMZBS-NEXT: and a4, a5, ra
-; RV32IMZBS-NEXT: or a4, a4, t2
-; RV32IMZBS-NEXT: and a5, t1, ra
-; RV32IMZBS-NEXT: slli a5, a5, 8
-; RV32IMZBS-NEXT: or a5, t3, a5
-; RV32IMZBS-NEXT: slli t3, t0, 31
-; RV32IMZBS-NEXT: seqz a2, a2
-; RV32IMZBS-NEXT: addi t2, s1, -1
-; RV32IMZBS-NEXT: addi s2, s2, -1
-; RV32IMZBS-NEXT: and t5, t2, t5
-; RV32IMZBS-NEXT: sw t5, 716(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and t5, s2, t6
-; RV32IMZBS-NEXT: sw t5, 720(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and t2, t2, t6
-; RV32IMZBS-NEXT: sw t2, 712(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli t2, a7, 31
-; RV32IMZBS-NEXT: seqz t5, s0
-; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: addi t5, t5, -1
-; RV32IMZBS-NEXT: and t3, a2, t3
-; RV32IMZBS-NEXT: sw t3, 704(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and t3, t5, t2
-; RV32IMZBS-NEXT: sw t3, 708(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a2, a2, t2
-; RV32IMZBS-NEXT: sw a2, 692(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: srli a7, s6, 24
+; RV32IMZBS-NEXT: slli s0, s6, 24
+; RV32IMZBS-NEXT: and s4, s6, ra
+; RV32IMZBS-NEXT: srli s5, t1, 8
+; RV32IMZBS-NEXT: and a2, a0, ra
+; RV32IMZBS-NEXT: or a2, a2, a1
+; RV32IMZBS-NEXT: srli a1, t1, 24
+; RV32IMZBS-NEXT: and a0, a3, ra
+; RV32IMZBS-NEXT: or a0, a0, a7
+; RV32IMZBS-NEXT: srli a3, t3, 8
+; RV32IMZBS-NEXT: slli s4, s4, 8
+; RV32IMZBS-NEXT: or a7, s0, s4
+; RV32IMZBS-NEXT: srli s0, t3, 24
+; RV32IMZBS-NEXT: and s4, s5, ra
+; RV32IMZBS-NEXT: or s7, s4, a1
+; RV32IMZBS-NEXT: slli s4, t3, 24
+; RV32IMZBS-NEXT: and a1, a3, ra
+; RV32IMZBS-NEXT: or a1, a1, s0
+; RV32IMZBS-NEXT: and a3, t3, ra
+; RV32IMZBS-NEXT: slli a3, a3, 8
+; RV32IMZBS-NEXT: or a3, s4, a3
+; RV32IMZBS-NEXT: srli s0, t0, 1
+; RV32IMZBS-NEXT: and t0, t0, s8
+; RV32IMZBS-NEXT: slli t6, t6, 31
+; RV32IMZBS-NEXT: and s0, s0, s8
+; RV32IMZBS-NEXT: slli s4, t0, 1
+; RV32IMZBS-NEXT: slli t0, t4, 31
+; RV32IMZBS-NEXT: srli s1, s1, 31
+; RV32IMZBS-NEXT: or s9, s0, s4
+; RV32IMZBS-NEXT: srli t4, s4, 31
+; RV32IMZBS-NEXT: seqz s0, s1
+; RV32IMZBS-NEXT: seqz s1, t4
+; RV32IMZBS-NEXT: addi t4, s0, -1
+; RV32IMZBS-NEXT: addi s1, s1, -1
+; RV32IMZBS-NEXT: and t6, t4, t6
+; RV32IMZBS-NEXT: sw t6, 720(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and t6, s1, t0
+; RV32IMZBS-NEXT: sw t6, 724(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and t0, t4, t0
+; RV32IMZBS-NEXT: sw t0, 712(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: srli t0, t5, 1
+; RV32IMZBS-NEXT: sw s8, 716(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and t4, t5, s8
+; RV32IMZBS-NEXT: slli t5, a5, 31
+; RV32IMZBS-NEXT: and a5, t0, s8
+; RV32IMZBS-NEXT: slli t4, t4, 1
+; RV32IMZBS-NEXT: slli a4, a4, 31
+; RV32IMZBS-NEXT: srli a6, a6, 31
+; RV32IMZBS-NEXT: or s8, a5, t4
+; RV32IMZBS-NEXT: srli a5, t4, 31
+; RV32IMZBS-NEXT: seqz a6, a6
+; RV32IMZBS-NEXT: seqz t0, a5
+; RV32IMZBS-NEXT: addi a5, a6, -1
+; RV32IMZBS-NEXT: addi t0, t0, -1
+; RV32IMZBS-NEXT: and a6, a5, t5
+; RV32IMZBS-NEXT: sw a6, 704(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a6, t0, a4
+; RV32IMZBS-NEXT: sw a6, 708(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a4, a5, a4
+; RV32IMZBS-NEXT: sw a4, 692(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: sw ra, 740(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a2, s6, ra
-; RV32IMZBS-NEXT: slli t2, a2, 8
-; RV32IMZBS-NEXT: slli a2, s6, 24
-; RV32IMZBS-NEXT: or t2, a2, t2
-; RV32IMZBS-NEXT: or a3, t2, a3
-; RV32IMZBS-NEXT: sw a3, 684(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: or a1, a1, a6
-; RV32IMZBS-NEXT: sw a1, 688(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a1, a7, ra
-; RV32IMZBS-NEXT: slli a1, a1, 8
-; RV32IMZBS-NEXT: slli s5, a7, 24
-; RV32IMZBS-NEXT: or a1, s5, a1
-; RV32IMZBS-NEXT: or a0, a1, a0
+; RV32IMZBS-NEXT: and a4, s2, ra
+; RV32IMZBS-NEXT: slli a4, a4, 8
+; RV32IMZBS-NEXT: slli t5, s2, 24
+; RV32IMZBS-NEXT: or a4, t5, a4
+; RV32IMZBS-NEXT: or a2, a4, a2
+; RV32IMZBS-NEXT: sw a2, 684(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: or a0, a7, a0
+; RV32IMZBS-NEXT: sw a0, 688(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a0, t1, ra
+; RV32IMZBS-NEXT: slli a0, a0, 8
+; RV32IMZBS-NEXT: slli s1, t1, 24
+; RV32IMZBS-NEXT: or a0, s1, a0
+; RV32IMZBS-NEXT: or a0, a0, s7
; RV32IMZBS-NEXT: sw a0, 696(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: or a4, a5, a4
-; RV32IMZBS-NEXT: sw a4, 700(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, s8, 2
+; RV32IMZBS-NEXT: or a1, a3, a1
+; RV32IMZBS-NEXT: sw a1, 700(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a0, s6, 2
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: andi a1, s9, 2
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a3, s7, 1
-; RV32IMZBS-NEXT: and s2, a0, a3
-; RV32IMZBS-NEXT: slli a3, s6, 1
-; RV32IMZBS-NEXT: and s1, a1, a3
-; RV32IMZBS-NEXT: and t2, a0, a3
-; RV32IMZBS-NEXT: andi a0, s8, 4
+; RV32IMZBS-NEXT: slli a2, s3, 1
+; RV32IMZBS-NEXT: and s4, a0, a2
+; RV32IMZBS-NEXT: slli a2, s2, 1
+; RV32IMZBS-NEXT: and s0, a1, a2
+; RV32IMZBS-NEXT: and a5, a0, a2
+; RV32IMZBS-NEXT: andi a0, s6, 4
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: andi a1, s9, 4
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a3, s7, 2
-; RV32IMZBS-NEXT: and s4, a0, a3
-; RV32IMZBS-NEXT: slli a3, s6, 2
-; RV32IMZBS-NEXT: and s3, a1, a3
-; RV32IMZBS-NEXT: and t6, a0, a3
-; RV32IMZBS-NEXT: andi a0, s8, 8
+; RV32IMZBS-NEXT: slli a2, s3, 2
+; RV32IMZBS-NEXT: and a2, a0, a2
+; RV32IMZBS-NEXT: sw a2, 632(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a2, s2, 2
+; RV32IMZBS-NEXT: and a1, a1, a2
+; RV32IMZBS-NEXT: sw a1, 648(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a7, a0, a2
+; RV32IMZBS-NEXT: andi a0, s6, 8
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: andi a1, s9, 8
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a3, s7, 3
-; RV32IMZBS-NEXT: and a3, a0, a3
-; RV32IMZBS-NEXT: sw a3, 620(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a3, s6, 3
-; RV32IMZBS-NEXT: and a1, a1, a3
-; RV32IMZBS-NEXT: sw a1, 624(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a0, a0, a3
-; RV32IMZBS-NEXT: sw a0, 672(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, s8, 16
+; RV32IMZBS-NEXT: slli a2, s3, 3
+; RV32IMZBS-NEXT: and a2, a0, a2
+; RV32IMZBS-NEXT: sw a2, 616(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a2, s2, 3
+; RV32IMZBS-NEXT: and a1, a1, a2
+; RV32IMZBS-NEXT: sw a1, 620(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and s7, a0, a2
+; RV32IMZBS-NEXT: andi a0, s6, 16
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: andi a1, s9, 16
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a3, s7, 4
-; RV32IMZBS-NEXT: and a3, a0, a3
-; RV32IMZBS-NEXT: sw a3, 608(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a3, s6, 4
-; RV32IMZBS-NEXT: and a1, a1, a3
-; RV32IMZBS-NEXT: sw a1, 616(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a0, a0, a3
-; RV32IMZBS-NEXT: sw a0, 652(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, s8, 32
+; RV32IMZBS-NEXT: slli a2, s3, 4
+; RV32IMZBS-NEXT: and a2, a0, a2
+; RV32IMZBS-NEXT: sw a2, 604(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a2, s2, 4
+; RV32IMZBS-NEXT: and a1, a1, a2
+; RV32IMZBS-NEXT: sw a1, 612(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a0, a0, a2
+; RV32IMZBS-NEXT: sw a0, 656(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a0, s6, 32
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: andi a1, s9, 32
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a3, s7, 5
-; RV32IMZBS-NEXT: and a3, a0, a3
-; RV32IMZBS-NEXT: sw a3, 568(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a3, s6, 5
-; RV32IMZBS-NEXT: and a1, a1, a3
-; RV32IMZBS-NEXT: sw a1, 580(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a0, a0, a3
-; RV32IMZBS-NEXT: sw a0, 632(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, s8, 64
+; RV32IMZBS-NEXT: slli a2, s3, 5
+; RV32IMZBS-NEXT: and a2, a0, a2
+; RV32IMZBS-NEXT: sw a2, 564(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a2, s2, 5
+; RV32IMZBS-NEXT: and a1, a1, a2
+; RV32IMZBS-NEXT: sw a1, 576(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a0, a0, a2
+; RV32IMZBS-NEXT: sw a0, 628(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a0, s6, 64
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: andi a1, s9, 64
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a3, s7, 6
-; RV32IMZBS-NEXT: and a3, a0, a3
-; RV32IMZBS-NEXT: sw a3, 640(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a3, s6, 6
-; RV32IMZBS-NEXT: and a1, a1, a3
-; RV32IMZBS-NEXT: sw a1, 656(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a0, a0, a3
+; RV32IMZBS-NEXT: slli a2, s3, 6
+; RV32IMZBS-NEXT: and a2, a0, a2
+; RV32IMZBS-NEXT: sw a2, 640(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a2, s2, 6
+; RV32IMZBS-NEXT: and a1, a1, a2
+; RV32IMZBS-NEXT: sw a1, 660(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a0, a0, a2
; RV32IMZBS-NEXT: sw a0, 676(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, s8, 128
+; RV32IMZBS-NEXT: andi a0, s6, 128
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: andi a1, s9, 128
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a3, s7, 7
-; RV32IMZBS-NEXT: and a3, a0, a3
-; RV32IMZBS-NEXT: sw a3, 536(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a3, s6, 7
-; RV32IMZBS-NEXT: and a1, a1, a3
-; RV32IMZBS-NEXT: sw a1, 540(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a0, a0, a3
-; RV32IMZBS-NEXT: sw a0, 592(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, s8, 256
+; RV32IMZBS-NEXT: slli a2, s3, 7
+; RV32IMZBS-NEXT: and a2, a0, a2
+; RV32IMZBS-NEXT: sw a2, 532(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a2, s2, 7
+; RV32IMZBS-NEXT: and a1, a1, a2
+; RV32IMZBS-NEXT: sw a1, 536(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a0, a0, a2
+; RV32IMZBS-NEXT: sw a0, 588(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a0, s6, 256
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: andi a1, s9, 256
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a3, s7, 8
-; RV32IMZBS-NEXT: and a3, a0, a3
-; RV32IMZBS-NEXT: sw a3, 516(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a3, s6, 8
-; RV32IMZBS-NEXT: and a1, a1, a3
-; RV32IMZBS-NEXT: sw a1, 532(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a0, a0, a3
-; RV32IMZBS-NEXT: sw a0, 564(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, s8, 512
+; RV32IMZBS-NEXT: slli a2, s3, 8
+; RV32IMZBS-NEXT: and a2, a0, a2
+; RV32IMZBS-NEXT: sw a2, 512(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a2, s2, 8
+; RV32IMZBS-NEXT: and a1, a1, a2
+; RV32IMZBS-NEXT: sw a1, 528(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a0, a0, a2
+; RV32IMZBS-NEXT: sw a0, 560(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a0, s6, 512
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: andi a1, s9, 512
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a3, s7, 9
-; RV32IMZBS-NEXT: and a3, a0, a3
-; RV32IMZBS-NEXT: sw a3, 572(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a3, s6, 9
-; RV32IMZBS-NEXT: and a1, a1, a3
-; RV32IMZBS-NEXT: sw a1, 600(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a0, a0, a3
-; RV32IMZBS-NEXT: sw a0, 628(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, s8, 1024
+; RV32IMZBS-NEXT: slli a2, s3, 9
+; RV32IMZBS-NEXT: and a2, a0, a2
+; RV32IMZBS-NEXT: sw a2, 568(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a2, s2, 9
+; RV32IMZBS-NEXT: and a1, a1, a2
+; RV32IMZBS-NEXT: sw a1, 596(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a0, a0, a2
+; RV32IMZBS-NEXT: sw a0, 624(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a0, s6, 1024
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: andi a1, s9, 1024
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a3, s7, 10
-; RV32IMZBS-NEXT: and a3, a0, a3
-; RV32IMZBS-NEXT: sw a3, 660(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a3, s6, 10
-; RV32IMZBS-NEXT: and a1, a1, a3
-; RV32IMZBS-NEXT: sw a1, 664(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a0, a0, a3
+; RV32IMZBS-NEXT: slli a2, s3, 10
+; RV32IMZBS-NEXT: and a2, a0, a2
+; RV32IMZBS-NEXT: sw a2, 664(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a2, s2, 10
+; RV32IMZBS-NEXT: and a1, a1, a2
+; RV32IMZBS-NEXT: sw a1, 668(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a0, a0, a2
; RV32IMZBS-NEXT: sw a0, 680(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: not a3, s8
-; RV32IMZBS-NEXT: bexti a0, a3, 11
+; RV32IMZBS-NEXT: not a2, s6
+; RV32IMZBS-NEXT: bexti a0, a2, 11
; RV32IMZBS-NEXT: addi a1, a0, -1
; RV32IMZBS-NEXT: not a0, s9
-; RV32IMZBS-NEXT: bexti a4, a0, 11
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: slli a5, s7, 11
-; RV32IMZBS-NEXT: and a5, a1, a5
-; RV32IMZBS-NEXT: sw a5, 456(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a5, s6, 11
-; RV32IMZBS-NEXT: and a4, a4, a5
-; RV32IMZBS-NEXT: sw a4, 468(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a1, a1, a5
-; RV32IMZBS-NEXT: sw a1, 504(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a1, a3, 12
-; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: bexti a4, a0, 12
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: slli a5, s7, 12
-; RV32IMZBS-NEXT: and a5, a1, a5
-; RV32IMZBS-NEXT: sw a5, 448(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a5, s6, 12
-; RV32IMZBS-NEXT: and a4, a4, a5
+; RV32IMZBS-NEXT: bexti a3, a0, 11
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s3, 11
+; RV32IMZBS-NEXT: and a4, a1, a4
; RV32IMZBS-NEXT: sw a4, 452(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a1, a1, a5
-; RV32IMZBS-NEXT: sw a1, 488(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a1, a3, 13
+; RV32IMZBS-NEXT: slli a4, s2, 11
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 464(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a1, a1, a4
+; RV32IMZBS-NEXT: sw a1, 500(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a1, a2, 12
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: bexti a4, a0, 13
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: slli a5, s7, 13
-; RV32IMZBS-NEXT: and a5, a1, a5
-; RV32IMZBS-NEXT: sw a5, 508(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a5, s6, 13
-; RV32IMZBS-NEXT: and a4, a4, a5
-; RV32IMZBS-NEXT: sw a4, 520(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a1, a1, a5
-; RV32IMZBS-NEXT: sw a1, 552(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a1, a3, 14
+; RV32IMZBS-NEXT: bexti a3, a0, 12
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s3, 12
+; RV32IMZBS-NEXT: and a4, a1, a4
+; RV32IMZBS-NEXT: sw a4, 444(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s2, 12
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 448(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a1, a1, a4
+; RV32IMZBS-NEXT: sw a1, 484(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a1, a2, 13
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: bexti a4, a0, 14
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: slli a5, s7, 14
-; RV32IMZBS-NEXT: and a5, a1, a5
-; RV32IMZBS-NEXT: sw a5, 588(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a5, s6, 14
-; RV32IMZBS-NEXT: and a4, a4, a5
-; RV32IMZBS-NEXT: sw a4, 604(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a1, a1, a5
-; RV32IMZBS-NEXT: sw a1, 636(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a1, a3, 15
+; RV32IMZBS-NEXT: bexti a3, a0, 13
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s3, 13
+; RV32IMZBS-NEXT: and a4, a1, a4
+; RV32IMZBS-NEXT: sw a4, 504(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s2, 13
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 516(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a1, a1, a4
+; RV32IMZBS-NEXT: sw a1, 548(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a1, a2, 14
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: bexti a4, a0, 15
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: slli a5, s7, 15
-; RV32IMZBS-NEXT: and a5, a1, a5
-; RV32IMZBS-NEXT: sw a5, 644(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a5, s6, 15
-; RV32IMZBS-NEXT: and a4, a4, a5
-; RV32IMZBS-NEXT: sw a4, 648(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a1, a1, a5
-; RV32IMZBS-NEXT: sw a1, 668(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a1, a3, 16
+; RV32IMZBS-NEXT: bexti a3, a0, 14
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s3, 14
+; RV32IMZBS-NEXT: and a4, a1, a4
+; RV32IMZBS-NEXT: sw a4, 584(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s2, 14
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 600(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a1, a1, a4
+; RV32IMZBS-NEXT: sw a1, 636(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a1, a2, 15
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: bexti a4, a0, 16
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: slli a5, s7, 16
-; RV32IMZBS-NEXT: and a5, a1, a5
-; RV32IMZBS-NEXT: sw a5, 412(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a5, s6, 16
-; RV32IMZBS-NEXT: and a4, a4, a5
-; RV32IMZBS-NEXT: sw a4, 420(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a1, a1, a5
-; RV32IMZBS-NEXT: sw a1, 436(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a1, a3, 17
+; RV32IMZBS-NEXT: bexti a3, a0, 15
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s3, 15
+; RV32IMZBS-NEXT: and a4, a1, a4
+; RV32IMZBS-NEXT: sw a4, 644(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s2, 15
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 652(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a1, a1, a4
+; RV32IMZBS-NEXT: sw a1, 672(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a1, a2, 16
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: bexti a4, a0, 17
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: slli a5, s7, 17
-; RV32IMZBS-NEXT: and a5, a1, a5
-; RV32IMZBS-NEXT: sw a5, 404(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a5, s6, 17
-; RV32IMZBS-NEXT: and a4, a4, a5
+; RV32IMZBS-NEXT: bexti a3, a0, 16
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s3, 16
+; RV32IMZBS-NEXT: and a4, a1, a4
; RV32IMZBS-NEXT: sw a4, 408(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a1, a1, a5
-; RV32IMZBS-NEXT: sw a1, 428(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a1, a3, 18
+; RV32IMZBS-NEXT: slli a4, s2, 16
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 416(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a1, a1, a4
+; RV32IMZBS-NEXT: sw a1, 432(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a1, a2, 17
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: bexti a4, a0, 18
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: slli a5, s7, 18
-; RV32IMZBS-NEXT: and a5, a1, a5
-; RV32IMZBS-NEXT: sw a5, 440(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a5, s6, 18
-; RV32IMZBS-NEXT: and a4, a4, a5
-; RV32IMZBS-NEXT: sw a4, 444(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a1, a1, a5
-; RV32IMZBS-NEXT: sw a1, 476(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a1, a3, 19
+; RV32IMZBS-NEXT: bexti a3, a0, 17
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s3, 17
+; RV32IMZBS-NEXT: and a4, a1, a4
+; RV32IMZBS-NEXT: sw a4, 400(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s2, 17
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 404(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a1, a1, a4
+; RV32IMZBS-NEXT: sw a1, 424(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a1, a2, 18
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: bexti a4, a0, 19
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: slli a5, s7, 19
-; RV32IMZBS-NEXT: and a5, a1, a5
-; RV32IMZBS-NEXT: sw a5, 496(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a5, s6, 19
-; RV32IMZBS-NEXT: and a4, a4, a5
-; RV32IMZBS-NEXT: sw a4, 512(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a1, a1, a5
-; RV32IMZBS-NEXT: sw a1, 548(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a1, a3, 20
+; RV32IMZBS-NEXT: bexti a3, a0, 18
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s3, 18
+; RV32IMZBS-NEXT: and a4, a1, a4
+; RV32IMZBS-NEXT: sw a4, 436(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s2, 18
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 440(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a1, a1, a4
+; RV32IMZBS-NEXT: sw a1, 472(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a1, a2, 19
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: bexti a4, a0, 20
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: slli a5, s7, 20
-; RV32IMZBS-NEXT: and a5, a1, a5
-; RV32IMZBS-NEXT: sw a5, 556(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a5, s6, 20
-; RV32IMZBS-NEXT: and a4, a4, a5
-; RV32IMZBS-NEXT: sw a4, 560(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a1, a1, a5
-; RV32IMZBS-NEXT: sw a1, 576(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a1, a3, 21
+; RV32IMZBS-NEXT: bexti a3, a0, 19
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s3, 19
+; RV32IMZBS-NEXT: and a4, a1, a4
+; RV32IMZBS-NEXT: sw a4, 492(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s2, 19
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 508(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a1, a1, a4
+; RV32IMZBS-NEXT: sw a1, 544(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a1, a2, 20
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: bexti a4, a0, 21
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: slli a5, s7, 21
-; RV32IMZBS-NEXT: and a5, a1, a5
-; RV32IMZBS-NEXT: sw a5, 584(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a5, s6, 21
-; RV32IMZBS-NEXT: and a4, a4, a5
-; RV32IMZBS-NEXT: sw a4, 596(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a1, a1, a5
-; RV32IMZBS-NEXT: sw a1, 612(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a1, a3, 22
+; RV32IMZBS-NEXT: bexti a3, a0, 20
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s3, 20
+; RV32IMZBS-NEXT: and a4, a1, a4
+; RV32IMZBS-NEXT: sw a4, 552(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s2, 20
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 556(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a1, a1, a4
+; RV32IMZBS-NEXT: sw a1, 572(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a1, a2, 21
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: bexti a4, a0, 22
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: slli a5, s7, 22
-; RV32IMZBS-NEXT: and a5, a1, a5
-; RV32IMZBS-NEXT: sw a5, 380(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a5, s6, 22
-; RV32IMZBS-NEXT: and a4, a4, a5
-; RV32IMZBS-NEXT: sw a4, 384(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a1, a1, a5
-; RV32IMZBS-NEXT: sw a1, 392(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a1, a3, 23
+; RV32IMZBS-NEXT: bexti a3, a0, 21
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s3, 21
+; RV32IMZBS-NEXT: and a4, a1, a4
+; RV32IMZBS-NEXT: sw a4, 580(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s2, 21
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 592(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a1, a1, a4
+; RV32IMZBS-NEXT: sw a1, 608(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a1, a2, 22
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: bexti a4, a0, 23
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: slli a5, s7, 23
-; RV32IMZBS-NEXT: and a5, a1, a5
-; RV32IMZBS-NEXT: sw a5, 372(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a5, s6, 23
-; RV32IMZBS-NEXT: and a4, a4, a5
+; RV32IMZBS-NEXT: bexti a3, a0, 22
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s3, 22
+; RV32IMZBS-NEXT: and a4, a1, a4
; RV32IMZBS-NEXT: sw a4, 376(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a1, a1, a5
+; RV32IMZBS-NEXT: slli a4, s2, 22
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 380(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a1, a1, a4
; RV32IMZBS-NEXT: sw a1, 388(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a1, a3, 24
+; RV32IMZBS-NEXT: bexti a1, a2, 23
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: bexti a4, a0, 24
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: slli a5, s7, 24
-; RV32IMZBS-NEXT: and a5, a1, a5
-; RV32IMZBS-NEXT: sw a5, 396(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a4, a4, a2
-; RV32IMZBS-NEXT: sw a4, 400(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 416(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a1, a3, 25
+; RV32IMZBS-NEXT: bexti a3, a0, 23
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s3, 23
+; RV32IMZBS-NEXT: and a4, a1, a4
+; RV32IMZBS-NEXT: sw a4, 368(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s2, 23
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 372(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a1, a1, a4
+; RV32IMZBS-NEXT: sw a1, 384(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a1, a2, 24
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: bexti a2, a0, 25
-; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: slli a4, s7, 25
+; RV32IMZBS-NEXT: bexti a3, a0, 24
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s3, 24
; RV32IMZBS-NEXT: and a4, a1, a4
-; RV32IMZBS-NEXT: sw a4, 424(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, s6, 25
-; RV32IMZBS-NEXT: and a2, a2, a4
-; RV32IMZBS-NEXT: sw a2, 432(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a4, 392(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a3, a3, t5
+; RV32IMZBS-NEXT: sw a3, 396(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a1, a1, t5
+; RV32IMZBS-NEXT: sw a1, 412(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a1, a2, 25
+; RV32IMZBS-NEXT: addi a1, a1, -1
+; RV32IMZBS-NEXT: bexti a3, a0, 25
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s3, 25
+; RV32IMZBS-NEXT: and a4, a1, a4
+; RV32IMZBS-NEXT: sw a4, 420(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s2, 25
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 428(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a1, a1, a4
-; RV32IMZBS-NEXT: sw a1, 460(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a1, a3, 26
+; RV32IMZBS-NEXT: sw a1, 456(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a1, a2, 26
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: bexti a2, a0, 26
-; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: slli a4, s7, 26
+; RV32IMZBS-NEXT: bexti a3, a0, 26
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s3, 26
; RV32IMZBS-NEXT: and a4, a1, a4
-; RV32IMZBS-NEXT: sw a4, 464(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, s6, 26
-; RV32IMZBS-NEXT: and a2, a2, a4
-; RV32IMZBS-NEXT: sw a2, 472(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a4, 460(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s2, 26
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 468(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a1, a1, a4
-; RV32IMZBS-NEXT: sw a1, 480(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a1, a3, 27
+; RV32IMZBS-NEXT: sw a1, 476(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a1, a2, 27
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: bexti a2, a0, 27
-; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: slli a4, s7, 27
+; RV32IMZBS-NEXT: bexti a3, a0, 27
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s3, 27
; RV32IMZBS-NEXT: and a4, a1, a4
-; RV32IMZBS-NEXT: sw a4, 484(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, s6, 27
-; RV32IMZBS-NEXT: and a2, a2, a4
-; RV32IMZBS-NEXT: sw a2, 492(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a4, 480(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s2, 27
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 488(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a1, a1, a4
-; RV32IMZBS-NEXT: sw a1, 500(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a1, a3, 28
+; RV32IMZBS-NEXT: sw a1, 496(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a1, a2, 28
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: bexti a2, a0, 28
-; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: slli a4, s7, 28
+; RV32IMZBS-NEXT: bexti a3, a0, 28
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s3, 28
; RV32IMZBS-NEXT: and a4, a1, a4
-; RV32IMZBS-NEXT: sw a4, 528(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, s6, 28
-; RV32IMZBS-NEXT: and a2, a2, a4
-; RV32IMZBS-NEXT: sw a2, 524(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a4, 524(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s2, 28
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 520(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a1, a1, a4
-; RV32IMZBS-NEXT: sw a1, 544(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti a1, a3, 29
+; RV32IMZBS-NEXT: sw a1, 540(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: bexti a1, a2, 29
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: bexti a2, a0, 29
-; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: slli a4, s7, 29
+; RV32IMZBS-NEXT: bexti a3, a0, 29
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s3, 29
; RV32IMZBS-NEXT: and a4, a1, a4
-; RV32IMZBS-NEXT: sw a4, 356(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, s6, 29
-; RV32IMZBS-NEXT: and a2, a2, a4
-; RV32IMZBS-NEXT: sw a2, 364(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a5, a1, a4
-; RV32IMZBS-NEXT: andi a1, s8, 1
-; RV32IMZBS-NEXT: andi a2, s9, 1
+; RV32IMZBS-NEXT: sw a4, 348(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, s2, 29
+; RV32IMZBS-NEXT: and a3, a3, a4
+; RV32IMZBS-NEXT: sw a3, 356(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a1, a1, a4
+; RV32IMZBS-NEXT: sw a1, 364(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a1, s6, 1
+; RV32IMZBS-NEXT: andi a3, s9, 1
; RV32IMZBS-NEXT: seqz a1, a1
-; RV32IMZBS-NEXT: seqz a2, a2
+; RV32IMZBS-NEXT: seqz a3, a3
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: slli a4, s7, 30
-; RV32IMZBS-NEXT: and a6, a1, s7
+; RV32IMZBS-NEXT: addi a3, a3, -1
+; RV32IMZBS-NEXT: slli a4, s3, 30
+; RV32IMZBS-NEXT: and a6, a1, s3
; RV32IMZBS-NEXT: sw a6, 324(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a2, a2, s6
-; RV32IMZBS-NEXT: sw a2, 340(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and s7, a1, s6
-; RV32IMZBS-NEXT: slli s6, s6, 30
-; RV32IMZBS-NEXT: bexti a1, a3, 30
+; RV32IMZBS-NEXT: and s3, a3, s2
+; RV32IMZBS-NEXT: and t5, a1, s2
+; RV32IMZBS-NEXT: slli s2, s2, 30
+; RV32IMZBS-NEXT: bexti a1, a2, 30
; RV32IMZBS-NEXT: bexti a0, a0, 30
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: and a4, a1, a4
; RV32IMZBS-NEXT: sw a4, 320(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a0, a0, s6
-; RV32IMZBS-NEXT: sw a0, 332(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a0, a1, s6
-; RV32IMZBS-NEXT: sw a0, 368(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, t1, 2
+; RV32IMZBS-NEXT: and s6, a0, s2
+; RV32IMZBS-NEXT: and a0, a1, s2
+; RV32IMZBS-NEXT: sw a0, 360(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a0, t3, 2
; RV32IMZBS-NEXT: seqz a0, a0
-; RV32IMZBS-NEXT: andi a1, t4, 2
+; RV32IMZBS-NEXT: andi a1, s8, 2
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t0, 1
+; RV32IMZBS-NEXT: slli a2, t2, 1
; RV32IMZBS-NEXT: and a2, a0, a2
; RV32IMZBS-NEXT: sw a2, 316(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a7, 1
-; RV32IMZBS-NEXT: and s6, a1, a2
+; RV32IMZBS-NEXT: slli a2, t1, 1
+; RV32IMZBS-NEXT: and s2, a1, a2
; RV32IMZBS-NEXT: and a0, a0, a2
-; RV32IMZBS-NEXT: sw a0, 360(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, t1, 4
+; RV32IMZBS-NEXT: sw a0, 352(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a0, t3, 4
; RV32IMZBS-NEXT: seqz a0, a0
-; RV32IMZBS-NEXT: andi a1, t4, 4
+; RV32IMZBS-NEXT: andi a1, s8, 4
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t0, 2
+; RV32IMZBS-NEXT: slli a2, t2, 2
; RV32IMZBS-NEXT: and a2, a0, a2
; RV32IMZBS-NEXT: sw a2, 292(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a7, 2
+; RV32IMZBS-NEXT: slli a2, t1, 2
; RV32IMZBS-NEXT: and a1, a1, a2
; RV32IMZBS-NEXT: sw a1, 304(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a0, a0, a2
-; RV32IMZBS-NEXT: sw a0, 348(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, t1, 8
+; RV32IMZBS-NEXT: sw a0, 340(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a0, t3, 8
; RV32IMZBS-NEXT: seqz a0, a0
-; RV32IMZBS-NEXT: andi a1, t4, 8
+; RV32IMZBS-NEXT: andi a1, s8, 8
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t0, 3
+; RV32IMZBS-NEXT: slli a2, t2, 3
; RV32IMZBS-NEXT: and a2, a0, a2
; RV32IMZBS-NEXT: sw a2, 268(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a7, 3
+; RV32IMZBS-NEXT: slli a2, t1, 3
; RV32IMZBS-NEXT: and a1, a1, a2
; RV32IMZBS-NEXT: sw a1, 276(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a0, a0, a2
; RV32IMZBS-NEXT: sw a0, 312(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, t1, 16
+; RV32IMZBS-NEXT: andi a0, t3, 16
; RV32IMZBS-NEXT: seqz a0, a0
-; RV32IMZBS-NEXT: andi a1, t4, 16
+; RV32IMZBS-NEXT: andi a1, s8, 16
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t0, 4
+; RV32IMZBS-NEXT: slli a2, t2, 4
; RV32IMZBS-NEXT: and a2, a0, a2
; RV32IMZBS-NEXT: sw a2, 248(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a7, 4
+; RV32IMZBS-NEXT: slli a2, t1, 4
; RV32IMZBS-NEXT: and a1, a1, a2
; RV32IMZBS-NEXT: sw a1, 256(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a0, a0, a2
; RV32IMZBS-NEXT: sw a0, 288(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, t1, 32
+; RV32IMZBS-NEXT: andi a0, t3, 32
; RV32IMZBS-NEXT: seqz a0, a0
-; RV32IMZBS-NEXT: andi a1, t4, 32
+; RV32IMZBS-NEXT: andi a1, s8, 32
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t0, 5
+; RV32IMZBS-NEXT: slli a2, t2, 5
; RV32IMZBS-NEXT: and a2, a0, a2
; RV32IMZBS-NEXT: sw a2, 224(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a7, 5
+; RV32IMZBS-NEXT: slli a2, t1, 5
; RV32IMZBS-NEXT: and a1, a1, a2
; RV32IMZBS-NEXT: sw a1, 236(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a0, a0, a2
; RV32IMZBS-NEXT: sw a0, 264(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, t1, 64
+; RV32IMZBS-NEXT: andi a0, t3, 64
; RV32IMZBS-NEXT: seqz a0, a0
-; RV32IMZBS-NEXT: andi a1, t4, 64
+; RV32IMZBS-NEXT: andi a1, s8, 64
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t0, 6
+; RV32IMZBS-NEXT: slli a2, t2, 6
; RV32IMZBS-NEXT: and a2, a0, a2
; RV32IMZBS-NEXT: sw a2, 296(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a7, 6
+; RV32IMZBS-NEXT: slli a2, t1, 6
; RV32IMZBS-NEXT: and a1, a1, a2
; RV32IMZBS-NEXT: sw a1, 308(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a0, a0, a2
-; RV32IMZBS-NEXT: sw a0, 344(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, t1, 128
+; RV32IMZBS-NEXT: sw a0, 336(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a0, t3, 128
; RV32IMZBS-NEXT: seqz a0, a0
-; RV32IMZBS-NEXT: andi a1, t4, 128
+; RV32IMZBS-NEXT: andi a1, s8, 128
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t0, 7
+; RV32IMZBS-NEXT: slli a2, t2, 7
; RV32IMZBS-NEXT: and a2, a0, a2
; RV32IMZBS-NEXT: sw a2, 184(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a7, 7
+; RV32IMZBS-NEXT: slli a2, t1, 7
; RV32IMZBS-NEXT: and a1, a1, a2
; RV32IMZBS-NEXT: sw a1, 192(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a0, a0, a2
; RV32IMZBS-NEXT: sw a0, 220(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, t1, 256
+; RV32IMZBS-NEXT: andi a0, t3, 256
; RV32IMZBS-NEXT: seqz a0, a0
-; RV32IMZBS-NEXT: andi a1, t4, 256
+; RV32IMZBS-NEXT: andi a1, s8, 256
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t0, 8
+; RV32IMZBS-NEXT: slli a2, t2, 8
; RV32IMZBS-NEXT: and a2, a0, a2
; RV32IMZBS-NEXT: sw a2, 156(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a7, 8
+; RV32IMZBS-NEXT: slli a2, t1, 8
; RV32IMZBS-NEXT: and a1, a1, a2
; RV32IMZBS-NEXT: sw a1, 176(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a0, a0, a2
; RV32IMZBS-NEXT: sw a0, 204(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, t1, 512
+; RV32IMZBS-NEXT: andi a0, t3, 512
; RV32IMZBS-NEXT: seqz a0, a0
-; RV32IMZBS-NEXT: andi a1, t4, 512
+; RV32IMZBS-NEXT: andi a1, s8, 512
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t0, 9
+; RV32IMZBS-NEXT: slli a2, t2, 9
; RV32IMZBS-NEXT: and a2, a0, a2
; RV32IMZBS-NEXT: sw a2, 228(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a7, 9
+; RV32IMZBS-NEXT: slli a2, t1, 9
; RV32IMZBS-NEXT: and a1, a1, a2
; RV32IMZBS-NEXT: sw a1, 240(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a0, a0, a2
; RV32IMZBS-NEXT: sw a0, 260(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a0, t1, 1024
+; RV32IMZBS-NEXT: andi a0, t3, 1024
; RV32IMZBS-NEXT: seqz a0, a0
-; RV32IMZBS-NEXT: andi a1, t4, 1024
+; RV32IMZBS-NEXT: andi a1, s8, 1024
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t0, 10
+; RV32IMZBS-NEXT: slli a2, t2, 10
; RV32IMZBS-NEXT: and a2, a0, a2
; RV32IMZBS-NEXT: sw a2, 328(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a7, 10
+; RV32IMZBS-NEXT: slli a2, t1, 10
; RV32IMZBS-NEXT: and a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 336(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 332(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a0, a0, a2
-; RV32IMZBS-NEXT: sw a0, 352(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: not a1, t1
+; RV32IMZBS-NEXT: sw a0, 344(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: not a1, t3
; RV32IMZBS-NEXT: bexti a0, a1, 11
; RV32IMZBS-NEXT: addi a2, a0, -1
-; RV32IMZBS-NEXT: not a0, t4
+; RV32IMZBS-NEXT: not a0, s8
; RV32IMZBS-NEXT: bexti a3, a0, 11
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 11
+; RV32IMZBS-NEXT: slli a4, t2, 11
; RV32IMZBS-NEXT: and a4, a2, a4
; RV32IMZBS-NEXT: sw a4, 108(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 11
+; RV32IMZBS-NEXT: slli a4, t1, 11
; RV32IMZBS-NEXT: and a3, a3, a4
; RV32IMZBS-NEXT: sw a3, 120(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
@@ -10575,10 +10576,10 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 12
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 12
+; RV32IMZBS-NEXT: slli a4, t2, 12
; RV32IMZBS-NEXT: and a4, a2, a4
; RV32IMZBS-NEXT: sw a4, 92(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 12
+; RV32IMZBS-NEXT: slli a4, t1, 12
; RV32IMZBS-NEXT: and a3, a3, a4
; RV32IMZBS-NEXT: sw a3, 96(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
@@ -10587,10 +10588,10 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 13
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 13
+; RV32IMZBS-NEXT: slli a4, t2, 13
; RV32IMZBS-NEXT: and a4, a2, a4
; RV32IMZBS-NEXT: sw a4, 144(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 13
+; RV32IMZBS-NEXT: slli a4, t1, 13
; RV32IMZBS-NEXT: and a3, a3, a4
; RV32IMZBS-NEXT: sw a3, 152(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
@@ -10599,10 +10600,10 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 14
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 14
+; RV32IMZBS-NEXT: slli a4, t2, 14
; RV32IMZBS-NEXT: and a4, a2, a4
; RV32IMZBS-NEXT: sw a4, 244(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 14
+; RV32IMZBS-NEXT: slli a4, t1, 14
; RV32IMZBS-NEXT: and a3, a3, a4
; RV32IMZBS-NEXT: sw a3, 252(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
@@ -10611,10 +10612,10 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 15
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 15
+; RV32IMZBS-NEXT: slli a4, t2, 15
; RV32IMZBS-NEXT: and a4, a2, a4
; RV32IMZBS-NEXT: sw a4, 280(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 15
+; RV32IMZBS-NEXT: slli a4, t1, 15
; RV32IMZBS-NEXT: and a3, a3, a4
; RV32IMZBS-NEXT: sw a3, 284(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
@@ -10623,10 +10624,10 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 16
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 16
+; RV32IMZBS-NEXT: slli a4, t2, 16
; RV32IMZBS-NEXT: and a4, a2, a4
; RV32IMZBS-NEXT: sw a4, 56(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 16
+; RV32IMZBS-NEXT: slli a4, t1, 16
; RV32IMZBS-NEXT: and a3, a3, a4
; RV32IMZBS-NEXT: sw a3, 60(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
@@ -10635,10 +10636,10 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 17
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 17
+; RV32IMZBS-NEXT: slli a4, t2, 17
; RV32IMZBS-NEXT: and a4, a2, a4
; RV32IMZBS-NEXT: sw a4, 44(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 17
+; RV32IMZBS-NEXT: slli a4, t1, 17
; RV32IMZBS-NEXT: and a3, a3, a4
; RV32IMZBS-NEXT: sw a3, 52(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
@@ -10647,10 +10648,10 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 18
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 18
+; RV32IMZBS-NEXT: slli a4, t2, 18
; RV32IMZBS-NEXT: and a4, a2, a4
; RV32IMZBS-NEXT: sw a4, 80(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 18
+; RV32IMZBS-NEXT: slli a4, t1, 18
; RV32IMZBS-NEXT: and a3, a3, a4
; RV32IMZBS-NEXT: sw a3, 84(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
@@ -10659,10 +10660,10 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 19
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 19
+; RV32IMZBS-NEXT: slli a4, t2, 19
; RV32IMZBS-NEXT: and a4, a2, a4
; RV32IMZBS-NEXT: sw a4, 148(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 19
+; RV32IMZBS-NEXT: slli a4, t1, 19
; RV32IMZBS-NEXT: and a3, a3, a4
; RV32IMZBS-NEXT: sw a3, 160(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
@@ -10671,10 +10672,10 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 20
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 20
+; RV32IMZBS-NEXT: slli a4, t2, 20
; RV32IMZBS-NEXT: and a4, a2, a4
; RV32IMZBS-NEXT: sw a4, 196(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 20
+; RV32IMZBS-NEXT: slli a4, t1, 20
; RV32IMZBS-NEXT: and a3, a3, a4
; RV32IMZBS-NEXT: sw a3, 200(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
@@ -10683,10 +10684,10 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 21
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 21
+; RV32IMZBS-NEXT: slli a4, t2, 21
; RV32IMZBS-NEXT: and a4, a2, a4
; RV32IMZBS-NEXT: sw a4, 212(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a4, a7, 21
+; RV32IMZBS-NEXT: slli a4, t1, 21
; RV32IMZBS-NEXT: and a3, a3, a4
; RV32IMZBS-NEXT: sw a3, 216(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, a2, a4
@@ -10695,10 +10696,10 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: addi a2, a2, -1
; RV32IMZBS-NEXT: bexti a3, a0, 22
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t0, 22
+; RV32IMZBS-NEXT: slli a4, t2, 22
; RV32IMZBS-NEXT: and a4, a2, a4
; RV32IMZBS-NEXT: sw a4, 28(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, a7, 22
+; RV32IMZBS-NEXT: slli a6, t1, 22
; RV32IMZBS-NEXT: and a4, a3, a6
; RV32IMZBS-NEXT: and a2, a2, a6
; RV32IMZBS-NEXT: sw a2, 32(sp) # 4-byte Folded Spill
@@ -10706,31 +10707,31 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: addi a6, a2, -1
; RV32IMZBS-NEXT: bexti a2, a0, 23
; RV32IMZBS-NEXT: addi a3, a2, -1
-; RV32IMZBS-NEXT: slli a2, t0, 23
+; RV32IMZBS-NEXT: slli a2, t2, 23
; RV32IMZBS-NEXT: and a2, a6, a2
; RV32IMZBS-NEXT: sw a2, 24(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli t3, a7, 23
-; RV32IMZBS-NEXT: and a3, a3, t3
-; RV32IMZBS-NEXT: and a6, a6, t3
-; RV32IMZBS-NEXT: bexti t3, a1, 24
-; RV32IMZBS-NEXT: addi s0, t3, -1
-; RV32IMZBS-NEXT: bexti t3, a0, 24
-; RV32IMZBS-NEXT: addi t5, t3, -1
-; RV32IMZBS-NEXT: slli t3, t0, 24
-; RV32IMZBS-NEXT: and a2, s0, t3
+; RV32IMZBS-NEXT: slli t0, t1, 23
+; RV32IMZBS-NEXT: and a3, a3, t0
+; RV32IMZBS-NEXT: and a6, a6, t0
+; RV32IMZBS-NEXT: bexti t0, a1, 24
+; RV32IMZBS-NEXT: addi t6, t0, -1
+; RV32IMZBS-NEXT: bexti t0, a0, 24
+; RV32IMZBS-NEXT: addi t4, t0, -1
+; RV32IMZBS-NEXT: slli t0, t2, 24
+; RV32IMZBS-NEXT: and a2, t6, t0
; RV32IMZBS-NEXT: sw a2, 36(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a2, t5, s5
+; RV32IMZBS-NEXT: and a2, t4, s1
; RV32IMZBS-NEXT: sw a2, 40(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: and a2, s0, s5
+; RV32IMZBS-NEXT: and a2, t6, s1
; RV32IMZBS-NEXT: sw a2, 48(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: bexti s5, a1, 25
-; RV32IMZBS-NEXT: addi s5, s5, -1
-; RV32IMZBS-NEXT: bexti s8, a0, 25
-; RV32IMZBS-NEXT: addi s9, s8, -1
-; RV32IMZBS-NEXT: slli s8, t0, 25
-; RV32IMZBS-NEXT: and a2, s5, s8
+; RV32IMZBS-NEXT: bexti s1, a1, 25
+; RV32IMZBS-NEXT: addi s5, s1, -1
+; RV32IMZBS-NEXT: bexti s1, a0, 25
+; RV32IMZBS-NEXT: addi s9, s1, -1
+; RV32IMZBS-NEXT: slli s1, t2, 25
+; RV32IMZBS-NEXT: and a2, s5, s1
; RV32IMZBS-NEXT: sw a2, 72(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli s10, a7, 25
+; RV32IMZBS-NEXT: slli s10, t1, 25
; RV32IMZBS-NEXT: and a2, s9, s10
; RV32IMZBS-NEXT: sw a2, 76(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, s5, s10
@@ -10739,10 +10740,10 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: addi s5, s5, -1
; RV32IMZBS-NEXT: bexti s10, a0, 26
; RV32IMZBS-NEXT: addi s10, s10, -1
-; RV32IMZBS-NEXT: slli s11, t0, 26
+; RV32IMZBS-NEXT: slli s11, t2, 26
; RV32IMZBS-NEXT: and a2, s5, s11
; RV32IMZBS-NEXT: sw a2, 100(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli s11, a7, 26
+; RV32IMZBS-NEXT: slli s11, t1, 26
; RV32IMZBS-NEXT: and a2, s10, s11
; RV32IMZBS-NEXT: sw a2, 104(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, s5, s11
@@ -10751,10 +10752,10 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: addi s5, s5, -1
; RV32IMZBS-NEXT: bexti s10, a0, 27
; RV32IMZBS-NEXT: addi s10, s10, -1
-; RV32IMZBS-NEXT: slli s11, t0, 27
+; RV32IMZBS-NEXT: slli s11, t2, 27
; RV32IMZBS-NEXT: and a2, s5, s11
; RV32IMZBS-NEXT: sw a2, 124(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli s11, a7, 27
+; RV32IMZBS-NEXT: slli s11, t1, 27
; RV32IMZBS-NEXT: and a2, s10, s11
; RV32IMZBS-NEXT: sw a2, 128(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, s5, s11
@@ -10763,10 +10764,10 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: addi s5, s5, -1
; RV32IMZBS-NEXT: bexti s10, a0, 28
; RV32IMZBS-NEXT: addi s10, s10, -1
-; RV32IMZBS-NEXT: slli s11, t0, 28
+; RV32IMZBS-NEXT: slli s11, t2, 28
; RV32IMZBS-NEXT: and a2, s5, s11
; RV32IMZBS-NEXT: sw a2, 168(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli s11, a7, 28
+; RV32IMZBS-NEXT: slli s11, t1, 28
; RV32IMZBS-NEXT: and a2, s10, s11
; RV32IMZBS-NEXT: sw a2, 164(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: and a2, s5, s11
@@ -10775,94 +10776,95 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: addi s5, s5, -1
; RV32IMZBS-NEXT: bexti s10, a0, 29
; RV32IMZBS-NEXT: addi s10, s10, -1
-; RV32IMZBS-NEXT: slli s11, t0, 29
+; RV32IMZBS-NEXT: slli s11, t2, 29
; RV32IMZBS-NEXT: and s11, s5, s11
-; RV32IMZBS-NEXT: slli ra, a7, 29
-; RV32IMZBS-NEXT: and s0, s10, ra
-; RV32IMZBS-NEXT: and s8, s5, ra
-; RV32IMZBS-NEXT: andi t1, t1, 1
-; RV32IMZBS-NEXT: andi t4, t4, 1
-; RV32IMZBS-NEXT: seqz t1, t1
-; RV32IMZBS-NEXT: seqz t4, t4
-; RV32IMZBS-NEXT: addi t1, t1, -1
-; RV32IMZBS-NEXT: addi t4, t4, -1
-; RV32IMZBS-NEXT: slli ra, t0, 30
-; RV32IMZBS-NEXT: and t0, t1, t0
-; RV32IMZBS-NEXT: and t4, t4, a7
-; RV32IMZBS-NEXT: and a2, t1, a7
+; RV32IMZBS-NEXT: slli ra, t1, 29
+; RV32IMZBS-NEXT: and t0, s10, ra
+; RV32IMZBS-NEXT: and a2, s5, ra
; RV32IMZBS-NEXT: sw a2, 20(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a7, a7, 30
+; RV32IMZBS-NEXT: andi t3, t3, 1
+; RV32IMZBS-NEXT: andi s8, s8, 1
+; RV32IMZBS-NEXT: seqz t3, t3
+; RV32IMZBS-NEXT: seqz s8, s8
+; RV32IMZBS-NEXT: addi t3, t3, -1
+; RV32IMZBS-NEXT: addi s8, s8, -1
+; RV32IMZBS-NEXT: slli ra, t2, 30
+; RV32IMZBS-NEXT: and t2, t3, t2
+; RV32IMZBS-NEXT: and s8, s8, t1
+; RV32IMZBS-NEXT: and a2, t3, t1
+; RV32IMZBS-NEXT: sw a2, 16(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli t1, t1, 30
; RV32IMZBS-NEXT: bexti a1, a1, 30
; RV32IMZBS-NEXT: bexti a0, a0, 30
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: addi a0, a0, -1
; RV32IMZBS-NEXT: and ra, a1, ra
-; RV32IMZBS-NEXT: and a0, a0, a7
-; RV32IMZBS-NEXT: and a1, a1, a7
-; RV32IMZBS-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a0, a0, t1
+; RV32IMZBS-NEXT: and a1, a1, t1
+; RV32IMZBS-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: lw a1, 324(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a1, a1, s2
+; RV32IMZBS-NEXT: xor a1, a1, s4
; RV32IMZBS-NEXT: sw a1, 324(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 620(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a1, s4, a1
-; RV32IMZBS-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 608(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 568(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 632(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 616(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 608(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 536(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 516(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 616(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 604(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 564(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 536(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 456(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 448(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 604(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 532(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 512(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 516(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 412(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 404(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 532(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 452(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 444(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 456(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 380(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 372(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 512(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 408(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 400(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 448(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 356(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 452(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 376(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 368(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a1, a1, a2
+; RV32IMZBS-NEXT: sw a1, 444(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 348(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a2, 320(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 412(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 340(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a1, a1, s1
-; RV32IMZBS-NEXT: sw a1, 620(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 624(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a1, s3, a1
-; RV32IMZBS-NEXT: sw a1, 404(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 616(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 580(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 408(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: xor a1, s3, s0
+; RV32IMZBS-NEXT: sw a1, 632(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 648(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 620(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 616(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 540(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 532(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 620(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 612(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 576(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 580(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 468(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 452(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 612(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 536(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 528(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 452(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 420(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 408(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 576(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 464(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 448(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 420(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 384(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 376(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 528(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 416(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 404(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 408(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a1, 364(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 332(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a1, 448(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 380(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 372(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 384(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 416(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a1, 356(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a1, a1, s6
+; RV32IMZBS-NEXT: sw a1, 404(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: lw a1, 316(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a1, t0, a1
-; RV32IMZBS-NEXT: sw a1, 624(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: xor a1, t2, a1
+; RV32IMZBS-NEXT: sw a1, 648(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: lw a1, 292(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a2, 268(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
@@ -10878,57 +10880,57 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: lw a1, 108(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a2, 92(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 364(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a1, 368(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: lw a1, 56(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a2, 44(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a1, a1, a2
-; RV32IMZBS-NEXT: sw a1, 356(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: xor s9, a1, a2
; RV32IMZBS-NEXT: lw a1, 28(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a2, 24(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s10, a1, a2
; RV32IMZBS-NEXT: xor s11, s11, ra
-; RV32IMZBS-NEXT: xor ra, t4, s6
+; RV32IMZBS-NEXT: xor a1, s8, s2
+; RV32IMZBS-NEXT: sw a1, 400(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: lw a1, 304(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a2, 276(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s5, a1, a2
+; RV32IMZBS-NEXT: xor ra, a1, a2
; RV32IMZBS-NEXT: lw a1, 256(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s1, 236(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s1, a1, s1
+; RV32IMZBS-NEXT: lw s0, 236(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s0, a1, s0
; RV32IMZBS-NEXT: lw a1, 192(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 176(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s2, a1, a2
+; RV32IMZBS-NEXT: lw s1, 176(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s1, a1, s1
; RV32IMZBS-NEXT: lw a1, 120(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a2, 96(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s3, a1, a2
+; RV32IMZBS-NEXT: xor s2, a1, a2
; RV32IMZBS-NEXT: lw a1, 60(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a2, 52(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s4, a1, a2
-; RV32IMZBS-NEXT: xor s6, a4, a3
-; RV32IMZBS-NEXT: xor s0, s0, a0
-; RV32IMZBS-NEXT: xor s7, s7, t2
-; RV32IMZBS-NEXT: lw a0, 672(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t0, t6, a0
-; RV32IMZBS-NEXT: lw a0, 652(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 632(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s3, a1, a2
+; RV32IMZBS-NEXT: xor s4, a4, a3
+; RV32IMZBS-NEXT: xor s6, t0, a0
+; RV32IMZBS-NEXT: xor s5, t5, a5
+; RV32IMZBS-NEXT: xor t0, a7, s7
+; RV32IMZBS-NEXT: lw a0, 656(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 628(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t1, a0, a1
-; RV32IMZBS-NEXT: lw a0, 592(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 564(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 588(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 560(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t2, a0, a1
-; RV32IMZBS-NEXT: lw a0, 504(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 488(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 500(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 484(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t3, a0, a1
-; RV32IMZBS-NEXT: lw a0, 436(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 428(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 432(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 424(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t4, a0, a1
-; RV32IMZBS-NEXT: lw a0, 392(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 388(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 388(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 384(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t5, a0, a1
-; RV32IMZBS-NEXT: lw a0, 368(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t6, a5, a0
-; RV32IMZBS-NEXT: lw a0, 360(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 20(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 364(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 360(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor t6, a0, a1
+; RV32IMZBS-NEXT: lw a0, 352(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a7, a1, a0
-; RV32IMZBS-NEXT: lw a0, 348(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 340(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a1, 312(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a0, a1
; RV32IMZBS-NEXT: lw a1, 288(sp) # 4-byte Folded Reload
@@ -10945,142 +10947,142 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: xor a4, a4, a5
; RV32IMZBS-NEXT: lw a5, 32(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a5, a5, a6
-; RV32IMZBS-NEXT: lw a6, 16(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a6, s8, a6
-; RV32IMZBS-NEXT: lw s8, 324(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 12(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s8, s8, s9
-; RV32IMZBS-NEXT: sw s8, 568(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s8, 640(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 608(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s8, s9, s8
-; RV32IMZBS-NEXT: sw s8, 564(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s8, 572(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 536(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s8, s9, s8
-; RV32IMZBS-NEXT: sw s8, 540(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s8, 508(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 516(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s8, s9, s8
-; RV32IMZBS-NEXT: sw s8, 536(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s8, 440(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 456(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s8, s9, s8
-; RV32IMZBS-NEXT: sw s8, 532(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s8, 396(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 448(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s8, s9, s8
-; RV32IMZBS-NEXT: sw s8, 516(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s8, 716(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 412(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s8, s9, s8
-; RV32IMZBS-NEXT: sw s8, 716(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s8, 620(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 404(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s8, s8, s9
-; RV32IMZBS-NEXT: sw s8, 488(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s8, 656(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 616(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s8, s9, s8
-; RV32IMZBS-NEXT: sw s8, 468(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s8, 600(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 580(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s8, s9, s8
-; RV32IMZBS-NEXT: sw s8, 456(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s8, 520(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 452(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s8, s9, s8
-; RV32IMZBS-NEXT: sw s8, 452(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a6, 20(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a6, a6, s7
+; RV32IMZBS-NEXT: lw s7, 324(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 616(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s7, s8
+; RV32IMZBS-NEXT: sw s7, 588(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 640(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 604(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s8, s7
+; RV32IMZBS-NEXT: sw s7, 564(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 568(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 532(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s8, s7
+; RV32IMZBS-NEXT: sw s7, 568(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 504(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 512(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s8, s7
+; RV32IMZBS-NEXT: sw s7, 560(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 436(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 452(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s8, s7
+; RV32IMZBS-NEXT: sw s7, 536(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 392(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw s8, 444(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 420(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s8, s9, s8
-; RV32IMZBS-NEXT: sw s8, 448(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s8, 400(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 408(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s8, s9, s8
-; RV32IMZBS-NEXT: sw s8, 444(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s8, 720(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 384(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s8, s9, s8
-; RV32IMZBS-NEXT: sw s8, 720(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s8, 624(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 380(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s8, s8, s9
-; RV32IMZBS-NEXT: sw s8, 672(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s8, 296(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 376(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s8, s9, s8
-; RV32IMZBS-NEXT: sw s8, 656(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s8, 228(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 372(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s8, s9, s8
-; RV32IMZBS-NEXT: sw s8, 652(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s8, 144(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 364(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s8, s9, s8
-; RV32IMZBS-NEXT: sw s8, 640(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s8, 80(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 356(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s9, s9, s8
-; RV32IMZBS-NEXT: lw s8, 36(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s10, s10, s8
-; RV32IMZBS-NEXT: lw s8, 704(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s8, s11, s8
-; RV32IMZBS-NEXT: sw s8, 704(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: xor s8, ra, s5
-; RV32IMZBS-NEXT: lw s5, 308(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s1, s1, s5
-; RV32IMZBS-NEXT: sw s1, 632(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s1, 240(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s1, s2, s1
-; RV32IMZBS-NEXT: sw s1, 624(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s1, 152(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s1, s3, s1
-; RV32IMZBS-NEXT: sw s1, 620(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s1, 84(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s1, s4, s1
-; RV32IMZBS-NEXT: sw s1, 616(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s1, 40(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s1, s6, s1
-; RV32IMZBS-NEXT: sw s1, 608(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw s1, 708(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s0, s0, s1
+; RV32IMZBS-NEXT: xor s7, s8, s7
+; RV32IMZBS-NEXT: sw s7, 532(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 720(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 408(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s8, s7
+; RV32IMZBS-NEXT: sw s7, 720(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 632(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 620(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s7, s8
+; RV32IMZBS-NEXT: sw s7, 504(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 660(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 612(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s8, s7
+; RV32IMZBS-NEXT: sw s7, 500(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 596(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 576(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s8, s7
+; RV32IMZBS-NEXT: sw s7, 484(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 516(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 528(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s8, s7
+; RV32IMZBS-NEXT: sw s7, 464(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 440(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 448(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s8, s7
+; RV32IMZBS-NEXT: sw s7, 452(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 396(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 416(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s8, s7
+; RV32IMZBS-NEXT: sw s7, 448(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 724(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 404(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s8, s7
+; RV32IMZBS-NEXT: sw s7, 724(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 648(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 380(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s7, s8
+; RV32IMZBS-NEXT: sw s7, 660(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 296(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 376(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s8, s7
+; RV32IMZBS-NEXT: sw s7, 656(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 228(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 372(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s8, s7
+; RV32IMZBS-NEXT: sw s7, 648(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 144(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 368(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s8, s7
+; RV32IMZBS-NEXT: sw s7, 640(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 80(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s9, s9, s7
+; RV32IMZBS-NEXT: lw s7, 36(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s10, s10, s7
+; RV32IMZBS-NEXT: lw s7, 704(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s7, s11, s7
+; RV32IMZBS-NEXT: sw s7, 704(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s7, 400(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s8, s7, ra
+; RV32IMZBS-NEXT: lw s7, 308(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s0, s0, s7
+; RV32IMZBS-NEXT: sw s0, 632(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s0, 240(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s1, s1, s0
+; RV32IMZBS-NEXT: lw s0, 152(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s0, s2, s0
+; RV32IMZBS-NEXT: sw s0, 628(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s0, 84(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s0, s3, s0
+; RV32IMZBS-NEXT: sw s0, 620(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s0, s4, s0
+; RV32IMZBS-NEXT: sw s0, 616(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw s0, 708(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s0, s6, s0
; RV32IMZBS-NEXT: sw s0, 708(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: xor t0, s7, t0
-; RV32IMZBS-NEXT: sw t0, 600(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: xor t0, s5, t0
+; RV32IMZBS-NEXT: sw t0, 612(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: lw t0, 676(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t1, t1, t0
-; RV32IMZBS-NEXT: lw t0, 628(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t0, 624(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, t2, t0
; RV32IMZBS-NEXT: sw t0, 676(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw t0, 552(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t0, 548(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, t3, t0
-; RV32IMZBS-NEXT: sw t0, 628(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw t0, 476(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw t0, 624(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw t0, 472(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, t4, t0
-; RV32IMZBS-NEXT: sw t0, 592(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw t0, 416(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw t0, 604(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw t0, 412(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, t5, t0
-; RV32IMZBS-NEXT: sw t0, 580(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw t0, 596(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: lw t0, 712(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, t6, t0
; RV32IMZBS-NEXT: sw t0, 712(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: xor a0, a7, a0
-; RV32IMZBS-NEXT: sw a0, 572(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 344(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a0, 576(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a0, 336(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a1, a0
-; RV32IMZBS-NEXT: sw a0, 552(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 548(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: lw a0, 260(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a2, a0
-; RV32IMZBS-NEXT: sw a0, 520(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 528(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: lw a0, 188(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a3, a3, a0
; RV32IMZBS-NEXT: lw a0, 112(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a4, a0
-; RV32IMZBS-NEXT: sw a0, 508(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 516(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a5, a0
-; RV32IMZBS-NEXT: sw a0, 504(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 512(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: lw a0, 692(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a6, a0
; RV32IMZBS-NEXT: sw a0, 692(sp) # 4-byte Folded Spill
@@ -11099,44 +11101,44 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: slli a6, a6, 4
; RV32IMZBS-NEXT: or a0, a5, a6
; RV32IMZBS-NEXT: sw a0, 688(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 568(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 588(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a2, 564(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a0, a2
-; RV32IMZBS-NEXT: sw a0, 568(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 660(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 540(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a0, 588(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a0, 664(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 568(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor ra, a2, a0
-; RV32IMZBS-NEXT: lw a0, 588(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 584(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 560(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a0, a2, a0
+; RV32IMZBS-NEXT: sw a0, 584(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a0, 492(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a2, 536(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a2, a0
-; RV32IMZBS-NEXT: sw a0, 588(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 496(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a0, 568(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a0, 420(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a2, 532(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a2, a0
; RV32IMZBS-NEXT: sw a0, 564(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 424(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 516(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a0, a2, a0
-; RV32IMZBS-NEXT: sw a0, 540(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 488(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 468(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 504(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 500(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a0, a2
-; RV32IMZBS-NEXT: sw a0, 660(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 664(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 456(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a0, 664(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a0, 668(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 484(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s11, a2, a0
-; RV32IMZBS-NEXT: lw a0, 604(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 600(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 464(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a0, a2, a0
+; RV32IMZBS-NEXT: sw a0, 668(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a0, 508(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a2, 452(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a2, a0
-; RV32IMZBS-NEXT: sw a0, 664(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 512(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: sw a0, 600(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: lw a0, 428(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a2, 448(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a2, a0
-; RV32IMZBS-NEXT: sw a0, 604(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 432(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 444(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a0, a2, a0
-; RV32IMZBS-NEXT: sw a0, 536(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 560(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: lw a0, 696(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: srli t2, a0, 4
; RV32IMZBS-NEXT: and t3, a0, a1
@@ -11151,12 +11153,12 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: slli a0, a0, 4
; RV32IMZBS-NEXT: or a0, t3, a0
; RV32IMZBS-NEXT: sw a0, 700(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: lw a0, 672(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 660(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a1, 656(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a0, a1
-; RV32IMZBS-NEXT: sw a0, 672(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 660(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: lw a0, 328(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 652(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 648(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s5, a1, a0
; RV32IMZBS-NEXT: lw a0, 244(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a1, 640(sp) # 4-byte Folded Reload
@@ -11167,69 +11169,68 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: xor s3, s10, a0
; RV32IMZBS-NEXT: lw a0, 632(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s4, s8, a0
-; RV32IMZBS-NEXT: lw a0, 336(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s0, 624(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s0, s0, a0
+; RV32IMZBS-NEXT: lw a0, 332(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s0, s1, a0
; RV32IMZBS-NEXT: lw a0, 252(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s1, 620(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s1, 628(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s1, s1, a0
; RV32IMZBS-NEXT: lw a0, 160(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 616(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 620(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t4, a1, a0
; RV32IMZBS-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 608(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 616(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t5, a1, a0
-; RV32IMZBS-NEXT: lw a0, 600(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 612(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t6, a0, t1
; RV32IMZBS-NEXT: lw a0, 680(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a1, 676(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t2, a1, a0
; RV32IMZBS-NEXT: lw a0, 636(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 628(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 624(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t3, a1, a0
-; RV32IMZBS-NEXT: lw a0, 548(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 592(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 544(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 604(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a7, a1, a0
-; RV32IMZBS-NEXT: lw a0, 460(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 580(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 456(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 596(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, a1, a0
-; RV32IMZBS-NEXT: lw a0, 572(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 552(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 576(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 548(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t1, a0, a1
-; RV32IMZBS-NEXT: lw a0, 352(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a4, 520(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 344(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a4, 528(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a4, a4, a0
; RV32IMZBS-NEXT: lw a0, 272(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a5, a3, a0
; RV32IMZBS-NEXT: lw a0, 180(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 508(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 516(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a6, a1, a0
; RV32IMZBS-NEXT: lw a0, 88(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a3, 504(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a3, 512(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a3, a3, a0
-; RV32IMZBS-NEXT: lw a0, 568(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 588(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor ra, a0, ra
; RV32IMZBS-NEXT: lw a0, 644(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 588(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 584(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a1, a0
-; RV32IMZBS-NEXT: lw a1, 556(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a2, 564(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 552(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 568(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a2, a1
-; RV32IMZBS-NEXT: lw a2, 464(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s8, 540(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a2, 460(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 564(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a2, s8, a2
-; RV32IMZBS-NEXT: lw s8, 660(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 664(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s11, s8, s11
-; RV32IMZBS-NEXT: lw s8, 648(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s9, 664(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s8, 652(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s9, 668(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s8, s9, s8
-; RV32IMZBS-NEXT: lw s9, 560(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s10, 604(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s9, 556(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s10, 600(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s9, s10, s9
-; RV32IMZBS-NEXT: lw s10, 472(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw s7, 536(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s10, 468(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s7, 560(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s10, s7, s10
-; RV32IMZBS-NEXT: lw s7, 672(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s7, 660(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s5, s7, s5
; RV32IMZBS-NEXT: lw s7, 280(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s6, s6, s7
@@ -11245,11 +11246,11 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: lw s4, 104(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t5, t5, s4
; RV32IMZBS-NEXT: xor t2, t6, t2
-; RV32IMZBS-NEXT: lw t6, 668(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t6, 672(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t3, t3, t6
-; RV32IMZBS-NEXT: lw t6, 576(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t6, 572(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a7, a7, t6
-; RV32IMZBS-NEXT: lw t6, 480(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t6, 476(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, t0, t6
; RV32IMZBS-NEXT: xor a4, t1, a4
; RV32IMZBS-NEXT: lw t1, 300(sp) # 4-byte Folded Reload
@@ -11259,14 +11260,14 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: lw t1, 116(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a3, a3, t1
; RV32IMZBS-NEXT: xor a0, ra, a0
-; RV32IMZBS-NEXT: lw t1, 584(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t1, 580(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, t1
-; RV32IMZBS-NEXT: lw t1, 484(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t1, 480(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a2, a2, t1
; RV32IMZBS-NEXT: xor t1, s11, s8
-; RV32IMZBS-NEXT: lw t6, 596(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t6, 592(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t6, s9, t6
-; RV32IMZBS-NEXT: lw s4, 492(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw s4, 488(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s4, s10, s4
; RV32IMZBS-NEXT: xor s5, s5, s6
; RV32IMZBS-NEXT: lw s6, 212(sp) # 4-byte Folded Reload
@@ -11279,9 +11280,9 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: lw s1, 128(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t5, t5, s1
; RV32IMZBS-NEXT: xor t2, t2, t3
-; RV32IMZBS-NEXT: lw t3, 612(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t3, 608(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a7, a7, t3
-; RV32IMZBS-NEXT: lw t3, 500(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t3, 496(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, t0, t3
; RV32IMZBS-NEXT: xor a4, a4, a5
; RV32IMZBS-NEXT: lw a5, 232(sp) # 4-byte Folded Reload
@@ -11302,10 +11303,10 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: slli s1, s1, 2
; RV32IMZBS-NEXT: or t3, t3, s1
; RV32IMZBS-NEXT: xor a0, a0, a1
-; RV32IMZBS-NEXT: lw a1, 528(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 524(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a2, a1
; RV32IMZBS-NEXT: xor a2, t1, t6
-; RV32IMZBS-NEXT: lw t1, 524(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t1, 520(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t1, s4, t1
; RV32IMZBS-NEXT: lw s1, 696(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: srli t6, s1, 2
@@ -11326,7 +11327,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: lw s0, 164(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t5, t5, s0
; RV32IMZBS-NEXT: xor a7, t2, a7
-; RV32IMZBS-NEXT: lw t2, 544(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t2, 540(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, t0, t2
; RV32IMZBS-NEXT: xor a4, a4, a5
; RV32IMZBS-NEXT: lw a5, 172(sp) # 4-byte Folded Reload
@@ -11334,129 +11335,131 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: xor a0, a0, a1
; RV32IMZBS-NEXT: xor a1, a2, t1
; RV32IMZBS-NEXT: srli a2, a6, 1
-; RV32IMZBS-NEXT: lw s4, 724(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: and a5, a6, s4
+; RV32IMZBS-NEXT: lw s7, 716(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: and a5, a6, s7
; RV32IMZBS-NEXT: xor a6, s2, s3
; RV32IMZBS-NEXT: srli t1, t3, 1
-; RV32IMZBS-NEXT: and t2, t3, s4
+; RV32IMZBS-NEXT: and t2, t3, s7
; RV32IMZBS-NEXT: xor t3, t4, t5
; RV32IMZBS-NEXT: srli t4, t6, 1
-; RV32IMZBS-NEXT: and t5, t6, s4
+; RV32IMZBS-NEXT: and t5, t6, s7
; RV32IMZBS-NEXT: xor a7, a7, t0
; RV32IMZBS-NEXT: srli t0, s1, 1
-; RV32IMZBS-NEXT: and t6, s1, s4
+; RV32IMZBS-NEXT: and t6, s1, s7
; RV32IMZBS-NEXT: xor a3, a4, a3
-; RV32IMZBS-NEXT: and a2, a2, s4
+; RV32IMZBS-NEXT: and a4, a2, s7
; RV32IMZBS-NEXT: slli a5, a5, 1
-; RV32IMZBS-NEXT: and a4, t1, s4
+; RV32IMZBS-NEXT: and t1, t1, s7
; RV32IMZBS-NEXT: slli t2, t2, 1
-; RV32IMZBS-NEXT: lw t1, 716(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t1, a0, t1
+; RV32IMZBS-NEXT: slli a2, a2, 31
; RV32IMZBS-NEXT: lw s0, 720(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s0, a1, s0
-; RV32IMZBS-NEXT: and t4, t4, s4
+; RV32IMZBS-NEXT: xor s0, a0, s0
+; RV32IMZBS-NEXT: lw s1, 724(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor s1, a1, s1
+; RV32IMZBS-NEXT: and s2, t4, s7
; RV32IMZBS-NEXT: slli t5, t5, 1
-; RV32IMZBS-NEXT: and t0, t0, s4
+; RV32IMZBS-NEXT: and t0, t0, s7
; RV32IMZBS-NEXT: slli t6, t6, 1
+; RV32IMZBS-NEXT: slli s5, t4, 31
; RV32IMZBS-NEXT: lw a0, 704(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor s1, a6, a0
+; RV32IMZBS-NEXT: xor a6, a6, a0
; RV32IMZBS-NEXT: lw a0, 708(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t3, t3, a0
+; RV32IMZBS-NEXT: xor s3, t3, a0
; RV32IMZBS-NEXT: lw a0, 712(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a7, a7, a0
+; RV32IMZBS-NEXT: xor s4, a7, a0
; RV32IMZBS-NEXT: lw a0, 692(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a3, a3, a0
-; RV32IMZBS-NEXT: or a0, a2, a5
-; RV32IMZBS-NEXT: or a1, a4, t2
-; RV32IMZBS-NEXT: srli a2, t2, 31
-; RV32IMZBS-NEXT: xor a4, s0, t1
-; RV32IMZBS-NEXT: sw a4, 720(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: or t2, t4, t5
+; RV32IMZBS-NEXT: or a0, a4, a5
+; RV32IMZBS-NEXT: or a1, t1, t2
+; RV32IMZBS-NEXT: srli a4, t2, 31
+; RV32IMZBS-NEXT: xor s0, s1, s0
+; RV32IMZBS-NEXT: sw s0, 724(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: or t4, s2, t5
; RV32IMZBS-NEXT: or s2, t0, t6
-; RV32IMZBS-NEXT: srli a4, t6, 31
-; RV32IMZBS-NEXT: xor a5, t3, s1
-; RV32IMZBS-NEXT: sw a5, 716(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: srli a5, a7, 8
-; RV32IMZBS-NEXT: srli t0, a7, 24
-; RV32IMZBS-NEXT: slli a6, a7, 24
-; RV32IMZBS-NEXT: lw s5, 740(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: and a7, a7, s5
-; RV32IMZBS-NEXT: srli t3, a3, 8
-; RV32IMZBS-NEXT: srli t4, a3, 24
-; RV32IMZBS-NEXT: slli t5, a3, 24
-; RV32IMZBS-NEXT: and a3, a3, s5
-; RV32IMZBS-NEXT: slli t6, a0, 1
-; RV32IMZBS-NEXT: andi s0, a1, 2
-; RV32IMZBS-NEXT: slli s1, a0, 2
-; RV32IMZBS-NEXT: andi t1, a1, 4
-; RV32IMZBS-NEXT: slli s3, a0, 3
-; RV32IMZBS-NEXT: and a5, a5, s5
-; RV32IMZBS-NEXT: or a5, a5, t0
-; RV32IMZBS-NEXT: andi t0, a1, 8
-; RV32IMZBS-NEXT: slli a7, a7, 8
-; RV32IMZBS-NEXT: or a7, a6, a7
-; RV32IMZBS-NEXT: slli a6, a0, 4
-; RV32IMZBS-NEXT: and t3, t3, s5
-; RV32IMZBS-NEXT: or t3, t3, t4
-; RV32IMZBS-NEXT: andi t4, a1, 16
+; RV32IMZBS-NEXT: srli a5, t6, 31
+; RV32IMZBS-NEXT: xor a6, s3, a6
+; RV32IMZBS-NEXT: sw a6, 720(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: srli a6, s4, 8
+; RV32IMZBS-NEXT: srli t0, s4, 24
+; RV32IMZBS-NEXT: slli t1, s4, 24
+; RV32IMZBS-NEXT: lw t3, 740(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: and t2, s4, t3
+; RV32IMZBS-NEXT: srli t5, a3, 8
+; RV32IMZBS-NEXT: srli t6, a3, 24
+; RV32IMZBS-NEXT: slli s0, a3, 24
+; RV32IMZBS-NEXT: and a3, a3, t3
+; RV32IMZBS-NEXT: slli s1, a0, 1
+; RV32IMZBS-NEXT: andi a7, a1, 2
+; RV32IMZBS-NEXT: slli s3, a0, 2
+; RV32IMZBS-NEXT: and a6, a6, t3
+; RV32IMZBS-NEXT: or a6, a6, t0
+; RV32IMZBS-NEXT: andi t0, a1, 4
+; RV32IMZBS-NEXT: slli t2, t2, 8
+; RV32IMZBS-NEXT: or t1, t1, t2
+; RV32IMZBS-NEXT: slli t2, a0, 3
+; RV32IMZBS-NEXT: and t5, t5, t3
+; RV32IMZBS-NEXT: or t5, t5, t6
+; RV32IMZBS-NEXT: andi t6, a1, 8
; RV32IMZBS-NEXT: slli a3, a3, 8
-; RV32IMZBS-NEXT: or a3, t5, a3
-; RV32IMZBS-NEXT: slli t5, a0, 31
-; RV32IMZBS-NEXT: seqz a2, a2
-; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: and a2, a2, t5
-; RV32IMZBS-NEXT: sw a2, 700(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, t2, 31
+; RV32IMZBS-NEXT: or a3, s0, a3
+; RV32IMZBS-NEXT: slli s0, a0, 4
; RV32IMZBS-NEXT: seqz a4, a4
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: and a2, a4, a2
-; RV32IMZBS-NEXT: sw a2, 708(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a2, a0, 5
-; RV32IMZBS-NEXT: or a4, a7, a5
-; RV32IMZBS-NEXT: sw a4, 704(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a4, a1, 32
-; RV32IMZBS-NEXT: or a3, a3, t3
+; RV32IMZBS-NEXT: sw a2, 700(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a2, a1, 16
+; RV32IMZBS-NEXT: seqz a4, a5
+; RV32IMZBS-NEXT: addi a4, a4, -1
+; RV32IMZBS-NEXT: and a4, a4, s5
+; RV32IMZBS-NEXT: sw a4, 708(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a4, a0, 5
+; RV32IMZBS-NEXT: or a5, t1, a6
+; RV32IMZBS-NEXT: sw a5, 704(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a5, a1, 32
+; RV32IMZBS-NEXT: or a3, a3, t5
; RV32IMZBS-NEXT: sw a3, 712(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: slli a3, a0, 6
-; RV32IMZBS-NEXT: seqz a5, s0
-; RV32IMZBS-NEXT: addi a5, a5, -1
-; RV32IMZBS-NEXT: and a5, a5, t6
-; RV32IMZBS-NEXT: sw a5, 692(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a5, a1, 64
-; RV32IMZBS-NEXT: seqz a7, t1
-; RV32IMZBS-NEXT: addi a7, a7, -1
-; RV32IMZBS-NEXT: and a7, a7, s1
-; RV32IMZBS-NEXT: sw a7, 688(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a7, a0, 7
+; RV32IMZBS-NEXT: seqz a6, a7
+; RV32IMZBS-NEXT: addi a6, a6, -1
+; RV32IMZBS-NEXT: and a6, a6, s1
+; RV32IMZBS-NEXT: sw a6, 692(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a6, a1, 64
; RV32IMZBS-NEXT: seqz t0, t0
; RV32IMZBS-NEXT: addi t0, t0, -1
-; RV32IMZBS-NEXT: and t0, t0, s3
-; RV32IMZBS-NEXT: sw t0, 676(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi t0, a1, 128
-; RV32IMZBS-NEXT: seqz t3, t4
-; RV32IMZBS-NEXT: addi t3, t3, -1
-; RV32IMZBS-NEXT: and a6, t3, a6
-; RV32IMZBS-NEXT: sw a6, 672(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: slli a6, a0, 8
-; RV32IMZBS-NEXT: seqz a4, a4
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: and a2, a4, a2
-; RV32IMZBS-NEXT: sw a2, 664(sp) # 4-byte Folded Spill
-; RV32IMZBS-NEXT: andi a2, a1, 256
-; RV32IMZBS-NEXT: seqz a4, a5
-; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: and a3, a4, a3
+; RV32IMZBS-NEXT: and a7, t0, s3
+; RV32IMZBS-NEXT: sw a7, 688(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli t0, a0, 7
+; RV32IMZBS-NEXT: seqz t1, t6
+; RV32IMZBS-NEXT: addi t1, t1, -1
+; RV32IMZBS-NEXT: and a7, t1, t2
+; RV32IMZBS-NEXT: sw a7, 676(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi t1, a1, 128
+; RV32IMZBS-NEXT: seqz a2, a2
+; RV32IMZBS-NEXT: addi a2, a2, -1
+; RV32IMZBS-NEXT: and a2, a2, s0
+; RV32IMZBS-NEXT: sw a2, 672(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: slli a2, a0, 8
+; RV32IMZBS-NEXT: seqz a5, a5
+; RV32IMZBS-NEXT: addi a5, a5, -1
+; RV32IMZBS-NEXT: and a4, a5, a4
+; RV32IMZBS-NEXT: sw a4, 664(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a4, a1, 256
+; RV32IMZBS-NEXT: seqz a5, a6
+; RV32IMZBS-NEXT: addi a5, a5, -1
+; RV32IMZBS-NEXT: and a3, a5, a3
; RV32IMZBS-NEXT: sw a3, 684(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: slli a3, a0, 9
-; RV32IMZBS-NEXT: seqz a4, t0
+; RV32IMZBS-NEXT: seqz a5, t1
+; RV32IMZBS-NEXT: addi a5, a5, -1
+; RV32IMZBS-NEXT: and a5, a5, t0
+; RV32IMZBS-NEXT: sw a5, 656(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: andi a5, a1, 512
+; RV32IMZBS-NEXT: seqz a4, a4
; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: and a5, a4, a7
-; RV32IMZBS-NEXT: andi a4, a1, 512
-; RV32IMZBS-NEXT: seqz a2, a2
-; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: and a7, a2, a6
+; RV32IMZBS-NEXT: and a2, a4, a2
+; RV32IMZBS-NEXT: sw a2, 644(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: slli a2, a0, 10
-; RV32IMZBS-NEXT: seqz a4, a4
+; RV32IMZBS-NEXT: seqz a4, a5
; RV32IMZBS-NEXT: addi a4, a4, -1
; RV32IMZBS-NEXT: and a3, a4, a3
; RV32IMZBS-NEXT: sw a3, 660(sp) # 4-byte Folded Spill
@@ -11469,18 +11472,17 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: bexti a3, a2, 11
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 11
-; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 636(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a5, a3, a4
; RV32IMZBS-NEXT: bexti a3, a2, 12
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 12
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 632(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 628(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 13
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 13
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 644(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 636(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 14
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 14
@@ -11495,258 +11497,257 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 16
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 612(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 608(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 17
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 17
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 608(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 604(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 18
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 18
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 620(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 616(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 19
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 19
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 648(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 640(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 20
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 20
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 652(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 648(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 21
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 21
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 656(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 652(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 22
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 22
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 600(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 596(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 23
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 23
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 596(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 592(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 24
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 24
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 604(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 600(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 25
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 25
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 616(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 612(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 26
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 26
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 624(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 620(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 27
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 27
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 628(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 624(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 28
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 28
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 640(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 632(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a3, a2, 29
; RV32IMZBS-NEXT: addi a3, a3, -1
; RV32IMZBS-NEXT: slli a4, a0, 29
; RV32IMZBS-NEXT: and a3, a3, a4
-; RV32IMZBS-NEXT: sw a3, 592(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a3, 588(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a1, a1, 1
; RV32IMZBS-NEXT: seqz a1, a1
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: and a1, a1, a0
-; RV32IMZBS-NEXT: sw a1, 584(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: and a6, a1, a0
; RV32IMZBS-NEXT: slli a0, a0, 30
; RV32IMZBS-NEXT: bexti a1, a2, 30
; RV32IMZBS-NEXT: addi a1, a1, -1
; RV32IMZBS-NEXT: and a0, a1, a0
-; RV32IMZBS-NEXT: sw a0, 588(sp) # 4-byte Folded Spill
+; RV32IMZBS-NEXT: sw a0, 584(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, s2, 2
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
-; RV32IMZBS-NEXT: slli a1, t2, 1
+; RV32IMZBS-NEXT: slli a1, t4, 1
; RV32IMZBS-NEXT: and a0, a0, a1
; RV32IMZBS-NEXT: sw a0, 580(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, s2, 4
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
-; RV32IMZBS-NEXT: slli a1, t2, 2
+; RV32IMZBS-NEXT: slli a1, t4, 2
; RV32IMZBS-NEXT: and a0, a0, a1
; RV32IMZBS-NEXT: sw a0, 576(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, s2, 8
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
-; RV32IMZBS-NEXT: slli a1, t2, 3
+; RV32IMZBS-NEXT: slli a1, t4, 3
; RV32IMZBS-NEXT: and a0, a0, a1
; RV32IMZBS-NEXT: sw a0, 568(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, s2, 16
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
-; RV32IMZBS-NEXT: slli a1, t2, 4
+; RV32IMZBS-NEXT: slli a1, t4, 4
; RV32IMZBS-NEXT: and a0, a0, a1
; RV32IMZBS-NEXT: sw a0, 560(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, s2, 32
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
-; RV32IMZBS-NEXT: slli a1, t2, 5
+; RV32IMZBS-NEXT: slli a1, t4, 5
; RV32IMZBS-NEXT: and a0, a0, a1
; RV32IMZBS-NEXT: sw a0, 556(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, s2, 64
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
-; RV32IMZBS-NEXT: slli a1, t2, 6
+; RV32IMZBS-NEXT: slli a1, t4, 6
; RV32IMZBS-NEXT: and a0, a0, a1
; RV32IMZBS-NEXT: sw a0, 564(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, s2, 128
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
-; RV32IMZBS-NEXT: slli a1, t2, 7
+; RV32IMZBS-NEXT: slli a1, t4, 7
; RV32IMZBS-NEXT: and a0, a0, a1
; RV32IMZBS-NEXT: sw a0, 540(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, s2, 256
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
-; RV32IMZBS-NEXT: slli a1, t2, 8
+; RV32IMZBS-NEXT: slli a1, t4, 8
; RV32IMZBS-NEXT: and a0, a0, a1
; RV32IMZBS-NEXT: sw a0, 536(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, s2, 512
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
-; RV32IMZBS-NEXT: slli a1, t2, 9
+; RV32IMZBS-NEXT: slli a1, t4, 9
; RV32IMZBS-NEXT: and a0, a0, a1
; RV32IMZBS-NEXT: sw a0, 544(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: andi a0, s2, 1024
; RV32IMZBS-NEXT: seqz a0, a0
; RV32IMZBS-NEXT: addi a0, a0, -1
-; RV32IMZBS-NEXT: slli a1, t2, 10
+; RV32IMZBS-NEXT: slli a1, t4, 10
; RV32IMZBS-NEXT: and a0, a0, a1
; RV32IMZBS-NEXT: sw a0, 572(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: not a0, s2
; RV32IMZBS-NEXT: bexti a1, a0, 11
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t2, 11
+; RV32IMZBS-NEXT: slli a2, t4, 11
; RV32IMZBS-NEXT: and a1, a1, a2
; RV32IMZBS-NEXT: sw a1, 516(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 12
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t2, 12
+; RV32IMZBS-NEXT: slli a2, t4, 12
; RV32IMZBS-NEXT: and s9, a1, a2
; RV32IMZBS-NEXT: bexti a1, a0, 13
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t2, 13
+; RV32IMZBS-NEXT: slli a2, t4, 13
; RV32IMZBS-NEXT: and a1, a1, a2
; RV32IMZBS-NEXT: sw a1, 524(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 14
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t2, 14
+; RV32IMZBS-NEXT: slli a2, t4, 14
; RV32IMZBS-NEXT: and a1, a1, a2
; RV32IMZBS-NEXT: sw a1, 548(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 15
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t2, 15
+; RV32IMZBS-NEXT: slli a2, t4, 15
; RV32IMZBS-NEXT: and a1, a1, a2
; RV32IMZBS-NEXT: sw a1, 552(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 16
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a3, t2, 16
-; RV32IMZBS-NEXT: and s5, a1, a3
+; RV32IMZBS-NEXT: slli a3, t4, 16
+; RV32IMZBS-NEXT: and s4, a1, a3
; RV32IMZBS-NEXT: bexti a1, a0, 17
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a2, t2, 17
+; RV32IMZBS-NEXT: slli a2, t4, 17
; RV32IMZBS-NEXT: and s3, a1, a2
; RV32IMZBS-NEXT: bexti a1, a0, 18
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a4, t2, 18
+; RV32IMZBS-NEXT: slli a4, t4, 18
; RV32IMZBS-NEXT: and s10, a1, a4
; RV32IMZBS-NEXT: bexti a1, a0, 19
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a4, t2, 19
+; RV32IMZBS-NEXT: slli a4, t4, 19
; RV32IMZBS-NEXT: and a1, a1, a4
; RV32IMZBS-NEXT: sw a1, 520(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 20
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli s0, t2, 20
+; RV32IMZBS-NEXT: slli s0, t4, 20
; RV32IMZBS-NEXT: and a1, a1, s0
; RV32IMZBS-NEXT: sw a1, 528(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 21
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli s1, t2, 21
+; RV32IMZBS-NEXT: slli s1, t4, 21
; RV32IMZBS-NEXT: and a1, a1, s1
; RV32IMZBS-NEXT: sw a1, 532(sp) # 4-byte Folded Spill
; RV32IMZBS-NEXT: bexti a1, a0, 22
; RV32IMZBS-NEXT: addi a1, a1, -1
-; RV32IMZBS-NEXT: slli a4, t2, 22
+; RV32IMZBS-NEXT: slli a4, t4, 22
; RV32IMZBS-NEXT: and s0, a1, a4
; RV32IMZBS-NEXT: bexti a2, a0, 23
; RV32IMZBS-NEXT: addi a2, a2, -1
-; RV32IMZBS-NEXT: slli a4, t2, 23
+; RV32IMZBS-NEXT: slli a4, t4, 23
; RV32IMZBS-NEXT: and t6, a2, a4
; RV32IMZBS-NEXT: bexti a3, a0, 24
; RV32IMZBS-NEXT: addi a3, a3, -1
-; RV32IMZBS-NEXT: slli a4, t2, 24
+; RV32IMZBS-NEXT: slli a4, t4, 24
; RV32IMZBS-NEXT: and s1, a3, a4
; RV32IMZBS-NEXT: bexti a4, a0, 25
; RV32IMZBS-NEXT: addi a4, a4, -1
-; RV32IMZBS-NEXT: slli t0, t2, 25
-; RV32IMZBS-NEXT: and s7, a4, t0
+; RV32IMZBS-NEXT: slli t0, t4, 25
+; RV32IMZBS-NEXT: and s5, a4, t0
; RV32IMZBS-NEXT: bexti t0, a0, 26
; RV32IMZBS-NEXT: addi t0, t0, -1
-; RV32IMZBS-NEXT: slli t3, t2, 26
-; RV32IMZBS-NEXT: and s8, t0, t3
-; RV32IMZBS-NEXT: bexti t3, a0, 27
-; RV32IMZBS-NEXT: addi t3, t3, -1
-; RV32IMZBS-NEXT: slli t5, t2, 27
-; RV32IMZBS-NEXT: and s11, t3, t5
+; RV32IMZBS-NEXT: slli t2, t4, 26
+; RV32IMZBS-NEXT: and s8, t0, t2
+; RV32IMZBS-NEXT: bexti t2, a0, 27
+; RV32IMZBS-NEXT: addi t2, t2, -1
+; RV32IMZBS-NEXT: slli t5, t4, 27
+; RV32IMZBS-NEXT: and s11, t2, t5
; RV32IMZBS-NEXT: bexti t5, a0, 28
; RV32IMZBS-NEXT: addi t5, t5, -1
-; RV32IMZBS-NEXT: slli a6, t2, 28
-; RV32IMZBS-NEXT: and t5, t5, a6
-; RV32IMZBS-NEXT: bexti a6, a0, 29
-; RV32IMZBS-NEXT: addi a6, a6, -1
-; RV32IMZBS-NEXT: slli t1, t2, 29
-; RV32IMZBS-NEXT: and t4, a6, t1
-; RV32IMZBS-NEXT: andi t1, s2, 1
-; RV32IMZBS-NEXT: seqz t1, t1
-; RV32IMZBS-NEXT: addi t1, t1, -1
-; RV32IMZBS-NEXT: and t1, t1, t2
-; RV32IMZBS-NEXT: slli t2, t2, 30
+; RV32IMZBS-NEXT: slli a7, t4, 28
+; RV32IMZBS-NEXT: and t5, t5, a7
+; RV32IMZBS-NEXT: bexti a7, a0, 29
+; RV32IMZBS-NEXT: addi a7, a7, -1
+; RV32IMZBS-NEXT: slli t3, t4, 29
+; RV32IMZBS-NEXT: and t2, a7, t3
+; RV32IMZBS-NEXT: andi t3, s2, 1
+; RV32IMZBS-NEXT: seqz t3, t3
+; RV32IMZBS-NEXT: addi t3, t3, -1
+; RV32IMZBS-NEXT: and t3, t3, t4
+; RV32IMZBS-NEXT: slli t4, t4, 30
; RV32IMZBS-NEXT: bexti a0, a0, 30
; RV32IMZBS-NEXT: addi a0, a0, -1
-; RV32IMZBS-NEXT: and t3, a0, t2
+; RV32IMZBS-NEXT: and t1, a0, t4
; RV32IMZBS-NEXT: lw a0, 692(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 584(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t2, a1, a0
+; RV32IMZBS-NEXT: xor t4, a6, a0
; RV32IMZBS-NEXT: lw a0, 688(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a1, 676(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s2, a0, a1
; RV32IMZBS-NEXT: lw a0, 672(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a1, 664(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a6, a0, a1
-; RV32IMZBS-NEXT: xor a7, a5, a7
-; RV32IMZBS-NEXT: lw a0, 636(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a1, 632(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t0, a0, a1
-; RV32IMZBS-NEXT: lw a0, 612(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a3, 608(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 656(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a1, 644(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor a7, a0, a1
+; RV32IMZBS-NEXT: lw a0, 628(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor t0, a5, a0
+; RV32IMZBS-NEXT: lw a0, 608(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a3, 604(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a3, a0, a3
-; RV32IMZBS-NEXT: lw a0, 600(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a4, 596(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 596(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a4, 592(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a4, a0, a4
-; RV32IMZBS-NEXT: lw a0, 592(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: lw a5, 588(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a0, 588(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a5, 584(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a5, a0, a5
; RV32IMZBS-NEXT: lw a0, 580(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t1, t1, a0
+; RV32IMZBS-NEXT: xor t3, t3, a0
; RV32IMZBS-NEXT: lw a0, 576(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: lw a1, 568(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a0, a0, a1
@@ -11758,40 +11759,40 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: xor a2, a2, ra
; RV32IMZBS-NEXT: lw ra, 516(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor s9, ra, s9
-; RV32IMZBS-NEXT: xor s3, s5, s3
+; RV32IMZBS-NEXT: xor s3, s4, s3
; RV32IMZBS-NEXT: xor t6, s0, t6
-; RV32IMZBS-NEXT: xor t3, t4, t3
-; RV32IMZBS-NEXT: xor t2, t2, s2
+; RV32IMZBS-NEXT: xor t1, t2, t1
+; RV32IMZBS-NEXT: xor t2, t4, s2
; RV32IMZBS-NEXT: lw t4, 684(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a6, a6, t4
; RV32IMZBS-NEXT: lw t4, 660(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a7, a7, t4
-; RV32IMZBS-NEXT: lw t4, 644(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t4, 636(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, t0, t4
-; RV32IMZBS-NEXT: lw t4, 620(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t4, 616(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t4, a3, t4
-; RV32IMZBS-NEXT: lw a3, 604(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a3, 600(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a4, a4, a3
; RV32IMZBS-NEXT: lw a3, 700(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a3, a5, a3
-; RV32IMZBS-NEXT: xor a5, t1, a0
+; RV32IMZBS-NEXT: xor a5, t3, a0
; RV32IMZBS-NEXT: lw a0, 564(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a1, a1, a0
; RV32IMZBS-NEXT: lw a0, 544(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a2, a2, a0
; RV32IMZBS-NEXT: lw a0, 524(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t1, s9, a0
+; RV32IMZBS-NEXT: xor t3, s9, a0
; RV32IMZBS-NEXT: xor s0, s3, s10
; RV32IMZBS-NEXT: xor t6, t6, s1
; RV32IMZBS-NEXT: lw a0, 708(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a0, t3, a0
+; RV32IMZBS-NEXT: xor a0, t1, a0
; RV32IMZBS-NEXT: lw s1, 704(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: srli t3, s1, 4
+; RV32IMZBS-NEXT: srli t1, s1, 4
; RV32IMZBS-NEXT: lw s3, 744(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: and s1, s1, s3
-; RV32IMZBS-NEXT: and t3, t3, s3
+; RV32IMZBS-NEXT: and t1, t1, s3
; RV32IMZBS-NEXT: slli s1, s1, 4
-; RV32IMZBS-NEXT: or t3, t3, s1
+; RV32IMZBS-NEXT: or t1, t1, s1
; RV32IMZBS-NEXT: lw s2, 712(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: srli s1, s2, 4
; RV32IMZBS-NEXT: and s2, s2, s3
@@ -11803,42 +11804,42 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: xor a7, a7, t2
; RV32IMZBS-NEXT: lw t2, 668(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, t0, t2
-; RV32IMZBS-NEXT: lw t2, 648(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t2, 640(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t2, t4, t2
-; RV32IMZBS-NEXT: lw t4, 616(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t4, 612(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a4, a4, t4
; RV32IMZBS-NEXT: xor a1, a5, a1
; RV32IMZBS-NEXT: lw a5, 572(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a2, a2, a5
; RV32IMZBS-NEXT: lw a5, 548(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a5, t1, a5
-; RV32IMZBS-NEXT: lw t1, 520(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor t1, s0, t1
-; RV32IMZBS-NEXT: xor t4, t6, s7
+; RV32IMZBS-NEXT: xor a5, t3, a5
+; RV32IMZBS-NEXT: lw t3, 520(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: xor t3, s0, t3
+; RV32IMZBS-NEXT: xor t4, t6, s5
; RV32IMZBS-NEXT: xor a6, a6, a7
; RV32IMZBS-NEXT: lw a7, 680(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a7, t0, a7
-; RV32IMZBS-NEXT: lw t0, 652(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t0, 648(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor t0, t2, t0
-; RV32IMZBS-NEXT: lw t2, 624(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t2, 620(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a4, a4, t2
; RV32IMZBS-NEXT: xor a1, a1, a2
; RV32IMZBS-NEXT: lw a2, 552(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a2, a5, a2
; RV32IMZBS-NEXT: lw a5, 528(sp) # 4-byte Folded Reload
-; RV32IMZBS-NEXT: xor a5, t1, a5
-; RV32IMZBS-NEXT: xor t1, t4, s8
+; RV32IMZBS-NEXT: xor a5, t3, a5
+; RV32IMZBS-NEXT: xor t2, t4, s8
; RV32IMZBS-NEXT: xor a6, a6, a7
-; RV32IMZBS-NEXT: lw a7, 656(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a7, 652(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a7, t0, a7
-; RV32IMZBS-NEXT: lw t0, 628(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw t0, 624(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a4, a4, t0
; RV32IMZBS-NEXT: xor a1, a1, a2
; RV32IMZBS-NEXT: lw a2, 532(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a2, a5, a2
-; RV32IMZBS-NEXT: xor a5, t1, s11
-; RV32IMZBS-NEXT: srli t0, t3, 2
-; RV32IMZBS-NEXT: and t1, t3, s6
+; RV32IMZBS-NEXT: xor a5, t2, s11
+; RV32IMZBS-NEXT: srli t0, t1, 2
+; RV32IMZBS-NEXT: and t1, t1, s6
; RV32IMZBS-NEXT: and t0, t0, s6
; RV32IMZBS-NEXT: slli t1, t1, 2
; RV32IMZBS-NEXT: or t0, t0, t1
@@ -11848,20 +11849,20 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: slli t2, t2, 2
; RV32IMZBS-NEXT: or t1, t1, t2
; RV32IMZBS-NEXT: xor a6, a6, a7
-; RV32IMZBS-NEXT: lw a7, 640(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a7, 632(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a4, a4, a7
; RV32IMZBS-NEXT: xor a1, a1, a2
; RV32IMZBS-NEXT: xor a2, a5, t5
; RV32IMZBS-NEXT: xor a4, a6, a4
; RV32IMZBS-NEXT: xor a1, a1, a2
; RV32IMZBS-NEXT: srli a2, t0, 1
-; RV32IMZBS-NEXT: and a5, t0, s4
+; RV32IMZBS-NEXT: and a5, t0, s7
; RV32IMZBS-NEXT: xor a3, a4, a3
; RV32IMZBS-NEXT: srli a4, t1, 1
-; RV32IMZBS-NEXT: and a6, t1, s4
-; RV32IMZBS-NEXT: and a2, a2, s4
+; RV32IMZBS-NEXT: and a6, t1, s7
+; RV32IMZBS-NEXT: and a2, a2, s7
; RV32IMZBS-NEXT: slli a5, a5, 1
-; RV32IMZBS-NEXT: and a4, a4, s4
+; RV32IMZBS-NEXT: and a4, a4, s7
; RV32IMZBS-NEXT: slli a6, a6, 1
; RV32IMZBS-NEXT: xor a7, a1, a0
; RV32IMZBS-NEXT: or a1, a2, a5
@@ -11911,17 +11912,17 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: srli a5, a4, 1
; RV32IMZBS-NEXT: and a3, a3, a6
; RV32IMZBS-NEXT: and a5, a5, a6
-; RV32IMZBS-NEXT: and a2, a2, s4
+; RV32IMZBS-NEXT: and a2, a2, s7
; RV32IMZBS-NEXT: slli a2, a2, 1
; RV32IMZBS-NEXT: or a2, a3, a2
-; RV32IMZBS-NEXT: and a3, a4, s4
+; RV32IMZBS-NEXT: and a3, a4, s7
; RV32IMZBS-NEXT: slli a3, a3, 1
; RV32IMZBS-NEXT: or a3, a5, a3
; RV32IMZBS-NEXT: srli a2, a2, 1
; RV32IMZBS-NEXT: srli a3, a3, 1
-; RV32IMZBS-NEXT: lw a4, 720(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a4, 724(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a2, a2, a4
-; RV32IMZBS-NEXT: lw a4, 716(sp) # 4-byte Folded Reload
+; RV32IMZBS-NEXT: lw a4, 720(sp) # 4-byte Folded Reload
; RV32IMZBS-NEXT: xor a3, a3, a4
; RV32IMZBS-NEXT: srli a4, a2, 8
; RV32IMZBS-NEXT: srli a5, a2, 24
@@ -11962,11 +11963,11 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32IMZBS-NEXT: or a2, a4, a2
; RV32IMZBS-NEXT: or a3, a5, a3
; RV32IMZBS-NEXT: srli a4, a2, 1
-; RV32IMZBS-NEXT: and a2, a2, s4
+; RV32IMZBS-NEXT: and a2, a2, s7
; RV32IMZBS-NEXT: srli a5, a3, 1
-; RV32IMZBS-NEXT: and a3, a3, s4
-; RV32IMZBS-NEXT: and a4, a4, s4
-; RV32IMZBS-NEXT: and a5, a5, s4
+; RV32IMZBS-NEXT: and a3, a3, s7
+; RV32IMZBS-NEXT: and a4, a4, s7
+; RV32IMZBS-NEXT: and a5, a5, s7
; RV32IMZBS-NEXT: slli a2, a2, 1
; RV32IMZBS-NEXT: or a2, a4, a2
; RV32IMZBS-NEXT: slli a3, a3, 1
@@ -11999,135 +12000,131 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
;
; RV64IMZBS-LABEL: commutative_clmulr_v2i64:
; RV64IMZBS: # %bb.0:
-; RV64IMZBS-NEXT: addi sp, sp, -1088
-; RV64IMZBS-NEXT: sd ra, 1080(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s0, 1072(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s1, 1064(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s2, 1056(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s3, 1048(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s4, 1040(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s5, 1032(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s6, 1024(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s7, 1016(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s8, 1008(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s9, 1000(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s10, 992(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd s11, 984(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd a5, 976(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sd a4, 968(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: mv t3, a3
-; RV64IMZBS-NEXT: mv t5, a0
-; RV64IMZBS-NEXT: srli a5, a2, 24
+; RV64IMZBS-NEXT: addi sp, sp, -1072
+; RV64IMZBS-NEXT: sd ra, 1064(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s0, 1056(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s1, 1048(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s2, 1040(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s3, 1032(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s4, 1024(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s5, 1016(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s6, 1008(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s7, 1000(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s8, 992(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s9, 984(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s10, 976(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s11, 968(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd a5, 960(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd a4, 952(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: mv t6, a3
+; RV64IMZBS-NEXT: mv a5, a0
+; RV64IMZBS-NEXT: srli a7, a2, 24
; RV64IMZBS-NEXT: lui s9, 4080
-; RV64IMZBS-NEXT: srli a7, a2, 8
-; RV64IMZBS-NEXT: li s8, 255
-; RV64IMZBS-NEXT: srli a4, a2, 40
-; RV64IMZBS-NEXT: lui a6, 16
-; RV64IMZBS-NEXT: srli t0, a2, 56
-; RV64IMZBS-NEXT: srliw t1, a2, 24
-; RV64IMZBS-NEXT: slli a0, a2, 56
-; RV64IMZBS-NEXT: sd a0, 920(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: lui s10, 61681
-; RV64IMZBS-NEXT: lui s1, 209715
+; RV64IMZBS-NEXT: srli t1, a2, 8
+; RV64IMZBS-NEXT: li t3, 255
+; RV64IMZBS-NEXT: srli a6, a2, 40
+; RV64IMZBS-NEXT: lui t0, 16
+; RV64IMZBS-NEXT: srli s5, a2, 56
+; RV64IMZBS-NEXT: srliw t4, a2, 24
+; RV64IMZBS-NEXT: slli a4, a2, 56
+; RV64IMZBS-NEXT: lui ra, 61681
+; RV64IMZBS-NEXT: lui s10, 209715
; RV64IMZBS-NEXT: lui s4, 349525
-; RV64IMZBS-NEXT: srli t2, t5, 24
-; RV64IMZBS-NEXT: srli t6, t5, 8
-; RV64IMZBS-NEXT: srli s5, t5, 40
-; RV64IMZBS-NEXT: srli s2, t5, 56
-; RV64IMZBS-NEXT: srliw s3, t5, 24
-; RV64IMZBS-NEXT: slli a0, t5, 56
-; RV64IMZBS-NEXT: sd a0, 912(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: srli t5, a0, 24
+; RV64IMZBS-NEXT: srli s3, a0, 8
+; RV64IMZBS-NEXT: srli t2, a0, 40
+; RV64IMZBS-NEXT: srli s2, a0, 56
+; RV64IMZBS-NEXT: srliw s1, a0, 24
+; RV64IMZBS-NEXT: slli a0, a0, 56
+; RV64IMZBS-NEXT: sd a0, 904(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: srli s7, a3, 24
; RV64IMZBS-NEXT: srli a3, a3, 8
-; RV64IMZBS-NEXT: srli s6, t3, 40
-; RV64IMZBS-NEXT: srli s11, t3, 56
-; RV64IMZBS-NEXT: and a5, a5, s9
-; RV64IMZBS-NEXT: slli s8, s8, 24
-; RV64IMZBS-NEXT: and a7, a7, s8
-; RV64IMZBS-NEXT: or a5, a7, a5
-; RV64IMZBS-NEXT: srliw s0, t3, 24
-; RV64IMZBS-NEXT: addi a0, a6, -256
-; RV64IMZBS-NEXT: and a4, a4, a0
-; RV64IMZBS-NEXT: or a6, a4, t0
-; RV64IMZBS-NEXT: and a4, a2, s9
-; RV64IMZBS-NEXT: slli t1, t1, 32
-; RV64IMZBS-NEXT: addi s10, s10, -241
-; RV64IMZBS-NEXT: addi ra, s1, 819
-; RV64IMZBS-NEXT: addi a7, s4, 1365
-; RV64IMZBS-NEXT: slli a4, a4, 24
-; RV64IMZBS-NEXT: or a4, a4, t1
-; RV64IMZBS-NEXT: slli t0, s10, 32
-; RV64IMZBS-NEXT: add s10, s10, t0
-; RV64IMZBS-NEXT: slli t0, ra, 32
-; RV64IMZBS-NEXT: add ra, ra, t0
-; RV64IMZBS-NEXT: slli t0, a7, 32
-; RV64IMZBS-NEXT: add t4, a7, t0
-; RV64IMZBS-NEXT: slli a7, t3, 56
-; RV64IMZBS-NEXT: and t0, t2, s9
-; RV64IMZBS-NEXT: and t1, t6, s8
-; RV64IMZBS-NEXT: or t0, t1, t0
-; RV64IMZBS-NEXT: srli t1, a1, 24
-; RV64IMZBS-NEXT: and t2, s5, a0
+; RV64IMZBS-NEXT: srli s6, t6, 40
+; RV64IMZBS-NEXT: srli s11, t6, 56
+; RV64IMZBS-NEXT: and a7, a7, s9
+; RV64IMZBS-NEXT: slli a0, t3, 24
+; RV64IMZBS-NEXT: and t1, t1, a0
+; RV64IMZBS-NEXT: or a7, t1, a7
+; RV64IMZBS-NEXT: srliw s0, t6, 24
+; RV64IMZBS-NEXT: addi s8, t0, -256
+; RV64IMZBS-NEXT: and a6, a6, s8
+; RV64IMZBS-NEXT: or t0, a6, s5
+; RV64IMZBS-NEXT: and a6, a2, s9
+; RV64IMZBS-NEXT: slli t4, t4, 32
+; RV64IMZBS-NEXT: addi t1, ra, -241
+; RV64IMZBS-NEXT: addi ra, s10, 819
+; RV64IMZBS-NEXT: addi t3, s4, 1365
+; RV64IMZBS-NEXT: slli a6, a6, 24
+; RV64IMZBS-NEXT: or a6, a6, t4
+; RV64IMZBS-NEXT: slli s10, t1, 32
+; RV64IMZBS-NEXT: add s10, t1, s10
+; RV64IMZBS-NEXT: slli t1, ra, 32
+; RV64IMZBS-NEXT: add ra, ra, t1
+; RV64IMZBS-NEXT: slli t1, t3, 32
+; RV64IMZBS-NEXT: add s5, t3, t1
+; RV64IMZBS-NEXT: slli t1, t6, 56
+; RV64IMZBS-NEXT: and t3, t5, s9
+; RV64IMZBS-NEXT: and t4, s3, a0
+; RV64IMZBS-NEXT: or t3, t4, t3
+; RV64IMZBS-NEXT: srli t4, a1, 24
+; RV64IMZBS-NEXT: and t2, t2, s8
; RV64IMZBS-NEXT: or t2, t2, s2
-; RV64IMZBS-NEXT: lui s5, 4080
-; RV64IMZBS-NEXT: and t6, t5, s5
-; RV64IMZBS-NEXT: slli s3, s3, 32
-; RV64IMZBS-NEXT: slli t6, t6, 24
-; RV64IMZBS-NEXT: or t6, t6, s3
+; RV64IMZBS-NEXT: and t5, a5, s9
+; RV64IMZBS-NEXT: slli s1, s1, 32
+; RV64IMZBS-NEXT: slli t5, t5, 24
+; RV64IMZBS-NEXT: or t5, t5, s1
; RV64IMZBS-NEXT: srli s1, a1, 8
-; RV64IMZBS-NEXT: and s2, s7, s5
-; RV64IMZBS-NEXT: sd s8, 960(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: and a3, a3, s8
+; RV64IMZBS-NEXT: and s2, s7, s9
+; RV64IMZBS-NEXT: sd a0, 944(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: and a3, a3, a0
; RV64IMZBS-NEXT: or a3, a3, s2
; RV64IMZBS-NEXT: srli s2, a1, 40
-; RV64IMZBS-NEXT: and s3, s6, a0
+; RV64IMZBS-NEXT: and s3, s6, s8
; RV64IMZBS-NEXT: or s3, s3, s11
-; RV64IMZBS-NEXT: and s4, t3, s5
+; RV64IMZBS-NEXT: and s4, t6, s9
; RV64IMZBS-NEXT: slli s0, s0, 32
; RV64IMZBS-NEXT: slli s4, s4, 24
; RV64IMZBS-NEXT: or s0, s4, s0
; RV64IMZBS-NEXT: srli s4, a1, 56
-; RV64IMZBS-NEXT: and t1, t1, s5
-; RV64IMZBS-NEXT: and s1, s1, s8
-; RV64IMZBS-NEXT: or t1, s1, t1
+; RV64IMZBS-NEXT: and t4, t4, s9
+; RV64IMZBS-NEXT: and s1, s1, a0
+; RV64IMZBS-NEXT: or t4, s1, t4
; RV64IMZBS-NEXT: srliw s1, a1, 24
-; RV64IMZBS-NEXT: and s2, s2, a0
+; RV64IMZBS-NEXT: and s2, s2, s8
; RV64IMZBS-NEXT: or s2, s2, s4
-; RV64IMZBS-NEXT: and s4, a1, s5
+; RV64IMZBS-NEXT: and s4, a1, s9
; RV64IMZBS-NEXT: slli s1, s1, 32
; RV64IMZBS-NEXT: slli s4, s4, 24
; RV64IMZBS-NEXT: or s1, s4, s1
; RV64IMZBS-NEXT: slli s4, a1, 56
-; RV64IMZBS-NEXT: mv s5, a0
-; RV64IMZBS-NEXT: sd a0, 936(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: and a2, a2, a0
-; RV64IMZBS-NEXT: and a0, t5, a0
-; RV64IMZBS-NEXT: and t3, t3, s5
-; RV64IMZBS-NEXT: and a1, a1, s5
+; RV64IMZBS-NEXT: sd s8, 920(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: and a2, a2, s8
+; RV64IMZBS-NEXT: and a0, a5, s8
+; RV64IMZBS-NEXT: and t6, t6, s8
+; RV64IMZBS-NEXT: and a1, a1, s8
; RV64IMZBS-NEXT: slli a2, a2, 40
; RV64IMZBS-NEXT: slli a0, a0, 40
-; RV64IMZBS-NEXT: slli t3, t3, 40
+; RV64IMZBS-NEXT: slli t6, t6, 40
; RV64IMZBS-NEXT: slli a1, a1, 40
-; RV64IMZBS-NEXT: or a5, a5, a6
-; RV64IMZBS-NEXT: ld a6, 920(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: or a2, a6, a2
-; RV64IMZBS-NEXT: or a6, t0, t2
-; RV64IMZBS-NEXT: ld t0, 912(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: or a0, t0, a0
+; RV64IMZBS-NEXT: or a7, a7, t0
+; RV64IMZBS-NEXT: or a2, a4, a2
+; RV64IMZBS-NEXT: or a4, t3, t2
+; RV64IMZBS-NEXT: ld a5, 904(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: or a0, a5, a0
; RV64IMZBS-NEXT: or a3, a3, s3
-; RV64IMZBS-NEXT: or a7, a7, t3
-; RV64IMZBS-NEXT: or t0, t1, s2
+; RV64IMZBS-NEXT: or a5, t1, t6
+; RV64IMZBS-NEXT: or t0, t4, s2
; RV64IMZBS-NEXT: or a1, s4, a1
-; RV64IMZBS-NEXT: or a2, a2, a4
-; RV64IMZBS-NEXT: or a0, a0, t6
-; RV64IMZBS-NEXT: or a4, a7, s0
+; RV64IMZBS-NEXT: or a2, a2, a6
+; RV64IMZBS-NEXT: or a0, a0, t5
+; RV64IMZBS-NEXT: or a5, a5, s0
; RV64IMZBS-NEXT: or a1, a1, s1
-; RV64IMZBS-NEXT: or a2, a2, a5
-; RV64IMZBS-NEXT: or a0, a0, a6
-; RV64IMZBS-NEXT: or a3, a4, a3
+; RV64IMZBS-NEXT: or a2, a2, a7
+; RV64IMZBS-NEXT: or a0, a0, a4
+; RV64IMZBS-NEXT: or a3, a5, a3
; RV64IMZBS-NEXT: or a1, a1, t0
; RV64IMZBS-NEXT: srli a4, a2, 4
-; RV64IMZBS-NEXT: sd s10, 952(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd s10, 936(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: and a2, a2, s10
; RV64IMZBS-NEXT: srli a5, a0, 4
; RV64IMZBS-NEXT: and a0, a0, s10
@@ -12148,7 +12145,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: or a3, a6, a3
; RV64IMZBS-NEXT: or a1, a7, a1
; RV64IMZBS-NEXT: srli a4, a2, 2
-; RV64IMZBS-NEXT: sd ra, 944(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sd ra, 928(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: and a2, a2, ra
; RV64IMZBS-NEXT: srli a5, a0, 2
; RV64IMZBS-NEXT: and a0, a0, ra
@@ -12167,692 +12164,688 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: or a2, a4, a2
; RV64IMZBS-NEXT: or a0, a5, a0
; RV64IMZBS-NEXT: or a3, a6, a3
-; RV64IMZBS-NEXT: or a1, a7, a1
-; RV64IMZBS-NEXT: srli a4, a2, 1
-; RV64IMZBS-NEXT: sd t4, 928(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: and a2, a2, t4
-; RV64IMZBS-NEXT: srli a5, a0, 1
-; RV64IMZBS-NEXT: and a0, a0, t4
-; RV64IMZBS-NEXT: srli a6, a3, 1
-; RV64IMZBS-NEXT: and a3, a3, t4
-; RV64IMZBS-NEXT: srli a7, a1, 1
-; RV64IMZBS-NEXT: and a1, a1, t4
-; RV64IMZBS-NEXT: and a4, a4, t4
-; RV64IMZBS-NEXT: slli a2, a2, 1
-; RV64IMZBS-NEXT: and a5, a5, t4
-; RV64IMZBS-NEXT: slli t0, a0, 1
-; RV64IMZBS-NEXT: and a6, a6, t4
-; RV64IMZBS-NEXT: slli a3, a3, 1
-; RV64IMZBS-NEXT: and a7, a7, t4
-; RV64IMZBS-NEXT: slli a0, a1, 1
-; RV64IMZBS-NEXT: or t4, a4, a2
-; RV64IMZBS-NEXT: or t5, a5, t0
-; RV64IMZBS-NEXT: srli a2, t0, 63
-; RV64IMZBS-NEXT: or t0, a6, a3
-; RV64IMZBS-NEXT: or s5, a7, a0
-; RV64IMZBS-NEXT: srli a0, a0, 63
-; RV64IMZBS-NEXT: slli a3, t4, 1
-; RV64IMZBS-NEXT: andi a4, t5, 2
-; RV64IMZBS-NEXT: slli a5, t4, 2
-; RV64IMZBS-NEXT: andi a6, t5, 4
-; RV64IMZBS-NEXT: slli a7, t4, 3
-; RV64IMZBS-NEXT: andi t1, t5, 8
-; RV64IMZBS-NEXT: slli t2, t4, 4
-; RV64IMZBS-NEXT: andi t3, t5, 16
-; RV64IMZBS-NEXT: slli t6, t4, 5
-; RV64IMZBS-NEXT: andi s0, t5, 32
-; RV64IMZBS-NEXT: slli s1, t4, 6
-; RV64IMZBS-NEXT: andi s2, t5, 64
-; RV64IMZBS-NEXT: slli s3, t4, 7
-; RV64IMZBS-NEXT: slli s4, t4, 63
-; RV64IMZBS-NEXT: seqz a2, a2
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: and a1, a2, s4
-; RV64IMZBS-NEXT: sd a1, 912(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: slli a2, t0, 63
-; RV64IMZBS-NEXT: seqz a0, a0
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: and a0, a0, a2
-; RV64IMZBS-NEXT: sd a0, 920(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: andi a0, t5, 128
-; RV64IMZBS-NEXT: seqz a2, a4
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 880(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: slli a2, t4, 8
-; RV64IMZBS-NEXT: seqz a3, a6
-; RV64IMZBS-NEXT: addi a3, a3, -1
-; RV64IMZBS-NEXT: and a3, a3, a5
-; RV64IMZBS-NEXT: sd a3, 864(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: andi a3, t5, 256
-; RV64IMZBS-NEXT: seqz a4, t1
-; RV64IMZBS-NEXT: addi a4, a4, -1
-; RV64IMZBS-NEXT: and a1, a4, a7
-; RV64IMZBS-NEXT: sd a1, 848(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: slli a4, t4, 9
-; RV64IMZBS-NEXT: seqz a5, t3
+; RV64IMZBS-NEXT: or a4, a7, a1
+; RV64IMZBS-NEXT: srli a6, a2, 1
+; RV64IMZBS-NEXT: sd s5, 912(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: and a5, a2, s5
+; RV64IMZBS-NEXT: srli a7, a0, 1
+; RV64IMZBS-NEXT: and a0, a0, s5
+; RV64IMZBS-NEXT: srli a1, a3, 1
+; RV64IMZBS-NEXT: and t0, a3, s5
+; RV64IMZBS-NEXT: srli t1, a4, 1
+; RV64IMZBS-NEXT: and t2, a4, s5
+; RV64IMZBS-NEXT: and a2, a6, s5
+; RV64IMZBS-NEXT: slli a3, a5, 1
+; RV64IMZBS-NEXT: and a4, a7, s5
+; RV64IMZBS-NEXT: slli a5, a0, 1
+; RV64IMZBS-NEXT: slli a0, a6, 63
+; RV64IMZBS-NEXT: and a6, a1, s5
+; RV64IMZBS-NEXT: slli a7, t0, 1
+; RV64IMZBS-NEXT: and t0, t1, s5
+; RV64IMZBS-NEXT: slli t1, t2, 1
+; RV64IMZBS-NEXT: slli a1, a1, 63
+; RV64IMZBS-NEXT: or s1, a2, a3
+; RV64IMZBS-NEXT: or a4, a4, a5
+; RV64IMZBS-NEXT: srli a5, a5, 63
+; RV64IMZBS-NEXT: or a3, a6, a7
+; RV64IMZBS-NEXT: or s5, t0, t1
+; RV64IMZBS-NEXT: srli a6, t1, 63
+; RV64IMZBS-NEXT: slli a7, s1, 1
+; RV64IMZBS-NEXT: andi t0, a4, 2
+; RV64IMZBS-NEXT: slli t1, s1, 2
+; RV64IMZBS-NEXT: andi t2, a4, 4
+; RV64IMZBS-NEXT: slli t3, s1, 3
+; RV64IMZBS-NEXT: andi t4, a4, 8
+; RV64IMZBS-NEXT: slli t5, s1, 4
+; RV64IMZBS-NEXT: andi t6, a4, 16
+; RV64IMZBS-NEXT: slli s0, s1, 5
+; RV64IMZBS-NEXT: andi s2, a4, 32
+; RV64IMZBS-NEXT: slli s3, s1, 6
+; RV64IMZBS-NEXT: andi s4, a4, 64
+; RV64IMZBS-NEXT: seqz a5, a5
+; RV64IMZBS-NEXT: addi a5, a5, -1
+; RV64IMZBS-NEXT: and a0, a5, a0
+; RV64IMZBS-NEXT: sd a0, 896(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: slli a0, s1, 7
+; RV64IMZBS-NEXT: seqz a5, a6
+; RV64IMZBS-NEXT: addi a5, a5, -1
+; RV64IMZBS-NEXT: and a1, a5, a1
+; RV64IMZBS-NEXT: sd a1, 904(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: andi a1, a4, 128
+; RV64IMZBS-NEXT: seqz a5, t0
; RV64IMZBS-NEXT: addi a5, a5, -1
-; RV64IMZBS-NEXT: and t2, a5, t2
-; RV64IMZBS-NEXT: andi a5, t5, 512
-; RV64IMZBS-NEXT: seqz a6, s0
+; RV64IMZBS-NEXT: and a2, a5, a7
+; RV64IMZBS-NEXT: sd a2, 864(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: slli a5, s1, 8
+; RV64IMZBS-NEXT: seqz a6, t2
; RV64IMZBS-NEXT: addi a6, a6, -1
-; RV64IMZBS-NEXT: and t3, a6, t6
-; RV64IMZBS-NEXT: slli a6, t4, 10
-; RV64IMZBS-NEXT: seqz a7, s2
+; RV64IMZBS-NEXT: and a2, a6, t1
+; RV64IMZBS-NEXT: sd a2, 848(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: andi a6, a4, 256
+; RV64IMZBS-NEXT: seqz a7, t4
; RV64IMZBS-NEXT: addi a7, a7, -1
-; RV64IMZBS-NEXT: and a1, a7, s1
-; RV64IMZBS-NEXT: sd a1, 888(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: andi a7, t5, 1024
-; RV64IMZBS-NEXT: seqz a0, a0
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: and t6, a0, s3
-; RV64IMZBS-NEXT: slli a0, t4, 11
-; RV64IMZBS-NEXT: seqz a3, a3
-; RV64IMZBS-NEXT: addi a3, a3, -1
-; RV64IMZBS-NEXT: and s2, a3, a2
-; RV64IMZBS-NEXT: not a2, t5
-; RV64IMZBS-NEXT: seqz a3, a5
-; RV64IMZBS-NEXT: addi a3, a3, -1
-; RV64IMZBS-NEXT: and a3, a3, a4
-; RV64IMZBS-NEXT: sd a3, 840(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: slli a3, t4, 12
-; RV64IMZBS-NEXT: seqz a4, a7
-; RV64IMZBS-NEXT: addi a4, a4, -1
-; RV64IMZBS-NEXT: and a1, a4, a6
-; RV64IMZBS-NEXT: sd a1, 904(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a4, a2, 11
-; RV64IMZBS-NEXT: addi a4, a4, -1
-; RV64IMZBS-NEXT: and a6, a4, a0
-; RV64IMZBS-NEXT: bexti a0, a2, 12
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 776(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 13
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 13
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 816(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 14
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 14
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 856(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 15
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 15
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 896(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 16
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 16
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 736(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 17
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 17
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 728(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 18
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 18
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 768(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 19
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 19
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 800(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 20
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 20
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 832(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 21
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 21
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 872(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 22
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 22
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 680(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 23
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 23
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 664(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 24
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 24
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 712(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 25
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 25
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 752(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 26
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 26
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 792(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 27
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 27
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 808(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 28
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 28
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 824(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 29
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 29
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 608(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 30
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 30
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 600(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sraiw a0, t5, 31
-; RV64IMZBS-NEXT: seqz a0, a0
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 31
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 648(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 32
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 32
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 672(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 33
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 33
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 704(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 34
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 34
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 744(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 35
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 35
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 760(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 36
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 36
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 784(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 37
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 37
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 552(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 38
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 38
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 544(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 39
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 39
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 568(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 40
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 40
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 592(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 41
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 41
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 640(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 42
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 42
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 656(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 43
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 43
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 688(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 44
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 44
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 696(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 45
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 45
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 720(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 46
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 46
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 496(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 47
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 47
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 488(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 48
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 48
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 520(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 49
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 49
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 536(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 50
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 50
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 560(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 51
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 51
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 576(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 52
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 52
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 584(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 53
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 53
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 616(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 54
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 54
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 624(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 55
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 55
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 632(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 56
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 56
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 464(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 57
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 57
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 456(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 58
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 58
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 472(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 59
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 59
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 480(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 60
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 60
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 504(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a0, a2, 61
-; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a3, t4, 61
-; RV64IMZBS-NEXT: and a0, a0, a3
-; RV64IMZBS-NEXT: sd a0, 512(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: andi a0, t5, 1
-; RV64IMZBS-NEXT: seqz a0, a0
+; RV64IMZBS-NEXT: and t3, a7, t3
+; RV64IMZBS-NEXT: slli a7, s1, 9
+; RV64IMZBS-NEXT: seqz t0, t6
+; RV64IMZBS-NEXT: addi t0, t0, -1
+; RV64IMZBS-NEXT: and t4, t0, t5
+; RV64IMZBS-NEXT: andi t0, a4, 512
+; RV64IMZBS-NEXT: seqz t1, s2
+; RV64IMZBS-NEXT: addi t1, t1, -1
+; RV64IMZBS-NEXT: and t5, t1, s0
+; RV64IMZBS-NEXT: slli t1, s1, 10
+; RV64IMZBS-NEXT: seqz t2, s4
+; RV64IMZBS-NEXT: addi t2, t2, -1
+; RV64IMZBS-NEXT: and a2, t2, s3
+; RV64IMZBS-NEXT: sd a2, 872(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: andi t2, a4, 1024
+; RV64IMZBS-NEXT: seqz a1, a1
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: and t6, a1, a0
+; RV64IMZBS-NEXT: slli a1, s1, 11
+; RV64IMZBS-NEXT: seqz a0, a6
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: and t5, a0, t4
-; RV64IMZBS-NEXT: slli t4, t4, 62
-; RV64IMZBS-NEXT: bexti a0, a2, 62
+; RV64IMZBS-NEXT: and s2, a0, a5
+; RV64IMZBS-NEXT: not a0, a4
+; RV64IMZBS-NEXT: seqz a5, t0
+; RV64IMZBS-NEXT: addi a5, a5, -1
+; RV64IMZBS-NEXT: and a2, a5, a7
+; RV64IMZBS-NEXT: sd a2, 832(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: slli a5, s1, 12
+; RV64IMZBS-NEXT: seqz a6, t2
+; RV64IMZBS-NEXT: addi a6, a6, -1
+; RV64IMZBS-NEXT: and a2, a6, t1
+; RV64IMZBS-NEXT: sd a2, 888(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a6, a0, 11
+; RV64IMZBS-NEXT: addi a6, a6, -1
+; RV64IMZBS-NEXT: and a7, a6, a1
+; RV64IMZBS-NEXT: bexti a1, a0, 12
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: and t1, a1, a5
+; RV64IMZBS-NEXT: bexti a1, a0, 13
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 13
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 808(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 14
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 14
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 840(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 15
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 15
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 880(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 16
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 16
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 736(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 17
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 17
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 728(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 18
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 18
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 768(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 19
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 19
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 792(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 20
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 20
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 824(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 21
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 21
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 856(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 22
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 22
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 680(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 23
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 23
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 664(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 24
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 24
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 712(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 25
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 25
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 752(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 26
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 26
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 784(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 27
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 27
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 800(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 28
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 28
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 816(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 29
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 29
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 608(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 30
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 30
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 600(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sraiw a1, a4, 31
+; RV64IMZBS-NEXT: seqz a1, a1
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 31
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 648(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 32
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 32
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 672(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 33
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 33
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 704(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 34
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 34
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 744(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 35
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 35
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 760(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 36
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 36
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 776(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 37
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 37
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 552(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 38
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 38
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 544(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 39
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 39
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 568(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 40
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 40
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 592(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 41
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 41
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 640(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 42
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 42
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 656(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 43
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 43
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 688(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 44
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 44
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 696(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 45
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 45
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 720(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 46
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 46
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 496(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 47
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 47
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 488(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 48
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 48
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 520(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 49
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 49
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 536(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 50
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 50
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 560(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 51
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 51
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 576(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 52
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 52
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 584(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 53
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 53
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 616(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 54
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 54
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 624(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 55
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 55
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 632(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 56
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 56
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 464(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 57
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 57
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 456(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 58
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 58
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 472(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 59
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 59
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 480(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 60
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 60
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 504(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 61
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, s1, 61
+; RV64IMZBS-NEXT: and a1, a1, a5
+; RV64IMZBS-NEXT: sd a1, 512(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: andi a4, a4, 1
+; RV64IMZBS-NEXT: seqz a1, a4
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: and s3, a1, s1
+; RV64IMZBS-NEXT: slli s1, s1, 62
+; RV64IMZBS-NEXT: bexti a0, a0, 62
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: and a0, a0, t4
+; RV64IMZBS-NEXT: and a0, a0, s1
; RV64IMZBS-NEXT: sd a0, 528(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: andi a0, s5, 2
; RV64IMZBS-NEXT: seqz a0, a0
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a2, t0, 1
-; RV64IMZBS-NEXT: and a0, a0, a2
+; RV64IMZBS-NEXT: slli a1, a3, 1
+; RV64IMZBS-NEXT: and a0, a0, a1
; RV64IMZBS-NEXT: sd a0, 448(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: andi a0, s5, 4
; RV64IMZBS-NEXT: seqz a0, a0
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a2, t0, 2
-; RV64IMZBS-NEXT: and a0, a0, a2
+; RV64IMZBS-NEXT: slli a1, a3, 2
+; RV64IMZBS-NEXT: and a0, a0, a1
; RV64IMZBS-NEXT: sd a0, 432(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: andi a0, s5, 8
; RV64IMZBS-NEXT: seqz a0, a0
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a2, t0, 3
-; RV64IMZBS-NEXT: and a0, a0, a2
+; RV64IMZBS-NEXT: slli a1, a3, 3
+; RV64IMZBS-NEXT: and a0, a0, a1
; RV64IMZBS-NEXT: sd a0, 408(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: andi a0, s5, 16
; RV64IMZBS-NEXT: seqz a0, a0
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a2, t0, 4
-; RV64IMZBS-NEXT: and a0, a0, a2
+; RV64IMZBS-NEXT: slli a1, a3, 4
+; RV64IMZBS-NEXT: and a0, a0, a1
; RV64IMZBS-NEXT: sd a0, 400(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: andi a0, s5, 32
; RV64IMZBS-NEXT: seqz a0, a0
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a2, t0, 5
-; RV64IMZBS-NEXT: and a0, a0, a2
+; RV64IMZBS-NEXT: slli a1, a3, 5
+; RV64IMZBS-NEXT: and a0, a0, a1
; RV64IMZBS-NEXT: sd a0, 376(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: andi a0, s5, 64
; RV64IMZBS-NEXT: seqz a0, a0
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a2, t0, 6
-; RV64IMZBS-NEXT: and a0, a0, a2
+; RV64IMZBS-NEXT: slli a1, a3, 6
+; RV64IMZBS-NEXT: and a0, a0, a1
; RV64IMZBS-NEXT: sd a0, 440(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: andi a0, s5, 128
; RV64IMZBS-NEXT: seqz a0, a0
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a2, t0, 7
-; RV64IMZBS-NEXT: and a0, a0, a2
+; RV64IMZBS-NEXT: slli a1, a3, 7
+; RV64IMZBS-NEXT: and a0, a0, a1
; RV64IMZBS-NEXT: sd a0, 360(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: andi a0, s5, 256
; RV64IMZBS-NEXT: seqz a0, a0
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a2, t0, 8
-; RV64IMZBS-NEXT: and a0, a0, a2
+; RV64IMZBS-NEXT: slli a1, a3, 8
+; RV64IMZBS-NEXT: and a0, a0, a1
; RV64IMZBS-NEXT: sd a0, 344(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: andi a0, s5, 512
; RV64IMZBS-NEXT: seqz a0, a0
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a2, t0, 9
-; RV64IMZBS-NEXT: and a0, a0, a2
+; RV64IMZBS-NEXT: slli a1, a3, 9
+; RV64IMZBS-NEXT: and a0, a0, a1
; RV64IMZBS-NEXT: sd a0, 392(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: andi a0, s5, 1024
; RV64IMZBS-NEXT: seqz a0, a0
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: slli a2, t0, 10
-; RV64IMZBS-NEXT: and a0, a0, a2
+; RV64IMZBS-NEXT: slli a1, a3, 10
+; RV64IMZBS-NEXT: and a0, a0, a1
; RV64IMZBS-NEXT: sd a0, 424(sp) # 8-byte Folded Spill
; RV64IMZBS-NEXT: not a0, s5
-; RV64IMZBS-NEXT: bexti a2, a0, 11
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 11
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 304(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 12
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 12
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 296(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 13
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 13
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 328(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 14
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 14
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 368(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 15
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 15
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 416(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 16
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 16
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 248(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 17
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 17
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 232(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 18
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 18
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 280(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 19
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 19
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 320(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 20
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 20
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 352(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 21
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 21
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 384(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 22
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 22
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 192(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 23
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 23
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 168(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 24
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 24
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 224(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 25
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 25
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 256(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 26
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 26
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 288(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 27
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 27
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 312(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 28
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 28
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 336(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 29
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 29
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 136(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 30
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 30
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 112(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: sraiw a2, s5, 31
-; RV64IMZBS-NEXT: seqz a2, a2
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 31
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 152(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 32
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 32
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 184(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 33
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 33
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 216(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 34
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 34
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 240(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 35
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 35
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 264(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 36
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 36
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 272(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 37
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 37
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 56(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 38
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 38
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 48(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 39
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 39
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 72(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 40
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 40
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 96(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 41
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 41
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 144(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 42
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 42
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 160(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 43
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 43
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 176(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 44
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 44
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 200(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 45
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 45
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 208(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 46
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 46
-; RV64IMZBS-NEXT: and s11, a2, a3
-; RV64IMZBS-NEXT: bexti a2, a0, 47
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a4, t0, 47
-; RV64IMZBS-NEXT: and s9, a2, a4
-; RV64IMZBS-NEXT: bexti a2, a0, 48
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 48
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 24(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 49
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 49
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 40(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 50
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 50
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 64(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 51
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli s0, t0, 51
-; RV64IMZBS-NEXT: and a2, a2, s0
-; RV64IMZBS-NEXT: sd a2, 80(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 52
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli s1, t0, 52
-; RV64IMZBS-NEXT: and a2, a2, s1
-; RV64IMZBS-NEXT: sd a2, 88(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 53
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 53
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 104(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 54
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 54
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 128(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 55
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 55
-; RV64IMZBS-NEXT: and a2, a2, a3
-; RV64IMZBS-NEXT: sd a2, 120(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: bexti a2, a0, 56
-; RV64IMZBS-NEXT: addi a2, a2, -1
-; RV64IMZBS-NEXT: slli a3, t0, 56
-; RV64IMZBS-NEXT: and s6, a2, a3
-; RV64IMZBS-NEXT: bexti a3, a0, 57
-; RV64IMZBS-NEXT: addi a3, a3, -1
-; RV64IMZBS-NEXT: slli a4, t0, 57
-; RV64IMZBS-NEXT: and s4, a3, a4
-; RV64IMZBS-NEXT: bexti a4, a0, 58
+; RV64IMZBS-NEXT: bexti a1, a0, 11
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 11
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 304(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 12
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 12
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 296(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 13
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 13
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 328(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 14
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 14
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 368(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 15
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 15
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 416(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 16
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 16
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 248(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 17
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 17
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 232(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 18
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 18
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 280(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 19
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 19
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 320(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 20
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 20
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 352(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 21
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 21
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 384(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 22
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 22
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 192(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 23
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 23
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 168(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 24
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 24
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 224(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 25
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 25
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 256(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 26
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 26
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 288(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 27
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 27
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 312(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 28
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 28
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 336(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 29
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 29
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 136(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 30
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 30
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 112(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: sraiw a1, s5, 31
+; RV64IMZBS-NEXT: seqz a1, a1
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 31
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 152(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 32
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 32
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 184(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 33
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 33
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 216(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 34
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 34
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 240(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 35
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 35
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 264(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 36
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 36
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 272(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 37
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 37
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 56(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 38
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 38
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 48(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 39
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 39
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 72(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 40
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 40
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 96(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 41
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 41
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 144(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 42
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 42
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 160(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 43
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 43
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 176(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 44
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 44
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 200(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 45
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 45
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 208(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 46
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 46
+; RV64IMZBS-NEXT: and s11, a1, a4
+; RV64IMZBS-NEXT: bexti a1, a0, 47
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a5, a3, 47
+; RV64IMZBS-NEXT: and s9, a1, a5
+; RV64IMZBS-NEXT: bexti a1, a0, 48
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 48
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 24(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 49
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 49
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 40(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 50
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 50
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 64(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 51
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli s0, a3, 51
+; RV64IMZBS-NEXT: and a1, a1, s0
+; RV64IMZBS-NEXT: sd a1, 80(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 52
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli s1, a3, 52
+; RV64IMZBS-NEXT: and a1, a1, s1
+; RV64IMZBS-NEXT: sd a1, 88(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 53
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 53
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 104(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 54
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 54
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 128(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 55
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 55
+; RV64IMZBS-NEXT: and a1, a1, a4
+; RV64IMZBS-NEXT: sd a1, 120(sp) # 8-byte Folded Spill
+; RV64IMZBS-NEXT: bexti a1, a0, 56
+; RV64IMZBS-NEXT: addi a1, a1, -1
+; RV64IMZBS-NEXT: slli a4, a3, 56
+; RV64IMZBS-NEXT: and s6, a1, a4
+; RV64IMZBS-NEXT: bexti a4, a0, 57
; RV64IMZBS-NEXT: addi a4, a4, -1
-; RV64IMZBS-NEXT: slli a5, t0, 58
-; RV64IMZBS-NEXT: and s7, a4, a5
-; RV64IMZBS-NEXT: bexti a5, a0, 59
+; RV64IMZBS-NEXT: slli a5, a3, 57
+; RV64IMZBS-NEXT: and s4, a4, a5
+; RV64IMZBS-NEXT: bexti a5, a0, 58
; RV64IMZBS-NEXT: addi a5, a5, -1
-; RV64IMZBS-NEXT: slli a7, t0, 59
-; RV64IMZBS-NEXT: and s8, a5, a7
-; RV64IMZBS-NEXT: bexti a7, a0, 60
-; RV64IMZBS-NEXT: addi a7, a7, -1
-; RV64IMZBS-NEXT: slli t1, t0, 60
-; RV64IMZBS-NEXT: and s10, a7, t1
-; RV64IMZBS-NEXT: bexti t1, a0, 61
-; RV64IMZBS-NEXT: addi t1, t1, -1
-; RV64IMZBS-NEXT: slli a1, t0, 61
-; RV64IMZBS-NEXT: and a1, t1, a1
+; RV64IMZBS-NEXT: slli a6, a3, 58
+; RV64IMZBS-NEXT: and s7, a5, a6
+; RV64IMZBS-NEXT: bexti a6, a0, 59
+; RV64IMZBS-NEXT: addi a6, a6, -1
+; RV64IMZBS-NEXT: slli t0, a3, 59
+; RV64IMZBS-NEXT: and s8, a6, t0
+; RV64IMZBS-NEXT: bexti t0, a0, 60
+; RV64IMZBS-NEXT: addi t0, t0, -1
+; RV64IMZBS-NEXT: slli t2, a3, 60
+; RV64IMZBS-NEXT: and s10, t0, t2
+; RV64IMZBS-NEXT: bexti t2, a0, 61
+; RV64IMZBS-NEXT: addi t2, t2, -1
+; RV64IMZBS-NEXT: slli a2, a3, 61
+; RV64IMZBS-NEXT: and a1, t2, a2
; RV64IMZBS-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: andi a1, s5, 1
-; RV64IMZBS-NEXT: seqz a1, a1
-; RV64IMZBS-NEXT: addi a1, a1, -1
-; RV64IMZBS-NEXT: and a1, a1, t0
-; RV64IMZBS-NEXT: slli t0, t0, 62
+; RV64IMZBS-NEXT: andi a2, s5, 1
+; RV64IMZBS-NEXT: seqz a2, a2
+; RV64IMZBS-NEXT: addi a2, a2, -1
+; RV64IMZBS-NEXT: and a2, a2, a3
+; RV64IMZBS-NEXT: slli a3, a3, 62
; RV64IMZBS-NEXT: bexti a0, a0, 62
; RV64IMZBS-NEXT: addi a0, a0, -1
-; RV64IMZBS-NEXT: and a0, a0, t0
+; RV64IMZBS-NEXT: and a0, a0, a3
; RV64IMZBS-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IMZBS-NEXT: ld a0, 880(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor s3, t5, a0
; RV64IMZBS-NEXT: ld a0, 864(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld a2, 848(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor s5, a0, a2
-; RV64IMZBS-NEXT: xor t2, t2, t3
-; RV64IMZBS-NEXT: xor t4, t6, s2
-; RV64IMZBS-NEXT: ld a0, 776(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor t5, a6, a0
+; RV64IMZBS-NEXT: xor s3, s3, a0
+; RV64IMZBS-NEXT: ld a0, 848(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor s5, a0, t3
+; RV64IMZBS-NEXT: xor t2, t4, t5
+; RV64IMZBS-NEXT: xor t3, t6, s2
+; RV64IMZBS-NEXT: xor t5, a7, t1
; RV64IMZBS-NEXT: ld a0, 736(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld a2, 728(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor t6, a0, a2
+; RV64IMZBS-NEXT: ld a1, 728(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor t6, a0, a1
; RV64IMZBS-NEXT: ld a0, 680(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: ld s0, 664(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor s0, a0, s0
@@ -12860,16 +12853,16 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: ld s1, 600(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor s1, a0, s1
; RV64IMZBS-NEXT: ld a0, 552(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld a2, 544(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor s2, a0, a2
+; RV64IMZBS-NEXT: ld a1, 544(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor s2, a0, a1
; RV64IMZBS-NEXT: ld a0, 496(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld a2, 488(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor t0, a0, a2
+; RV64IMZBS-NEXT: ld a1, 488(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor t0, a0, a1
; RV64IMZBS-NEXT: ld a0, 464(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld a2, 456(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor t1, a0, a2
+; RV64IMZBS-NEXT: ld a1, 456(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor t1, a0, a1
; RV64IMZBS-NEXT: ld a0, 448(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor t3, a1, a0
+; RV64IMZBS-NEXT: xor t4, a2, a0
; RV64IMZBS-NEXT: ld a0, 432(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: ld a1, 408(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor a0, a0, a1
@@ -12897,11 +12890,11 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: xor s9, s11, s9
; RV64IMZBS-NEXT: xor s4, s6, s4
; RV64IMZBS-NEXT: xor s3, s3, s5
-; RV64IMZBS-NEXT: ld s5, 888(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s5, 872(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t2, t2, s5
-; RV64IMZBS-NEXT: ld s5, 840(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor t4, t4, s5
-; RV64IMZBS-NEXT: ld s5, 816(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s5, 832(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor t3, t3, s5
+; RV64IMZBS-NEXT: ld s5, 808(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t5, t5, s5
; RV64IMZBS-NEXT: ld s5, 768(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t6, t6, s5
@@ -12915,30 +12908,30 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: xor t0, t0, s5
; RV64IMZBS-NEXT: ld s5, 472(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t1, t1, s5
-; RV64IMZBS-NEXT: xor a0, t3, a0
-; RV64IMZBS-NEXT: ld t3, 440(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor a1, a1, t3
-; RV64IMZBS-NEXT: ld t3, 392(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor a2, a2, t3
-; RV64IMZBS-NEXT: ld t3, 328(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor a3, a3, t3
-; RV64IMZBS-NEXT: ld t3, 280(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor a4, a4, t3
-; RV64IMZBS-NEXT: ld t3, 224(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor a5, a5, t3
-; RV64IMZBS-NEXT: ld t3, 152(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor a6, a6, t3
-; RV64IMZBS-NEXT: ld t3, 72(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor a7, a7, t3
-; RV64IMZBS-NEXT: ld t3, 24(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor t3, s9, t3
+; RV64IMZBS-NEXT: xor a0, t4, a0
+; RV64IMZBS-NEXT: ld t4, 440(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor a1, a1, t4
+; RV64IMZBS-NEXT: ld t4, 392(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor a2, a2, t4
+; RV64IMZBS-NEXT: ld t4, 328(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor a3, a3, t4
+; RV64IMZBS-NEXT: ld t4, 280(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor a4, a4, t4
+; RV64IMZBS-NEXT: ld t4, 224(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor a5, a5, t4
+; RV64IMZBS-NEXT: ld t4, 152(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor a6, a6, t4
+; RV64IMZBS-NEXT: ld t4, 72(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor a7, a7, t4
+; RV64IMZBS-NEXT: ld t4, 24(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor t4, s9, t4
; RV64IMZBS-NEXT: xor s4, s4, s7
; RV64IMZBS-NEXT: xor t2, s3, t2
-; RV64IMZBS-NEXT: ld s3, 904(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor t4, t4, s3
-; RV64IMZBS-NEXT: ld s3, 856(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s3, 888(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor t3, t3, s3
+; RV64IMZBS-NEXT: ld s3, 840(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t5, t5, s3
-; RV64IMZBS-NEXT: ld s3, 800(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s3, 792(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t6, t6, s3
; RV64IMZBS-NEXT: ld s3, 752(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor s0, s0, s3
@@ -12964,14 +12957,14 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: ld a6, 96(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor a6, a7, a6
; RV64IMZBS-NEXT: ld a7, 40(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor a7, t3, a7
-; RV64IMZBS-NEXT: xor t3, s4, s8
-; RV64IMZBS-NEXT: xor t2, t2, t4
-; RV64IMZBS-NEXT: ld t4, 896(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: xor t4, t5, t4
-; RV64IMZBS-NEXT: ld t5, 832(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor a7, t4, a7
+; RV64IMZBS-NEXT: xor t4, s4, s8
+; RV64IMZBS-NEXT: xor t2, t2, t3
+; RV64IMZBS-NEXT: ld t3, 880(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor t3, t5, t3
+; RV64IMZBS-NEXT: ld t5, 824(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t5, t6, t5
-; RV64IMZBS-NEXT: ld t6, 792(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld t6, 784(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t6, s0, t6
; RV64IMZBS-NEXT: ld s0, 704(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor s0, s1, s0
@@ -12994,11 +12987,11 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: xor a5, a6, a5
; RV64IMZBS-NEXT: ld a6, 64(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor a6, a7, a6
-; RV64IMZBS-NEXT: xor a7, t3, s10
-; RV64IMZBS-NEXT: xor t2, t2, t4
-; RV64IMZBS-NEXT: ld t3, 872(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: xor a7, t4, s10
+; RV64IMZBS-NEXT: xor t2, t2, t3
+; RV64IMZBS-NEXT: ld t3, 856(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t3, t5, t3
-; RV64IMZBS-NEXT: ld t4, 808(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld t4, 800(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t4, t6, t4
; RV64IMZBS-NEXT: ld t5, 744(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t5, s0, t5
@@ -13022,7 +13015,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: ld a6, 16(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor a6, a7, a6
; RV64IMZBS-NEXT: xor a7, t2, t3
-; RV64IMZBS-NEXT: ld t2, 824(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld t2, 816(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t2, t4, t2
; RV64IMZBS-NEXT: ld t3, 760(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t3, t5, t3
@@ -13044,13 +13037,13 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: ld a5, 32(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor a5, a6, a5
; RV64IMZBS-NEXT: xor a6, a7, t2
-; RV64IMZBS-NEXT: ld a7, 784(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld a7, 776(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor a7, t3, a7
; RV64IMZBS-NEXT: ld t2, 696(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t2, t4, t2
; RV64IMZBS-NEXT: ld t3, 616(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t0, t0, t3
-; RV64IMZBS-NEXT: ld t3, 912(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld t3, 896(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor t1, t1, t3
; RV64IMZBS-NEXT: xor a0, a0, a1
; RV64IMZBS-NEXT: ld a1, 272(sp) # 8-byte Folded Reload
@@ -13059,7 +13052,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: xor a2, a3, a2
; RV64IMZBS-NEXT: ld a3, 104(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor a3, a4, a3
-; RV64IMZBS-NEXT: ld a4, 920(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld a4, 904(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: xor a4, a5, a4
; RV64IMZBS-NEXT: xor a5, a6, a7
; RV64IMZBS-NEXT: ld a6, 720(sp) # 8-byte Folded Reload
@@ -13086,48 +13079,48 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: srli a4, a1, 24
; RV64IMZBS-NEXT: srli a5, a1, 8
; RV64IMZBS-NEXT: srliw a6, a1, 24
-; RV64IMZBS-NEXT: lui t3, 4080
-; RV64IMZBS-NEXT: and a7, a1, t3
+; RV64IMZBS-NEXT: lui t4, 4080
+; RV64IMZBS-NEXT: and a7, a1, t4
; RV64IMZBS-NEXT: slli t0, a1, 56
-; RV64IMZBS-NEXT: ld t4, 936(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: and a1, a1, t4
-; RV64IMZBS-NEXT: srli t1, a0, 8
-; RV64IMZBS-NEXT: ld t2, 960(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: and a5, a5, t2
-; RV64IMZBS-NEXT: and t1, t1, t2
-; RV64IMZBS-NEXT: srli t2, a0, 40
-; RV64IMZBS-NEXT: and a2, a2, t4
+; RV64IMZBS-NEXT: ld t5, 920(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: and a1, a1, t5
+; RV64IMZBS-NEXT: srli t1, a0, 40
+; RV64IMZBS-NEXT: srli t2, a0, 8
+; RV64IMZBS-NEXT: ld t3, 944(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: and a5, a5, t3
+; RV64IMZBS-NEXT: and t2, t2, t3
+; RV64IMZBS-NEXT: srli t3, a0, 56
+; RV64IMZBS-NEXT: and a2, a2, t5
; RV64IMZBS-NEXT: or a2, a2, a3
-; RV64IMZBS-NEXT: srli a3, a0, 56
-; RV64IMZBS-NEXT: and a4, a4, t3
+; RV64IMZBS-NEXT: srli a3, a0, 24
+; RV64IMZBS-NEXT: and a4, a4, t4
; RV64IMZBS-NEXT: or a4, a5, a4
-; RV64IMZBS-NEXT: srli a5, a0, 24
-; RV64IMZBS-NEXT: slli a6, a6, 32
-; RV64IMZBS-NEXT: slli a7, a7, 24
-; RV64IMZBS-NEXT: or a6, a7, a6
-; RV64IMZBS-NEXT: srliw a7, a0, 24
-; RV64IMZBS-NEXT: and a5, a5, t3
-; RV64IMZBS-NEXT: and t3, a0, t3
-; RV64IMZBS-NEXT: and t2, t2, t4
+; RV64IMZBS-NEXT: srliw a5, a0, 24
+; RV64IMZBS-NEXT: and a3, a3, t4
; RV64IMZBS-NEXT: and t4, a0, t4
+; RV64IMZBS-NEXT: and t1, t1, t5
+; RV64IMZBS-NEXT: and t5, a0, t5
; RV64IMZBS-NEXT: slli a0, a0, 56
+; RV64IMZBS-NEXT: slli a6, a6, 32
+; RV64IMZBS-NEXT: slli a7, a7, 24
; RV64IMZBS-NEXT: slli a1, a1, 40
-; RV64IMZBS-NEXT: slli a7, a7, 32
-; RV64IMZBS-NEXT: slli t3, t3, 24
-; RV64IMZBS-NEXT: slli t4, t4, 40
+; RV64IMZBS-NEXT: slli a5, a5, 32
+; RV64IMZBS-NEXT: slli t4, t4, 24
+; RV64IMZBS-NEXT: slli t5, t5, 40
+; RV64IMZBS-NEXT: or a6, a7, a6
; RV64IMZBS-NEXT: or a1, t0, a1
+; RV64IMZBS-NEXT: or a7, t1, t3
; RV64IMZBS-NEXT: or a3, t2, a3
-; RV64IMZBS-NEXT: or a5, t1, a5
-; RV64IMZBS-NEXT: or a7, t3, a7
-; RV64IMZBS-NEXT: or a0, a0, t4
+; RV64IMZBS-NEXT: or a5, t4, a5
+; RV64IMZBS-NEXT: or a0, a0, t5
; RV64IMZBS-NEXT: or a2, a4, a2
; RV64IMZBS-NEXT: or a1, a1, a6
-; RV64IMZBS-NEXT: or a3, a5, a3
-; RV64IMZBS-NEXT: or a0, a0, a7
+; RV64IMZBS-NEXT: or a3, a3, a7
+; RV64IMZBS-NEXT: or a0, a0, a5
; RV64IMZBS-NEXT: or a1, a1, a2
; RV64IMZBS-NEXT: or a0, a0, a3
; RV64IMZBS-NEXT: srli a2, a1, 4
-; RV64IMZBS-NEXT: ld a4, 952(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld a4, 936(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: and a1, a1, a4
; RV64IMZBS-NEXT: srli a3, a0, 4
; RV64IMZBS-NEXT: and a0, a0, a4
@@ -13138,7 +13131,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: or a1, a2, a1
; RV64IMZBS-NEXT: or a0, a3, a0
; RV64IMZBS-NEXT: srli a2, a1, 2
-; RV64IMZBS-NEXT: ld a4, 944(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld a4, 928(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: and a1, a1, a4
; RV64IMZBS-NEXT: srli a3, a0, 2
; RV64IMZBS-NEXT: and a0, a0, a4
@@ -13149,7 +13142,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: or a1, a2, a1
; RV64IMZBS-NEXT: or a0, a3, a0
; RV64IMZBS-NEXT: srli a2, a1, 1
-; RV64IMZBS-NEXT: ld a4, 928(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld a4, 912(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: and a1, a1, a4
; RV64IMZBS-NEXT: srli a3, a0, 1
; RV64IMZBS-NEXT: and a0, a0, a4
@@ -13159,26 +13152,26 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64IMZBS-NEXT: slli a0, a0, 1
; RV64IMZBS-NEXT: or a1, a2, a1
; RV64IMZBS-NEXT: or a0, a3, a0
-; RV64IMZBS-NEXT: ld a2, 968(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld a2, 952(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: sd a1, 0(a2)
; RV64IMZBS-NEXT: sd a0, 8(a2)
-; RV64IMZBS-NEXT: ld a2, 976(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld a2, 960(sp) # 8-byte Folded Reload
; RV64IMZBS-NEXT: sd a1, 0(a2)
; RV64IMZBS-NEXT: sd a0, 8(a2)
-; RV64IMZBS-NEXT: ld ra, 1080(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s0, 1072(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s1, 1064(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s2, 1056(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s3, 1048(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s4, 1040(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s5, 1032(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s6, 1024(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s7, 1016(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s8, 1008(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s9, 1000(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s10, 992(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: ld s11, 984(sp) # 8-byte Folded Reload
-; RV64IMZBS-NEXT: addi sp, sp, 1088
+; RV64IMZBS-NEXT: ld ra, 1064(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s0, 1056(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s1, 1048(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s2, 1040(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s3, 1032(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s4, 1024(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s5, 1016(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s6, 1008(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s7, 1000(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s8, 992(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s9, 984(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s10, 976(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: ld s11, 968(sp) # 8-byte Folded Reload
+; RV64IMZBS-NEXT: addi sp, sp, 1072
; RV64IMZBS-NEXT: ret
%x.ext = zext <2 x i64> %x to <2 x i128>
%y.ext = zext <2 x i64> %y to <2 x i128>
diff --git a/llvm/test/CodeGen/RISCV/idiv_large.ll b/llvm/test/CodeGen/RISCV/idiv_large.ll
index 2d67c05ac63f6..ce5c6998ba6ef 100644
--- a/llvm/test/CodeGen/RISCV/idiv_large.ll
+++ b/llvm/test/CodeGen/RISCV/idiv_large.ll
@@ -145,7 +145,7 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: # %bb.7: # %_udiv-special-cases
; RV32-NEXT: mv t3, s1
; RV32-NEXT: .LBB1_8: # %_udiv-special-cases
-; RV32-NEXT: snez s4, a1
+; RV32-NEXT: snez s3, a1
; RV32-NEXT: srli a1, a2, 1
; RV32-NEXT: slli t2, s2, 31
; RV32-NEXT: slli t4, a2, 31
@@ -180,7 +180,7 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: slli t4, t2, 16
; RV32-NEXT: add t2, t2, t4
; RV32-NEXT: srli t2, t2, 24
-; RV32-NEXT: addi s3, t2, 32
+; RV32-NEXT: addi s4, t2, 32
; RV32-NEXT: j .LBB1_11
; RV32-NEXT: .LBB1_10:
; RV32-NEXT: srli t2, a1, 1
@@ -208,7 +208,7 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: add t2, t2, t4
; RV32-NEXT: slli t4, t2, 16
; RV32-NEXT: add t2, t2, t4
-; RV32-NEXT: srli s3, t2, 24
+; RV32-NEXT: srli s4, t2, 24
; RV32-NEXT: .LBB1_11: # %_udiv-special-cases
; RV32-NEXT: andi t4, s2, 1
; RV32-NEXT: andi t1, t1, 1
@@ -216,7 +216,7 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: or s2, a5, a2
; RV32-NEXT: sltu s0, s1, s0
; RV32-NEXT: slli s1, a5, 31
-; RV32-NEXT: addi s4, s4, -1
+; RV32-NEXT: addi s3, s3, -1
; RV32-NEXT: beqz s1, .LBB1_13
; RV32-NEXT: # %bb.12:
; RV32-NEXT: srli t5, s1, 1
@@ -246,41 +246,40 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: add a6, a6, a7
; RV32-NEXT: srli t5, a6, 24
; RV32-NEXT: .LBB1_13: # %_udiv-special-cases
-; RV32-NEXT: or t0, t2, t1
+; RV32-NEXT: or a7, t2, t1
; RV32-NEXT: or a6, s2, t4
-; RV32-NEXT: and a7, s4, s0
+; RV32-NEXT: and t0, s3, s0
; RV32-NEXT: or t6, t6, a1
; RV32-NEXT: addi s0, t5, 64
; RV32-NEXT: bnez t6, .LBB1_15
; RV32-NEXT: # %bb.14: # %_udiv-special-cases
-; RV32-NEXT: mv s3, s0
+; RV32-NEXT: mv s4, s0
; RV32-NEXT: .LBB1_15: # %_udiv-special-cases
-; RV32-NEXT: seqz a1, t0
-; RV32-NEXT: sltu t0, s0, t5
+; RV32-NEXT: seqz a1, a7
+; RV32-NEXT: sltu a7, s0, t5
; RV32-NEXT: snez t5, t6
; RV32-NEXT: addi t5, t5, -1
-; RV32-NEXT: and t0, t5, t0
-; RV32-NEXT: sltu t5, t3, s3
-; RV32-NEXT: seqz a6, a6
-; RV32-NEXT: mv t6, t5
-; RV32-NEXT: beq a7, t0, .LBB1_17
+; RV32-NEXT: and t5, t5, a7
+; RV32-NEXT: sltu t6, t3, s4
+; RV32-NEXT: seqz a7, a6
+; RV32-NEXT: mv a6, t6
+; RV32-NEXT: beq t0, t5, .LBB1_17
; RV32-NEXT: # %bb.16: # %_udiv-special-cases
-; RV32-NEXT: sltu t6, a7, t0
+; RV32-NEXT: sltu a6, t0, t5
; RV32-NEXT: .LBB1_17: # %_udiv-special-cases
-; RV32-NEXT: or a1, a1, a6
-; RV32-NEXT: andi a6, t6, 1
-; RV32-NEXT: sub a7, a7, t0
-; RV32-NEXT: sub t0, a7, t5
-; RV32-NEXT: sub a7, t3, s3
+; RV32-NEXT: or a1, a1, a7
+; RV32-NEXT: sub a7, t3, s4
+; RV32-NEXT: sub t0, t0, t5
+; RV32-NEXT: sub t0, t0, t6
; RV32-NEXT: beqz a6, .LBB1_19
; RV32-NEXT: # %bb.18: # %_udiv-special-cases
; RV32-NEXT: mv t3, a6
; RV32-NEXT: j .LBB1_20
; RV32-NEXT: .LBB1_19:
-; RV32-NEXT: sltiu t3, a7, 65
-; RV32-NEXT: xori t3, t3, 1
-; RV32-NEXT: snez t5, t0
-; RV32-NEXT: or t3, t3, t5
+; RV32-NEXT: snez t3, t0
+; RV32-NEXT: sltiu t5, a7, 65
+; RV32-NEXT: xori t5, t5, 1
+; RV32-NEXT: or t3, t5, t3
; RV32-NEXT: .LBB1_20: # %_udiv-special-cases
; RV32-NEXT: or t6, a1, t3
; RV32-NEXT: addi t5, t6, -1
@@ -745,24 +744,21 @@ define i128 @udiv_i128(i128 %x, i128 %y) nounwind {
; RV32-NEXT: mv a0, a1
; RV32-NEXT: .LBB2_16: # %_udiv-special-cases
; RV32-NEXT: seqz a1, t4
-; RV32-NEXT: seqz t4, s1
-; RV32-NEXT: sltu t6, t5, a0
-; RV32-NEXT: sub s1, t2, t3
-; RV32-NEXT: mv s0, t6
+; RV32-NEXT: sltu t4, t5, a0
+; RV32-NEXT: seqz t6, s1
+; RV32-NEXT: mv s0, t4
; RV32-NEXT: beq t2, t3, .LBB2_18
; RV32-NEXT: # %bb.17: # %_udiv-special-cases
; RV32-NEXT: sltu s0, t2, t3
; RV32-NEXT: .LBB2_18: # %_udiv-special-cases
-; RV32-NEXT: sub t2, s1, t6
-; RV32-NEXT: or a1, a1, t4
+; RV32-NEXT: or a1, a1, t6
; RV32-NEXT: neg t6, s0
-; RV32-NEXT: seqz s0, s0
-; RV32-NEXT: addi s0, s0, -1
-; RV32-NEXT: or t4, t6, s0
+; RV32-NEXT: sub t2, t2, t3
+; RV32-NEXT: sub t2, t2, t4
; RV32-NEXT: sub t3, t5, a0
-; RV32-NEXT: beqz t4, .LBB2_20
+; RV32-NEXT: beqz t6, .LBB2_20
; RV32-NEXT: # %bb.19: # %_udiv-special-cases
-; RV32-NEXT: snez a0, t4
+; RV32-NEXT: snez a0, t6
; RV32-NEXT: j .LBB2_21
; RV32-NEXT: .LBB2_20:
; RV32-NEXT: snez a0, t2
@@ -770,19 +766,19 @@ define i128 @udiv_i128(i128 %x, i128 %y) nounwind {
; RV32-NEXT: xori t4, t4, 1
; RV32-NEXT: or a0, t4, a0
; RV32-NEXT: .LBB2_21: # %_udiv-special-cases
-; RV32-NEXT: or s1, a1, a0
-; RV32-NEXT: addi t5, s1, -1
+; RV32-NEXT: or s0, a1, a0
+; RV32-NEXT: addi t5, s0, -1
; RV32-NEXT: and a1, t5, a7
; RV32-NEXT: and t4, t5, t0
; RV32-NEXT: and a0, t5, a6
; RV32-NEXT: and t5, t5, t1
-; RV32-NEXT: bnez s1, .LBB2_32
+; RV32-NEXT: bnez s0, .LBB2_32
; RV32-NEXT: # %bb.22: # %_udiv-special-cases
-; RV32-NEXT: xori s1, t3, 127
-; RV32-NEXT: or s1, s1, t6
-; RV32-NEXT: or s2, t2, s0
-; RV32-NEXT: or s1, s1, s2
-; RV32-NEXT: beqz s1, .LBB2_32
+; RV32-NEXT: xori s0, t3, 127
+; RV32-NEXT: or s0, s0, t6
+; RV32-NEXT: or s1, t2, t6
+; RV32-NEXT: or s0, s0, s1
+; RV32-NEXT: beqz s0, .LBB2_32
; RV32-NEXT: # %bb.23: # %udiv-bb1
; RV32-NEXT: sw a3, 8(sp) # 4-byte Folded Spill
; RV32-NEXT: addi a1, t3, 1
@@ -808,26 +804,26 @@ define i128 @udiv_i128(i128 %x, i128 %y) nounwind {
; RV32-NEXT: sub a3, a3, a0
; RV32-NEXT: add t4, t6, t4
; RV32-NEXT: lw a0, 0(a3)
-; RV32-NEXT: lw s1, 4(a3)
-; RV32-NEXT: lw s3, 8(a3)
+; RV32-NEXT: lw s0, 4(a3)
+; RV32-NEXT: lw s1, 8(a3)
; RV32-NEXT: lw a3, 12(a3)
; RV32-NEXT: sltu t5, t4, t6
-; RV32-NEXT: or t6, a1, t4
-; RV32-NEXT: add t5, s0, t5
-; RV32-NEXT: or s0, t2, t5
-; RV32-NEXT: or t6, t6, s0
-; RV32-NEXT: srli s0, s3, 1
+; RV32-NEXT: or s2, a1, t4
+; RV32-NEXT: add t5, t6, t5
+; RV32-NEXT: or t6, t2, t5
+; RV32-NEXT: or t6, s2, t6
; RV32-NEXT: srli s2, s1, 1
+; RV32-NEXT: srli s3, s0, 1
; RV32-NEXT: srli s4, a0, 1
-; RV32-NEXT: srl s0, s0, a4
-; RV32-NEXT: srl s5, s2, a4
+; RV32-NEXT: srl s2, s2, a4
+; RV32-NEXT: srl s3, s3, a4
; RV32-NEXT: srl a4, s4, a4
; RV32-NEXT: not t3, t3
; RV32-NEXT: sll a3, a3, t3
-; RV32-NEXT: or s2, a3, s0
-; RV32-NEXT: sll a3, s3, t3
-; RV32-NEXT: sll s1, s1, t3
-; RV32-NEXT: or a3, a3, s5
+; RV32-NEXT: or s2, a3, s2
+; RV32-NEXT: sll a3, s1, t3
+; RV32-NEXT: sll s1, s0, t3
+; RV32-NEXT: or a3, a3, s3
; RV32-NEXT: or s1, s1, a4
; RV32-NEXT: sll t3, a0, t3
; RV32-NEXT: beqz t6, .LBB2_31
@@ -1033,10 +1029,10 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: sw s10, 192(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s11, 188(sp) # 4-byte Folded Spill
; RV32-NEXT: mv s6, a0
-; RV32-NEXT: lw t1, 16(a2)
+; RV32-NEXT: lw a6, 16(a2)
; RV32-NEXT: lw a4, 0(a2)
; RV32-NEXT: lw a5, 4(a2)
-; RV32-NEXT: lw a6, 8(a2)
+; RV32-NEXT: lw a7, 8(a2)
; RV32-NEXT: lw a0, 12(a2)
; RV32-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
; RV32-NEXT: lui a0, 349525
@@ -1045,19 +1041,19 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: addi t5, a0, 1365
; RV32-NEXT: addi t4, a2, 819
; RV32-NEXT: addi t3, a3, -241
-; RV32-NEXT: sw a6, 32(sp) # 4-byte Folded Spill
-; RV32-NEXT: slli a0, a6, 31
+; RV32-NEXT: sw a7, 32(sp) # 4-byte Folded Spill
+; RV32-NEXT: slli a0, a7, 31
; RV32-NEXT: srli a2, a5, 1
; RV32-NEXT: sw a5, 24(sp) # 4-byte Folded Spill
; RV32-NEXT: slli a3, a5, 31
-; RV32-NEXT: or a6, a2, a0
+; RV32-NEXT: or a7, a2, a0
; RV32-NEXT: sw a4, 36(sp) # 4-byte Folded Spill
; RV32-NEXT: srli a0, a4, 1
-; RV32-NEXT: or a7, a0, a3
-; RV32-NEXT: bnez a6, .LBB3_2
+; RV32-NEXT: or t0, a0, a3
+; RV32-NEXT: bnez a7, .LBB3_2
; RV32-NEXT: # %bb.1: # %_udiv-special-cases
-; RV32-NEXT: srli a0, a7, 1
-; RV32-NEXT: or a0, a7, a0
+; RV32-NEXT: srli a0, t0, 1
+; RV32-NEXT: or a0, t0, a0
; RV32-NEXT: srli a2, a0, 2
; RV32-NEXT: or a0, a0, a2
; RV32-NEXT: srli a2, a0, 4
@@ -1085,8 +1081,8 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: addi a4, a0, 32
; RV32-NEXT: j .LBB3_3
; RV32-NEXT: .LBB3_2:
-; RV32-NEXT: srli a0, a6, 1
-; RV32-NEXT: or a0, a6, a0
+; RV32-NEXT: srli a0, a7, 1
+; RV32-NEXT: or a0, a7, a0
; RV32-NEXT: srli a2, a0, 2
; RV32-NEXT: or a0, a0, a2
; RV32-NEXT: srli a2, a0, 4
@@ -1114,10 +1110,10 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: .LBB3_3: # %_udiv-special-cases
; RV32-NEXT: lw a5, 28(sp) # 4-byte Folded Reload
; RV32-NEXT: srli a0, a5, 1
-; RV32-NEXT: slli a3, t1, 31
+; RV32-NEXT: slli a3, a6, 31
; RV32-NEXT: slli a5, a5, 31
; RV32-NEXT: lw a2, 32(sp) # 4-byte Folded Reload
-; RV32-NEXT: srli t0, a2, 1
+; RV32-NEXT: srli t1, a2, 1
; RV32-NEXT: lw a2, 36(sp) # 4-byte Folded Reload
; RV32-NEXT: slli a2, a2, 31
; RV32-NEXT: li s1, 64
@@ -1154,15 +1150,15 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: srli t6, t2, 24
; RV32-NEXT: .LBB3_6: # %_udiv-special-cases
; RV32-NEXT: or s0, a3, a0
-; RV32-NEXT: or a5, t0, a5
+; RV32-NEXT: or a5, t1, a5
; RV32-NEXT: bnez a2, .LBB3_8
; RV32-NEXT: # %bb.7: # %_udiv-special-cases
; RV32-NEXT: li t6, 128
; RV32-NEXT: .LBB3_8: # %_udiv-special-cases
; RV32-NEXT: or t2, a5, s0
-; RV32-NEXT: addi t0, a4, 64
-; RV32-NEXT: or a0, a6, s0
-; RV32-NEXT: or a3, a7, a5
+; RV32-NEXT: addi t1, a4, 64
+; RV32-NEXT: or a0, a7, s0
+; RV32-NEXT: or a3, t0, a5
; RV32-NEXT: or a3, a3, a0
; RV32-NEXT: addi a0, t6, 128
; RV32-NEXT: bnez a3, .LBB3_11
@@ -1200,7 +1196,7 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: j .LBB3_14
; RV32-NEXT: .LBB3_11:
; RV32-NEXT: snez a2, t2
-; RV32-NEXT: sltu a4, t0, a4
+; RV32-NEXT: sltu a4, t1, a4
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and t6, a2, a4
; RV32-NEXT: bnez s0, .LBB3_10
@@ -1234,22 +1230,22 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: addi s0, a2, 32
; RV32-NEXT: bnez t2, .LBB3_14
; RV32-NEXT: .LBB3_13: # %_udiv-special-cases
-; RV32-NEXT: mv s0, t0
+; RV32-NEXT: mv s0, t1
; RV32-NEXT: .LBB3_14: # %_udiv-special-cases
-; RV32-NEXT: lw a7, 0(a1)
-; RV32-NEXT: lw t0, 4(a1)
-; RV32-NEXT: lw a6, 8(a1)
+; RV32-NEXT: lw t0, 0(a1)
+; RV32-NEXT: lw t1, 4(a1)
+; RV32-NEXT: lw a7, 8(a1)
; RV32-NEXT: bnez a3, .LBB3_16
; RV32-NEXT: # %bb.15: # %_udiv-special-cases
; RV32-NEXT: mv s0, a0
; RV32-NEXT: .LBB3_16: # %_udiv-special-cases
; RV32-NEXT: lw t2, 12(a1)
; RV32-NEXT: lw a1, 16(a1)
-; RV32-NEXT: slli a0, a6, 31
-; RV32-NEXT: srli a2, t0, 1
+; RV32-NEXT: slli a0, a7, 31
+; RV32-NEXT: srli a2, t1, 1
; RV32-NEXT: or s2, a2, a0
-; RV32-NEXT: slli a0, t0, 31
-; RV32-NEXT: srli a2, a7, 1
+; RV32-NEXT: slli a0, t1, 31
+; RV32-NEXT: srli a2, t0, 1
; RV32-NEXT: or s3, a2, a0
; RV32-NEXT: bnez s2, .LBB3_18
; RV32-NEXT: # %bb.17: # %_udiv-special-cases
@@ -1312,8 +1308,8 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: srli a2, t2, 1
; RV32-NEXT: slli a3, a1, 31
; RV32-NEXT: slli a4, t2, 31
-; RV32-NEXT: slli a5, a7, 31
-; RV32-NEXT: srli s4, a6, 1
+; RV32-NEXT: slli a5, t0, 31
+; RV32-NEXT: srli s4, a7, 1
; RV32-NEXT: beqz a5, .LBB3_21
; RV32-NEXT: # %bb.20:
; RV32-NEXT: srli s1, a5, 1
@@ -1385,7 +1381,7 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: add a0, a0, a2
; RV32-NEXT: slli a2, a0, 16
; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: srli a4, a0, 24
+; RV32-NEXT: srli a2, a0, 24
; RV32-NEXT: j .LBB3_28
; RV32-NEXT: .LBB3_26:
; RV32-NEXT: snez a5, s4
@@ -1420,54 +1416,53 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: slli a2, a0, 16
; RV32-NEXT: add a0, a0, a2
; RV32-NEXT: srli a0, a0, 24
-; RV32-NEXT: addi a4, a0, 32
+; RV32-NEXT: addi a2, a0, 32
; RV32-NEXT: .LBB3_28: # %_udiv-special-cases
; RV32-NEXT: andi s11, a1, 1
-; RV32-NEXT: andi a0, t1, 1
+; RV32-NEXT: andi a0, a6, 1
; RV32-NEXT: lw a1, 36(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw a2, 32(sp) # 4-byte Folded Reload
-; RV32-NEXT: or s9, a1, a2
-; RV32-NEXT: or a1, a7, a6
+; RV32-NEXT: lw a4, 32(sp) # 4-byte Folded Reload
+; RV32-NEXT: or s9, a1, a4
+; RV32-NEXT: or a1, t0, a7
; RV32-NEXT: bnez s4, .LBB3_30
; RV32-NEXT: # %bb.29: # %_udiv-special-cases
-; RV32-NEXT: mv a4, a3
+; RV32-NEXT: mv a2, a3
; RV32-NEXT: .LBB3_30: # %_udiv-special-cases
-; RV32-NEXT: lw a2, 24(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw a3, 28(sp) # 4-byte Folded Reload
-; RV32-NEXT: or s10, a2, a3
+; RV32-NEXT: lw a3, 24(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a4, 28(sp) # 4-byte Folded Reload
+; RV32-NEXT: or s10, a3, a4
; RV32-NEXT: or a3, s9, a0
-; RV32-NEXT: or a2, t0, t2
+; RV32-NEXT: or a4, t1, t2
; RV32-NEXT: or a5, a1, s11
; RV32-NEXT: bnez s3, .LBB3_32
; RV32-NEXT: # %bb.31: # %_udiv-special-cases
-; RV32-NEXT: mv a4, s2
+; RV32-NEXT: mv a2, s2
; RV32-NEXT: .LBB3_32: # %_udiv-special-cases
; RV32-NEXT: or a1, a3, s10
-; RV32-NEXT: sltu a3, s0, a4
-; RV32-NEXT: or a2, a5, a2
-; RV32-NEXT: mv a5, a3
+; RV32-NEXT: or a3, a5, a4
+; RV32-NEXT: sltu a4, s0, a2
+; RV32-NEXT: sub a5, t6, s1
+; RV32-NEXT: mv t4, a4
; RV32-NEXT: beq t6, s1, .LBB3_34
; RV32-NEXT: # %bb.33: # %_udiv-special-cases
-; RV32-NEXT: sltu a5, t6, s1
+; RV32-NEXT: sltu t4, t6, s1
; RV32-NEXT: .LBB3_34: # %_udiv-special-cases
+; RV32-NEXT: sub a6, a5, a4
; RV32-NEXT: seqz a1, a1
-; RV32-NEXT: seqz a2, a2
-; RV32-NEXT: andi t4, a5, 1
-; RV32-NEXT: sub t1, t6, s1
-; RV32-NEXT: neg t3, a5
-; RV32-NEXT: snez a5, a5
-; RV32-NEXT: sub t1, t1, a3
-; RV32-NEXT: neg t5, a5
-; RV32-NEXT: or a3, t3, t5
-; RV32-NEXT: sub t6, s0, a4
-; RV32-NEXT: beqz a3, .LBB3_36
+; RV32-NEXT: neg t3, t4
+; RV32-NEXT: snez a4, t4
+; RV32-NEXT: neg t5, a4
+; RV32-NEXT: sub t6, s0, a2
+; RV32-NEXT: or a4, t3, t5
+; RV32-NEXT: seqz a2, a3
+; RV32-NEXT: beqz a4, .LBB3_36
; RV32-NEXT: # %bb.35: # %_udiv-special-cases
-; RV32-NEXT: snez a3, a3
+; RV32-NEXT: snez a3, a4
; RV32-NEXT: or a1, a1, a2
; RV32-NEXT: bnez t4, .LBB3_37
; RV32-NEXT: j .LBB3_38
; RV32-NEXT: .LBB3_36:
-; RV32-NEXT: snez a3, t1
+; RV32-NEXT: snez a3, a6
; RV32-NEXT: sltiu a4, t6, 129
; RV32-NEXT: xori a4, a4, 1
; RV32-NEXT: or a3, a4, a3
@@ -1480,12 +1475,12 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: addi a4, a5, -1
; RV32-NEXT: and s0, s11, a4
; RV32-NEXT: and a3, a4, t2
-; RV32-NEXT: and a2, a4, a6
-; RV32-NEXT: and a1, a4, t0
-; RV32-NEXT: and a4, a4, a7
+; RV32-NEXT: and a2, a4, a7
+; RV32-NEXT: and a1, a4, t1
+; RV32-NEXT: and a4, a4, t0
; RV32-NEXT: bnez a5, .LBB3_55
; RV32-NEXT: # %bb.39: # %_udiv-special-cases
-; RV32-NEXT: or a5, t1, t5
+; RV32-NEXT: or a5, a6, t5
; RV32-NEXT: xori s1, t6, 128
; RV32-NEXT: or s1, s1, t4
; RV32-NEXT: or s1, s1, t3
@@ -1502,9 +1497,9 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: sw zero, 124(sp)
; RV32-NEXT: sw zero, 128(sp)
; RV32-NEXT: sw zero, 132(sp)
-; RV32-NEXT: sw a7, 152(sp)
-; RV32-NEXT: sw t0, 156(sp)
-; RV32-NEXT: sw a6, 160(sp)
+; RV32-NEXT: sw t0, 152(sp)
+; RV32-NEXT: sw t1, 156(sp)
+; RV32-NEXT: sw a7, 160(sp)
; RV32-NEXT: sw t2, 164(sp)
; RV32-NEXT: sw s11, 168(sp)
; RV32-NEXT: li a2, 128
@@ -1512,10 +1507,10 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: neg ra, t6
; RV32-NEXT: seqz a4, a1
; RV32-NEXT: sub a2, a2, t6
-; RV32-NEXT: add t1, t1, a4
+; RV32-NEXT: add a6, a6, a4
; RV32-NEXT: andi a4, a2, 31
; RV32-NEXT: srli a2, a2, 3
-; RV32-NEXT: or a5, a1, t1
+; RV32-NEXT: or a5, a1, a6
; RV32-NEXT: xori s8, a4, 31
; RV32-NEXT: andi a2, a2, 28
; RV32-NEXT: seqz t6, a5
@@ -1528,7 +1523,7 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: sltu t3, t6, t3
; RV32-NEXT: or s0, a1, t6
; RV32-NEXT: add t3, t5, t3
-; RV32-NEXT: or t5, t1, t3
+; RV32-NEXT: or t5, a6, t3
; RV32-NEXT: or t5, s0, t5
; RV32-NEXT: srli s0, s1, 1
; RV32-NEXT: seqz s2, t5
@@ -1568,23 +1563,23 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: sw zero, 76(sp)
; RV32-NEXT: sw zero, 80(sp)
; RV32-NEXT: sw zero, 84(sp)
-; RV32-NEXT: sw a7, 56(sp)
-; RV32-NEXT: sw t0, 60(sp)
-; RV32-NEXT: sw a6, 64(sp)
+; RV32-NEXT: sw t0, 56(sp)
+; RV32-NEXT: sw t1, 60(sp)
+; RV32-NEXT: sw a7, 64(sp)
; RV32-NEXT: sw t2, 68(sp)
; RV32-NEXT: srli a2, a1, 3
; RV32-NEXT: addi a5, sp, 56
-; RV32-NEXT: andi a6, a1, 31
-; RV32-NEXT: or a7, s9, s10
+; RV32-NEXT: andi a7, a1, 31
+; RV32-NEXT: or t0, s9, s10
; RV32-NEXT: srl a4, a4, s8
; RV32-NEXT: andi a2, a2, 28
-; RV32-NEXT: xori a6, a6, 31
-; RV32-NEXT: snez a7, a7
+; RV32-NEXT: xori a7, a7, 31
+; RV32-NEXT: snez t0, t0
; RV32-NEXT: add a2, a5, a2
-; RV32-NEXT: add a0, a0, a7
+; RV32-NEXT: add a0, a0, t0
; RV32-NEXT: lw a5, 16(a2)
-; RV32-NEXT: lw a7, 0(a2)
-; RV32-NEXT: lw t0, 4(a2)
+; RV32-NEXT: lw t0, 0(a2)
+; RV32-NEXT: lw t1, 4(a2)
; RV32-NEXT: lw t2, 8(a2)
; RV32-NEXT: lw a2, 12(a2)
; RV32-NEXT: sll a3, a3, ra
@@ -1592,11 +1587,11 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: slli a5, a5, 1
; RV32-NEXT: slli a4, a2, 1
; RV32-NEXT: slli t4, t2, 1
-; RV32-NEXT: slli s4, t0, 1
-; RV32-NEXT: sll a5, a5, a6
-; RV32-NEXT: sll a4, a4, a6
-; RV32-NEXT: sll t4, t4, a6
-; RV32-NEXT: sll a6, s4, a6
+; RV32-NEXT: slli s4, t1, 1
+; RV32-NEXT: sll a5, a5, a7
+; RV32-NEXT: sll a4, a4, a7
+; RV32-NEXT: sll t4, t4, a7
+; RV32-NEXT: sll a7, s4, a7
; RV32-NEXT: srl a2, a2, a1
; RV32-NEXT: or s9, a2, a5
; RV32-NEXT: lw s4, 36(sp) # 4-byte Folded Reload
@@ -1607,11 +1602,11 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: or a4, s4, a5
; RV32-NEXT: sub a5, a5, a2
; RV32-NEXT: seqz a2, a4
-; RV32-NEXT: srl a4, t0, a1
+; RV32-NEXT: srl a4, t1, a1
; RV32-NEXT: or s11, a4, t4
; RV32-NEXT: lw a4, 32(sp) # 4-byte Folded Reload
-; RV32-NEXT: sub t0, a4, a2
-; RV32-NEXT: sw t0, 40(sp) # 4-byte Folded Spill
+; RV32-NEXT: sub t1, a4, a2
+; RV32-NEXT: sw t1, 40(sp) # 4-byte Folded Spill
; RV32-NEXT: sltu a2, a4, a2
; RV32-NEXT: not a0, a0
; RV32-NEXT: lw a4, 28(sp) # 4-byte Folded Reload
@@ -1619,8 +1614,8 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: andi a0, a0, 1
; RV32-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
; RV32-NEXT: andi a0, a3, 1
-; RV32-NEXT: srl a2, a7, a1
-; RV32-NEXT: or s8, a2, a6
+; RV32-NEXT: srl a2, t0, a1
+; RV32-NEXT: or s8, a2, a7
; RV32-NEXT: addi s4, s4, -1
; RV32-NEXT: sw s4, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: sw a5, 20(sp) # 4-byte Folded Spill
@@ -1629,15 +1624,15 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: # in Loop: Header=BB3_43 Depth=1
; RV32-NEXT: lw a2, 32(sp) # 4-byte Folded Reload
; RV32-NEXT: and t2, a0, a2
-; RV32-NEXT: xor a2, a3, a6
-; RV32-NEXT: xor a7, ra, t2
-; RV32-NEXT: or a2, a7, a2
+; RV32-NEXT: xor a2, a3, a7
+; RV32-NEXT: xor t0, ra, t2
+; RV32-NEXT: or a2, t0, a2
; RV32-NEXT: srli a2, s2, 31
-; RV32-NEXT: sltu a7, ra, t2
+; RV32-NEXT: sltu t0, ra, t2
; RV32-NEXT: sub t2, ra, t2
; RV32-NEXT: slli ra, s0, 1
-; RV32-NEXT: sub a3, a3, a6
-; RV32-NEXT: srli a6, s3, 31
+; RV32-NEXT: sub a3, a3, a7
+; RV32-NEXT: srli a7, s3, 31
; RV32-NEXT: slli s2, s2, 1
; RV32-NEXT: sub a5, s11, a5
; RV32-NEXT: srli s11, t5, 31
@@ -1645,11 +1640,11 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: srli s0, s0, 31
; RV32-NEXT: slli t5, t5, 1
; RV32-NEXT: or a2, ra, a2
-; RV32-NEXT: or t0, a1, t6
-; RV32-NEXT: or a6, s2, a6
-; RV32-NEXT: or s2, t1, t3
+; RV32-NEXT: or t1, a1, t6
+; RV32-NEXT: or a7, s2, a7
+; RV32-NEXT: or s2, a6, t3
; RV32-NEXT: or s3, s3, s11
-; RV32-NEXT: or t4, a1, t1
+; RV32-NEXT: or t4, a1, a6
; RV32-NEXT: lw s4, 52(sp) # 4-byte Folded Reload
; RV32-NEXT: or t5, s4, t5
; RV32-NEXT: seqz s4, a1
@@ -1659,15 +1654,15 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: sw a0, 52(sp) # 4-byte Folded Spill
; RV32-NEXT: sub ra, t2, s9
; RV32-NEXT: sltu t2, t2, s9
-; RV32-NEXT: sub a3, a3, a7
+; RV32-NEXT: sub a3, a3, t0
; RV32-NEXT: sub s11, a5, a4
-; RV32-NEXT: or a4, t0, s2
+; RV32-NEXT: or a4, t1, s2
; RV32-NEXT: seqz a5, t4
-; RV32-NEXT: sub t1, t1, s4
+; RV32-NEXT: sub a6, a6, s4
; RV32-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
; RV32-NEXT: or s3, a0, s3
; RV32-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
-; RV32-NEXT: or s2, a0, a6
+; RV32-NEXT: or s2, a0, a7
; RV32-NEXT: or s0, s6, a2
; RV32-NEXT: andi a0, s7, 1
; RV32-NEXT: sub s9, a3, t2
@@ -1678,7 +1673,7 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: sub t3, t3, a3
; RV32-NEXT: or a3, a1, t6
; RV32-NEXT: not s1, a2
-; RV32-NEXT: or a2, t1, t3
+; RV32-NEXT: or a2, a6, t3
; RV32-NEXT: andi s1, s1, 1
; RV32-NEXT: or a2, a3, a2
; RV32-NEXT: or a2, a2, s1
@@ -1740,7 +1735,7 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: slli a0, a2, 31
; RV32-NEXT: srai a0, a0, 31
; RV32-NEXT: lw a2, 28(sp) # 4-byte Folded Reload
-; RV32-NEXT: and a6, a0, a2
+; RV32-NEXT: and a7, a0, a2
; RV32-NEXT: lw a2, 36(sp) # 4-byte Folded Reload
; RV32-NEXT: and s8, a0, a2
; RV32-NEXT: lw a5, 24(sp) # 4-byte Folded Reload
@@ -2047,41 +2042,40 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV64-NEXT: add a6, a6, a7
; RV64-NEXT: srli t5, a6, 56
; RV64-NEXT: .LBB3_13: # %_udiv-special-cases
-; RV64-NEXT: or t0, t3, t1
+; RV64-NEXT: or a7, t3, t1
; RV64-NEXT: or a6, s2, t4
-; RV64-NEXT: and a7, s3, s0
+; RV64-NEXT: and t0, s3, s0
; RV64-NEXT: or t6, t6, a1
; RV64-NEXT: addi s0, t5, 128
; RV64-NEXT: bnez t6, .LBB3_15
; RV64-NEXT: # %bb.14: # %_udiv-special-cases
; RV64-NEXT: mv s4, s0
; RV64-NEXT: .LBB3_15: # %_udiv-special-cases
-; RV64-NEXT: seqz a1, t0
-; RV64-NEXT: sltu t0, s0, t5
+; RV64-NEXT: seqz a1, a7
+; RV64-NEXT: sltu a7, s0, t5
; RV64-NEXT: snez t5, t6
; RV64-NEXT: addi t5, t5, -1
-; RV64-NEXT: and t0, t5, t0
-; RV64-NEXT: sltu t5, t2, s4
-; RV64-NEXT: seqz a6, a6
-; RV64-NEXT: mv t6, t5
-; RV64-NEXT: beq a7, t0, .LBB3_17
+; RV64-NEXT: and t5, t5, a7
+; RV64-NEXT: sltu t6, t2, s4
+; RV64-NEXT: seqz a7, a6
+; RV64-NEXT: mv a6, t6
+; RV64-NEXT: beq t0, t5, .LBB3_17
; RV64-NEXT: # %bb.16: # %_udiv-special-cases
-; RV64-NEXT: sltu t6, a7, t0
+; RV64-NEXT: sltu a6, t0, t5
; RV64-NEXT: .LBB3_17: # %_udiv-special-cases
-; RV64-NEXT: or a1, a1, a6
-; RV64-NEXT: andi a6, t6, 1
-; RV64-NEXT: sub a7, a7, t0
-; RV64-NEXT: sub t0, a7, t5
+; RV64-NEXT: or a1, a1, a7
; RV64-NEXT: sub a7, t2, s4
+; RV64-NEXT: sub t0, t0, t5
+; RV64-NEXT: sub t0, t0, t6
; RV64-NEXT: beqz a6, .LBB3_19
; RV64-NEXT: # %bb.18: # %_udiv-special-cases
; RV64-NEXT: mv t2, a6
; RV64-NEXT: j .LBB3_20
; RV64-NEXT: .LBB3_19:
-; RV64-NEXT: sltiu t2, a7, 129
-; RV64-NEXT: xori t2, t2, 1
-; RV64-NEXT: snez t5, t0
-; RV64-NEXT: or t2, t2, t5
+; RV64-NEXT: snez t2, t0
+; RV64-NEXT: sltiu t5, a7, 129
+; RV64-NEXT: xori t5, t5, 1
+; RV64-NEXT: or t2, t5, t2
; RV64-NEXT: .LBB3_20: # %_udiv-special-cases
; RV64-NEXT: or t6, a1, t2
; RV64-NEXT: addi t5, t6, -1
diff --git a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
index c62fb0ae63555..305aeed22d13e 100644
--- a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
@@ -265,17 +265,19 @@ define i32 @ctlz_lshr_i32(i32 signext %a) {
; RV64I-NEXT: srliw a0, a0, 1
; RV64I-NEXT: beqz a0, .LBB4_2
; RV64I-NEXT: # %bb.1: # %cond.false
-; RV64I-NEXT: srliw a1, a0, 1
+; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addi a1, a2, 1365
-; RV64I-NEXT: srliw a2, a0, 2
+; RV64I-NEXT: srli a2, a0, 2
; RV64I-NEXT: or a0, a0, a2
-; RV64I-NEXT: srliw a2, a0, 4
+; RV64I-NEXT: srli a2, a0, 4
; RV64I-NEXT: or a0, a0, a2
-; RV64I-NEXT: srliw a2, a0, 8
+; RV64I-NEXT: slli a2, a0, 33
+; RV64I-NEXT: srli a2, a2, 41
; RV64I-NEXT: or a0, a0, a2
-; RV64I-NEXT: srliw a2, a0, 16
+; RV64I-NEXT: slli a2, a0, 33
+; RV64I-NEXT: srli a2, a2, 49
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: srli a2, a0, 1
diff --git a/llvm/test/CodeGen/RISCV/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64zbb.ll
index e840605710f21..58ba26e210519 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb.ll
@@ -229,17 +229,19 @@ define i32 @ctlz_lshr_i32(i32 signext %a) {
; RV64I-NEXT: srliw a0, a0, 1
; RV64I-NEXT: beqz a0, .LBB4_2
; RV64I-NEXT: # %bb.1: # %cond.false
-; RV64I-NEXT: srliw a1, a0, 1
+; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addi a1, a2, 1365
-; RV64I-NEXT: srliw a2, a0, 2
+; RV64I-NEXT: srli a2, a0, 2
; RV64I-NEXT: or a0, a0, a2
-; RV64I-NEXT: srliw a2, a0, 4
+; RV64I-NEXT: srli a2, a0, 4
; RV64I-NEXT: or a0, a0, a2
-; RV64I-NEXT: srliw a2, a0, 8
+; RV64I-NEXT: slli a2, a0, 33
+; RV64I-NEXT: srli a2, a2, 41
; RV64I-NEXT: or a0, a0, a2
-; RV64I-NEXT: srliw a2, a0, 16
+; RV64I-NEXT: slli a2, a0, 33
+; RV64I-NEXT: srli a2, a2, 49
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: srli a2, a0, 1
diff --git a/llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll b/llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
index cd7f30d8f5898..32753ca382fc7 100644
--- a/llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
+++ b/llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
@@ -716,101 +716,92 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: slli a4, a4, 8
; RV32I-NEXT: slli a5, a5, 16
; RV32I-NEXT: slli a6, a6, 24
-; RV32I-NEXT: or a3, a4, a3
-; RV32I-NEXT: or a4, a6, a5
-; RV32I-NEXT: lbu a5, 8(a0)
-; RV32I-NEXT: lbu a6, 9(a0)
-; RV32I-NEXT: lbu t3, 10(a0)
-; RV32I-NEXT: lbu t4, 11(a0)
; RV32I-NEXT: slli t0, t0, 8
+; RV32I-NEXT: or a4, a4, a3
+; RV32I-NEXT: or a5, a6, a5
+; RV32I-NEXT: or a3, t0, a7
+; RV32I-NEXT: lbu a6, 8(a0)
+; RV32I-NEXT: lbu a7, 9(a0)
+; RV32I-NEXT: lbu t0, 10(a0)
+; RV32I-NEXT: lbu t3, 11(a0)
; RV32I-NEXT: slli t1, t1, 16
; RV32I-NEXT: slli t2, t2, 24
-; RV32I-NEXT: slli a6, a6, 8
-; RV32I-NEXT: or a7, t0, a7
-; RV32I-NEXT: or t0, t2, t1
-; RV32I-NEXT: or a5, a6, a5
-; RV32I-NEXT: lbu a6, 12(a0)
-; RV32I-NEXT: lbu t1, 13(a0)
-; RV32I-NEXT: lbu t2, 14(a0)
-; RV32I-NEXT: lbu a0, 15(a0)
-; RV32I-NEXT: slli t3, t3, 16
-; RV32I-NEXT: slli t4, t4, 24
-; RV32I-NEXT: slli t1, t1, 8
-; RV32I-NEXT: slli t2, t2, 16
-; RV32I-NEXT: slli a0, a0, 24
-; RV32I-NEXT: or t3, t4, t3
-; RV32I-NEXT: or a6, t1, a6
-; RV32I-NEXT: or a0, a0, t2
-; RV32I-NEXT: lbu t1, 1(a1)
-; RV32I-NEXT: lbu t2, 0(a1)
-; RV32I-NEXT: lbu t4, 2(a1)
-; RV32I-NEXT: lbu a1, 3(a1)
-; RV32I-NEXT: slli t1, t1, 8
-; RV32I-NEXT: or t1, t1, t2
+; RV32I-NEXT: slli a7, a7, 8
+; RV32I-NEXT: slli t0, t0, 16
+; RV32I-NEXT: slli t3, t3, 24
+; RV32I-NEXT: or t1, t2, t1
+; RV32I-NEXT: or a6, a7, a6
+; RV32I-NEXT: or a7, t3, t0
+; RV32I-NEXT: lbu t0, 12(a0)
+; RV32I-NEXT: lbu t2, 13(a0)
+; RV32I-NEXT: lbu t3, 14(a0)
+; RV32I-NEXT: lbu t4, 15(a0)
+; RV32I-NEXT: lbu a0, 0(a1)
; RV32I-NEXT: sw zero, 16(sp)
; RV32I-NEXT: sw zero, 20(sp)
; RV32I-NEXT: sw zero, 24(sp)
; RV32I-NEXT: sw zero, 28(sp)
-; RV32I-NEXT: slli t4, t4, 16
-; RV32I-NEXT: slli a1, a1, 24
-; RV32I-NEXT: or a1, a1, t4
-; RV32I-NEXT: mv t2, sp
-; RV32I-NEXT: or a3, a4, a3
-; RV32I-NEXT: or a4, t0, a7
-; RV32I-NEXT: or a5, t3, a5
-; RV32I-NEXT: or a0, a0, a6
-; RV32I-NEXT: or a1, a1, t1
-; RV32I-NEXT: sw a3, 0(sp)
-; RV32I-NEXT: sw a4, 4(sp)
-; RV32I-NEXT: sw a5, 8(sp)
-; RV32I-NEXT: sw a0, 12(sp)
-; RV32I-NEXT: srli a0, a1, 3
-; RV32I-NEXT: andi a3, a1, 31
-; RV32I-NEXT: andi a0, a0, 12
-; RV32I-NEXT: xori a3, a3, 31
-; RV32I-NEXT: add a0, t2, a0
-; RV32I-NEXT: lw a4, 4(a0)
-; RV32I-NEXT: lw a5, 8(a0)
-; RV32I-NEXT: lw a6, 0(a0)
-; RV32I-NEXT: lw a0, 12(a0)
-; RV32I-NEXT: srl a7, a4, a1
-; RV32I-NEXT: slli t0, a5, 1
-; RV32I-NEXT: srl a6, a6, a1
-; RV32I-NEXT: slli a4, a4, 1
-; RV32I-NEXT: srl a5, a5, a1
-; RV32I-NEXT: slli t1, a0, 1
-; RV32I-NEXT: srl a0, a0, a1
-; RV32I-NEXT: sll a1, t0, a3
-; RV32I-NEXT: sll a4, a4, a3
-; RV32I-NEXT: sll a3, t1, a3
+; RV32I-NEXT: slli t2, t2, 8
+; RV32I-NEXT: or a1, t2, t0
+; RV32I-NEXT: mv t0, sp
+; RV32I-NEXT: slli t3, t3, 16
+; RV32I-NEXT: slli t4, t4, 24
+; RV32I-NEXT: or t2, t4, t3
+; RV32I-NEXT: srli t3, a0, 3
+; RV32I-NEXT: or a4, a5, a4
+; RV32I-NEXT: andi a5, a0, 31
+; RV32I-NEXT: andi t3, t3, 12
+; RV32I-NEXT: xori a5, a5, 31
+; RV32I-NEXT: or a3, t1, a3
+; RV32I-NEXT: or a6, a7, a6
+; RV32I-NEXT: or a1, t2, a1
+; RV32I-NEXT: add t0, t0, t3
+; RV32I-NEXT: sw a4, 0(sp)
+; RV32I-NEXT: sw a3, 4(sp)
+; RV32I-NEXT: sw a6, 8(sp)
+; RV32I-NEXT: sw a1, 12(sp)
+; RV32I-NEXT: lw a1, 4(t0)
+; RV32I-NEXT: lw a3, 8(t0)
+; RV32I-NEXT: lw a4, 0(t0)
+; RV32I-NEXT: lw a6, 12(t0)
+; RV32I-NEXT: srl a7, a1, a0
+; RV32I-NEXT: slli t0, a3, 1
+; RV32I-NEXT: srl a4, a4, a0
+; RV32I-NEXT: slli a1, a1, 1
+; RV32I-NEXT: srl a3, a3, a0
+; RV32I-NEXT: slli t1, a6, 1
+; RV32I-NEXT: srl a0, a6, a0
+; RV32I-NEXT: sll a6, t0, a5
+; RV32I-NEXT: sll a1, a1, a5
+; RV32I-NEXT: sll a5, t1, a5
; RV32I-NEXT: srli t0, a0, 16
; RV32I-NEXT: srli t1, a0, 24
; RV32I-NEXT: srli t2, a0, 8
-; RV32I-NEXT: or a1, a7, a1
-; RV32I-NEXT: or a4, a6, a4
-; RV32I-NEXT: or a3, a5, a3
+; RV32I-NEXT: or a6, a7, a6
+; RV32I-NEXT: or a1, a4, a1
+; RV32I-NEXT: or a3, a3, a5
; RV32I-NEXT: sb a0, 12(a2)
; RV32I-NEXT: sb t2, 13(a2)
; RV32I-NEXT: sb t0, 14(a2)
; RV32I-NEXT: sb t1, 15(a2)
; RV32I-NEXT: srli a0, a3, 16
-; RV32I-NEXT: srli a5, a3, 24
-; RV32I-NEXT: srli a6, a3, 8
-; RV32I-NEXT: srli a7, a4, 16
-; RV32I-NEXT: srli t0, a4, 24
-; RV32I-NEXT: srli t1, a4, 8
-; RV32I-NEXT: srli t2, a1, 16
-; RV32I-NEXT: srli t3, a1, 24
+; RV32I-NEXT: srli a4, a3, 24
+; RV32I-NEXT: srli a5, a3, 8
+; RV32I-NEXT: srli a7, a1, 16
+; RV32I-NEXT: srli t0, a1, 24
+; RV32I-NEXT: srli t1, a1, 8
+; RV32I-NEXT: srli t2, a6, 16
+; RV32I-NEXT: srli t3, a6, 24
; RV32I-NEXT: sb a3, 8(a2)
-; RV32I-NEXT: sb a6, 9(a2)
+; RV32I-NEXT: sb a5, 9(a2)
; RV32I-NEXT: sb a0, 10(a2)
-; RV32I-NEXT: sb a5, 11(a2)
-; RV32I-NEXT: srli a0, a1, 8
-; RV32I-NEXT: sb a4, 0(a2)
+; RV32I-NEXT: sb a4, 11(a2)
+; RV32I-NEXT: srli a0, a6, 8
+; RV32I-NEXT: sb a1, 0(a2)
; RV32I-NEXT: sb t1, 1(a2)
; RV32I-NEXT: sb a7, 2(a2)
; RV32I-NEXT: sb t0, 3(a2)
-; RV32I-NEXT: sb a1, 4(a2)
+; RV32I-NEXT: sb a6, 4(a2)
; RV32I-NEXT: sb a0, 5(a2)
; RV32I-NEXT: sb t2, 6(a2)
; RV32I-NEXT: sb t3, 7(a2)
@@ -952,102 +943,93 @@ define void @shl_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: slli a4, a4, 8
; RV32I-NEXT: slli a5, a5, 16
; RV32I-NEXT: slli a6, a6, 24
-; RV32I-NEXT: or a3, a4, a3
-; RV32I-NEXT: or a4, a6, a5
-; RV32I-NEXT: lbu a5, 8(a0)
-; RV32I-NEXT: lbu a6, 9(a0)
-; RV32I-NEXT: lbu t3, 10(a0)
-; RV32I-NEXT: lbu t4, 11(a0)
; RV32I-NEXT: slli t0, t0, 8
+; RV32I-NEXT: or a4, a4, a3
+; RV32I-NEXT: or a5, a6, a5
+; RV32I-NEXT: or a3, t0, a7
+; RV32I-NEXT: lbu a6, 8(a0)
+; RV32I-NEXT: lbu a7, 9(a0)
+; RV32I-NEXT: lbu t0, 10(a0)
+; RV32I-NEXT: lbu t3, 11(a0)
; RV32I-NEXT: slli t1, t1, 16
; RV32I-NEXT: slli t2, t2, 24
-; RV32I-NEXT: slli a6, a6, 8
-; RV32I-NEXT: or a7, t0, a7
-; RV32I-NEXT: or t0, t2, t1
-; RV32I-NEXT: or a5, a6, a5
-; RV32I-NEXT: lbu a6, 12(a0)
-; RV32I-NEXT: lbu t1, 13(a0)
-; RV32I-NEXT: lbu t2, 14(a0)
-; RV32I-NEXT: lbu a0, 15(a0)
-; RV32I-NEXT: slli t3, t3, 16
-; RV32I-NEXT: slli t4, t4, 24
-; RV32I-NEXT: slli t1, t1, 8
-; RV32I-NEXT: slli t2, t2, 16
-; RV32I-NEXT: slli a0, a0, 24
-; RV32I-NEXT: or t3, t4, t3
-; RV32I-NEXT: or a6, t1, a6
-; RV32I-NEXT: or a0, a0, t2
-; RV32I-NEXT: lbu t1, 1(a1)
-; RV32I-NEXT: lbu t2, 0(a1)
-; RV32I-NEXT: lbu t4, 2(a1)
-; RV32I-NEXT: lbu a1, 3(a1)
-; RV32I-NEXT: slli t1, t1, 8
-; RV32I-NEXT: or t1, t1, t2
+; RV32I-NEXT: slli a7, a7, 8
+; RV32I-NEXT: slli t0, t0, 16
+; RV32I-NEXT: slli t3, t3, 24
+; RV32I-NEXT: or t1, t2, t1
+; RV32I-NEXT: or a6, a7, a6
+; RV32I-NEXT: or a7, t3, t0
+; RV32I-NEXT: lbu t0, 12(a0)
+; RV32I-NEXT: lbu t2, 13(a0)
+; RV32I-NEXT: lbu t3, 14(a0)
+; RV32I-NEXT: lbu t4, 15(a0)
+; RV32I-NEXT: lbu a0, 0(a1)
; RV32I-NEXT: sw zero, 0(sp)
; RV32I-NEXT: sw zero, 4(sp)
; RV32I-NEXT: sw zero, 8(sp)
; RV32I-NEXT: sw zero, 12(sp)
-; RV32I-NEXT: slli t4, t4, 16
-; RV32I-NEXT: slli a1, a1, 24
-; RV32I-NEXT: or a1, a1, t4
-; RV32I-NEXT: addi t2, sp, 16
+; RV32I-NEXT: slli t2, t2, 8
+; RV32I-NEXT: or a1, t2, t0
+; RV32I-NEXT: addi t0, sp, 16
+; RV32I-NEXT: slli t3, t3, 16
+; RV32I-NEXT: slli t4, t4, 24
+; RV32I-NEXT: or t2, t4, t3
+; RV32I-NEXT: srli t3, a0, 3
+; RV32I-NEXT: or a4, a5, a4
+; RV32I-NEXT: andi a5, a0, 31
+; RV32I-NEXT: andi t3, t3, 12
+; RV32I-NEXT: or a3, t1, a3
+; RV32I-NEXT: or a6, a7, a6
+; RV32I-NEXT: or a1, t2, a1
+; RV32I-NEXT: sub a7, t0, t3
+; RV32I-NEXT: sw a4, 16(sp)
+; RV32I-NEXT: sw a3, 20(sp)
+; RV32I-NEXT: sw a6, 24(sp)
+; RV32I-NEXT: sw a1, 28(sp)
+; RV32I-NEXT: lw a1, 0(a7)
+; RV32I-NEXT: lw a3, 4(a7)
+; RV32I-NEXT: lw a4, 8(a7)
+; RV32I-NEXT: lw a6, 12(a7)
+; RV32I-NEXT: xori a5, a5, 31
+; RV32I-NEXT: sll a7, a3, a0
+; RV32I-NEXT: srli t0, a1, 1
+; RV32I-NEXT: sll a6, a6, a0
+; RV32I-NEXT: srli t1, a4, 1
+; RV32I-NEXT: sll a4, a4, a0
+; RV32I-NEXT: srli a3, a3, 1
+; RV32I-NEXT: sll a0, a1, a0
+; RV32I-NEXT: srl a1, t0, a5
+; RV32I-NEXT: srl t0, t1, a5
+; RV32I-NEXT: srl a3, a3, a5
+; RV32I-NEXT: srli a5, a0, 16
+; RV32I-NEXT: srli t1, a0, 24
+; RV32I-NEXT: srli t2, a0, 8
+; RV32I-NEXT: or a1, a7, a1
+; RV32I-NEXT: or a6, a6, t0
; RV32I-NEXT: or a3, a4, a3
-; RV32I-NEXT: or a4, t0, a7
-; RV32I-NEXT: or a5, t3, a5
-; RV32I-NEXT: or a0, a0, a6
-; RV32I-NEXT: or a1, a1, t1
-; RV32I-NEXT: sw a3, 16(sp)
-; RV32I-NEXT: sw a4, 20(sp)
-; RV32I-NEXT: sw a5, 24(sp)
-; RV32I-NEXT: sw a0, 28(sp)
-; RV32I-NEXT: srli a0, a1, 3
-; RV32I-NEXT: andi a3, a1, 31
-; RV32I-NEXT: andi a0, a0, 12
-; RV32I-NEXT: sub a0, t2, a0
-; RV32I-NEXT: lw a4, 0(a0)
-; RV32I-NEXT: lw a5, 4(a0)
-; RV32I-NEXT: lw a6, 8(a0)
-; RV32I-NEXT: lw a0, 12(a0)
-; RV32I-NEXT: xori a3, a3, 31
-; RV32I-NEXT: sll a7, a5, a1
-; RV32I-NEXT: srli t0, a4, 1
-; RV32I-NEXT: sll a0, a0, a1
-; RV32I-NEXT: srli t1, a6, 1
-; RV32I-NEXT: sll a6, a6, a1
-; RV32I-NEXT: srli a5, a5, 1
-; RV32I-NEXT: sll a1, a4, a1
-; RV32I-NEXT: srl a4, t0, a3
-; RV32I-NEXT: srl t0, t1, a3
-; RV32I-NEXT: srl a3, a5, a3
-; RV32I-NEXT: srli a5, a1, 16
-; RV32I-NEXT: srli t1, a1, 24
-; RV32I-NEXT: srli t2, a1, 8
-; RV32I-NEXT: or a4, a7, a4
-; RV32I-NEXT: or a0, a0, t0
-; RV32I-NEXT: or a3, a6, a3
-; RV32I-NEXT: sb a1, 0(a2)
+; RV32I-NEXT: sb a0, 0(a2)
; RV32I-NEXT: sb t2, 1(a2)
; RV32I-NEXT: sb a5, 2(a2)
; RV32I-NEXT: sb t1, 3(a2)
-; RV32I-NEXT: srli a1, a3, 16
-; RV32I-NEXT: srli a5, a3, 24
-; RV32I-NEXT: srli a6, a3, 8
-; RV32I-NEXT: srli a7, a0, 16
-; RV32I-NEXT: srli t0, a0, 24
-; RV32I-NEXT: srli t1, a0, 8
-; RV32I-NEXT: srli t2, a4, 16
-; RV32I-NEXT: srli t3, a4, 24
+; RV32I-NEXT: srli a0, a3, 16
+; RV32I-NEXT: srli a4, a3, 24
+; RV32I-NEXT: srli a5, a3, 8
+; RV32I-NEXT: srli a7, a6, 16
+; RV32I-NEXT: srli t0, a6, 24
+; RV32I-NEXT: srli t1, a6, 8
+; RV32I-NEXT: srli t2, a1, 16
+; RV32I-NEXT: srli t3, a1, 24
; RV32I-NEXT: sb a3, 8(a2)
-; RV32I-NEXT: sb a6, 9(a2)
-; RV32I-NEXT: sb a1, 10(a2)
-; RV32I-NEXT: sb a5, 11(a2)
-; RV32I-NEXT: srli a1, a4, 8
-; RV32I-NEXT: sb a0, 12(a2)
+; RV32I-NEXT: sb a5, 9(a2)
+; RV32I-NEXT: sb a0, 10(a2)
+; RV32I-NEXT: sb a4, 11(a2)
+; RV32I-NEXT: srli a0, a1, 8
+; RV32I-NEXT: sb a6, 12(a2)
; RV32I-NEXT: sb t1, 13(a2)
; RV32I-NEXT: sb a7, 14(a2)
; RV32I-NEXT: sb t0, 15(a2)
-; RV32I-NEXT: sb a4, 4(a2)
-; RV32I-NEXT: sb a1, 5(a2)
+; RV32I-NEXT: sb a1, 4(a2)
+; RV32I-NEXT: sb a0, 5(a2)
; RV32I-NEXT: sb t2, 6(a2)
; RV32I-NEXT: sb t3, 7(a2)
; RV32I-NEXT: addi sp, sp, 32
@@ -1186,82 +1168,73 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: lbu t1, 6(a0)
; RV32I-NEXT: lbu t2, 7(a0)
; RV32I-NEXT: slli a4, a4, 8
-; RV32I-NEXT: or a3, a4, a3
-; RV32I-NEXT: lbu a4, 8(a0)
-; RV32I-NEXT: lbu t3, 9(a0)
-; RV32I-NEXT: lbu t4, 10(a0)
-; RV32I-NEXT: lbu t5, 11(a0)
; RV32I-NEXT: slli a5, a5, 16
; RV32I-NEXT: slli a6, a6, 24
; RV32I-NEXT: slli t0, t0, 8
+; RV32I-NEXT: or a3, a4, a3
+; RV32I-NEXT: or a4, a6, a5
+; RV32I-NEXT: or a5, t0, a7
+; RV32I-NEXT: lbu a6, 8(a0)
+; RV32I-NEXT: lbu a7, 9(a0)
+; RV32I-NEXT: lbu t0, 10(a0)
+; RV32I-NEXT: lbu t3, 11(a0)
; RV32I-NEXT: slli t1, t1, 16
; RV32I-NEXT: slli t2, t2, 24
-; RV32I-NEXT: or a5, a6, a5
-; RV32I-NEXT: or a6, t0, a7
-; RV32I-NEXT: or a7, t2, t1
+; RV32I-NEXT: slli a7, a7, 8
+; RV32I-NEXT: slli t0, t0, 16
+; RV32I-NEXT: slli t3, t3, 24
+; RV32I-NEXT: or t1, t2, t1
+; RV32I-NEXT: or a6, a7, a6
+; RV32I-NEXT: or a7, t3, t0
; RV32I-NEXT: lbu t0, 12(a0)
-; RV32I-NEXT: lbu t1, 13(a0)
-; RV32I-NEXT: lbu t2, 14(a0)
-; RV32I-NEXT: lbu a0, 15(a0)
-; RV32I-NEXT: slli t3, t3, 8
-; RV32I-NEXT: slli t4, t4, 16
-; RV32I-NEXT: slli t5, t5, 24
-; RV32I-NEXT: slli t1, t1, 8
-; RV32I-NEXT: or a4, t3, a4
-; RV32I-NEXT: or t3, t5, t4
-; RV32I-NEXT: or t0, t1, t0
-; RV32I-NEXT: lbu t1, 1(a1)
-; RV32I-NEXT: lbu t4, 0(a1)
-; RV32I-NEXT: lbu t5, 2(a1)
-; RV32I-NEXT: lbu a1, 3(a1)
-; RV32I-NEXT: slli t1, t1, 8
-; RV32I-NEXT: or t1, t1, t4
-; RV32I-NEXT: slli t5, t5, 16
-; RV32I-NEXT: slli a1, a1, 24
-; RV32I-NEXT: or a1, a1, t5
-; RV32I-NEXT: or a3, a5, a3
-; RV32I-NEXT: mv a5, sp
-; RV32I-NEXT: slli t2, t2, 16
-; RV32I-NEXT: slli a0, a0, 24
-; RV32I-NEXT: or t2, a0, t2
-; RV32I-NEXT: srai a0, a0, 31
+; RV32I-NEXT: lbu t2, 13(a0)
+; RV32I-NEXT: lbu t3, 14(a0)
+; RV32I-NEXT: lbu t4, 15(a0)
+; RV32I-NEXT: lbu a0, 0(a1)
+; RV32I-NEXT: slli t2, t2, 8
+; RV32I-NEXT: or a1, t2, t0
+; RV32I-NEXT: mv t0, sp
+; RV32I-NEXT: slli t3, t3, 16
+; RV32I-NEXT: slli t4, t4, 24
+; RV32I-NEXT: or a3, a4, a3
+; RV32I-NEXT: srli a4, a0, 3
+; RV32I-NEXT: or a5, t1, a5
+; RV32I-NEXT: andi t1, a0, 31
+; RV32I-NEXT: or t2, t4, t3
+; RV32I-NEXT: srai t3, t4, 31
+; RV32I-NEXT: andi a4, a4, 12
+; RV32I-NEXT: xori t1, t1, 31
; RV32I-NEXT: or a6, a7, a6
-; RV32I-NEXT: or a4, t3, a4
-; RV32I-NEXT: or a7, t2, t0
-; RV32I-NEXT: or a1, a1, t1
-; RV32I-NEXT: sw a0, 16(sp)
-; RV32I-NEXT: sw a0, 20(sp)
-; RV32I-NEXT: sw a0, 24(sp)
-; RV32I-NEXT: sw a0, 28(sp)
+; RV32I-NEXT: or a1, t2, a1
+; RV32I-NEXT: sw t3, 16(sp)
+; RV32I-NEXT: sw t3, 20(sp)
+; RV32I-NEXT: sw t3, 24(sp)
+; RV32I-NEXT: sw t3, 28(sp)
+; RV32I-NEXT: add a4, t0, a4
; RV32I-NEXT: sw a3, 0(sp)
-; RV32I-NEXT: sw a6, 4(sp)
-; RV32I-NEXT: sw a4, 8(sp)
-; RV32I-NEXT: sw a7, 12(sp)
-; RV32I-NEXT: srli a0, a1, 3
-; RV32I-NEXT: andi a3, a1, 31
-; RV32I-NEXT: andi a0, a0, 12
-; RV32I-NEXT: xori a3, a3, 31
-; RV32I-NEXT: add a0, a5, a0
-; RV32I-NEXT: lw a4, 4(a0)
-; RV32I-NEXT: lw a5, 8(a0)
-; RV32I-NEXT: lw a6, 0(a0)
-; RV32I-NEXT: lw a0, 12(a0)
-; RV32I-NEXT: srl a7, a4, a1
-; RV32I-NEXT: slli t0, a5, 1
-; RV32I-NEXT: srl a6, a6, a1
-; RV32I-NEXT: slli a4, a4, 1
-; RV32I-NEXT: srl a5, a5, a1
-; RV32I-NEXT: slli t1, a0, 1
-; RV32I-NEXT: sra a0, a0, a1
-; RV32I-NEXT: sll a1, t0, a3
-; RV32I-NEXT: sll a4, a4, a3
-; RV32I-NEXT: sll a3, t1, a3
+; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a6, 8(sp)
+; RV32I-NEXT: sw a1, 12(sp)
+; RV32I-NEXT: lw a1, 4(a4)
+; RV32I-NEXT: lw a3, 8(a4)
+; RV32I-NEXT: lw a5, 0(a4)
+; RV32I-NEXT: lw a4, 12(a4)
+; RV32I-NEXT: srl a6, a1, a0
+; RV32I-NEXT: slli a7, a3, 1
+; RV32I-NEXT: srl a5, a5, a0
+; RV32I-NEXT: slli a1, a1, 1
+; RV32I-NEXT: srl a3, a3, a0
+; RV32I-NEXT: slli t0, a4, 1
+; RV32I-NEXT: sra a0, a4, a0
+; RV32I-NEXT: sll a4, a7, t1
+; RV32I-NEXT: sll a1, a1, t1
+; RV32I-NEXT: sll a7, t0, t1
; RV32I-NEXT: srli t0, a0, 16
; RV32I-NEXT: srli t1, a0, 24
; RV32I-NEXT: srli t2, a0, 8
-; RV32I-NEXT: or a1, a7, a1
; RV32I-NEXT: or a4, a6, a4
-; RV32I-NEXT: or a3, a5, a3
+; RV32I-NEXT: or a1, a5, a1
+; RV32I-NEXT: or a3, a3, a7
; RV32I-NEXT: sb a0, 12(a2)
; RV32I-NEXT: sb t2, 13(a2)
; RV32I-NEXT: sb t0, 14(a2)
@@ -1269,21 +1242,21 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: srli a0, a3, 16
; RV32I-NEXT: srli a5, a3, 24
; RV32I-NEXT: srli a6, a3, 8
-; RV32I-NEXT: srli a7, a4, 16
-; RV32I-NEXT: srli t0, a4, 24
-; RV32I-NEXT: srli t1, a4, 8
-; RV32I-NEXT: srli t2, a1, 16
-; RV32I-NEXT: srli t3, a1, 24
+; RV32I-NEXT: srli a7, a1, 16
+; RV32I-NEXT: srli t0, a1, 24
+; RV32I-NEXT: srli t1, a1, 8
+; RV32I-NEXT: srli t2, a4, 16
+; RV32I-NEXT: srli t3, a4, 24
; RV32I-NEXT: sb a3, 8(a2)
; RV32I-NEXT: sb a6, 9(a2)
; RV32I-NEXT: sb a0, 10(a2)
; RV32I-NEXT: sb a5, 11(a2)
-; RV32I-NEXT: srli a0, a1, 8
-; RV32I-NEXT: sb a4, 0(a2)
+; RV32I-NEXT: srli a0, a4, 8
+; RV32I-NEXT: sb a1, 0(a2)
; RV32I-NEXT: sb t1, 1(a2)
; RV32I-NEXT: sb a7, 2(a2)
; RV32I-NEXT: sb t0, 3(a2)
-; RV32I-NEXT: sb a1, 4(a2)
+; RV32I-NEXT: sb a4, 4(a2)
; RV32I-NEXT: sb a0, 5(a2)
; RV32I-NEXT: sb t2, 6(a2)
; RV32I-NEXT: sb t3, 7(a2)
@@ -1299,19 +1272,17 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-LABEL: lshr_32bytes:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -160
-; RV64I-NEXT: sd s0, 152(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 144(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 136(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 128(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s4, 120(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s5, 112(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s6, 104(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s7, 96(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s8, 88(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s9, 80(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s10, 72(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s11, 64(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -144
+; RV64I-NEXT: sd s0, 136(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 128(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 120(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 112(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 104(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s5, 96(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s6, 88(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s7, 80(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s8, 72(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s9, 64(sp) # 8-byte Folded Spill
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: lbu a4, 1(a0)
; RV64I-NEXT: lbu a5, 2(a0)
@@ -1328,143 +1299,122 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: lbu s1, 13(a0)
; RV64I-NEXT: lbu s2, 14(a0)
; RV64I-NEXT: lbu s3, 15(a0)
+; RV64I-NEXT: slli a4, a4, 8
+; RV64I-NEXT: slli a5, a5, 16
+; RV64I-NEXT: slli a6, a6, 24
+; RV64I-NEXT: or a3, a4, a3
+; RV64I-NEXT: or a4, a6, a5
; RV64I-NEXT: lbu s4, 16(a0)
; RV64I-NEXT: lbu s5, 17(a0)
; RV64I-NEXT: lbu s6, 18(a0)
; RV64I-NEXT: lbu s7, 19(a0)
-; RV64I-NEXT: slli a4, a4, 8
-; RV64I-NEXT: slli s8, a5, 16
-; RV64I-NEXT: slli a6, a6, 24
; RV64I-NEXT: slli t0, t0, 8
; RV64I-NEXT: slli t1, t1, 16
; RV64I-NEXT: slli t2, t2, 24
-; RV64I-NEXT: or a5, a4, a3
-; RV64I-NEXT: or a6, a6, s8
-; RV64I-NEXT: or a3, t0, a7
-; RV64I-NEXT: or a4, t2, t1
-; RV64I-NEXT: lbu s8, 20(a0)
-; RV64I-NEXT: lbu s9, 21(a0)
-; RV64I-NEXT: lbu s10, 22(a0)
-; RV64I-NEXT: lbu s11, 23(a0)
; RV64I-NEXT: slli t4, t4, 8
; RV64I-NEXT: slli t5, t5, 16
; RV64I-NEXT: slli t6, t6, 24
+; RV64I-NEXT: or a5, t0, a7
+; RV64I-NEXT: or a6, t2, t1
+; RV64I-NEXT: or a7, t4, t3
+; RV64I-NEXT: or t0, t6, t5
+; RV64I-NEXT: lbu t5, 20(a0)
+; RV64I-NEXT: lbu t6, 21(a0)
+; RV64I-NEXT: lbu s8, 22(a0)
+; RV64I-NEXT: lbu s9, 23(a0)
; RV64I-NEXT: slli s1, s1, 8
; RV64I-NEXT: slli s2, s2, 16
; RV64I-NEXT: slli s3, s3, 24
-; RV64I-NEXT: or a7, t4, t3
-; RV64I-NEXT: or t0, t6, t5
-; RV64I-NEXT: or t1, s1, s0
-; RV64I-NEXT: or t2, s3, s2
-; RV64I-NEXT: lbu t6, 24(a0)
-; RV64I-NEXT: lbu s0, 25(a0)
-; RV64I-NEXT: lbu s1, 26(a0)
-; RV64I-NEXT: lbu s2, 27(a0)
; RV64I-NEXT: slli s5, s5, 8
; RV64I-NEXT: slli s6, s6, 16
; RV64I-NEXT: slli s7, s7, 24
-; RV64I-NEXT: slli s9, s9, 8
+; RV64I-NEXT: or t1, s1, s0
+; RV64I-NEXT: or t2, s3, s2
; RV64I-NEXT: or t3, s5, s4
; RV64I-NEXT: or t4, s7, s6
-; RV64I-NEXT: or t5, s9, s8
-; RV64I-NEXT: lbu s3, 28(a0)
+; RV64I-NEXT: lbu s0, 24(a0)
+; RV64I-NEXT: lbu s1, 25(a0)
+; RV64I-NEXT: lbu s2, 26(a0)
+; RV64I-NEXT: lbu s3, 27(a0)
+; RV64I-NEXT: slli t6, t6, 8
+; RV64I-NEXT: slli s8, s8, 16
+; RV64I-NEXT: slli s9, s9, 24
+; RV64I-NEXT: slli s1, s1, 8
+; RV64I-NEXT: or t5, t6, t5
+; RV64I-NEXT: or t6, s9, s8
+; RV64I-NEXT: or s0, s1, s0
+; RV64I-NEXT: lbu s1, 28(a0)
; RV64I-NEXT: lbu s4, 29(a0)
; RV64I-NEXT: lbu s5, 30(a0)
; RV64I-NEXT: lbu s6, 31(a0)
-; RV64I-NEXT: slli s10, s10, 16
-; RV64I-NEXT: slli s11, s11, 24
-; RV64I-NEXT: slli s0, s0, 8
-; RV64I-NEXT: slli s1, s1, 16
-; RV64I-NEXT: slli s2, s2, 24
-; RV64I-NEXT: slli s4, s4, 8
-; RV64I-NEXT: or a0, s11, s10
-; RV64I-NEXT: or t6, s0, t6
-; RV64I-NEXT: or s0, s2, s1
-; RV64I-NEXT: or s1, s4, s3
-; RV64I-NEXT: lbu s2, 0(a1)
-; RV64I-NEXT: lbu s3, 1(a1)
-; RV64I-NEXT: lbu s4, 2(a1)
-; RV64I-NEXT: lbu s7, 3(a1)
-; RV64I-NEXT: slli s5, s5, 16
-; RV64I-NEXT: slli s6, s6, 24
-; RV64I-NEXT: slli s3, s3, 8
-; RV64I-NEXT: slli s4, s4, 16
-; RV64I-NEXT: slli s7, s7, 24
-; RV64I-NEXT: or s5, s6, s5
-; RV64I-NEXT: or s2, s3, s2
-; RV64I-NEXT: or s3, s7, s4
-; RV64I-NEXT: lbu s4, 5(a1)
-; RV64I-NEXT: lbu s6, 4(a1)
-; RV64I-NEXT: lbu s7, 6(a1)
-; RV64I-NEXT: lbu a1, 7(a1)
-; RV64I-NEXT: slli s4, s4, 8
-; RV64I-NEXT: or s4, s4, s6
-; RV64I-NEXT: slli s7, s7, 16
-; RV64I-NEXT: slli a1, a1, 24
-; RV64I-NEXT: or a1, a1, s7
+; RV64I-NEXT: lbu a0, 0(a1)
; RV64I-NEXT: sd zero, 32(sp)
; RV64I-NEXT: sd zero, 40(sp)
; RV64I-NEXT: sd zero, 48(sp)
; RV64I-NEXT: sd zero, 56(sp)
-; RV64I-NEXT: or a5, a6, a5
-; RV64I-NEXT: mv a6, sp
+; RV64I-NEXT: slli s2, s2, 16
+; RV64I-NEXT: slli s3, s3, 24
+; RV64I-NEXT: or a1, s3, s2
+; RV64I-NEXT: mv s2, sp
+; RV64I-NEXT: slli s4, s4, 8
+; RV64I-NEXT: slli s5, s5, 16
+; RV64I-NEXT: slli s6, s6, 24
+; RV64I-NEXT: or s1, s4, s1
+; RV64I-NEXT: srli s3, a0, 3
+; RV64I-NEXT: or s4, s6, s5
+; RV64I-NEXT: andi s5, a0, 63
+; RV64I-NEXT: andi s3, s3, 24
+; RV64I-NEXT: xori s5, s5, 63
; RV64I-NEXT: or a3, a4, a3
-; RV64I-NEXT: or a4, t0, a7
-; RV64I-NEXT: or a7, t2, t1
-; RV64I-NEXT: or t0, t4, t3
-; RV64I-NEXT: or a0, a0, t5
-; RV64I-NEXT: or t1, s0, t6
-; RV64I-NEXT: or t2, s5, s1
-; RV64I-NEXT: or t3, s3, s2
-; RV64I-NEXT: or a1, a1, s4
-; RV64I-NEXT: slli a3, a3, 32
-; RV64I-NEXT: slli a7, a7, 32
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: slli t2, t2, 32
-; RV64I-NEXT: slli a1, a1, 32
-; RV64I-NEXT: or a3, a3, a5
-; RV64I-NEXT: or a4, a7, a4
-; RV64I-NEXT: or a0, a0, t0
-; RV64I-NEXT: or a5, t2, t1
-; RV64I-NEXT: or a1, a1, t3
+; RV64I-NEXT: or a4, a6, a5
+; RV64I-NEXT: or a5, t0, a7
+; RV64I-NEXT: or a6, t2, t1
+; RV64I-NEXT: or a7, t4, t3
+; RV64I-NEXT: or t0, t6, t5
+; RV64I-NEXT: or a1, a1, s0
+; RV64I-NEXT: or t1, s4, s1
+; RV64I-NEXT: add s2, s2, s3
+; RV64I-NEXT: slli a4, a4, 32
+; RV64I-NEXT: slli a6, a6, 32
+; RV64I-NEXT: slli t0, t0, 32
+; RV64I-NEXT: slli t1, t1, 32
+; RV64I-NEXT: or a3, a4, a3
+; RV64I-NEXT: or a4, a6, a5
+; RV64I-NEXT: or a5, t0, a7
+; RV64I-NEXT: or a1, t1, a1
; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: sd a4, 8(sp)
-; RV64I-NEXT: sd a0, 16(sp)
-; RV64I-NEXT: sd a5, 24(sp)
-; RV64I-NEXT: srli a0, a1, 3
-; RV64I-NEXT: andi a3, a1, 63
-; RV64I-NEXT: andi a0, a0, 24
-; RV64I-NEXT: xori a3, a3, 63
-; RV64I-NEXT: add a0, a6, a0
-; RV64I-NEXT: ld a4, 8(a0)
-; RV64I-NEXT: ld a5, 16(a0)
-; RV64I-NEXT: ld a6, 0(a0)
-; RV64I-NEXT: ld a0, 24(a0)
-; RV64I-NEXT: srl a7, a4, a1
+; RV64I-NEXT: sd a5, 16(sp)
+; RV64I-NEXT: sd a1, 24(sp)
+; RV64I-NEXT: ld a1, 8(s2)
+; RV64I-NEXT: ld a3, 16(s2)
+; RV64I-NEXT: ld a4, 0(s2)
+; RV64I-NEXT: ld a5, 24(s2)
+; RV64I-NEXT: srl a6, a1, a0
+; RV64I-NEXT: slli a7, a3, 1
+; RV64I-NEXT: srl a4, a4, a0
+; RV64I-NEXT: slli a1, a1, 1
+; RV64I-NEXT: srl a3, a3, a0
; RV64I-NEXT: slli t0, a5, 1
-; RV64I-NEXT: srl a6, a6, a1
-; RV64I-NEXT: slli a4, a4, 1
-; RV64I-NEXT: srl a5, a5, a1
-; RV64I-NEXT: slli t1, a0, 1
-; RV64I-NEXT: srl t2, a0, a1
-; RV64I-NEXT: sll a0, t0, a3
-; RV64I-NEXT: sll a1, a4, a3
-; RV64I-NEXT: sll a3, t1, a3
-; RV64I-NEXT: srli a4, t2, 56
-; RV64I-NEXT: srli t0, t2, 48
-; RV64I-NEXT: srli t1, t2, 40
-; RV64I-NEXT: srli t3, t2, 32
-; RV64I-NEXT: srli t4, t2, 24
-; RV64I-NEXT: srli t5, t2, 16
-; RV64I-NEXT: srli t6, t2, 8
-; RV64I-NEXT: or a0, a7, a0
-; RV64I-NEXT: or a1, a6, a1
-; RV64I-NEXT: or a3, a5, a3
+; RV64I-NEXT: srl a5, a5, a0
+; RV64I-NEXT: sll a0, a7, s5
+; RV64I-NEXT: sll a1, a1, s5
+; RV64I-NEXT: sll a7, t0, s5
+; RV64I-NEXT: srli t0, a5, 56
+; RV64I-NEXT: srli t1, a5, 48
+; RV64I-NEXT: srli t2, a5, 40
+; RV64I-NEXT: srli t3, a5, 32
+; RV64I-NEXT: srli t4, a5, 24
+; RV64I-NEXT: srli t5, a5, 16
+; RV64I-NEXT: srli t6, a5, 8
+; RV64I-NEXT: or a0, a6, a0
+; RV64I-NEXT: or a1, a4, a1
+; RV64I-NEXT: or a3, a3, a7
; RV64I-NEXT: sb t3, 28(a2)
-; RV64I-NEXT: sb t1, 29(a2)
-; RV64I-NEXT: sb t0, 30(a2)
-; RV64I-NEXT: sb a4, 31(a2)
-; RV64I-NEXT: sb t2, 24(a2)
+; RV64I-NEXT: sb t2, 29(a2)
+; RV64I-NEXT: sb t1, 30(a2)
+; RV64I-NEXT: sb t0, 31(a2)
+; RV64I-NEXT: sb a5, 24(a2)
; RV64I-NEXT: sb t6, 25(a2)
; RV64I-NEXT: sb t5, 26(a2)
; RV64I-NEXT: sb t4, 27(a2)
@@ -1513,19 +1463,17 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: sb a1, 9(a2)
; RV64I-NEXT: sb a5, 10(a2)
; RV64I-NEXT: sb a3, 11(a2)
-; RV64I-NEXT: ld s0, 152(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 144(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 136(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 128(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s4, 120(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 112(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s6, 104(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s7, 96(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s8, 88(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s9, 80(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s10, 72(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s11, 64(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 160
+; RV64I-NEXT: ld s0, 136(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 128(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 120(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 112(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 104(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s5, 96(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s6, 88(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s7, 80(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s8, 72(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s9, 64(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 144
; RV64I-NEXT: ret
;
; RV32I-LABEL: lshr_32bytes:
@@ -1550,67 +1498,55 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: lbu a7, 3(a0)
; RV32I-NEXT: lbu a5, 4(a0)
; RV32I-NEXT: lbu t0, 5(a0)
-; RV32I-NEXT: lbu t1, 6(a0)
-; RV32I-NEXT: lbu t2, 7(a0)
-; RV32I-NEXT: lbu t3, 8(a0)
-; RV32I-NEXT: lbu t4, 9(a0)
-; RV32I-NEXT: lbu t5, 10(a0)
-; RV32I-NEXT: lbu t6, 11(a0)
-; RV32I-NEXT: lbu s0, 12(a0)
-; RV32I-NEXT: lbu s2, 13(a0)
-; RV32I-NEXT: lbu s4, 14(a0)
-; RV32I-NEXT: lbu s5, 15(a0)
-; RV32I-NEXT: lbu s6, 16(a0)
-; RV32I-NEXT: lbu s7, 17(a0)
-; RV32I-NEXT: lbu s8, 18(a0)
-; RV32I-NEXT: lbu s9, 19(a0)
+; RV32I-NEXT: lbu t3, 6(a0)
+; RV32I-NEXT: lbu t6, 7(a0)
+; RV32I-NEXT: lbu s2, 8(a0)
+; RV32I-NEXT: lbu s3, 9(a0)
+; RV32I-NEXT: lbu s4, 10(a0)
+; RV32I-NEXT: lbu s5, 11(a0)
+; RV32I-NEXT: lbu s7, 12(a0)
+; RV32I-NEXT: lbu s8, 13(a0)
+; RV32I-NEXT: lbu s9, 14(a0)
+; RV32I-NEXT: lbu s10, 15(a0)
+; RV32I-NEXT: lbu s11, 16(a0)
+; RV32I-NEXT: lbu ra, 17(a0)
+; RV32I-NEXT: lbu t4, 18(a0)
+; RV32I-NEXT: lbu s0, 19(a0)
; RV32I-NEXT: slli a4, a4, 8
; RV32I-NEXT: slli a6, a6, 16
; RV32I-NEXT: slli a7, a7, 24
; RV32I-NEXT: or a3, a4, a3
-; RV32I-NEXT: sw a3, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: or a4, a7, a6
-; RV32I-NEXT: lbu s10, 20(a0)
-; RV32I-NEXT: lbu s11, 21(a0)
-; RV32I-NEXT: lbu ra, 22(a0)
-; RV32I-NEXT: lbu a3, 23(a0)
+; RV32I-NEXT: lbu t1, 20(a0)
+; RV32I-NEXT: lbu t2, 21(a0)
+; RV32I-NEXT: lbu t5, 22(a0)
+; RV32I-NEXT: lbu s1, 23(a0)
; RV32I-NEXT: slli t0, t0, 8
-; RV32I-NEXT: slli t1, t1, 16
-; RV32I-NEXT: slli t2, t2, 24
-; RV32I-NEXT: slli t4, t4, 8
-; RV32I-NEXT: slli t5, t5, 16
+; RV32I-NEXT: slli t3, t3, 16
; RV32I-NEXT: slli t6, t6, 24
-; RV32I-NEXT: or a5, t0, a5
-; RV32I-NEXT: or a6, t2, t1
-; RV32I-NEXT: or a7, t4, t3
-; RV32I-NEXT: or t0, t6, t5
-; RV32I-NEXT: lbu s1, 24(a0)
-; RV32I-NEXT: lbu s3, 25(a0)
-; RV32I-NEXT: lbu t4, 26(a0)
-; RV32I-NEXT: lbu t5, 27(a0)
-; RV32I-NEXT: slli s2, s2, 8
+; RV32I-NEXT: slli s3, s3, 8
; RV32I-NEXT: slli s4, s4, 16
; RV32I-NEXT: slli s5, s5, 24
-; RV32I-NEXT: slli s7, s7, 8
-; RV32I-NEXT: or t1, s2, s0
-; RV32I-NEXT: or t2, s5, s4
-; RV32I-NEXT: or t3, s7, s6
-; RV32I-NEXT: lbu t6, 28(a0)
-; RV32I-NEXT: lbu s4, 29(a0)
-; RV32I-NEXT: lbu s5, 30(a0)
-; RV32I-NEXT: lbu s6, 31(a0)
-; RV32I-NEXT: slli s8, s8, 16
-; RV32I-NEXT: slli s9, s9, 24
-; RV32I-NEXT: slli s11, s11, 8
-; RV32I-NEXT: slli ra, ra, 16
-; RV32I-NEXT: slli a3, a3, 24
-; RV32I-NEXT: or a0, s9, s8
-; RV32I-NEXT: or s0, s11, s10
-; RV32I-NEXT: or s2, a3, ra
-; RV32I-NEXT: lbu a3, 0(a1)
-; RV32I-NEXT: lbu s7, 1(a1)
-; RV32I-NEXT: lbu s8, 2(a1)
-; RV32I-NEXT: lbu a1, 3(a1)
+; RV32I-NEXT: or a5, t0, a5
+; RV32I-NEXT: or a6, t6, t3
+; RV32I-NEXT: or a7, s3, s2
+; RV32I-NEXT: or t0, s5, s4
+; RV32I-NEXT: lbu t3, 24(a0)
+; RV32I-NEXT: lbu s5, 25(a0)
+; RV32I-NEXT: lbu s6, 26(a0)
+; RV32I-NEXT: lbu t6, 27(a0)
+; RV32I-NEXT: slli s8, s8, 8
+; RV32I-NEXT: slli s9, s9, 16
+; RV32I-NEXT: slli s10, s10, 24
+; RV32I-NEXT: slli ra, ra, 8
+; RV32I-NEXT: or s7, s8, s7
+; RV32I-NEXT: or s2, s10, s9
+; RV32I-NEXT: or s3, ra, s11
+; RV32I-NEXT: lbu s4, 28(a0)
+; RV32I-NEXT: lbu s8, 29(a0)
+; RV32I-NEXT: lbu s9, 30(a0)
+; RV32I-NEXT: lbu s10, 31(a0)
+; RV32I-NEXT: lbu a0, 0(a1)
; RV32I-NEXT: sw zero, 56(sp)
; RV32I-NEXT: sw zero, 60(sp)
; RV32I-NEXT: sw zero, 64(sp)
@@ -1619,89 +1555,90 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: sw zero, 44(sp)
; RV32I-NEXT: sw zero, 48(sp)
; RV32I-NEXT: sw zero, 52(sp)
-; RV32I-NEXT: slli s3, s3, 8
-; RV32I-NEXT: or s1, s3, s1
-; RV32I-NEXT: addi s3, sp, 8
; RV32I-NEXT: slli t4, t4, 16
-; RV32I-NEXT: slli t5, t5, 24
-; RV32I-NEXT: slli s4, s4, 8
-; RV32I-NEXT: slli s5, s5, 16
-; RV32I-NEXT: slli s6, s6, 24
-; RV32I-NEXT: slli s7, s7, 8
-; RV32I-NEXT: slli s8, s8, 16
-; RV32I-NEXT: slli a1, a1, 24
-; RV32I-NEXT: or t4, t5, t4
-; RV32I-NEXT: or t5, s4, t6
-; RV32I-NEXT: or t6, s6, s5
-; RV32I-NEXT: or a3, s7, a3
-; RV32I-NEXT: or a1, a1, s8
-; RV32I-NEXT: lw s4, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT: or a4, a4, s4
-; RV32I-NEXT: or a5, a6, a5
-; RV32I-NEXT: or a6, t0, a7
-; RV32I-NEXT: or a7, t2, t1
-; RV32I-NEXT: or t0, a0, t3
-; RV32I-NEXT: or t1, s2, s0
-; RV32I-NEXT: or t2, t4, s1
-; RV32I-NEXT: or t3, t6, t5
-; RV32I-NEXT: or a0, a1, a3
-; RV32I-NEXT: sw t0, 24(sp)
-; RV32I-NEXT: sw t1, 28(sp)
-; RV32I-NEXT: sw t2, 32(sp)
-; RV32I-NEXT: sw t3, 36(sp)
-; RV32I-NEXT: sw a4, 8(sp)
-; RV32I-NEXT: sw a5, 12(sp)
-; RV32I-NEXT: sw a6, 16(sp)
-; RV32I-NEXT: sw a7, 20(sp)
+; RV32I-NEXT: slli s0, s0, 24
+; RV32I-NEXT: or t4, s0, t4
+; RV32I-NEXT: addi s0, sp, 8
+; RV32I-NEXT: slli t2, t2, 8
+; RV32I-NEXT: slli t5, t5, 16
+; RV32I-NEXT: slli s1, s1, 24
+; RV32I-NEXT: slli s5, s5, 8
+; RV32I-NEXT: slli s6, s6, 16
+; RV32I-NEXT: slli t6, t6, 24
+; RV32I-NEXT: slli s8, s8, 8
+; RV32I-NEXT: slli s9, s9, 16
+; RV32I-NEXT: slli s10, s10, 24
+; RV32I-NEXT: or t1, t2, t1
; RV32I-NEXT: srli a1, a0, 3
-; RV32I-NEXT: andi a3, a0, 31
-; RV32I-NEXT: andi a4, a1, 28
-; RV32I-NEXT: xori a1, a3, 31
-; RV32I-NEXT: add a4, s3, a4
-; RV32I-NEXT: lw a3, 0(a4)
-; RV32I-NEXT: lw a5, 4(a4)
-; RV32I-NEXT: lw a6, 8(a4)
-; RV32I-NEXT: lw a7, 12(a4)
-; RV32I-NEXT: lw t0, 16(a4)
-; RV32I-NEXT: lw t1, 20(a4)
-; RV32I-NEXT: lw t2, 24(a4)
-; RV32I-NEXT: lw a4, 28(a4)
-; RV32I-NEXT: srl t3, a5, a0
-; RV32I-NEXT: slli t4, a6, 1
+; RV32I-NEXT: or t2, s1, t5
+; RV32I-NEXT: andi t5, a0, 31
+; RV32I-NEXT: or t3, s5, t3
+; RV32I-NEXT: or t6, t6, s6
+; RV32I-NEXT: or s1, s8, s4
+; RV32I-NEXT: or s4, s10, s9
+; RV32I-NEXT: andi s5, a1, 28
+; RV32I-NEXT: xori a1, t5, 31
+; RV32I-NEXT: or a3, a4, a3
+; RV32I-NEXT: or a4, a6, a5
+; RV32I-NEXT: or a5, t0, a7
+; RV32I-NEXT: or a6, s2, s7
+; RV32I-NEXT: or a7, t4, s3
+; RV32I-NEXT: or t0, t2, t1
+; RV32I-NEXT: or t1, t6, t3
+; RV32I-NEXT: or t2, s4, s1
+; RV32I-NEXT: add s0, s0, s5
+; RV32I-NEXT: sw a7, 24(sp)
+; RV32I-NEXT: sw t0, 28(sp)
+; RV32I-NEXT: sw t1, 32(sp)
+; RV32I-NEXT: sw t2, 36(sp)
+; RV32I-NEXT: sw a3, 8(sp)
+; RV32I-NEXT: sw a4, 12(sp)
+; RV32I-NEXT: sw a5, 16(sp)
+; RV32I-NEXT: sw a6, 20(sp)
+; RV32I-NEXT: lw a3, 0(s0)
+; RV32I-NEXT: lw a4, 4(s0)
+; RV32I-NEXT: lw a5, 8(s0)
+; RV32I-NEXT: lw a6, 12(s0)
+; RV32I-NEXT: lw a7, 16(s0)
+; RV32I-NEXT: lw t0, 20(s0)
+; RV32I-NEXT: lw t1, 24(s0)
+; RV32I-NEXT: lw t2, 28(s0)
+; RV32I-NEXT: srl t3, a4, a0
+; RV32I-NEXT: slli t4, a5, 1
; RV32I-NEXT: srl a3, a3, a0
-; RV32I-NEXT: slli a5, a5, 1
-; RV32I-NEXT: srl t5, a7, a0
-; RV32I-NEXT: slli t6, t0, 1
-; RV32I-NEXT: srl a6, a6, a0
-; RV32I-NEXT: slli a7, a7, 1
-; RV32I-NEXT: srl s0, t1, a0
-; RV32I-NEXT: slli s1, t2, 1
-; RV32I-NEXT: srl t0, t0, a0
-; RV32I-NEXT: slli t1, t1, 1
+; RV32I-NEXT: slli a4, a4, 1
+; RV32I-NEXT: srl t5, a6, a0
+; RV32I-NEXT: slli t6, a7, 1
+; RV32I-NEXT: srl a5, a5, a0
+; RV32I-NEXT: slli a6, a6, 1
+; RV32I-NEXT: srl s0, t0, a0
+; RV32I-NEXT: slli s1, t1, 1
+; RV32I-NEXT: srl a7, a7, a0
+; RV32I-NEXT: slli t0, t0, 1
+; RV32I-NEXT: srl t1, t1, a0
+; RV32I-NEXT: slli s2, t2, 1
; RV32I-NEXT: srl t2, t2, a0
-; RV32I-NEXT: slli s2, a4, 1
-; RV32I-NEXT: srl s3, a4, a0
; RV32I-NEXT: sll a0, t4, a1
-; RV32I-NEXT: sll a4, a5, a1
-; RV32I-NEXT: sll a5, t6, a1
-; RV32I-NEXT: sll a7, a7, a1
-; RV32I-NEXT: sll t4, s1, a1
-; RV32I-NEXT: sll t1, t1, a1
-; RV32I-NEXT: sll t6, s2, a1
-; RV32I-NEXT: srli s1, s3, 24
-; RV32I-NEXT: srli s2, s3, 16
-; RV32I-NEXT: srli s4, s3, 8
+; RV32I-NEXT: sll a4, a4, a1
+; RV32I-NEXT: sll t4, t6, a1
+; RV32I-NEXT: sll a6, a6, a1
+; RV32I-NEXT: sll t6, s1, a1
+; RV32I-NEXT: sll t0, t0, a1
+; RV32I-NEXT: sll s1, s2, a1
+; RV32I-NEXT: srli s2, t2, 24
+; RV32I-NEXT: srli s3, t2, 16
+; RV32I-NEXT: srli s4, t2, 8
; RV32I-NEXT: or a0, t3, a0
; RV32I-NEXT: or a1, a3, a4
-; RV32I-NEXT: or a3, t5, a5
-; RV32I-NEXT: or a4, a6, a7
-; RV32I-NEXT: or a5, s0, t4
-; RV32I-NEXT: or a6, t0, t1
-; RV32I-NEXT: or a7, t2, t6
-; RV32I-NEXT: sb s3, 28(a2)
+; RV32I-NEXT: or a3, t5, t4
+; RV32I-NEXT: or a4, a5, a6
+; RV32I-NEXT: or a5, s0, t6
+; RV32I-NEXT: or a6, a7, t0
+; RV32I-NEXT: or a7, t1, s1
+; RV32I-NEXT: sb t2, 28(a2)
; RV32I-NEXT: sb s4, 29(a2)
-; RV32I-NEXT: sb s2, 30(a2)
-; RV32I-NEXT: sb s1, 31(a2)
+; RV32I-NEXT: sb s3, 30(a2)
+; RV32I-NEXT: sb s2, 31(a2)
; RV32I-NEXT: srli t0, a7, 24
; RV32I-NEXT: srli t1, a7, 16
; RV32I-NEXT: srli t2, a7, 8
@@ -1775,19 +1712,17 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-LABEL: shl_32bytes:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -160
-; RV64I-NEXT: sd s0, 152(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 144(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 136(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 128(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s4, 120(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s5, 112(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s6, 104(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s7, 96(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s8, 88(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s9, 80(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s10, 72(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s11, 64(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -144
+; RV64I-NEXT: sd s0, 136(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 128(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 120(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 112(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 104(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s5, 96(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s6, 88(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s7, 80(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s8, 72(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s9, 64(sp) # 8-byte Folded Spill
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: lbu a4, 1(a0)
; RV64I-NEXT: lbu a5, 2(a0)
@@ -1804,146 +1739,125 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: lbu s1, 13(a0)
; RV64I-NEXT: lbu s2, 14(a0)
; RV64I-NEXT: lbu s3, 15(a0)
+; RV64I-NEXT: slli a4, a4, 8
+; RV64I-NEXT: slli a5, a5, 16
+; RV64I-NEXT: slli a6, a6, 24
+; RV64I-NEXT: or a3, a4, a3
+; RV64I-NEXT: or a4, a6, a5
; RV64I-NEXT: lbu s4, 16(a0)
; RV64I-NEXT: lbu s5, 17(a0)
; RV64I-NEXT: lbu s6, 18(a0)
; RV64I-NEXT: lbu s7, 19(a0)
-; RV64I-NEXT: slli a4, a4, 8
-; RV64I-NEXT: slli s8, a5, 16
-; RV64I-NEXT: slli a6, a6, 24
; RV64I-NEXT: slli t0, t0, 8
; RV64I-NEXT: slli t1, t1, 16
; RV64I-NEXT: slli t2, t2, 24
-; RV64I-NEXT: or a5, a4, a3
-; RV64I-NEXT: or a6, a6, s8
-; RV64I-NEXT: or a3, t0, a7
-; RV64I-NEXT: or a4, t2, t1
-; RV64I-NEXT: lbu s8, 20(a0)
-; RV64I-NEXT: lbu s9, 21(a0)
-; RV64I-NEXT: lbu s10, 22(a0)
-; RV64I-NEXT: lbu s11, 23(a0)
; RV64I-NEXT: slli t4, t4, 8
; RV64I-NEXT: slli t5, t5, 16
; RV64I-NEXT: slli t6, t6, 24
+; RV64I-NEXT: or a5, t0, a7
+; RV64I-NEXT: or a6, t2, t1
+; RV64I-NEXT: or a7, t4, t3
+; RV64I-NEXT: or t0, t6, t5
+; RV64I-NEXT: lbu t5, 20(a0)
+; RV64I-NEXT: lbu t6, 21(a0)
+; RV64I-NEXT: lbu s8, 22(a0)
+; RV64I-NEXT: lbu s9, 23(a0)
; RV64I-NEXT: slli s1, s1, 8
; RV64I-NEXT: slli s2, s2, 16
; RV64I-NEXT: slli s3, s3, 24
-; RV64I-NEXT: or a7, t4, t3
-; RV64I-NEXT: or t0, t6, t5
-; RV64I-NEXT: or t1, s1, s0
-; RV64I-NEXT: or t2, s3, s2
-; RV64I-NEXT: lbu t6, 24(a0)
-; RV64I-NEXT: lbu s0, 25(a0)
-; RV64I-NEXT: lbu s1, 26(a0)
-; RV64I-NEXT: lbu s2, 27(a0)
; RV64I-NEXT: slli s5, s5, 8
; RV64I-NEXT: slli s6, s6, 16
; RV64I-NEXT: slli s7, s7, 24
-; RV64I-NEXT: slli s9, s9, 8
+; RV64I-NEXT: or t1, s1, s0
+; RV64I-NEXT: or t2, s3, s2
; RV64I-NEXT: or t3, s5, s4
; RV64I-NEXT: or t4, s7, s6
-; RV64I-NEXT: or t5, s9, s8
-; RV64I-NEXT: lbu s3, 28(a0)
+; RV64I-NEXT: lbu s0, 24(a0)
+; RV64I-NEXT: lbu s1, 25(a0)
+; RV64I-NEXT: lbu s2, 26(a0)
+; RV64I-NEXT: lbu s3, 27(a0)
+; RV64I-NEXT: slli t6, t6, 8
+; RV64I-NEXT: slli s8, s8, 16
+; RV64I-NEXT: slli s9, s9, 24
+; RV64I-NEXT: slli s1, s1, 8
+; RV64I-NEXT: or t5, t6, t5
+; RV64I-NEXT: or t6, s9, s8
+; RV64I-NEXT: or s0, s1, s0
+; RV64I-NEXT: lbu s1, 28(a0)
; RV64I-NEXT: lbu s4, 29(a0)
; RV64I-NEXT: lbu s5, 30(a0)
; RV64I-NEXT: lbu s6, 31(a0)
-; RV64I-NEXT: slli s10, s10, 16
-; RV64I-NEXT: slli s11, s11, 24
-; RV64I-NEXT: slli s0, s0, 8
-; RV64I-NEXT: slli s1, s1, 16
-; RV64I-NEXT: slli s2, s2, 24
-; RV64I-NEXT: slli s4, s4, 8
-; RV64I-NEXT: or a0, s11, s10
-; RV64I-NEXT: or t6, s0, t6
-; RV64I-NEXT: or s0, s2, s1
-; RV64I-NEXT: or s1, s4, s3
-; RV64I-NEXT: lbu s2, 0(a1)
-; RV64I-NEXT: lbu s3, 1(a1)
-; RV64I-NEXT: lbu s4, 2(a1)
-; RV64I-NEXT: lbu s7, 3(a1)
-; RV64I-NEXT: slli s5, s5, 16
-; RV64I-NEXT: slli s6, s6, 24
-; RV64I-NEXT: slli s3, s3, 8
-; RV64I-NEXT: slli s4, s4, 16
-; RV64I-NEXT: slli s7, s7, 24
-; RV64I-NEXT: or s5, s6, s5
-; RV64I-NEXT: or s2, s3, s2
-; RV64I-NEXT: or s3, s7, s4
-; RV64I-NEXT: lbu s4, 5(a1)
-; RV64I-NEXT: lbu s6, 4(a1)
-; RV64I-NEXT: lbu s7, 6(a1)
-; RV64I-NEXT: lbu a1, 7(a1)
-; RV64I-NEXT: slli s4, s4, 8
-; RV64I-NEXT: or s4, s4, s6
-; RV64I-NEXT: slli s7, s7, 16
-; RV64I-NEXT: slli a1, a1, 24
-; RV64I-NEXT: or a1, a1, s7
+; RV64I-NEXT: lbu a0, 0(a1)
; RV64I-NEXT: sd zero, 0(sp)
; RV64I-NEXT: sd zero, 8(sp)
; RV64I-NEXT: sd zero, 16(sp)
; RV64I-NEXT: sd zero, 24(sp)
-; RV64I-NEXT: or a5, a6, a5
-; RV64I-NEXT: addi a6, sp, 32
+; RV64I-NEXT: slli s2, s2, 16
+; RV64I-NEXT: slli s3, s3, 24
+; RV64I-NEXT: or a1, s3, s2
+; RV64I-NEXT: addi s2, sp, 32
+; RV64I-NEXT: slli s4, s4, 8
+; RV64I-NEXT: slli s5, s5, 16
+; RV64I-NEXT: slli s6, s6, 24
+; RV64I-NEXT: or s1, s4, s1
+; RV64I-NEXT: srli s3, a0, 3
+; RV64I-NEXT: or s4, s6, s5
+; RV64I-NEXT: andi s5, a0, 63
+; RV64I-NEXT: andi s3, s3, 24
; RV64I-NEXT: or a3, a4, a3
-; RV64I-NEXT: or a4, t0, a7
-; RV64I-NEXT: or a7, t2, t1
-; RV64I-NEXT: or t0, t4, t3
-; RV64I-NEXT: or a0, a0, t5
-; RV64I-NEXT: or t1, s0, t6
-; RV64I-NEXT: or t2, s5, s1
-; RV64I-NEXT: or t3, s3, s2
-; RV64I-NEXT: or a1, a1, s4
-; RV64I-NEXT: slli a3, a3, 32
-; RV64I-NEXT: slli a7, a7, 32
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: slli t2, t2, 32
-; RV64I-NEXT: slli a1, a1, 32
-; RV64I-NEXT: or a3, a3, a5
-; RV64I-NEXT: or a4, a7, a4
-; RV64I-NEXT: or a0, a0, t0
-; RV64I-NEXT: or a5, t2, t1
-; RV64I-NEXT: or a1, a1, t3
+; RV64I-NEXT: or a4, a6, a5
+; RV64I-NEXT: or a5, t0, a7
+; RV64I-NEXT: or a6, t2, t1
+; RV64I-NEXT: or a7, t4, t3
+; RV64I-NEXT: or t0, t6, t5
+; RV64I-NEXT: or a1, a1, s0
+; RV64I-NEXT: or t1, s4, s1
+; RV64I-NEXT: sub t2, s2, s3
+; RV64I-NEXT: slli a4, a4, 32
+; RV64I-NEXT: slli a6, a6, 32
+; RV64I-NEXT: slli t0, t0, 32
+; RV64I-NEXT: slli t1, t1, 32
+; RV64I-NEXT: or a3, a4, a3
+; RV64I-NEXT: or a4, a6, a5
+; RV64I-NEXT: or a5, t0, a7
+; RV64I-NEXT: or a1, t1, a1
; RV64I-NEXT: sd a3, 32(sp)
; RV64I-NEXT: sd a4, 40(sp)
-; RV64I-NEXT: sd a0, 48(sp)
-; RV64I-NEXT: sd a5, 56(sp)
-; RV64I-NEXT: srli a0, a1, 3
-; RV64I-NEXT: andi a3, a1, 63
-; RV64I-NEXT: andi a0, a0, 24
-; RV64I-NEXT: sub a0, a6, a0
-; RV64I-NEXT: ld a4, 0(a0)
-; RV64I-NEXT: ld a5, 8(a0)
-; RV64I-NEXT: ld a6, 16(a0)
-; RV64I-NEXT: ld a0, 24(a0)
-; RV64I-NEXT: xori a3, a3, 63
-; RV64I-NEXT: sll a7, a5, a1
-; RV64I-NEXT: srli t0, a4, 1
-; RV64I-NEXT: sll t1, a0, a1
-; RV64I-NEXT: srli a0, a6, 1
-; RV64I-NEXT: sll a6, a6, a1
-; RV64I-NEXT: srli a5, a5, 1
-; RV64I-NEXT: sll a4, a4, a1
-; RV64I-NEXT: srl a1, t0, a3
-; RV64I-NEXT: srl t0, a0, a3
-; RV64I-NEXT: srl a3, a5, a3
-; RV64I-NEXT: srli a5, a4, 56
-; RV64I-NEXT: srli t2, a4, 48
-; RV64I-NEXT: srli t3, a4, 40
-; RV64I-NEXT: srli t4, a4, 32
-; RV64I-NEXT: srli t5, a4, 24
-; RV64I-NEXT: srli t6, a4, 16
-; RV64I-NEXT: srli s0, a4, 8
-; RV64I-NEXT: or a0, a7, a1
-; RV64I-NEXT: or a1, t1, t0
-; RV64I-NEXT: or a3, a6, a3
-; RV64I-NEXT: sb t4, 4(a2)
-; RV64I-NEXT: sb t3, 5(a2)
-; RV64I-NEXT: sb t2, 6(a2)
-; RV64I-NEXT: sb a5, 7(a2)
-; RV64I-NEXT: sb a4, 0(a2)
-; RV64I-NEXT: sb s0, 1(a2)
-; RV64I-NEXT: sb t6, 2(a2)
-; RV64I-NEXT: sb t5, 3(a2)
+; RV64I-NEXT: sd a5, 48(sp)
+; RV64I-NEXT: sd a1, 56(sp)
+; RV64I-NEXT: ld a1, 0(t2)
+; RV64I-NEXT: ld a3, 8(t2)
+; RV64I-NEXT: ld a4, 16(t2)
+; RV64I-NEXT: ld a5, 24(t2)
+; RV64I-NEXT: xori a6, s5, 63
+; RV64I-NEXT: sll a7, a3, a0
+; RV64I-NEXT: srli t0, a1, 1
+; RV64I-NEXT: sll a5, a5, a0
+; RV64I-NEXT: srli t1, a4, 1
+; RV64I-NEXT: sll a4, a4, a0
+; RV64I-NEXT: srli a3, a3, 1
+; RV64I-NEXT: sll t2, a1, a0
+; RV64I-NEXT: srl a0, t0, a6
+; RV64I-NEXT: srl a1, t1, a6
+; RV64I-NEXT: srl a3, a3, a6
+; RV64I-NEXT: srli a6, t2, 56
+; RV64I-NEXT: srli t0, t2, 48
+; RV64I-NEXT: srli t1, t2, 40
+; RV64I-NEXT: srli t3, t2, 32
+; RV64I-NEXT: srli t4, t2, 24
+; RV64I-NEXT: srli t5, t2, 16
+; RV64I-NEXT: srli t6, t2, 8
+; RV64I-NEXT: or a0, a7, a0
+; RV64I-NEXT: or a1, a5, a1
+; RV64I-NEXT: or a3, a4, a3
+; RV64I-NEXT: sb t3, 4(a2)
+; RV64I-NEXT: sb t1, 5(a2)
+; RV64I-NEXT: sb t0, 6(a2)
+; RV64I-NEXT: sb a6, 7(a2)
+; RV64I-NEXT: sb t2, 0(a2)
+; RV64I-NEXT: sb t6, 1(a2)
+; RV64I-NEXT: sb t5, 2(a2)
+; RV64I-NEXT: sb t4, 3(a2)
; RV64I-NEXT: srli a4, a3, 56
; RV64I-NEXT: srli a5, a3, 48
; RV64I-NEXT: srli a6, a3, 40
@@ -1989,19 +1903,17 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: sb a1, 9(a2)
; RV64I-NEXT: sb a5, 10(a2)
; RV64I-NEXT: sb a3, 11(a2)
-; RV64I-NEXT: ld s0, 152(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 144(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 136(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 128(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s4, 120(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 112(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s6, 104(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s7, 96(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s8, 88(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s9, 80(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s10, 72(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s11, 64(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 160
+; RV64I-NEXT: ld s0, 136(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 128(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 120(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 112(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 104(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s5, 96(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s6, 88(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s7, 80(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s8, 72(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s9, 64(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 144
; RV64I-NEXT: ret
;
; RV32I-LABEL: shl_32bytes:
@@ -2026,67 +1938,55 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: lbu a7, 3(a0)
; RV32I-NEXT: lbu a5, 4(a0)
; RV32I-NEXT: lbu t0, 5(a0)
-; RV32I-NEXT: lbu t1, 6(a0)
-; RV32I-NEXT: lbu t2, 7(a0)
-; RV32I-NEXT: lbu t3, 8(a0)
-; RV32I-NEXT: lbu t4, 9(a0)
-; RV32I-NEXT: lbu t5, 10(a0)
-; RV32I-NEXT: lbu t6, 11(a0)
-; RV32I-NEXT: lbu s0, 12(a0)
-; RV32I-NEXT: lbu s2, 13(a0)
-; RV32I-NEXT: lbu s4, 14(a0)
-; RV32I-NEXT: lbu s5, 15(a0)
-; RV32I-NEXT: lbu s6, 16(a0)
-; RV32I-NEXT: lbu s7, 17(a0)
-; RV32I-NEXT: lbu s8, 18(a0)
-; RV32I-NEXT: lbu s9, 19(a0)
+; RV32I-NEXT: lbu t3, 6(a0)
+; RV32I-NEXT: lbu t6, 7(a0)
+; RV32I-NEXT: lbu s2, 8(a0)
+; RV32I-NEXT: lbu s3, 9(a0)
+; RV32I-NEXT: lbu s4, 10(a0)
+; RV32I-NEXT: lbu s5, 11(a0)
+; RV32I-NEXT: lbu s7, 12(a0)
+; RV32I-NEXT: lbu s8, 13(a0)
+; RV32I-NEXT: lbu s9, 14(a0)
+; RV32I-NEXT: lbu s10, 15(a0)
+; RV32I-NEXT: lbu s11, 16(a0)
+; RV32I-NEXT: lbu ra, 17(a0)
+; RV32I-NEXT: lbu t4, 18(a0)
+; RV32I-NEXT: lbu s0, 19(a0)
; RV32I-NEXT: slli a4, a4, 8
; RV32I-NEXT: slli a6, a6, 16
; RV32I-NEXT: slli a7, a7, 24
; RV32I-NEXT: or a3, a4, a3
-; RV32I-NEXT: sw a3, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: or a4, a7, a6
-; RV32I-NEXT: lbu s10, 20(a0)
-; RV32I-NEXT: lbu s11, 21(a0)
-; RV32I-NEXT: lbu ra, 22(a0)
-; RV32I-NEXT: lbu a3, 23(a0)
+; RV32I-NEXT: lbu t1, 20(a0)
+; RV32I-NEXT: lbu t2, 21(a0)
+; RV32I-NEXT: lbu t5, 22(a0)
+; RV32I-NEXT: lbu s1, 23(a0)
; RV32I-NEXT: slli t0, t0, 8
-; RV32I-NEXT: slli t1, t1, 16
-; RV32I-NEXT: slli t2, t2, 24
-; RV32I-NEXT: slli t4, t4, 8
-; RV32I-NEXT: slli t5, t5, 16
+; RV32I-NEXT: slli t3, t3, 16
; RV32I-NEXT: slli t6, t6, 24
-; RV32I-NEXT: or a5, t0, a5
-; RV32I-NEXT: or a6, t2, t1
-; RV32I-NEXT: or a7, t4, t3
-; RV32I-NEXT: or t0, t6, t5
-; RV32I-NEXT: lbu s1, 24(a0)
-; RV32I-NEXT: lbu s3, 25(a0)
-; RV32I-NEXT: lbu t4, 26(a0)
-; RV32I-NEXT: lbu t5, 27(a0)
-; RV32I-NEXT: slli s2, s2, 8
+; RV32I-NEXT: slli s3, s3, 8
; RV32I-NEXT: slli s4, s4, 16
; RV32I-NEXT: slli s5, s5, 24
-; RV32I-NEXT: slli s7, s7, 8
-; RV32I-NEXT: or t1, s2, s0
-; RV32I-NEXT: or t2, s5, s4
-; RV32I-NEXT: or t3, s7, s6
-; RV32I-NEXT: lbu t6, 28(a0)
-; RV32I-NEXT: lbu s4, 29(a0)
-; RV32I-NEXT: lbu s5, 30(a0)
-; RV32I-NEXT: lbu s6, 31(a0)
-; RV32I-NEXT: slli s8, s8, 16
-; RV32I-NEXT: slli s9, s9, 24
-; RV32I-NEXT: slli s11, s11, 8
-; RV32I-NEXT: slli ra, ra, 16
-; RV32I-NEXT: slli a3, a3, 24
-; RV32I-NEXT: or a0, s9, s8
-; RV32I-NEXT: or s0, s11, s10
-; RV32I-NEXT: or s2, a3, ra
-; RV32I-NEXT: lbu a3, 0(a1)
-; RV32I-NEXT: lbu s7, 1(a1)
-; RV32I-NEXT: lbu s8, 2(a1)
-; RV32I-NEXT: lbu a1, 3(a1)
+; RV32I-NEXT: or a5, t0, a5
+; RV32I-NEXT: or a6, t6, t3
+; RV32I-NEXT: or a7, s3, s2
+; RV32I-NEXT: or t0, s5, s4
+; RV32I-NEXT: lbu t3, 24(a0)
+; RV32I-NEXT: lbu s5, 25(a0)
+; RV32I-NEXT: lbu s6, 26(a0)
+; RV32I-NEXT: lbu t6, 27(a0)
+; RV32I-NEXT: slli s8, s8, 8
+; RV32I-NEXT: slli s9, s9, 16
+; RV32I-NEXT: slli s10, s10, 24
+; RV32I-NEXT: slli ra, ra, 8
+; RV32I-NEXT: or s7, s8, s7
+; RV32I-NEXT: or s2, s10, s9
+; RV32I-NEXT: or s3, ra, s11
+; RV32I-NEXT: lbu s4, 28(a0)
+; RV32I-NEXT: lbu s8, 29(a0)
+; RV32I-NEXT: lbu s9, 30(a0)
+; RV32I-NEXT: lbu s10, 31(a0)
+; RV32I-NEXT: lbu a0, 0(a1)
; RV32I-NEXT: sw zero, 24(sp)
; RV32I-NEXT: sw zero, 28(sp)
; RV32I-NEXT: sw zero, 32(sp)
@@ -2095,88 +1995,89 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: sw zero, 12(sp)
; RV32I-NEXT: sw zero, 16(sp)
; RV32I-NEXT: sw zero, 20(sp)
-; RV32I-NEXT: slli s3, s3, 8
-; RV32I-NEXT: or s1, s3, s1
-; RV32I-NEXT: addi s3, sp, 40
; RV32I-NEXT: slli t4, t4, 16
-; RV32I-NEXT: slli t5, t5, 24
-; RV32I-NEXT: slli s4, s4, 8
-; RV32I-NEXT: slli s5, s5, 16
-; RV32I-NEXT: slli s6, s6, 24
-; RV32I-NEXT: slli s7, s7, 8
-; RV32I-NEXT: slli s8, s8, 16
-; RV32I-NEXT: slli a1, a1, 24
-; RV32I-NEXT: or t4, t5, t4
-; RV32I-NEXT: or t5, s4, t6
-; RV32I-NEXT: or t6, s6, s5
-; RV32I-NEXT: or a3, s7, a3
-; RV32I-NEXT: or a1, a1, s8
-; RV32I-NEXT: lw s4, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT: or a4, a4, s4
-; RV32I-NEXT: or a5, a6, a5
-; RV32I-NEXT: or a6, t0, a7
-; RV32I-NEXT: or a7, t2, t1
-; RV32I-NEXT: or t0, a0, t3
-; RV32I-NEXT: or t1, s2, s0
-; RV32I-NEXT: or t2, t4, s1
-; RV32I-NEXT: or t3, t6, t5
-; RV32I-NEXT: or a0, a1, a3
-; RV32I-NEXT: sw t0, 56(sp)
-; RV32I-NEXT: sw t1, 60(sp)
-; RV32I-NEXT: sw t2, 64(sp)
-; RV32I-NEXT: sw t3, 68(sp)
-; RV32I-NEXT: sw a4, 40(sp)
-; RV32I-NEXT: sw a5, 44(sp)
-; RV32I-NEXT: sw a6, 48(sp)
-; RV32I-NEXT: sw a7, 52(sp)
+; RV32I-NEXT: slli s0, s0, 24
+; RV32I-NEXT: or t4, s0, t4
+; RV32I-NEXT: addi s0, sp, 40
+; RV32I-NEXT: slli t2, t2, 8
+; RV32I-NEXT: slli t5, t5, 16
+; RV32I-NEXT: slli s1, s1, 24
+; RV32I-NEXT: slli s5, s5, 8
+; RV32I-NEXT: slli s6, s6, 16
+; RV32I-NEXT: slli t6, t6, 24
+; RV32I-NEXT: slli s8, s8, 8
+; RV32I-NEXT: slli s9, s9, 16
+; RV32I-NEXT: slli s10, s10, 24
+; RV32I-NEXT: or t1, t2, t1
; RV32I-NEXT: srli a1, a0, 3
-; RV32I-NEXT: andi a3, a0, 31
-; RV32I-NEXT: andi a4, a1, 28
-; RV32I-NEXT: xori a1, a3, 31
-; RV32I-NEXT: sub a3, s3, a4
-; RV32I-NEXT: lw a4, 0(a3)
-; RV32I-NEXT: lw a5, 4(a3)
-; RV32I-NEXT: lw a6, 8(a3)
-; RV32I-NEXT: lw a7, 12(a3)
-; RV32I-NEXT: lw t0, 16(a3)
-; RV32I-NEXT: lw t1, 20(a3)
-; RV32I-NEXT: lw t2, 24(a3)
-; RV32I-NEXT: lw a3, 28(a3)
-; RV32I-NEXT: sll t3, a5, a0
-; RV32I-NEXT: srli t4, a4, 1
-; RV32I-NEXT: sll t5, a7, a0
-; RV32I-NEXT: srli t6, a6, 1
-; RV32I-NEXT: sll a6, a6, a0
-; RV32I-NEXT: srli a5, a5, 1
-; RV32I-NEXT: sll s0, t1, a0
-; RV32I-NEXT: srli s1, t0, 1
-; RV32I-NEXT: sll t0, t0, a0
-; RV32I-NEXT: srli a7, a7, 1
-; RV32I-NEXT: sll s2, a3, a0
-; RV32I-NEXT: srli a3, t2, 1
+; RV32I-NEXT: or t2, s1, t5
+; RV32I-NEXT: andi t5, a0, 31
+; RV32I-NEXT: or t3, s5, t3
+; RV32I-NEXT: or t6, t6, s6
+; RV32I-NEXT: or s1, s8, s4
+; RV32I-NEXT: or s4, s10, s9
+; RV32I-NEXT: andi s5, a1, 28
+; RV32I-NEXT: xori a1, t5, 31
+; RV32I-NEXT: or a3, a4, a3
+; RV32I-NEXT: or a4, a6, a5
+; RV32I-NEXT: or a5, t0, a7
+; RV32I-NEXT: or a6, s2, s7
+; RV32I-NEXT: or a7, t4, s3
+; RV32I-NEXT: or t0, t2, t1
+; RV32I-NEXT: or t1, t6, t3
+; RV32I-NEXT: or t2, s4, s1
+; RV32I-NEXT: sub t3, s0, s5
+; RV32I-NEXT: sw a7, 56(sp)
+; RV32I-NEXT: sw t0, 60(sp)
+; RV32I-NEXT: sw t1, 64(sp)
+; RV32I-NEXT: sw t2, 68(sp)
+; RV32I-NEXT: sw a3, 40(sp)
+; RV32I-NEXT: sw a4, 44(sp)
+; RV32I-NEXT: sw a5, 48(sp)
+; RV32I-NEXT: sw a6, 52(sp)
+; RV32I-NEXT: lw a3, 0(t3)
+; RV32I-NEXT: lw a4, 4(t3)
+; RV32I-NEXT: lw a5, 8(t3)
+; RV32I-NEXT: lw a6, 12(t3)
+; RV32I-NEXT: lw a7, 16(t3)
+; RV32I-NEXT: lw t0, 20(t3)
+; RV32I-NEXT: lw t1, 24(t3)
+; RV32I-NEXT: lw t2, 28(t3)
+; RV32I-NEXT: sll t3, a4, a0
+; RV32I-NEXT: srli t4, a3, 1
+; RV32I-NEXT: sll t5, a6, a0
+; RV32I-NEXT: srli t6, a5, 1
+; RV32I-NEXT: sll a5, a5, a0
+; RV32I-NEXT: srli a4, a4, 1
+; RV32I-NEXT: sll s0, t0, a0
+; RV32I-NEXT: srli s1, a7, 1
+; RV32I-NEXT: sll a7, a7, a0
+; RV32I-NEXT: srli a6, a6, 1
; RV32I-NEXT: sll t2, t2, a0
-; RV32I-NEXT: srli t1, t1, 1
-; RV32I-NEXT: sll s3, a4, a0
+; RV32I-NEXT: srli s2, t1, 1
+; RV32I-NEXT: sll t1, t1, a0
+; RV32I-NEXT: srli t0, t0, 1
+; RV32I-NEXT: sll s3, a3, a0
; RV32I-NEXT: srl a0, t4, a1
-; RV32I-NEXT: srl a4, t6, a1
-; RV32I-NEXT: srl a5, a5, a1
+; RV32I-NEXT: srl a3, t6, a1
+; RV32I-NEXT: srl a4, a4, a1
; RV32I-NEXT: srl t4, s1, a1
-; RV32I-NEXT: srl a7, a7, a1
-; RV32I-NEXT: srl t6, a3, a1
-; RV32I-NEXT: srl t1, t1, a1
+; RV32I-NEXT: srl a6, a6, a1
+; RV32I-NEXT: srl t6, s2, a1
+; RV32I-NEXT: srl t0, t0, a1
; RV32I-NEXT: srli s1, s3, 24
-; RV32I-NEXT: srli s4, s3, 16
-; RV32I-NEXT: srli s5, s3, 8
+; RV32I-NEXT: srli s2, s3, 16
+; RV32I-NEXT: srli s4, s3, 8
; RV32I-NEXT: or a0, t3, a0
-; RV32I-NEXT: or a1, t5, a4
-; RV32I-NEXT: or a3, a6, a5
+; RV32I-NEXT: or a1, t5, a3
+; RV32I-NEXT: or a3, a5, a4
; RV32I-NEXT: or a4, s0, t4
-; RV32I-NEXT: or a5, t0, a7
-; RV32I-NEXT: or a6, s2, t6
-; RV32I-NEXT: or a7, t2, t1
+; RV32I-NEXT: or a5, a7, a6
+; RV32I-NEXT: or a6, t2, t6
+; RV32I-NEXT: or a7, t1, t0
; RV32I-NEXT: sb s3, 0(a2)
-; RV32I-NEXT: sb s5, 1(a2)
-; RV32I-NEXT: sb s4, 2(a2)
+; RV32I-NEXT: sb s4, 1(a2)
+; RV32I-NEXT: sb s2, 2(a2)
; RV32I-NEXT: sb s1, 3(a2)
; RV32I-NEXT: srli t0, a7, 24
; RV32I-NEXT: srli t1, a7, 16
@@ -2251,19 +2152,17 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
define void @ashr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-LABEL: ashr_32bytes:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -160
-; RV64I-NEXT: sd s0, 152(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 144(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 136(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 128(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s4, 120(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s5, 112(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s6, 104(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s7, 96(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s8, 88(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s9, 80(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s10, 72(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s11, 64(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -144
+; RV64I-NEXT: sd s0, 136(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 128(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 120(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 112(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 104(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s5, 96(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s6, 88(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s7, 80(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s8, 72(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s9, 64(sp) # 8-byte Folded Spill
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: lbu a4, 1(a0)
; RV64I-NEXT: lbu a5, 2(a0)
@@ -2280,144 +2179,123 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: lbu s1, 13(a0)
; RV64I-NEXT: lbu s2, 14(a0)
; RV64I-NEXT: lbu s3, 15(a0)
+; RV64I-NEXT: slli a4, a4, 8
+; RV64I-NEXT: slli a5, a5, 16
+; RV64I-NEXT: slli a6, a6, 24
+; RV64I-NEXT: or a3, a4, a3
+; RV64I-NEXT: or a4, a6, a5
; RV64I-NEXT: lbu s4, 16(a0)
; RV64I-NEXT: lbu s5, 17(a0)
; RV64I-NEXT: lbu s6, 18(a0)
; RV64I-NEXT: lbu s7, 19(a0)
-; RV64I-NEXT: slli a4, a4, 8
-; RV64I-NEXT: slli a5, a5, 16
-; RV64I-NEXT: slli a6, a6, 24
; RV64I-NEXT: slli t0, t0, 8
; RV64I-NEXT: slli t1, t1, 16
; RV64I-NEXT: slli t2, t2, 24
-; RV64I-NEXT: or a3, a4, a3
-; RV64I-NEXT: or a4, a6, a5
-; RV64I-NEXT: or a5, t0, a7
-; RV64I-NEXT: or a6, t2, t1
-; RV64I-NEXT: lbu s8, 20(a0)
-; RV64I-NEXT: lbu s9, 21(a0)
-; RV64I-NEXT: lbu s10, 22(a0)
-; RV64I-NEXT: lbu s11, 23(a0)
; RV64I-NEXT: slli t4, t4, 8
; RV64I-NEXT: slli t5, t5, 16
; RV64I-NEXT: slli t6, t6, 24
+; RV64I-NEXT: or a5, t0, a7
+; RV64I-NEXT: or a6, t2, t1
+; RV64I-NEXT: or a7, t4, t3
+; RV64I-NEXT: or t0, t6, t5
+; RV64I-NEXT: lbu t5, 20(a0)
+; RV64I-NEXT: lbu t6, 21(a0)
+; RV64I-NEXT: lbu s8, 22(a0)
+; RV64I-NEXT: lbu s9, 23(a0)
; RV64I-NEXT: slli s1, s1, 8
; RV64I-NEXT: slli s2, s2, 16
; RV64I-NEXT: slli s3, s3, 24
-; RV64I-NEXT: or a7, t4, t3
-; RV64I-NEXT: or t0, t6, t5
-; RV64I-NEXT: or t1, s1, s0
-; RV64I-NEXT: or t2, s3, s2
-; RV64I-NEXT: lbu t6, 24(a0)
-; RV64I-NEXT: lbu s0, 25(a0)
-; RV64I-NEXT: lbu s1, 26(a0)
-; RV64I-NEXT: lbu s2, 27(a0)
; RV64I-NEXT: slli s5, s5, 8
; RV64I-NEXT: slli s6, s6, 16
; RV64I-NEXT: slli s7, s7, 24
-; RV64I-NEXT: slli s9, s9, 8
+; RV64I-NEXT: or t1, s1, s0
+; RV64I-NEXT: or t2, s3, s2
; RV64I-NEXT: or t3, s5, s4
; RV64I-NEXT: or t4, s7, s6
-; RV64I-NEXT: or t5, s9, s8
-; RV64I-NEXT: lbu s3, 28(a0)
+; RV64I-NEXT: lbu s0, 24(a0)
+; RV64I-NEXT: lbu s1, 25(a0)
+; RV64I-NEXT: lbu s2, 26(a0)
+; RV64I-NEXT: lbu s3, 27(a0)
+; RV64I-NEXT: slli t6, t6, 8
+; RV64I-NEXT: slli s8, s8, 16
+; RV64I-NEXT: slli s9, s9, 24
+; RV64I-NEXT: slli s1, s1, 8
+; RV64I-NEXT: or t5, t6, t5
+; RV64I-NEXT: or t6, s9, s8
+; RV64I-NEXT: or s0, s1, s0
+; RV64I-NEXT: lbu s1, 28(a0)
; RV64I-NEXT: lbu s4, 29(a0)
; RV64I-NEXT: lbu s5, 30(a0)
; RV64I-NEXT: lbu s6, 31(a0)
-; RV64I-NEXT: slli s10, s10, 16
-; RV64I-NEXT: slli s11, s11, 24
-; RV64I-NEXT: slli s0, s0, 8
-; RV64I-NEXT: slli s1, s1, 16
-; RV64I-NEXT: slli s2, s2, 24
+; RV64I-NEXT: lbu a0, 0(a1)
+; RV64I-NEXT: slli s2, s2, 16
+; RV64I-NEXT: slli s3, s3, 24
+; RV64I-NEXT: or a1, s3, s2
+; RV64I-NEXT: mv s2, sp
; RV64I-NEXT: slli s4, s4, 8
-; RV64I-NEXT: or a0, s11, s10
-; RV64I-NEXT: or t6, s0, t6
-; RV64I-NEXT: or s0, s2, s1
-; RV64I-NEXT: or s1, s4, s3
-; RV64I-NEXT: lbu s2, 0(a1)
-; RV64I-NEXT: lbu s3, 1(a1)
-; RV64I-NEXT: lbu s4, 2(a1)
-; RV64I-NEXT: lbu s7, 3(a1)
; RV64I-NEXT: slli s5, s5, 16
; RV64I-NEXT: slli s6, s6, 24
-; RV64I-NEXT: slli s3, s3, 8
-; RV64I-NEXT: slli s4, s4, 16
-; RV64I-NEXT: slli s7, s7, 24
-; RV64I-NEXT: or s5, s6, s5
-; RV64I-NEXT: or s2, s3, s2
-; RV64I-NEXT: or s3, s7, s4
-; RV64I-NEXT: lbu s4, 5(a1)
-; RV64I-NEXT: lbu s6, 4(a1)
-; RV64I-NEXT: lbu s7, 6(a1)
-; RV64I-NEXT: lbu a1, 7(a1)
-; RV64I-NEXT: slli s4, s4, 8
-; RV64I-NEXT: or s4, s4, s6
-; RV64I-NEXT: slli s7, s7, 16
-; RV64I-NEXT: slli a1, a1, 24
-; RV64I-NEXT: or a1, a1, s7
-; RV64I-NEXT: mv s6, sp
+; RV64I-NEXT: or s1, s4, s1
+; RV64I-NEXT: srli s3, a0, 3
+; RV64I-NEXT: or s4, s6, s5
+; RV64I-NEXT: andi s5, a0, 63
+; RV64I-NEXT: andi s3, s3, 24
+; RV64I-NEXT: xori s5, s5, 63
; RV64I-NEXT: or a3, a4, a3
; RV64I-NEXT: or a4, a6, a5
; RV64I-NEXT: or a5, t0, a7
; RV64I-NEXT: or a6, t2, t1
; RV64I-NEXT: or a7, t4, t3
-; RV64I-NEXT: or a0, a0, t5
-; RV64I-NEXT: or t0, s0, t6
-; RV64I-NEXT: or t1, s5, s1
-; RV64I-NEXT: or t2, s3, s2
-; RV64I-NEXT: or a1, a1, s4
+; RV64I-NEXT: or t0, t6, t5
+; RV64I-NEXT: or a1, a1, s0
+; RV64I-NEXT: or t1, s4, s1
+; RV64I-NEXT: add s2, s2, s3
; RV64I-NEXT: slli a4, a4, 32
; RV64I-NEXT: slli a6, a6, 32
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: slli t3, t1, 32
-; RV64I-NEXT: slli a1, a1, 32
+; RV64I-NEXT: slli t0, t0, 32
+; RV64I-NEXT: slli t2, t1, 32
; RV64I-NEXT: sraiw t1, t1, 31
; RV64I-NEXT: or a3, a4, a3
; RV64I-NEXT: or a4, a6, a5
-; RV64I-NEXT: or a0, a0, a7
-; RV64I-NEXT: or a5, t3, t0
-; RV64I-NEXT: or a1, a1, t2
+; RV64I-NEXT: or a5, t0, a7
+; RV64I-NEXT: or a1, t2, a1
; RV64I-NEXT: sd t1, 32(sp)
; RV64I-NEXT: sd t1, 40(sp)
; RV64I-NEXT: sd t1, 48(sp)
; RV64I-NEXT: sd t1, 56(sp)
; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: sd a4, 8(sp)
-; RV64I-NEXT: sd a0, 16(sp)
-; RV64I-NEXT: sd a5, 24(sp)
-; RV64I-NEXT: srli a0, a1, 3
-; RV64I-NEXT: andi a3, a1, 63
-; RV64I-NEXT: andi a0, a0, 24
-; RV64I-NEXT: xori a3, a3, 63
-; RV64I-NEXT: add a0, s6, a0
-; RV64I-NEXT: ld a4, 8(a0)
-; RV64I-NEXT: ld a5, 16(a0)
-; RV64I-NEXT: ld a6, 0(a0)
-; RV64I-NEXT: ld a0, 24(a0)
-; RV64I-NEXT: srl a7, a4, a1
+; RV64I-NEXT: sd a5, 16(sp)
+; RV64I-NEXT: sd a1, 24(sp)
+; RV64I-NEXT: ld a1, 8(s2)
+; RV64I-NEXT: ld a3, 16(s2)
+; RV64I-NEXT: ld a4, 0(s2)
+; RV64I-NEXT: ld a5, 24(s2)
+; RV64I-NEXT: srl a6, a1, a0
+; RV64I-NEXT: slli a7, a3, 1
+; RV64I-NEXT: srl a4, a4, a0
+; RV64I-NEXT: slli a1, a1, 1
+; RV64I-NEXT: srl a3, a3, a0
; RV64I-NEXT: slli t0, a5, 1
-; RV64I-NEXT: srl a6, a6, a1
-; RV64I-NEXT: slli a4, a4, 1
-; RV64I-NEXT: srl a5, a5, a1
-; RV64I-NEXT: slli t1, a0, 1
-; RV64I-NEXT: sra t2, a0, a1
-; RV64I-NEXT: sll a0, t0, a3
-; RV64I-NEXT: sll a1, a4, a3
-; RV64I-NEXT: sll a3, t1, a3
-; RV64I-NEXT: srli a4, t2, 56
-; RV64I-NEXT: srli t0, t2, 48
-; RV64I-NEXT: srli t1, t2, 40
-; RV64I-NEXT: srli t3, t2, 32
-; RV64I-NEXT: srli t4, t2, 24
-; RV64I-NEXT: srli t5, t2, 16
-; RV64I-NEXT: srli t6, t2, 8
-; RV64I-NEXT: or a0, a7, a0
-; RV64I-NEXT: or a1, a6, a1
-; RV64I-NEXT: or a3, a5, a3
+; RV64I-NEXT: sra a5, a5, a0
+; RV64I-NEXT: sll a0, a7, s5
+; RV64I-NEXT: sll a1, a1, s5
+; RV64I-NEXT: sll a7, t0, s5
+; RV64I-NEXT: srli t0, a5, 56
+; RV64I-NEXT: srli t1, a5, 48
+; RV64I-NEXT: srli t2, a5, 40
+; RV64I-NEXT: srli t3, a5, 32
+; RV64I-NEXT: srli t4, a5, 24
+; RV64I-NEXT: srli t5, a5, 16
+; RV64I-NEXT: srli t6, a5, 8
+; RV64I-NEXT: or a0, a6, a0
+; RV64I-NEXT: or a1, a4, a1
+; RV64I-NEXT: or a3, a3, a7
; RV64I-NEXT: sb t3, 28(a2)
-; RV64I-NEXT: sb t1, 29(a2)
-; RV64I-NEXT: sb t0, 30(a2)
-; RV64I-NEXT: sb a4, 31(a2)
-; RV64I-NEXT: sb t2, 24(a2)
+; RV64I-NEXT: sb t2, 29(a2)
+; RV64I-NEXT: sb t1, 30(a2)
+; RV64I-NEXT: sb t0, 31(a2)
+; RV64I-NEXT: sb a5, 24(a2)
; RV64I-NEXT: sb t6, 25(a2)
; RV64I-NEXT: sb t5, 26(a2)
; RV64I-NEXT: sb t4, 27(a2)
@@ -2438,47 +2316,45 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: srli s3, a0, 56
; RV64I-NEXT: srli s4, a0, 48
; RV64I-NEXT: srli s5, a0, 40
-; RV64I-NEXT: srli s6, a0, 32
; RV64I-NEXT: sb a7, 20(a2)
; RV64I-NEXT: sb a6, 21(a2)
; RV64I-NEXT: sb a5, 22(a2)
; RV64I-NEXT: sb a4, 23(a2)
-; RV64I-NEXT: srli a4, a0, 24
+; RV64I-NEXT: srli a4, a0, 32
; RV64I-NEXT: sb a3, 16(a2)
; RV64I-NEXT: sb t2, 17(a2)
; RV64I-NEXT: sb t1, 18(a2)
; RV64I-NEXT: sb t0, 19(a2)
-; RV64I-NEXT: srli a3, a0, 16
+; RV64I-NEXT: srli a3, a0, 24
; RV64I-NEXT: sb t6, 4(a2)
; RV64I-NEXT: sb t5, 5(a2)
; RV64I-NEXT: sb t4, 6(a2)
; RV64I-NEXT: sb t3, 7(a2)
-; RV64I-NEXT: srli a5, a0, 8
+; RV64I-NEXT: srli a5, a0, 16
; RV64I-NEXT: sb a1, 0(a2)
; RV64I-NEXT: sb s2, 1(a2)
; RV64I-NEXT: sb s1, 2(a2)
; RV64I-NEXT: sb s0, 3(a2)
-; RV64I-NEXT: sb s6, 12(a2)
+; RV64I-NEXT: srli a1, a0, 8
+; RV64I-NEXT: sb a4, 12(a2)
; RV64I-NEXT: sb s5, 13(a2)
; RV64I-NEXT: sb s4, 14(a2)
; RV64I-NEXT: sb s3, 15(a2)
; RV64I-NEXT: sb a0, 8(a2)
-; RV64I-NEXT: sb a5, 9(a2)
-; RV64I-NEXT: sb a3, 10(a2)
-; RV64I-NEXT: sb a4, 11(a2)
-; RV64I-NEXT: ld s0, 152(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 144(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 136(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 128(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s4, 120(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 112(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s6, 104(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s7, 96(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s8, 88(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s9, 80(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s10, 72(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s11, 64(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 160
+; RV64I-NEXT: sb a1, 9(a2)
+; RV64I-NEXT: sb a5, 10(a2)
+; RV64I-NEXT: sb a3, 11(a2)
+; RV64I-NEXT: ld s0, 136(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 128(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 120(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 112(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 104(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s5, 96(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s6, 88(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s7, 80(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s8, 72(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s9, 64(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 144
; RV64I-NEXT: ret
;
; RV32I-LABEL: ashr_32bytes:
@@ -2503,159 +2379,148 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: lbu a7, 3(a0)
; RV32I-NEXT: lbu a5, 4(a0)
; RV32I-NEXT: lbu t0, 5(a0)
-; RV32I-NEXT: lbu t1, 6(a0)
-; RV32I-NEXT: lbu t2, 7(a0)
-; RV32I-NEXT: lbu t3, 8(a0)
-; RV32I-NEXT: lbu t4, 9(a0)
-; RV32I-NEXT: lbu t5, 10(a0)
-; RV32I-NEXT: lbu t6, 11(a0)
-; RV32I-NEXT: lbu s0, 12(a0)
-; RV32I-NEXT: lbu s1, 13(a0)
-; RV32I-NEXT: lbu s2, 14(a0)
-; RV32I-NEXT: lbu s3, 15(a0)
-; RV32I-NEXT: lbu s4, 16(a0)
-; RV32I-NEXT: lbu s5, 17(a0)
-; RV32I-NEXT: lbu s6, 18(a0)
-; RV32I-NEXT: lbu s7, 19(a0)
+; RV32I-NEXT: lbu t3, 6(a0)
+; RV32I-NEXT: lbu t4, 7(a0)
+; RV32I-NEXT: lbu t6, 8(a0)
+; RV32I-NEXT: lbu s0, 9(a0)
+; RV32I-NEXT: lbu s4, 10(a0)
+; RV32I-NEXT: lbu s5, 11(a0)
+; RV32I-NEXT: lbu s6, 12(a0)
+; RV32I-NEXT: lbu s7, 13(a0)
+; RV32I-NEXT: lbu s8, 14(a0)
+; RV32I-NEXT: lbu s9, 15(a0)
+; RV32I-NEXT: lbu s10, 16(a0)
+; RV32I-NEXT: lbu s11, 17(a0)
+; RV32I-NEXT: lbu s2, 18(a0)
+; RV32I-NEXT: lbu s3, 19(a0)
; RV32I-NEXT: slli a4, a4, 8
; RV32I-NEXT: slli a6, a6, 16
; RV32I-NEXT: slli a7, a7, 24
; RV32I-NEXT: or a3, a4, a3
-; RV32I-NEXT: sw a3, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: or a4, a7, a6
-; RV32I-NEXT: lbu s8, 20(a0)
-; RV32I-NEXT: lbu s9, 21(a0)
-; RV32I-NEXT: lbu s10, 22(a0)
-; RV32I-NEXT: lbu s11, 23(a0)
+; RV32I-NEXT: lbu t1, 20(a0)
+; RV32I-NEXT: lbu t2, 21(a0)
+; RV32I-NEXT: lbu t5, 22(a0)
+; RV32I-NEXT: lbu s1, 23(a0)
; RV32I-NEXT: slli t0, t0, 8
-; RV32I-NEXT: slli t1, t1, 16
-; RV32I-NEXT: slli t2, t2, 24
-; RV32I-NEXT: slli t4, t4, 8
-; RV32I-NEXT: slli t5, t5, 16
-; RV32I-NEXT: slli t6, t6, 24
+; RV32I-NEXT: slli t3, t3, 16
+; RV32I-NEXT: slli t4, t4, 24
+; RV32I-NEXT: slli s0, s0, 8
+; RV32I-NEXT: slli s4, s4, 16
+; RV32I-NEXT: slli s5, s5, 24
; RV32I-NEXT: or a5, t0, a5
-; RV32I-NEXT: or a6, t2, t1
-; RV32I-NEXT: or a7, t4, t3
-; RV32I-NEXT: or t0, t6, t5
-; RV32I-NEXT: lbu ra, 24(a0)
-; RV32I-NEXT: lbu a3, 25(a0)
-; RV32I-NEXT: lbu t4, 26(a0)
-; RV32I-NEXT: lbu t5, 27(a0)
-; RV32I-NEXT: slli s1, s1, 8
+; RV32I-NEXT: or a6, t4, t3
+; RV32I-NEXT: or a7, s0, t6
+; RV32I-NEXT: or t0, s5, s4
+; RV32I-NEXT: lbu t3, 24(a0)
+; RV32I-NEXT: lbu s4, 25(a0)
+; RV32I-NEXT: lbu s5, 26(a0)
+; RV32I-NEXT: lbu ra, 27(a0)
+; RV32I-NEXT: slli s7, s7, 8
+; RV32I-NEXT: slli s8, s8, 16
+; RV32I-NEXT: slli s9, s9, 24
+; RV32I-NEXT: slli s11, s11, 8
+; RV32I-NEXT: or t4, s7, s6
+; RV32I-NEXT: or t6, s9, s8
+; RV32I-NEXT: or s0, s11, s10
+; RV32I-NEXT: lbu s6, 28(a0)
+; RV32I-NEXT: lbu s7, 29(a0)
+; RV32I-NEXT: lbu s8, 30(a0)
+; RV32I-NEXT: lbu s9, 31(a0)
+; RV32I-NEXT: lbu a0, 0(a1)
; RV32I-NEXT: slli s2, s2, 16
; RV32I-NEXT: slli s3, s3, 24
-; RV32I-NEXT: slli s5, s5, 8
-; RV32I-NEXT: or t1, s1, s0
-; RV32I-NEXT: or t2, s3, s2
-; RV32I-NEXT: or t3, s5, s4
-; RV32I-NEXT: lbu t6, 28(a0)
-; RV32I-NEXT: lbu s0, 29(a0)
-; RV32I-NEXT: lbu s1, 30(a0)
-; RV32I-NEXT: lbu a0, 31(a0)
-; RV32I-NEXT: slli s6, s6, 16
-; RV32I-NEXT: slli s7, s7, 24
-; RV32I-NEXT: slli s9, s9, 8
-; RV32I-NEXT: slli s10, s10, 16
-; RV32I-NEXT: slli s11, s11, 24
-; RV32I-NEXT: or s2, s7, s6
-; RV32I-NEXT: or s3, s9, s8
-; RV32I-NEXT: or s4, s11, s10
-; RV32I-NEXT: lbu s5, 0(a1)
-; RV32I-NEXT: lbu s6, 1(a1)
-; RV32I-NEXT: lbu s7, 2(a1)
-; RV32I-NEXT: lbu a1, 3(a1)
-; RV32I-NEXT: slli a3, a3, 8
-; RV32I-NEXT: or a3, a3, ra
-; RV32I-NEXT: addi s8, sp, 8
-; RV32I-NEXT: slli t4, t4, 16
-; RV32I-NEXT: slli t5, t5, 24
-; RV32I-NEXT: slli s0, s0, 8
-; RV32I-NEXT: slli s1, s1, 16
-; RV32I-NEXT: slli a0, a0, 24
-; RV32I-NEXT: slli s6, s6, 8
-; RV32I-NEXT: slli s7, s7, 16
-; RV32I-NEXT: slli a1, a1, 24
-; RV32I-NEXT: or t4, t5, t4
-; RV32I-NEXT: or t5, s0, t6
-; RV32I-NEXT: or s1, a0, s1
-; RV32I-NEXT: or t6, s6, s5
-; RV32I-NEXT: or a1, a1, s7
-; RV32I-NEXT: srai s0, a0, 31
-; RV32I-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT: or a4, a4, a0
-; RV32I-NEXT: or a5, a6, a5
-; RV32I-NEXT: or a6, t0, a7
-; RV32I-NEXT: or a7, t2, t1
-; RV32I-NEXT: or t0, s2, t3
-; RV32I-NEXT: or t1, s4, s3
-; RV32I-NEXT: or a3, t4, a3
+; RV32I-NEXT: or s2, s3, s2
+; RV32I-NEXT: addi s3, sp, 8
+; RV32I-NEXT: slli t2, t2, 8
+; RV32I-NEXT: slli t5, t5, 16
+; RV32I-NEXT: slli s1, s1, 24
+; RV32I-NEXT: slli s4, s4, 8
+; RV32I-NEXT: slli s5, s5, 16
+; RV32I-NEXT: slli ra, ra, 24
+; RV32I-NEXT: slli s7, s7, 8
+; RV32I-NEXT: slli s8, s8, 16
+; RV32I-NEXT: slli s9, s9, 24
+; RV32I-NEXT: or t1, t2, t1
+; RV32I-NEXT: srli a1, a0, 3
; RV32I-NEXT: or t2, s1, t5
-; RV32I-NEXT: or a0, a1, t6
-; RV32I-NEXT: sw s0, 56(sp)
-; RV32I-NEXT: sw s0, 60(sp)
-; RV32I-NEXT: sw s0, 64(sp)
-; RV32I-NEXT: sw s0, 68(sp)
-; RV32I-NEXT: sw s0, 40(sp)
-; RV32I-NEXT: sw s0, 44(sp)
-; RV32I-NEXT: sw s0, 48(sp)
-; RV32I-NEXT: sw s0, 52(sp)
-; RV32I-NEXT: sw t0, 24(sp)
-; RV32I-NEXT: sw t1, 28(sp)
-; RV32I-NEXT: sw a3, 32(sp)
+; RV32I-NEXT: andi t5, a0, 31
+; RV32I-NEXT: or t3, s4, t3
+; RV32I-NEXT: or s1, ra, s5
+; RV32I-NEXT: or s4, s7, s6
+; RV32I-NEXT: or s5, s9, s8
+; RV32I-NEXT: srai s6, s9, 31
+; RV32I-NEXT: andi s7, a1, 28
+; RV32I-NEXT: xori a1, t5, 31
+; RV32I-NEXT: or a3, a4, a3
+; RV32I-NEXT: or a4, a6, a5
+; RV32I-NEXT: or a5, t0, a7
+; RV32I-NEXT: or a6, t6, t4
+; RV32I-NEXT: or a7, s2, s0
+; RV32I-NEXT: or t0, t2, t1
+; RV32I-NEXT: or t1, s1, t3
+; RV32I-NEXT: or t2, s5, s4
+; RV32I-NEXT: sw s6, 56(sp)
+; RV32I-NEXT: sw s6, 60(sp)
+; RV32I-NEXT: sw s6, 64(sp)
+; RV32I-NEXT: sw s6, 68(sp)
+; RV32I-NEXT: sw s6, 40(sp)
+; RV32I-NEXT: sw s6, 44(sp)
+; RV32I-NEXT: sw s6, 48(sp)
+; RV32I-NEXT: sw s6, 52(sp)
+; RV32I-NEXT: add s3, s3, s7
+; RV32I-NEXT: sw a7, 24(sp)
+; RV32I-NEXT: sw t0, 28(sp)
+; RV32I-NEXT: sw t1, 32(sp)
; RV32I-NEXT: sw t2, 36(sp)
-; RV32I-NEXT: sw a4, 8(sp)
-; RV32I-NEXT: sw a5, 12(sp)
-; RV32I-NEXT: sw a6, 16(sp)
-; RV32I-NEXT: sw a7, 20(sp)
-; RV32I-NEXT: srli a1, a0, 3
-; RV32I-NEXT: andi a3, a0, 31
-; RV32I-NEXT: andi a4, a1, 28
-; RV32I-NEXT: xori a1, a3, 31
-; RV32I-NEXT: add a4, s8, a4
-; RV32I-NEXT: lw a3, 0(a4)
-; RV32I-NEXT: lw a5, 4(a4)
-; RV32I-NEXT: lw a6, 8(a4)
-; RV32I-NEXT: lw a7, 12(a4)
-; RV32I-NEXT: lw t0, 16(a4)
-; RV32I-NEXT: lw t1, 20(a4)
-; RV32I-NEXT: lw t2, 24(a4)
-; RV32I-NEXT: lw a4, 28(a4)
-; RV32I-NEXT: srl t3, a5, a0
-; RV32I-NEXT: slli t4, a6, 1
+; RV32I-NEXT: sw a3, 8(sp)
+; RV32I-NEXT: sw a4, 12(sp)
+; RV32I-NEXT: sw a5, 16(sp)
+; RV32I-NEXT: sw a6, 20(sp)
+; RV32I-NEXT: lw a3, 0(s3)
+; RV32I-NEXT: lw a4, 4(s3)
+; RV32I-NEXT: lw a5, 8(s3)
+; RV32I-NEXT: lw a6, 12(s3)
+; RV32I-NEXT: lw a7, 16(s3)
+; RV32I-NEXT: lw t0, 20(s3)
+; RV32I-NEXT: lw t1, 24(s3)
+; RV32I-NEXT: lw t2, 28(s3)
+; RV32I-NEXT: srl t3, a4, a0
+; RV32I-NEXT: slli t4, a5, 1
; RV32I-NEXT: srl a3, a3, a0
-; RV32I-NEXT: slli a5, a5, 1
-; RV32I-NEXT: srl t5, a7, a0
-; RV32I-NEXT: slli t6, t0, 1
-; RV32I-NEXT: srl a6, a6, a0
-; RV32I-NEXT: slli a7, a7, 1
-; RV32I-NEXT: srl s0, t1, a0
-; RV32I-NEXT: slli s1, t2, 1
-; RV32I-NEXT: srl t0, t0, a0
-; RV32I-NEXT: slli t1, t1, 1
-; RV32I-NEXT: srl t2, t2, a0
-; RV32I-NEXT: slli s2, a4, 1
-; RV32I-NEXT: sra s3, a4, a0
+; RV32I-NEXT: slli a4, a4, 1
+; RV32I-NEXT: srl t5, a6, a0
+; RV32I-NEXT: slli t6, a7, 1
+; RV32I-NEXT: srl a5, a5, a0
+; RV32I-NEXT: slli a6, a6, 1
+; RV32I-NEXT: srl s0, t0, a0
+; RV32I-NEXT: slli s1, t1, 1
+; RV32I-NEXT: srl a7, a7, a0
+; RV32I-NEXT: slli t0, t0, 1
+; RV32I-NEXT: srl t1, t1, a0
+; RV32I-NEXT: slli s2, t2, 1
+; RV32I-NEXT: sra t2, t2, a0
; RV32I-NEXT: sll a0, t4, a1
-; RV32I-NEXT: sll a4, a5, a1
-; RV32I-NEXT: sll a5, t6, a1
-; RV32I-NEXT: sll a7, a7, a1
-; RV32I-NEXT: sll t4, s1, a1
-; RV32I-NEXT: sll t1, t1, a1
-; RV32I-NEXT: sll t6, s2, a1
-; RV32I-NEXT: srli s1, s3, 24
-; RV32I-NEXT: srli s2, s3, 16
-; RV32I-NEXT: srli s4, s3, 8
+; RV32I-NEXT: sll a4, a4, a1
+; RV32I-NEXT: sll t4, t6, a1
+; RV32I-NEXT: sll a6, a6, a1
+; RV32I-NEXT: sll t6, s1, a1
+; RV32I-NEXT: sll t0, t0, a1
+; RV32I-NEXT: sll s1, s2, a1
+; RV32I-NEXT: srli s2, t2, 24
+; RV32I-NEXT: srli s3, t2, 16
+; RV32I-NEXT: srli s4, t2, 8
; RV32I-NEXT: or a0, t3, a0
; RV32I-NEXT: or a1, a3, a4
-; RV32I-NEXT: or a3, t5, a5
-; RV32I-NEXT: or a4, a6, a7
-; RV32I-NEXT: or a5, s0, t4
-; RV32I-NEXT: or a6, t0, t1
-; RV32I-NEXT: or a7, t2, t6
-; RV32I-NEXT: sb s3, 28(a2)
+; RV32I-NEXT: or a3, t5, t4
+; RV32I-NEXT: or a4, a5, a6
+; RV32I-NEXT: or a5, s0, t6
+; RV32I-NEXT: or a6, a7, t0
+; RV32I-NEXT: or a7, t1, s1
+; RV32I-NEXT: sb t2, 28(a2)
; RV32I-NEXT: sb s4, 29(a2)
-; RV32I-NEXT: sb s2, 30(a2)
-; RV32I-NEXT: sb s1, 31(a2)
+; RV32I-NEXT: sb s3, 30(a2)
+; RV32I-NEXT: sb s2, 31(a2)
; RV32I-NEXT: srli t0, a7, 24
; RV32I-NEXT: srli t1, a7, 16
; RV32I-NEXT: srli t2, a7, 8
diff --git a/llvm/test/CodeGen/SystemZ/pr60413.ll b/llvm/test/CodeGen/SystemZ/pr60413.ll
index 8a6a30318ae58..bbf4d50bd716d 100644
--- a/llvm/test/CodeGen/SystemZ/pr60413.ll
+++ b/llvm/test/CodeGen/SystemZ/pr60413.ll
@@ -16,31 +16,31 @@ define dso_local void @m() local_unnamed_addr #1 {
; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: lhrl %r1, f+4
-; CHECK-NEXT: sll %r1, 8
; CHECK-NEXT: larl %r2, f
-; CHECK-NEXT: ic %r1, 6(%r2)
-; CHECK-NEXT: larl %r2, e
-; CHECK-NEXT: lb %r0, 3(%r2)
-; CHECK-NEXT: vlvgp %v0, %r0, %r1
-; CHECK-NEXT: vlvgp %v1, %r1, %r0
-; CHECK-NEXT: vlvgf %v1, %r1, 0
-; CHECK-NEXT: vlvgf %v1, %r1, 2
-; CHECK-NEXT: vlvgp %v2, %r1, %r1
-; CHECK-NEXT: # kill: def $r1l killed $r1l killed $r1d
+; CHECK-NEXT: llc %r2, 6(%r2)
+; CHECK-NEXT: larl %r3, e
+; CHECK-NEXT: lb %r0, 3(%r3)
+; CHECK-NEXT: rosbg %r2, %r1, 32, 55, 8
+; CHECK-NEXT: vlvgp %v0, %r2, %r0
+; CHECK-NEXT: vlvgf %v0, %r2, 0
+; CHECK-NEXT: vlvgf %v0, %r2, 2
+; CHECK-NEXT: vlvgp %v1, %r0, %r2
+; CHECK-NEXT: vlvgp %v2, %r2, %r2
+; CHECK-NEXT: lr %r1, %r2
; CHECK-NEXT: nilh %r1, 255
; CHECK-NEXT: chi %r1, 128
; CHECK-NEXT: ipm %r1
; CHECK-NEXT: risbg %r1, %r1, 63, 191, 36
-; CHECK-NEXT: vlvgf %v0, %r0, 0
-; CHECK-NEXT: vlvgf %v0, %r0, 2
; CHECK-NEXT: vgbm %v3, 30583
; CHECK-NEXT: vn %v0, %v0, %v3
+; CHECK-NEXT: vlvgf %v1, %r0, 0
+; CHECK-NEXT: vlvgf %v1, %r0, 2
; CHECK-NEXT: vn %v1, %v1, %v3
; CHECK-NEXT: vrepf %v2, %v2, 1
; CHECK-NEXT: vn %v2, %v2, %v3
; CHECK-NEXT: vrepif %v3, 127
-; CHECK-NEXT: vchlf %v1, %v1, %v3
-; CHECK-NEXT: vlgvf %r13, %v1, 0
+; CHECK-NEXT: vchlf %v0, %v0, %v3
+; CHECK-NEXT: vlgvf %r13, %v0, 0
; CHECK-NEXT: vchlf %v2, %v2, %v3
; CHECK-NEXT: vlgvf %r3, %v2, 1
; CHECK-NEXT: nilf %r3, 1
@@ -54,13 +54,13 @@ define dso_local void @m() local_unnamed_addr #1 {
; CHECK-NEXT: nilf %r14, 1
; CHECK-NEXT: rosbg %r2, %r14, 32, 51, 12
; CHECK-NEXT: rosbg %r2, %r13, 52, 52, 11
-; CHECK-NEXT: vlgvf %r13, %v1, 1
+; CHECK-NEXT: vlgvf %r13, %v0, 1
; CHECK-NEXT: rosbg %r2, %r13, 53, 53, 10
-; CHECK-NEXT: vlgvf %r13, %v1, 2
+; CHECK-NEXT: vlgvf %r13, %v0, 2
; CHECK-NEXT: rosbg %r2, %r13, 54, 54, 9
-; CHECK-NEXT: vlgvf %r13, %v1, 3
+; CHECK-NEXT: vlgvf %r13, %v0, 3
; CHECK-NEXT: rosbg %r2, %r13, 55, 55, 8
-; CHECK-NEXT: vchlf %v0, %v0, %v3
+; CHECK-NEXT: vchlf %v0, %v1, %v3
; CHECK-NEXT: vlgvf %r13, %v0, 0
; CHECK-NEXT: rosbg %r2, %r13, 56, 56, 7
; CHECK-NEXT: vlgvf %r13, %v0, 1
diff --git a/llvm/test/CodeGen/X86/abds-neg.ll b/llvm/test/CodeGen/X86/abds-neg.ll
index d9064c684cb20..2911edfbfd409 100644
--- a/llvm/test/CodeGen/X86/abds-neg.ll
+++ b/llvm/test/CodeGen/X86/abds-neg.ll
@@ -1076,15 +1076,15 @@ define i64 @abd_subnsw_i64(i64 %a, i64 %b) nounwind {
; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
-; X86-NEXT: subl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: sbbl {{[0-9]+}}(%esp), %esi
-; X86-NEXT: movl %esi, %edx
+; X86-NEXT: subl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: sbbl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %ecx, %edx
; X86-NEXT: sarl $31, %edx
-; X86-NEXT: xorl %edx, %esi
; X86-NEXT: xorl %edx, %ecx
+; X86-NEXT: xorl %edx, %esi
; X86-NEXT: movl %edx, %eax
-; X86-NEXT: subl %ecx, %eax
-; X86-NEXT: sbbl %esi, %edx
+; X86-NEXT: subl %esi, %eax
+; X86-NEXT: sbbl %ecx, %edx
; X86-NEXT: popl %esi
; X86-NEXT: retl
;
@@ -1107,15 +1107,15 @@ define i64 @abd_subnsw_i64_undef(i64 %a, i64 %b) nounwind {
; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
-; X86-NEXT: subl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: sbbl {{[0-9]+}}(%esp), %esi
-; X86-NEXT: movl %esi, %edx
+; X86-NEXT: subl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: sbbl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %ecx, %edx
; X86-NEXT: sarl $31, %edx
-; X86-NEXT: xorl %edx, %esi
; X86-NEXT: xorl %edx, %ecx
+; X86-NEXT: xorl %edx, %esi
; X86-NEXT: movl %edx, %eax
-; X86-NEXT: subl %ecx, %eax
-; X86-NEXT: sbbl %esi, %edx
+; X86-NEXT: subl %esi, %eax
+; X86-NEXT: sbbl %ecx, %edx
; X86-NEXT: popl %esi
; X86-NEXT: retl
;
@@ -1142,32 +1142,32 @@ define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
; X86-NEXT: pushl %esi
; X86-NEXT: andl $-16, %esp
; X86-NEXT: subl $16, %esp
-; X86-NEXT: movl 32(%ebp), %ecx
; X86-NEXT: movl 36(%ebp), %eax
-; X86-NEXT: movl 24(%ebp), %edi
+; X86-NEXT: movl 32(%ebp), %ecx
; X86-NEXT: movl 28(%ebp), %edx
-; X86-NEXT: subl 40(%ebp), %edi
+; X86-NEXT: movl 24(%ebp), %esi
+; X86-NEXT: subl 40(%ebp), %esi
; X86-NEXT: sbbl 44(%ebp), %edx
; X86-NEXT: sbbl 48(%ebp), %ecx
; X86-NEXT: sbbl 52(%ebp), %eax
-; X86-NEXT: movl %eax, %esi
-; X86-NEXT: sarl $31, %esi
-; X86-NEXT: xorl %esi, %eax
-; X86-NEXT: xorl %esi, %ecx
-; X86-NEXT: xorl %esi, %edx
-; X86-NEXT: xorl %esi, %edi
-; X86-NEXT: movl %esi, %ebx
-; X86-NEXT: subl %edi, %ebx
-; X86-NEXT: movl %esi, %edi
-; X86-NEXT: sbbl %edx, %edi
-; X86-NEXT: movl %esi, %edx
+; X86-NEXT: movl %eax, %edi
+; X86-NEXT: sarl $31, %edi
+; X86-NEXT: xorl %edi, %eax
+; X86-NEXT: xorl %edi, %ecx
+; X86-NEXT: xorl %edi, %edx
+; X86-NEXT: xorl %edi, %esi
+; X86-NEXT: movl %edi, %ebx
+; X86-NEXT: subl %esi, %ebx
+; X86-NEXT: movl %edi, %esi
+; X86-NEXT: sbbl %edx, %esi
+; X86-NEXT: movl %edi, %edx
; X86-NEXT: sbbl %ecx, %edx
-; X86-NEXT: sbbl %eax, %esi
+; X86-NEXT: sbbl %eax, %edi
; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: movl %ebx, (%eax)
-; X86-NEXT: movl %edi, 4(%eax)
+; X86-NEXT: movl %esi, 4(%eax)
; X86-NEXT: movl %edx, 8(%eax)
-; X86-NEXT: movl %esi, 12(%eax)
+; X86-NEXT: movl %edi, 12(%eax)
; X86-NEXT: leal -12(%ebp), %esp
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
@@ -1203,32 +1203,32 @@ define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {
; X86-NEXT: pushl %esi
; X86-NEXT: andl $-16, %esp
; X86-NEXT: subl $16, %esp
-; X86-NEXT: movl 32(%ebp), %ecx
; X86-NEXT: movl 36(%ebp), %eax
-; X86-NEXT: movl 24(%ebp), %edi
+; X86-NEXT: movl 32(%ebp), %ecx
; X86-NEXT: movl 28(%ebp), %edx
-; X86-NEXT: subl 40(%ebp), %edi
+; X86-NEXT: movl 24(%ebp), %esi
+; X86-NEXT: subl 40(%ebp), %esi
; X86-NEXT: sbbl 44(%ebp), %edx
; X86-NEXT: sbbl 48(%ebp), %ecx
; X86-NEXT: sbbl 52(%ebp), %eax
-; X86-NEXT: movl %eax, %esi
-; X86-NEXT: sarl $31, %esi
-; X86-NEXT: xorl %esi, %eax
-; X86-NEXT: xorl %esi, %ecx
-; X86-NEXT: xorl %esi, %edx
-; X86-NEXT: xorl %esi, %edi
-; X86-NEXT: movl %esi, %ebx
-; X86-NEXT: subl %edi, %ebx
-; X86-NEXT: movl %esi, %edi
-; X86-NEXT: sbbl %edx, %edi
-; X86-NEXT: movl %esi, %edx
+; X86-NEXT: movl %eax, %edi
+; X86-NEXT: sarl $31, %edi
+; X86-NEXT: xorl %edi, %eax
+; X86-NEXT: xorl %edi, %ecx
+; X86-NEXT: xorl %edi, %edx
+; X86-NEXT: xorl %edi, %esi
+; X86-NEXT: movl %edi, %ebx
+; X86-NEXT: subl %esi, %ebx
+; X86-NEXT: movl %edi, %esi
+; X86-NEXT: sbbl %edx, %esi
+; X86-NEXT: movl %edi, %edx
; X86-NEXT: sbbl %ecx, %edx
-; X86-NEXT: sbbl %eax, %esi
+; X86-NEXT: sbbl %eax, %edi
; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: movl %ebx, (%eax)
-; X86-NEXT: movl %edi, 4(%eax)
+; X86-NEXT: movl %esi, 4(%eax)
; X86-NEXT: movl %edx, 8(%eax)
-; X86-NEXT: movl %esi, 12(%eax)
+; X86-NEXT: movl %edi, 12(%eax)
; X86-NEXT: leal -12(%ebp), %esp
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
diff --git a/llvm/test/CodeGen/X86/avg.ll b/llvm/test/CodeGen/X86/avg.ll
index 5152c00521f81..5a016e14b204d 100644
--- a/llvm/test/CodeGen/X86/avg.ll
+++ b/llvm/test/CodeGen/X86/avg.ll
@@ -1758,20 +1758,20 @@ define void @not_avg_v16i8_wide_constants(ptr %a, ptr %b) nounwind {
; SSE2-LABEL: not_avg_v16i8_wide_constants:
; SSE2: # %bb.0:
; SSE2-NEXT: movaps (%rdi), %xmm1
-; SSE2-NEXT: movdqa (%rsi), %xmm0
+; SSE2-NEXT: movdqa (%rsi), %xmm2
; SSE2-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: decl %eax
-; SSE2-NEXT: movd %eax, %xmm2
+; SSE2-NEXT: movd %eax, %xmm0
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: decl %eax
; SSE2-NEXT: movd %eax, %xmm1
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: decl %eax
-; SSE2-NEXT: movd %eax, %xmm3
+; SSE2-NEXT: movd %eax, %xmm4
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: decl %eax
-; SSE2-NEXT: movd %eax, %xmm4
+; SSE2-NEXT: movd %eax, %xmm3
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: decl %eax
; SSE2-NEXT: movd %eax, %xmm5
@@ -1786,9 +1786,6 @@ define void @not_avg_v16i8_wide_constants(ptr %a, ptr %b) nounwind {
; SSE2-NEXT: movd %eax, %xmm8
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: decl %eax
-; SSE2-NEXT: movd %eax, %xmm10
-; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; SSE2-NEXT: decl %eax
; SSE2-NEXT: movd %eax, %xmm9
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: decl %eax
@@ -1798,6 +1795,9 @@ define void @not_avg_v16i8_wide_constants(ptr %a, ptr %b) nounwind {
; SSE2-NEXT: movd %eax, %xmm12
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: decl %eax
+; SSE2-NEXT: movd %eax, %xmm10
+; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
+; SSE2-NEXT: decl %eax
; SSE2-NEXT: movd %eax, %xmm13
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: decl %eax
@@ -1807,45 +1807,43 @@ define void @not_avg_v16i8_wide_constants(ptr %a, ptr %b) nounwind {
; SSE2-NEXT: movd %eax, %xmm15
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: decl %eax
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
-; SSE2-NEXT: movd %eax, %xmm2
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,0,0,0]
-; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
+; SSE2-NEXT: movd %eax, %xmm0
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3]
+; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1],xmm6[2],xmm5[2],xmm6[3],xmm5[3]
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm6[0,0,0,0]
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm6[0,0,0,0]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm8 = xmm8[0],xmm7[0],xmm8[1],xmm7[1],xmm8[2],xmm7[2],xmm8[3],xmm7[3]
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm8[0,0,0,0]
-; SSE2-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm3[2],xmm4[3],xmm3[3]
-; SSE2-NEXT: movsd {{.*#+}} xmm4 = xmm1[0],xmm4[1]
+; SSE2-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm1[2],xmm4[3],xmm1[3]
+; SSE2-NEXT: movsd {{.*#+}} xmm4 = xmm3[0],xmm4[1]
; SSE2-NEXT: pxor %xmm3, %xmm3
-; SSE2-NEXT: movdqa %xmm0, %xmm1
+; SSE2-NEXT: movdqa %xmm2, %xmm1
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3],xmm1[4],xmm3[4],xmm1[5],xmm3[5],xmm1[6],xmm3[6],xmm1[7],xmm3[7]
; SSE2-NEXT: movapd %xmm4, %xmm5
; SSE2-NEXT: andpd %xmm1, %xmm5
; SSE2-NEXT: xorpd %xmm4, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
; SSE2-NEXT: paddw %xmm5, %xmm1
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm9 = xmm9[0],xmm10[0],xmm9[1],xmm10[1],xmm9[2],xmm10[2],xmm9[3],xmm10[3]
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm12 = xmm12[0],xmm11[0],xmm12[1],xmm11[1],xmm12[2],xmm11[2],xmm12[3],xmm11[3]
-; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm12[0,0,0,0]
-; SSE2-NEXT: punpckldq {{.*#+}} xmm9 = xmm9[0],xmm4[0],xmm9[1],xmm4[1]
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm11 = xmm11[0],xmm9[0],xmm11[1],xmm9[1],xmm11[2],xmm9[2],xmm11[3],xmm9[3]
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm10 = xmm10[0],xmm12[0],xmm10[1],xmm12[1],xmm10[2],xmm12[2],xmm10[3],xmm12[3]
+; SSE2-NEXT: punpckldq {{.*#+}} xmm10 = xmm10[0],xmm11[0],xmm10[1],xmm11[1]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm14 = xmm14[0],xmm13[0],xmm14[1],xmm13[1],xmm14[2],xmm13[2],xmm14[3],xmm13[3]
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm14[0,0,0,0]
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm15[0],xmm2[1],xmm15[1],xmm2[2],xmm15[2],xmm2[3],xmm15[3]
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,0,0]
-; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm4[2],xmm2[3],xmm4[3]
-; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm9[0],xmm2[1]
-; SSE2-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm3[8],xmm0[9],xmm3[9],xmm0[10],xmm3[10],xmm0[11],xmm3[11],xmm0[12],xmm3[12],xmm0[13],xmm3[13],xmm0[14],xmm3[14],xmm0[15],xmm3[15]
-; SSE2-NEXT: movapd %xmm2, %xmm3
-; SSE2-NEXT: andpd %xmm0, %xmm3
-; SSE2-NEXT: xorpd %xmm2, %xmm0
-; SSE2-NEXT: psrlw $1, %xmm0
-; SSE2-NEXT: paddw %xmm3, %xmm0
-; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0]
-; SSE2-NEXT: pand %xmm2, %xmm0
-; SSE2-NEXT: pand %xmm2, %xmm1
-; SSE2-NEXT: packuswb %xmm0, %xmm1
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm15[0],xmm0[1],xmm15[1],xmm0[2],xmm15[2],xmm0[3],xmm15[3]
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
+; SSE2-NEXT: punpckhdq {{.*#+}} xmm0 = xmm0[2],xmm4[2],xmm0[3],xmm4[3]
+; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm10[0],xmm0[1]
+; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm3[8],xmm2[9],xmm3[9],xmm2[10],xmm3[10],xmm2[11],xmm3[11],xmm2[12],xmm3[12],xmm2[13],xmm3[13],xmm2[14],xmm3[14],xmm2[15],xmm3[15]
+; SSE2-NEXT: movapd %xmm0, %xmm3
+; SSE2-NEXT: andpd %xmm2, %xmm3
+; SSE2-NEXT: xorpd %xmm0, %xmm2
+; SSE2-NEXT: psrlw $1, %xmm2
+; SSE2-NEXT: paddw %xmm3, %xmm2
+; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0]
+; SSE2-NEXT: pand %xmm0, %xmm2
+; SSE2-NEXT: pand %xmm0, %xmm1
+; SSE2-NEXT: packuswb %xmm2, %xmm1
; SSE2-NEXT: movdqu %xmm1, (%rax)
; SSE2-NEXT: retq
;
@@ -1855,75 +1853,71 @@ define void @not_avg_v16i8_wide_constants(ptr %a, ptr %b) nounwind {
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm3 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
-; AVX1-NEXT: vpextrw $7, %xmm3, %edx
-; AVX1-NEXT: vpextrw $6, %xmm3, %ecx
-; AVX1-NEXT: vpextrw $5, %xmm3, %eax
+; AVX1-NEXT: vpextrw $3, %xmm3, %edx
+; AVX1-NEXT: vpextrw $2, %xmm3, %ecx
+; AVX1-NEXT: vpextrw $1, %xmm3, %eax
; AVX1-NEXT: decl %edx
; AVX1-NEXT: vmovd %edx, %xmm4
-; AVX1-NEXT: vpextrw $4, %xmm3, %edx
+; AVX1-NEXT: vpextrw $0, %xmm3, %edx
; AVX1-NEXT: decl %ecx
; AVX1-NEXT: vmovd %ecx, %xmm5
-; AVX1-NEXT: vpextrw $1, %xmm3, %ecx
+; AVX1-NEXT: vpextrw $3, %xmm2, %ecx
; AVX1-NEXT: decl %eax
; AVX1-NEXT: vmovd %eax, %xmm6
-; AVX1-NEXT: vpextrw $0, %xmm3, %eax
+; AVX1-NEXT: vpextrw $2, %xmm2, %eax
; AVX1-NEXT: decl %edx
; AVX1-NEXT: vmovd %edx, %xmm7
-; AVX1-NEXT: vpextrw $3, %xmm3, %edx
-; AVX1-NEXT: decq %rcx
-; AVX1-NEXT: vmovq %rcx, %xmm8
-; AVX1-NEXT: vpextrw $2, %xmm3, %ecx
-; AVX1-NEXT: decq %rax
-; AVX1-NEXT: vmovq %rax, %xmm3
-; AVX1-NEXT: vpextrw $7, %xmm2, %eax
+; AVX1-NEXT: vpextrw $1, %xmm2, %edx
+; AVX1-NEXT: decl %ecx
+; AVX1-NEXT: vmovd %ecx, %xmm8
+; AVX1-NEXT: vpextrw $0, %xmm2, %ecx
+; AVX1-NEXT: decl %eax
+; AVX1-NEXT: vmovd %eax, %xmm9
+; AVX1-NEXT: vpextrw $7, %xmm3, %eax
; AVX1-NEXT: decl %edx
-; AVX1-NEXT: vmovd %edx, %xmm9
-; AVX1-NEXT: vpextrw $6, %xmm2, %edx
+; AVX1-NEXT: vmovd %edx, %xmm10
+; AVX1-NEXT: vpextrw $6, %xmm3, %edx
; AVX1-NEXT: decl %ecx
-; AVX1-NEXT: vmovd %ecx, %xmm10
-; AVX1-NEXT: vpextrw $5, %xmm2, %ecx
+; AVX1-NEXT: vmovd %ecx, %xmm11
+; AVX1-NEXT: vpextrw $7, %xmm2, %ecx
; AVX1-NEXT: decl %eax
-; AVX1-NEXT: vmovd %eax, %xmm11
-; AVX1-NEXT: vpextrw $4, %xmm2, %eax
+; AVX1-NEXT: vmovd %eax, %xmm12
+; AVX1-NEXT: vpextrw $6, %xmm2, %eax
; AVX1-NEXT: decl %edx
-; AVX1-NEXT: vmovd %edx, %xmm12
-; AVX1-NEXT: vpextrw $1, %xmm2, %edx
+; AVX1-NEXT: vmovd %edx, %xmm13
+; AVX1-NEXT: vpextrw $5, %xmm3, %edx
; AVX1-NEXT: decl %ecx
-; AVX1-NEXT: vmovd %ecx, %xmm13
-; AVX1-NEXT: vpextrw $0, %xmm2, %ecx
+; AVX1-NEXT: vmovd %ecx, %xmm14
+; AVX1-NEXT: vpextrw $4, %xmm3, %ecx
; AVX1-NEXT: decl %eax
-; AVX1-NEXT: vmovd %eax, %xmm14
-; AVX1-NEXT: vpextrw $3, %xmm2, %eax
-; AVX1-NEXT: decq %rdx
-; AVX1-NEXT: vmovq %rdx, %xmm15
-; AVX1-NEXT: vpextrw $2, %xmm2, %edx
-; AVX1-NEXT: decq %rcx
-; AVX1-NEXT: vmovq %rcx, %xmm2
+; AVX1-NEXT: vmovd %eax, %xmm3
+; AVX1-NEXT: vpextrw $5, %xmm2, %eax
+; AVX1-NEXT: decl %edx
+; AVX1-NEXT: vmovd %edx, %xmm15
+; AVX1-NEXT: vpextrw $4, %xmm2, %edx
+; AVX1-NEXT: decl %ecx
+; AVX1-NEXT: vmovd %ecx, %xmm2
; AVX1-NEXT: decl %eax
; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm5[0],xmm4[0],xmm5[1],xmm4[1],xmm5[2],xmm4[2],xmm5[3],xmm4[3]
; AVX1-NEXT: vmovd %eax, %xmm5
; AVX1-NEXT: decl %edx
; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm7[0],xmm6[0],xmm7[1],xmm6[1],xmm7[2],xmm6[2],xmm7[3],xmm6[3]
; AVX1-NEXT: vmovd %edx, %xmm7
-; AVX1-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[0,0,0,0]
-; AVX1-NEXT: vpshufd {{.*#+}} xmm6 = xmm6[0,1,0,1]
-; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm6[0,1,2,3,4,5],xmm4[6,7]
-; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm3[0],xmm8[0],xmm3[1],xmm8[1],xmm3[2],xmm8[2],xmm3[3],xmm8[3]
-; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm10[0],xmm9[0],xmm10[1],xmm9[1],xmm10[2],xmm9[2],xmm10[3],xmm9[3]
-; AVX1-NEXT: vpshufd {{.*#+}} xmm6 = xmm6[0,0,1,1]
-; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm6[2,3],xmm3[4,5,6,7]
-; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm4[4,5,6,7]
-; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm12[0],xmm11[0],xmm12[1],xmm11[1],xmm12[2],xmm11[2],xmm12[3],xmm11[3]
-; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm14[0],xmm13[0],xmm14[1],xmm13[1],xmm14[2],xmm13[2],xmm14[3],xmm13[3]
-; AVX1-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[0,0,0,0]
-; AVX1-NEXT: vpshufd {{.*#+}} xmm6 = xmm6[0,1,0,1]
-; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm6[0,1,2,3,4,5],xmm4[6,7]
+; AVX1-NEXT: vpunpckldq {{.*#+}} xmm4 = xmm6[0],xmm4[0],xmm6[1],xmm4[1]
+; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm9[0],xmm8[0],xmm9[1],xmm8[1],xmm9[2],xmm8[2],xmm9[3],xmm8[3]
+; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm8 = xmm11[0],xmm10[0],xmm11[1],xmm10[1],xmm11[2],xmm10[2],xmm11[3],xmm10[3]
+; AVX1-NEXT: vpunpckldq {{.*#+}} xmm6 = xmm8[0],xmm6[0],xmm8[1],xmm6[1]
+; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm6, %ymm4
+; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm13[0],xmm12[0],xmm13[1],xmm12[1],xmm13[2],xmm12[2],xmm13[3],xmm12[3]
+; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm3[0],xmm14[0],xmm3[1],xmm14[1],xmm3[2],xmm14[2],xmm3[3],xmm14[3]
+; AVX1-NEXT: vinsertf128 $1, %xmm6, %ymm3, %ymm3
; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm2[0],xmm15[0],xmm2[1],xmm15[1],xmm2[2],xmm15[2],xmm2[3],xmm15[3]
+; AVX1-NEXT: vshufps {{.*#+}} ymm3 = ymm3[0,0,0,0,4,4,4,4]
; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm5 = xmm7[0],xmm5[0],xmm7[1],xmm5[1],xmm7[2],xmm5[2],xmm7[3],xmm5[3]
-; AVX1-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[0,0,1,1]
-; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm5[2,3],xmm2[4,5,6,7]
-; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm4[4,5,6,7]
-; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2
+; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm5, %ymm2
+; AVX1-NEXT: vmovddup {{.*#+}} ymm2 = ymm2[0,0,2,2]
+; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2],ymm3[3],ymm2[4,5,6],ymm3[7]
+; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm4[0,1],ymm2[2,3],ymm4[4,5],ymm2[6,7]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vandps %ymm0, %ymm2, %ymm1
; AVX1-NEXT: vxorps %ymm0, %ymm2, %ymm0
diff --git a/llvm/test/CodeGen/X86/bit-manip-i256.ll b/llvm/test/CodeGen/X86/bit-manip-i256.ll
index 994443117c165..bb875b9a6ca55 100644
--- a/llvm/test/CodeGen/X86/bit-manip-i256.ll
+++ b/llvm/test/CodeGen/X86/bit-manip-i256.ll
@@ -2408,88 +2408,92 @@ define i256 @isolate_msb_i256(i256 %a0, i256 %idx) nounwind {
; SSE-LABEL: isolate_msb_i256:
; SSE: # %bb.0:
; SSE-NEXT: pushq %rbx
-; SSE-NEXT: movq %rcx, %rax
-; SSE-NEXT: movq %rdx, %r9
-; SSE-NEXT: orq %r8, %r9
-; SSE-NEXT: bsrq %rsi, %rcx
-; SSE-NEXT: orq %rax, %rsi
-; SSE-NEXT: bsrq %r8, %r10
-; SSE-NEXT: xorq $63, %r10
-; SSE-NEXT: bsrq %rax, %r11
-; SSE-NEXT: xorq $63, %r11
-; SSE-NEXT: orq $64, %r11
+; SSE-NEXT: movq %rdx, %rax
+; SSE-NEXT: orq %r8, %rax
+; SSE-NEXT: movq %rsi, %r9
+; SSE-NEXT: orq %rcx, %r9
+; SSE-NEXT: bsrq %r8, %r11
+; SSE-NEXT: xorl $63, %r11d
+; SSE-NEXT: bsrq %rcx, %r10
+; SSE-NEXT: xorl $63, %r10d
+; SSE-NEXT: addb $64, %r10b
+; SSE-NEXT: movzbl %r10b, %r10d
; SSE-NEXT: testq %r8, %r8
-; SSE-NEXT: cmovneq %r10, %r11
-; SSE-NEXT: bsrq %rdx, %r10
-; SSE-NEXT: xorq $63, %r10
-; SSE-NEXT: xorq $63, %rcx
-; SSE-NEXT: orq $64, %rcx
+; SSE-NEXT: cmovnel %r11d, %r10d
+; SSE-NEXT: bsrq %rdx, %r11
+; SSE-NEXT: xorl $63, %r11d
+; SSE-NEXT: bsrq %rsi, %rsi
+; SSE-NEXT: xorl $63, %esi
+; SSE-NEXT: addb $64, %sil
+; SSE-NEXT: movzbl %sil, %esi
; SSE-NEXT: testq %rdx, %rdx
-; SSE-NEXT: cmovneq %r10, %rcx
-; SSE-NEXT: orq $128, %rcx
-; SSE-NEXT: orq %r8, %rax
-; SSE-NEXT: cmovneq %r11, %rcx
+; SSE-NEXT: cmovnel %r11d, %esi
+; SSE-NEXT: addb $-128, %sil
+; SSE-NEXT: orq %r8, %rcx
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
-; SSE-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
+; SSE-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; SSE-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movl %ecx, %eax
-; SSE-NEXT: shrb $6, %al
-; SSE-NEXT: movzbl %al, %eax
+; SSE-NEXT: movzbl %sil, %ecx
+; SSE-NEXT: cmovnel %r10d, %ecx
+; SSE-NEXT: movl %ecx, %edx
+; SSE-NEXT: shrb $6, %dl
+; SSE-NEXT: movzbl %dl, %esi
; SSE-NEXT: movq $0, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movq -40(%rsp,%rax,8), %rdx
-; SSE-NEXT: movq -48(%rsp,%rax,8), %r8
+; SSE-NEXT: movq -40(%rsp,%rsi,8), %rdx
+; SSE-NEXT: movq -48(%rsp,%rsi,8), %r8
; SSE-NEXT: movq %r8, %r10
; SSE-NEXT: shrdq %cl, %rdx, %r10
-; SSE-NEXT: movq -56(%rsp,%rax,8), %r11
+; SSE-NEXT: movq -56(%rsp,%rsi,8), %r11
; SSE-NEXT: movq %r11, %rbx
; SSE-NEXT: shrdq %cl, %r8, %rbx
-; SSE-NEXT: movq -64(%rsp,%rax,8), %r8
+; SSE-NEXT: movq -64(%rsp,%rsi,8), %rsi
; SSE-NEXT: shrq %cl, %rdx
-; SSE-NEXT: # kill: def $cl killed $cl killed $rcx
-; SSE-NEXT: shrdq %cl, %r11, %r8
+; SSE-NEXT: # kill: def $cl killed $cl killed $ecx
+; SSE-NEXT: shrdq %cl, %r11, %rsi
; SSE-NEXT: xorl %ecx, %ecx
-; SSE-NEXT: orq %r9, %rsi
+; SSE-NEXT: orq %rax, %r9
; SSE-NEXT: cmoveq %rcx, %rbx
; SSE-NEXT: cmoveq %rcx, %r10
-; SSE-NEXT: cmoveq %rcx, %r8
+; SSE-NEXT: cmoveq %rcx, %rsi
; SSE-NEXT: movq %rdi, %rax
; SSE-NEXT: cmoveq %rcx, %rdx
; SSE-NEXT: movq %rdx, 24(%rdi)
; SSE-NEXT: movq %r10, 16(%rdi)
; SSE-NEXT: movq %rbx, 8(%rdi)
-; SSE-NEXT: movq %r8, (%rdi)
+; SSE-NEXT: movq %rsi, (%rdi)
; SSE-NEXT: popq %rbx
; SSE-NEXT: retq
;
; AVX2-LABEL: isolate_msb_i256:
; AVX2: # %bb.0:
; AVX2-NEXT: pushq %rbx
-; AVX2-NEXT: movq %rcx, %rax
; AVX2-NEXT: movq %rdx, %r9
; AVX2-NEXT: orq %r8, %r9
-; AVX2-NEXT: xorl %ecx, %ecx
-; AVX2-NEXT: lzcntq %rsi, %rcx
-; AVX2-NEXT: orq %rax, %rsi
+; AVX2-NEXT: lzcntq %rsi, %rax
+; AVX2-NEXT: orq %rcx, %rsi
; AVX2-NEXT: lzcntq %r8, %r10
-; AVX2-NEXT: lzcntq %rax, %r11
-; AVX2-NEXT: addq $64, %r11
+; AVX2-NEXT: lzcntq %rcx, %r11
+; AVX2-NEXT: addb $64, %r11b
+; AVX2-NEXT: movzbl %r11b, %r11d
; AVX2-NEXT: testq %r8, %r8
-; AVX2-NEXT: cmovneq %r10, %r11
+; AVX2-NEXT: cmovnel %r10d, %r11d
; AVX2-NEXT: xorl %r10d, %r10d
; AVX2-NEXT: lzcntq %rdx, %r10
-; AVX2-NEXT: addq $64, %rcx
+; AVX2-NEXT: addb $64, %al
+; AVX2-NEXT: movzbl %al, %eax
; AVX2-NEXT: testq %rdx, %rdx
-; AVX2-NEXT: cmovneq %r10, %rcx
-; AVX2-NEXT: subq $-128, %rcx
-; AVX2-NEXT: orq %r8, %rax
-; AVX2-NEXT: cmovneq %r11, %rcx
+; AVX2-NEXT: cmovnel %r10d, %eax
; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: addb $-128, %al
; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,9223372036854775808]
; AVX2-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: orq %r8, %rcx
+; AVX2-NEXT: movzbl %al, %ecx
+; AVX2-NEXT: cmovnel %r11d, %ecx
; AVX2-NEXT: movl %ecx, %eax
; AVX2-NEXT: shrb $6, %al
; AVX2-NEXT: movzbl %al, %eax
@@ -2521,25 +2525,27 @@ define i256 @isolate_msb_i256(i256 %a0, i256 %idx) nounwind {
; AVX512F-LABEL: isolate_msb_i256:
; AVX512F: # %bb.0:
; AVX512F-NEXT: pushq %rbx
-; AVX512F-NEXT: movq %rcx, %rax
; AVX512F-NEXT: movq %rdx, %r9
; AVX512F-NEXT: orq %r8, %r9
-; AVX512F-NEXT: lzcntq %rsi, %rcx
-; AVX512F-NEXT: orq %rax, %rsi
+; AVX512F-NEXT: lzcntq %rsi, %rax
+; AVX512F-NEXT: orq %rcx, %rsi
; AVX512F-NEXT: lzcntq %r8, %r10
-; AVX512F-NEXT: lzcntq %rax, %r11
-; AVX512F-NEXT: addq $64, %r11
+; AVX512F-NEXT: lzcntq %rcx, %r11
+; AVX512F-NEXT: addb $64, %r11b
+; AVX512F-NEXT: movzbl %r11b, %r11d
; AVX512F-NEXT: testq %r8, %r8
-; AVX512F-NEXT: cmovneq %r10, %r11
+; AVX512F-NEXT: cmovnel %r10d, %r11d
; AVX512F-NEXT: lzcntq %rdx, %r10
-; AVX512F-NEXT: addq $64, %rcx
+; AVX512F-NEXT: addb $64, %al
+; AVX512F-NEXT: movzbl %al, %eax
; AVX512F-NEXT: testq %rdx, %rdx
-; AVX512F-NEXT: cmovneq %r10, %rcx
-; AVX512F-NEXT: subq $-128, %rcx
-; AVX512F-NEXT: orq %r8, %rax
-; AVX512F-NEXT: cmovneq %r11, %rcx
+; AVX512F-NEXT: cmovnel %r10d, %eax
+; AVX512F-NEXT: addb $-128, %al
; AVX512F-NEXT: vmovaps {{.*#+}} zmm0 = [0,0,0,9223372036854775808,0,0,0,0]
; AVX512F-NEXT: vmovups %zmm0, -{{[0-9]+}}(%rsp)
+; AVX512F-NEXT: orq %r8, %rcx
+; AVX512F-NEXT: movzbl %al, %ecx
+; AVX512F-NEXT: cmovnel %r11d, %ecx
; AVX512F-NEXT: movl %ecx, %eax
; AVX512F-NEXT: shrb $6, %al
; AVX512F-NEXT: movzbl %al, %eax
@@ -2570,27 +2576,29 @@ define i256 @isolate_msb_i256(i256 %a0, i256 %idx) nounwind {
; AVX512VL-LABEL: isolate_msb_i256:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: pushq %rbx
-; AVX512VL-NEXT: movq %rcx, %rax
; AVX512VL-NEXT: movq %rdx, %r9
; AVX512VL-NEXT: orq %r8, %r9
-; AVX512VL-NEXT: lzcntq %rsi, %rcx
-; AVX512VL-NEXT: orq %rax, %rsi
+; AVX512VL-NEXT: lzcntq %rsi, %rax
+; AVX512VL-NEXT: orq %rcx, %rsi
; AVX512VL-NEXT: lzcntq %r8, %r10
-; AVX512VL-NEXT: lzcntq %rax, %r11
-; AVX512VL-NEXT: addq $64, %r11
+; AVX512VL-NEXT: lzcntq %rcx, %r11
+; AVX512VL-NEXT: addb $64, %r11b
+; AVX512VL-NEXT: movzbl %r11b, %r11d
; AVX512VL-NEXT: testq %r8, %r8
-; AVX512VL-NEXT: cmovneq %r10, %r11
+; AVX512VL-NEXT: cmovnel %r10d, %r11d
; AVX512VL-NEXT: lzcntq %rdx, %r10
-; AVX512VL-NEXT: addq $64, %rcx
+; AVX512VL-NEXT: addb $64, %al
+; AVX512VL-NEXT: movzbl %al, %eax
; AVX512VL-NEXT: testq %rdx, %rdx
-; AVX512VL-NEXT: cmovneq %r10, %rcx
-; AVX512VL-NEXT: subq $-128, %rcx
-; AVX512VL-NEXT: orq %r8, %rax
-; AVX512VL-NEXT: cmovneq %r11, %rcx
+; AVX512VL-NEXT: cmovnel %r10d, %eax
+; AVX512VL-NEXT: addb $-128, %al
+; AVX512VL-NEXT: orq %r8, %rcx
; AVX512VL-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512VL-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
; AVX512VL-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,9223372036854775808]
; AVX512VL-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
+; AVX512VL-NEXT: movzbl %al, %ecx
+; AVX512VL-NEXT: cmovnel %r11d, %ecx
; AVX512VL-NEXT: movl %ecx, %eax
; AVX512VL-NEXT: shrb $6, %al
; AVX512VL-NEXT: movzbl %al, %eax
@@ -2622,27 +2630,29 @@ define i256 @isolate_msb_i256(i256 %a0, i256 %idx) nounwind {
; AVX512VBMI-LABEL: isolate_msb_i256:
; AVX512VBMI: # %bb.0:
; AVX512VBMI-NEXT: pushq %rbx
-; AVX512VBMI-NEXT: movq %rcx, %rax
; AVX512VBMI-NEXT: movq %rdx, %r9
; AVX512VBMI-NEXT: orq %r8, %r9
-; AVX512VBMI-NEXT: lzcntq %rsi, %rcx
-; AVX512VBMI-NEXT: orq %rax, %rsi
+; AVX512VBMI-NEXT: lzcntq %rsi, %rax
+; AVX512VBMI-NEXT: orq %rcx, %rsi
; AVX512VBMI-NEXT: lzcntq %r8, %r10
-; AVX512VBMI-NEXT: lzcntq %rax, %r11
-; AVX512VBMI-NEXT: addq $64, %r11
+; AVX512VBMI-NEXT: lzcntq %rcx, %r11
+; AVX512VBMI-NEXT: addb $64, %r11b
+; AVX512VBMI-NEXT: movzbl %r11b, %r11d
; AVX512VBMI-NEXT: testq %r8, %r8
-; AVX512VBMI-NEXT: cmovneq %r10, %r11
+; AVX512VBMI-NEXT: cmovnel %r10d, %r11d
; AVX512VBMI-NEXT: lzcntq %rdx, %r10
-; AVX512VBMI-NEXT: addq $64, %rcx
+; AVX512VBMI-NEXT: addb $64, %al
+; AVX512VBMI-NEXT: movzbl %al, %eax
; AVX512VBMI-NEXT: testq %rdx, %rdx
-; AVX512VBMI-NEXT: cmovneq %r10, %rcx
-; AVX512VBMI-NEXT: subq $-128, %rcx
-; AVX512VBMI-NEXT: orq %r8, %rax
-; AVX512VBMI-NEXT: cmovneq %r11, %rcx
+; AVX512VBMI-NEXT: cmovnel %r10d, %eax
+; AVX512VBMI-NEXT: addb $-128, %al
+; AVX512VBMI-NEXT: orq %r8, %rcx
; AVX512VBMI-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512VBMI-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
; AVX512VBMI-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,9223372036854775808]
; AVX512VBMI-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
+; AVX512VBMI-NEXT: movzbl %al, %ecx
+; AVX512VBMI-NEXT: cmovnel %r11d, %ecx
; AVX512VBMI-NEXT: movl %ecx, %eax
; AVX512VBMI-NEXT: shrb $6, %al
; AVX512VBMI-NEXT: movzbl %al, %eax
@@ -2681,10 +2691,10 @@ define i256 @isolate_msb_i256(i256 %a0, i256 %idx) nounwind {
define i256 @isolate_msb_i256_vector(<4 x i64> %v0, i256 %idx) nounwind {
; SSE2-LABEL: isolate_msb_i256_vector:
; SSE2: # %bb.0:
-; SSE2-NEXT: movq %xmm0, %rcx
+; SSE2-NEXT: movq %xmm0, %rsi
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,2,3]
-; SSE2-NEXT: movq %xmm2, %rdx
-; SSE2-NEXT: movq %xmm1, %rsi
+; SSE2-NEXT: movq %xmm2, %rcx
+; SSE2-NEXT: movq %xmm1, %rdx
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]
; SSE2-NEXT: movq %xmm2, %r8
; SSE2-NEXT: por %xmm1, %xmm0
@@ -2693,29 +2703,32 @@ define i256 @isolate_msb_i256_vector(<4 x i64> %v0, i256 %idx) nounwind {
; SSE2-NEXT: movmskps %xmm0, %eax
; SSE2-NEXT: xorl $15, %eax
; SSE2-NEXT: bsrq %r8, %r9
-; SSE2-NEXT: xorq $63, %r9
-; SSE2-NEXT: bsrq %rsi, %rsi
-; SSE2-NEXT: xorq $63, %rsi
-; SSE2-NEXT: orq $64, %rsi
+; SSE2-NEXT: xorl $63, %r9d
+; SSE2-NEXT: bsrq %rdx, %rdx
+; SSE2-NEXT: xorl $63, %edx
+; SSE2-NEXT: addb $64, %dl
+; SSE2-NEXT: movzbl %dl, %edx
; SSE2-NEXT: testq %r8, %r8
-; SSE2-NEXT: cmovneq %r9, %rsi
-; SSE2-NEXT: bsrq %rdx, %r8
-; SSE2-NEXT: xorq $63, %r8
-; SSE2-NEXT: bsrq %rcx, %rcx
-; SSE2-NEXT: xorq $63, %rcx
-; SSE2-NEXT: orq $64, %rcx
-; SSE2-NEXT: testq %rdx, %rdx
-; SSE2-NEXT: cmovneq %r8, %rcx
-; SSE2-NEXT: orq $128, %rcx
+; SSE2-NEXT: cmovnel %r9d, %edx
+; SSE2-NEXT: bsrq %rcx, %r8
+; SSE2-NEXT: xorl $63, %r8d
+; SSE2-NEXT: bsrq %rsi, %rsi
+; SSE2-NEXT: xorl $63, %esi
+; SSE2-NEXT: addb $64, %sil
+; SSE2-NEXT: movzbl %sil, %esi
+; SSE2-NEXT: testq %rcx, %rcx
+; SSE2-NEXT: cmovnel %r8d, %esi
+; SSE2-NEXT: addb $-128, %sil
; SSE2-NEXT: pcmpeqd %xmm2, %xmm1
-; SSE2-NEXT: movmskps %xmm1, %edx
-; SSE2-NEXT: xorl $15, %edx
-; SSE2-NEXT: cmovneq %rsi, %rcx
+; SSE2-NEXT: movmskps %xmm1, %ecx
+; SSE2-NEXT: xorl $15, %ecx
; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000
-; SSE2-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; SSE2-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movzbl %sil, %ecx
+; SSE2-NEXT: cmovnel %edx, %ecx
; SSE2-NEXT: movl %ecx, %edx
; SSE2-NEXT: shrb $6, %dl
; SSE2-NEXT: movzbl %dl, %esi
@@ -2729,7 +2742,7 @@ define i256 @isolate_msb_i256_vector(<4 x i64> %v0, i256 %idx) nounwind {
; SSE2-NEXT: shrdq %cl, %r8, %r11
; SSE2-NEXT: movq -72(%rsp,%rsi,8), %rsi
; SSE2-NEXT: shrq %cl, %rdx
-; SSE2-NEXT: # kill: def $cl killed $cl killed $rcx
+; SSE2-NEXT: # kill: def $cl killed $cl killed $ecx
; SSE2-NEXT: shrdq %cl, %r10, %rsi
; SSE2-NEXT: xorl %ecx, %ecx
; SSE2-NEXT: testl %eax, %eax
@@ -2746,33 +2759,36 @@ define i256 @isolate_msb_i256_vector(<4 x i64> %v0, i256 %idx) nounwind {
;
; SSE42-LABEL: isolate_msb_i256_vector:
; SSE42: # %bb.0:
-; SSE42-NEXT: pextrq $1, %xmm0, %rdx
-; SSE42-NEXT: movq %xmm0, %rcx
-; SSE42-NEXT: movq %xmm1, %rax
-; SSE42-NEXT: pextrq $1, %xmm1, %rsi
-; SSE42-NEXT: bsrq %rsi, %r8
-; SSE42-NEXT: xorq $63, %r8
-; SSE42-NEXT: bsrq %rax, %rax
-; SSE42-NEXT: xorq $63, %rax
-; SSE42-NEXT: orq $64, %rax
-; SSE42-NEXT: testq %rsi, %rsi
-; SSE42-NEXT: cmovneq %r8, %rax
-; SSE42-NEXT: bsrq %rdx, %rsi
-; SSE42-NEXT: xorq $63, %rsi
-; SSE42-NEXT: bsrq %rcx, %rcx
-; SSE42-NEXT: xorq $63, %rcx
-; SSE42-NEXT: orq $64, %rcx
-; SSE42-NEXT: testq %rdx, %rdx
-; SSE42-NEXT: cmovneq %rsi, %rcx
; SSE42-NEXT: xorps %xmm2, %xmm2
; SSE42-NEXT: movaps %xmm2, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movaps %xmm2, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movaps %xmm2, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: orq $128, %rcx
+; SSE42-NEXT: movq %xmm0, %rax
+; SSE42-NEXT: pextrq $1, %xmm0, %rcx
+; SSE42-NEXT: movq %xmm1, %rdx
+; SSE42-NEXT: pextrq $1, %xmm1, %rsi
+; SSE42-NEXT: bsrq %rsi, %r8
+; SSE42-NEXT: xorl $63, %r8d
+; SSE42-NEXT: bsrq %rdx, %rdx
+; SSE42-NEXT: xorl $63, %edx
+; SSE42-NEXT: addb $64, %dl
+; SSE42-NEXT: movzbl %dl, %edx
+; SSE42-NEXT: testq %rsi, %rsi
+; SSE42-NEXT: cmovnel %r8d, %edx
+; SSE42-NEXT: bsrq %rcx, %rsi
+; SSE42-NEXT: xorl $63, %esi
+; SSE42-NEXT: bsrq %rax, %rax
+; SSE42-NEXT: xorl $63, %eax
+; SSE42-NEXT: addb $64, %al
+; SSE42-NEXT: movzbl %al, %eax
+; SSE42-NEXT: testq %rcx, %rcx
+; SSE42-NEXT: cmovnel %esi, %eax
+; SSE42-NEXT: addb $-128, %al
; SSE42-NEXT: ptest %xmm1, %xmm1
-; SSE42-NEXT: cmovneq %rax, %rcx
-; SSE42-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
-; SSE42-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; SSE42-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: movzbl %al, %ecx
+; SSE42-NEXT: cmovnel %edx, %ecx
; SSE42-NEXT: movl %ecx, %eax
; SSE42-NEXT: shrb $6, %al
; SSE42-NEXT: movzbl %al, %eax
@@ -2786,7 +2802,7 @@ define i256 @isolate_msb_i256_vector(<4 x i64> %v0, i256 %idx) nounwind {
; SSE42-NEXT: shrdq %cl, %rsi, %r10
; SSE42-NEXT: movq -72(%rsp,%rax,8), %rsi
; SSE42-NEXT: shrq %cl, %rdx
-; SSE42-NEXT: # kill: def $cl killed $cl killed $rcx
+; SSE42-NEXT: # kill: def $cl killed $cl killed $ecx
; SSE42-NEXT: shrdq %cl, %r9, %rsi
; SSE42-NEXT: por %xmm1, %xmm0
; SSE42-NEXT: xorl %ecx, %ecx
@@ -2804,29 +2820,31 @@ define i256 @isolate_msb_i256_vector(<4 x i64> %v0, i256 %idx) nounwind {
;
; AVX2-LABEL: isolate_msb_i256_vector:
; AVX2: # %bb.0:
-; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: vpextrq $1, %xmm0, %rdx
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2-NEXT: vmovq %xmm1, %rsi
-; AVX2-NEXT: vpextrq $1, %xmm1, %r8
-; AVX2-NEXT: lzcntq %r8, %rcx
-; AVX2-NEXT: lzcntq %rsi, %r9
-; AVX2-NEXT: addq $64, %r9
-; AVX2-NEXT: testq %r8, %r8
-; AVX2-NEXT: cmovneq %rcx, %r9
-; AVX2-NEXT: lzcntq %rdx, %r10
-; AVX2-NEXT: xorl %ecx, %ecx
-; AVX2-NEXT: lzcntq %rax, %rcx
-; AVX2-NEXT: addq $64, %rcx
+; AVX2-NEXT: vpextrq $1, %xmm1, %rax
+; AVX2-NEXT: vmovq %xmm1, %rcx
+; AVX2-NEXT: lzcntq %rax, %rsi
+; AVX2-NEXT: lzcntq %rcx, %r8
+; AVX2-NEXT: addb $64, %r8b
+; AVX2-NEXT: movzbl %r8b, %r8d
+; AVX2-NEXT: testq %rax, %rax
+; AVX2-NEXT: cmovnel %esi, %r8d
+; AVX2-NEXT: vmovq %xmm0, %rsi
+; AVX2-NEXT: lzcntq %rdx, %r9
+; AVX2-NEXT: lzcntq %rsi, %rsi
+; AVX2-NEXT: addb $64, %sil
+; AVX2-NEXT: movzbl %sil, %esi
; AVX2-NEXT: testq %rdx, %rdx
-; AVX2-NEXT: cmovneq %r10, %rcx
-; AVX2-NEXT: subq $-128, %rcx
-; AVX2-NEXT: orq %r8, %rsi
-; AVX2-NEXT: cmovneq %r9, %rcx
+; AVX2-NEXT: cmovnel %r9d, %esi
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vmovdqu %ymm1, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: addb $-128, %sil
; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,9223372036854775808]
; AVX2-NEXT: vmovups %ymm1, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: orq %rax, %rcx
+; AVX2-NEXT: movzbl %sil, %ecx
+; AVX2-NEXT: cmovnel %r8d, %ecx
; AVX2-NEXT: movl %ecx, %eax
; AVX2-NEXT: shrb $6, %al
; AVX2-NEXT: movzbl %al, %edx
@@ -2983,37 +3001,46 @@ define i256 @isolate_msb_i256_vector(<4 x i64> %v0, i256 %idx) nounwind {
define i256 @isolate_msb_i256_load(ptr %p0, i256 %idx) nounwind {
; SSE2-LABEL: isolate_msb_i256_load:
; SSE2: # %bb.0:
-; SSE2-NEXT: movq 8(%rsi), %r9
+; SSE2-NEXT: movq 24(%rsi), %rcx
+; SSE2-NEXT: movq %rcx, %xmm0
; SSE2-NEXT: movq 16(%rsi), %rdx
-; SSE2-NEXT: movq 24(%rsi), %r8
-; SSE2-NEXT: movdqa (%rsi), %xmm1
-; SSE2-NEXT: por 16(%rsi), %xmm1
+; SSE2-NEXT: movq %rdx, %xmm1
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; SSE2-NEXT: movq (%rsi), %r8
+; SSE2-NEXT: movq 8(%rsi), %rsi
+; SSE2-NEXT: movq %r8, %xmm2
+; SSE2-NEXT: movq %rsi, %xmm0
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
+; SSE2-NEXT: por %xmm1, %xmm2
; SSE2-NEXT: pxor %xmm0, %xmm0
-; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
-; SSE2-NEXT: movmskps %xmm1, %eax
+; SSE2-NEXT: pcmpeqd %xmm0, %xmm2
+; SSE2-NEXT: movmskps %xmm2, %eax
; SSE2-NEXT: xorl $15, %eax
-; SSE2-NEXT: bsrq %r8, %rcx
-; SSE2-NEXT: xorq $63, %rcx
-; SSE2-NEXT: bsrq %rdx, %r10
-; SSE2-NEXT: xorq $63, %r10
-; SSE2-NEXT: orq $64, %r10
-; SSE2-NEXT: testq %r8, %r8
-; SSE2-NEXT: cmovneq %rcx, %r10
-; SSE2-NEXT: bsrq %r9, %r11
-; SSE2-NEXT: xorq $63, %r11
-; SSE2-NEXT: bsrq (%rsi), %rcx
-; SSE2-NEXT: xorq $63, %rcx
-; SSE2-NEXT: orq $64, %rcx
-; SSE2-NEXT: testq %r9, %r9
-; SSE2-NEXT: cmovneq %r11, %rcx
-; SSE2-NEXT: orq $128, %rcx
-; SSE2-NEXT: orq %r8, %rdx
-; SSE2-NEXT: cmovneq %r10, %rcx
+; SSE2-NEXT: bsrq %rcx, %r10
+; SSE2-NEXT: xorl $63, %r10d
+; SSE2-NEXT: bsrq %rdx, %r9
+; SSE2-NEXT: xorl $63, %r9d
+; SSE2-NEXT: addb $64, %r9b
+; SSE2-NEXT: movzbl %r9b, %r9d
+; SSE2-NEXT: testq %rcx, %rcx
+; SSE2-NEXT: cmovnel %r10d, %r9d
+; SSE2-NEXT: bsrq %rsi, %r10
+; SSE2-NEXT: xorl $63, %r10d
+; SSE2-NEXT: bsrq %r8, %r8
+; SSE2-NEXT: xorl $63, %r8d
+; SSE2-NEXT: addb $64, %r8b
+; SSE2-NEXT: movzbl %r8b, %r8d
+; SSE2-NEXT: testq %rsi, %rsi
+; SSE2-NEXT: cmovnel %r10d, %r8d
+; SSE2-NEXT: addb $-128, %r8b
+; SSE2-NEXT: orq %rcx, %rdx
; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000
-; SSE2-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; SSE2-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movzbl %r8b, %ecx
+; SSE2-NEXT: cmovnel %r9d, %ecx
; SSE2-NEXT: movl %ecx, %edx
; SSE2-NEXT: shrb $6, %dl
; SSE2-NEXT: movzbl %dl, %esi
@@ -3027,7 +3054,7 @@ define i256 @isolate_msb_i256_load(ptr %p0, i256 %idx) nounwind {
; SSE2-NEXT: shrdq %cl, %r8, %r11
; SSE2-NEXT: movq -72(%rsp,%rsi,8), %rsi
; SSE2-NEXT: shrq %cl, %rdx
-; SSE2-NEXT: # kill: def $cl killed $cl killed $rcx
+; SSE2-NEXT: # kill: def $cl killed $cl killed $ecx
; SSE2-NEXT: shrdq %cl, %r10, %rsi
; SSE2-NEXT: xorl %ecx, %ecx
; SSE2-NEXT: testl %eax, %eax
@@ -3044,163 +3071,198 @@ define i256 @isolate_msb_i256_load(ptr %p0, i256 %idx) nounwind {
;
; SSE42-LABEL: isolate_msb_i256_load:
; SSE42: # %bb.0:
-; SSE42-NEXT: movq 16(%rsi), %rax
-; SSE42-NEXT: movq 24(%rsi), %rdx
-; SSE42-NEXT: movdqa (%rsi), %xmm0
-; SSE42-NEXT: por 16(%rsi), %xmm0
-; SSE42-NEXT: bsrq %rdx, %rcx
-; SSE42-NEXT: xorq $63, %rcx
-; SSE42-NEXT: bsrq %rax, %r8
-; SSE42-NEXT: xorq $63, %r8
-; SSE42-NEXT: orq $64, %r8
-; SSE42-NEXT: testq %rdx, %rdx
-; SSE42-NEXT: cmovneq %rcx, %r8
-; SSE42-NEXT: movq 8(%rsi), %r9
-; SSE42-NEXT: bsrq %r9, %r10
-; SSE42-NEXT: bsrq (%rsi), %rcx
-; SSE42-NEXT: xorq $63, %r10
-; SSE42-NEXT: xorq $63, %rcx
-; SSE42-NEXT: orq $64, %rcx
-; SSE42-NEXT: testq %r9, %r9
-; SSE42-NEXT: cmovneq %r10, %rcx
-; SSE42-NEXT: orq $128, %rcx
-; SSE42-NEXT: orq %rdx, %rax
-; SSE42-NEXT: cmovneq %r8, %rcx
+; SSE42-NEXT: pushq %rbx
+; SSE42-NEXT: movq 24(%rsi), %r8
+; SSE42-NEXT: movq 16(%rsi), %rcx
+; SSE42-NEXT: movq (%rsi), %rdx
+; SSE42-NEXT: movq 8(%rsi), %rax
+; SSE42-NEXT: bsrq %r8, %r9
+; SSE42-NEXT: xorl $63, %r9d
+; SSE42-NEXT: bsrq %rcx, %rsi
+; SSE42-NEXT: xorl $63, %esi
+; SSE42-NEXT: addb $64, %sil
+; SSE42-NEXT: movzbl %sil, %esi
+; SSE42-NEXT: testq %r8, %r8
+; SSE42-NEXT: cmovnel %r9d, %esi
+; SSE42-NEXT: bsrq %rax, %r9
+; SSE42-NEXT: xorl $63, %r9d
+; SSE42-NEXT: bsrq %rdx, %r10
+; SSE42-NEXT: xorl $63, %r10d
+; SSE42-NEXT: addb $64, %r10b
+; SSE42-NEXT: movzbl %r10b, %r10d
+; SSE42-NEXT: testq %rax, %rax
+; SSE42-NEXT: cmovnel %r9d, %r10d
+; SSE42-NEXT: movq %rcx, %xmm0
+; SSE42-NEXT: addb $-128, %r10b
+; SSE42-NEXT: orq %r8, %rcx
; SSE42-NEXT: xorps %xmm1, %xmm1
; SSE42-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
-; SSE42-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; SSE42-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movl %ecx, %eax
-; SSE42-NEXT: shrb $6, %al
-; SSE42-NEXT: movzbl %al, %eax
+; SSE42-NEXT: movzbl %r10b, %ecx
+; SSE42-NEXT: cmovnel %esi, %ecx
+; SSE42-NEXT: movl %ecx, %esi
+; SSE42-NEXT: shrb $6, %sil
+; SSE42-NEXT: movzbl %sil, %r10d
; SSE42-NEXT: movq $0, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movq -48(%rsp,%rax,8), %rdx
-; SSE42-NEXT: movq -56(%rsp,%rax,8), %rsi
-; SSE42-NEXT: movq %rsi, %r8
-; SSE42-NEXT: shrdq %cl, %rdx, %r8
-; SSE42-NEXT: movq -64(%rsp,%rax,8), %r9
-; SSE42-NEXT: movq %r9, %r10
-; SSE42-NEXT: shrdq %cl, %rsi, %r10
-; SSE42-NEXT: movq -72(%rsp,%rax,8), %rsi
-; SSE42-NEXT: shrq %cl, %rdx
-; SSE42-NEXT: # kill: def $cl killed $cl killed $rcx
-; SSE42-NEXT: shrdq %cl, %r9, %rsi
+; SSE42-NEXT: movq -40(%rsp,%r10,8), %rsi
+; SSE42-NEXT: movq -48(%rsp,%r10,8), %r11
+; SSE42-NEXT: movq %r11, %r9
+; SSE42-NEXT: shrdq %cl, %rsi, %r9
+; SSE42-NEXT: movq %r8, %xmm1
+; SSE42-NEXT: movq -56(%rsp,%r10,8), %r8
+; SSE42-NEXT: movq %r8, %rbx
+; SSE42-NEXT: shrdq %cl, %r11, %rbx
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE42-NEXT: movq %rdx, %xmm1
+; SSE42-NEXT: movq -64(%rsp,%r10,8), %rdx
+; SSE42-NEXT: shrq %cl, %rsi
+; SSE42-NEXT: # kill: def $cl killed $cl killed $ecx
+; SSE42-NEXT: shrdq %cl, %r8, %rdx
+; SSE42-NEXT: movq %rax, %xmm2
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; SSE42-NEXT: por %xmm0, %xmm1
; SSE42-NEXT: xorl %ecx, %ecx
-; SSE42-NEXT: ptest %xmm0, %xmm0
-; SSE42-NEXT: cmoveq %rcx, %r10
-; SSE42-NEXT: cmoveq %rcx, %r8
-; SSE42-NEXT: cmoveq %rcx, %rsi
-; SSE42-NEXT: movq %rdi, %rax
+; SSE42-NEXT: ptest %xmm1, %xmm1
+; SSE42-NEXT: cmoveq %rcx, %rbx
+; SSE42-NEXT: cmoveq %rcx, %r9
; SSE42-NEXT: cmoveq %rcx, %rdx
-; SSE42-NEXT: movq %rdx, 24(%rdi)
-; SSE42-NEXT: movq %r8, 16(%rdi)
-; SSE42-NEXT: movq %r10, 8(%rdi)
-; SSE42-NEXT: movq %rsi, (%rdi)
+; SSE42-NEXT: movq %rdi, %rax
+; SSE42-NEXT: cmoveq %rcx, %rsi
+; SSE42-NEXT: movq %rsi, 24(%rdi)
+; SSE42-NEXT: movq %r9, 16(%rdi)
+; SSE42-NEXT: movq %rbx, 8(%rdi)
+; SSE42-NEXT: movq %rdx, (%rdi)
+; SSE42-NEXT: popq %rbx
; SSE42-NEXT: retq
;
; AVX2-LABEL: isolate_msb_i256_load:
; AVX2: # %bb.0:
-; AVX2-NEXT: movq 16(%rsi), %rax
-; AVX2-NEXT: movq 24(%rsi), %rdx
-; AVX2-NEXT: lzcntq %rdx, %rcx
-; AVX2-NEXT: lzcntq %rax, %r8
-; AVX2-NEXT: addq $64, %r8
-; AVX2-NEXT: testq %rdx, %rdx
-; AVX2-NEXT: cmovneq %rcx, %r8
-; AVX2-NEXT: movq 8(%rsi), %r9
-; AVX2-NEXT: lzcntq %r9, %r10
-; AVX2-NEXT: xorl %ecx, %ecx
-; AVX2-NEXT: lzcntq (%rsi), %rcx
-; AVX2-NEXT: addq $64, %rcx
-; AVX2-NEXT: testq %r9, %r9
-; AVX2-NEXT: cmovneq %r10, %rcx
-; AVX2-NEXT: subq $-128, %rcx
-; AVX2-NEXT: orq %rdx, %rax
-; AVX2-NEXT: cmovneq %r8, %rcx
-; AVX2-NEXT: vmovdqu (%rsi), %ymm0
-; AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; AVX2-NEXT: vmovups %ymm1, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,9223372036854775808]
-; AVX2-NEXT: vmovups %ymm1, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movl %ecx, %eax
-; AVX2-NEXT: shrb $6, %al
-; AVX2-NEXT: movzbl %al, %edx
-; AVX2-NEXT: movq -48(%rsp,%rdx,8), %rsi
-; AVX2-NEXT: movq -56(%rsp,%rdx,8), %r8
-; AVX2-NEXT: movq %r8, %r9
-; AVX2-NEXT: shrdq %cl, %rsi, %r9
; AVX2-NEXT: movq %rdi, %rax
-; AVX2-NEXT: movq -72(%rsp,%rdx,8), %rdi
+; AVX2-NEXT: movq 24(%rsi), %rcx
+; AVX2-NEXT: vmovq %rcx, %xmm0
+; AVX2-NEXT: movq 16(%rsi), %rdx
+; AVX2-NEXT: vmovq %rdx, %xmm1
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; AVX2-NEXT: movq (%rsi), %rdi
+; AVX2-NEXT: movq 8(%rsi), %rsi
+; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; AVX2-NEXT: vmovdqu %ymm1, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: vmovq %rsi, %xmm1
+; AVX2-NEXT: vmovaps {{.*#+}} ymm2 = [0,0,0,9223372036854775808]
+; AVX2-NEXT: vmovups %ymm2, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: vmovq %rdi, %xmm2
+; AVX2-NEXT: lzcntq %rcx, %r8
+; AVX2-NEXT: lzcntq %rdx, %r9
+; AVX2-NEXT: addb $64, %r9b
+; AVX2-NEXT: movzbl %r9b, %r9d
+; AVX2-NEXT: testq %rcx, %rcx
+; AVX2-NEXT: cmovnel %r8d, %r9d
+; AVX2-NEXT: xorl %r8d, %r8d
+; AVX2-NEXT: lzcntq %rsi, %r8
+; AVX2-NEXT: lzcntq %rdi, %rdi
+; AVX2-NEXT: addb $64, %dil
+; AVX2-NEXT: movzbl %dil, %edi
+; AVX2-NEXT: testq %rsi, %rsi
+; AVX2-NEXT: cmovnel %r8d, %edi
+; AVX2-NEXT: addb $-128, %dil
+; AVX2-NEXT: orq %rcx, %rdx
+; AVX2-NEXT: movzbl %dil, %ecx
+; AVX2-NEXT: cmovnel %r9d, %ecx
+; AVX2-NEXT: movl %ecx, %edx
+; AVX2-NEXT: shrb $6, %dl
+; AVX2-NEXT: movzbl %dl, %edx
+; AVX2-NEXT: movq -48(%rsp,%rdx,8), %rsi
+; AVX2-NEXT: movq -56(%rsp,%rdx,8), %rdi
+; AVX2-NEXT: movq %rdi, %r8
+; AVX2-NEXT: shrdq %cl, %rsi, %r8
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
+; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
+; AVX2-NEXT: movq -72(%rsp,%rdx,8), %r9
; AVX2-NEXT: movq -64(%rsp,%rdx,8), %rdx
; AVX2-NEXT: movq %rdx, %r10
-; AVX2-NEXT: shrdq %cl, %r8, %r10
-; AVX2-NEXT: shrdq %cl, %rdx, %rdi
+; AVX2-NEXT: shrdq %cl, %rdi, %r10
+; AVX2-NEXT: shrdq %cl, %rdx, %r9
; AVX2-NEXT: xorl %edx, %edx
; AVX2-NEXT: vptest %ymm0, %ymm0
; AVX2-NEXT: shrxq %rcx, %rsi, %rcx
; AVX2-NEXT: cmoveq %rdx, %r10
+; AVX2-NEXT: cmoveq %rdx, %r8
; AVX2-NEXT: cmoveq %rdx, %r9
-; AVX2-NEXT: cmoveq %rdx, %rdi
; AVX2-NEXT: cmoveq %rdx, %rcx
; AVX2-NEXT: movq %rcx, 24(%rax)
-; AVX2-NEXT: movq %r9, 16(%rax)
+; AVX2-NEXT: movq %r8, 16(%rax)
; AVX2-NEXT: movq %r10, 8(%rax)
-; AVX2-NEXT: movq %rdi, (%rax)
+; AVX2-NEXT: movq %r9, (%rax)
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
; AVX512F-LABEL: isolate_msb_i256_load:
; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovdqu (%rsi), %ymm0
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,9223372036854775808,0,0,0,0]
-; AVX512F-NEXT: vmovups %zmm1, -{{[0-9]+}}(%rsp)
-; AVX512F-NEXT: vpermq {{.*#+}} ymm1 = ymm0[3,2,1,0]
-; AVX512F-NEXT: vptestmq %zmm1, %zmm1, %k0
-; AVX512F-NEXT: vplzcntq %zmm1, %zmm1
-; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
+; AVX512F-NEXT: movq %rdi, %rax
+; AVX512F-NEXT: vmovq {{.*#+}} xmm3 = mem[0],zero
+; AVX512F-NEXT: vmovq {{.*#+}} xmm4 = mem[0],zero
+; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm4[0],xmm3[0]
+; AVX512F-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
+; AVX512F-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero
+; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm5 = xmm1[0],xmm2[0]
+; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0]
+; AVX512F-NEXT: vinserti128 $1, %xmm5, %ymm3, %ymm3
+; AVX512F-NEXT: vplzcntq %zmm3, %zmm4
+; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4 # [0,64,128,192]
+; AVX512F-NEXT: vptestmq %zmm3, %zmm3, %k0
; AVX512F-NEXT: kshiftlw $12, %k0, %k0
; AVX512F-NEXT: kshiftrw $12, %k0, %k1
-; AVX512F-NEXT: vpcompressq %zmm1, %zmm1 {%k1} {z}
-; AVX512F-NEXT: vmovd %xmm1, %ecx
-; AVX512F-NEXT: movl %ecx, %eax
-; AVX512F-NEXT: shrb $6, %al
-; AVX512F-NEXT: movzbl %al, %edx
+; AVX512F-NEXT: vpcompressq %zmm4, %zmm3 {%k1}
+; AVX512F-NEXT: vmovaps {{.*#+}} zmm4 = [0,0,0,9223372036854775808,0,0,0,0]
+; AVX512F-NEXT: vmovups %zmm4, -{{[0-9]+}}(%rsp)
+; AVX512F-NEXT: vmovd %xmm3, %ecx
+; AVX512F-NEXT: movl %ecx, %edx
+; AVX512F-NEXT: shrb $6, %dl
+; AVX512F-NEXT: movzbl %dl, %edx
; AVX512F-NEXT: movq -48(%rsp,%rdx,8), %rsi
-; AVX512F-NEXT: movq -56(%rsp,%rdx,8), %r8
-; AVX512F-NEXT: movq %r8, %r9
-; AVX512F-NEXT: shrdq %cl, %rsi, %r9
-; AVX512F-NEXT: movq %rdi, %rax
-; AVX512F-NEXT: movq -72(%rsp,%rdx,8), %rdi
+; AVX512F-NEXT: movq -56(%rsp,%rdx,8), %rdi
+; AVX512F-NEXT: movq %rdi, %r8
+; AVX512F-NEXT: shrdq %cl, %rsi, %r8
+; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
+; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
+; AVX512F-NEXT: movq -72(%rsp,%rdx,8), %r9
; AVX512F-NEXT: movq -64(%rsp,%rdx,8), %rdx
; AVX512F-NEXT: movq %rdx, %r10
-; AVX512F-NEXT: shrdq %cl, %r8, %r10
-; AVX512F-NEXT: shrdq %cl, %rdx, %rdi
+; AVX512F-NEXT: shrdq %cl, %rdi, %r10
+; AVX512F-NEXT: shrdq %cl, %rdx, %r9
; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k0
; AVX512F-NEXT: xorl %edx, %edx
; AVX512F-NEXT: kortestw %k0, %k0
; AVX512F-NEXT: shrxq %rcx, %rsi, %rcx
; AVX512F-NEXT: cmoveq %rdx, %r10
+; AVX512F-NEXT: cmoveq %rdx, %r8
; AVX512F-NEXT: cmoveq %rdx, %r9
-; AVX512F-NEXT: cmoveq %rdx, %rdi
; AVX512F-NEXT: cmoveq %rdx, %rcx
; AVX512F-NEXT: movq %rcx, 24(%rax)
-; AVX512F-NEXT: movq %r9, 16(%rax)
+; AVX512F-NEXT: movq %r8, 16(%rax)
; AVX512F-NEXT: movq %r10, 8(%rax)
-; AVX512F-NEXT: movq %rdi, (%rax)
+; AVX512F-NEXT: movq %r9, (%rax)
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: isolate_msb_i256_load:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovdqu (%rsi), %ymm0
+; AVX512VL-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
+; AVX512VL-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
+; AVX512VL-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero
+; AVX512VL-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; AVX512VL-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
+; AVX512VL-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX512VL-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
; AVX512VL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[3,2,1,0]
; AVX512VL-NEXT: vptestmq %ymm1, %ymm1, %k1
; AVX512VL-NEXT: vplzcntq %ymm1, %ymm1
; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
-; AVX512VL-NEXT: vpcompressq %ymm1, %ymm1 {%k1} {z}
-; AVX512VL-NEXT: vxorps %xmm2, %xmm2, %xmm2
-; AVX512VL-NEXT: vmovups %ymm2, -{{[0-9]+}}(%rsp)
+; AVX512VL-NEXT: vpcompressq %ymm1, %ymm1 {%k1}
+; AVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX512VL-NEXT: vmovdqu %ymm2, -{{[0-9]+}}(%rsp)
; AVX512VL-NEXT: vmovaps {{.*#+}} ymm2 = [0,0,0,9223372036854775808]
; AVX512VL-NEXT: vmovups %ymm2, -{{[0-9]+}}(%rsp)
; AVX512VL-NEXT: vmovd %xmm1, %ecx
@@ -3233,14 +3295,20 @@ define i256 @isolate_msb_i256_load(ptr %p0, i256 %idx) nounwind {
;
; AVX512VBMI-LABEL: isolate_msb_i256_load:
; AVX512VBMI: # %bb.0:
-; AVX512VBMI-NEXT: vmovdqu (%rsi), %ymm0
+; AVX512VBMI-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
+; AVX512VBMI-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
+; AVX512VBMI-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero
+; AVX512VBMI-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; AVX512VBMI-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
+; AVX512VBMI-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX512VBMI-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
; AVX512VBMI-NEXT: vpermq {{.*#+}} ymm1 = ymm0[3,2,1,0]
; AVX512VBMI-NEXT: vptestmq %ymm1, %ymm1, %k1
; AVX512VBMI-NEXT: vplzcntq %ymm1, %ymm1
; AVX512VBMI-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
-; AVX512VBMI-NEXT: vpcompressq %ymm1, %ymm1 {%k1} {z}
-; AVX512VBMI-NEXT: vxorps %xmm2, %xmm2, %xmm2
-; AVX512VBMI-NEXT: vmovups %ymm2, -{{[0-9]+}}(%rsp)
+; AVX512VBMI-NEXT: vpcompressq %ymm1, %ymm1 {%k1}
+; AVX512VBMI-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX512VBMI-NEXT: vmovdqu %ymm2, -{{[0-9]+}}(%rsp)
; AVX512VBMI-NEXT: vmovaps {{.*#+}} ymm2 = [0,0,0,9223372036854775808]
; AVX512VBMI-NEXT: vmovups %ymm2, -{{[0-9]+}}(%rsp)
; AVX512VBMI-NEXT: vmovd %xmm1, %ecx
diff --git a/llvm/test/CodeGen/X86/bit-manip-i512.ll b/llvm/test/CodeGen/X86/bit-manip-i512.ll
index 461b5eed3250b..77872fe167e36 100644
--- a/llvm/test/CodeGen/X86/bit-manip-i512.ll
+++ b/llvm/test/CodeGen/X86/bit-manip-i512.ll
@@ -4112,58 +4112,57 @@ define i512 @isolate_msb_i512(i512 %a0, i512 %idx) nounwind {
; SSE-NEXT: pushq %r12
; SSE-NEXT: pushq %rbx
; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r11
-; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx
; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r14
+; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx
; SSE-NEXT: movq %r8, %r10
; SSE-NEXT: orq %r14, %r10
; SSE-NEXT: movq %rdx, %rax
-; SSE-NEXT: orq %r11, %rax
+; SSE-NEXT: orq %rbx, %rax
; SSE-NEXT: orq %r10, %rax
-; SSE-NEXT: movq %rcx, %r15
-; SSE-NEXT: orq %rbx, %r15
-; SSE-NEXT: movq %rsi, %r10
-; SSE-NEXT: orq %r9, %r10
+; SSE-NEXT: movq %rsi, %r15
+; SSE-NEXT: orq %r9, %r15
+; SSE-NEXT: movq %rcx, %r10
+; SSE-NEXT: orq %r11, %r10
; SSE-NEXT: orq %r15, %r10
; SSE-NEXT: bsrq %r14, %r15
-; SSE-NEXT: xorq $63, %r15
-; SSE-NEXT: bsrq %rbx, %r12
-; SSE-NEXT: xorq $63, %r12
-; SSE-NEXT: orq $64, %r12
+; SSE-NEXT: xorl $63, %r15d
+; SSE-NEXT: bsrq %r11, %r12
+; SSE-NEXT: xorl $63, %r12d
+; SSE-NEXT: addl $64, %r12d
; SSE-NEXT: testq %r14, %r14
-; SSE-NEXT: cmovneq %r15, %r12
-; SSE-NEXT: bsrq %r11, %r13
-; SSE-NEXT: xorq $63, %r13
+; SSE-NEXT: cmovnel %r15d, %r12d
+; SSE-NEXT: bsrq %rbx, %r13
+; SSE-NEXT: xorl $63, %r13d
; SSE-NEXT: bsrq %r9, %r15
-; SSE-NEXT: xorq $63, %r15
-; SSE-NEXT: orq $64, %r15
-; SSE-NEXT: testq %r11, %r11
-; SSE-NEXT: cmovneq %r13, %r15
-; SSE-NEXT: orq $128, %r15
-; SSE-NEXT: movq %rbx, %r13
+; SSE-NEXT: xorl $63, %r15d
+; SSE-NEXT: addl $64, %r15d
+; SSE-NEXT: testq %rbx, %rbx
+; SSE-NEXT: cmovnel %r13d, %r15d
+; SSE-NEXT: subl $-128, %r15d
+; SSE-NEXT: movq %r11, %r13
; SSE-NEXT: orq %r14, %r13
-; SSE-NEXT: cmovneq %r12, %r15
+; SSE-NEXT: cmovnel %r12d, %r15d
; SSE-NEXT: bsrq %r8, %r12
-; SSE-NEXT: xorq $63, %r12
+; SSE-NEXT: xorl $63, %r12d
; SSE-NEXT: bsrq %rcx, %r13
-; SSE-NEXT: xorq $63, %r13
-; SSE-NEXT: orq $64, %r13
+; SSE-NEXT: xorl $63, %r13d
+; SSE-NEXT: addl $64, %r13d
; SSE-NEXT: testq %r8, %r8
-; SSE-NEXT: cmovneq %r12, %r13
+; SSE-NEXT: cmovnel %r12d, %r13d
; SSE-NEXT: bsrq %rdx, %r12
-; SSE-NEXT: xorq $63, %r12
+; SSE-NEXT: xorl $63, %r12d
; SSE-NEXT: bsrq %rsi, %rsi
-; SSE-NEXT: xorq $63, %rsi
-; SSE-NEXT: orq $64, %rsi
+; SSE-NEXT: xorl $63, %esi
+; SSE-NEXT: addl $64, %esi
; SSE-NEXT: testq %rdx, %rdx
-; SSE-NEXT: cmovneq %r12, %rsi
-; SSE-NEXT: orq $128, %rsi
+; SSE-NEXT: cmovnel %r12d, %esi
+; SSE-NEXT: subl $-128, %esi
; SSE-NEXT: orq %r8, %rcx
-; SSE-NEXT: cmovneq %r13, %rsi
-; SSE-NEXT: orq $256, %rsi # imm = 0x100
-; SSE-NEXT: orq %r14, %r11
-; SSE-NEXT: orq %rbx, %r9
+; SSE-NEXT: cmovnel %r13d, %esi
+; SSE-NEXT: addl $256, %esi # imm = 0x100
+; SSE-NEXT: orq %r14, %rbx
; SSE-NEXT: orq %r11, %r9
-; SSE-NEXT: cmovneq %r15, %rsi
+; SSE-NEXT: orq %rbx, %r9
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
@@ -4174,6 +4173,7 @@ define i512 @isolate_msb_i512(i512 %a0, i512 %idx) nounwind {
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
+; SSE-NEXT: cmovnel %r15d, %esi
; SSE-NEXT: movl %esi, %ecx
; SSE-NEXT: andl $63, %ecx
; SSE-NEXT: shrl $3, %esi
@@ -4230,124 +4230,119 @@ define i512 @isolate_msb_i512(i512 %a0, i512 %idx) nounwind {
;
; AVX2-LABEL: isolate_msb_i512:
; AVX2: # %bb.0:
-; AVX2-NEXT: pushq %rbp
; AVX2-NEXT: pushq %r15
; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %r13
; AVX2-NEXT: pushq %r12
; AVX2-NEXT: pushq %rbx
-; AVX2-NEXT: pushq %rax
; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rbx
; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r14
-; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r15
-; AVX2-NEXT: movq %r8, %rax
-; AVX2-NEXT: orq %r15, %rax
+; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; AVX2-NEXT: movq %r8, %r11
+; AVX2-NEXT: orq %r14, %r11
; AVX2-NEXT: movq %rdx, %r10
-; AVX2-NEXT: orq %rbx, %r10
; AVX2-NEXT: orq %rax, %r10
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: orq %r14, %rax
-; AVX2-NEXT: movq %rsi, %r11
-; AVX2-NEXT: orq %r9, %r11
-; AVX2-NEXT: orq %rax, %r11
-; AVX2-NEXT: xorl %eax, %eax
-; AVX2-NEXT: lzcntq %r15, %rax
+; AVX2-NEXT: orq %r11, %r10
+; AVX2-NEXT: movq %rsi, %r15
+; AVX2-NEXT: orq %r9, %r15
+; AVX2-NEXT: movq %rcx, %r11
+; AVX2-NEXT: orq %rbx, %r11
+; AVX2-NEXT: orq %r15, %r11
+; AVX2-NEXT: xorl %r15d, %r15d
+; AVX2-NEXT: lzcntq %r14, %r15
+; AVX2-NEXT: xorl %r12d, %r12d
+; AVX2-NEXT: lzcntq %rbx, %r12
+; AVX2-NEXT: addl $64, %r12d
+; AVX2-NEXT: testq %r14, %r14
+; AVX2-NEXT: cmovnel %r15d, %r12d
; AVX2-NEXT: xorl %r13d, %r13d
-; AVX2-NEXT: lzcntq %r14, %r13
-; AVX2-NEXT: addq $64, %r13
-; AVX2-NEXT: testq %r15, %r15
-; AVX2-NEXT: cmovneq %rax, %r13
-; AVX2-NEXT: xorl %eax, %eax
-; AVX2-NEXT: lzcntq %rbx, %rax
+; AVX2-NEXT: lzcntq %rax, %r13
+; AVX2-NEXT: xorl %r15d, %r15d
+; AVX2-NEXT: lzcntq %r9, %r15
+; AVX2-NEXT: addl $64, %r15d
+; AVX2-NEXT: testq %rax, %rax
+; AVX2-NEXT: cmovnel %r13d, %r15d
+; AVX2-NEXT: subl $-128, %r15d
+; AVX2-NEXT: movq %rbx, %r13
+; AVX2-NEXT: orq %r14, %r13
+; AVX2-NEXT: cmovnel %r12d, %r15d
; AVX2-NEXT: xorl %r12d, %r12d
-; AVX2-NEXT: lzcntq %r9, %r12
-; AVX2-NEXT: addq $64, %r12
-; AVX2-NEXT: testq %rbx, %rbx
-; AVX2-NEXT: cmovneq %rax, %r12
-; AVX2-NEXT: subq $-128, %r12
-; AVX2-NEXT: movq %r14, %rax
-; AVX2-NEXT: orq %r15, %rax
-; AVX2-NEXT: cmovneq %r13, %r12
-; AVX2-NEXT: xorl %eax, %eax
-; AVX2-NEXT: lzcntq %r8, %rax
+; AVX2-NEXT: lzcntq %r8, %r12
; AVX2-NEXT: xorl %r13d, %r13d
; AVX2-NEXT: lzcntq %rcx, %r13
-; AVX2-NEXT: addq $64, %r13
+; AVX2-NEXT: addl $64, %r13d
; AVX2-NEXT: testq %r8, %r8
-; AVX2-NEXT: cmovneq %rax, %r13
-; AVX2-NEXT: xorl %ebp, %ebp
-; AVX2-NEXT: lzcntq %rdx, %rbp
-; AVX2-NEXT: xorl %eax, %eax
-; AVX2-NEXT: lzcntq %rsi, %rax
-; AVX2-NEXT: addq $64, %rax
+; AVX2-NEXT: cmovnel %r12d, %r13d
+; AVX2-NEXT: xorl %r12d, %r12d
+; AVX2-NEXT: lzcntq %rdx, %r12
+; AVX2-NEXT: lzcntq %rsi, %rsi
+; AVX2-NEXT: addl $64, %esi
; AVX2-NEXT: testq %rdx, %rdx
-; AVX2-NEXT: cmovneq %rbp, %rax
-; AVX2-NEXT: subq $-128, %rax
+; AVX2-NEXT: cmovnel %r12d, %esi
+; AVX2-NEXT: subl $-128, %esi
; AVX2-NEXT: orq %r8, %rcx
-; AVX2-NEXT: cmovneq %r13, %rax
-; AVX2-NEXT: addq $256, %rax # imm = 0x100
-; AVX2-NEXT: orq %r15, %rbx
-; AVX2-NEXT: orq %r14, %r9
-; AVX2-NEXT: orq %rbx, %r9
-; AVX2-NEXT: cmovneq %r12, %rax
+; AVX2-NEXT: cmovnel %r13d, %esi
+; AVX2-NEXT: addl $256, %esi # imm = 0x100
+; AVX2-NEXT: orq %r14, %rax
; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: orq %rbx, %r9
; AVX2-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,9223372036854775808]
; AVX2-NEXT: vmovups %ymm1, -{{[0-9]+}}(%rsp)
; AVX2-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movl %eax, %ecx
+; AVX2-NEXT: orq %rax, %r9
+; AVX2-NEXT: cmovnel %r15d, %esi
+; AVX2-NEXT: movl %esi, %ecx
; AVX2-NEXT: andl $63, %ecx
-; AVX2-NEXT: shrl $3, %eax
-; AVX2-NEXT: andl $56, %eax
-; AVX2-NEXT: movq -72(%rsp,%rax), %rbx
-; AVX2-NEXT: movq -80(%rsp,%rax), %r8
-; AVX2-NEXT: movq %r8, %rdx
-; AVX2-NEXT: shrdq %cl, %rbx, %rdx
-; AVX2-NEXT: movq -88(%rsp,%rax), %r9
-; AVX2-NEXT: movq %r9, %rsi
-; AVX2-NEXT: shrdq %cl, %r8, %rsi
-; AVX2-NEXT: movq -96(%rsp,%rax), %r14
-; AVX2-NEXT: movq %r14, %r8
-; AVX2-NEXT: shrdq %cl, %r9, %r8
-; AVX2-NEXT: movq -104(%rsp,%rax), %r15
-; AVX2-NEXT: movq %r15, %r9
-; AVX2-NEXT: shrdq %cl, %r14, %r9
-; AVX2-NEXT: movq -112(%rsp,%rax), %r13
-; AVX2-NEXT: movq %r13, %r14
-; AVX2-NEXT: shrdq %cl, %r15, %r14
-; AVX2-NEXT: movq -128(%rsp,%rax), %r15
-; AVX2-NEXT: movq -120(%rsp,%rax), %rax
-; AVX2-NEXT: movq %rax, %r12
+; AVX2-NEXT: shrl $3, %esi
+; AVX2-NEXT: andl $56, %esi
+; AVX2-NEXT: movq -72(%rsp,%rsi), %r14
+; AVX2-NEXT: movq -80(%rsp,%rsi), %rax
+; AVX2-NEXT: movq %rax, %rdx
+; AVX2-NEXT: shrdq %cl, %r14, %rdx
+; AVX2-NEXT: movq -88(%rsp,%rsi), %rbx
+; AVX2-NEXT: movq %rbx, %r8
+; AVX2-NEXT: shrdq %cl, %rax, %r8
+; AVX2-NEXT: movq -96(%rsp,%rsi), %rax
+; AVX2-NEXT: movq %rax, %r9
+; AVX2-NEXT: shrdq %cl, %rbx, %r9
+; AVX2-NEXT: movq -104(%rsp,%rsi), %r12
+; AVX2-NEXT: movq %r12, %rbx
+; AVX2-NEXT: shrdq %cl, %rax, %rbx
+; AVX2-NEXT: movq -112(%rsp,%rsi), %rax
+; AVX2-NEXT: movq %rax, %r15
+; AVX2-NEXT: shrdq %cl, %r12, %r15
+; AVX2-NEXT: movq -128(%rsp,%rsi), %r12
+; AVX2-NEXT: movq -120(%rsp,%rsi), %r13
+; AVX2-NEXT: movq %r13, %rsi
+; AVX2-NEXT: shrdq %cl, %rax, %rsi
; AVX2-NEXT: shrdq %cl, %r13, %r12
-; AVX2-NEXT: shrdq %cl, %rax, %r15
; AVX2-NEXT: movq %rdi, %rax
; AVX2-NEXT: xorl %edi, %edi
; AVX2-NEXT: orq %r10, %r11
-; AVX2-NEXT: shrxq %rcx, %rbx, %rcx
-; AVX2-NEXT: cmoveq %rdi, %r12
-; AVX2-NEXT: cmoveq %rdi, %r14
+; AVX2-NEXT: shrxq %rcx, %r14, %rcx
+; AVX2-NEXT: cmoveq %rdi, %rsi
+; AVX2-NEXT: cmoveq %rdi, %r15
+; AVX2-NEXT: cmoveq %rdi, %rbx
; AVX2-NEXT: cmoveq %rdi, %r9
; AVX2-NEXT: cmoveq %rdi, %r8
-; AVX2-NEXT: cmoveq %rdi, %rsi
; AVX2-NEXT: cmoveq %rdi, %rdx
-; AVX2-NEXT: cmoveq %rdi, %r15
+; AVX2-NEXT: cmoveq %rdi, %r12
; AVX2-NEXT: cmoveq %rdi, %rcx
; AVX2-NEXT: movq %rcx, 56(%rax)
; AVX2-NEXT: movq %rdx, 48(%rax)
-; AVX2-NEXT: movq %rsi, 40(%rax)
-; AVX2-NEXT: movq %r8, 32(%rax)
-; AVX2-NEXT: movq %r9, 24(%rax)
-; AVX2-NEXT: movq %r14, 16(%rax)
-; AVX2-NEXT: movq %r12, 8(%rax)
-; AVX2-NEXT: movq %r15, (%rax)
-; AVX2-NEXT: addq $8, %rsp
+; AVX2-NEXT: movq %r8, 40(%rax)
+; AVX2-NEXT: movq %r9, 32(%rax)
+; AVX2-NEXT: movq %rbx, 24(%rax)
+; AVX2-NEXT: movq %r15, 16(%rax)
+; AVX2-NEXT: movq %rsi, 8(%rax)
+; AVX2-NEXT: movq %r12, (%rax)
; AVX2-NEXT: popq %rbx
; AVX2-NEXT: popq %r12
; AVX2-NEXT: popq %r13
; AVX2-NEXT: popq %r14
; AVX2-NEXT: popq %r15
-; AVX2-NEXT: popq %rbp
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
@@ -4524,49 +4519,48 @@ define i512 @isolate_msb_i512_vector(<8 x i64> %v0, i512 %idx) nounwind {
; SSE2-NEXT: movmskps %xmm0, %eax
; SSE2-NEXT: xorl $15, %eax
; SSE2-NEXT: bsrq %rbx, %r14
-; SSE2-NEXT: xorq $63, %r14
+; SSE2-NEXT: xorl $63, %r14d
; SSE2-NEXT: bsrq %r10, %r10
-; SSE2-NEXT: xorq $63, %r10
-; SSE2-NEXT: orq $64, %r10
+; SSE2-NEXT: xorl $63, %r10d
+; SSE2-NEXT: addl $64, %r10d
; SSE2-NEXT: testq %rbx, %rbx
-; SSE2-NEXT: cmovneq %r14, %r10
+; SSE2-NEXT: cmovnel %r14d, %r10d
; SSE2-NEXT: bsrq %r11, %rbx
-; SSE2-NEXT: xorq $63, %rbx
+; SSE2-NEXT: xorl $63, %ebx
; SSE2-NEXT: bsrq %r9, %r9
-; SSE2-NEXT: xorq $63, %r9
-; SSE2-NEXT: orq $64, %r9
+; SSE2-NEXT: xorl $63, %r9d
+; SSE2-NEXT: addl $64, %r9d
; SSE2-NEXT: testq %r11, %r11
-; SSE2-NEXT: cmovneq %rbx, %r9
-; SSE2-NEXT: orq $128, %r9
+; SSE2-NEXT: cmovnel %ebx, %r9d
+; SSE2-NEXT: subl $-128, %r9d
; SSE2-NEXT: por %xmm3, %xmm2
; SSE2-NEXT: pcmpeqd %xmm4, %xmm3
; SSE2-NEXT: movmskps %xmm3, %r11d
; SSE2-NEXT: xorl $15, %r11d
-; SSE2-NEXT: cmovneq %r10, %r9
+; SSE2-NEXT: cmovnel %r10d, %r9d
; SSE2-NEXT: bsrq %rsi, %r10
-; SSE2-NEXT: xorq $63, %r10
+; SSE2-NEXT: xorl $63, %r10d
; SSE2-NEXT: bsrq %r8, %r8
-; SSE2-NEXT: xorq $63, %r8
-; SSE2-NEXT: orq $64, %r8
+; SSE2-NEXT: xorl $63, %r8d
+; SSE2-NEXT: addl $64, %r8d
; SSE2-NEXT: testq %rsi, %rsi
-; SSE2-NEXT: cmovneq %r10, %r8
+; SSE2-NEXT: cmovnel %r10d, %r8d
; SSE2-NEXT: bsrq %rcx, %rsi
-; SSE2-NEXT: xorq $63, %rsi
+; SSE2-NEXT: xorl $63, %esi
; SSE2-NEXT: bsrq %rdx, %rdx
-; SSE2-NEXT: xorq $63, %rdx
-; SSE2-NEXT: orq $64, %rdx
+; SSE2-NEXT: xorl $63, %edx
+; SSE2-NEXT: addl $64, %edx
; SSE2-NEXT: testq %rcx, %rcx
-; SSE2-NEXT: cmovneq %rsi, %rdx
-; SSE2-NEXT: orq $128, %rdx
+; SSE2-NEXT: cmovnel %esi, %edx
+; SSE2-NEXT: subl $-128, %edx
; SSE2-NEXT: pcmpeqd %xmm4, %xmm1
; SSE2-NEXT: movmskps %xmm1, %ecx
; SSE2-NEXT: xorl $15, %ecx
-; SSE2-NEXT: cmovneq %r8, %rdx
-; SSE2-NEXT: orq $256, %rdx # imm = 0x100
+; SSE2-NEXT: cmovnel %r8d, %edx
+; SSE2-NEXT: addl $256, %edx # imm = 0x100
; SSE2-NEXT: pcmpeqd %xmm4, %xmm2
; SSE2-NEXT: movmskps %xmm2, %ecx
; SSE2-NEXT: xorl $15, %ecx
-; SSE2-NEXT: cmovneq %r9, %rdx
; SSE2-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp)
@@ -4576,6 +4570,7 @@ define i512 @isolate_msb_i512_vector(<8 x i64> %v0, i512 %idx) nounwind {
; SSE2-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: cmovnel %r9d, %edx
; SSE2-NEXT: movl %edx, %ecx
; SSE2-NEXT: andl $63, %ecx
; SSE2-NEXT: shrl $3, %edx
@@ -4637,51 +4632,50 @@ define i512 @isolate_msb_i512_vector(<8 x i64> %v0, i512 %idx) nounwind {
; SSE42-NEXT: pushq %rbx
; SSE42-NEXT: movq %xmm0, %rax
; SSE42-NEXT: pextrq $1, %xmm0, %rcx
-; SSE42-NEXT: pextrq $1, %xmm1, %rdx
+; SSE42-NEXT: pextrq $1, %xmm1, %rsi
; SSE42-NEXT: movq %xmm1, %r8
-; SSE42-NEXT: movq %xmm2, %rsi
+; SSE42-NEXT: movq %xmm2, %rdx
; SSE42-NEXT: pextrq $1, %xmm2, %r9
; SSE42-NEXT: movq %xmm3, %r10
; SSE42-NEXT: pextrq $1, %xmm3, %r11
; SSE42-NEXT: bsrq %r11, %rbx
-; SSE42-NEXT: xorq $63, %rbx
+; SSE42-NEXT: xorl $63, %ebx
; SSE42-NEXT: bsrq %r10, %r10
-; SSE42-NEXT: xorq $63, %r10
-; SSE42-NEXT: orq $64, %r10
+; SSE42-NEXT: xorl $63, %r10d
+; SSE42-NEXT: addl $64, %r10d
; SSE42-NEXT: testq %r11, %r11
-; SSE42-NEXT: cmovneq %rbx, %r10
+; SSE42-NEXT: cmovnel %ebx, %r10d
; SSE42-NEXT: bsrq %r9, %r11
-; SSE42-NEXT: xorq $63, %r11
-; SSE42-NEXT: bsrq %rsi, %rsi
-; SSE42-NEXT: xorq $63, %rsi
-; SSE42-NEXT: orq $64, %rsi
+; SSE42-NEXT: xorl $63, %r11d
+; SSE42-NEXT: bsrq %rdx, %rdx
+; SSE42-NEXT: xorl $63, %edx
+; SSE42-NEXT: addl $64, %edx
; SSE42-NEXT: testq %r9, %r9
-; SSE42-NEXT: cmovneq %r11, %rsi
-; SSE42-NEXT: orq $128, %rsi
+; SSE42-NEXT: cmovnel %r11d, %edx
+; SSE42-NEXT: subl $-128, %edx
; SSE42-NEXT: ptest %xmm3, %xmm3
-; SSE42-NEXT: cmovneq %r10, %rsi
-; SSE42-NEXT: bsrq %rdx, %r9
-; SSE42-NEXT: xorq $63, %r9
+; SSE42-NEXT: cmovnel %r10d, %edx
+; SSE42-NEXT: bsrq %rsi, %r9
+; SSE42-NEXT: xorl $63, %r9d
; SSE42-NEXT: bsrq %r8, %r8
-; SSE42-NEXT: xorq $63, %r8
-; SSE42-NEXT: orq $64, %r8
-; SSE42-NEXT: testq %rdx, %rdx
-; SSE42-NEXT: cmovneq %r9, %r8
-; SSE42-NEXT: bsrq %rcx, %rdx
-; SSE42-NEXT: xorq $63, %rdx
+; SSE42-NEXT: xorl $63, %r8d
+; SSE42-NEXT: addl $64, %r8d
+; SSE42-NEXT: testq %rsi, %rsi
+; SSE42-NEXT: cmovnel %r9d, %r8d
+; SSE42-NEXT: bsrq %rcx, %rsi
+; SSE42-NEXT: xorl $63, %esi
; SSE42-NEXT: bsrq %rax, %rax
-; SSE42-NEXT: xorq $63, %rax
-; SSE42-NEXT: orq $64, %rax
+; SSE42-NEXT: xorl $63, %eax
+; SSE42-NEXT: addl $64, %eax
; SSE42-NEXT: testq %rcx, %rcx
-; SSE42-NEXT: cmovneq %rdx, %rax
-; SSE42-NEXT: por %xmm2, %xmm0
-; SSE42-NEXT: orq $128, %rax
+; SSE42-NEXT: cmovnel %esi, %eax
+; SSE42-NEXT: subl $-128, %eax
; SSE42-NEXT: ptest %xmm1, %xmm1
-; SSE42-NEXT: cmovneq %r8, %rax
-; SSE42-NEXT: orq $256, %rax # imm = 0x100
+; SSE42-NEXT: por %xmm2, %xmm0
+; SSE42-NEXT: cmovnel %r8d, %eax
+; SSE42-NEXT: addl $256, %eax # imm = 0x100
; SSE42-NEXT: por %xmm3, %xmm2
; SSE42-NEXT: ptest %xmm2, %xmm2
-; SSE42-NEXT: cmovneq %rsi, %rax
; SSE42-NEXT: pxor %xmm2, %xmm2
; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
@@ -4692,6 +4686,7 @@ define i512 @isolate_msb_i512_vector(<8 x i64> %v0, i512 %idx) nounwind {
; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: cmovnel %edx, %eax
; SSE42-NEXT: movl %eax, %ecx
; SSE42-NEXT: andl $63, %ecx
; SSE42-NEXT: shrl $3, %eax
@@ -4769,39 +4764,39 @@ define i512 @isolate_msb_i512_vector(<8 x i64> %v0, i512 %idx) nounwind {
; AVX2-NEXT: lzcntq %rsi, %rbx
; AVX2-NEXT: xorl %r14d, %r14d
; AVX2-NEXT: lzcntq %rdx, %r14
-; AVX2-NEXT: addq $64, %r14
+; AVX2-NEXT: addl $64, %r14d
; AVX2-NEXT: testq %rsi, %rsi
-; AVX2-NEXT: cmovneq %rbx, %r14
+; AVX2-NEXT: cmovnel %ebx, %r14d
; AVX2-NEXT: xorl %ebx, %ebx
; AVX2-NEXT: lzcntq %r11, %rbx
; AVX2-NEXT: lzcntq %r10, %r10
-; AVX2-NEXT: addq $64, %r10
+; AVX2-NEXT: addl $64, %r10d
; AVX2-NEXT: testq %r11, %r11
-; AVX2-NEXT: cmovneq %rbx, %r10
-; AVX2-NEXT: subq $-128, %r10
+; AVX2-NEXT: cmovnel %ebx, %r10d
+; AVX2-NEXT: subl $-128, %r10d
; AVX2-NEXT: orq %rsi, %rdx
-; AVX2-NEXT: cmovneq %r14, %r10
+; AVX2-NEXT: cmovnel %r14d, %r10d
; AVX2-NEXT: xorl %edx, %edx
; AVX2-NEXT: lzcntq %rcx, %rdx
; AVX2-NEXT: xorl %esi, %esi
; AVX2-NEXT: lzcntq %rax, %rsi
-; AVX2-NEXT: addq $64, %rsi
+; AVX2-NEXT: addl $64, %esi
; AVX2-NEXT: testq %rcx, %rcx
-; AVX2-NEXT: cmovneq %rdx, %rsi
+; AVX2-NEXT: cmovnel %edx, %esi
; AVX2-NEXT: xorl %edx, %edx
; AVX2-NEXT: lzcntq %r9, %rdx
; AVX2-NEXT: lzcntq %r8, %r8
-; AVX2-NEXT: addq $64, %r8
+; AVX2-NEXT: addl $64, %r8d
; AVX2-NEXT: testq %r9, %r9
-; AVX2-NEXT: cmovneq %rdx, %r8
-; AVX2-NEXT: subq $-128, %r8
+; AVX2-NEXT: cmovnel %edx, %r8d
+; AVX2-NEXT: subl $-128, %r8d
; AVX2-NEXT: orq %rcx, %rax
-; AVX2-NEXT: cmovneq %rsi, %r8
-; AVX2-NEXT: addq $256, %r8 # imm = 0x100
+; AVX2-NEXT: cmovnel %esi, %r8d
+; AVX2-NEXT: addl $256, %r8d # imm = 0x100
; AVX2-NEXT: vptest %ymm1, %ymm1
-; AVX2-NEXT: cmovneq %r10, %r8
; AVX2-NEXT: vmovdqu %ymm2, -{{[0-9]+}}(%rsp)
; AVX2-NEXT: vmovdqu %ymm2, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: cmovnel %r10d, %r8d
; AVX2-NEXT: movl %r8d, %ecx
; AVX2-NEXT: andl $63, %ecx
; AVX2-NEXT: shrl $3, %r8d
@@ -4956,72 +4951,82 @@ define i512 @isolate_msb_i512_load(ptr %p0, i512 %idx) nounwind {
; SSE2-NEXT: pushq %r12
; SSE2-NEXT: pushq %rbx
; SSE2-NEXT: pushq %rax
-; SSE2-NEXT: movq 8(%rsi), %r9
-; SSE2-NEXT: movq 16(%rsi), %rcx
-; SSE2-NEXT: movq 24(%rsi), %r8
-; SSE2-NEXT: movq 48(%rsi), %rdx
+; SSE2-NEXT: movq 40(%rsi), %r10
+; SSE2-NEXT: movq %r10, %xmm1
+; SSE2-NEXT: movq 32(%rsi), %r9
+; SSE2-NEXT: movq %r9, %xmm0
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT: movq (%rsi), %rdx
+; SSE2-NEXT: movq 8(%rsi), %rcx
+; SSE2-NEXT: movq %rdx, %xmm3
+; SSE2-NEXT: movq %rcx, %xmm1
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm1[0]
; SSE2-NEXT: movq 56(%rsi), %r11
-; SSE2-NEXT: movdqa 32(%rsi), %xmm1
-; SSE2-NEXT: movdqa 48(%rsi), %xmm2
-; SSE2-NEXT: movdqa 16(%rsi), %xmm0
-; SSE2-NEXT: por %xmm2, %xmm0
-; SSE2-NEXT: movdqa (%rsi), %xmm3
-; SSE2-NEXT: por %xmm1, %xmm3
+; SSE2-NEXT: movq %r11, %xmm2
+; SSE2-NEXT: movq 48(%rsi), %rbx
+; SSE2-NEXT: movq %rbx, %xmm1
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; SSE2-NEXT: movq 24(%rsi), %r8
+; SSE2-NEXT: movq %r8, %xmm2
+; SSE2-NEXT: movq 16(%rsi), %rsi
+; SSE2-NEXT: movq %rsi, %xmm4
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm2[0]
+; SSE2-NEXT: por %xmm1, %xmm4
; SSE2-NEXT: por %xmm0, %xmm3
-; SSE2-NEXT: pxor %xmm0, %xmm0
-; SSE2-NEXT: pcmpeqd %xmm0, %xmm3
+; SSE2-NEXT: por %xmm4, %xmm3
+; SSE2-NEXT: pxor %xmm2, %xmm2
+; SSE2-NEXT: pcmpeqd %xmm2, %xmm3
; SSE2-NEXT: movmskps %xmm3, %eax
; SSE2-NEXT: xorl $15, %eax
-; SSE2-NEXT: bsrq %r11, %r10
-; SSE2-NEXT: xorq $63, %r10
-; SSE2-NEXT: bsrq %rdx, %rbx
-; SSE2-NEXT: xorq $63, %rbx
-; SSE2-NEXT: orq $64, %rbx
+; SSE2-NEXT: bsrq %r11, %r14
+; SSE2-NEXT: xorl $63, %r14d
+; SSE2-NEXT: bsrq %rbx, %r15
+; SSE2-NEXT: xorl $63, %r15d
+; SSE2-NEXT: addl $64, %r15d
; SSE2-NEXT: testq %r11, %r11
-; SSE2-NEXT: cmovneq %r10, %rbx
-; SSE2-NEXT: movq 40(%rsi), %r14
-; SSE2-NEXT: bsrq %r14, %r15
-; SSE2-NEXT: bsrq 32(%rsi), %r10
-; SSE2-NEXT: xorq $63, %r15
-; SSE2-NEXT: xorq $63, %r10
-; SSE2-NEXT: orq $64, %r10
-; SSE2-NEXT: testq %r14, %r14
-; SSE2-NEXT: cmovneq %r15, %r10
-; SSE2-NEXT: orq $128, %r10
-; SSE2-NEXT: orq %r11, %rdx
-; SSE2-NEXT: cmovneq %rbx, %r10
-; SSE2-NEXT: bsrq %r8, %rdx
-; SSE2-NEXT: xorq $63, %rdx
-; SSE2-NEXT: bsrq %rcx, %r11
-; SSE2-NEXT: xorq $63, %r11
-; SSE2-NEXT: orq $64, %r11
+; SSE2-NEXT: cmovnel %r14d, %r15d
+; SSE2-NEXT: bsrq %r10, %r14
+; SSE2-NEXT: xorl $63, %r14d
+; SSE2-NEXT: bsrq %r9, %r9
+; SSE2-NEXT: xorl $63, %r9d
+; SSE2-NEXT: addl $64, %r9d
+; SSE2-NEXT: testq %r10, %r10
+; SSE2-NEXT: cmovnel %r14d, %r9d
+; SSE2-NEXT: subl $-128, %r9d
+; SSE2-NEXT: orq %r11, %rbx
+; SSE2-NEXT: cmovnel %r15d, %r9d
+; SSE2-NEXT: bsrq %r8, %r10
+; SSE2-NEXT: xorl $63, %r10d
+; SSE2-NEXT: bsrq %rsi, %r11
+; SSE2-NEXT: xorl $63, %r11d
+; SSE2-NEXT: addl $64, %r11d
; SSE2-NEXT: testq %r8, %r8
-; SSE2-NEXT: cmovneq %rdx, %r11
-; SSE2-NEXT: bsrq %r9, %rbx
-; SSE2-NEXT: xorq $63, %rbx
-; SSE2-NEXT: bsrq (%rsi), %rdx
-; SSE2-NEXT: xorq $63, %rdx
-; SSE2-NEXT: orq $64, %rdx
-; SSE2-NEXT: testq %r9, %r9
-; SSE2-NEXT: cmovneq %rbx, %rdx
-; SSE2-NEXT: orq $128, %rdx
-; SSE2-NEXT: orq %r8, %rcx
-; SSE2-NEXT: cmovneq %r11, %rdx
-; SSE2-NEXT: orq $256, %rdx # imm = 0x100
-; SSE2-NEXT: por %xmm2, %xmm1
-; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
+; SSE2-NEXT: cmovnel %r10d, %r11d
+; SSE2-NEXT: bsrq %rcx, %r10
+; SSE2-NEXT: xorl $63, %r10d
+; SSE2-NEXT: bsrq %rdx, %rdx
+; SSE2-NEXT: xorl $63, %edx
+; SSE2-NEXT: addl $64, %edx
+; SSE2-NEXT: testq %rcx, %rcx
+; SSE2-NEXT: cmovnel %r10d, %edx
+; SSE2-NEXT: subl $-128, %edx
+; SSE2-NEXT: orq %r8, %rsi
+; SSE2-NEXT: cmovnel %r11d, %edx
+; SSE2-NEXT: addl $256, %edx # imm = 0x100
+; SSE2-NEXT: por %xmm0, %xmm1
+; SSE2-NEXT: pcmpeqd %xmm2, %xmm1
; SSE2-NEXT: movmskps %xmm1, %ecx
; SSE2-NEXT: xorl $15, %ecx
-; SSE2-NEXT: cmovneq %r10, %rdx
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
; SSE2-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: cmovnel %r9d, %edx
; SSE2-NEXT: movl %edx, %ecx
; SSE2-NEXT: andl $63, %ecx
; SSE2-NEXT: shrl $3, %edx
@@ -5080,116 +5085,130 @@ define i512 @isolate_msb_i512_load(ptr %p0, i512 %idx) nounwind {
; SSE42: # %bb.0:
; SSE42-NEXT: pushq %r15
; SSE42-NEXT: pushq %r14
+; SSE42-NEXT: pushq %r13
+; SSE42-NEXT: pushq %r12
; SSE42-NEXT: pushq %rbx
-; SSE42-NEXT: movq 8(%rsi), %r8
-; SSE42-NEXT: movq 16(%rsi), %rcx
-; SSE42-NEXT: movq 24(%rsi), %rdx
-; SSE42-NEXT: movq 40(%rsi), %r11
-; SSE42-NEXT: movq 48(%rsi), %rax
-; SSE42-NEXT: movq 56(%rsi), %r10
-; SSE42-NEXT: movdqa 32(%rsi), %xmm2
-; SSE42-NEXT: movdqa 48(%rsi), %xmm0
-; SSE42-NEXT: movdqa (%rsi), %xmm1
-; SSE42-NEXT: bsrq %r10, %r9
-; SSE42-NEXT: xorq $63, %r9
-; SSE42-NEXT: bsrq %rax, %rbx
-; SSE42-NEXT: xorq $63, %rbx
-; SSE42-NEXT: orq $64, %rbx
-; SSE42-NEXT: testq %r10, %r10
-; SSE42-NEXT: cmovneq %r9, %rbx
-; SSE42-NEXT: bsrq %r11, %r14
-; SSE42-NEXT: xorq $63, %r14
-; SSE42-NEXT: bsrq 32(%rsi), %r9
-; SSE42-NEXT: xorq $63, %r9
-; SSE42-NEXT: orq $64, %r9
+; SSE42-NEXT: movq 40(%rsi), %r10
+; SSE42-NEXT: movq %r10, %xmm1
+; SSE42-NEXT: movq 32(%rsi), %r9
+; SSE42-NEXT: movq %r9, %xmm0
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE42-NEXT: movq (%rsi), %rax
+; SSE42-NEXT: movq 8(%rsi), %rdx
+; SSE42-NEXT: movq 56(%rsi), %r11
+; SSE42-NEXT: movq %r11, %xmm1
+; SSE42-NEXT: movq 48(%rsi), %rbx
+; SSE42-NEXT: movq %rbx, %xmm2
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
+; SSE42-NEXT: movq 24(%rsi), %rcx
+; SSE42-NEXT: movq %rcx, %xmm3
+; SSE42-NEXT: movq 16(%rsi), %r8
+; SSE42-NEXT: movq %r8, %xmm1
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
+; SSE42-NEXT: por %xmm2, %xmm1
+; SSE42-NEXT: bsrq %r11, %rsi
+; SSE42-NEXT: xorl $63, %esi
+; SSE42-NEXT: bsrq %rbx, %r14
+; SSE42-NEXT: xorl $63, %r14d
+; SSE42-NEXT: addl $64, %r14d
; SSE42-NEXT: testq %r11, %r11
-; SSE42-NEXT: cmovneq %r14, %r9
-; SSE42-NEXT: orq $128, %r9
-; SSE42-NEXT: orq %r10, %rax
-; SSE42-NEXT: cmovneq %rbx, %r9
-; SSE42-NEXT: bsrq %rdx, %rax
-; SSE42-NEXT: xorq $63, %rax
-; SSE42-NEXT: bsrq %rcx, %r10
-; SSE42-NEXT: xorq $63, %r10
-; SSE42-NEXT: orq $64, %r10
+; SSE42-NEXT: cmovnel %esi, %r14d
+; SSE42-NEXT: bsrq %r10, %rsi
+; SSE42-NEXT: xorl $63, %esi
+; SSE42-NEXT: bsrq %r9, %r9
+; SSE42-NEXT: xorl $63, %r9d
+; SSE42-NEXT: addl $64, %r9d
+; SSE42-NEXT: testq %r10, %r10
+; SSE42-NEXT: cmovnel %esi, %r9d
+; SSE42-NEXT: subl $-128, %r9d
+; SSE42-NEXT: orq %r11, %rbx
+; SSE42-NEXT: cmovnel %r14d, %r9d
+; SSE42-NEXT: bsrq %rcx, %rsi
+; SSE42-NEXT: xorl $63, %esi
+; SSE42-NEXT: bsrq %r8, %r10
+; SSE42-NEXT: xorl $63, %r10d
+; SSE42-NEXT: addl $64, %r10d
+; SSE42-NEXT: testq %rcx, %rcx
+; SSE42-NEXT: cmovnel %esi, %r10d
+; SSE42-NEXT: bsrq %rdx, %r11
+; SSE42-NEXT: xorl $63, %r11d
+; SSE42-NEXT: bsrq %rax, %rsi
+; SSE42-NEXT: xorl $63, %esi
+; SSE42-NEXT: addl $64, %esi
; SSE42-NEXT: testq %rdx, %rdx
-; SSE42-NEXT: cmovneq %rax, %r10
-; SSE42-NEXT: por %xmm2, %xmm1
-; SSE42-NEXT: bsrq %r8, %r11
-; SSE42-NEXT: bsrq (%rsi), %rax
-; SSE42-NEXT: xorq $63, %r11
-; SSE42-NEXT: xorq $63, %rax
-; SSE42-NEXT: orq $64, %rax
-; SSE42-NEXT: testq %r8, %r8
-; SSE42-NEXT: cmovneq %r11, %rax
-; SSE42-NEXT: orq $128, %rax
-; SSE42-NEXT: orq %rdx, %rcx
-; SSE42-NEXT: cmovneq %r10, %rax
-; SSE42-NEXT: orq $256, %rax # imm = 0x100
+; SSE42-NEXT: cmovnel %r11d, %esi
+; SSE42-NEXT: subl $-128, %esi
+; SSE42-NEXT: orq %rcx, %r8
+; SSE42-NEXT: cmovnel %r10d, %esi
+; SSE42-NEXT: addl $256, %esi # imm = 0x100
; SSE42-NEXT: por %xmm0, %xmm2
; SSE42-NEXT: ptest %xmm2, %xmm2
-; SSE42-NEXT: cmovneq %r9, %rax
-; SSE42-NEXT: movdqa 16(%rsi), %xmm2
-; SSE42-NEXT: xorps %xmm3, %xmm3
-; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: pxor %xmm2, %xmm2
+; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
; SSE42-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movl %eax, %ecx
+; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: cmovnel %r9d, %esi
+; SSE42-NEXT: movl %esi, %ecx
; SSE42-NEXT: andl $63, %ecx
-; SSE42-NEXT: shrl $3, %eax
-; SSE42-NEXT: andl $56, %eax
+; SSE42-NEXT: shrl $3, %esi
+; SSE42-NEXT: andl $56, %esi
; SSE42-NEXT: movq $0, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movq -72(%rsp,%rax), %rdx
-; SSE42-NEXT: movq -80(%rsp,%rax), %r9
-; SSE42-NEXT: movq %r9, %rsi
-; SSE42-NEXT: shrdq %cl, %rdx, %rsi
-; SSE42-NEXT: movq -88(%rsp,%rax), %r10
-; SSE42-NEXT: movq %r10, %r8
-; SSE42-NEXT: shrdq %cl, %r9, %r8
-; SSE42-NEXT: movq -96(%rsp,%rax), %r11
+; SSE42-NEXT: movq -72(%rsp,%rsi), %r8
+; SSE42-NEXT: movq -80(%rsp,%rsi), %r11
; SSE42-NEXT: movq %r11, %r9
-; SSE42-NEXT: shrdq %cl, %r10, %r9
-; SSE42-NEXT: movq -104(%rsp,%rax), %rbx
+; SSE42-NEXT: shrdq %cl, %r8, %r9
+; SSE42-NEXT: movq -88(%rsp,%rsi), %rbx
; SSE42-NEXT: movq %rbx, %r10
; SSE42-NEXT: shrdq %cl, %r11, %r10
-; SSE42-NEXT: movq -112(%rsp,%rax), %r14
+; SSE42-NEXT: movq -96(%rsp,%rsi), %r14
; SSE42-NEXT: movq %r14, %r11
; SSE42-NEXT: shrdq %cl, %rbx, %r11
-; SSE42-NEXT: movq -120(%rsp,%rax), %r15
+; SSE42-NEXT: movq -104(%rsp,%rsi), %r15
; SSE42-NEXT: movq %r15, %rbx
; SSE42-NEXT: shrdq %cl, %r14, %rbx
-; SSE42-NEXT: movq -128(%rsp,%rax), %r14
-; SSE42-NEXT: shrq %cl, %rdx
-; SSE42-NEXT: # kill: def $cl killed $cl killed $ecx
+; SSE42-NEXT: movq -112(%rsp,%rsi), %r12
+; SSE42-NEXT: movq %r12, %r14
; SSE42-NEXT: shrdq %cl, %r15, %r14
+; SSE42-NEXT: movq -120(%rsp,%rsi), %r13
+; SSE42-NEXT: movq %r13, %r15
+; SSE42-NEXT: shrdq %cl, %r12, %r15
+; SSE42-NEXT: movq %rax, %xmm2
+; SSE42-NEXT: movq %rdx, %xmm3
+; SSE42-NEXT: movq -128(%rsp,%rsi), %rdx
+; SSE42-NEXT: shrq %cl, %r8
+; SSE42-NEXT: # kill: def $cl killed $cl killed $ecx
+; SSE42-NEXT: shrdq %cl, %r13, %rdx
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; SSE42-NEXT: por %xmm0, %xmm2
-; SSE42-NEXT: por %xmm2, %xmm1
+; SSE42-NEXT: por %xmm1, %xmm2
; SSE42-NEXT: xorl %ecx, %ecx
-; SSE42-NEXT: ptest %xmm1, %xmm1
+; SSE42-NEXT: ptest %xmm2, %xmm2
+; SSE42-NEXT: cmoveq %rcx, %r15
+; SSE42-NEXT: cmoveq %rcx, %r14
; SSE42-NEXT: cmoveq %rcx, %rbx
; SSE42-NEXT: cmoveq %rcx, %r11
; SSE42-NEXT: cmoveq %rcx, %r10
; SSE42-NEXT: cmoveq %rcx, %r9
-; SSE42-NEXT: cmoveq %rcx, %r8
-; SSE42-NEXT: cmoveq %rcx, %rsi
-; SSE42-NEXT: cmoveq %rcx, %r14
-; SSE42-NEXT: movq %rdi, %rax
; SSE42-NEXT: cmoveq %rcx, %rdx
-; SSE42-NEXT: movq %rdx, 56(%rdi)
-; SSE42-NEXT: movq %rsi, 48(%rdi)
-; SSE42-NEXT: movq %r8, 40(%rdi)
-; SSE42-NEXT: movq %r9, 32(%rdi)
-; SSE42-NEXT: movq %r10, 24(%rdi)
-; SSE42-NEXT: movq %r11, 16(%rdi)
-; SSE42-NEXT: movq %rbx, 8(%rdi)
-; SSE42-NEXT: movq %r14, (%rdi)
+; SSE42-NEXT: movq %rdi, %rax
+; SSE42-NEXT: cmoveq %rcx, %r8
+; SSE42-NEXT: movq %r8, 56(%rdi)
+; SSE42-NEXT: movq %r9, 48(%rdi)
+; SSE42-NEXT: movq %r10, 40(%rdi)
+; SSE42-NEXT: movq %r11, 32(%rdi)
+; SSE42-NEXT: movq %rbx, 24(%rdi)
+; SSE42-NEXT: movq %r14, 16(%rdi)
+; SSE42-NEXT: movq %r15, 8(%rdi)
+; SSE42-NEXT: movq %rdx, (%rdi)
; SSE42-NEXT: popq %rbx
+; SSE42-NEXT: popq %r12
+; SSE42-NEXT: popq %r13
; SSE42-NEXT: popq %r14
; SSE42-NEXT: popq %r15
; SSE42-NEXT: retq
@@ -5199,102 +5218,117 @@ define i512 @isolate_msb_i512_load(ptr %p0, i512 %idx) nounwind {
; AVX2-NEXT: pushq %r15
; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %rbx
-; AVX2-NEXT: vmovdqu 32(%rsi), %ymm1
-; AVX2-NEXT: movq 8(%rsi), %r8
-; AVX2-NEXT: movq 16(%rsi), %rax
-; AVX2-NEXT: movq 24(%rsi), %rcx
-; AVX2-NEXT: movq 40(%rsi), %rdx
+; AVX2-NEXT: movq 56(%rsi), %r9
+; AVX2-NEXT: vmovq %r9, %xmm0
; AVX2-NEXT: movq 48(%rsi), %r10
-; AVX2-NEXT: vpor (%rsi), %ymm1, %ymm0
-; AVX2-NEXT: movq 56(%rsi), %r11
-; AVX2-NEXT: lzcntq %r11, %r9
+; AVX2-NEXT: vmovq %r10, %xmm1
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; AVX2-NEXT: movq 40(%rsi), %r11
+; AVX2-NEXT: vmovq %r11, %xmm1
+; AVX2-NEXT: movq 32(%rsi), %rcx
+; AVX2-NEXT: vmovq %rcx, %xmm2
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
+; AVX2-NEXT: movq 24(%rsi), %r8
+; AVX2-NEXT: movq 16(%rsi), %rax
+; AVX2-NEXT: vmovq %rax, %xmm2
+; AVX2-NEXT: movq (%rsi), %rdx
+; AVX2-NEXT: movq 8(%rsi), %rsi
; AVX2-NEXT: xorl %ebx, %ebx
-; AVX2-NEXT: lzcntq %r10, %rbx
-; AVX2-NEXT: addq $64, %rbx
-; AVX2-NEXT: testq %r11, %r11
-; AVX2-NEXT: cmovneq %r9, %rbx
+; AVX2-NEXT: lzcntq %r9, %rbx
; AVX2-NEXT: xorl %r14d, %r14d
-; AVX2-NEXT: lzcntq %rdx, %r14
+; AVX2-NEXT: lzcntq %r10, %r14
+; AVX2-NEXT: addl $64, %r14d
+; AVX2-NEXT: testq %r9, %r9
+; AVX2-NEXT: cmovnel %ebx, %r14d
+; AVX2-NEXT: xorl %ebx, %ebx
+; AVX2-NEXT: lzcntq %r11, %rbx
+; AVX2-NEXT: lzcntq %rcx, %rcx
+; AVX2-NEXT: addl $64, %ecx
+; AVX2-NEXT: testq %r11, %r11
+; AVX2-NEXT: cmovnel %ebx, %ecx
+; AVX2-NEXT: subl $-128, %ecx
+; AVX2-NEXT: orq %r9, %r10
+; AVX2-NEXT: cmovnel %r14d, %ecx
; AVX2-NEXT: xorl %r9d, %r9d
-; AVX2-NEXT: lzcntq 32(%rsi), %r9
-; AVX2-NEXT: addq $64, %r9
-; AVX2-NEXT: testq %rdx, %rdx
-; AVX2-NEXT: cmovneq %r14, %r9
-; AVX2-NEXT: subq $-128, %r9
-; AVX2-NEXT: orq %r11, %r10
-; AVX2-NEXT: cmovneq %rbx, %r9
-; AVX2-NEXT: xorl %edx, %edx
-; AVX2-NEXT: lzcntq %rcx, %rdx
+; AVX2-NEXT: lzcntq %r8, %r9
; AVX2-NEXT: xorl %r10d, %r10d
; AVX2-NEXT: lzcntq %rax, %r10
-; AVX2-NEXT: addq $64, %r10
-; AVX2-NEXT: testq %rcx, %rcx
-; AVX2-NEXT: cmovneq %rdx, %r10
-; AVX2-NEXT: xorl %r11d, %r11d
-; AVX2-NEXT: lzcntq %r8, %r11
-; AVX2-NEXT: xorl %edx, %edx
-; AVX2-NEXT: lzcntq (%rsi), %rdx
-; AVX2-NEXT: addq $64, %rdx
+; AVX2-NEXT: addl $64, %r10d
; AVX2-NEXT: testq %r8, %r8
-; AVX2-NEXT: cmovneq %r11, %rdx
-; AVX2-NEXT: subq $-128, %rdx
-; AVX2-NEXT: orq %rcx, %rax
-; AVX2-NEXT: cmovneq %r10, %rdx
-; AVX2-NEXT: addq $256, %rdx # imm = 0x100
-; AVX2-NEXT: vpor 48(%rsi), %xmm1, %xmm1
-; AVX2-NEXT: vptest %xmm1, %xmm1
-; AVX2-NEXT: cmovneq %r9, %rdx
-; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX2-NEXT: vmovdqu %ymm1, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: vmovdqu %ymm1, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: vmovaps {{.*#+}} ymm2 = [0,0,0,9223372036854775808]
-; AVX2-NEXT: vmovups %ymm2, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: vmovdqu %ymm1, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movl %edx, %ecx
+; AVX2-NEXT: cmovnel %r9d, %r10d
+; AVX2-NEXT: xorl %r11d, %r11d
+; AVX2-NEXT: lzcntq %rsi, %r11
+; AVX2-NEXT: xorl %r9d, %r9d
+; AVX2-NEXT: lzcntq %rdx, %r9
+; AVX2-NEXT: addl $64, %r9d
+; AVX2-NEXT: testq %rsi, %rsi
+; AVX2-NEXT: cmovnel %r11d, %r9d
+; AVX2-NEXT: subl $-128, %r9d
+; AVX2-NEXT: orq %r8, %rax
+; AVX2-NEXT: cmovnel %r10d, %r9d
+; AVX2-NEXT: addl $256, %r9d # imm = 0x100
+; AVX2-NEXT: vpor %xmm0, %xmm1, %xmm3
+; AVX2-NEXT: vptest %xmm3, %xmm3
+; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3
+; AVX2-NEXT: vmovdqu %ymm3, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: vmovdqu %ymm3, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: vmovaps {{.*#+}} ymm4 = [0,0,0,9223372036854775808]
+; AVX2-NEXT: vmovups %ymm4, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: vmovdqu %ymm3, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: cmovnel %ecx, %r9d
+; AVX2-NEXT: movl %r9d, %ecx
; AVX2-NEXT: andl $63, %ecx
-; AVX2-NEXT: shrl $3, %edx
-; AVX2-NEXT: andl $56, %edx
-; AVX2-NEXT: movq -72(%rsp,%rdx), %r11
-; AVX2-NEXT: movq -80(%rsp,%rdx), %rax
-; AVX2-NEXT: movq %rax, %rsi
-; AVX2-NEXT: shrdq %cl, %r11, %rsi
-; AVX2-NEXT: movq -88(%rsp,%rdx), %r10
-; AVX2-NEXT: movq %r10, %r8
-; AVX2-NEXT: shrdq %cl, %rax, %r8
-; AVX2-NEXT: movq -96(%rsp,%rdx), %rax
-; AVX2-NEXT: movq %rax, %r9
-; AVX2-NEXT: shrdq %cl, %r10, %r9
-; AVX2-NEXT: movq -104(%rsp,%rdx), %r14
-; AVX2-NEXT: movq %r14, %r10
-; AVX2-NEXT: shrdq %cl, %rax, %r10
-; AVX2-NEXT: movq -112(%rsp,%rdx), %r15
-; AVX2-NEXT: movq %r15, %rbx
-; AVX2-NEXT: shrdq %cl, %r14, %rbx
+; AVX2-NEXT: shrl $3, %r9d
+; AVX2-NEXT: andl $56, %r9d
+; AVX2-NEXT: movq -72(%rsp,%r9), %rbx
+; AVX2-NEXT: movq -80(%rsp,%r9), %rax
+; AVX2-NEXT: movq %rax, %r10
+; AVX2-NEXT: shrdq %cl, %rbx, %r10
+; AVX2-NEXT: movq -88(%rsp,%r9), %r14
+; AVX2-NEXT: movq %r14, %r11
+; AVX2-NEXT: shrdq %cl, %rax, %r11
; AVX2-NEXT: movq %rdi, %rax
-; AVX2-NEXT: movq -128(%rsp,%rdx), %rdi
-; AVX2-NEXT: movq -120(%rsp,%rdx), %r14
-; AVX2-NEXT: movq %r14, %rdx
-; AVX2-NEXT: shrdq %cl, %r15, %rdx
+; AVX2-NEXT: movq -96(%rsp,%r9), %r15
+; AVX2-NEXT: movq %r15, %rdi
; AVX2-NEXT: shrdq %cl, %r14, %rdi
+; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
+; AVX2-NEXT: vmovq %r8, %xmm1
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
+; AVX2-NEXT: movq -104(%rsp,%r9), %r14
+; AVX2-NEXT: movq %r14, %r8
+; AVX2-NEXT: shrdq %cl, %r15, %r8
+; AVX2-NEXT: vmovq %rsi, %xmm2
+; AVX2-NEXT: vmovq %rdx, %xmm3
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
+; AVX2-NEXT: movq -112(%rsp,%r9), %r15
+; AVX2-NEXT: movq %r15, %rdx
+; AVX2-NEXT: shrdq %cl, %r14, %rdx
+; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
+; AVX2-NEXT: vpor %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: movq -128(%rsp,%r9), %rsi
+; AVX2-NEXT: movq -120(%rsp,%r9), %r14
+; AVX2-NEXT: movq %r14, %r9
+; AVX2-NEXT: shrdq %cl, %r15, %r9
+; AVX2-NEXT: shrdq %cl, %r14, %rsi
; AVX2-NEXT: xorl %r14d, %r14d
; AVX2-NEXT: vptest %ymm0, %ymm0
-; AVX2-NEXT: shrxq %rcx, %r11, %rcx
-; AVX2-NEXT: cmoveq %r14, %rdx
-; AVX2-NEXT: cmoveq %r14, %rbx
-; AVX2-NEXT: cmoveq %r14, %r10
+; AVX2-NEXT: shrxq %rcx, %rbx, %rcx
; AVX2-NEXT: cmoveq %r14, %r9
+; AVX2-NEXT: cmoveq %r14, %rdx
; AVX2-NEXT: cmoveq %r14, %r8
-; AVX2-NEXT: cmoveq %r14, %rsi
; AVX2-NEXT: cmoveq %r14, %rdi
+; AVX2-NEXT: cmoveq %r14, %r11
+; AVX2-NEXT: cmoveq %r14, %r10
+; AVX2-NEXT: cmoveq %r14, %rsi
; AVX2-NEXT: cmoveq %r14, %rcx
; AVX2-NEXT: movq %rcx, 56(%rax)
-; AVX2-NEXT: movq %rsi, 48(%rax)
-; AVX2-NEXT: movq %r8, 40(%rax)
-; AVX2-NEXT: movq %r9, 32(%rax)
-; AVX2-NEXT: movq %r10, 24(%rax)
-; AVX2-NEXT: movq %rbx, 16(%rax)
-; AVX2-NEXT: movq %rdx, 8(%rax)
-; AVX2-NEXT: movq %rdi, (%rax)
+; AVX2-NEXT: movq %r10, 48(%rax)
+; AVX2-NEXT: movq %r11, 40(%rax)
+; AVX2-NEXT: movq %rdi, 32(%rax)
+; AVX2-NEXT: movq %r8, 24(%rax)
+; AVX2-NEXT: movq %rdx, 16(%rax)
+; AVX2-NEXT: movq %r9, 8(%rax)
+; AVX2-NEXT: movq %rsi, (%rax)
; AVX2-NEXT: popq %rbx
; AVX2-NEXT: popq %r14
; AVX2-NEXT: popq %r15
diff --git a/llvm/test/CodeGen/X86/clmul-vector.ll b/llvm/test/CodeGen/X86/clmul-vector.ll
index 6fd01e446897d..789f263405701 100644
--- a/llvm/test/CodeGen/X86/clmul-vector.ll
+++ b/llvm/test/CodeGen/X86/clmul-vector.ll
@@ -1362,9 +1362,9 @@ define <2 x i64> @clmul_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
define <16 x i8> @clmulr_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
; SSE2-LABEL: clmulr_v16i8:
; SSE2: # %bb.0:
+; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: psrlw $4, %xmm3
-; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: pand %xmm2, %xmm3
; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: psllw $4, %xmm0
@@ -2707,20 +2707,20 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: psrlq $32, %xmm9
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm12 = [2,2]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, %xmm7
; SSE2-NOPCLMUL-NEXT: pand %xmm12, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm7
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm7
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm7
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: movdqa %xmm0, %xmm4
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm5
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm5, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, %xmm5
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5
@@ -2728,7 +2728,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm5, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm5
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm5
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm5
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm5
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm5
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm5
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm3
@@ -2737,14 +2737,14 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, %xmm7
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm7
; SSE2-NOPCLMUL-NEXT: movdqa %xmm8, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm7
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm7
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm7
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm7
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm11 = [64,64]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm4
@@ -2753,7 +2753,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm3, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, %xmm3
@@ -2762,14 +2762,14 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm5
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm5, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm5, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa %xmm0, %xmm5
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5
; SSE2-NOPCLMUL-NEXT: movdqa %xmm8, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm5, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm5
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm5
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm5
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm5
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm5
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm15 = [512,512]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, %xmm7
@@ -2778,7 +2778,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm7
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm7
-; SSE2-NOPCLMUL-NEXT: por %xmm3, %xmm7
+; SSE2-NOPCLMUL-NEXT: paddq %xmm3, %xmm7
; SSE2-NOPCLMUL-NEXT: pxor %xmm5, %xmm7
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm3
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
@@ -2786,7 +2786,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm5
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm5, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm5, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, %xmm4
@@ -2795,7 +2795,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm5
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm5, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm14 = [4096,4096]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm5
; SSE2-NOPCLMUL-NEXT: pand %xmm14, %xmm5
@@ -2803,7 +2803,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm5, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm5
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm5
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm5
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm5
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm5
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm6 = [8192,8192]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -2813,7 +2813,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm5
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5
@@ -2821,7 +2821,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm5, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm5
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm5
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm5
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm5
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm5
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, %xmm4
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
@@ -2829,7 +2829,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm5 = [65536,65536]
@@ -2840,7 +2840,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm5
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm5, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm5, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm6 = [131072,131072]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, %xmm5
@@ -2849,7 +2849,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm5, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm5
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm5
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm5
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm5
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm5
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm10 = [262144,262144]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm3
@@ -2858,7 +2858,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm5, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm6 = [524288,524288]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -2868,7 +2868,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm5, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm5
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm5
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm5
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm5
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm5
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm3 = [1048576,1048576]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -2878,7 +2878,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm7
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm7
-; SSE2-NOPCLMUL-NEXT: por %xmm3, %xmm7
+; SSE2-NOPCLMUL-NEXT: paddq %xmm3, %xmm7
; SSE2-NOPCLMUL-NEXT: pxor %xmm5, %xmm7
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm5 = [2097152,2097152]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -2888,7 +2888,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm5
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm5, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm5, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm5 = [4194304,4194304]
@@ -2900,7 +2900,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: movdqa %xmm9, %xmm6
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm5, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm7 = [8388608,8388608]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, %xmm5
@@ -2909,7 +2909,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm5, %xmm9
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm5
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm5
-; SSE2-NOPCLMUL-NEXT: por %xmm9, %xmm5
+; SSE2-NOPCLMUL-NEXT: paddq %xmm9, %xmm5
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm5
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm4 = [16777216,16777216]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -2918,7 +2918,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm0, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm0
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm0
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm0
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm0
; SSE2-NOPCLMUL-NEXT: pxor %xmm5, %xmm0
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm5 = [33554432,33554432]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm5, (%rsp) # 16-byte Spill
@@ -2928,7 +2928,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm5
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm5, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm0, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm5 = [67108864,67108864]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -2938,7 +2938,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm0, %xmm5
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm0
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm0
-; SSE2-NOPCLMUL-NEXT: por %xmm5, %xmm0
+; SSE2-NOPCLMUL-NEXT: paddq %xmm5, %xmm0
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm0
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm4 = [134217728,134217728]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -2948,7 +2948,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm5
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm5
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm5
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm5
; SSE2-NOPCLMUL-NEXT: pxor %xmm0, %xmm5
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm0 = [268435456,268435456]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -2958,7 +2958,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm0
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm0, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm0, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -2972,14 +2972,14 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: movdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm0
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm0
-; SSE2-NOPCLMUL-NEXT: por %xmm3, %xmm0
+; SSE2-NOPCLMUL-NEXT: paddq %xmm3, %xmm0
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm3
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa %xmm8, %xmm6
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm6
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm6, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm6, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm0, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE2-NOPCLMUL-NEXT: psrlq $32, %xmm1
@@ -3141,7 +3141,7 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm0, %xmm8
; SSE2-NOPCLMUL-NEXT: pmuludq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm0
-; SSE2-NOPCLMUL-NEXT: por %xmm8, %xmm0
+; SSE2-NOPCLMUL-NEXT: paddq %xmm8, %xmm0
; SSE2-NOPCLMUL-NEXT: pxor {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm5
; SSE2-NOPCLMUL-NEXT: pxor %xmm0, %xmm5
@@ -3310,9 +3310,9 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
define <16 x i8> @clmulh_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
; SSE2-LABEL: clmulh_v16i8:
; SSE2: # %bb.0:
+; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: psrlw $4, %xmm3
-; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: pand %xmm2, %xmm3
; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: psllw $4, %xmm0
@@ -4595,20 +4595,20 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: psrlq $32, %xmm9
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm12 = [2,2]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, %xmm7
; SSE2-NOPCLMUL-NEXT: pand %xmm12, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm7
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm7
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm7
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: movdqa %xmm0, %xmm4
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm5
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm5, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, %xmm5
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5
@@ -4616,7 +4616,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm5, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm5
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm5
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm5
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm5
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm5
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm5
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm3
@@ -4625,14 +4625,14 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, %xmm7
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm7
; SSE2-NOPCLMUL-NEXT: movdqa %xmm8, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm7
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm7
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm7
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm7
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm11 = [64,64]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm4
@@ -4641,7 +4641,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm3, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, %xmm3
@@ -4650,14 +4650,14 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm5
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm5, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm5, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa %xmm0, %xmm5
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5
; SSE2-NOPCLMUL-NEXT: movdqa %xmm8, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm5, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm5
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm5
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm5
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm5
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm5
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm15 = [512,512]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, %xmm7
@@ -4666,7 +4666,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm7
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm7
-; SSE2-NOPCLMUL-NEXT: por %xmm3, %xmm7
+; SSE2-NOPCLMUL-NEXT: paddq %xmm3, %xmm7
; SSE2-NOPCLMUL-NEXT: pxor %xmm5, %xmm7
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm3
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
@@ -4674,7 +4674,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm5
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm5, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm5, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, %xmm4
@@ -4683,7 +4683,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm5
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm5, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm14 = [4096,4096]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm5
; SSE2-NOPCLMUL-NEXT: pand %xmm14, %xmm5
@@ -4691,7 +4691,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm5, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm5
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm5
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm5
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm5
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm5
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm6 = [8192,8192]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -4701,7 +4701,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm5
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5
@@ -4709,7 +4709,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm5, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm5
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm5
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm5
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm5
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm5
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, %xmm4
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
@@ -4717,7 +4717,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm5 = [65536,65536]
@@ -4728,7 +4728,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm5
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm5, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm5, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm6 = [131072,131072]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, %xmm5
@@ -4737,7 +4737,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm5, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm5
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm5
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm5
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm5
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm5
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm10 = [262144,262144]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm3
@@ -4746,7 +4746,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm5, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm6 = [524288,524288]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -4756,7 +4756,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm5, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm5
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm5
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm5
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm5
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm5
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm3 = [1048576,1048576]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -4766,7 +4766,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm7
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm7
-; SSE2-NOPCLMUL-NEXT: por %xmm3, %xmm7
+; SSE2-NOPCLMUL-NEXT: paddq %xmm3, %xmm7
; SSE2-NOPCLMUL-NEXT: pxor %xmm5, %xmm7
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm5 = [2097152,2097152]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -4776,7 +4776,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm5
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm5, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm5, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm5 = [4194304,4194304]
@@ -4788,7 +4788,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: movdqa %xmm9, %xmm6
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm5, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm7 = [8388608,8388608]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, %xmm5
@@ -4797,7 +4797,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm5, %xmm9
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm5
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm5
-; SSE2-NOPCLMUL-NEXT: por %xmm9, %xmm5
+; SSE2-NOPCLMUL-NEXT: paddq %xmm9, %xmm5
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm5
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm4 = [16777216,16777216]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -4806,7 +4806,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm0, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm0
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm0
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm0
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm0
; SSE2-NOPCLMUL-NEXT: pxor %xmm5, %xmm0
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm5 = [33554432,33554432]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm5, (%rsp) # 16-byte Spill
@@ -4816,7 +4816,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm5
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm5, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm0, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm5 = [67108864,67108864]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -4826,7 +4826,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm0, %xmm5
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm0
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm0
-; SSE2-NOPCLMUL-NEXT: por %xmm5, %xmm0
+; SSE2-NOPCLMUL-NEXT: paddq %xmm5, %xmm0
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm0
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm4 = [134217728,134217728]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -4836,7 +4836,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm5
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm5
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm5
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm5
; SSE2-NOPCLMUL-NEXT: pxor %xmm0, %xmm5
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm0 = [268435456,268435456]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -4846,7 +4846,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm0
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm0, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm0, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -4860,14 +4860,14 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: movdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm0
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm0
-; SSE2-NOPCLMUL-NEXT: por %xmm3, %xmm0
+; SSE2-NOPCLMUL-NEXT: paddq %xmm3, %xmm0
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm3
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa %xmm8, %xmm6
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm6
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm6, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm6, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm0, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE2-NOPCLMUL-NEXT: psrlq $32, %xmm1
@@ -5029,7 +5029,7 @@ define <2 x i64> @clmulh_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm0, %xmm8
; SSE2-NOPCLMUL-NEXT: pmuludq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm0
-; SSE2-NOPCLMUL-NEXT: por %xmm8, %xmm0
+; SSE2-NOPCLMUL-NEXT: paddq %xmm8, %xmm0
; SSE2-NOPCLMUL-NEXT: pxor {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm5
; SSE2-NOPCLMUL-NEXT: pxor %xmm0, %xmm5
@@ -5861,20 +5861,20 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: psrlq $32, %xmm9
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm2
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm2
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm2
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm2
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm12 = [2,2]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm7
; SSE2-NOPCLMUL-NEXT: pand %xmm12, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm7
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm7
-; SSE2-NOPCLMUL-NEXT: por %xmm3, %xmm7
+; SSE2-NOPCLMUL-NEXT: paddq %xmm3, %xmm7
; SSE2-NOPCLMUL-NEXT: movdqa %xmm0, %xmm3
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm4
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
@@ -5882,7 +5882,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm2, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa %xmm5, %xmm2
@@ -5891,14 +5891,14 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm2, %xmm3
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm2
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm2
-; SSE2-NOPCLMUL-NEXT: por %xmm3, %xmm2
+; SSE2-NOPCLMUL-NEXT: paddq %xmm3, %xmm2
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm7
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm7
; SSE2-NOPCLMUL-NEXT: movdqa %xmm8, %xmm3
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm7
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm7
-; SSE2-NOPCLMUL-NEXT: por %xmm3, %xmm7
+; SSE2-NOPCLMUL-NEXT: paddq %xmm3, %xmm7
; SSE2-NOPCLMUL-NEXT: pxor %xmm2, %xmm7
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm11 = [64,64]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm5, %xmm3
@@ -5907,7 +5907,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm2
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm2, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm2, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm2
@@ -5916,14 +5916,14 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm2, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm2
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm2
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm2
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm2
; SSE2-NOPCLMUL-NEXT: movdqa %xmm0, %xmm4
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa %xmm8, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm2, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm15 = [512,512]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm7
@@ -5932,7 +5932,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm7, %xmm2
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm7
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm7
-; SSE2-NOPCLMUL-NEXT: por %xmm2, %xmm7
+; SSE2-NOPCLMUL-NEXT: paddq %xmm2, %xmm7
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: movdqa %xmm5, %xmm2
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
@@ -5940,7 +5940,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm2, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm2
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm2
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm2
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm2
; SSE2-NOPCLMUL-NEXT: pxor %xmm7, %xmm2
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm2
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm3
@@ -5949,7 +5949,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm14 = [4096,4096]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: pand %xmm14, %xmm4
@@ -5957,7 +5957,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm6 = [8192,8192]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -5967,7 +5967,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
@@ -5975,7 +5975,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm3
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
@@ -5983,7 +5983,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm2, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm4 = [65536,65536]
@@ -5994,7 +5994,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm2, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm2
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm2
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm2
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm2
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm6 = [131072,131072]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm4
@@ -6003,7 +6003,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm2, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm10 = [262144,262144]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm5, %xmm2
@@ -6012,7 +6012,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm2, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm2
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm2
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm2
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm2
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm2
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm6 = [524288,524288]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -6022,7 +6022,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm2, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm2 = [1048576,1048576]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -6032,7 +6032,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm7, %xmm2
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm7
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm7
-; SSE2-NOPCLMUL-NEXT: por %xmm2, %xmm7
+; SSE2-NOPCLMUL-NEXT: paddq %xmm2, %xmm7
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm4 = [2097152,2097152]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -6042,7 +6042,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm2, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm2
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm2
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm2
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm2
; SSE2-NOPCLMUL-NEXT: pxor %xmm7, %xmm2
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm2
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm4 = [4194304,4194304]
@@ -6054,7 +6054,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: movdqa %xmm9, %xmm6
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm7 = [8388608,8388608]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm4
@@ -6063,7 +6063,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm9
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm9, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm3 = [16777216,16777216]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -6072,7 +6072,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm0, %xmm3
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm0
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm0
-; SSE2-NOPCLMUL-NEXT: por %xmm3, %xmm0
+; SSE2-NOPCLMUL-NEXT: paddq %xmm3, %xmm0
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm0
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm4 = [33554432,33554432]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm4, (%rsp) # 16-byte Spill
@@ -6082,7 +6082,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm0, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm4 = [67108864,67108864]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -6092,7 +6092,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm0, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm0
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm0
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm0
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm0
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm0
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm3 = [134217728,134217728]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -6102,7 +6102,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm3, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm0, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm0 = [268435456,268435456]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -6112,7 +6112,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm0
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm0, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm0, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm2, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -6126,14 +6126,14 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: movdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm0
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm0
-; SSE2-NOPCLMUL-NEXT: por %xmm2, %xmm0
+; SSE2-NOPCLMUL-NEXT: paddq %xmm2, %xmm0
; SSE2-NOPCLMUL-NEXT: movdqa %xmm5, %xmm2
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NOPCLMUL-NEXT: movdqa %xmm8, %xmm6
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm2, %xmm6
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm2
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm2
-; SSE2-NOPCLMUL-NEXT: por %xmm6, %xmm2
+; SSE2-NOPCLMUL-NEXT: paddq %xmm6, %xmm2
; SSE2-NOPCLMUL-NEXT: pxor %xmm0, %xmm2
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE2-NOPCLMUL-NEXT: psrlq $32, %xmm5
@@ -6295,7 +6295,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm0, %xmm8
; SSE2-NOPCLMUL-NEXT: pmuludq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm0
-; SSE2-NOPCLMUL-NEXT: por %xmm8, %xmm0
+; SSE2-NOPCLMUL-NEXT: paddq %xmm8, %xmm0
; SSE2-NOPCLMUL-NEXT: pxor {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm0, %xmm4
@@ -6540,20 +6540,20 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: psrlq $32, %xmm9
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm2
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm2
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm2
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm2
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm12 = [2,2]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm7
; SSE2-NOPCLMUL-NEXT: pand %xmm12, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm7
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm7
-; SSE2-NOPCLMUL-NEXT: por %xmm3, %xmm7
+; SSE2-NOPCLMUL-NEXT: paddq %xmm3, %xmm7
; SSE2-NOPCLMUL-NEXT: movdqa %xmm0, %xmm3
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm4
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
@@ -6561,7 +6561,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm2, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa %xmm5, %xmm2
@@ -6570,14 +6570,14 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm2, %xmm3
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm2
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm2
-; SSE2-NOPCLMUL-NEXT: por %xmm3, %xmm2
+; SSE2-NOPCLMUL-NEXT: paddq %xmm3, %xmm2
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm7
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm7
; SSE2-NOPCLMUL-NEXT: movdqa %xmm8, %xmm3
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm7
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm7
-; SSE2-NOPCLMUL-NEXT: por %xmm3, %xmm7
+; SSE2-NOPCLMUL-NEXT: paddq %xmm3, %xmm7
; SSE2-NOPCLMUL-NEXT: pxor %xmm2, %xmm7
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm11 = [64,64]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm5, %xmm3
@@ -6586,7 +6586,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm2
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm2, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm2, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm2
@@ -6595,14 +6595,14 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm2, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm2
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm2
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm2
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm2
; SSE2-NOPCLMUL-NEXT: movdqa %xmm0, %xmm4
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa %xmm8, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm2, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm15 = [512,512]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm7
@@ -6611,7 +6611,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm7, %xmm2
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm7
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm7
-; SSE2-NOPCLMUL-NEXT: por %xmm2, %xmm7
+; SSE2-NOPCLMUL-NEXT: paddq %xmm2, %xmm7
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: movdqa %xmm5, %xmm2
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
@@ -6619,7 +6619,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm2, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm2
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm2
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm2
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm2
; SSE2-NOPCLMUL-NEXT: pxor %xmm7, %xmm2
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm2
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm3
@@ -6628,7 +6628,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm14 = [4096,4096]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: pand %xmm14, %xmm4
@@ -6636,7 +6636,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm6 = [8192,8192]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -6646,7 +6646,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa %xmm5, %xmm4
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
@@ -6654,7 +6654,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm3
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
@@ -6662,7 +6662,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm2, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm4 = [65536,65536]
@@ -6673,7 +6673,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm2, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm2
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm2
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm2
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm2
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm6 = [131072,131072]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm4
@@ -6682,7 +6682,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm2, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm10 = [262144,262144]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm5, %xmm2
@@ -6691,7 +6691,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm2, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm2
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm2
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm2
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm2
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm2
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm6 = [524288,524288]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -6701,7 +6701,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm7, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm7, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm2, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm2 = [1048576,1048576]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -6711,7 +6711,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm7, %xmm2
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm7
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm7
-; SSE2-NOPCLMUL-NEXT: por %xmm2, %xmm7
+; SSE2-NOPCLMUL-NEXT: paddq %xmm2, %xmm7
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm7
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm4 = [2097152,2097152]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -6721,7 +6721,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm2, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm2
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm2
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm2
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm2
; SSE2-NOPCLMUL-NEXT: pxor %xmm7, %xmm2
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm2
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm4 = [4194304,4194304]
@@ -6733,7 +6733,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: movdqa %xmm9, %xmm6
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm9, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm7 = [8388608,8388608]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE2-NOPCLMUL-NEXT: movdqa %xmm1, %xmm4
@@ -6742,7 +6742,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm9
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm9, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm9, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm3 = [16777216,16777216]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -6751,7 +6751,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm0, %xmm3
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm0
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm0
-; SSE2-NOPCLMUL-NEXT: por %xmm3, %xmm0
+; SSE2-NOPCLMUL-NEXT: paddq %xmm3, %xmm0
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm0
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm4 = [33554432,33554432]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm4, (%rsp) # 16-byte Spill
@@ -6761,7 +6761,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm0, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm4 = [67108864,67108864]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -6771,7 +6771,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm0, %xmm4
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm0
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm0
-; SSE2-NOPCLMUL-NEXT: por %xmm4, %xmm0
+; SSE2-NOPCLMUL-NEXT: paddq %xmm4, %xmm0
; SSE2-NOPCLMUL-NEXT: pxor %xmm3, %xmm0
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm3 = [134217728,134217728]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -6781,7 +6781,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm4
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
-; SSE2-NOPCLMUL-NEXT: por %xmm3, %xmm4
+; SSE2-NOPCLMUL-NEXT: paddq %xmm3, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm0, %xmm4
; SSE2-NOPCLMUL-NEXT: movdqa {{.*#+}} xmm0 = [268435456,268435456]
; SSE2-NOPCLMUL-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -6791,7 +6791,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm0
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm3
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm3
-; SSE2-NOPCLMUL-NEXT: por %xmm0, %xmm3
+; SSE2-NOPCLMUL-NEXT: paddq %xmm0, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm4, %xmm3
; SSE2-NOPCLMUL-NEXT: pxor %xmm2, %xmm3
; SSE2-NOPCLMUL-NEXT: movdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -6805,14 +6805,14 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: movdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm6, %xmm0
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm0
-; SSE2-NOPCLMUL-NEXT: por %xmm2, %xmm0
+; SSE2-NOPCLMUL-NEXT: paddq %xmm2, %xmm0
; SSE2-NOPCLMUL-NEXT: movdqa %xmm5, %xmm2
; SSE2-NOPCLMUL-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NOPCLMUL-NEXT: movdqa %xmm8, %xmm6
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm2, %xmm6
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm3, %xmm2
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm2
-; SSE2-NOPCLMUL-NEXT: por %xmm6, %xmm2
+; SSE2-NOPCLMUL-NEXT: paddq %xmm6, %xmm2
; SSE2-NOPCLMUL-NEXT: pxor %xmm0, %xmm2
; SSE2-NOPCLMUL-NEXT: movdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE2-NOPCLMUL-NEXT: psrlq $32, %xmm5
@@ -6974,7 +6974,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; SSE2-NOPCLMUL-NEXT: pmuludq %xmm0, %xmm8
; SSE2-NOPCLMUL-NEXT: pmuludq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm0
-; SSE2-NOPCLMUL-NEXT: por %xmm8, %xmm0
+; SSE2-NOPCLMUL-NEXT: paddq %xmm8, %xmm0
; SSE2-NOPCLMUL-NEXT: pxor {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; SSE2-NOPCLMUL-NEXT: psllq $32, %xmm4
; SSE2-NOPCLMUL-NEXT: pxor %xmm0, %xmm4
diff --git a/llvm/test/CodeGen/X86/combine-add.ll b/llvm/test/CodeGen/X86/combine-add.ll
index 5efc8cd111d1f..c9455d5c4db4b 100644
--- a/llvm/test/CodeGen/X86/combine-add.ll
+++ b/llvm/test/CodeGen/X86/combine-add.ll
@@ -209,14 +209,14 @@ define <4 x i32> @combine_vec_add_sub_sub(<4 x i32> %a, <4 x i32> %b, <4 x i32>
; SSE: # %bb.0:
; SSE-NEXT: paddd %xmm2, %xmm1
; SSE-NEXT: psubd %xmm1, %xmm0
-; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [0,1,2,3]
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_add_sub_sub:
; AVX: # %bb.0:
; AVX-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [0,1,2,3]
; AVX-NEXT: retq
%1 = sub <4 x i32> %a, %b
%2 = sub <4 x i32> <i32 0, i32 1, i32 2, i32 3>, %d
diff --git a/llvm/test/CodeGen/X86/div_i129_v_pow2k.ll b/llvm/test/CodeGen/X86/div_i129_v_pow2k.ll
index 0924ea85a0126..e27f2d7fa02e0 100644
--- a/llvm/test/CodeGen/X86/div_i129_v_pow2k.ll
+++ b/llvm/test/CodeGen/X86/div_i129_v_pow2k.ll
@@ -53,10 +53,10 @@ define i129 @v_sdiv_i129_v_pow2k(i129 %lhs) nounwind {
; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl %ecx, %ebx
+; X86-NEXT: movl %edx, %ebx
; X86-NEXT: andl $1, %ebx
; X86-NEXT: negl %ebx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -65,18 +65,18 @@ define i129 @v_sdiv_i129_v_pow2k(i129 %lhs) nounwind {
; X86-NEXT: addl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: adcl {{[0-9]+}}(%esp), %edi
; X86-NEXT: adcl $0, %esi
-; X86-NEXT: adcl $0, %edx
; X86-NEXT: adcl $0, %ecx
-; X86-NEXT: movl %ecx, %ebx
+; X86-NEXT: adcl $0, %edx
+; X86-NEXT: movl %edx, %ebx
; X86-NEXT: andl $1, %ebx
; X86-NEXT: movl %ebx, %ebp
; X86-NEXT: negl %ebp
-; X86-NEXT: shldl $31, %edx, %ecx
-; X86-NEXT: shldl $31, %esi, %edx
+; X86-NEXT: shldl $31, %ecx, %edx
+; X86-NEXT: shldl $31, %esi, %ecx
; X86-NEXT: shldl $31, %edi, %esi
; X86-NEXT: movl %esi, (%eax)
-; X86-NEXT: movl %edx, 4(%eax)
-; X86-NEXT: movl %ecx, 8(%eax)
+; X86-NEXT: movl %ecx, 4(%eax)
+; X86-NEXT: movl %edx, 8(%eax)
; X86-NEXT: movl %ebp, 12(%eax)
; X86-NEXT: movb %bl, 16(%eax)
; X86-NEXT: popl %esi
diff --git a/llvm/test/CodeGen/X86/freeze-binary.ll b/llvm/test/CodeGen/X86/freeze-binary.ll
index 7201ca47d8588..03c72edd398ec 100644
--- a/llvm/test/CodeGen/X86/freeze-binary.ll
+++ b/llvm/test/CodeGen/X86/freeze-binary.ll
@@ -202,14 +202,13 @@ define <4 x i32> @freeze_add_vec(<4 x i32> %a0) nounwind {
define <4 x i32> @freeze_add_vec_undef(<4 x i32> %a0) nounwind {
; X86-LABEL: freeze_add_vec_undef:
; X86: # %bb.0:
-; X86-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # [1,2,3,0]
-; X86-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # [4,3,2,u]
+; X86-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # [5,5,5,u]
; X86-NEXT: retl
;
; X64-LABEL: freeze_add_vec_undef:
; X64: # %bb.0:
-; X64-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [1,2,3,0]
-; X64-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [4,3,2,u]
+; X64-NEXT: vpbroadcastd {{.*#+}} xmm1 = [5,5,5,5]
+; X64-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; X64-NEXT: retq
%x = add <4 x i32> %a0, <i32 1, i32 2, i32 3, i32 undef>
%y = freeze <4 x i32> %x
@@ -274,13 +273,12 @@ define <4 x i32> @freeze_sub_vec_undef(<4 x i32> %a0) nounwind {
; X86-LABEL: freeze_sub_vec_undef:
; X86: # %bb.0:
; X86-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
-; X86-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: freeze_sub_vec_undef:
; X64: # %bb.0:
-; X64-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; X64-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpbroadcastd {{.*#+}} xmm1 = [5,5,5,5]
+; X64-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; X64-NEXT: retq
%x = sub <4 x i32> %a0, <i32 1, i32 2, i32 3, i32 undef>
%y = freeze <4 x i32> %x
@@ -345,14 +343,12 @@ define <8 x i16> @freeze_mul_vec(<8 x i16> %a0) nounwind {
define <8 x i16> @freeze_mul_vec_undef(<8 x i16> %a0) nounwind {
; X86-LABEL: freeze_mul_vec_undef:
; X86: # %bb.0:
-; X86-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # [1,2,3,4,4,3,0,1]
-; X86-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # [4,3,2,1,1,2,u,4]
+; X86-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # [4,6,6,4,4,6,0,4]
; X86-NEXT: retl
;
; X64-LABEL: freeze_mul_vec_undef:
; X64: # %bb.0:
-; X64-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [1,2,3,4,4,3,0,1]
-; X64-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [4,3,2,1,1,2,u,4]
+; X64-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [4,6,6,4,4,6,0,4]
; X64-NEXT: retq
%x = mul <8 x i16> %a0, <i16 1, i16 2, i16 3, i16 4, i16 4, i16 3, i16 undef, i16 1>
%y = freeze <8 x i16> %x
@@ -452,8 +448,7 @@ define i32 @freeze_ashr(i32 %a0) nounwind {
; X86-LABEL: freeze_ashr:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: sarl $3, %eax
-; X86-NEXT: sarl $3, %eax
+; X86-NEXT: sarl $6, %eax
; X86-NEXT: retl
;
; X64-LABEL: freeze_ashr:
@@ -471,15 +466,13 @@ define i32 @freeze_ashr_exact(i32 %a0) nounwind {
; X86-LABEL: freeze_ashr_exact:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: sarl $3, %eax
-; X86-NEXT: sarl $6, %eax
+; X86-NEXT: sarl $9, %eax
; X86-NEXT: retl
;
; X64-LABEL: freeze_ashr_exact:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: sarl $3, %eax
-; X64-NEXT: sarl $6, %eax
+; X64-NEXT: sarl $9, %eax
; X64-NEXT: retq
%x = ashr exact i32 %a0, 3
%y = freeze i32 %x
@@ -490,20 +483,20 @@ define i32 @freeze_ashr_exact(i32 %a0) nounwind {
define i32 @freeze_ashr_exact_extra_use(i32 %a0, ptr %escape) nounwind {
; X86-LABEL: freeze_ashr_exact_extra_use:
; X86: # %bb.0:
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: sarl $3, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl %eax, %edx
-; X86-NEXT: sarl $6, %eax
+; X86-NEXT: sarl $3, %edx
+; X86-NEXT: sarl $9, %eax
; X86-NEXT: movl %edx, (%ecx)
; X86-NEXT: retl
;
; X64-LABEL: freeze_ashr_exact_extra_use:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: sarl $3, %eax
-; X64-NEXT: movl %eax, %ecx
-; X64-NEXT: sarl $6, %eax
+; X64-NEXT: movl %edi, %ecx
+; X64-NEXT: sarl $3, %ecx
+; X64-NEXT: sarl $9, %eax
; X64-NEXT: movl %ecx, (%rsi)
; X64-NEXT: retq
%x = ashr exact i32 %a0, 3
@@ -567,8 +560,7 @@ define i32 @freeze_lshr(i32 %a0) nounwind {
; X86-LABEL: freeze_lshr:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: shrl $2, %eax
-; X86-NEXT: shrl %eax
+; X86-NEXT: shrl $3, %eax
; X86-NEXT: retl
;
; X64-LABEL: freeze_lshr:
@@ -586,15 +578,13 @@ define i32 @freeze_lshr_exact(i32 %a0) nounwind {
; X86-LABEL: freeze_lshr_exact:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: shrl $3, %eax
-; X86-NEXT: shrl $5, %eax
+; X86-NEXT: shrl $8, %eax
; X86-NEXT: retl
;
; X64-LABEL: freeze_lshr_exact:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: shrl $3, %eax
-; X64-NEXT: shrl $5, %eax
+; X64-NEXT: shrl $8, %eax
; X64-NEXT: retq
%x = lshr exact i32 %a0, 3
%y = freeze i32 %x
@@ -605,20 +595,20 @@ define i32 @freeze_lshr_exact(i32 %a0) nounwind {
define i32 @freeze_lshr_exact_extra_use(i32 %a0, ptr %escape) nounwind {
; X86-LABEL: freeze_lshr_exact_extra_use:
; X86: # %bb.0:
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: shrl $3, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl %eax, %edx
-; X86-NEXT: shrl $5, %eax
+; X86-NEXT: shrl $3, %edx
+; X86-NEXT: shrl $8, %eax
; X86-NEXT: movl %edx, (%ecx)
; X86-NEXT: retl
;
; X64-LABEL: freeze_lshr_exact_extra_use:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: shrl $3, %eax
-; X64-NEXT: movl %eax, %ecx
-; X64-NEXT: shrl $5, %eax
+; X64-NEXT: movl %edi, %ecx
+; X64-NEXT: shrl $3, %ecx
+; X64-NEXT: shrl $8, %eax
; X64-NEXT: movl %ecx, (%rsi)
; X64-NEXT: retq
%x = lshr exact i32 %a0, 3
diff --git a/llvm/test/CodeGen/X86/freeze-unary.ll b/llvm/test/CodeGen/X86/freeze-unary.ll
index bc9e29957c74a..49a043ffb7cb0 100644
--- a/llvm/test/CodeGen/X86/freeze-unary.ll
+++ b/llvm/test/CodeGen/X86/freeze-unary.ll
@@ -6,6 +6,7 @@ define i32 @freeze_sext(i8 %a0) nounwind {
; X86-LABEL: freeze_sext:
; X86: # %bb.0:
; X86-NEXT: movsbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cwtl
; X86-NEXT: retl
;
; X64-LABEL: freeze_sext:
@@ -40,6 +41,7 @@ define i32 @freeze_zext(i8 %a0) nounwind {
; X86-LABEL: freeze_zext:
; X86: # %bb.0:
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movzwl %ax, %eax
; X86-NEXT: retl
;
; X64-LABEL: freeze_zext:
diff --git a/llvm/test/CodeGen/X86/freeze-vector.ll b/llvm/test/CodeGen/X86/freeze-vector.ll
index b24ca513ebb54..697bf14e89976 100644
--- a/llvm/test/CodeGen/X86/freeze-vector.ll
+++ b/llvm/test/CodeGen/X86/freeze-vector.ll
@@ -171,15 +171,15 @@ define void @freeze_extractelement(ptr %origin0, ptr %origin1, ptr %dst) nounwin
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT: vmovdqa (%edx), %xmm0
-; X86-NEXT: vpand (%ecx), %xmm0, %xmm0
+; X86-NEXT: vmovdqa (%ecx), %xmm0
+; X86-NEXT: vpand (%edx), %xmm0, %xmm0
; X86-NEXT: vpextrb $6, %xmm0, (%eax)
; X86-NEXT: retl
;
; X64-LABEL: freeze_extractelement:
; X64: # %bb.0:
-; X64-NEXT: vmovdqa (%rdi), %xmm0
-; X64-NEXT: vpand (%rsi), %xmm0, %xmm0
+; X64-NEXT: vmovdqa (%rsi), %xmm0
+; X64-NEXT: vpand (%rdi), %xmm0, %xmm0
; X64-NEXT: vpextrb $6, %xmm0, (%rdx)
; X64-NEXT: retq
%i0 = load <16 x i8>, ptr %origin0
@@ -198,8 +198,8 @@ define void @freeze_extractelement_escape(ptr %origin0, ptr %origin1, ptr %dst,
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
-; X86-NEXT: vmovdqa (%esi), %xmm0
-; X86-NEXT: vpand (%edx), %xmm0, %xmm0
+; X86-NEXT: vmovdqa (%edx), %xmm0
+; X86-NEXT: vpand (%esi), %xmm0, %xmm0
; X86-NEXT: vmovdqa %xmm0, (%ecx)
; X86-NEXT: vpextrb $6, %xmm0, (%eax)
; X86-NEXT: popl %esi
@@ -207,8 +207,8 @@ define void @freeze_extractelement_escape(ptr %origin0, ptr %origin1, ptr %dst,
;
; X64-LABEL: freeze_extractelement_escape:
; X64: # %bb.0:
-; X64-NEXT: vmovdqa (%rdi), %xmm0
-; X64-NEXT: vpand (%rsi), %xmm0, %xmm0
+; X64-NEXT: vmovdqa (%rsi), %xmm0
+; X64-NEXT: vpand (%rdi), %xmm0, %xmm0
; X64-NEXT: vmovdqa %xmm0, (%rcx)
; X64-NEXT: vpextrb $6, %xmm0, (%rdx)
; X64-NEXT: retq
@@ -239,8 +239,8 @@ define void @freeze_extractelement_extra_use(ptr %origin0, ptr %origin1, i64 %id
; X86-NEXT: movl 32(%ebp), %edx
; X86-NEXT: movl 12(%ebp), %esi
; X86-NEXT: movl 8(%ebp), %edi
-; X86-NEXT: vmovaps (%edi), %xmm0
-; X86-NEXT: vandps (%esi), %xmm0, %xmm0
+; X86-NEXT: vmovaps (%esi), %xmm0
+; X86-NEXT: vandps (%edi), %xmm0, %xmm0
; X86-NEXT: vmovaps %xmm0, (%esp)
; X86-NEXT: movzbl (%esp,%ecx), %ecx
; X86-NEXT: cmpb (%esp,%eax), %cl
@@ -255,8 +255,8 @@ define void @freeze_extractelement_extra_use(ptr %origin0, ptr %origin1, i64 %id
; X64: # %bb.0:
; X64-NEXT: andl $15, %ecx
; X64-NEXT: andl $15, %edx
-; X64-NEXT: vmovaps (%rdi), %xmm0
-; X64-NEXT: vandps (%rsi), %xmm0, %xmm0
+; X64-NEXT: vmovaps (%rsi), %xmm0
+; X64-NEXT: vandps (%rdi), %xmm0, %xmm0
; X64-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
; X64-NEXT: movzbl -24(%rsp,%rdx), %eax
; X64-NEXT: cmpb -24(%rsp,%rcx), %al
diff --git a/llvm/test/CodeGen/X86/freeze.ll b/llvm/test/CodeGen/X86/freeze.ll
index 38e3e23f7caac..171dbc13ab250 100644
--- a/llvm/test/CodeGen/X86/freeze.ll
+++ b/llvm/test/CodeGen/X86/freeze.ll
@@ -148,20 +148,21 @@ define i64 @pr155345(ptr %p1, i1 %cond, ptr %p2, ptr %p3) {
; X86ASM-LABEL: pr155345:
; X86ASM: # %bb.0: # %entry
; X86ASM-NEXT: movzbl (%rdi), %edi
-; X86ASM-NEXT: xorl %eax, %eax
-; X86ASM-NEXT: orb $1, %dil
+; X86ASM-NEXT: orq $1, %rdi
; X86ASM-NEXT: movb %dil, (%rdx)
-; X86ASM-NEXT: movzbl %dil, %edx
-; X86ASM-NEXT: cmovel %edx, %eax
-; X86ASM-NEXT: sete %dil
+; X86ASM-NEXT: movsbq %dil, %rdx
+; X86ASM-NEXT: xorl %eax, %eax
+; X86ASM-NEXT: testq %rdx, %rdx
+; X86ASM-NEXT: cmovel %edi, %eax
+; X86ASM-NEXT: sete %r8b
; X86ASM-NEXT: testb $1, %sil
-; X86ASM-NEXT: cmovnel %edx, %eax
+; X86ASM-NEXT: cmovnel %edi, %eax
; X86ASM-NEXT: movb %dl, (%rcx)
; X86ASM-NEXT: movl $1, %edx
; X86ASM-NEXT: movl %eax, %ecx
; X86ASM-NEXT: shlq %cl, %rdx
-; X86ASM-NEXT: orb %sil, %dil
-; X86ASM-NEXT: movzbl %dil, %eax
+; X86ASM-NEXT: orb %sil, %r8b
+; X86ASM-NEXT: movzbl %r8b, %eax
; X86ASM-NEXT: andl %edx, %eax
; X86ASM-NEXT: andl $1, %eax
; X86ASM-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll b/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll
index 64ff0014d6cb7..b238a1932e2e1 100644
--- a/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll
+++ b/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll
@@ -855,22 +855,21 @@ define <64 x i8> @vec512_i8_signed_mem_reg(ptr %a1_addr, <64 x i8> %a2) nounwind
; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm4
; AVX512F-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm5
; AVX512F-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4
-; AVX512F-NEXT: vpminsb %ymm2, %ymm3, %ymm5
-; AVX512F-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2
-; AVX512F-NEXT: vpsubb %ymm5, %ymm2, %ymm2
; AVX512F-NEXT: vpminsb %ymm0, %ymm1, %ymm5
; AVX512F-NEXT: vpmaxsb %ymm0, %ymm1, %ymm0
; AVX512F-NEXT: vpsubb %ymm5, %ymm0, %ymm0
-; AVX512F-NEXT: vpsrlw $1, %ymm0, %ymm0
+; AVX512F-NEXT: vpminsb %ymm2, %ymm3, %ymm5
+; AVX512F-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2
+; AVX512F-NEXT: vpsubb %ymm5, %ymm2, %ymm2
; AVX512F-NEXT: vpsrlw $1, %ymm2, %ymm2
+; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
+; AVX512F-NEXT: vpand %ymm5, %ymm2, %ymm2
+; AVX512F-NEXT: vpsrlw $1, %ymm0, %ymm0
+; AVX512F-NEXT: vpand %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm5
-; AVX512F-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; AVX512F-NEXT: vpandq %zmm6, %zmm5, %zmm5
-; AVX512F-NEXT: vpand %ymm6, %ymm2, %ymm2
-; AVX512F-NEXT: vpxor %xmm7, %xmm7, %xmm7
-; AVX512F-NEXT: vpsubb %ymm2, %ymm7, %ymm2
-; AVX512F-NEXT: vpand %ymm6, %ymm0, %ymm0
-; AVX512F-NEXT: vpsubb %ymm0, %ymm7, %ymm0
+; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6
+; AVX512F-NEXT: vpsubb %ymm2, %ymm6, %ymm2
+; AVX512F-NEXT: vpsubb %ymm0, %ymm6, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
; AVX512F-NEXT: vpternlogq {{.*#+}} zmm0 = zmm5 ^ (zmm4 & (zmm0 ^ zmm5))
; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm2
@@ -887,22 +886,21 @@ define <64 x i8> @vec512_i8_signed_mem_reg(ptr %a1_addr, <64 x i8> %a2) nounwind
; AVX512VL-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm4
; AVX512VL-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm5
; AVX512VL-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4
-; AVX512VL-NEXT: vpminsb %ymm2, %ymm3, %ymm5
-; AVX512VL-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2
-; AVX512VL-NEXT: vpsubb %ymm5, %ymm2, %ymm2
; AVX512VL-NEXT: vpminsb %ymm0, %ymm1, %ymm5
; AVX512VL-NEXT: vpmaxsb %ymm0, %ymm1, %ymm0
; AVX512VL-NEXT: vpsubb %ymm5, %ymm0, %ymm0
-; AVX512VL-NEXT: vpsrlw $1, %ymm0, %ymm0
+; AVX512VL-NEXT: vpminsb %ymm2, %ymm3, %ymm5
+; AVX512VL-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2
+; AVX512VL-NEXT: vpsubb %ymm5, %ymm2, %ymm2
; AVX512VL-NEXT: vpsrlw $1, %ymm2, %ymm2
+; AVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
+; AVX512VL-NEXT: vpand %ymm5, %ymm2, %ymm2
+; AVX512VL-NEXT: vpsrlw $1, %ymm0, %ymm0
+; AVX512VL-NEXT: vpand %ymm5, %ymm0, %ymm0
; AVX512VL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm5
-; AVX512VL-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; AVX512VL-NEXT: vpandq %zmm6, %zmm5, %zmm5
-; AVX512VL-NEXT: vpand %ymm6, %ymm2, %ymm2
-; AVX512VL-NEXT: vpxor %xmm7, %xmm7, %xmm7
-; AVX512VL-NEXT: vpsubb %ymm2, %ymm7, %ymm2
-; AVX512VL-NEXT: vpand %ymm6, %ymm0, %ymm0
-; AVX512VL-NEXT: vpsubb %ymm0, %ymm7, %ymm0
+; AVX512VL-NEXT: vpxor %xmm6, %xmm6, %xmm6
+; AVX512VL-NEXT: vpsubb %ymm2, %ymm6, %ymm2
+; AVX512VL-NEXT: vpsubb %ymm0, %ymm6, %ymm0
; AVX512VL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
; AVX512VL-NEXT: vpternlogq {{.*#+}} zmm0 = zmm5 ^ (zmm4 & (zmm0 ^ zmm5))
; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm2
@@ -945,22 +943,21 @@ define <64 x i8> @vec512_i8_signed_reg_mem(<64 x i8> %a1, ptr %a2_addr) nounwind
; AVX512F-NEXT: vpcmpgtb %ymm3, %ymm2, %ymm4
; AVX512F-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm5
; AVX512F-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4
-; AVX512F-NEXT: vpminsb %ymm3, %ymm2, %ymm5
-; AVX512F-NEXT: vpmaxsb %ymm3, %ymm2, %ymm3
-; AVX512F-NEXT: vpsubb %ymm5, %ymm3, %ymm3
; AVX512F-NEXT: vpminsb %ymm1, %ymm0, %ymm5
; AVX512F-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX512F-NEXT: vpsubb %ymm5, %ymm1, %ymm1
-; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1
+; AVX512F-NEXT: vpminsb %ymm3, %ymm2, %ymm5
+; AVX512F-NEXT: vpmaxsb %ymm3, %ymm2, %ymm3
+; AVX512F-NEXT: vpsubb %ymm5, %ymm3, %ymm3
; AVX512F-NEXT: vpsrlw $1, %ymm3, %ymm3
+; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
+; AVX512F-NEXT: vpand %ymm5, %ymm3, %ymm3
+; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1
+; AVX512F-NEXT: vpand %ymm5, %ymm1, %ymm1
; AVX512F-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm5
-; AVX512F-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; AVX512F-NEXT: vpandq %zmm6, %zmm5, %zmm5
-; AVX512F-NEXT: vpand %ymm6, %ymm3, %ymm3
-; AVX512F-NEXT: vpxor %xmm7, %xmm7, %xmm7
-; AVX512F-NEXT: vpsubb %ymm3, %ymm7, %ymm3
-; AVX512F-NEXT: vpand %ymm6, %ymm1, %ymm1
-; AVX512F-NEXT: vpsubb %ymm1, %ymm7, %ymm1
+; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6
+; AVX512F-NEXT: vpsubb %ymm3, %ymm6, %ymm3
+; AVX512F-NEXT: vpsubb %ymm1, %ymm6, %ymm1
; AVX512F-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm1
; AVX512F-NEXT: vpternlogq {{.*#+}} zmm1 = zmm5 ^ (zmm4 & (zmm1 ^ zmm5))
; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm3
@@ -977,22 +974,21 @@ define <64 x i8> @vec512_i8_signed_reg_mem(<64 x i8> %a1, ptr %a2_addr) nounwind
; AVX512VL-NEXT: vpcmpgtb %ymm3, %ymm2, %ymm4
; AVX512VL-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm5
; AVX512VL-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4
-; AVX512VL-NEXT: vpminsb %ymm3, %ymm2, %ymm5
-; AVX512VL-NEXT: vpmaxsb %ymm3, %ymm2, %ymm3
-; AVX512VL-NEXT: vpsubb %ymm5, %ymm3, %ymm3
; AVX512VL-NEXT: vpminsb %ymm1, %ymm0, %ymm5
; AVX512VL-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX512VL-NEXT: vpsubb %ymm5, %ymm1, %ymm1
-; AVX512VL-NEXT: vpsrlw $1, %ymm1, %ymm1
+; AVX512VL-NEXT: vpminsb %ymm3, %ymm2, %ymm5
+; AVX512VL-NEXT: vpmaxsb %ymm3, %ymm2, %ymm3
+; AVX512VL-NEXT: vpsubb %ymm5, %ymm3, %ymm3
; AVX512VL-NEXT: vpsrlw $1, %ymm3, %ymm3
+; AVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
+; AVX512VL-NEXT: vpand %ymm5, %ymm3, %ymm3
+; AVX512VL-NEXT: vpsrlw $1, %ymm1, %ymm1
+; AVX512VL-NEXT: vpand %ymm5, %ymm1, %ymm1
; AVX512VL-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm5
-; AVX512VL-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; AVX512VL-NEXT: vpandq %zmm6, %zmm5, %zmm5
-; AVX512VL-NEXT: vpand %ymm6, %ymm3, %ymm3
-; AVX512VL-NEXT: vpxor %xmm7, %xmm7, %xmm7
-; AVX512VL-NEXT: vpsubb %ymm3, %ymm7, %ymm3
-; AVX512VL-NEXT: vpand %ymm6, %ymm1, %ymm1
-; AVX512VL-NEXT: vpsubb %ymm1, %ymm7, %ymm1
+; AVX512VL-NEXT: vpxor %xmm6, %xmm6, %xmm6
+; AVX512VL-NEXT: vpsubb %ymm3, %ymm6, %ymm3
+; AVX512VL-NEXT: vpsubb %ymm1, %ymm6, %ymm1
; AVX512VL-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm1
; AVX512VL-NEXT: vpternlogq {{.*#+}} zmm1 = zmm5 ^ (zmm4 & (zmm1 ^ zmm5))
; AVX512VL-NEXT: vextracti64x4 $1, %zmm1, %ymm3
@@ -1036,22 +1032,21 @@ define <64 x i8> @vec512_i8_signed_mem_mem(ptr %a1_addr, ptr %a2_addr) nounwind
; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm4
; AVX512F-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm5
; AVX512F-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4
-; AVX512F-NEXT: vpminsb %ymm2, %ymm3, %ymm5
-; AVX512F-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2
-; AVX512F-NEXT: vpsubb %ymm5, %ymm2, %ymm2
; AVX512F-NEXT: vpminsb %ymm1, %ymm0, %ymm5
; AVX512F-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX512F-NEXT: vpsubb %ymm5, %ymm1, %ymm1
-; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1
+; AVX512F-NEXT: vpminsb %ymm2, %ymm3, %ymm5
+; AVX512F-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2
+; AVX512F-NEXT: vpsubb %ymm5, %ymm2, %ymm2
; AVX512F-NEXT: vpsrlw $1, %ymm2, %ymm2
+; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
+; AVX512F-NEXT: vpand %ymm5, %ymm2, %ymm2
+; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1
+; AVX512F-NEXT: vpand %ymm5, %ymm1, %ymm1
; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm5
-; AVX512F-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; AVX512F-NEXT: vpandq %zmm6, %zmm5, %zmm5
-; AVX512F-NEXT: vpand %ymm6, %ymm2, %ymm2
-; AVX512F-NEXT: vpxor %xmm7, %xmm7, %xmm7
-; AVX512F-NEXT: vpsubb %ymm2, %ymm7, %ymm2
-; AVX512F-NEXT: vpand %ymm6, %ymm1, %ymm1
-; AVX512F-NEXT: vpsubb %ymm1, %ymm7, %ymm1
+; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6
+; AVX512F-NEXT: vpsubb %ymm2, %ymm6, %ymm2
+; AVX512F-NEXT: vpsubb %ymm1, %ymm6, %ymm1
; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1
; AVX512F-NEXT: vpternlogq {{.*#+}} zmm1 = zmm5 ^ (zmm4 & (zmm1 ^ zmm5))
; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2
@@ -1069,22 +1064,21 @@ define <64 x i8> @vec512_i8_signed_mem_mem(ptr %a1_addr, ptr %a2_addr) nounwind
; AVX512VL-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm4
; AVX512VL-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm5
; AVX512VL-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4
-; AVX512VL-NEXT: vpminsb %ymm2, %ymm3, %ymm5
-; AVX512VL-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2
-; AVX512VL-NEXT: vpsubb %ymm5, %ymm2, %ymm2
; AVX512VL-NEXT: vpminsb %ymm1, %ymm0, %ymm5
; AVX512VL-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX512VL-NEXT: vpsubb %ymm5, %ymm1, %ymm1
-; AVX512VL-NEXT: vpsrlw $1, %ymm1, %ymm1
+; AVX512VL-NEXT: vpminsb %ymm2, %ymm3, %ymm5
+; AVX512VL-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2
+; AVX512VL-NEXT: vpsubb %ymm5, %ymm2, %ymm2
; AVX512VL-NEXT: vpsrlw $1, %ymm2, %ymm2
+; AVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
+; AVX512VL-NEXT: vpand %ymm5, %ymm2, %ymm2
+; AVX512VL-NEXT: vpsrlw $1, %ymm1, %ymm1
+; AVX512VL-NEXT: vpand %ymm5, %ymm1, %ymm1
; AVX512VL-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm5
-; AVX512VL-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; AVX512VL-NEXT: vpandq %zmm6, %zmm5, %zmm5
-; AVX512VL-NEXT: vpand %ymm6, %ymm2, %ymm2
-; AVX512VL-NEXT: vpxor %xmm7, %xmm7, %xmm7
-; AVX512VL-NEXT: vpsubb %ymm2, %ymm7, %ymm2
-; AVX512VL-NEXT: vpand %ymm6, %ymm1, %ymm1
-; AVX512VL-NEXT: vpsubb %ymm1, %ymm7, %ymm1
+; AVX512VL-NEXT: vpxor %xmm6, %xmm6, %xmm6
+; AVX512VL-NEXT: vpsubb %ymm2, %ymm6, %ymm2
+; AVX512VL-NEXT: vpsubb %ymm1, %ymm6, %ymm1
; AVX512VL-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1
; AVX512VL-NEXT: vpternlogq {{.*#+}} zmm1 = zmm5 ^ (zmm4 & (zmm1 ^ zmm5))
; AVX512VL-NEXT: vextracti64x4 $1, %zmm1, %ymm2
diff --git a/llvm/test/CodeGen/X86/pr120906.ll b/llvm/test/CodeGen/X86/pr120906.ll
index f5f6331bf3bf6..f95598a0a4fa6 100644
--- a/llvm/test/CodeGen/X86/pr120906.ll
+++ b/llvm/test/CodeGen/X86/pr120906.ll
@@ -11,17 +11,16 @@ define i32 @PR120906(ptr %p) {
; CHECK-NEXT: paddb %xmm1, %xmm1
; CHECK-NEXT: pxor %xmm2, %xmm2
; CHECK-NEXT: pcmpgtb %xmm1, %xmm2
-; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [11,11,11,11,u,u,u,u,u,u,u,u,u,u,u,u]
-; CHECK-NEXT: movdqa %xmm1, %xmm3
-; CHECK-NEXT: paddb %xmm1, %xmm3
-; CHECK-NEXT: pand %xmm2, %xmm3
-; CHECK-NEXT: pandn %xmm1, %xmm2
-; CHECK-NEXT: por %xmm1, %xmm2
-; CHECK-NEXT: por %xmm3, %xmm2
-; CHECK-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
-; CHECK-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
-; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,2,3]
-; CHECK-NEXT: por %xmm2, %xmm0
+; CHECK-NEXT: movd {{.*#+}} xmm1 = [11,11,11,11,0,0,0,0,0,0,0,0,0,0,0,0]
+; CHECK-NEXT: movdqa %xmm2, %xmm3
+; CHECK-NEXT: pandn %xmm1, %xmm3
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; CHECK-NEXT: por %xmm1, %xmm3
+; CHECK-NEXT: por %xmm2, %xmm3
+; CHECK-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm3[2,3,2,3]
+; CHECK-NEXT: por %xmm3, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
; CHECK-NEXT: por %xmm0, %xmm1
; CHECK-NEXT: movd %xmm1, %eax
diff --git a/llvm/test/CodeGen/X86/setcc-non-simple-type.ll b/llvm/test/CodeGen/X86/setcc-non-simple-type.ll
index 2ac2be5545dfd..d2b292f1a7996 100644
--- a/llvm/test/CodeGen/X86/setcc-non-simple-type.ll
+++ b/llvm/test/CodeGen/X86/setcc-non-simple-type.ll
@@ -119,8 +119,8 @@ define void @failing(ptr %0, ptr %1) nounwind {
; CHECK-AVX2-NEXT: .LBB0_2: # %vector.body
; CHECK-AVX2-NEXT: # Parent Loop BB0_1 Depth=1
; CHECK-AVX2-NEXT: # => This Inner Loop Header: Depth=2
-; CHECK-AVX2-NEXT: vmovdqu 1024(%rdx,%rsi), %xmm5
-; CHECK-AVX2-NEXT: vmovdqu 1040(%rdx,%rsi), %xmm6
+; CHECK-AVX2-NEXT: vmovdqu 1024(%rdx,%rsi), %ymm5
+; CHECK-AVX2-NEXT: vextracti128 $1, %ymm5, %xmm6
; CHECK-AVX2-NEXT: vpextrq $1, %xmm5, %rdi
; CHECK-AVX2-NEXT: vpextrq $1, %xmm6, %r8
; CHECK-AVX2-NEXT: vmovq %xmm5, %r9
diff --git a/llvm/test/CodeGen/X86/shift-i128.ll b/llvm/test/CodeGen/X86/shift-i128.ll
index 73755f5b2a5ee..38c498b4b1e6e 100644
--- a/llvm/test/CodeGen/X86/shift-i128.ll
+++ b/llvm/test/CodeGen/X86/shift-i128.ll
@@ -1077,25 +1077,25 @@ define i128 @shift_i128_limited_shamt_unknown_lhs(i128 noundef %a, i32 noundef %
; i686-NEXT: pushl %esi
; i686-NEXT: andl $-16, %esp
; i686-NEXT: subl $48, %esp
+; i686-NEXT: movl 44(%ebp), %ecx
; i686-NEXT: movl 24(%ebp), %eax
; i686-NEXT: movl 28(%ebp), %edx
; i686-NEXT: movl 32(%ebp), %esi
; i686-NEXT: movl 36(%ebp), %edi
-; i686-NEXT: movl 44(%ebp), %ecx
; i686-NEXT: subl 40(%ebp), %ecx
; i686-NEXT: movl %edi, {{[0-9]+}}(%esp)
; i686-NEXT: movl %esi, {{[0-9]+}}(%esp)
; i686-NEXT: movl %edx, {{[0-9]+}}(%esp)
; i686-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; i686-NEXT: movl $0, {{[0-9]+}}(%esp)
-; i686-NEXT: movl $0, {{[0-9]+}}(%esp)
-; i686-NEXT: movl $0, {{[0-9]+}}(%esp)
-; i686-NEXT: movl $0, (%esp)
; i686-NEXT: movl %ecx, %eax
; i686-NEXT: shrb $3, %al
; i686-NEXT: andb $12, %al
; i686-NEXT: negb %al
; i686-NEXT: movsbl %al, %eax
+; i686-NEXT: movl $0, {{[0-9]+}}(%esp)
+; i686-NEXT: movl $0, {{[0-9]+}}(%esp)
+; i686-NEXT: movl $0, {{[0-9]+}}(%esp)
+; i686-NEXT: movl $0, (%esp)
; i686-NEXT: movl 20(%esp,%eax), %edx
; i686-NEXT: movl 24(%esp,%eax), %ebx
; i686-NEXT: movl %ebx, %edi
diff --git a/llvm/test/CodeGen/X86/shift-i512.ll b/llvm/test/CodeGen/X86/shift-i512.ll
index ecbab7d022092..077dd86d01fab 100644
--- a/llvm/test/CodeGen/X86/shift-i512.ll
+++ b/llvm/test/CodeGen/X86/shift-i512.ll
@@ -2500,7 +2500,7 @@ define i64 @lshr_extract_i512_i64(i512 %a0, i512 %a1) nounwind {
; AVX512F-LABEL: lshr_extract_i512_i64:
; AVX512F: # %bb.0:
; AVX512F-NEXT: pushq %rax
-; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; AVX512F-NEXT: movl {{[0-9]+}}(%rsp), %r10d
; AVX512F-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm0
; AVX512F-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: vmovups %zmm1, -{{[0-9]+}}(%rsp)
@@ -2524,7 +2524,7 @@ define i64 @lshr_extract_i512_i64(i512 %a0, i512 %a1) nounwind {
; AVX512VL-LABEL: lshr_extract_i512_i64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: pushq %rax
-; AVX512VL-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; AVX512VL-NEXT: movl {{[0-9]+}}(%rsp), %r10d
; AVX512VL-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm0
; AVX512VL-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX512VL-NEXT: vmovups %ymm1, -{{[0-9]+}}(%rsp)
@@ -2550,7 +2550,7 @@ define i64 @lshr_extract_i512_i64(i512 %a0, i512 %a1) nounwind {
; AVX512VBMI-LABEL: lshr_extract_i512_i64:
; AVX512VBMI: # %bb.0:
; AVX512VBMI-NEXT: pushq %rax
-; AVX512VBMI-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; AVX512VBMI-NEXT: movl {{[0-9]+}}(%rsp), %r10d
; AVX512VBMI-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm0
; AVX512VBMI-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX512VBMI-NEXT: vmovups %ymm1, -{{[0-9]+}}(%rsp)
@@ -2578,105 +2578,38 @@ define i64 @lshr_extract_i512_i64(i512 %a0, i512 %a1) nounwind {
}
define i64 @ashr_extract_i512_i64(i512 %a0, i512 %a1) nounwind {
-; SSE-LABEL: ashr_extract_i512_i64:
-; SSE: # %bb.0:
-; SSE-NEXT: pushq %rax
-; SSE-NEXT: movl {{[0-9]+}}(%rsp), %r10d
-; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rax
-; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r11
-; SSE-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movq %r9, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movq %r8, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movq %rsi, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movq %rdi, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: sarq $63, %r11
-; SSE-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movl %r10d, %ecx
-; SSE-NEXT: shrl $3, %ecx
-; SSE-NEXT: andl $56, %ecx
-; SSE-NEXT: movq -128(%rsp,%rcx), %rax
-; SSE-NEXT: movq -120(%rsp,%rcx), %rdx
-; SSE-NEXT: movl %r10d, %ecx
-; SSE-NEXT: shrdq %cl, %rdx, %rax
-; SSE-NEXT: popq %rcx
-; SSE-NEXT: retq
-;
-; AVX2-LABEL: ashr_extract_i512_i64:
-; AVX2: # %bb.0:
-; AVX2-NEXT: pushq %rax
-; AVX2-NEXT: movl {{[0-9]+}}(%rsp), %r10d
-; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rax
-; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r11
-; AVX2-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movq %r9, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movq %r8, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movq %rsi, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movq %rdi, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: sarq $63, %r11
-; AVX2-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movl %r10d, %ecx
-; AVX2-NEXT: shrl $3, %ecx
-; AVX2-NEXT: andl $56, %ecx
-; AVX2-NEXT: movq -128(%rsp,%rcx), %rax
-; AVX2-NEXT: movq -120(%rsp,%rcx), %rdx
-; AVX2-NEXT: movl %r10d, %ecx
-; AVX2-NEXT: shrdq %cl, %rdx, %rax
-; AVX2-NEXT: popq %rcx
-; AVX2-NEXT: retq
-;
-; AVX512-LABEL: ashr_extract_i512_i64:
-; AVX512: # %bb.0:
-; AVX512-NEXT: pushq %rax
-; AVX512-NEXT: movq %rcx, %rax
-; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rcx
-; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %r10
-; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %r11
-; AVX512-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; AVX512-NEXT: movq %r10, -{{[0-9]+}}(%rsp)
-; AVX512-NEXT: movq %r9, -{{[0-9]+}}(%rsp)
-; AVX512-NEXT: movq %r8, -{{[0-9]+}}(%rsp)
-; AVX512-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
-; AVX512-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
-; AVX512-NEXT: movq %rsi, -{{[0-9]+}}(%rsp)
-; AVX512-NEXT: movq %rdi, -{{[0-9]+}}(%rsp)
-; AVX512-NEXT: sarq $63, %r11
-; AVX512-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; AVX512-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; AVX512-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; AVX512-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; AVX512-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; AVX512-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; AVX512-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; AVX512-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
-; AVX512-NEXT: movl %ecx, %edx
-; AVX512-NEXT: shrl $3, %edx
-; AVX512-NEXT: andl $56, %edx
-; AVX512-NEXT: movq -128(%rsp,%rdx), %rax
-; AVX512-NEXT: movq -120(%rsp,%rdx), %rdx
-; AVX512-NEXT: # kill: def $cl killed $cl killed $rcx
-; AVX512-NEXT: shrdq %cl, %rdx, %rax
-; AVX512-NEXT: popq %rcx
-; AVX512-NEXT: retq
+; CHECK-LABEL: ashr_extract_i512_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rax
+; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %r10d
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; CHECK-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %r9, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %r8, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %rsi, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %rdi, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: sarq $63, %r11
+; CHECK-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movq %r11, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movl %r10d, %ecx
+; CHECK-NEXT: shrl $3, %ecx
+; CHECK-NEXT: andl $56, %ecx
+; CHECK-NEXT: movq -128(%rsp,%rcx), %rax
+; CHECK-NEXT: movq -120(%rsp,%rcx), %rdx
+; CHECK-NEXT: movl %r10d, %ecx
+; CHECK-NEXT: shrdq %cl, %rdx, %rax
+; CHECK-NEXT: popq %rcx
+; CHECK-NEXT: retq
%b = ashr i512 %a0, %a1
%r = trunc i512 %b to i64
ret i64 %r
diff --git a/llvm/test/CodeGen/X86/vector-compare-all_of.ll b/llvm/test/CodeGen/X86/vector-compare-all_of.ll
index 8995989ef4474..1640736fbbda7 100644
--- a/llvm/test/CodeGen/X86/vector-compare-all_of.ll
+++ b/llvm/test/CodeGen/X86/vector-compare-all_of.ll
@@ -1549,9 +1549,10 @@ define i1 @select_v2i8(ptr %s0, ptr %s1) {
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm1[0,0,1,1,4,5,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
-; SSE2-NEXT: movmskpd %xmm0, %eax
-; SSE2-NEXT: cmpl $3, %eax
-; SSE2-NEXT: sete %al
+; SSE2-NEXT: movmskpd %xmm0, %ecx
+; SSE2-NEXT: movl %ecx, %eax
+; SSE2-NEXT: shrb %al
+; SSE2-NEXT: andb %cl, %al
; SSE2-NEXT: retq
;
; SSE42-LABEL: select_v2i8:
@@ -1562,9 +1563,10 @@ define i1 @select_v2i8(ptr %s0, ptr %s1) {
; SSE42-NEXT: movd %eax, %xmm1
; SSE42-NEXT: pcmpeqb %xmm0, %xmm1
; SSE42-NEXT: pmovsxbq %xmm1, %xmm0
-; SSE42-NEXT: movmskpd %xmm0, %eax
-; SSE42-NEXT: cmpl $3, %eax
-; SSE42-NEXT: sete %al
+; SSE42-NEXT: movmskpd %xmm0, %ecx
+; SSE42-NEXT: movl %ecx, %eax
+; SSE42-NEXT: shrb %al
+; SSE42-NEXT: andb %cl, %al
; SSE42-NEXT: retq
;
; AVX1OR2-LABEL: select_v2i8:
@@ -1575,21 +1577,16 @@ define i1 @select_v2i8(ptr %s0, ptr %s1) {
; AVX1OR2-NEXT: vmovd %eax, %xmm1
; AVX1OR2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX1OR2-NEXT: vpmovsxbq %xmm0, %xmm0
-; AVX1OR2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
-; AVX1OR2-NEXT: vtestpd %xmm1, %xmm0
-; AVX1OR2-NEXT: setb %al
+; AVX1OR2-NEXT: vmovmskpd %xmm0, %ecx
+; AVX1OR2-NEXT: movl %ecx, %eax
+; AVX1OR2-NEXT: shrb %al
+; AVX1OR2-NEXT: andb %cl, %al
; AVX1OR2-NEXT: retq
;
; AVX512-LABEL: select_v2i8:
; AVX512: # %bb.0:
-; AVX512-NEXT: movzwl (%rdi), %eax
-; AVX512-NEXT: vmovd %eax, %xmm0
; AVX512-NEXT: movzwl (%rsi), %eax
-; AVX512-NEXT: vmovd %eax, %xmm1
-; AVX512-NEXT: vpcmpeqb %xmm1, %xmm0, %k0
-; AVX512-NEXT: knotw %k0, %k0
-; AVX512-NEXT: kmovd %k0, %eax
-; AVX512-NEXT: testb $3, %al
+; AVX512-NEXT: cmpw %ax, (%rdi)
; AVX512-NEXT: sete %al
; AVX512-NEXT: retq
%v0 = load <2 x i8>, ptr %s0, align 1
diff --git a/llvm/test/CodeGen/X86/vector-compare-any_of.ll b/llvm/test/CodeGen/X86/vector-compare-any_of.ll
index 24fee35c73404..49065c73df19e 100644
--- a/llvm/test/CodeGen/X86/vector-compare-any_of.ll
+++ b/llvm/test/CodeGen/X86/vector-compare-any_of.ll
@@ -1432,9 +1432,10 @@ define i1 @select_v2i8(ptr %s0, ptr %s1) {
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm1[0,0,1,1,4,5,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
-; SSE2-NEXT: movmskpd %xmm0, %eax
-; SSE2-NEXT: testl %eax, %eax
-; SSE2-NEXT: setne %al
+; SSE2-NEXT: movmskpd %xmm0, %ecx
+; SSE2-NEXT: movl %ecx, %eax
+; SSE2-NEXT: shrb %al
+; SSE2-NEXT: orb %cl, %al
; SSE2-NEXT: retq
;
; SSE42-LABEL: select_v2i8:
@@ -1445,9 +1446,10 @@ define i1 @select_v2i8(ptr %s0, ptr %s1) {
; SSE42-NEXT: movd %eax, %xmm1
; SSE42-NEXT: pcmpeqb %xmm0, %xmm1
; SSE42-NEXT: pmovsxbq %xmm1, %xmm0
-; SSE42-NEXT: movmskpd %xmm0, %eax
-; SSE42-NEXT: testl %eax, %eax
-; SSE42-NEXT: setne %al
+; SSE42-NEXT: movmskpd %xmm0, %ecx
+; SSE42-NEXT: movl %ecx, %eax
+; SSE42-NEXT: shrb %al
+; SSE42-NEXT: orb %cl, %al
; SSE42-NEXT: retq
;
; AVX1OR2-LABEL: select_v2i8:
@@ -1458,8 +1460,10 @@ define i1 @select_v2i8(ptr %s0, ptr %s1) {
; AVX1OR2-NEXT: vmovd %eax, %xmm1
; AVX1OR2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX1OR2-NEXT: vpmovsxbq %xmm0, %xmm0
-; AVX1OR2-NEXT: vtestpd %xmm0, %xmm0
-; AVX1OR2-NEXT: setne %al
+; AVX1OR2-NEXT: vmovmskpd %xmm0, %ecx
+; AVX1OR2-NEXT: movl %ecx, %eax
+; AVX1OR2-NEXT: shrb %al
+; AVX1OR2-NEXT: orb %cl, %al
; AVX1OR2-NEXT: retq
;
; AVX512-LABEL: select_v2i8:
diff --git a/llvm/test/CodeGen/X86/vector-fshr-128.ll b/llvm/test/CodeGen/X86/vector-fshr-128.ll
index 2ef640e99945d..2a69640fb679e 100644
--- a/llvm/test/CodeGen/X86/vector-fshr-128.ll
+++ b/llvm/test/CodeGen/X86/vector-fshr-128.ll
@@ -733,65 +733,65 @@ define <8 x i16> @var_funnnel_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %amt)
define <16 x i8> @var_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %amt) nounwind {
; SSE2-LABEL: var_funnnel_v16i8:
; SSE2: # %bb.0:
-; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
-; SSE2-NEXT: movdqa %xmm2, %xmm6
-; SSE2-NEXT: pand %xmm5, %xmm6
-; SSE2-NEXT: psllw $5, %xmm6
-; SSE2-NEXT: pxor %xmm4, %xmm4
+; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
+; SSE2-NEXT: movdqa %xmm2, %xmm5
+; SSE2-NEXT: pandn %xmm4, %xmm5
+; SSE2-NEXT: psllw $5, %xmm5
; SSE2-NEXT: pxor %xmm3, %xmm3
-; SSE2-NEXT: pcmpgtb %xmm6, %xmm3
-; SSE2-NEXT: movdqa %xmm3, %xmm7
-; SSE2-NEXT: pandn %xmm1, %xmm7
-; SSE2-NEXT: psrlw $4, %xmm1
-; SSE2-NEXT: pand %xmm1, %xmm3
-; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
-; SSE2-NEXT: por %xmm7, %xmm3
-; SSE2-NEXT: paddb %xmm6, %xmm6
-; SSE2-NEXT: pxor %xmm1, %xmm1
-; SSE2-NEXT: pcmpgtb %xmm6, %xmm1
-; SSE2-NEXT: movdqa %xmm1, %xmm7
-; SSE2-NEXT: pandn %xmm3, %xmm7
-; SSE2-NEXT: psrlw $2, %xmm3
-; SSE2-NEXT: pand %xmm1, %xmm3
-; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
-; SSE2-NEXT: por %xmm7, %xmm3
-; SSE2-NEXT: paddb %xmm6, %xmm6
-; SSE2-NEXT: pxor %xmm1, %xmm1
-; SSE2-NEXT: pcmpgtb %xmm6, %xmm1
-; SSE2-NEXT: movdqa %xmm1, %xmm6
-; SSE2-NEXT: pandn %xmm3, %xmm6
-; SSE2-NEXT: psrlw $1, %xmm3
-; SSE2-NEXT: pand %xmm1, %xmm3
-; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
-; SSE2-NEXT: por %xmm6, %xmm3
-; SSE2-NEXT: pandn %xmm5, %xmm2
-; SSE2-NEXT: psllw $5, %xmm2
-; SSE2-NEXT: pxor %xmm1, %xmm1
-; SSE2-NEXT: pcmpgtb %xmm2, %xmm1
+; SSE2-NEXT: pxor %xmm6, %xmm6
+; SSE2-NEXT: pcmpgtb %xmm5, %xmm6
; SSE2-NEXT: paddb %xmm0, %xmm0
-; SSE2-NEXT: movdqa %xmm1, %xmm5
-; SSE2-NEXT: pandn %xmm0, %xmm5
+; SSE2-NEXT: movdqa %xmm6, %xmm7
+; SSE2-NEXT: pandn %xmm0, %xmm7
; SSE2-NEXT: psllw $4, %xmm0
-; SSE2-NEXT: pand %xmm1, %xmm0
+; SSE2-NEXT: pand %xmm6, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: por %xmm7, %xmm0
+; SSE2-NEXT: paddb %xmm5, %xmm5
+; SSE2-NEXT: pxor %xmm6, %xmm6
+; SSE2-NEXT: pcmpgtb %xmm5, %xmm6
+; SSE2-NEXT: movdqa %xmm6, %xmm7
+; SSE2-NEXT: pandn %xmm0, %xmm7
+; SSE2-NEXT: paddb %xmm0, %xmm0
+; SSE2-NEXT: paddb %xmm0, %xmm0
+; SSE2-NEXT: pand %xmm6, %xmm0
+; SSE2-NEXT: por %xmm7, %xmm0
+; SSE2-NEXT: paddb %xmm5, %xmm5
+; SSE2-NEXT: pxor %xmm6, %xmm6
+; SSE2-NEXT: pcmpgtb %xmm5, %xmm6
+; SSE2-NEXT: movdqa %xmm6, %xmm5
+; SSE2-NEXT: pandn %xmm0, %xmm5
+; SSE2-NEXT: paddb %xmm0, %xmm0
+; SSE2-NEXT: pand %xmm6, %xmm0
; SSE2-NEXT: por %xmm5, %xmm0
+; SSE2-NEXT: pand %xmm4, %xmm2
+; SSE2-NEXT: psllw $5, %xmm2
+; SSE2-NEXT: pxor %xmm4, %xmm4
+; SSE2-NEXT: pcmpgtb %xmm2, %xmm4
+; SSE2-NEXT: movdqa %xmm4, %xmm5
+; SSE2-NEXT: pandn %xmm1, %xmm5
+; SSE2-NEXT: psrlw $4, %xmm1
+; SSE2-NEXT: pand %xmm1, %xmm4
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
+; SSE2-NEXT: por %xmm5, %xmm4
; SSE2-NEXT: paddb %xmm2, %xmm2
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpgtb %xmm2, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm5
-; SSE2-NEXT: pandn %xmm0, %xmm5
-; SSE2-NEXT: paddb %xmm0, %xmm0
-; SSE2-NEXT: paddb %xmm0, %xmm0
-; SSE2-NEXT: pand %xmm1, %xmm0
-; SSE2-NEXT: por %xmm5, %xmm0
+; SSE2-NEXT: pandn %xmm4, %xmm5
+; SSE2-NEXT: psrlw $2, %xmm4
+; SSE2-NEXT: pand %xmm1, %xmm4
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
+; SSE2-NEXT: por %xmm5, %xmm4
; SSE2-NEXT: paddb %xmm2, %xmm2
-; SSE2-NEXT: pcmpgtb %xmm2, %xmm4
-; SSE2-NEXT: movdqa %xmm4, %xmm1
-; SSE2-NEXT: pandn %xmm0, %xmm1
-; SSE2-NEXT: paddb %xmm0, %xmm0
-; SSE2-NEXT: pand %xmm4, %xmm0
-; SSE2-NEXT: por %xmm1, %xmm0
-; SSE2-NEXT: por %xmm3, %xmm0
+; SSE2-NEXT: pcmpgtb %xmm2, %xmm3
+; SSE2-NEXT: movdqa %xmm3, %xmm1
+; SSE2-NEXT: pandn %xmm4, %xmm1
+; SSE2-NEXT: psrlw $1, %xmm4
+; SSE2-NEXT: pand %xmm3, %xmm4
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
+; SSE2-NEXT: por %xmm1, %xmm4
+; SSE2-NEXT: por %xmm4, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: var_funnnel_v16i8:
@@ -1023,65 +1023,65 @@ define <16 x i8> @var_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %amt)
;
; X86-SSE2-LABEL: var_funnnel_v16i8:
; X86-SSE2: # %bb.0:
-; X86-SSE2-NEXT: movdqa {{.*#+}} xmm5 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
-; X86-SSE2-NEXT: movdqa %xmm2, %xmm6
-; X86-SSE2-NEXT: pand %xmm5, %xmm6
-; X86-SSE2-NEXT: psllw $5, %xmm6
-; X86-SSE2-NEXT: pxor %xmm4, %xmm4
+; X86-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
+; X86-SSE2-NEXT: movdqa %xmm2, %xmm5
+; X86-SSE2-NEXT: pandn %xmm4, %xmm5
+; X86-SSE2-NEXT: psllw $5, %xmm5
; X86-SSE2-NEXT: pxor %xmm3, %xmm3
-; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm3
-; X86-SSE2-NEXT: movdqa %xmm3, %xmm7
-; X86-SSE2-NEXT: pandn %xmm1, %xmm7
-; X86-SSE2-NEXT: psrlw $4, %xmm1
-; X86-SSE2-NEXT: pand %xmm1, %xmm3
-; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3
-; X86-SSE2-NEXT: por %xmm7, %xmm3
-; X86-SSE2-NEXT: paddb %xmm6, %xmm6
-; X86-SSE2-NEXT: pxor %xmm1, %xmm1
-; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm1
-; X86-SSE2-NEXT: movdqa %xmm1, %xmm7
-; X86-SSE2-NEXT: pandn %xmm3, %xmm7
-; X86-SSE2-NEXT: psrlw $2, %xmm3
-; X86-SSE2-NEXT: pand %xmm1, %xmm3
-; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3
-; X86-SSE2-NEXT: por %xmm7, %xmm3
-; X86-SSE2-NEXT: paddb %xmm6, %xmm6
-; X86-SSE2-NEXT: pxor %xmm1, %xmm1
-; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm1
-; X86-SSE2-NEXT: movdqa %xmm1, %xmm6
-; X86-SSE2-NEXT: pandn %xmm3, %xmm6
-; X86-SSE2-NEXT: psrlw $1, %xmm3
-; X86-SSE2-NEXT: pand %xmm1, %xmm3
-; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3
-; X86-SSE2-NEXT: por %xmm6, %xmm3
-; X86-SSE2-NEXT: pandn %xmm5, %xmm2
-; X86-SSE2-NEXT: psllw $5, %xmm2
-; X86-SSE2-NEXT: pxor %xmm1, %xmm1
-; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm1
+; X86-SSE2-NEXT: pxor %xmm6, %xmm6
+; X86-SSE2-NEXT: pcmpgtb %xmm5, %xmm6
; X86-SSE2-NEXT: paddb %xmm0, %xmm0
-; X86-SSE2-NEXT: movdqa %xmm1, %xmm5
-; X86-SSE2-NEXT: pandn %xmm0, %xmm5
+; X86-SSE2-NEXT: movdqa %xmm6, %xmm7
+; X86-SSE2-NEXT: pandn %xmm0, %xmm7
; X86-SSE2-NEXT: psllw $4, %xmm0
-; X86-SSE2-NEXT: pand %xmm1, %xmm0
+; X86-SSE2-NEXT: pand %xmm6, %xmm0
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: por %xmm7, %xmm0
+; X86-SSE2-NEXT: paddb %xmm5, %xmm5
+; X86-SSE2-NEXT: pxor %xmm6, %xmm6
+; X86-SSE2-NEXT: pcmpgtb %xmm5, %xmm6
+; X86-SSE2-NEXT: movdqa %xmm6, %xmm7
+; X86-SSE2-NEXT: pandn %xmm0, %xmm7
+; X86-SSE2-NEXT: paddb %xmm0, %xmm0
+; X86-SSE2-NEXT: paddb %xmm0, %xmm0
+; X86-SSE2-NEXT: pand %xmm6, %xmm0
+; X86-SSE2-NEXT: por %xmm7, %xmm0
+; X86-SSE2-NEXT: paddb %xmm5, %xmm5
+; X86-SSE2-NEXT: pxor %xmm6, %xmm6
+; X86-SSE2-NEXT: pcmpgtb %xmm5, %xmm6
+; X86-SSE2-NEXT: movdqa %xmm6, %xmm5
+; X86-SSE2-NEXT: pandn %xmm0, %xmm5
+; X86-SSE2-NEXT: paddb %xmm0, %xmm0
+; X86-SSE2-NEXT: pand %xmm6, %xmm0
; X86-SSE2-NEXT: por %xmm5, %xmm0
+; X86-SSE2-NEXT: pand %xmm4, %xmm2
+; X86-SSE2-NEXT: psllw $5, %xmm2
+; X86-SSE2-NEXT: pxor %xmm4, %xmm4
+; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm4
+; X86-SSE2-NEXT: movdqa %xmm4, %xmm5
+; X86-SSE2-NEXT: pandn %xmm1, %xmm5
+; X86-SSE2-NEXT: psrlw $4, %xmm1
+; X86-SSE2-NEXT: pand %xmm1, %xmm4
+; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm4
+; X86-SSE2-NEXT: por %xmm5, %xmm4
; X86-SSE2-NEXT: paddb %xmm2, %xmm2
; X86-SSE2-NEXT: pxor %xmm1, %xmm1
; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm1
; X86-SSE2-NEXT: movdqa %xmm1, %xmm5
-; X86-SSE2-NEXT: pandn %xmm0, %xmm5
-; X86-SSE2-NEXT: paddb %xmm0, %xmm0
-; X86-SSE2-NEXT: paddb %xmm0, %xmm0
-; X86-SSE2-NEXT: pand %xmm1, %xmm0
-; X86-SSE2-NEXT: por %xmm5, %xmm0
+; X86-SSE2-NEXT: pandn %xmm4, %xmm5
+; X86-SSE2-NEXT: psrlw $2, %xmm4
+; X86-SSE2-NEXT: pand %xmm1, %xmm4
+; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm4
+; X86-SSE2-NEXT: por %xmm5, %xmm4
; X86-SSE2-NEXT: paddb %xmm2, %xmm2
-; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm4
-; X86-SSE2-NEXT: movdqa %xmm4, %xmm1
-; X86-SSE2-NEXT: pandn %xmm0, %xmm1
-; X86-SSE2-NEXT: paddb %xmm0, %xmm0
-; X86-SSE2-NEXT: pand %xmm4, %xmm0
-; X86-SSE2-NEXT: por %xmm1, %xmm0
-; X86-SSE2-NEXT: por %xmm3, %xmm0
+; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm3
+; X86-SSE2-NEXT: movdqa %xmm3, %xmm1
+; X86-SSE2-NEXT: pandn %xmm4, %xmm1
+; X86-SSE2-NEXT: psrlw $1, %xmm4
+; X86-SSE2-NEXT: pand %xmm3, %xmm4
+; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm4
+; X86-SSE2-NEXT: por %xmm1, %xmm4
+; X86-SSE2-NEXT: por %xmm4, %xmm0
; X86-SSE2-NEXT: retl
%res = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %amt)
ret <16 x i8> %res
diff --git a/llvm/test/CodeGen/X86/vector-fshr-256.ll b/llvm/test/CodeGen/X86/vector-fshr-256.ll
index 425441b738399..b91702839481d 100644
--- a/llvm/test/CodeGen/X86/vector-fshr-256.ll
+++ b/llvm/test/CodeGen/X86/vector-fshr-256.ll
@@ -519,48 +519,48 @@ define <32 x i8> @var_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %amt)
; AVX1-NEXT: vandps %ymm3, %ymm2, %ymm2
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm7
; AVX1-NEXT: vpsllw $5, %xmm7, %xmm8
-; AVX1-NEXT: vpblendvb %xmm8, %xmm6, %xmm5, %xmm5
-; AVX1-NEXT: vpsrlw $2, %xmm5, %xmm9
-; AVX1-NEXT: vbroadcastss {{.*#+}} xmm6 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; AVX1-NEXT: vpand %xmm6, %xmm9, %xmm9
+; AVX1-NEXT: vpblendvb %xmm8, %xmm6, %xmm5, %xmm6
+; AVX1-NEXT: vpsrlw $2, %xmm6, %xmm9
+; AVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
+; AVX1-NEXT: vpand %xmm5, %xmm9, %xmm9
; AVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm8
-; AVX1-NEXT: vpblendvb %xmm8, %xmm9, %xmm5, %xmm5
-; AVX1-NEXT: vpsrlw $1, %xmm5, %xmm9
+; AVX1-NEXT: vpblendvb %xmm8, %xmm9, %xmm6, %xmm6
+; AVX1-NEXT: vpsrlw $1, %xmm6, %xmm9
; AVX1-NEXT: vbroadcastss {{.*#+}} xmm10 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
; AVX1-NEXT: vpand %xmm10, %xmm9, %xmm9
; AVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm8
-; AVX1-NEXT: vpblendvb %xmm8, %xmm9, %xmm5, %xmm8
-; AVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm9
-; AVX1-NEXT: vpaddb %xmm9, %xmm9, %xmm9
-; AVX1-NEXT: vpsllw $4, %xmm9, %xmm11
-; AVX1-NEXT: vpand %xmm5, %xmm11, %xmm11
+; AVX1-NEXT: vpblendvb %xmm8, %xmm9, %xmm6, %xmm6
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm8
+; AVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm8
+; AVX1-NEXT: vpsllw $4, %xmm8, %xmm9
+; AVX1-NEXT: vbroadcastss {{.*#+}} xmm11 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
+; AVX1-NEXT: vpand %xmm11, %xmm9, %xmm9
; AVX1-NEXT: vpxor %xmm3, %xmm7, %xmm7
; AVX1-NEXT: vpsllw $5, %xmm7, %xmm7
-; AVX1-NEXT: vpblendvb %xmm7, %xmm11, %xmm9, %xmm9
-; AVX1-NEXT: vpaddb %xmm9, %xmm9, %xmm11
-; AVX1-NEXT: vpaddb %xmm11, %xmm11, %xmm11
+; AVX1-NEXT: vpblendvb %xmm7, %xmm9, %xmm8, %xmm8
+; AVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm9
+; AVX1-NEXT: vpaddb %xmm9, %xmm9, %xmm9
; AVX1-NEXT: vpaddb %xmm7, %xmm7, %xmm7
-; AVX1-NEXT: vpblendvb %xmm7, %xmm11, %xmm9, %xmm9
-; AVX1-NEXT: vpaddb %xmm9, %xmm9, %xmm11
+; AVX1-NEXT: vpblendvb %xmm7, %xmm9, %xmm8, %xmm8
+; AVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm9
; AVX1-NEXT: vpaddb %xmm7, %xmm7, %xmm7
-; AVX1-NEXT: vpblendvb %xmm7, %xmm11, %xmm9, %xmm7
-; AVX1-NEXT: vpor %xmm7, %xmm8, %xmm7
-; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm8
-; AVX1-NEXT: vpand %xmm4, %xmm8, %xmm4
-; AVX1-NEXT: vpsllw $5, %xmm2, %xmm8
-; AVX1-NEXT: vpblendvb %xmm8, %xmm4, %xmm1, %xmm1
+; AVX1-NEXT: vpblendvb %xmm7, %xmm9, %xmm8, %xmm7
+; AVX1-NEXT: vpor %xmm6, %xmm7, %xmm6
+; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm7
+; AVX1-NEXT: vpand %xmm4, %xmm7, %xmm4
+; AVX1-NEXT: vpsllw $5, %xmm2, %xmm7
+; AVX1-NEXT: vpblendvb %xmm7, %xmm4, %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $2, %xmm1, %xmm4
-; AVX1-NEXT: vpand %xmm6, %xmm4, %xmm4
-; AVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm6
-; AVX1-NEXT: vpblendvb %xmm6, %xmm4, %xmm1, %xmm1
+; AVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
+; AVX1-NEXT: vpaddb %xmm7, %xmm7, %xmm5
+; AVX1-NEXT: vpblendvb %xmm5, %xmm4, %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $1, %xmm1, %xmm4
; AVX1-NEXT: vpand %xmm4, %xmm10, %xmm4
-; AVX1-NEXT: vpaddb %xmm6, %xmm6, %xmm6
-; AVX1-NEXT: vpblendvb %xmm6, %xmm4, %xmm1, %xmm1
+; AVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5
+; AVX1-NEXT: vpblendvb %xmm5, %xmm4, %xmm1, %xmm1
; AVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vpsllw $4, %xmm0, %xmm4
-; AVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
+; AVX1-NEXT: vpand %xmm4, %xmm11, %xmm4
; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpsllw $5, %xmm2, %xmm2
; AVX1-NEXT: vpblendvb %xmm2, %xmm4, %xmm0, %xmm0
@@ -572,7 +572,7 @@ define <32 x i8> @var_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %amt)
; AVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpblendvb %xmm2, %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vinsertf128 $1, %xmm7, %ymm0, %ymm0
+; AVX1-NEXT: vinsertf128 $1, %xmm6, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: var_funnnel_v32i8:
diff --git a/llvm/test/CodeGen/X86/vector-fshr-512.ll b/llvm/test/CodeGen/X86/vector-fshr-512.ll
index 4c6cd5feaf593..9b1ed296f6da2 100644
--- a/llvm/test/CodeGen/X86/vector-fshr-512.ll
+++ b/llvm/test/CodeGen/X86/vector-fshr-512.ll
@@ -254,24 +254,24 @@ define <64 x i8> @var_funnnel_v64i8(<64 x i8> %x, <64 x i8> %y, <64 x i8> %amt)
; AVX512F-NEXT: vpaddb %ymm7, %ymm7, %ymm7
; AVX512F-NEXT: vpblendvb %ymm7, %ymm6, %ymm1, %ymm1
; AVX512F-NEXT: vinserti64x4 $1, %ymm5, %zmm1, %zmm1
-; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm5 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm6
-; AVX512F-NEXT: vpaddb %ymm6, %ymm6, %ymm6
-; AVX512F-NEXT: vpsllw $4, %ymm6, %ymm7
-; AVX512F-NEXT: vpand %ymm5, %ymm7, %ymm7
+; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm5
+; AVX512F-NEXT: vpaddb %ymm5, %ymm5, %ymm5
+; AVX512F-NEXT: vpsllw $4, %ymm5, %ymm6
+; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm7 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
+; AVX512F-NEXT: vpand %ymm7, %ymm6, %ymm6
; AVX512F-NEXT: vpxor %ymm3, %ymm4, %ymm4
; AVX512F-NEXT: vpsllw $5, %ymm4, %ymm4
-; AVX512F-NEXT: vpblendvb %ymm4, %ymm7, %ymm6, %ymm6
-; AVX512F-NEXT: vpaddb %ymm6, %ymm6, %ymm7
-; AVX512F-NEXT: vpaddb %ymm7, %ymm7, %ymm7
+; AVX512F-NEXT: vpblendvb %ymm4, %ymm6, %ymm5, %ymm5
+; AVX512F-NEXT: vpaddb %ymm5, %ymm5, %ymm6
+; AVX512F-NEXT: vpaddb %ymm6, %ymm6, %ymm6
; AVX512F-NEXT: vpaddb %ymm4, %ymm4, %ymm4
-; AVX512F-NEXT: vpblendvb %ymm4, %ymm7, %ymm6, %ymm6
-; AVX512F-NEXT: vpaddb %ymm6, %ymm6, %ymm7
+; AVX512F-NEXT: vpblendvb %ymm4, %ymm6, %ymm5, %ymm5
+; AVX512F-NEXT: vpaddb %ymm5, %ymm5, %ymm6
; AVX512F-NEXT: vpaddb %ymm4, %ymm4, %ymm4
-; AVX512F-NEXT: vpblendvb %ymm4, %ymm7, %ymm6, %ymm4
+; AVX512F-NEXT: vpblendvb %ymm4, %ymm6, %ymm5, %ymm4
; AVX512F-NEXT: vpaddb %ymm0, %ymm0, %ymm0
-; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm6
-; AVX512F-NEXT: vpand %ymm5, %ymm6, %ymm5
+; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm5
+; AVX512F-NEXT: vpand %ymm7, %ymm5, %ymm5
; AVX512F-NEXT: vpxor %ymm3, %ymm2, %ymm2
; AVX512F-NEXT: vpsllw $5, %ymm2, %ymm2
; AVX512F-NEXT: vpblendvb %ymm2, %ymm5, %ymm0, %ymm0
@@ -320,24 +320,24 @@ define <64 x i8> @var_funnnel_v64i8(<64 x i8> %x, <64 x i8> %y, <64 x i8> %amt)
; AVX512VL-NEXT: vpaddb %ymm6, %ymm6, %ymm6
; AVX512VL-NEXT: vpblendvb %ymm6, %ymm5, %ymm1, %ymm1
; AVX512VL-NEXT: vinserti64x4 $1, %ymm4, %zmm1, %zmm1
-; AVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm5
-; AVX512VL-NEXT: vpaddb %ymm5, %ymm5, %ymm5
-; AVX512VL-NEXT: vpsllw $4, %ymm5, %ymm6
-; AVX512VL-NEXT: vpand %ymm4, %ymm6, %ymm6
+; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm4
+; AVX512VL-NEXT: vpaddb %ymm4, %ymm4, %ymm4
+; AVX512VL-NEXT: vpsllw $4, %ymm4, %ymm5
+; AVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm6 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
+; AVX512VL-NEXT: vpand %ymm6, %ymm5, %ymm5
; AVX512VL-NEXT: vpxor %ymm7, %ymm3, %ymm3
; AVX512VL-NEXT: vpsllw $5, %ymm3, %ymm3
-; AVX512VL-NEXT: vpblendvb %ymm3, %ymm6, %ymm5, %ymm5
-; AVX512VL-NEXT: vpaddb %ymm5, %ymm5, %ymm6
-; AVX512VL-NEXT: vpaddb %ymm6, %ymm6, %ymm6
+; AVX512VL-NEXT: vpblendvb %ymm3, %ymm5, %ymm4, %ymm4
+; AVX512VL-NEXT: vpaddb %ymm4, %ymm4, %ymm5
+; AVX512VL-NEXT: vpaddb %ymm5, %ymm5, %ymm5
; AVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3
-; AVX512VL-NEXT: vpblendvb %ymm3, %ymm6, %ymm5, %ymm5
-; AVX512VL-NEXT: vpaddb %ymm5, %ymm5, %ymm6
+; AVX512VL-NEXT: vpblendvb %ymm3, %ymm5, %ymm4, %ymm4
+; AVX512VL-NEXT: vpaddb %ymm4, %ymm4, %ymm5
; AVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3
-; AVX512VL-NEXT: vpblendvb %ymm3, %ymm6, %ymm5, %ymm3
+; AVX512VL-NEXT: vpblendvb %ymm3, %ymm5, %ymm4, %ymm3
; AVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm0
-; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm5
-; AVX512VL-NEXT: vpand %ymm4, %ymm5, %ymm4
+; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm4
+; AVX512VL-NEXT: vpand %ymm6, %ymm4, %ymm4
; AVX512VL-NEXT: vpxor %ymm7, %ymm2, %ymm2
; AVX512VL-NEXT: vpsllw $5, %ymm2, %ymm2
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining.ll
index 4e68a259a075b..c27095eaa51e7 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-combining.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-combining.ll
@@ -3629,8 +3629,8 @@ define void @SpinningCube() {
; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: movss {{.*#+}} xmm1 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,1]
-; SSE2-NEXT: movd {{.*#+}} xmm2 = [NaN,0.0E+0,0.0E+0,0.0E+0]
-; SSE2-NEXT: movq {{.*#+}} xmm2 = xmm2[0],zero
+; SSE2-NEXT: movss {{.*#+}} xmm2 = [NaN,0.0E+0,0.0E+0,0.0E+0]
+; SSE2-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,0]
; SSE2-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
@@ -3648,8 +3648,8 @@ define void @SpinningCube() {
; SSSE3-NEXT: xorps %xmm0, %xmm0
; SSSE3-NEXT: movss {{.*#+}} xmm1 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,1]
-; SSSE3-NEXT: movd {{.*#+}} xmm2 = [NaN,0.0E+0,0.0E+0,0.0E+0]
-; SSSE3-NEXT: movq {{.*#+}} xmm2 = xmm2[0],zero
+; SSSE3-NEXT: movss {{.*#+}} xmm2 = [NaN,0.0E+0,0.0E+0,0.0E+0]
+; SSSE3-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0]
; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,0]
; SSSE3-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
@@ -3663,11 +3663,12 @@ define void @SpinningCube() {
;
; SSE41-LABEL: SpinningCube:
; SSE41: # %bb.0: # %entry
-; SSE41-NEXT: insertps {{.*#+}} xmm0 = zero,zero,zero,mem[0]
-; SSE41-NEXT: movaps %xmm0, %xmm1
+; SSE41-NEXT: movl $1065353216, (%rax) # imm = 0x3F800000
+; SSE41-NEXT: movss {{.*#+}} xmm0 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]
+; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],zero,zero,xmm0[0]
; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3]
; SSE41-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
-; SSE41-NEXT: movl $1065353216, (%rax) # imm = 0x3F800000
+; SSE41-NEXT: insertps {{.*#+}} xmm0 = zero,zero,zero,xmm0[0]
; SSE41-NEXT: movaps %xmm1, (%rax)
; SSE41-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,2]
@@ -3680,7 +3681,8 @@ define void @SpinningCube() {
; AVX: # %bb.0: # %entry
; AVX-NEXT: movl $1065353216, (%rax) # imm = 0x3F800000
; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [0.0E+0,0.0E+0,0.0E+0,1.0E+0]
-; AVX-NEXT: vinsertps {{.*#+}} xmm1 = xmm0[0],mem[0],xmm0[2,3]
+; AVX-NEXT: vblendps {{.*#+}} xmm1 = xmm0[0,1,2,3]
+; AVX-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],zero,xmm1[3]
; AVX-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vmovaps %xmm1, (%rax)
; AVX-NEXT: vbroadcastss (%rax), %xmm1
diff --git a/llvm/test/CodeGen/X86/vector-trunc-packus.ll b/llvm/test/CodeGen/X86/vector-trunc-packus.ll
index 9481d9ae70471..394b36a423034 100644
--- a/llvm/test/CodeGen/X86/vector-trunc-packus.ll
+++ b/llvm/test/CodeGen/X86/vector-trunc-packus.ll
@@ -698,29 +698,29 @@ define <8 x i32> @trunc_packus_v8i64_v8i32(ptr %p0) "min-legal-vector-width"="25
;
; AVX1-LABEL: trunc_packus_v8i64_v8i32:
; AVX1: # %bb.0:
-; AVX1-NEXT: vmovdqa (%rdi), %xmm0
-; AVX1-NEXT: vmovdqa 16(%rdi), %xmm1
-; AVX1-NEXT: vmovdqa 32(%rdi), %xmm2
-; AVX1-NEXT: vmovdqa 48(%rdi), %xmm3
-; AVX1-NEXT: vpmovsxbd {{.*#+}} xmm4 = [4294967295,0,4294967295,0]
-; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm2, %xmm4, %xmm2
-; AVX1-NEXT: vpcmpgtq %xmm3, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm3, %xmm4, %xmm3
-; AVX1-NEXT: vpcmpgtq %xmm0, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm0, %xmm4, %xmm0
-; AVX1-NEXT: vpcmpgtq %xmm1, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm1, %xmm4, %xmm1
-; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm1, %xmm5
-; AVX1-NEXT: vpand %xmm1, %xmm5, %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm0, %xmm5
+; AVX1-NEXT: vmovdqa (%rdi), %ymm0
+; AVX1-NEXT: vmovdqa 32(%rdi), %ymm1
+; AVX1-NEXT: vpmovsxbd {{.*#+}} xmm2 = [4294967295,0,4294967295,0]
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm3
+; AVX1-NEXT: vblendvpd %xmm3, %xmm1, %xmm2, %xmm3
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm4
+; AVX1-NEXT: vblendvpd %xmm4, %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm4
+; AVX1-NEXT: vblendvpd %xmm4, %xmm0, %xmm2, %xmm4
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm5
+; AVX1-NEXT: vblendvpd %xmm5, %xmm0, %xmm2, %xmm0
+; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm5
; AVX1-NEXT: vpand %xmm0, %xmm5, %xmm0
-; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm3, %xmm1
-; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm2, %xmm3
-; AVX1-NEXT: vpand %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm5
+; AVX1-NEXT: vpand %xmm4, %xmm5, %xmm4
+; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm4[0,2],xmm0[0,2]
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm1, %xmm4
+; AVX1-NEXT: vpand %xmm1, %xmm4, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm2[0,2],xmm1[0,2]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
@@ -1688,31 +1688,32 @@ define <8 x i16> @trunc_packus_v8i64_v8i16(ptr %p0) "min-legal-vector-width"="25
;
; AVX1-LABEL: trunc_packus_v8i64_v8i16:
; AVX1: # %bb.0:
-; AVX1-NEXT: vmovdqa (%rdi), %xmm0
-; AVX1-NEXT: vmovdqa 16(%rdi), %xmm1
-; AVX1-NEXT: vmovdqa 32(%rdi), %xmm2
-; AVX1-NEXT: vmovdqa 48(%rdi), %xmm3
-; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm4 = [65535,65535]
-; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm2, %xmm4, %xmm2
-; AVX1-NEXT: vpcmpgtq %xmm3, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm3, %xmm4, %xmm3
-; AVX1-NEXT: vpcmpgtq %xmm0, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm0, %xmm4, %xmm0
-; AVX1-NEXT: vpcmpgtq %xmm1, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm1, %xmm4, %xmm1
-; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm1, %xmm5
-; AVX1-NEXT: vpand %xmm1, %xmm5, %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm0, %xmm5
+; AVX1-NEXT: vmovdqa (%rdi), %ymm0
+; AVX1-NEXT: vmovdqa 32(%rdi), %ymm1
+; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm2 = [65535,65535]
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm3
+; AVX1-NEXT: vblendvpd %xmm3, %xmm1, %xmm2, %xmm3
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm4
+; AVX1-NEXT: vblendvpd %xmm4, %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm4
+; AVX1-NEXT: vblendvpd %xmm4, %xmm0, %xmm2, %xmm4
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm5
+; AVX1-NEXT: vblendvpd %xmm5, %xmm0, %xmm2, %xmm0
+; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm5
; AVX1-NEXT: vpand %xmm0, %xmm5, %xmm0
-; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm3, %xmm1
-; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm2, %xmm3
-; AVX1-NEXT: vpand %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm5
+; AVX1-NEXT: vpand %xmm4, %xmm5, %xmm4
+; AVX1-NEXT: vpackusdw %xmm0, %xmm4, %xmm0
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm1, %xmm4
+; AVX1-NEXT: vpand %xmm1, %xmm4, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpackusdw %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: trunc_packus_v8i64_v8i16:
@@ -3123,32 +3124,33 @@ define <8 x i8> @trunc_packus_v8i64_v8i8(ptr %p0) "min-legal-vector-width"="256"
;
; AVX1-LABEL: trunc_packus_v8i64_v8i8:
; AVX1: # %bb.0:
-; AVX1-NEXT: vmovdqa (%rdi), %xmm0
-; AVX1-NEXT: vmovdqa 16(%rdi), %xmm1
-; AVX1-NEXT: vmovdqa 32(%rdi), %xmm2
-; AVX1-NEXT: vmovdqa 48(%rdi), %xmm3
-; AVX1-NEXT: vpmovzxbq {{.*#+}} xmm4 = [255,255]
-; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm2, %xmm4, %xmm2
-; AVX1-NEXT: vpcmpgtq %xmm3, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm3, %xmm4, %xmm3
-; AVX1-NEXT: vpcmpgtq %xmm0, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm0, %xmm4, %xmm0
-; AVX1-NEXT: vpcmpgtq %xmm1, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm1, %xmm4, %xmm1
-; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm1, %xmm5
-; AVX1-NEXT: vpand %xmm1, %xmm5, %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm0, %xmm5
+; AVX1-NEXT: vmovdqa (%rdi), %ymm0
+; AVX1-NEXT: vmovdqa 32(%rdi), %ymm1
+; AVX1-NEXT: vpmovzxbq {{.*#+}} xmm2 = [255,255]
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm3
+; AVX1-NEXT: vblendvpd %xmm3, %xmm1, %xmm2, %xmm3
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm4
+; AVX1-NEXT: vblendvpd %xmm4, %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm4
+; AVX1-NEXT: vblendvpd %xmm4, %xmm0, %xmm2, %xmm4
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm5
+; AVX1-NEXT: vblendvpd %xmm5, %xmm0, %xmm2, %xmm0
+; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm5
; AVX1-NEXT: vpand %xmm0, %xmm5, %xmm0
-; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm3, %xmm1
-; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm2, %xmm3
-; AVX1-NEXT: vpand %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm5
+; AVX1-NEXT: vpand %xmm4, %xmm5, %xmm4
+; AVX1-NEXT: vpackusdw %xmm0, %xmm4, %xmm0
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm1, %xmm4
+; AVX1-NEXT: vpand %xmm1, %xmm4, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpackusdw %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm0, %xmm0, %xmm0
+; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: trunc_packus_v8i64_v8i8:
@@ -3425,33 +3427,34 @@ define void @trunc_packus_v8i64_v8i8_store(ptr %p0, ptr%p1) "min-legal-vector-wi
;
; AVX1-LABEL: trunc_packus_v8i64_v8i8_store:
; AVX1: # %bb.0:
-; AVX1-NEXT: vmovdqa (%rdi), %xmm0
-; AVX1-NEXT: vmovdqa 16(%rdi), %xmm1
-; AVX1-NEXT: vmovdqa 32(%rdi), %xmm2
-; AVX1-NEXT: vmovdqa 48(%rdi), %xmm3
-; AVX1-NEXT: vpmovzxbq {{.*#+}} xmm4 = [255,255]
-; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm2, %xmm4, %xmm2
-; AVX1-NEXT: vpcmpgtq %xmm3, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm3, %xmm4, %xmm3
-; AVX1-NEXT: vpcmpgtq %xmm0, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm0, %xmm4, %xmm0
-; AVX1-NEXT: vpcmpgtq %xmm1, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm1, %xmm4, %xmm1
-; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm1, %xmm5
-; AVX1-NEXT: vpand %xmm1, %xmm5, %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm0, %xmm5
+; AVX1-NEXT: vmovdqa (%rdi), %ymm0
+; AVX1-NEXT: vmovdqa 32(%rdi), %ymm1
+; AVX1-NEXT: vpmovzxbq {{.*#+}} xmm2 = [255,255]
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm3
+; AVX1-NEXT: vblendvpd %xmm3, %xmm1, %xmm2, %xmm3
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm4
+; AVX1-NEXT: vblendvpd %xmm4, %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm4
+; AVX1-NEXT: vblendvpd %xmm4, %xmm0, %xmm2, %xmm4
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm5
+; AVX1-NEXT: vblendvpd %xmm5, %xmm0, %xmm2, %xmm0
+; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm5
; AVX1-NEXT: vpand %xmm0, %xmm5, %xmm0
-; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm3, %xmm1
-; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm2, %xmm3
-; AVX1-NEXT: vpand %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm5
+; AVX1-NEXT: vpand %xmm4, %xmm5, %xmm4
+; AVX1-NEXT: vpackusdw %xmm0, %xmm4, %xmm0
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm1, %xmm4
+; AVX1-NEXT: vpand %xmm1, %xmm4, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpackusdw %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vmovq %xmm0, (%rsi)
+; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: trunc_packus_v8i64_v8i8_store:
@@ -3936,55 +3939,56 @@ define <16 x i8> @trunc_packus_v16i64_v16i8(ptr %p0) "min-legal-vector-width"="2
;
; AVX1-LABEL: trunc_packus_v16i64_v16i8:
; AVX1: # %bb.0:
-; AVX1-NEXT: vmovdqa 96(%rdi), %xmm0
-; AVX1-NEXT: vpmovzxbq {{.*#+}} xmm2 = [255,255]
-; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm1
-; AVX1-NEXT: vblendvpd %xmm1, %xmm0, %xmm2, %xmm0
-; AVX1-NEXT: vmovdqa 112(%rdi), %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm3
-; AVX1-NEXT: vblendvpd %xmm3, %xmm1, %xmm2, %xmm1
-; AVX1-NEXT: vmovdqa 64(%rdi), %xmm3
-; AVX1-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm4
-; AVX1-NEXT: vblendvpd %xmm4, %xmm3, %xmm2, %xmm3
-; AVX1-NEXT: vmovdqa 80(%rdi), %xmm4
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm2, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm4, %xmm2, %xmm4
-; AVX1-NEXT: vmovdqa (%rdi), %xmm5
-; AVX1-NEXT: vmovdqa 16(%rdi), %xmm6
-; AVX1-NEXT: vmovdqa 32(%rdi), %xmm7
-; AVX1-NEXT: vmovdqa 48(%rdi), %xmm8
-; AVX1-NEXT: vpcmpgtq %xmm7, %xmm2, %xmm9
-; AVX1-NEXT: vblendvpd %xmm9, %xmm7, %xmm2, %xmm7
-; AVX1-NEXT: vpcmpgtq %xmm8, %xmm2, %xmm9
-; AVX1-NEXT: vblendvpd %xmm9, %xmm8, %xmm2, %xmm8
+; AVX1-NEXT: vmovdqa (%rdi), %ymm2
+; AVX1-NEXT: vmovdqa 32(%rdi), %ymm3
+; AVX1-NEXT: vmovdqa 64(%rdi), %ymm4
+; AVX1-NEXT: vmovdqa 96(%rdi), %ymm1
+; AVX1-NEXT: vpmovzxbq {{.*#+}} xmm5 = [255,255]
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm5, %xmm0
+; AVX1-NEXT: vblendvpd %xmm0, %xmm1, %xmm5, %xmm0
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm5, %xmm6
+; AVX1-NEXT: vblendvpd %xmm6, %xmm1, %xmm5, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm4, %xmm5, %xmm6
+; AVX1-NEXT: vblendvpd %xmm6, %xmm4, %xmm5, %xmm6
+; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm4
+; AVX1-NEXT: vpcmpgtq %xmm4, %xmm5, %xmm7
+; AVX1-NEXT: vblendvpd %xmm7, %xmm4, %xmm5, %xmm4
+; AVX1-NEXT: vpcmpgtq %xmm3, %xmm5, %xmm7
+; AVX1-NEXT: vblendvpd %xmm7, %xmm3, %xmm5, %xmm7
+; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm3
+; AVX1-NEXT: vpcmpgtq %xmm3, %xmm5, %xmm8
+; AVX1-NEXT: vblendvpd %xmm8, %xmm3, %xmm5, %xmm3
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm5, %xmm8
+; AVX1-NEXT: vblendvpd %xmm8, %xmm2, %xmm5, %xmm8
+; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm5, %xmm9
+; AVX1-NEXT: vblendvpd %xmm9, %xmm2, %xmm5, %xmm2
+; AVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5
; AVX1-NEXT: vpcmpgtq %xmm5, %xmm2, %xmm9
-; AVX1-NEXT: vblendvpd %xmm9, %xmm5, %xmm2, %xmm5
-; AVX1-NEXT: vpcmpgtq %xmm6, %xmm2, %xmm9
-; AVX1-NEXT: vblendvpd %xmm9, %xmm6, %xmm2, %xmm2
-; AVX1-NEXT: vpxor %xmm6, %xmm6, %xmm6
-; AVX1-NEXT: vpcmpgtq %xmm6, %xmm2, %xmm9
; AVX1-NEXT: vpand %xmm2, %xmm9, %xmm2
-; AVX1-NEXT: vpcmpgtq %xmm6, %xmm5, %xmm9
-; AVX1-NEXT: vpand %xmm5, %xmm9, %xmm5
-; AVX1-NEXT: vpackusdw %xmm2, %xmm5, %xmm2
-; AVX1-NEXT: vpcmpgtq %xmm6, %xmm8, %xmm5
-; AVX1-NEXT: vpand %xmm5, %xmm8, %xmm5
-; AVX1-NEXT: vpcmpgtq %xmm6, %xmm7, %xmm8
+; AVX1-NEXT: vpcmpgtq %xmm5, %xmm8, %xmm9
+; AVX1-NEXT: vpand %xmm8, %xmm9, %xmm8
+; AVX1-NEXT: vpackusdw %xmm2, %xmm8, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm5, %xmm3, %xmm8
+; AVX1-NEXT: vpand %xmm3, %xmm8, %xmm3
+; AVX1-NEXT: vpcmpgtq %xmm5, %xmm7, %xmm8
; AVX1-NEXT: vpand %xmm7, %xmm8, %xmm7
-; AVX1-NEXT: vpackusdw %xmm5, %xmm7, %xmm5
-; AVX1-NEXT: vpackusdw %xmm5, %xmm2, %xmm2
-; AVX1-NEXT: vpcmpgtq %xmm6, %xmm4, %xmm5
-; AVX1-NEXT: vpand %xmm4, %xmm5, %xmm4
-; AVX1-NEXT: vpcmpgtq %xmm6, %xmm3, %xmm5
-; AVX1-NEXT: vpand %xmm3, %xmm5, %xmm3
-; AVX1-NEXT: vpackusdw %xmm4, %xmm3, %xmm3
-; AVX1-NEXT: vpcmpgtq %xmm6, %xmm1, %xmm4
+; AVX1-NEXT: vpackusdw %xmm3, %xmm7, %xmm3
+; AVX1-NEXT: vpackusdw %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm5, %xmm4, %xmm3
+; AVX1-NEXT: vpand %xmm4, %xmm3, %xmm3
+; AVX1-NEXT: vpcmpgtq %xmm5, %xmm6, %xmm4
+; AVX1-NEXT: vpand %xmm6, %xmm4, %xmm4
+; AVX1-NEXT: vpackusdw %xmm3, %xmm4, %xmm3
+; AVX1-NEXT: vpcmpgtq %xmm5, %xmm1, %xmm4
; AVX1-NEXT: vpand %xmm1, %xmm4, %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm6, %xmm0, %xmm4
+; AVX1-NEXT: vpcmpgtq %xmm5, %xmm0, %xmm4
; AVX1-NEXT: vpand %xmm0, %xmm4, %xmm0
; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackusdw %xmm0, %xmm3, %xmm0
; AVX1-NEXT: vpackuswb %xmm0, %xmm2, %xmm0
+; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: trunc_packus_v16i64_v16i8:
diff --git a/llvm/test/CodeGen/X86/vshift-6.ll b/llvm/test/CodeGen/X86/vshift-6.ll
index 671de15488168..c3e49b87873ba 100644
--- a/llvm/test/CodeGen/X86/vshift-6.ll
+++ b/llvm/test/CodeGen/X86/vshift-6.ll
@@ -27,9 +27,10 @@
define <16 x i8> @do_not_crash(ptr, ptr, ptr, i32, i64, i8) {
; X86-LABEL: do_not_crash:
; X86: # %bb.0: # %entry
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movb %al, (%ecx)
+; X86-NEXT: movzbl %al, %eax
; X86-NEXT: movd %eax, %xmm1
; X86-NEXT: psllq $56, %xmm1
; X86-NEXT: pcmpeqd %xmm3, %xmm3
diff --git a/llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll b/llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll
index fde915247760a..4e07a02176da7 100644
--- a/llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll
+++ b/llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll
@@ -834,7 +834,6 @@ define void @load_8byte_chunk_of_16byte_alloca_with_zero_upper_half(ptr %src, i6
; X86-NO-BMI2-NO-SHLD-NEXT: pushl %esi
; X86-NO-BMI2-NO-SHLD-NEXT: subl $44, %esp
; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; X86-NO-BMI2-NO-SHLD-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
@@ -845,26 +844,27 @@ define void @load_8byte_chunk_of_16byte_alloca_with_zero_upper_half(ptr %src, i6
; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shrb $3, %cl
; X86-NO-BMI2-NO-SHLD-NEXT: andb $12, %cl
-; X86-NO-BMI2-NO-SHLD-NEXT: movzbl %cl, %ebx
-; X86-NO-BMI2-NO-SHLD-NEXT: movl (%esp,%ebx), %ebp
-; X86-NO-BMI2-NO-SHLD-NEXT: movl 4(%esp,%ebx), %esi
-; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
-; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %ebp
-; X86-NO-BMI2-NO-SHLD-NEXT: notb %cl
-; X86-NO-BMI2-NO-SHLD-NEXT: leal (%esi,%esi), %edi
-; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %edi
-; X86-NO-BMI2-NO-SHLD-NEXT: orl %ebp, %edi
+; X86-NO-BMI2-NO-SHLD-NEXT: movzbl %cl, %ebp
+; X86-NO-BMI2-NO-SHLD-NEXT: movl (%esp,%ebp), %esi
+; X86-NO-BMI2-NO-SHLD-NEXT: movl 4(%esp,%ebp), %edi
; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %esi
-; X86-NO-BMI2-NO-SHLD-NEXT: andb $24, %al
-; X86-NO-BMI2-NO-SHLD-NEXT: notb %al
-; X86-NO-BMI2-NO-SHLD-NEXT: movl 8(%esp,%ebx), %ebx
-; X86-NO-BMI2-NO-SHLD-NEXT: addl %ebx, %ebx
-; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %edx
+; X86-NO-BMI2-NO-SHLD-NEXT: notb %dl
+; X86-NO-BMI2-NO-SHLD-NEXT: leal (%edi,%edi), %ebx
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %edx, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %ebx
; X86-NO-BMI2-NO-SHLD-NEXT: orl %esi, %ebx
-; X86-NO-BMI2-NO-SHLD-NEXT: movl %ebx, 4(%edx)
-; X86-NO-BMI2-NO-SHLD-NEXT: movl %edi, (%edx)
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
+; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %edi
+; X86-NO-BMI2-NO-SHLD-NEXT: movl 8(%esp,%ebp), %eax
+; X86-NO-BMI2-NO-SHLD-NEXT: addl %eax, %eax
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %edx, %ecx
+; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %eax
+; X86-NO-BMI2-NO-SHLD-NEXT: orl %edi, %eax
+; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, 4(%ecx)
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %ebx, (%ecx)
; X86-NO-BMI2-NO-SHLD-NEXT: addl $44, %esp
; X86-NO-BMI2-NO-SHLD-NEXT: popl %esi
; X86-NO-BMI2-NO-SHLD-NEXT: popl %edi
@@ -923,25 +923,23 @@ define void @load_8byte_chunk_of_16byte_alloca_with_zero_upper_half(ptr %src, i6
; X86-HAVE-BMI2-NO-SHLD-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
; X86-HAVE-BMI2-NO-SHLD-NEXT: movdqa %xmm0, (%esp)
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ecx, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shrb $3, %dl
-; X86-HAVE-BMI2-NO-SHLD-NEXT: andb $12, %dl
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movzbl %dl, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ecx, (%esp,%edx), %esi
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ecx, %ebx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: notb %bl
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 4(%esp,%edx), %edi
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 8(%esp,%edx), %ebp
-; X86-HAVE-BMI2-NO-SHLD-NEXT: leal (%edi,%edi), %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %ebx, %edx, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %esi, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ecx, %edi, %esi
-; X86-HAVE-BMI2-NO-SHLD-NEXT: andb $24, %cl
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shrb $3, %bl
+; X86-HAVE-BMI2-NO-SHLD-NEXT: andb $12, %bl
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movzbl %bl, %esi
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %edx, (%esp,%esi), %edi
; X86-HAVE-BMI2-NO-SHLD-NEXT: notb %cl
-; X86-HAVE-BMI2-NO-SHLD-NEXT: addl %ebp, %ebp
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %ecx, %ebp, %ecx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %esi, %ecx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 4(%esp,%esi), %ebx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 8(%esp,%esi), %esi
+; X86-HAVE-BMI2-NO-SHLD-NEXT: leal (%ebx,%ebx), %ebp
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %ecx, %ebp, %ebp
+; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %edi, %ebp
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %edx, %ebx, %edx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: addl %esi, %esi
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %ecx, %esi, %ecx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %edx, %ecx
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ecx, 4(%eax)
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %edx, (%eax)
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ebp, (%eax)
; X86-HAVE-BMI2-NO-SHLD-NEXT: addl $44, %esp
; X86-HAVE-BMI2-NO-SHLD-NEXT: popl %esi
; X86-HAVE-BMI2-NO-SHLD-NEXT: popl %edi
@@ -1436,7 +1434,6 @@ define void @load_8byte_chunk_of_32byte_alloca_with_zero_upper_half(ptr %src, i6
; X86-NO-BMI2-NO-SHLD-NEXT: pushl %esi
; X86-NO-BMI2-NO-SHLD-NEXT: subl $76, %esp
; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: movups (%ecx), %xmm0
; X86-NO-BMI2-NO-SHLD-NEXT: xorps %xmm1, %xmm1
@@ -1447,26 +1444,27 @@ define void @load_8byte_chunk_of_32byte_alloca_with_zero_upper_half(ptr %src, i6
; X86-NO-BMI2-NO-SHLD-NEXT: movaps %xmm0, (%esp)
; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shrb $5, %cl
-; X86-NO-BMI2-NO-SHLD-NEXT: movzbl %cl, %ebx
-; X86-NO-BMI2-NO-SHLD-NEXT: movl (%esp,%ebx,4), %ebp
-; X86-NO-BMI2-NO-SHLD-NEXT: movl 4(%esp,%ebx,4), %esi
-; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
-; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %ebp
-; X86-NO-BMI2-NO-SHLD-NEXT: notb %cl
-; X86-NO-BMI2-NO-SHLD-NEXT: leal (%esi,%esi), %edi
-; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %edi
-; X86-NO-BMI2-NO-SHLD-NEXT: orl %ebp, %edi
+; X86-NO-BMI2-NO-SHLD-NEXT: movzbl %cl, %ebp
+; X86-NO-BMI2-NO-SHLD-NEXT: movl (%esp,%ebp,4), %esi
+; X86-NO-BMI2-NO-SHLD-NEXT: movl 4(%esp,%ebp,4), %edi
; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %esi
-; X86-NO-BMI2-NO-SHLD-NEXT: andb $24, %al
-; X86-NO-BMI2-NO-SHLD-NEXT: notb %al
-; X86-NO-BMI2-NO-SHLD-NEXT: movl 8(%esp,%ebx,4), %ebx
-; X86-NO-BMI2-NO-SHLD-NEXT: addl %ebx, %ebx
-; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %edx
+; X86-NO-BMI2-NO-SHLD-NEXT: notb %dl
+; X86-NO-BMI2-NO-SHLD-NEXT: leal (%edi,%edi), %ebx
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %edx, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %ebx
; X86-NO-BMI2-NO-SHLD-NEXT: orl %esi, %ebx
-; X86-NO-BMI2-NO-SHLD-NEXT: movl %ebx, 4(%edx)
-; X86-NO-BMI2-NO-SHLD-NEXT: movl %edi, (%edx)
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
+; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %edi
+; X86-NO-BMI2-NO-SHLD-NEXT: movl 8(%esp,%ebp,4), %eax
+; X86-NO-BMI2-NO-SHLD-NEXT: addl %eax, %eax
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %edx, %ecx
+; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %eax
+; X86-NO-BMI2-NO-SHLD-NEXT: orl %edi, %eax
+; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, 4(%ecx)
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %ebx, (%ecx)
; X86-NO-BMI2-NO-SHLD-NEXT: addl $76, %esp
; X86-NO-BMI2-NO-SHLD-NEXT: popl %esi
; X86-NO-BMI2-NO-SHLD-NEXT: popl %edi
@@ -1526,24 +1524,22 @@ define void @load_8byte_chunk_of_32byte_alloca_with_zero_upper_half(ptr %src, i6
; X86-HAVE-BMI2-NO-SHLD-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
; X86-HAVE-BMI2-NO-SHLD-NEXT: movaps %xmm0, (%esp)
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ecx, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shrb $5, %dl
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movzbl %dl, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ecx, (%esp,%edx,4), %esi
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ecx, %ebx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: notb %bl
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 4(%esp,%edx,4), %edi
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 8(%esp,%edx,4), %ebp
-; X86-HAVE-BMI2-NO-SHLD-NEXT: leal (%edi,%edi), %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %ebx, %edx, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %esi, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ecx, %edi, %esi
-; X86-HAVE-BMI2-NO-SHLD-NEXT: andb $24, %cl
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shrb $5, %bl
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movzbl %bl, %esi
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %edx, (%esp,%esi,4), %edi
; X86-HAVE-BMI2-NO-SHLD-NEXT: notb %cl
-; X86-HAVE-BMI2-NO-SHLD-NEXT: addl %ebp, %ebp
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %ecx, %ebp, %ecx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %esi, %ecx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 4(%esp,%esi,4), %ebx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 8(%esp,%esi,4), %esi
+; X86-HAVE-BMI2-NO-SHLD-NEXT: leal (%ebx,%ebx), %ebp
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %ecx, %ebp, %ebp
+; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %edi, %ebp
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %edx, %ebx, %edx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: addl %esi, %esi
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %ecx, %esi, %ecx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %edx, %ecx
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ecx, 4(%eax)
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %edx, (%eax)
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ebp, (%eax)
; X86-HAVE-BMI2-NO-SHLD-NEXT: addl $76, %esp
; X86-HAVE-BMI2-NO-SHLD-NEXT: popl %esi
; X86-HAVE-BMI2-NO-SHLD-NEXT: popl %edi
@@ -1699,39 +1695,40 @@ define void @load_16byte_chunk_of_32byte_alloca_with_zero_upper_half(ptr %src, i
; X86-NO-BMI2-NO-SHLD-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shrb $5, %cl
-; X86-NO-BMI2-NO-SHLD-NEXT: movzbl %cl, %edi
-; X86-NO-BMI2-NO-SHLD-NEXT: movl 16(%esp,%edi,4), %edx
-; X86-NO-BMI2-NO-SHLD-NEXT: movl 20(%esp,%edi,4), %ebp
+; X86-NO-BMI2-NO-SHLD-NEXT: movzbl %cl, %ebx
+; X86-NO-BMI2-NO-SHLD-NEXT: movl 16(%esp,%ebx,4), %esi
+; X86-NO-BMI2-NO-SHLD-NEXT: movl 20(%esp,%ebx,4), %ebp
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
-; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %edx
-; X86-NO-BMI2-NO-SHLD-NEXT: notb %cl
-; X86-NO-BMI2-NO-SHLD-NEXT: movb %cl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
-; X86-NO-BMI2-NO-SHLD-NEXT: leal (%ebp,%ebp), %esi
-; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %esi
-; X86-NO-BMI2-NO-SHLD-NEXT: orl %edx, %esi
-; X86-NO-BMI2-NO-SHLD-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %esi
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %edx
+; X86-NO-BMI2-NO-SHLD-NEXT: notb %dl
+; X86-NO-BMI2-NO-SHLD-NEXT: leal (%ebp,%ebp), %edi
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %edx, %ecx
+; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %edi
+; X86-NO-BMI2-NO-SHLD-NEXT: orl %esi, %edi
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %ebp
-; X86-NO-BMI2-NO-SHLD-NEXT: movb %al, %ch
-; X86-NO-BMI2-NO-SHLD-NEXT: andb $24, %ch
-; X86-NO-BMI2-NO-SHLD-NEXT: xorb $31, %ch
-; X86-NO-BMI2-NO-SHLD-NEXT: movl 24(%esp,%edi,4), %edx
-; X86-NO-BMI2-NO-SHLD-NEXT: leal (%edx,%edx), %ebx
-; X86-NO-BMI2-NO-SHLD-NEXT: movb %ch, %cl
+; X86-NO-BMI2-NO-SHLD-NEXT: movl 24(%esp,%ebx,4), %edi
+; X86-NO-BMI2-NO-SHLD-NEXT: leal (%edi,%edi), %ebx
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %edx, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %ebx
; X86-NO-BMI2-NO-SHLD-NEXT: orl %ebp, %ebx
-; X86-NO-BMI2-NO-SHLD-NEXT: movb %al, %cl
-; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %edx
-; X86-NO-BMI2-NO-SHLD-NEXT: movl 28(%esp,%edi,4), %esi
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
+; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %edi
+; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NO-BMI2-NO-SHLD-NEXT: movl 28(%esp,%ecx,4), %esi
; X86-NO-BMI2-NO-SHLD-NEXT: leal (%esi,%esi), %ebp
-; X86-NO-BMI2-NO-SHLD-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %cl # 1-byte Reload
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %edx, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %ebp
-; X86-NO-BMI2-NO-SHLD-NEXT: orl %edx, %ebp
-; X86-NO-BMI2-NO-SHLD-NEXT: movb %al, %cl
+; X86-NO-BMI2-NO-SHLD-NEXT: orl %edi, %ebp
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %esi
-; X86-NO-BMI2-NO-SHLD-NEXT: movl 32(%esp,%edi,4), %eax
+; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NO-BMI2-NO-SHLD-NEXT: movl 32(%esp,%eax,4), %eax
; X86-NO-BMI2-NO-SHLD-NEXT: addl %eax, %eax
-; X86-NO-BMI2-NO-SHLD-NEXT: movb %ch, %cl
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %edx, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %eax
; X86-NO-BMI2-NO-SHLD-NEXT: orl %esi, %eax
; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[0-9]+}}(%esp), %ecx
@@ -1810,40 +1807,33 @@ define void @load_16byte_chunk_of_32byte_alloca_with_zero_upper_half(ptr %src, i
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %eax, %edx
; X86-HAVE-BMI2-NO-SHLD-NEXT: shrb $5, %dl
; X86-HAVE-BMI2-NO-SHLD-NEXT: movzbl %dl, %esi
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ecx, 16(%esp,%esi,4), %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ecx, %ebp
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %eax, %ebx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: notb %bl
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 20(%esp,%esi,4), %edi
-; X86-HAVE-BMI2-NO-SHLD-NEXT: leal (%edi,%edi), %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %ebx, %edx, %ecx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 24(%esp,%esi,4), %ecx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ebp, %edi, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: andb $24, %al
-; X86-HAVE-BMI2-NO-SHLD-NEXT: xorb $31, %al
-; X86-HAVE-BMI2-NO-SHLD-NEXT: leal (%ecx,%ecx), %edi
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ecx, 16(%esp,%esi,4), %edi
+; X86-HAVE-BMI2-NO-SHLD-NEXT: notb %al
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 20(%esp,%esi,4), %ebx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 24(%esp,%esi,4), %ebp
+; X86-HAVE-BMI2-NO-SHLD-NEXT: leal (%ebx,%ebx), %edx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %eax, %edx, %edx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %edi, %edx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ecx, %ebx, %ebx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: leal (%ebp,%ebp), %edi
; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %eax, %edi, %edi
-; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %edx, %edi
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 28(%esp,%esi,4), %ecx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: leal (%ecx,%ecx), %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %ebx, %edx, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ebp, {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload
-; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %ebx, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ebp, %ecx, %ecx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %ebx, %edi
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ecx, %ebp, %ebx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 28(%esp,%esi,4), %ebp
+; X86-HAVE-BMI2-NO-SHLD-NEXT: leal (%ebp,%ebp), %ebx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %eax, %ebx, %ebx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ecx, %ebp, %ecx
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 32(%esp,%esi,4), %esi
; X86-HAVE-BMI2-NO-SHLD-NEXT: addl %esi, %esi
; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %eax, %esi, %eax
; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %ecx, %eax
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %eax, 12(%ecx)
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %edx, 8(%ecx)
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ebx, 8(%ecx)
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %edi, 4(%ecx)
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %eax, (%ecx)
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %edx, (%ecx)
; X86-HAVE-BMI2-NO-SHLD-NEXT: addl $92, %esp
; X86-HAVE-BMI2-NO-SHLD-NEXT: popl %esi
; X86-HAVE-BMI2-NO-SHLD-NEXT: popl %edi
diff --git a/llvm/test/CodeGen/X86/widen-load-of-small-alloca.ll b/llvm/test/CodeGen/X86/widen-load-of-small-alloca.ll
index bed8e5806380c..144836af33511 100644
--- a/llvm/test/CodeGen/X86/widen-load-of-small-alloca.ll
+++ b/llvm/test/CodeGen/X86/widen-load-of-small-alloca.ll
@@ -1066,7 +1066,6 @@ define void @load_8byte_chunk_of_16byte_alloca(ptr %src, i64 %byteOff, ptr %dst)
; X86-NO-BMI2-NO-SHLD-NEXT: pushl %esi
; X86-NO-BMI2-NO-SHLD-NEXT: subl $44, %esp
; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: movups (%ecx), %xmm0
; X86-NO-BMI2-NO-SHLD-NEXT: shll $3, %eax
@@ -1076,26 +1075,27 @@ define void @load_8byte_chunk_of_16byte_alloca(ptr %src, i64 %byteOff, ptr %dst)
; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shrb $3, %cl
; X86-NO-BMI2-NO-SHLD-NEXT: andb $12, %cl
-; X86-NO-BMI2-NO-SHLD-NEXT: movzbl %cl, %ebx
-; X86-NO-BMI2-NO-SHLD-NEXT: movl (%esp,%ebx), %ebp
-; X86-NO-BMI2-NO-SHLD-NEXT: movl 4(%esp,%ebx), %esi
-; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
-; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %ebp
-; X86-NO-BMI2-NO-SHLD-NEXT: notb %cl
-; X86-NO-BMI2-NO-SHLD-NEXT: leal (%esi,%esi), %edi
-; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %edi
-; X86-NO-BMI2-NO-SHLD-NEXT: orl %ebp, %edi
+; X86-NO-BMI2-NO-SHLD-NEXT: movzbl %cl, %ebp
+; X86-NO-BMI2-NO-SHLD-NEXT: movl (%esp,%ebp), %esi
+; X86-NO-BMI2-NO-SHLD-NEXT: movl 4(%esp,%ebp), %edi
; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %esi
-; X86-NO-BMI2-NO-SHLD-NEXT: andb $24, %al
-; X86-NO-BMI2-NO-SHLD-NEXT: notb %al
-; X86-NO-BMI2-NO-SHLD-NEXT: movl 8(%esp,%ebx), %ebx
-; X86-NO-BMI2-NO-SHLD-NEXT: addl %ebx, %ebx
-; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %edx
+; X86-NO-BMI2-NO-SHLD-NEXT: notb %dl
+; X86-NO-BMI2-NO-SHLD-NEXT: leal (%edi,%edi), %ebx
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %edx, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %ebx
; X86-NO-BMI2-NO-SHLD-NEXT: orl %esi, %ebx
-; X86-NO-BMI2-NO-SHLD-NEXT: movl %ebx, 4(%edx)
-; X86-NO-BMI2-NO-SHLD-NEXT: movl %edi, (%edx)
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
+; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %edi
+; X86-NO-BMI2-NO-SHLD-NEXT: movl 8(%esp,%ebp), %eax
+; X86-NO-BMI2-NO-SHLD-NEXT: addl %eax, %eax
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %edx, %ecx
+; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %eax
+; X86-NO-BMI2-NO-SHLD-NEXT: orl %edi, %eax
+; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, 4(%ecx)
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %ebx, (%ecx)
; X86-NO-BMI2-NO-SHLD-NEXT: addl $44, %esp
; X86-NO-BMI2-NO-SHLD-NEXT: popl %esi
; X86-NO-BMI2-NO-SHLD-NEXT: popl %edi
@@ -1152,25 +1152,23 @@ define void @load_8byte_chunk_of_16byte_alloca(ptr %src, i64 %byteOff, ptr %dst)
; X86-HAVE-BMI2-NO-SHLD-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
; X86-HAVE-BMI2-NO-SHLD-NEXT: movaps %xmm0, (%esp)
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ecx, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shrb $3, %dl
-; X86-HAVE-BMI2-NO-SHLD-NEXT: andb $12, %dl
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movzbl %dl, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ecx, (%esp,%edx), %esi
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ecx, %ebx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: notb %bl
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 4(%esp,%edx), %edi
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 8(%esp,%edx), %ebp
-; X86-HAVE-BMI2-NO-SHLD-NEXT: leal (%edi,%edi), %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %ebx, %edx, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %esi, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ecx, %edi, %esi
-; X86-HAVE-BMI2-NO-SHLD-NEXT: andb $24, %cl
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shrb $3, %bl
+; X86-HAVE-BMI2-NO-SHLD-NEXT: andb $12, %bl
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movzbl %bl, %esi
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %edx, (%esp,%esi), %edi
; X86-HAVE-BMI2-NO-SHLD-NEXT: notb %cl
-; X86-HAVE-BMI2-NO-SHLD-NEXT: addl %ebp, %ebp
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %ecx, %ebp, %ecx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %esi, %ecx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 4(%esp,%esi), %ebx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 8(%esp,%esi), %esi
+; X86-HAVE-BMI2-NO-SHLD-NEXT: leal (%ebx,%ebx), %ebp
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %ecx, %ebp, %ebp
+; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %edi, %ebp
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %edx, %ebx, %edx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: addl %esi, %esi
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %ecx, %esi, %ecx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %edx, %ecx
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ecx, 4(%eax)
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %edx, (%eax)
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ebp, (%eax)
; X86-HAVE-BMI2-NO-SHLD-NEXT: addl $44, %esp
; X86-HAVE-BMI2-NO-SHLD-NEXT: popl %esi
; X86-HAVE-BMI2-NO-SHLD-NEXT: popl %edi
@@ -1676,7 +1674,6 @@ define void @load_8byte_chunk_of_32byte_alloca(ptr %src, i64 %byteOff, ptr %dst)
; X86-NO-BMI2-NO-SHLD-NEXT: pushl %esi
; X86-NO-BMI2-NO-SHLD-NEXT: subl $76, %esp
; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: movups (%ecx), %xmm0
; X86-NO-BMI2-NO-SHLD-NEXT: movups 16(%ecx), %xmm1
@@ -1688,26 +1685,27 @@ define void @load_8byte_chunk_of_32byte_alloca(ptr %src, i64 %byteOff, ptr %dst)
; X86-NO-BMI2-NO-SHLD-NEXT: movaps %xmm0, (%esp)
; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shrb $5, %cl
-; X86-NO-BMI2-NO-SHLD-NEXT: movzbl %cl, %ebx
-; X86-NO-BMI2-NO-SHLD-NEXT: movl (%esp,%ebx,4), %ebp
-; X86-NO-BMI2-NO-SHLD-NEXT: movl 4(%esp,%ebx,4), %esi
-; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
-; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %ebp
-; X86-NO-BMI2-NO-SHLD-NEXT: notb %cl
-; X86-NO-BMI2-NO-SHLD-NEXT: leal (%esi,%esi), %edi
-; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %edi
-; X86-NO-BMI2-NO-SHLD-NEXT: orl %ebp, %edi
+; X86-NO-BMI2-NO-SHLD-NEXT: movzbl %cl, %ebp
+; X86-NO-BMI2-NO-SHLD-NEXT: movl (%esp,%ebp,4), %esi
+; X86-NO-BMI2-NO-SHLD-NEXT: movl 4(%esp,%ebp,4), %edi
; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %esi
-; X86-NO-BMI2-NO-SHLD-NEXT: andb $24, %al
-; X86-NO-BMI2-NO-SHLD-NEXT: notb %al
-; X86-NO-BMI2-NO-SHLD-NEXT: movl 8(%esp,%ebx,4), %ebx
-; X86-NO-BMI2-NO-SHLD-NEXT: addl %ebx, %ebx
-; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %edx
+; X86-NO-BMI2-NO-SHLD-NEXT: notb %dl
+; X86-NO-BMI2-NO-SHLD-NEXT: leal (%edi,%edi), %ebx
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %edx, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %ebx
; X86-NO-BMI2-NO-SHLD-NEXT: orl %esi, %ebx
-; X86-NO-BMI2-NO-SHLD-NEXT: movl %ebx, 4(%edx)
-; X86-NO-BMI2-NO-SHLD-NEXT: movl %edi, (%edx)
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
+; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %edi
+; X86-NO-BMI2-NO-SHLD-NEXT: movl 8(%esp,%ebp,4), %eax
+; X86-NO-BMI2-NO-SHLD-NEXT: addl %eax, %eax
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %edx, %ecx
+; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %eax
+; X86-NO-BMI2-NO-SHLD-NEXT: orl %edi, %eax
+; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, 4(%ecx)
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %ebx, (%ecx)
; X86-NO-BMI2-NO-SHLD-NEXT: addl $76, %esp
; X86-NO-BMI2-NO-SHLD-NEXT: popl %esi
; X86-NO-BMI2-NO-SHLD-NEXT: popl %edi
@@ -1769,24 +1767,22 @@ define void @load_8byte_chunk_of_32byte_alloca(ptr %src, i64 %byteOff, ptr %dst)
; X86-HAVE-BMI2-NO-SHLD-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
; X86-HAVE-BMI2-NO-SHLD-NEXT: movaps %xmm0, (%esp)
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ecx, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shrb $5, %dl
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movzbl %dl, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ecx, (%esp,%edx,4), %esi
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ecx, %ebx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: notb %bl
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 4(%esp,%edx,4), %edi
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 8(%esp,%edx,4), %ebp
-; X86-HAVE-BMI2-NO-SHLD-NEXT: leal (%edi,%edi), %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %ebx, %edx, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %esi, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ecx, %edi, %esi
-; X86-HAVE-BMI2-NO-SHLD-NEXT: andb $24, %cl
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shrb $5, %bl
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movzbl %bl, %esi
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %edx, (%esp,%esi,4), %edi
; X86-HAVE-BMI2-NO-SHLD-NEXT: notb %cl
-; X86-HAVE-BMI2-NO-SHLD-NEXT: addl %ebp, %ebp
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %ecx, %ebp, %ecx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %esi, %ecx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 4(%esp,%esi,4), %ebx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 8(%esp,%esi,4), %esi
+; X86-HAVE-BMI2-NO-SHLD-NEXT: leal (%ebx,%ebx), %ebp
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %ecx, %ebp, %ebp
+; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %edi, %ebp
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %edx, %ebx, %edx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: addl %esi, %esi
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %ecx, %esi, %ecx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %edx, %ecx
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ecx, 4(%eax)
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %edx, (%eax)
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ebp, (%eax)
; X86-HAVE-BMI2-NO-SHLD-NEXT: addl $76, %esp
; X86-HAVE-BMI2-NO-SHLD-NEXT: popl %esi
; X86-HAVE-BMI2-NO-SHLD-NEXT: popl %edi
@@ -1945,39 +1941,40 @@ define void @load_16byte_chunk_of_32byte_alloca(ptr %src, i64 %byteOff, ptr %dst
; X86-NO-BMI2-NO-SHLD-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shrb $5, %cl
-; X86-NO-BMI2-NO-SHLD-NEXT: movzbl %cl, %edi
-; X86-NO-BMI2-NO-SHLD-NEXT: movl 16(%esp,%edi,4), %edx
-; X86-NO-BMI2-NO-SHLD-NEXT: movl 20(%esp,%edi,4), %ebp
+; X86-NO-BMI2-NO-SHLD-NEXT: movzbl %cl, %ebx
+; X86-NO-BMI2-NO-SHLD-NEXT: movl 16(%esp,%ebx,4), %esi
+; X86-NO-BMI2-NO-SHLD-NEXT: movl 20(%esp,%ebx,4), %ebp
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
-; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %edx
-; X86-NO-BMI2-NO-SHLD-NEXT: notb %cl
-; X86-NO-BMI2-NO-SHLD-NEXT: movb %cl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
-; X86-NO-BMI2-NO-SHLD-NEXT: leal (%ebp,%ebp), %esi
-; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %esi
-; X86-NO-BMI2-NO-SHLD-NEXT: orl %edx, %esi
-; X86-NO-BMI2-NO-SHLD-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %esi
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %edx
+; X86-NO-BMI2-NO-SHLD-NEXT: notb %dl
+; X86-NO-BMI2-NO-SHLD-NEXT: leal (%ebp,%ebp), %edi
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %edx, %ecx
+; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %edi
+; X86-NO-BMI2-NO-SHLD-NEXT: orl %esi, %edi
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %ebp
-; X86-NO-BMI2-NO-SHLD-NEXT: movb %al, %ch
-; X86-NO-BMI2-NO-SHLD-NEXT: andb $24, %ch
-; X86-NO-BMI2-NO-SHLD-NEXT: xorb $31, %ch
-; X86-NO-BMI2-NO-SHLD-NEXT: movl 24(%esp,%edi,4), %edx
-; X86-NO-BMI2-NO-SHLD-NEXT: leal (%edx,%edx), %ebx
-; X86-NO-BMI2-NO-SHLD-NEXT: movb %ch, %cl
+; X86-NO-BMI2-NO-SHLD-NEXT: movl 24(%esp,%ebx,4), %edi
+; X86-NO-BMI2-NO-SHLD-NEXT: leal (%edi,%edi), %ebx
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %edx, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %ebx
; X86-NO-BMI2-NO-SHLD-NEXT: orl %ebp, %ebx
-; X86-NO-BMI2-NO-SHLD-NEXT: movb %al, %cl
-; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %edx
-; X86-NO-BMI2-NO-SHLD-NEXT: movl 28(%esp,%edi,4), %esi
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
+; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %edi
+; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NO-BMI2-NO-SHLD-NEXT: movl 28(%esp,%ecx,4), %esi
; X86-NO-BMI2-NO-SHLD-NEXT: leal (%esi,%esi), %ebp
-; X86-NO-BMI2-NO-SHLD-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %cl # 1-byte Reload
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %edx, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %ebp
-; X86-NO-BMI2-NO-SHLD-NEXT: orl %edx, %ebp
-; X86-NO-BMI2-NO-SHLD-NEXT: movb %al, %cl
+; X86-NO-BMI2-NO-SHLD-NEXT: orl %edi, %ebp
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %eax, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shrl %cl, %esi
-; X86-NO-BMI2-NO-SHLD-NEXT: movl 32(%esp,%edi,4), %eax
+; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NO-BMI2-NO-SHLD-NEXT: movl 32(%esp,%eax,4), %eax
; X86-NO-BMI2-NO-SHLD-NEXT: addl %eax, %eax
-; X86-NO-BMI2-NO-SHLD-NEXT: movb %ch, %cl
+; X86-NO-BMI2-NO-SHLD-NEXT: movl %edx, %ecx
; X86-NO-BMI2-NO-SHLD-NEXT: shll %cl, %eax
; X86-NO-BMI2-NO-SHLD-NEXT: orl %esi, %eax
; X86-NO-BMI2-NO-SHLD-NEXT: movl {{[0-9]+}}(%esp), %ecx
@@ -2058,40 +2055,33 @@ define void @load_16byte_chunk_of_32byte_alloca(ptr %src, i64 %byteOff, ptr %dst
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %eax, %edx
; X86-HAVE-BMI2-NO-SHLD-NEXT: shrb $5, %dl
; X86-HAVE-BMI2-NO-SHLD-NEXT: movzbl %dl, %esi
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ecx, 16(%esp,%esi,4), %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ecx, %ebp
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %eax, %ebx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: notb %bl
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 20(%esp,%esi,4), %edi
-; X86-HAVE-BMI2-NO-SHLD-NEXT: leal (%edi,%edi), %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %ebx, %edx, %ecx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 24(%esp,%esi,4), %ecx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ebp, %edi, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: andb $24, %al
-; X86-HAVE-BMI2-NO-SHLD-NEXT: xorb $31, %al
-; X86-HAVE-BMI2-NO-SHLD-NEXT: leal (%ecx,%ecx), %edi
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ecx, 16(%esp,%esi,4), %edi
+; X86-HAVE-BMI2-NO-SHLD-NEXT: notb %al
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 20(%esp,%esi,4), %ebx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 24(%esp,%esi,4), %ebp
+; X86-HAVE-BMI2-NO-SHLD-NEXT: leal (%ebx,%ebx), %edx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %eax, %edx, %edx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %edi, %edx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ecx, %ebx, %ebx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: leal (%ebp,%ebp), %edi
; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %eax, %edi, %edi
-; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %edx, %edi
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 28(%esp,%esi,4), %ecx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: leal (%ecx,%ecx), %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %ebx, %edx, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ebp, {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload
-; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %ebx, %edx
-; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ebp, %ecx, %ecx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %ebx, %edi
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ecx, %ebp, %ebx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 28(%esp,%esi,4), %ebp
+; X86-HAVE-BMI2-NO-SHLD-NEXT: leal (%ebp,%ebp), %ebx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %eax, %ebx, %ebx
+; X86-HAVE-BMI2-NO-SHLD-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload
+; X86-HAVE-BMI2-NO-SHLD-NEXT: shrxl %ecx, %ebp, %ecx
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl 32(%esp,%esi,4), %esi
; X86-HAVE-BMI2-NO-SHLD-NEXT: addl %esi, %esi
; X86-HAVE-BMI2-NO-SHLD-NEXT: shlxl %eax, %esi, %eax
; X86-HAVE-BMI2-NO-SHLD-NEXT: orl %ecx, %eax
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %eax, 12(%ecx)
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %edx, 8(%ecx)
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %ebx, 8(%ecx)
; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %edi, 4(%ecx)
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %eax, (%ecx)
+; X86-HAVE-BMI2-NO-SHLD-NEXT: movl %edx, (%ecx)
; X86-HAVE-BMI2-NO-SHLD-NEXT: addl $92, %esp
; X86-HAVE-BMI2-NO-SHLD-NEXT: popl %esi
; X86-HAVE-BMI2-NO-SHLD-NEXT: popl %edi
diff --git a/llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll b/llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
index f905fac15bffb..87a5d2fc3e285 100644
--- a/llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
+++ b/llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
@@ -3273,19 +3273,19 @@ define void @vec384_i8_widen_to_i128_factor16_broadcast_to_v3i128_factor3(ptr %i
;
; AVX1-LABEL: vec384_i8_widen_to_i128_factor16_broadcast_to_v3i128_factor3:
; AVX1: # %bb.0:
-; AVX1-NEXT: vmovdqa (%rdi), %xmm0
-; AVX1-NEXT: vmovdqa 48(%rdi), %xmm1
-; AVX1-NEXT: vpaddb 48(%rsi), %xmm1, %xmm1
-; AVX1-NEXT: vpaddb (%rsi), %xmm0, %xmm0
+; AVX1-NEXT: vmovdqa (%rsi), %xmm0
+; AVX1-NEXT: vmovdqa 48(%rsi), %xmm1
+; AVX1-NEXT: vpaddb 48(%rdi), %xmm1, %xmm1
+; AVX1-NEXT: vpaddb (%rdi), %xmm0, %xmm0
; AVX1-NEXT: vpmovsxwq {{.*#+}} xmm2 = [18446744073709551360,18446744073709551615]
; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm1
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpaddb (%rdx), %xmm1, %xmm1
; AVX1-NEXT: vpaddb 32(%rdx), %xmm0, %xmm2
; AVX1-NEXT: vpaddb 16(%rdx), %xmm0, %xmm0
+; AVX1-NEXT: vmovdqa %xmm1, (%rcx)
; AVX1-NEXT: vmovdqa %xmm0, 16(%rcx)
; AVX1-NEXT: vmovdqa %xmm2, 32(%rcx)
-; AVX1-NEXT: vmovdqa %xmm1, (%rcx)
; AVX1-NEXT: retq
;
; AVX2-LABEL: vec384_i8_widen_to_i128_factor16_broadcast_to_v3i128_factor3:
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