[llvm] [GlobalISel] Avoid repeated target info queries in combiners (PR #196530)
Cullen Rhodes via llvm-commits
llvm-commits at lists.llvm.org
Fri May 8 06:14:39 PDT 2026
https://github.com/c-rhodes created https://github.com/llvm/llvm-project/pull/196530
tryCombineAllImpl queries target info for every instruction. Cache
TargetInstrInfo/TargetRegisterInfo/RegisterBankInfo in CombinerHelper and pass
to executeMatchTable instead.
This avoids repeated virtual calls on the combiner executeMatchTable path.
CTMark -0.08% geomean improvement on aarch64-O0-g.
https://llvm-compile-time-tracker.com/compare.php?from=71fef6d5a306d1adf8bf7d30d2fe9e286380fecf&to=13bc49510657450402c066098e3a4b7d1af9d0e6&stat=instructions%3Au
Assisted-by: codex
>From 13bc49510657450402c066098e3a4b7d1af9d0e6 Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Fri, 8 May 2026 12:17:40 +0000
Subject: [PATCH] [GlobalISel] Avoid repeated target info queries in combiners
---
llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h | 8 ++++++++
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp | 1 +
.../TableGen/GlobalISelCombinerEmitter/match-table.td | 3 +--
llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp | 5 ++---
4 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
index 97f29015c6911..6fa435270334a 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
@@ -44,6 +44,7 @@ class LegalizerInfo;
struct LegalityQuery;
class RegisterBank;
class RegisterBankInfo;
+class TargetInstrInfo;
class TargetLowering;
class TargetRegisterInfo;
@@ -120,6 +121,7 @@ class CombinerHelper {
MachineDominatorTree *MDT;
bool IsPreLegalize;
const LegalizerInfo *LI;
+ const TargetInstrInfo *TII;
const RegisterBankInfo *RBI;
const TargetRegisterInfo *TRI;
@@ -135,6 +137,12 @@ class CombinerHelper {
return Builder;
}
+ const TargetInstrInfo &getTII() const { return *TII; }
+
+ const TargetRegisterInfo &getTRI() const { return *TRI; }
+
+ const RegisterBankInfo &getRBI() const { return *RBI; }
+
const TargetLowering &getTargetLowering() const;
const MachineFunction &getMachineFunction() const;
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index c58fb84a3890e..8f2ef1d5efa94 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -62,6 +62,7 @@ CombinerHelper::CombinerHelper(GISelChangeObserver &Observer,
const LegalizerInfo *LI)
: Builder(B), MRI(Builder.getMF().getRegInfo()), Observer(Observer), VT(VT),
MDT(MDT), IsPreLegalize(IsPreLegalize), LI(LI),
+ TII(Builder.getMF().getSubtarget().getInstrInfo()),
RBI(Builder.getMF().getSubtarget().getRegBankInfo()),
TRI(Builder.getMF().getSubtarget().getRegisterInfo()) {
(void)this->VT;
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
index 8907cfe811abd..daeb17a61959c 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
@@ -84,12 +84,11 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// Verify we reset MatchData on each tryCombineAll
// CHECK: bool GenMyCombiner::tryCombineAll(MachineInstr &I) const {
-// CHECK-NEXT: const TargetSubtargetInfo &ST = MF.getSubtarget();
// CHECK-NEXT: const PredicateBitset AvailableFeatures = getAvailableFeatures();
// CHECK-NEXT: B.setInstrAndDebugLoc(I);
// CHECK-NEXT: State.MIs.clear();
// CHECK-NEXT: State.MIs.push_back(&I);
-// CHECK-NEXT: if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), *ST.getInstrInfo(), MRI, *MRI.getTargetRegisterInfo(), *ST.getRegBankInfo(), AvailableFeatures, /*CoverageInfo*/ nullptr))
+// CHECK-NEXT: if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), Helper.getTII(), MRI, Helper.getTRI(), Helper.getRBI(), AvailableFeatures, /*CoverageInfo*/ nullptr))
// CHECK-NEXT: return true;
// CHECK-NEXT: }
// CHECK-EMPTY:
diff --git a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
index 56b39fcd1cc9e..5f13fb6303a35 100644
--- a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
@@ -2560,15 +2560,14 @@ void GICombinerEmitter::emitRuleConfigImpl(raw_ostream &OS) {
void GICombinerEmitter::emitAdditionalImpl(raw_ostream &OS) {
OS << "bool " << getClassName() << "::" << getCombineAllMethodName()
<< "(MachineInstr &I) const {\n"
- << " const TargetSubtargetInfo &ST = MF.getSubtarget();\n"
<< " const PredicateBitset AvailableFeatures = "
"getAvailableFeatures();\n"
<< " B.setInstrAndDebugLoc(I);\n"
<< " State.MIs.clear();\n"
<< " State.MIs.push_back(&I);\n"
<< " if (executeMatchTable(*this, State, ExecInfo, B"
- << ", getMatchTable(), *ST.getInstrInfo(), MRI, "
- "*MRI.getTargetRegisterInfo(), *ST.getRegBankInfo(), AvailableFeatures"
+ << ", getMatchTable(), Helper.getTII(), MRI, Helper.getTRI(), "
+ "Helper.getRBI(), AvailableFeatures"
<< ", /*CoverageInfo*/ nullptr)) {\n"
<< " return true;\n"
<< " }\n\n"
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