[llvm] [AMDGPU] Add subtarget features for MTBUF and formatted MUBUF instructions. (PR #196315)
Mariusz Sikora via llvm-commits
llvm-commits at lists.llvm.org
Fri May 8 06:34:40 PDT 2026
https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/196315
>From 8fe742fa021e8bce93288e8b04977f27f668b366 Mon Sep 17 00:00:00 2001
From: Mariusz Sikora <mariusz.sikora at amd.com>
Date: Thu, 7 May 2026 08:21:45 -0400
Subject: [PATCH 1/2] [AMDGPU] Add subtarget features for MTBUF and formatted
MUBUF instructions.
---
llvm/lib/Target/AMDGPU/AMDGPU.td | 33 +++++++++++--------
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 4 ---
.../atomic_optimizations_mul_one.ll | 2 +-
.../AMDGPU/load-local-redundant-copies.ll | 2 +-
llvm/test/CodeGen/AMDGPU/mubuf.ll | 2 +-
llvm/test/CodeGen/AMDGPU/wait.ll | 4 +--
llvm/test/MC/AMDGPU/reg-syntax-extra.s | 2 +-
7 files changed, 26 insertions(+), 23 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 25fc64d178858..888c8b9a5d08a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -483,6 +483,14 @@ defm SBarrierLeaveImm : AMDGPUSubtargetFeature<"s-barrier-leave-imm",
"s_barrier_leave takes an immediate operand"
>;
+defm MTBUFInsts : AMDGPUSubtargetFeature<"mtbuf-insts",
+ "Has memory typed buffer instructions."
+>;
+
+defm FormattedMUBUFInsts : AMDGPUSubtargetFeature<"formatted-mubuf-insts",
+ "Has formatted memory untyped buffer instructions."
+>;
+
defm GFX950Insts : AMDGPUSubtargetFeature<"gfx950-insts",
"Additional instructions for GFX950+",
/*GenPredicate=*/1,
@@ -1377,7 +1385,8 @@ def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
FeatureGDS, FeatureGWS, FeatureDefaultComponentZero,
FeatureAtomicFMinFMaxF32GlobalInsts, FeatureAtomicFMinFMaxF64GlobalInsts,
FeatureVmemWriteVgprInOrder, FeatureCubeInsts, FeatureLerpInst,
- FeatureSadInsts, FeatureCvtPkNormVOP2Insts, FeatureDX10ClampAndIEEEMode
+ FeatureSadInsts, FeatureCvtPkNormVOP2Insts, FeatureDX10ClampAndIEEEMode,
+ FeatureMTBUFInsts, FeatureFormattedMUBUFInsts
]
>;
@@ -1393,7 +1402,8 @@ def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
FeatureAtomicFMinFMaxF32FlatInsts, FeatureAtomicFMinFMaxF64FlatInsts,
FeatureVmemWriteVgprInOrder, FeatureCubeInsts, FeatureLerpInst,
FeatureSadInsts, FeatureQsadInsts, FeatureCvtPkNormVOP2Insts,
- FeatureDX10ClampAndIEEEMode, FeatureInstCacheLineSize64
+ FeatureDX10ClampAndIEEEMode, FeatureInstCacheLineSize64,
+ FeatureMTBUFInsts, FeatureFormattedMUBUFInsts
]
>;
@@ -1413,7 +1423,7 @@ def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
FeatureDefaultComponentZero, FeatureVmemWriteVgprInOrder, FeatureCubeInsts,
FeatureLerpInst, FeatureSadInsts, FeatureQsadInsts,
FeatureCvtPkNormVOP2Insts, FeatureDX10ClampAndIEEEMode,
- FeatureInstCacheLineSize64
+ FeatureInstCacheLineSize64, FeatureMTBUFInsts, FeatureFormattedMUBUFInsts
]
>;
@@ -1436,7 +1446,7 @@ def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
FeatureCubeInsts, FeatureLerpInst, FeatureSadInsts, FeatureQsadInsts,
FeatureCvtNormInsts, FeatureCvtPkNormVOP2Insts,
FeatureCvtPkNormVOP3Insts, FeatureDX10ClampAndIEEEMode,
- FeatureInstCacheLineSize64
+ FeatureInstCacheLineSize64, FeatureMTBUFInsts, FeatureFormattedMUBUFInsts
]
>;
@@ -1464,7 +1474,7 @@ def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
FeatureLerpInst, FeatureSadInsts, FeatureQsadInsts,
FeatureCvtNormInsts, FeatureCvtPkNormVOP2Insts,
FeatureCvtPkNormVOP3Insts, FeatureDX10ClampAndIEEEMode, FeatureFlatOffsetBits12,
- FeatureInstCacheLineSize64
+ FeatureInstCacheLineSize64, FeatureMTBUFInsts, FeatureFormattedMUBUFInsts
]
>;
@@ -1490,7 +1500,7 @@ def FeatureGFX11 : GCNSubtargetFeatureGeneration<"GFX11",
FeatureVmemWriteVgprInOrder, FeatureCubeInsts, FeatureLerpInst,
FeatureSadInsts, FeatureQsadInsts, FeatureCvtNormInsts,
FeatureCvtPkNormVOP2Insts, FeatureCvtPkNormVOP3Insts,
- FeatureInstCacheLineSize128
+ FeatureInstCacheLineSize128, FeatureMTBUFInsts, FeatureFormattedMUBUFInsts
]
>;
@@ -1542,7 +1552,8 @@ def FeatureGFX13 : GCNSubtargetFeatureGeneration<"GFX13",
FeatureIEEEMinimumMaximumInsts, FeatureSALUMinimumMaximumInsts,
FeatureMinimum3Maximum3F32, FeatureMinimum3Maximum3F16,
FeatureAgentScopeFineGrainedRemoteMemoryAtomics, FeatureFlatOffsetBits24,
- FeatureFlatSignedOffset, FeatureInstCacheLineSize128
+ FeatureFlatSignedOffset, FeatureInstCacheLineSize128,
+ FeatureMTBUFInsts, FeatureFormattedMUBUFInsts
]
>;
//===----------------------------------------------------------------------===//
@@ -2030,6 +2041,8 @@ def FeatureISAVersion12 : FeatureSet<
FeatureCvtPkNormVOP3Insts,
FeatureNoF16PseudoScalarTransInlineConstants,
FeatureRealTrue16Insts,
+ FeatureMTBUFInsts,
+ FeatureFormattedMUBUFInsts,
]>;
def FeatureISAVersion12_50_Common : FeatureSet<
@@ -2589,12 +2602,6 @@ def D16PreservesUnusedBits :
def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
-def HasMTBUFInsts : Predicate<"Subtarget->hasMTBUFInsts()">,
- AssemblerPredicate<(all_of (not FeatureGFX1250Insts))>;
-
-def HasFormattedMUBUFInsts : Predicate<"Subtarget->hasFormattedMUBUFInsts()">,
- AssemblerPredicate<(all_of (not FeatureGFX1250Insts))>;
-
def HasExportInsts : Predicate<"Subtarget->hasExportInsts()">,
AssemblerPredicate<(any_of FeatureGFX13Insts, (all_of (not FeatureGFX90AInsts), (not FeatureGFX1250Insts)))>;
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index ec7dd92d6b10e..663d2d43fc29b 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -359,10 +359,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool hasAtomicCSub() const { return HasGFX10_BEncoding; }
- bool hasMTBUFInsts() const { return !hasGFX1250Insts(); }
-
- bool hasFormattedMUBUFInsts() const { return !hasGFX1250Insts(); }
-
bool hasExportInsts() const {
return !hasGFX940Insts() && !hasGFX1250Insts();
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
index 65bc2d73b36b6..eee8a032cf32e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-atomic-optimizer %s | FileCheck -check-prefix=IR %s
-; RUN: llc -global-isel -mtriple=amdgcn-- < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -global-isel -mtriple=amdgcn-- -mattr=+mtbuf-insts,+formatted-mubuf-insts < %s | FileCheck -check-prefix=GCN %s
declare i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.struct.buffer.atomic.sub.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)
diff --git a/llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll b/llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
index 157b4fbe6803d..2fc8a78f74067 100644
--- a/llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn -mattr=+mtbuf-insts,+formatted-mubuf-insts < %s | FileCheck %s
; Test that checks for redundant copies to temporary stack slot produced by
; expandUnalignedLoad.
diff --git a/llvm/test/CodeGen/AMDGPU/mubuf.ll b/llvm/test/CodeGen/AMDGPU/mubuf.ll
index 2f59d75800b26..6e95de5e10906 100644
--- a/llvm/test/CodeGen/AMDGPU/mubuf.ll
+++ b/llvm/test/CodeGen/AMDGPU/mubuf.ll
@@ -1,4 +1,4 @@
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -show-mc-encoding < %s | FileCheck %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mattr=+mtbuf-insts,+formatted-mubuf-insts -show-mc-encoding < %s | FileCheck %s
;;;==========================================================================;;;
;;; MUBUF LOAD TESTS
diff --git a/llvm/test/CodeGen/AMDGPU/wait.ll b/llvm/test/CodeGen/AMDGPU/wait.ll
index 10090e31d5788..07af75b7fa63b 100644
--- a/llvm/test/CodeGen/AMDGPU/wait.ll
+++ b/llvm/test/CodeGen/AMDGPU/wait.ll
@@ -1,6 +1,6 @@
-; RUN: llc -mtriple=amdgcn < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT
+; RUN: llc -mtriple=amdgcn -mattr=+mtbuf-insts,+formatted-mubuf-insts < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT
; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT
-; RUN: llc -mtriple=amdgcn --misched=ilpmax < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX
+; RUN: llc -mtriple=amdgcn --misched=ilpmax -mattr=+mtbuf-insts,+formatted-mubuf-insts < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX
; RUN: llc -mtriple=amdgcn --misched=ilpmax -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX
; The ilpmax scheduler is used for the second test to get the ordering we want for the test.
diff --git a/llvm/test/MC/AMDGPU/reg-syntax-extra.s b/llvm/test/MC/AMDGPU/reg-syntax-extra.s
index 77d74b043f819..5e1ef46a65bbb 100644
--- a/llvm/test/MC/AMDGPU/reg-syntax-extra.s
+++ b/llvm/test/MC/AMDGPU/reg-syntax-extra.s
@@ -1,5 +1,5 @@
// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
-// RUN: not llvm-mc -triple=amdgcn -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
+// RUN: not llvm-mc -triple=amdgcn -mattr=+mtbuf-insts,+formatted-mubuf-insts -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefixes=GCN,VI %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefixes=GCN,GFX10 %s
>From e0f3f0641296597e6bbc50b8711215a420bcf57a Mon Sep 17 00:00:00 2001
From: Mariusz Sikora <mariusz.sikora at amd.com>
Date: Fri, 8 May 2026 09:20:23 -0400
Subject: [PATCH 2/2] Use tahiti subtarget
---
.../atomic_optimizations_mul_one.ll | 38 +++++++-------
.../AMDGPU/load-local-redundant-copies.ll | 52 +++++++++----------
llvm/test/CodeGen/AMDGPU/mubuf.ll | 2 +-
llvm/test/CodeGen/AMDGPU/wait.ll | 4 +-
llvm/test/MC/AMDGPU/reg-syntax-extra.s | 1 -
5 files changed, 48 insertions(+), 49 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
index eee8a032cf32e..4cb566721348f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-atomic-optimizer %s | FileCheck -check-prefix=IR %s
-; RUN: llc -global-isel -mtriple=amdgcn-- -mattr=+mtbuf-insts,+formatted-mubuf-insts < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=tahiti < %s | FileCheck -check-prefix=GCN %s
declare i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.struct.buffer.atomic.sub.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)
@@ -43,9 +43,9 @@ define amdgpu_cs void @atomic_add(<4 x i32> inreg %arg) {
; GCN-NEXT: s_cbranch_execz .LBB0_2
; GCN-NEXT: ; %bb.1:
; GCN-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
-; GCN-NEXT: v_mov_b32_e32 v0, 0
-; GCN-NEXT: v_mov_b32_e32 v1, s4
-; GCN-NEXT: buffer_atomic_add v1, v0, s[0:3], 0 idxen
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: buffer_atomic_add v0, v1, s[0:3], 0 idxen
; GCN-NEXT: .LBB0_2:
; GCN-NEXT: s_endpgm
.entry:
@@ -139,9 +139,9 @@ define amdgpu_cs void @atomic_sub(<4 x i32> inreg %arg) {
; GCN-NEXT: s_cbranch_execz .LBB2_2
; GCN-NEXT: ; %bb.1:
; GCN-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
-; GCN-NEXT: v_mov_b32_e32 v0, 0
-; GCN-NEXT: v_mov_b32_e32 v1, s4
-; GCN-NEXT: buffer_atomic_sub v1, v0, s[0:3], 0 idxen
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: buffer_atomic_sub v0, v1, s[0:3], 0 idxen
; GCN-NEXT: .LBB2_2:
; GCN-NEXT: s_endpgm
.entry:
@@ -237,9 +237,9 @@ define amdgpu_cs void @atomic_xor(<4 x i32> inreg %arg) {
; GCN-NEXT: ; %bb.1:
; GCN-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
; GCN-NEXT: s_and_b32 s4, s4, 1
-; GCN-NEXT: v_mov_b32_e32 v0, 0
-; GCN-NEXT: v_mov_b32_e32 v1, s4
-; GCN-NEXT: buffer_atomic_xor v1, v0, s[0:3], 0 idxen
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: buffer_atomic_xor v0, v1, s[0:3], 0 idxen
; GCN-NEXT: .LBB4_2:
; GCN-NEXT: s_endpgm
.entry:
@@ -337,9 +337,9 @@ define amdgpu_cs void @atomic_ptr_add(ptr addrspace(8) inreg %arg) {
; GCN-NEXT: s_cbranch_execz .LBB6_2
; GCN-NEXT: ; %bb.1:
; GCN-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
-; GCN-NEXT: v_mov_b32_e32 v0, 0
-; GCN-NEXT: v_mov_b32_e32 v1, s4
-; GCN-NEXT: buffer_atomic_add v1, v0, s[0:3], 0 idxen
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: buffer_atomic_add v0, v1, s[0:3], 0 idxen
; GCN-NEXT: .LBB6_2:
; GCN-NEXT: s_endpgm
.entry:
@@ -437,9 +437,9 @@ define amdgpu_cs void @atomic_ptr_sub(ptr addrspace(8) inreg %arg) {
; GCN-NEXT: s_cbranch_execz .LBB8_2
; GCN-NEXT: ; %bb.1:
; GCN-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
-; GCN-NEXT: v_mov_b32_e32 v0, 0
-; GCN-NEXT: v_mov_b32_e32 v1, s4
-; GCN-NEXT: buffer_atomic_sub v1, v0, s[0:3], 0 idxen
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: buffer_atomic_sub v0, v1, s[0:3], 0 idxen
; GCN-NEXT: .LBB8_2:
; GCN-NEXT: s_endpgm
.entry:
@@ -539,9 +539,9 @@ define amdgpu_cs void @atomic_ptr_xor(ptr addrspace(8) inreg %arg) {
; GCN-NEXT: ; %bb.1:
; GCN-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
; GCN-NEXT: s_and_b32 s4, s4, 1
-; GCN-NEXT: v_mov_b32_e32 v0, 0
-; GCN-NEXT: v_mov_b32_e32 v1, s4
-; GCN-NEXT: buffer_atomic_xor v1, v0, s[0:3], 0 idxen
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: buffer_atomic_xor v0, v1, s[0:3], 0 idxen
; GCN-NEXT: .LBB10_2:
; GCN-NEXT: s_endpgm
.entry:
diff --git a/llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll b/llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
index 2fc8a78f74067..eb3386b64e72b 100644
--- a/llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mattr=+mtbuf-insts,+formatted-mubuf-insts < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck %s
; Test that checks for redundant copies to temporary stack slot produced by
; expandUnalignedLoad.
@@ -9,15 +9,15 @@ define amdgpu_vs void @test(ptr addrspace(8) inreg %arg1, ptr addrspace(3) %arg2
; CHECK: ; %bb.0:
; CHECK-NEXT: v_add_i32_e32 v1, vcc, 12, v0
; CHECK-NEXT: v_add_i32_e32 v2, vcc, 8, v0
-; CHECK-NEXT: v_add_i32_e32 v4, vcc, 4, v0
; CHECK-NEXT: s_mov_b32 m0, -1
+; CHECK-NEXT: v_add_i32_e32 v4, vcc, 4, v0
; CHECK-NEXT: ds_read_b32 v3, v1
; CHECK-NEXT: ds_read_b32 v2, v2
; CHECK-NEXT: ds_read_b32 v1, v4
; CHECK-NEXT: ds_read_b32 v0, v0
+; CHECK-NEXT: v_mov_b32_e32 v4, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: exp mrt0, off, off, off, off
-; CHECK-NEXT: v_mov_b32_e32 v4, 0
; CHECK-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_FLOAT] idxen
; CHECK-NEXT: s_endpgm
call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float poison, float poison, float poison, float poison, i1 false, i1 false)
@@ -36,8 +36,8 @@ define amdgpu_vs void @test_2(ptr addrspace(8) inreg %arg1, i32 %arg2, i32 inreg
; CHECK-NEXT: v_add_i32_e32 v6, vcc, 24, v1
; CHECK-NEXT: v_add_i32_e32 v7, vcc, 12, v1
; CHECK-NEXT: v_add_i32_e32 v8, vcc, 8, v1
-; CHECK-NEXT: v_add_i32_e32 v10, vcc, 4, v1
; CHECK-NEXT: s_mov_b32 m0, -1
+; CHECK-NEXT: v_add_i32_e32 v10, vcc, 4, v1
; CHECK-NEXT: ds_read_b32 v2, v2
; CHECK-NEXT: ds_read_b32 v5, v4
; CHECK-NEXT: ds_read_b32 v4, v6
@@ -62,43 +62,43 @@ define amdgpu_vs void @test_2(ptr addrspace(8) inreg %arg1, i32 %arg2, i32 inreg
define amdgpu_vs void @test_3(i32 inreg %arg1, i32 inreg %arg2, ptr addrspace(8) inreg %arg3, i32 %arg4, ptr addrspace(3) %arg5, ptr addrspace(3) %arg6) {
; CHECK-LABEL: test_3:
; CHECK: ; %bb.0:
-; CHECK-NEXT: s_mov_b32 s7, s5
-; CHECK-NEXT: s_mov_b32 s6, s4
-; CHECK-NEXT: s_mov_b32 s5, s3
-; CHECK-NEXT: s_mov_b32 s4, s2
; CHECK-NEXT: v_add_i32_e32 v0, vcc, 12, v1
; CHECK-NEXT: v_add_i32_e32 v3, vcc, 8, v1
; CHECK-NEXT: v_add_i32_e32 v4, vcc, 4, v1
; CHECK-NEXT: v_add_i32_e32 v7, vcc, 20, v1
-; CHECK-NEXT: v_add_i32_e32 v9, vcc, 16, v1
-; CHECK-NEXT: v_mov_b32_e32 v10, s0
-; CHECK-NEXT: v_add_i32_e32 v11, vcc, 12, v2
-; CHECK-NEXT: v_add_i32_e32 v12, vcc, 8, v2
; CHECK-NEXT: s_mov_b32 m0, -1
+; CHECK-NEXT: v_add_i32_e32 v9, vcc, 16, v1
; CHECK-NEXT: ds_read_b32 v6, v0
; CHECK-NEXT: ds_read_b32 v5, v3
; CHECK-NEXT: ds_read_b32 v4, v4
; CHECK-NEXT: ds_read_b32 v8, v7
; CHECK-NEXT: ds_read_b32 v7, v9
; CHECK-NEXT: ds_read_b32 v3, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, 4, v2
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, 20, v2
-; CHECK-NEXT: v_add_i32_e32 v9, vcc, 16, v2
+; CHECK-NEXT: s_mov_b32 s7, s5
+; CHECK-NEXT: s_mov_b32 s6, s4
+; CHECK-NEXT: s_mov_b32 s5, s3
+; CHECK-NEXT: s_mov_b32 s4, s2
+; CHECK-NEXT: v_mov_b32_e32 v9, s0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: tbuffer_store_format_xyzw v[3:6], v10, s[4:7], s1 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:264 glc slc
-; CHECK-NEXT: tbuffer_store_format_xy v[7:8], v10, s[4:7], s1 format:[BUF_DATA_FORMAT_INVALID,BUF_NUM_FORMAT_UINT] idxen offset:280 glc slc
+; CHECK-NEXT: tbuffer_store_format_xyzw v[3:6], v9, s[4:7], s1 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:264 glc slc
+; CHECK-NEXT: tbuffer_store_format_xy v[7:8], v9, s[4:7], s1 format:[BUF_DATA_FORMAT_INVALID,BUF_NUM_FORMAT_UINT] idxen offset:280 glc slc
+; CHECK-NEXT: v_add_i32_e32 v0, vcc, 12, v2
+; CHECK-NEXT: v_add_i32_e32 v1, vcc, 8, v2
; CHECK-NEXT: s_waitcnt expcnt(1)
-; CHECK-NEXT: ds_read_b32 v5, v11
-; CHECK-NEXT: ds_read_b32 v4, v12
-; CHECK-NEXT: ds_read_b32 v3, v0
-; CHECK-NEXT: ds_read_b32 v1, v1
-; CHECK-NEXT: ds_read_b32 v0, v9
+; CHECK-NEXT: v_add_i32_e32 v3, vcc, 4, v2
+; CHECK-NEXT: v_add_i32_e32 v6, vcc, 20, v2
+; CHECK-NEXT: s_waitcnt expcnt(0)
+; CHECK-NEXT: v_add_i32_e32 v7, vcc, 16, v2
+; CHECK-NEXT: ds_read_b32 v5, v0
+; CHECK-NEXT: ds_read_b32 v4, v1
+; CHECK-NEXT: ds_read_b32 v3, v3
+; CHECK-NEXT: ds_read_b32 v1, v6
+; CHECK-NEXT: ds_read_b32 v0, v7
; CHECK-NEXT: ds_read_b32 v2, v2
-; CHECK-NEXT: s_waitcnt lgkmcnt(1)
-; CHECK-NEXT: exp mrt0, off, off, off, off
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: tbuffer_store_format_xyzw v[2:5], v10, s[4:7], s1 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:240 glc slc
-; CHECK-NEXT: tbuffer_store_format_xy v[0:1], v10, s[4:7], s1 format:[BUF_DATA_FORMAT_INVALID,BUF_NUM_FORMAT_UINT] idxen offset:256 glc slc
+; CHECK-NEXT: tbuffer_store_format_xyzw v[2:5], v9, s[4:7], s1 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:240 glc slc
+; CHECK-NEXT: tbuffer_store_format_xy v[0:1], v9, s[4:7], s1 format:[BUF_DATA_FORMAT_INVALID,BUF_NUM_FORMAT_UINT] idxen offset:256 glc slc
+; CHECK-NEXT: exp mrt0, off, off, off, off
; CHECK-NEXT: s_endpgm
%load1 = load <6 x float>, ptr addrspace(3) %arg5, align 4
%vec11 = shufflevector <6 x float> %load1, <6 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
diff --git a/llvm/test/CodeGen/AMDGPU/mubuf.ll b/llvm/test/CodeGen/AMDGPU/mubuf.ll
index 6e95de5e10906..438b63b559de9 100644
--- a/llvm/test/CodeGen/AMDGPU/mubuf.ll
+++ b/llvm/test/CodeGen/AMDGPU/mubuf.ll
@@ -1,4 +1,4 @@
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mattr=+mtbuf-insts,+formatted-mubuf-insts -show-mc-encoding < %s | FileCheck %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -show-mc-encoding < %s | FileCheck %s
;;;==========================================================================;;;
;;; MUBUF LOAD TESTS
diff --git a/llvm/test/CodeGen/AMDGPU/wait.ll b/llvm/test/CodeGen/AMDGPU/wait.ll
index 07af75b7fa63b..04f6df8042a2c 100644
--- a/llvm/test/CodeGen/AMDGPU/wait.ll
+++ b/llvm/test/CodeGen/AMDGPU/wait.ll
@@ -1,6 +1,6 @@
-; RUN: llc -mtriple=amdgcn -mattr=+mtbuf-insts,+formatted-mubuf-insts < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT
; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT
-; RUN: llc -mtriple=amdgcn --misched=ilpmax -mattr=+mtbuf-insts,+formatted-mubuf-insts < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX
+; RUN: llc -mtriple=amdgcn --misched=ilpmax -mcpu=tahiti < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX
; RUN: llc -mtriple=amdgcn --misched=ilpmax -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX
; The ilpmax scheduler is used for the second test to get the ordering we want for the test.
diff --git a/llvm/test/MC/AMDGPU/reg-syntax-extra.s b/llvm/test/MC/AMDGPU/reg-syntax-extra.s
index 5e1ef46a65bbb..dc77f4d89fa01 100644
--- a/llvm/test/MC/AMDGPU/reg-syntax-extra.s
+++ b/llvm/test/MC/AMDGPU/reg-syntax-extra.s
@@ -1,5 +1,4 @@
// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
-// RUN: not llvm-mc -triple=amdgcn -mattr=+mtbuf-insts,+formatted-mubuf-insts -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefixes=GCN,VI %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefixes=GCN,GFX10 %s
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